From 97bc7f0dcc398dd45f5fe2c979aa74a7999d6681 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Tue, 20 Apr 2021 17:05:04 -0500 Subject: Add "_arm" suffix to Makalu ELP CPU lib ELP processors can sometimes have different MIDR values or features so we are adding the "_arm" suffix to differentiate the reference implementation from other future versions. Signed-off-by: John Powell Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20 --- lib/cpus/aarch64/cortex_makalu_elp.S | 77 -------------------------------- lib/cpus/aarch64/cortex_makalu_elp_arm.S | 77 ++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 77 deletions(-) delete mode 100644 lib/cpus/aarch64/cortex_makalu_elp.S create mode 100644 lib/cpus/aarch64/cortex_makalu_elp_arm.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_makalu_elp.S b/lib/cpus/aarch64/cortex_makalu_elp.S deleted file mode 100644 index e3a3e9de8..000000000 --- a/lib/cpus/aarch64/cortex_makalu_elp.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_makalu_elp_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_makalu_elp_core_pwr_dwn - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Makalu ELP. Must follow AAPCS. - */ -func cortex_makalu_elp_errata_report - ret -endfunc cortex_makalu_elp_errata_report -#endif - -func cortex_makalu_elp_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - isb - ret -endfunc cortex_makalu_elp_reset_func - - /* --------------------------------------------- - * This function provides Cortex Makalu ELP- - * specific register information for crash - * reporting. It needs to return with x6 - * pointing to a list of register names in ascii - * and x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_makalu_elp_regs, "aS" -cortex_makalu_elp_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_makalu_elp_cpu_reg_dump - adr x6, cortex_makalu_elp_regs - mrs x8, CORTEX_MAKALU_ELP_CPUECTLR_EL1 - ret -endfunc cortex_makalu_elp_cpu_reg_dump - -declare_cpu_ops cortex_makalu_elp, CORTEX_MAKALU_ELP_MIDR, \ - cortex_makalu_elp_reset_func, \ - cortex_makalu_elp_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_makalu_elp_arm.S b/lib/cpus/aarch64/cortex_makalu_elp_arm.S new file mode 100644 index 000000000..fbbf20501 --- /dev/null +++ b/lib/cpus/aarch64/cortex_makalu_elp_arm.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_makalu_elp_arm_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_makalu_elp_arm_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Makalu ELP. Must follow AAPCS. + */ +func cortex_makalu_elp_arm_errata_report + ret +endfunc cortex_makalu_elp_arm_errata_report +#endif + +func cortex_makalu_elp_arm_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_makalu_elp_arm_reset_func + + /* --------------------------------------------- + * This function provides Cortex Makalu ELP- + * specific register information for crash + * reporting. It needs to return with x6 + * pointing to a list of register names in ascii + * and x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_makalu_elp_arm_regs, "aS" +cortex_makalu_elp_arm_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_makalu_elp_arm_cpu_reg_dump + adr x6, cortex_makalu_elp_arm_regs + mrs x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 + ret +endfunc cortex_makalu_elp_arm_cpu_reg_dump + +declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \ + cortex_makalu_elp_arm_reset_func, \ + cortex_makalu_elp_arm_core_pwr_dwn -- cgit v1.2.3