From 0b1838a97083a347e16d39d20f9349f0ea410062 Mon Sep 17 00:00:00 2001 From: Heyi Guo Date: Wed, 22 Apr 2020 20:00:00 +0800 Subject: lib/extensions/ras: fix bug of binary search In ras_interrupt_handler(), binary search end was set to the size of the ras_interrupt_mappings array, which would cause out of bound access when the input intr_raw is larger than all the elements in ras_interrupt_mappings. Signed-off-by: Heyi Guo Change-Id: Id2cff73177134b09d4d8beb596c3429b98ec5066 --- lib/extensions/ras/ras_common.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/extensions/ras/ras_common.c b/lib/extensions/ras/ras_common.c index 36f9a95b6..622879efa 100644 --- a/lib/extensions/ras/ras_common.c +++ b/lib/extensions/ras/ras_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -139,7 +139,7 @@ static int ras_interrupt_handler(uint32_t intr_raw, uint32_t flags, assert(ras_interrupt_mappings.num_intrs > 0UL); start = 0; - end = (int) ras_interrupt_mappings.num_intrs; + end = (int)ras_interrupt_mappings.num_intrs - 1; while (start <= end) { mid = ((end + start) / 2); if (intr_raw == ras_inrs[mid].intr_number) { -- cgit v1.2.3 From e3b9cc1262f1fba4906a3e75319c36e01235c3a3 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 23 Feb 2021 14:50:44 +0100 Subject: lib: cpus: aarch32: sanity check pointers before use This is the AARCH32 update of patch [1]. [1] 601e3ed209eb ("lib: cpus: sanity check pointers before use") Signed-off-by: Yann Gautier Change-Id: I43dbe00a5802a7e1c6f877e22d1c66ec8275c6fa --- lib/cpus/aarch32/cpu_helpers.S | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S index 9b5d787ed..6ed800cbc 100644 --- a/lib/cpus/aarch32/cpu_helpers.S +++ b/lib/cpus/aarch32/cpu_helpers.S @@ -78,6 +78,10 @@ func prepare_cpu_pwr_dwn mov r1, #CPU_PWR_DWN_OPS add r1, r1, r2, lsl #2 ldr r1, [r0, r1] +#if ENABLE_ASSERTIONS + cmp r1, #0 + ASM_ASSERT(ne) +#endif bx r1 endfunc prepare_cpu_pwr_dwn @@ -146,6 +150,10 @@ func get_cpu_ops_ptr /* Subtract the increment and offset to get the cpu-ops pointer */ sub r0, r4, #(CPU_OPS_SIZE + CPU_MIDR) +#if ENABLE_ASSERTIONS + cmp r0, #0 + ASM_ASSERT(ne) +#endif error_exit: bx lr endfunc get_cpu_ops_ptr @@ -224,7 +232,15 @@ func print_errata_status * function. If it's non-NULL, jump to the function in turn. */ bl _cpu_data +#if ENABLE_ASSERTIONS + cmp r0, #0 + ASM_ASSERT(ne) +#endif ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR] +#if ENABLE_ASSERTIONS + cmp r1, #0 + ASM_ASSERT(ne) +#endif ldr r0, [r1, #CPU_ERRATA_FUNC] cmp r0, #0 beq 1f -- cgit v1.2.3 From 005415a39a411c2c92da48409441304173884d08 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 24 Sep 2020 15:50:40 +0100 Subject: libc: memset: Fix MISRA issues MISRA complained about "0"s not being followed by an "U" (please note my protest about this!) and about values not being explicitly compared to 0 (fair enough). Also use explicit pointer types. Fix those issues to make the CI happy. Change-Id: I4d11e49c14f16223a71c78b0fc3e68ba9a1382d3 Signed-off-by: Andre Przywara --- lib/libc/memset.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) (limited to 'lib') diff --git a/lib/libc/memset.c b/lib/libc/memset.c index f9dd4c5db..17f798cb9 100644 --- a/lib/libc/memset.c +++ b/lib/libc/memset.c @@ -10,19 +10,20 @@ void *memset(void *dst, int val, size_t count) { - char *ptr = dst; + uint8_t *ptr = dst; uint64_t *ptr64; uint64_t fill = (unsigned char)val; /* Simplify code below by making sure we write at least one byte. */ - if (count == 0) { + if (count == 0U) { return dst; } /* Handle the first part, until the pointer becomes 64-bit aligned. */ - while (((uintptr_t)ptr & 7)) { - *ptr++ = val; - if (--count == 0) { + while (((uintptr_t)ptr & 7U) != 0U) { + *ptr = (uint8_t)val; + ptr++; + if (--count == 0U) { return dst; } } @@ -33,15 +34,17 @@ void *memset(void *dst, int val, size_t count) fill |= fill << 32; /* Use 64-bit writes for as long as possible. */ - ptr64 = (void *)ptr; - for (; count >= 8; count -= 8) { - *ptr64++ = fill; + ptr64 = (uint64_t *)ptr; + for (; count >= 8U; count -= 8) { + *ptr64 = fill; + ptr64++; } /* Handle the remaining part byte-per-byte. */ - ptr = (void *)ptr64; - while (count--) { - *ptr++ = val; + ptr = (uint8_t *)ptr64; + while (count-- > 0U) { + *ptr = (uint8_t)val; + ptr++; } return dst; -- cgit v1.2.3 From 873d4241e324cf619e68880aaa9f890296cdba8b Mon Sep 17 00:00:00 2001 From: johpow01 Date: Fri, 2 Oct 2020 13:41:11 -0500 Subject: Enable v8.6 AMU enhancements (FEAT_AMUv1p1) ARMv8.6 adds virtual offset registers to support virtualization of the event counters in EL1 and EL0. This patch enables support for this feature in EL3 firmware. Signed-off-by: John Powell Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217 --- lib/el3_runtime/aarch64/context_mgmt.c | 12 ++- lib/extensions/amu/aarch32/amu.c | 53 ++++++--- lib/extensions/amu/aarch32/amu_helpers.S | 74 ++++++------- lib/extensions/amu/aarch64/amu.c | 180 +++++++++++++++++++++++++++---- lib/extensions/amu/aarch64/amu_helpers.S | 174 +++++++++++++++++++++++++++++- 5 files changed, 420 insertions(+), 73 deletions(-) (limited to 'lib') diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 72d463b71..e0e429849 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -216,6 +216,16 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) scr_el3 |= SCR_EEL2_BIT; } + /* + * FEAT_AMUv1p1 virtual offset registers are only accessible from EL3 + * and EL2, when clear, this bit traps accesses from EL2 so we set it + * to 1 when EL2 is present. + */ + if (is_armv8_6_feat_amuv1p1_present() && + (el_implemented(2) != EL_IMPL_NONE)) { + scr_el3 |= SCR_AMVOFFEN_BIT; + } + /* * Initialise SCTLR_EL1 to the reset value corresponding to the target * execution state setting all fields rather than relying of the hw. diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c index 0f75f0791..ed56dddc9 100644 --- a/lib/extensions/amu/aarch32/amu.c +++ b/lib/extensions/amu/aarch32/amu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,13 +18,17 @@ static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT]; -/* Check if AMUv1 for Armv8.4 or 8.6 is implemented */ -bool amu_supported(void) +/* + * Get AMU version value from pfr0. + * Return values + * ID_PFR0_AMU_V1: FEAT_AMUv1 supported (introduced in ARM v8.4) + * ID_PFR0_AMU_V1P1: FEAT_AMUv1p1 supported (introduced in ARM v8.6) + * ID_PFR0_AMU_NOT_SUPPORTED: not supported + */ +unsigned int amu_get_version(void) { - uint32_t features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT; - - features &= ID_PFR0_AMU_MASK; - return ((features == 1U) || (features == 2U)); + return (unsigned int)(read_id_pfr0() >> ID_PFR0_AMU_SHIFT) & + ID_PFR0_AMU_MASK; } #if AMU_GROUP1_NR_COUNTERS @@ -43,7 +47,7 @@ bool amu_group1_supported(void) */ void amu_enable(bool el2_unused) { - if (!amu_supported()) { + if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) { return; } @@ -87,12 +91,31 @@ void amu_enable(bool el2_unused) /* Enable group 1 counters */ write_amcntenset1(AMU_GROUP1_COUNTERS_MASK); #endif + + /* Initialize FEAT_AMUv1p1 features if present. */ + if (amu_get_version() < ID_PFR0_AMU_V1P1) { + return; + } + +#if AMU_RESTRICT_COUNTERS + /* + * FEAT_AMUv1p1 adds a register field to restrict access to group 1 + * counters at all but the highest implemented EL. This is controlled + * with the AMU_RESTRICT_COUNTERS compile time flag, when set, system + * register reads at lower ELs return zero. Reads from the memory + * mapped view are unaffected. + */ + VERBOSE("AMU group 1 counter access restricted.\n"); + write_amcr(read_amcr() | AMCR_CG1RZ_BIT); +#else + write_amcr(read_amcr() & ~AMCR_CG1RZ_BIT); +#endif } /* Read the group 0 counter identified by the given `idx`. */ uint64_t amu_group0_cnt_read(unsigned int idx) { - assert(amu_supported()); + assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED); assert(idx < AMU_GROUP0_NR_COUNTERS); return amu_group0_cnt_read_internal(idx); @@ -101,7 +124,7 @@ uint64_t amu_group0_cnt_read(unsigned int idx) /* Write the group 0 counter identified by the given `idx` with `val` */ void amu_group0_cnt_write(unsigned int idx, uint64_t val) { - assert(amu_supported()); + assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED); assert(idx < AMU_GROUP0_NR_COUNTERS); amu_group0_cnt_write_internal(idx, val); @@ -112,7 +135,7 @@ void amu_group0_cnt_write(unsigned int idx, uint64_t val) /* Read the group 1 counter identified by the given `idx` */ uint64_t amu_group1_cnt_read(unsigned int idx) { - assert(amu_supported()); + assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED); assert(amu_group1_supported()); assert(idx < AMU_GROUP1_NR_COUNTERS); @@ -122,7 +145,7 @@ uint64_t amu_group1_cnt_read(unsigned int idx) /* Write the group 1 counter identified by the given `idx` with `val` */ void amu_group1_cnt_write(unsigned int idx, uint64_t val) { - assert(amu_supported()); + assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED); assert(amu_group1_supported()); assert(idx < AMU_GROUP1_NR_COUNTERS); @@ -136,7 +159,7 @@ void amu_group1_cnt_write(unsigned int idx, uint64_t val) */ void amu_group1_set_evtype(unsigned int idx, unsigned int val) { - assert(amu_supported()); + assert(amu_get_version() != ID_PFR0_AMU_NOT_SUPPORTED); assert(amu_group1_supported()); assert(idx < AMU_GROUP1_NR_COUNTERS); @@ -150,7 +173,7 @@ static void *amu_context_save(const void *arg) struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; unsigned int i; - if (!amu_supported()) { + if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) { return (void *)-1; } @@ -197,7 +220,7 @@ static void *amu_context_restore(const void *arg) struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; unsigned int i; - if (!amu_supported()) { + if (amu_get_version() == ID_PFR0_AMU_NOT_SUPPORTED) { return (void *)-1; } diff --git a/lib/extensions/amu/aarch32/amu_helpers.S b/lib/extensions/amu/aarch32/amu_helpers.S index effb8e50f..d387341f7 100644 --- a/lib/extensions/amu/aarch32/amu_helpers.S +++ b/lib/extensions/amu/aarch32/amu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -75,13 +75,13 @@ func amu_group0_cnt_write_internal 1: stcopr16 r2, r3, AMEVCNTR00 /* index 0 */ - bx lr + bx lr stcopr16 r2, r3, AMEVCNTR01 /* index 1 */ - bx lr + bx lr stcopr16 r2, r3, AMEVCNTR02 /* index 2 */ - bx lr + bx lr stcopr16 r2, r3, AMEVCNTR03 /* index 3 */ - bx lr + bx lr endfunc amu_group0_cnt_write_internal /* @@ -169,37 +169,37 @@ func amu_group1_cnt_write_internal bx r1 1: - stcopr16 r2, r3, AMEVCNTR10 /* index 0 */ + stcopr16 r2, r3, AMEVCNTR10 /* index 0 */ bx lr - stcopr16 r2, r3, AMEVCNTR11 /* index 1 */ + stcopr16 r2, r3, AMEVCNTR11 /* index 1 */ bx lr - stcopr16 r2, r3, AMEVCNTR12 /* index 2 */ + stcopr16 r2, r3, AMEVCNTR12 /* index 2 */ bx lr - stcopr16 r2, r3, AMEVCNTR13 /* index 3 */ + stcopr16 r2, r3, AMEVCNTR13 /* index 3 */ bx lr - stcopr16 r2, r3, AMEVCNTR14 /* index 4 */ + stcopr16 r2, r3, AMEVCNTR14 /* index 4 */ bx lr - stcopr16 r2, r3, AMEVCNTR15 /* index 5 */ + stcopr16 r2, r3, AMEVCNTR15 /* index 5 */ bx lr - stcopr16 r2, r3, AMEVCNTR16 /* index 6 */ + stcopr16 r2, r3, AMEVCNTR16 /* index 6 */ bx lr - stcopr16 r2, r3, AMEVCNTR17 /* index 7 */ + stcopr16 r2, r3, AMEVCNTR17 /* index 7 */ bx lr - stcopr16 r2, r3, AMEVCNTR18 /* index 8 */ + stcopr16 r2, r3, AMEVCNTR18 /* index 8 */ bx lr - stcopr16 r2, r3, AMEVCNTR19 /* index 9 */ + stcopr16 r2, r3, AMEVCNTR19 /* index 9 */ bx lr - stcopr16 r2, r3, AMEVCNTR1A /* index 10 */ + stcopr16 r2, r3, AMEVCNTR1A /* index 10 */ bx lr - stcopr16 r2, r3, AMEVCNTR1B /* index 11 */ + stcopr16 r2, r3, AMEVCNTR1B /* index 11 */ bx lr - stcopr16 r2, r3, AMEVCNTR1C /* index 12 */ + stcopr16 r2, r3, AMEVCNTR1C /* index 12 */ bx lr - stcopr16 r2, r3, AMEVCNTR1D /* index 13 */ + stcopr16 r2, r3, AMEVCNTR1D /* index 13 */ bx lr - stcopr16 r2, r3, AMEVCNTR1E /* index 14 */ + stcopr16 r2, r3, AMEVCNTR1E /* index 14 */ bx lr - stcopr16 r2, r3, AMEVCNTR1F /* index 15 */ + stcopr16 r2, r3, AMEVCNTR1F /* index 15 */ bx lr endfunc amu_group1_cnt_write_internal @@ -234,36 +234,36 @@ func amu_group1_set_evtype_internal bx r2 1: - stcopr r1, AMEVTYPER10 /* index 0 */ + stcopr r1, AMEVTYPER10 /* index 0 */ bx lr - stcopr r1, AMEVTYPER11 /* index 1 */ + stcopr r1, AMEVTYPER11 /* index 1 */ bx lr - stcopr r1, AMEVTYPER12 /* index 2 */ + stcopr r1, AMEVTYPER12 /* index 2 */ bx lr - stcopr r1, AMEVTYPER13 /* index 3 */ + stcopr r1, AMEVTYPER13 /* index 3 */ bx lr - stcopr r1, AMEVTYPER14 /* index 4 */ + stcopr r1, AMEVTYPER14 /* index 4 */ bx lr - stcopr r1, AMEVTYPER15 /* index 5 */ + stcopr r1, AMEVTYPER15 /* index 5 */ bx lr - stcopr r1, AMEVTYPER16 /* index 6 */ + stcopr r1, AMEVTYPER16 /* index 6 */ bx lr - stcopr r1, AMEVTYPER17 /* index 7 */ + stcopr r1, AMEVTYPER17 /* index 7 */ bx lr - stcopr r1, AMEVTYPER18 /* index 8 */ + stcopr r1, AMEVTYPER18 /* index 8 */ bx lr - stcopr r1, AMEVTYPER19 /* index 9 */ + stcopr r1, AMEVTYPER19 /* index 9 */ bx lr - stcopr r1, AMEVTYPER1A /* index 10 */ + stcopr r1, AMEVTYPER1A /* index 10 */ bx lr - stcopr r1, AMEVTYPER1B /* index 11 */ + stcopr r1, AMEVTYPER1B /* index 11 */ bx lr - stcopr r1, AMEVTYPER1C /* index 12 */ + stcopr r1, AMEVTYPER1C /* index 12 */ bx lr - stcopr r1, AMEVTYPER1D /* index 13 */ + stcopr r1, AMEVTYPER1D /* index 13 */ bx lr - stcopr r1, AMEVTYPER1E /* index 14 */ + stcopr r1, AMEVTYPER1E /* index 14 */ bx lr - stcopr r1, AMEVTYPER1F /* index 15 */ + stcopr r1, AMEVTYPER1F /* index 15 */ bx lr endfunc amu_group1_set_evtype_internal diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c index 499736345..24c3737b7 100644 --- a/lib/extensions/amu/aarch64/amu.c +++ b/lib/extensions/amu/aarch64/amu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include #include +#include #include #include @@ -18,13 +19,17 @@ static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT]; -/* Check if AMUv1 for Armv8.4 or 8.6 is implemented */ -bool amu_supported(void) +/* + * Get AMU version value from aa64pfr0. + * Return values + * ID_AA64PFR0_AMU_V1: FEAT_AMUv1 supported (introduced in ARM v8.4) + * ID_AA64PFR0_AMU_V1P1: FEAT_AMUv1p1 supported (introduced in ARM v8.6) + * ID_AA64PFR0_AMU_NOT_SUPPORTED: not supported + */ +unsigned int amu_get_version(void) { - uint64_t features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT; - - features &= ID_AA64PFR0_AMU_MASK; - return ((features == 1U) || (features == 2U)); + return (unsigned int)(read_id_aa64pfr0_el1() >> ID_AA64PFR0_AMU_SHIFT) & + ID_AA64PFR0_AMU_MASK; } #if AMU_GROUP1_NR_COUNTERS @@ -44,8 +49,9 @@ bool amu_group1_supported(void) void amu_enable(bool el2_unused) { uint64_t v; + unsigned int amu_version = amu_get_version(); - if (!amu_supported()) { + if (amu_version == ID_AA64PFR0_AMU_NOT_SUPPORTED) { return; } @@ -96,12 +102,36 @@ void amu_enable(bool el2_unused) /* Enable group 1 counters */ write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK); #endif + + /* Initialize FEAT_AMUv1p1 features if present. */ + if (amu_version < ID_AA64PFR0_AMU_V1P1) { + return; + } + + if (el2_unused) { + /* Make sure virtual offsets are disabled if EL2 not used. */ + write_hcr_el2(read_hcr_el2() & ~HCR_AMVOFFEN_BIT); + } + +#if AMU_RESTRICT_COUNTERS + /* + * FEAT_AMUv1p1 adds a register field to restrict access to group 1 + * counters at all but the highest implemented EL. This is controlled + * with the AMU_RESTRICT_COUNTERS compile time flag, when set, system + * register reads at lower ELs return zero. Reads from the memory + * mapped view are unaffected. + */ + VERBOSE("AMU group 1 counter access restricted.\n"); + write_amcr_el0(read_amcr_el0() | AMCR_CG1RZ_BIT); +#else + write_amcr_el0(read_amcr_el0() & ~AMCR_CG1RZ_BIT); +#endif } /* Read the group 0 counter identified by the given `idx`. */ uint64_t amu_group0_cnt_read(unsigned int idx) { - assert(amu_supported()); + assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED); assert(idx < AMU_GROUP0_NR_COUNTERS); return amu_group0_cnt_read_internal(idx); @@ -110,18 +140,49 @@ uint64_t amu_group0_cnt_read(unsigned int idx) /* Write the group 0 counter identified by the given `idx` with `val` */ void amu_group0_cnt_write(unsigned int idx, uint64_t val) { - assert(amu_supported()); + assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED); assert(idx < AMU_GROUP0_NR_COUNTERS); amu_group0_cnt_write_internal(idx, val); isb(); } +/* + * Read the group 0 offset register for a given index. Index must be 0, 2, + * or 3, the register for 1 does not exist. + * + * Using this function requires FEAT_AMUv1p1 support. + */ +uint64_t amu_group0_voffset_read(unsigned int idx) +{ + assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1); + assert(idx < AMU_GROUP0_NR_COUNTERS); + assert(idx != 1U); + + return amu_group0_voffset_read_internal(idx); +} + +/* + * Write the group 0 offset register for a given index. Index must be 0, 2, or + * 3, the register for 1 does not exist. + * + * Using this function requires FEAT_AMUv1p1 support. + */ +void amu_group0_voffset_write(unsigned int idx, uint64_t val) +{ + assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1); + assert(idx < AMU_GROUP0_NR_COUNTERS); + assert(idx != 1U); + + amu_group0_voffset_write_internal(idx, val); + isb(); +} + #if AMU_GROUP1_NR_COUNTERS /* Read the group 1 counter identified by the given `idx` */ -uint64_t amu_group1_cnt_read(unsigned int idx) +uint64_t amu_group1_cnt_read(unsigned int idx) { - assert(amu_supported()); + assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED); assert(amu_group1_supported()); assert(idx < AMU_GROUP1_NR_COUNTERS); @@ -129,9 +190,9 @@ uint64_t amu_group1_cnt_read(unsigned int idx) } /* Write the group 1 counter identified by the given `idx` with `val` */ -void amu_group1_cnt_write(unsigned int idx, uint64_t val) +void amu_group1_cnt_write(unsigned int idx, uint64_t val) { - assert(amu_supported()); + assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED); assert(amu_group1_supported()); assert(idx < AMU_GROUP1_NR_COUNTERS); @@ -139,13 +200,46 @@ void amu_group1_cnt_write(unsigned int idx, uint64_t val) isb(); } +/* + * Read the group 1 offset register for a given index. + * + * Using this function requires FEAT_AMUv1p1 support. + */ +uint64_t amu_group1_voffset_read(unsigned int idx) +{ + assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1); + assert(amu_group1_supported()); + assert(idx < AMU_GROUP1_NR_COUNTERS); + assert(((read_amcg1idr_el0() >> AMCG1IDR_VOFF_SHIFT) & + (1ULL << idx)) != 0ULL); + + return amu_group1_voffset_read_internal(idx); +} + +/* + * Write the group 1 offset register for a given index. + * + * Using this function requires FEAT_AMUv1p1 support. + */ +void amu_group1_voffset_write(unsigned int idx, uint64_t val) +{ + assert(amu_get_version() >= ID_AA64PFR0_AMU_V1P1); + assert(amu_group1_supported()); + assert(idx < AMU_GROUP1_NR_COUNTERS); + assert(((read_amcg1idr_el0() >> AMCG1IDR_VOFF_SHIFT) & + (1ULL << idx)) != 0ULL); + + amu_group1_voffset_write_internal(idx, val); + isb(); +} + /* * Program the event type register for the given `idx` with * the event number `val` */ void amu_group1_set_evtype(unsigned int idx, unsigned int val) { - assert(amu_supported()); + assert(amu_get_version() != ID_AA64PFR0_AMU_NOT_SUPPORTED); assert(amu_group1_supported()); assert(idx < AMU_GROUP1_NR_COUNTERS); @@ -159,7 +253,7 @@ static void *amu_context_save(const void *arg) struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; unsigned int i; - if (!amu_supported()) { + if (amu_get_version() == ID_AA64PFR0_AMU_NOT_SUPPORTED) { return (void *)-1; } @@ -190,13 +284,37 @@ static void *amu_context_save(const void *arg) ctx->group0_cnts[i] = amu_group0_cnt_read(i); } + /* Save group 0 virtual offsets if supported and enabled. */ + if ((amu_get_version() >= ID_AA64PFR0_AMU_V1P1) && + ((read_hcr_el2() & HCR_AMVOFFEN_BIT) != 0ULL)) { + /* Not using a loop because count is fixed and index 1 DNE. */ + ctx->group0_voffsets[0U] = amu_group0_voffset_read(0U); + ctx->group0_voffsets[1U] = amu_group0_voffset_read(2U); + ctx->group0_voffsets[2U] = amu_group0_voffset_read(3U); + } + #if AMU_GROUP1_NR_COUNTERS /* Save group 1 counters */ for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) { - if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) { + if ((AMU_GROUP1_COUNTERS_MASK & (1UL << i)) != 0U) { ctx->group1_cnts[i] = amu_group1_cnt_read(i); } } + + /* Save group 1 virtual offsets if supported and enabled. */ + if ((amu_get_version() >= ID_AA64PFR0_AMU_V1P1) && + ((read_hcr_el2() & HCR_AMVOFFEN_BIT) != 0ULL)) { + u_register_t amcg1idr = read_amcg1idr_el0() >> + AMCG1IDR_VOFF_SHIFT; + amcg1idr = amcg1idr & AMU_GROUP1_COUNTERS_MASK; + + for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) { + if (((amcg1idr >> i) & 1ULL) != 0ULL) { + ctx->group1_voffsets[i] = + amu_group1_voffset_read(i); + } + } + } #endif return (void *)0; } @@ -206,7 +324,7 @@ static void *amu_context_restore(const void *arg) struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; unsigned int i; - if (!amu_supported()) { + if (amu_get_version() == ID_AA64PFR0_AMU_NOT_SUPPORTED) { return (void *)-1; } @@ -227,17 +345,41 @@ static void *amu_context_restore(const void *arg) amu_group0_cnt_write(i, ctx->group0_cnts[i]); } + /* Restore group 0 virtual offsets if supported and enabled. */ + if ((amu_get_version() >= ID_AA64PFR0_AMU_V1P1) && + ((read_hcr_el2() & HCR_AMVOFFEN_BIT) != 0ULL)) { + /* Not using a loop because count is fixed and index 1 DNE. */ + amu_group0_voffset_write(0U, ctx->group0_voffsets[0U]); + amu_group0_voffset_write(2U, ctx->group0_voffsets[1U]); + amu_group0_voffset_write(3U, ctx->group0_voffsets[2U]); + } + /* Restore group 0 counter configuration */ write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK); #if AMU_GROUP1_NR_COUNTERS /* Restore group 1 counters */ for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) { - if ((AMU_GROUP1_COUNTERS_MASK & (1U << i)) != 0U) { + if ((AMU_GROUP1_COUNTERS_MASK & (1UL << i)) != 0U) { amu_group1_cnt_write(i, ctx->group1_cnts[i]); } } + /* Restore group 1 virtual offsets if supported and enabled. */ + if ((amu_get_version() >= ID_AA64PFR0_AMU_V1P1) && + ((read_hcr_el2() & HCR_AMVOFFEN_BIT) != 0ULL)) { + u_register_t amcg1idr = read_amcg1idr_el0() >> + AMCG1IDR_VOFF_SHIFT; + amcg1idr = amcg1idr & AMU_GROUP1_COUNTERS_MASK; + + for (i = 0U; i < AMU_GROUP1_NR_COUNTERS; i++) { + if (((amcg1idr >> i) & 1ULL) != 0ULL) { + amu_group1_voffset_write(i, + ctx->group1_voffsets[i]); + } + } + } + /* Restore group 1 counter configuration */ write_amcntenset1_el0(AMU_GROUP1_COUNTERS_MASK); #endif diff --git a/lib/extensions/amu/aarch64/amu_helpers.S b/lib/extensions/amu/aarch64/amu_helpers.S index 89007a3fb..9989abdeb 100644 --- a/lib/extensions/amu/aarch64/amu_helpers.S +++ b/lib/extensions/amu/aarch64/amu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,12 @@ .globl amu_group1_cnt_write_internal .globl amu_group1_set_evtype_internal + /* FEAT_AMUv1p1 virtualisation offset register functions */ + .globl amu_group0_voffset_read_internal + .globl amu_group0_voffset_write_internal + .globl amu_group1_voffset_read_internal + .globl amu_group1_voffset_write_internal + /* * uint64_t amu_group0_cnt_read_internal(int idx); * @@ -211,3 +217,169 @@ func amu_group1_set_evtype_internal write AMEVTYPER1E_EL0 /* index 14 */ write AMEVTYPER1F_EL0 /* index 15 */ endfunc amu_group1_set_evtype_internal + +/* + * Accessor functions for virtual offset registers added with FEAT_AMUv1p1 + */ + +/* + * uint64_t amu_group0_voffset_read_internal(int idx); + * + * Given `idx`, read the corresponding AMU virtual offset register + * and return it in `x0`. + */ +func amu_group0_voffset_read_internal + adr x1, 1f +#if ENABLE_ASSERTIONS + /* + * It can be dangerous to call this function with an + * out of bounds index. Ensure `idx` is valid. + */ + tst x0, #~3 + ASM_ASSERT(eq) + /* Make sure idx != 1 since AMEVCNTVOFF01_EL2 does not exist */ + cmp x0, #1 + ASM_ASSERT(ne) +#endif + /* + * Given `idx` calculate address of mrs/ret instruction pair + * in the table below. + */ + add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */ +#if ENABLE_BTI + add x1, x1, x0, lsl #2 /* + "bti j" instruction */ +#endif + br x1 + +1: read AMEVCNTVOFF00_EL2 /* index 0 */ + .skip 8 /* AMEVCNTVOFF01_EL2 does not exist */ +#if ENABLE_BTI + .skip 4 +#endif + read AMEVCNTVOFF02_EL2 /* index 2 */ + read AMEVCNTVOFF03_EL2 /* index 3 */ +endfunc amu_group0_voffset_read_internal + +/* + * void amu_group0_voffset_write_internal(int idx, uint64_t val); + * + * Given `idx`, write `val` to the corresponding AMU virtual offset register. + */ +func amu_group0_voffset_write_internal + adr x2, 1f +#if ENABLE_ASSERTIONS + /* + * It can be dangerous to call this function with an + * out of bounds index. Ensure `idx` is valid. + */ + tst x0, #~3 + ASM_ASSERT(eq) + /* Make sure idx != 1 since AMEVCNTVOFF01_EL2 does not exist */ + cmp x0, #1 + ASM_ASSERT(ne) +#endif + /* + * Given `idx` calculate address of mrs/ret instruction pair + * in the table below. + */ + add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */ +#if ENABLE_BTI + add x2, x2, x0, lsl #2 /* + "bti j" instruction */ +#endif + br x2 + +1: write AMEVCNTVOFF00_EL2 /* index 0 */ + .skip 8 /* AMEVCNTVOFF01_EL2 does not exist */ +#if ENABLE_BTI + .skip 4 +#endif + write AMEVCNTVOFF02_EL2 /* index 2 */ + write AMEVCNTVOFF03_EL2 /* index 3 */ +endfunc amu_group0_voffset_write_internal + +/* + * uint64_t amu_group1_voffset_read_internal(int idx); + * + * Given `idx`, read the corresponding AMU virtual offset register + * and return it in `x0`. + */ +func amu_group1_voffset_read_internal + adr x1, 1f +#if ENABLE_ASSERTIONS + /* + * It can be dangerous to call this function with an + * out of bounds index. Ensure `idx` is valid. + */ + tst x0, #~0xF + ASM_ASSERT(eq) +#endif + /* + * Given `idx` calculate address of mrs/ret instruction pair + * in the table below. + */ + add x1, x1, x0, lsl #3 /* each mrs/ret sequence is 8 bytes */ +#if ENABLE_BTI + add x1, x1, x0, lsl #2 /* + "bti j" instruction */ +#endif + br x1 + +1: read AMEVCNTVOFF10_EL2 /* index 0 */ + read AMEVCNTVOFF11_EL2 /* index 1 */ + read AMEVCNTVOFF12_EL2 /* index 2 */ + read AMEVCNTVOFF13_EL2 /* index 3 */ + read AMEVCNTVOFF14_EL2 /* index 4 */ + read AMEVCNTVOFF15_EL2 /* index 5 */ + read AMEVCNTVOFF16_EL2 /* index 6 */ + read AMEVCNTVOFF17_EL2 /* index 7 */ + read AMEVCNTVOFF18_EL2 /* index 8 */ + read AMEVCNTVOFF19_EL2 /* index 9 */ + read AMEVCNTVOFF1A_EL2 /* index 10 */ + read AMEVCNTVOFF1B_EL2 /* index 11 */ + read AMEVCNTVOFF1C_EL2 /* index 12 */ + read AMEVCNTVOFF1D_EL2 /* index 13 */ + read AMEVCNTVOFF1E_EL2 /* index 14 */ + read AMEVCNTVOFF1F_EL2 /* index 15 */ +endfunc amu_group1_voffset_read_internal + +/* + * void amu_group1_voffset_write_internal(int idx, uint64_t val); + * + * Given `idx`, write `val` to the corresponding AMU virtual offset register. + */ +func amu_group1_voffset_write_internal + adr x2, 1f +#if ENABLE_ASSERTIONS + /* + * It can be dangerous to call this function with an + * out of bounds index. Ensure `idx` is valid. + */ + tst x0, #~0xF + ASM_ASSERT(eq) +#endif + /* + * Given `idx` calculate address of mrs/ret instruction pair + * in the table below. + */ + add x2, x2, x0, lsl #3 /* each msr/ret sequence is 8 bytes */ +#if ENABLE_BTI + add x2, x2, x0, lsl #2 /* + "bti j" instruction */ +#endif + br x2 + +1: write AMEVCNTVOFF10_EL2 /* index 0 */ + write AMEVCNTVOFF11_EL2 /* index 1 */ + write AMEVCNTVOFF12_EL2 /* index 2 */ + write AMEVCNTVOFF13_EL2 /* index 3 */ + write AMEVCNTVOFF14_EL2 /* index 4 */ + write AMEVCNTVOFF15_EL2 /* index 5 */ + write AMEVCNTVOFF16_EL2 /* index 6 */ + write AMEVCNTVOFF17_EL2 /* index 7 */ + write AMEVCNTVOFF18_EL2 /* index 8 */ + write AMEVCNTVOFF19_EL2 /* index 9 */ + write AMEVCNTVOFF1A_EL2 /* index 10 */ + write AMEVCNTVOFF1B_EL2 /* index 11 */ + write AMEVCNTVOFF1C_EL2 /* index 12 */ + write AMEVCNTVOFF1D_EL2 /* index 13 */ + write AMEVCNTVOFF1E_EL2 /* index 14 */ + write AMEVCNTVOFF1F_EL2 /* index 15 */ +endfunc amu_group1_voffset_write_internal -- cgit v1.2.3 From aaabf9789ae7d73724c43e7225b1313b7e228054 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Thu, 15 Oct 2020 13:40:04 -0500 Subject: Add Makalu CPU lib Add basic support for Makalu CPU. Signed-off-by: John Powell Change-Id: I4e85d425eedea499adf585eb8ab548931185043d --- lib/cpus/aarch64/cortex_makalu.S | 77 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 lib/cpus/aarch64/cortex_makalu.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_makalu.S b/lib/cpus/aarch64/cortex_makalu.S new file mode 100644 index 000000000..98c7d6dfc --- /dev/null +++ b/lib/cpus/aarch64/cortex_makalu.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +func cortex_makalu_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_makalu_reset_func + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_makalu_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_MAKALU_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_MAKALU_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_makalu_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Makalu. Must follow AAPCS. + */ +func cortex_makalu_errata_report + ret +endfunc cortex_makalu_errata_report +#endif + + /* --------------------------------------------- + * This function provides Cortex Makalu-specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_makalu_regs, "aS" +cortex_makalu_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_makalu_cpu_reg_dump + adr x6, cortex_makalu_regs + mrs x8, CORTEX_MAKALU_CPUECTLR_EL1 + ret +endfunc cortex_makalu_cpu_reg_dump + +declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \ + cortex_makalu_reset_func, \ + cortex_makalu_core_pwr_dwn -- cgit v1.2.3 From 614c14e7781ef63f2aaf145549acaf7d5c2e5c30 Mon Sep 17 00:00:00 2001 From: Usama Arif Date: Wed, 18 Nov 2020 16:46:32 +0000 Subject: cpus: add Matterhorn ELP ARM cpu library Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607 Signed-off-by: Usama Arif --- lib/cpus/aarch64/cortex_matterhorn_elp_arm.S | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 lib/cpus/aarch64/cortex_matterhorn_elp_arm.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S b/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S new file mode 100644 index 000000000..b0f81a20a --- /dev/null +++ b/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Matterhorn ELP ARM must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Matterhorn ELP ARM supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_matterhorn_elp_arm_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_matterhorn_elp_arm_core_pwr_dwn + + /* + * Errata printing function for Cortex Matterhorn_elp_arm. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_matterhorn_elp_arm_errata_report + ret +endfunc cortex_matterhorn_elp_arm_errata_report +#endif + +func cortex_matterhorn_elp_arm_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_matterhorn_elp_arm_reset_func + + /* --------------------------------------------- + * This function provides Cortex-Matterhorn_elp_arm specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_matterhorn_elp_arm_regs, "aS" +cortex_matterhorn_elp_arm_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_matterhorn_elp_arm_cpu_reg_dump + adr x6, cortex_matterhorn_elp_arm_regs + mrs x8, CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1 + ret +endfunc cortex_matterhorn_elp_arm_cpu_reg_dump + +declare_cpu_ops cortex_matterhorn_elp_arm, CORTEX_MATTERHORN_ELP_ARM_MIDR, \ + cortex_matterhorn_elp_arm_reset_func, \ + cortex_matterhorn_elp_arm_core_pwr_dwn -- cgit v1.2.3 From cb090c1924816c379228eda01444aac7f76b965f Mon Sep 17 00:00:00 2001 From: johpow01 Date: Mon, 15 Mar 2021 15:07:21 -0500 Subject: Add Makalu ELP CPU lib Add basic support for Makalu ELP processor core. Signed-off-by: John Powell Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93 --- lib/cpus/aarch64/cortex_makalu_elp.S | 77 ++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 lib/cpus/aarch64/cortex_makalu_elp.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_makalu_elp.S b/lib/cpus/aarch64/cortex_makalu_elp.S new file mode 100644 index 000000000..e3a3e9de8 --- /dev/null +++ b/lib/cpus/aarch64/cortex_makalu_elp.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_makalu_elp_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_makalu_elp_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Makalu ELP. Must follow AAPCS. + */ +func cortex_makalu_elp_errata_report + ret +endfunc cortex_makalu_elp_errata_report +#endif + +func cortex_makalu_elp_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_makalu_elp_reset_func + + /* --------------------------------------------- + * This function provides Cortex Makalu ELP- + * specific register information for crash + * reporting. It needs to return with x6 + * pointing to a list of register names in ascii + * and x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_makalu_elp_regs, "aS" +cortex_makalu_elp_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_makalu_elp_cpu_reg_dump + adr x6, cortex_makalu_elp_regs + mrs x8, CORTEX_MAKALU_ELP_CPUECTLR_EL1 + ret +endfunc cortex_makalu_elp_cpu_reg_dump + +declare_cpu_ops cortex_makalu_elp, CORTEX_MAKALU_ELP_MIDR, \ + cortex_makalu_elp_reset_func, \ + cortex_makalu_elp_core_pwr_dwn -- cgit v1.2.3 From 0a144dd4ea1ab292d0fe5b14d0420063bd0936f5 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 16 Mar 2021 15:20:58 -0500 Subject: Add Cortex_A78C CPU lib Add basic support for Cortex_A78C CPU. Signed-off-by: Bipin Ravi Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56 --- lib/cpus/aarch64/cortex_a78c.S | 65 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 lib/cpus/aarch64/cortex_a78c.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S new file mode 100644 index 000000000..1b170fe65 --- /dev/null +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -0,0 +1,65 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_a78c_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a78c_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex A78C. Must follow AAPCS. + */ +func cortex_a78c_errata_report + ret +endfunc cortex_a78c_errata_report +#endif + + /* --------------------------------------------- + * This function provides cortex_a78c specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a78c_regs, "aS" +cortex_a78c_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a78c_cpu_reg_dump + adr x6, cortex_a78c_regs + mrs x8, CORTEX_A78C_CPUECTLR_EL1 + ret +endfunc cortex_a78c_cpu_reg_dump + +declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ + CPU_NO_RESET_FUNC, \ + cortex_a78c_core_pwr_dwn -- cgit v1.2.3 From a492edc49c650bab1b2106c936c3cd487bbcc580 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Tue, 23 Mar 2021 13:09:35 -0500 Subject: lib/cpu: Workaround for Cortex A77 erratum 1946167 Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions <= r1p1. This erratum is avoided by inserting a DMB ST before acquire atomic instructions without release semantics through a series of writes to implementation defined system registers. SDEN can be found here: https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token= Signed-off-by: Lauren Wehrmeister Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f --- lib/cpus/aarch64/cortex_a77.S | 60 ++++++++++++++++++++++++++++++++++++++++++- lib/cpus/cpu-ops.mk | 8 ++++++ 2 files changed, 67 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index e3a6f5fbf..06b23d929 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -114,6 +114,58 @@ func check_errata_1925769 b cpu_rev_var_ls endfunc check_errata_1925769 + /* -------------------------------------------------- + * Errata Workaround for Cortex A77 Errata #1946167. + * This applies to revision <= r1p1 of Cortex A77. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a77_1946167_wa + /* Compare x0 against revision <= r1p1 */ + mov x17, x30 + bl check_errata_1946167 + cbz x0, 1f + + ldr x0,=0x4 + msr CORTEX_A77_CPUPSELR_EL3,x0 + ldr x0,=0x10E3900002 + msr CORTEX_A77_CPUPOR_EL3,x0 + ldr x0,=0x10FFF00083 + msr CORTEX_A77_CPUPMR_EL3,x0 + ldr x0,=0x2001003FF + msr CORTEX_A77_CPUPCR_EL3,x0 + + ldr x0,=0x5 + msr CORTEX_A77_CPUPSELR_EL3,x0 + ldr x0,=0x10E3800082 + msr CORTEX_A77_CPUPOR_EL3,x0 + ldr x0,=0x10FFF00083 + msr CORTEX_A77_CPUPMR_EL3,x0 + ldr x0,=0x2001003FF + msr CORTEX_A77_CPUPCR_EL3,x0 + + ldr x0,=0x6 + msr CORTEX_A77_CPUPSELR_EL3,x0 + ldr x0,=0x10E3800200 + msr CORTEX_A77_CPUPOR_EL3,x0 + ldr x0,=0x10FFF003E0 + msr CORTEX_A77_CPUPMR_EL3,x0 + ldr x0,=0x2001003FF + msr CORTEX_A77_CPUPCR_EL3,x0 + + isb +1: + ret x17 +endfunc errata_a77_1946167_wa + +func check_errata_1946167 + /* Applies to everything <= r1p1 */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_1946167 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A77. * Shall clobber: x0-x19 @@ -134,6 +186,11 @@ func cortex_a77_reset_func bl errata_a77_1925769_wa #endif +#if ERRATA_A77_1946167 + mov x0, x18 + bl errata_a77_1946167_wa +#endif + ret x19 endfunc cortex_a77_reset_func @@ -169,6 +226,7 @@ func cortex_a77_errata_report */ report_errata ERRATA_A77_1508412, cortex_a77, 1508412 report_errata ERRATA_A77_1925769, cortex_a77, 1925769 + report_errata ERRATA_A77_1946167, cortex_a77, 1946167 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 64a4b4d47..fb3334676 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -290,6 +290,10 @@ ERRATA_A77_1508412 ?=0 # only to revision <= r1p1 of the Cortex A77 cpu. ERRATA_A77_1925769 ?=0 +# Flag to apply erratum 1946167 workaround during reset. This erratum applies +# only to revision <= r1p1 of the Cortex A77 cpu. +ERRATA_A77_1946167 ?=0 + # Flag to apply erratum 1688305 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the A78 cpu. ERRATA_A78_1688305 ?=0 @@ -585,6 +589,10 @@ $(eval $(call add_define,ERRATA_A77_1508412)) $(eval $(call assert_boolean,ERRATA_A77_1925769)) $(eval $(call add_define,ERRATA_A77_1925769)) +# Process ERRATA_A77_1946167 flag +$(eval $(call assert_boolean,ERRATA_A77_1946167)) +$(eval $(call add_define,ERRATA_A77_1946167)) + # Process ERRATA_A78_1688305 flag $(eval $(call assert_boolean,ERRATA_A78_1688305)) $(eval $(call add_define,ERRATA_A78_1688305)) -- cgit v1.2.3 From a7cf2743f3eb487912302aafc748c81bbd1fc603 Mon Sep 17 00:00:00 2001 From: Max Shvetsov Date: Wed, 31 Mar 2021 19:00:38 +0100 Subject: Fix: Remove save/restore of EL2 timer registers Since there is a secure and non-secure version of the timer registers there is no need to preserve their context in EL3. With that, following registers were removed from EL3 save/restore routine: cnthps_ctl_el2 cnthps_tval_el2 cnthps_cval_el2 cnthvs_ctl_el2 cnthvs_tval_el2 cnthvs_cval_el2 cnthp_ctl_el2 cnthp_cval_el2 cnthp_tval_el2 cnthv_ctl_el2 cnthv_cval_el2 cnthv_tval_el2 Signed-off-by: Max Shvetsov Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b --- lib/el3_runtime/aarch64/context.S | 420 ++++++++++++++++---------------------- 1 file changed, 177 insertions(+), 243 deletions(-) (limited to 'lib') diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 75e214d9c..7daf30da1 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -30,7 +30,7 @@ /* ----------------------------------------------------- * The following function strictly follows the AArch64 - * PCS to use x9-x17 (temporary caller-saved registers) + * PCS to use x9-x16 (temporary caller-saved registers) * to save EL2 system register context. It assumes that * 'x0' is pointing to a 'el2_sys_regs' structure where * the register context will be saved. @@ -43,7 +43,6 @@ * ICH_LR_EL2 * ----------------------------------------------------- */ - func el2_sysregs_context_save mrs x9, actlr_el2 mrs x10, afsr0_el2 @@ -54,185 +53,153 @@ func el2_sysregs_context_save stp x11, x12, [x0, #CTX_AFSR1_EL2] mrs x13, cnthctl_el2 - mrs x14, cnthp_ctl_el2 + mrs x14, cntvoff_el2 stp x13, x14, [x0, #CTX_CNTHCTL_EL2] - mrs x15, cnthp_cval_el2 - mrs x16, cnthp_tval_el2 - stp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] - - mrs x17, cntvoff_el2 - mrs x9, cptr_el2 - stp x17, x9, [x0, #CTX_CNTVOFF_EL2] + mrs x15, cptr_el2 + str x15, [x0, #CTX_CPTR_EL2] - mrs x11, elr_el2 #if CTX_INCLUDE_AARCH32_REGS - mrs x10, dbgvcr32_el2 - stp x10, x11, [x0, #CTX_DBGVCR32_EL2] -#else - str x11, [x0, #CTX_ELR_EL2] + mrs x16, dbgvcr32_el2 + str x16, [x0, #CTX_DBGVCR32_EL2] #endif - mrs x14, esr_el2 - mrs x15, far_el2 - stp x14, x15, [x0, #CTX_ESR_EL2] + mrs x9, elr_el2 + mrs x10, esr_el2 + stp x9, x10, [x0, #CTX_ELR_EL2] - mrs x16, hacr_el2 - mrs x17, hcr_el2 - stp x16, x17, [x0, #CTX_HACR_EL2] + mrs x11, far_el2 + mrs x12, hacr_el2 + stp x11, x12, [x0, #CTX_FAR_EL2] - mrs x9, hpfar_el2 - mrs x10, hstr_el2 - stp x9, x10, [x0, #CTX_HPFAR_EL2] + mrs x13, hcr_el2 + mrs x14, hpfar_el2 + stp x13, x14, [x0, #CTX_HCR_EL2] - mrs x11, ICC_SRE_EL2 - mrs x12, ICH_HCR_EL2 - stp x11, x12, [x0, #CTX_ICC_SRE_EL2] + mrs x15, hstr_el2 + mrs x16, ICC_SRE_EL2 + stp x15, x16, [x0, #CTX_HSTR_EL2] - mrs x13, ICH_VMCR_EL2 - mrs x14, mair_el2 - stp x13, x14, [x0, #CTX_ICH_VMCR_EL2] + mrs x9, ICH_HCR_EL2 + mrs x10, ICH_VMCR_EL2 + stp x9, x10, [x0, #CTX_ICH_HCR_EL2] + + mrs x11, mair_el2 + mrs x12, mdcr_el2 + stp x11, x12, [x0, #CTX_MAIR_EL2] - mrs x15, mdcr_el2 #if ENABLE_SPE_FOR_LOWER_ELS - mrs x16, PMSCR_EL2 - stp x15, x16, [x0, #CTX_MDCR_EL2] -#else - str x15, [x0, #CTX_MDCR_EL2] + mrs x13, PMSCR_EL2 + str x13, [x0, #CTX_PMSCR_EL2] #endif + mrs x14, sctlr_el2 + str x14, [x0, #CTX_SCTLR_EL2] - mrs x17, sctlr_el2 - mrs x9, spsr_el2 - stp x17, x9, [x0, #CTX_SCTLR_EL2] + mrs x15, spsr_el2 + mrs x16, sp_el2 + stp x15, x16, [x0, #CTX_SPSR_EL2] - mrs x10, sp_el2 - mrs x11, tcr_el2 - stp x10, x11, [x0, #CTX_SP_EL2] + mrs x9, tcr_el2 + mrs x10, tpidr_el2 + stp x9, x10, [x0, #CTX_TCR_EL2] - mrs x12, tpidr_el2 - mrs x13, ttbr0_el2 - stp x12, x13, [x0, #CTX_TPIDR_EL2] + mrs x11, ttbr0_el2 + mrs x12, vbar_el2 + stp x11, x12, [x0, #CTX_TTBR0_EL2] - mrs x14, vbar_el2 - mrs x15, vmpidr_el2 - stp x14, x15, [x0, #CTX_VBAR_EL2] + mrs x13, vmpidr_el2 + mrs x14, vpidr_el2 + stp x13, x14, [x0, #CTX_VMPIDR_EL2] - mrs x16, vpidr_el2 - mrs x17, vtcr_el2 - stp x16, x17, [x0, #CTX_VPIDR_EL2] - - mrs x9, vttbr_el2 - str x9, [x0, #CTX_VTTBR_EL2] + mrs x15, vtcr_el2 + mrs x16, vttbr_el2 + stp x15, x16, [x0, #CTX_VTCR_EL2] #if CTX_INCLUDE_MTE_REGS - mrs x10, TFSR_EL2 - str x10, [x0, #CTX_TFSR_EL2] + mrs x9, TFSR_EL2 + str x9, [x0, #CTX_TFSR_EL2] #endif #if ENABLE_MPAM_FOR_LOWER_ELS - mrs x9, MPAM2_EL2 - mrs x10, MPAMHCR_EL2 - stp x9, x10, [x0, #CTX_MPAM2_EL2] + mrs x10, MPAM2_EL2 + str x10, [x0, #CTX_MPAM2_EL2] - mrs x11, MPAMVPM0_EL2 - mrs x12, MPAMVPM1_EL2 - stp x11, x12, [x0, #CTX_MPAMVPM0_EL2] + mrs x11, MPAMHCR_EL2 + mrs x12, MPAMVPM0_EL2 + stp x11, x12, [x0, #CTX_MPAMHCR_EL2] - mrs x13, MPAMVPM2_EL2 - mrs x14, MPAMVPM3_EL2 - stp x13, x14, [x0, #CTX_MPAMVPM2_EL2] + mrs x13, MPAMVPM1_EL2 + mrs x14, MPAMVPM2_EL2 + stp x13, x14, [x0, #CTX_MPAMVPM1_EL2] - mrs x15, MPAMVPM4_EL2 - mrs x16, MPAMVPM5_EL2 - stp x15, x16, [x0, #CTX_MPAMVPM4_EL2] + mrs x15, MPAMVPM3_EL2 + mrs x16, MPAMVPM4_EL2 + stp x15, x16, [x0, #CTX_MPAMVPM3_EL2] - mrs x17, MPAMVPM6_EL2 - mrs x9, MPAMVPM7_EL2 - stp x17, x9, [x0, #CTX_MPAMVPM6_EL2] + mrs x9, MPAMVPM5_EL2 + mrs x10, MPAMVPM6_EL2 + stp x9, x10, [x0, #CTX_MPAMVPM5_EL2] - mrs x10, MPAMVPMV_EL2 - str x10, [x0, #CTX_MPAMVPMV_EL2] + mrs x11, MPAMVPM7_EL2 + mrs x12, MPAMVPMV_EL2 + stp x11, x12, [x0, #CTX_MPAMVPM7_EL2] #endif - #if ARM_ARCH_AT_LEAST(8, 6) - mrs x11, HAFGRTR_EL2 - mrs x12, HDFGRTR_EL2 - stp x11, x12, [x0, #CTX_HAFGRTR_EL2] + mrs x13, HAFGRTR_EL2 + mrs x14, HDFGRTR_EL2 + stp x13, x14, [x0, #CTX_HAFGRTR_EL2] - mrs x13, HDFGWTR_EL2 - mrs x14, HFGITR_EL2 - stp x13, x14, [x0, #CTX_HDFGWTR_EL2] + mrs x15, HDFGWTR_EL2 + mrs x16, HFGITR_EL2 + stp x15, x16, [x0, #CTX_HDFGWTR_EL2] - mrs x15, HFGRTR_EL2 - mrs x16, HFGWTR_EL2 - stp x15, x16, [x0, #CTX_HFGRTR_EL2] + mrs x9, HFGRTR_EL2 + mrs x10, HFGWTR_EL2 + stp x9, x10, [x0, #CTX_HFGRTR_EL2] - mrs x17, CNTPOFF_EL2 - str x17, [x0, #CTX_CNTPOFF_EL2] + mrs x11, CNTPOFF_EL2 + str x11, [x0, #CTX_CNTPOFF_EL2] #endif #if ARM_ARCH_AT_LEAST(8, 4) - mrs x9, cnthps_ctl_el2 - mrs x10, cnthps_cval_el2 - stp x9, x10, [x0, #CTX_CNTHPS_CTL_EL2] - - mrs x11, cnthps_tval_el2 - mrs x12, cnthvs_ctl_el2 - stp x11, x12, [x0, #CTX_CNTHPS_TVAL_EL2] - - mrs x13, cnthvs_cval_el2 - mrs x14, cnthvs_tval_el2 - stp x13, x14, [x0, #CTX_CNTHVS_CVAL_EL2] - - mrs x15, cnthv_ctl_el2 - mrs x16, cnthv_cval_el2 - stp x15, x16, [x0, #CTX_CNTHV_CTL_EL2] - - mrs x17, cnthv_tval_el2 - mrs x9, contextidr_el2 - stp x17, x9, [x0, #CTX_CNTHV_TVAL_EL2] + mrs x12, contextidr_el2 + str x12, [x0, #CTX_CONTEXTIDR_EL2] #if CTX_INCLUDE_AARCH32_REGS - mrs x10, sder32_el2 - str x10, [x0, #CTX_SDER32_EL2] + mrs x13, sder32_el2 + str x13, [x0, #CTX_SDER32_EL2] #endif - - mrs x11, ttbr1_el2 - str x11, [x0, #CTX_TTBR1_EL2] - - mrs x12, vdisr_el2 - str x12, [x0, #CTX_VDISR_EL2] + mrs x14, ttbr1_el2 + mrs x15, vdisr_el2 + stp x14, x15, [x0, #CTX_TTBR1_EL2] #if CTX_INCLUDE_NEVE_REGS - mrs x13, vncr_el2 - str x13, [x0, #CTX_VNCR_EL2] + mrs x16, vncr_el2 + str x16, [x0, #CTX_VNCR_EL2] #endif - mrs x14, vsesr_el2 - str x14, [x0, #CTX_VSESR_EL2] - - mrs x15, vstcr_el2 - str x15, [x0, #CTX_VSTCR_EL2] + mrs x9, vsesr_el2 + mrs x10, vstcr_el2 + stp x9, x10, [x0, #CTX_VSESR_EL2] - mrs x16, vsttbr_el2 - str x16, [x0, #CTX_VSTTBR_EL2] - - mrs x17, TRFCR_EL2 - str x17, [x0, #CTX_TRFCR_EL2] + mrs x11, vsttbr_el2 + mrs x12, TRFCR_EL2 + stp x11, x12, [x0, #CTX_VSTTBR_EL2] #endif #if ARM_ARCH_AT_LEAST(8, 5) - mrs x9, scxtnum_el2 - str x9, [x0, #CTX_SCXTNUM_EL2] + mrs x13, scxtnum_el2 + str x13, [x0, #CTX_SCXTNUM_EL2] #endif ret endfunc el2_sysregs_context_save + /* ----------------------------------------------------- * The following function strictly follows the AArch64 - * PCS to use x9-x17 (temporary caller-saved registers) + * PCS to use x9-x16 (temporary caller-saved registers) * to restore EL2 system register context. It assumes * that 'x0' is pointing to a 'el2_sys_regs' structure * from where the register context will be restored @@ -246,7 +213,6 @@ endfunc el2_sysregs_context_save * ----------------------------------------------------- */ func el2_sysregs_context_restore - ldp x9, x10, [x0, #CTX_ACTLR_EL2] msr actlr_el2, x9 msr afsr0_el2, x10 @@ -257,74 +223,66 @@ func el2_sysregs_context_restore ldp x13, x14, [x0, #CTX_CNTHCTL_EL2] msr cnthctl_el2, x13 - msr cnthp_ctl_el2, x14 - - ldp x15, x16, [x0, #CTX_CNTHP_CVAL_EL2] - msr cnthp_cval_el2, x15 - msr cnthp_tval_el2, x16 + msr cntvoff_el2, x14 - ldp x17, x9, [x0, #CTX_CNTVOFF_EL2] - msr cntvoff_el2, x17 - msr cptr_el2, x9 + ldr x15, [x0, #CTX_CPTR_EL2] + msr cptr_el2, x15 #if CTX_INCLUDE_AARCH32_REGS - ldp x10, x11, [x0, #CTX_DBGVCR32_EL2] - msr dbgvcr32_el2, x10 -#else - ldr x11, [x0, #CTX_ELR_EL2] + ldr x16, [x0, #CTX_DBGVCR32_EL2] + msr dbgvcr32_el2, x16 #endif - msr elr_el2, x11 - ldp x14, x15, [x0, #CTX_ESR_EL2] - msr esr_el2, x14 - msr far_el2, x15 + ldp x9, x10, [x0, #CTX_ELR_EL2] + msr elr_el2, x9 + msr esr_el2, x10 + + ldp x11, x12, [x0, #CTX_FAR_EL2] + msr far_el2, x11 + msr hacr_el2, x12 - ldp x16, x17, [x0, #CTX_HACR_EL2] - msr hacr_el2, x16 - msr hcr_el2, x17 + ldp x13, x14, [x0, #CTX_HCR_EL2] + msr hcr_el2, x13 + msr hpfar_el2, x14 - ldp x9, x10, [x0, #CTX_HPFAR_EL2] - msr hpfar_el2, x9 - msr hstr_el2, x10 + ldp x15, x16, [x0, #CTX_HSTR_EL2] + msr hstr_el2, x15 + msr ICC_SRE_EL2, x16 - ldp x11, x12, [x0, #CTX_ICC_SRE_EL2] - msr ICC_SRE_EL2, x11 - msr ICH_HCR_EL2, x12 + ldp x9, x10, [x0, #CTX_ICH_HCR_EL2] + msr ICH_HCR_EL2, x9 + msr ICH_VMCR_EL2, x10 - ldp x13, x14, [x0, #CTX_ICH_VMCR_EL2] - msr ICH_VMCR_EL2, x13 - msr mair_el2, x14 + ldp x11, x12, [x0, #CTX_MAIR_EL2] + msr mair_el2, x11 + msr mdcr_el2, x12 #if ENABLE_SPE_FOR_LOWER_ELS - ldp x15, x16, [x0, #CTX_MDCR_EL2] - msr PMSCR_EL2, x16 -#else - ldr x15, [x0, #CTX_MDCR_EL2] + ldr x13, [x0, #CTX_PMSCR_EL2] + msr PMSCR_EL2, x13 #endif - msr mdcr_el2, x15 + ldr x14, [x0, #CTX_SCTLR_EL2] + msr sctlr_el2, x14 - ldp x17, x9, [x0, #CTX_SCTLR_EL2] - msr sctlr_el2, x17 - msr spsr_el2, x9 + ldp x15, x16, [x0, #CTX_SPSR_EL2] + msr spsr_el2, x15 + msr sp_el2, x16 - ldp x10, x11, [x0, #CTX_SP_EL2] - msr sp_el2, x10 - msr tcr_el2, x11 + ldp x9, x10, [x0, #CTX_TCR_EL2] + msr tcr_el2, x9 + msr tpidr_el2, x10 - ldp x12, x13, [x0, #CTX_TPIDR_EL2] - msr tpidr_el2, x12 - msr ttbr0_el2, x13 + ldp x11, x12, [x0, #CTX_TTBR0_EL2] + msr ttbr0_el2, x11 + msr vbar_el2, x12 - ldp x13, x14, [x0, #CTX_VBAR_EL2] - msr vbar_el2, x13 - msr vmpidr_el2, x14 + ldp x13, x14, [x0, #CTX_VMPIDR_EL2] + msr vmpidr_el2, x13 + msr vpidr_el2, x14 - ldp x15, x16, [x0, #CTX_VPIDR_EL2] - msr vpidr_el2, x15 - msr vtcr_el2, x16 - - ldr x17, [x0, #CTX_VTTBR_EL2] - msr vttbr_el2, x17 + ldp x15, x16, [x0, #CTX_VTCR_EL2] + msr vtcr_el2, x15 + msr vttbr_el2, x16 #if CTX_INCLUDE_MTE_REGS ldr x9, [x0, #CTX_TFSR_EL2] @@ -332,100 +290,76 @@ func el2_sysregs_context_restore #endif #if ENABLE_MPAM_FOR_LOWER_ELS - ldp x10, x11, [x0, #CTX_MPAM2_EL2] + ldr x10, [x0, #CTX_MPAM2_EL2] msr MPAM2_EL2, x10 - msr MPAMHCR_EL2, x11 - ldp x12, x13, [x0, #CTX_MPAMVPM0_EL2] + ldp x11, x12, [x0, #CTX_MPAMHCR_EL2] + msr MPAMHCR_EL2, x11 msr MPAMVPM0_EL2, x12 - msr MPAMVPM1_EL2, x13 - ldp x14, x15, [x0, #CTX_MPAMVPM2_EL2] + ldp x13, x14, [x0, #CTX_MPAMVPM1_EL2] + msr MPAMVPM1_EL2, x13 msr MPAMVPM2_EL2, x14 - msr MPAMVPM3_EL2, x15 - ldp x16, x17, [x0, #CTX_MPAMVPM4_EL2] + ldp x15, x16, [x0, #CTX_MPAMVPM3_EL2] + msr MPAMVPM3_EL2, x15 msr MPAMVPM4_EL2, x16 - msr MPAMVPM5_EL2, x17 - ldp x9, x10, [x0, #CTX_MPAMVPM6_EL2] - msr MPAMVPM6_EL2, x9 - msr MPAMVPM7_EL2, x10 + ldp x9, x10, [x0, #CTX_MPAMVPM5_EL2] + msr MPAMVPM5_EL2, x9 + msr MPAMVPM6_EL2, x10 - ldr x11, [x0, #CTX_MPAMVPMV_EL2] - msr MPAMVPMV_EL2, x11 + ldp x11, x12, [x0, #CTX_MPAMVPM7_EL2] + msr MPAMVPM7_EL2, x11 + msr MPAMVPMV_EL2, x12 #endif #if ARM_ARCH_AT_LEAST(8, 6) - ldp x12, x13, [x0, #CTX_HAFGRTR_EL2] - msr HAFGRTR_EL2, x12 - msr HDFGRTR_EL2, x13 + ldp x13, x14, [x0, #CTX_HAFGRTR_EL2] + msr HAFGRTR_EL2, x13 + msr HDFGRTR_EL2, x14 - ldp x14, x15, [x0, #CTX_HDFGWTR_EL2] - msr HDFGWTR_EL2, x14 - msr HFGITR_EL2, x15 + ldp x15, x16, [x0, #CTX_HDFGWTR_EL2] + msr HDFGWTR_EL2, x15 + msr HFGITR_EL2, x16 - ldp x16, x17, [x0, #CTX_HFGRTR_EL2] - msr HFGRTR_EL2, x16 - msr HFGWTR_EL2, x17 + ldp x9, x10, [x0, #CTX_HFGRTR_EL2] + msr HFGRTR_EL2, x9 + msr HFGWTR_EL2, x10 - ldr x9, [x0, #CTX_CNTPOFF_EL2] - msr CNTPOFF_EL2, x9 + ldr x11, [x0, #CTX_CNTPOFF_EL2] + msr CNTPOFF_EL2, x11 #endif #if ARM_ARCH_AT_LEAST(8, 4) - ldp x10, x11, [x0, #CTX_CNTHPS_CTL_EL2] - msr cnthps_ctl_el2, x10 - msr cnthps_cval_el2, x11 - - ldp x12, x13, [x0, #CTX_CNTHPS_TVAL_EL2] - msr cnthps_tval_el2, x12 - msr cnthvs_ctl_el2, x13 - - ldp x14, x15, [x0, #CTX_CNTHVS_CVAL_EL2] - msr cnthvs_cval_el2, x14 - msr cnthvs_tval_el2, x15 - - ldp x16, x17, [x0, #CTX_CNTHV_CTL_EL2] - msr cnthv_ctl_el2, x16 - msr cnthv_cval_el2, x17 - - ldp x9, x10, [x0, #CTX_CNTHV_TVAL_EL2] - msr cnthv_tval_el2, x9 - msr contextidr_el2, x10 + ldr x12, [x0, #CTX_CONTEXTIDR_EL2] + msr contextidr_el2, x12 #if CTX_INCLUDE_AARCH32_REGS - ldr x11, [x0, #CTX_SDER32_EL2] - msr sder32_el2, x11 + ldr x13, [x0, #CTX_SDER32_EL2] + msr sder32_el2, x13 #endif - - ldr x12, [x0, #CTX_TTBR1_EL2] - msr ttbr1_el2, x12 - - ldr x13, [x0, #CTX_VDISR_EL2] - msr vdisr_el2, x13 + ldp x14, x15, [x0, #CTX_TTBR1_EL2] + msr ttbr1_el2, x14 + msr vdisr_el2, x15 #if CTX_INCLUDE_NEVE_REGS - ldr x14, [x0, #CTX_VNCR_EL2] - msr vncr_el2, x14 + ldr x16, [x0, #CTX_VNCR_EL2] + msr vncr_el2, x16 #endif - ldr x15, [x0, #CTX_VSESR_EL2] - msr vsesr_el2, x15 - - ldr x16, [x0, #CTX_VSTCR_EL2] - msr vstcr_el2, x16 - - ldr x17, [x0, #CTX_VSTTBR_EL2] - msr vsttbr_el2, x17 + ldp x9, x10, [x0, #CTX_VSESR_EL2] + msr vsesr_el2, x9 + msr vstcr_el2, x10 - ldr x9, [x0, #CTX_TRFCR_EL2] - msr TRFCR_EL2, x9 + ldp x11, x12, [x0, #CTX_VSTTBR_EL2] + msr vsttbr_el2, x11 + msr TRFCR_EL2, x12 #endif #if ARM_ARCH_AT_LEAST(8, 5) - ldr x10, [x0, #CTX_SCXTNUM_EL2] - msr scxtnum_el2, x10 + ldr x13, [x0, #CTX_SCXTNUM_EL2] + msr scxtnum_el2, x13 #endif ret -- cgit v1.2.3 From 5d764e05e424bc4a82bbd27cf145122e729660b0 Mon Sep 17 00:00:00 2001 From: Leif Lindholm Date: Wed, 10 Mar 2021 13:23:24 +0000 Subject: Add support for QEMU "max" CPU Enable basic support for QEMU "max" CPU. The "max" CPU does not attampt to emulate any specific CPU, but rather just enables all the functions emulated by QEMU. Change-Id: I69c212932ef61433509662d0fefbabb1e9e71cf2 Signed-off-by: Leif Lindholm --- lib/cpus/aarch64/qemu_max.S | 81 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) create mode 100644 lib/cpus/aarch64/qemu_max.S (limited to 'lib') diff --git a/lib/cpus/aarch64/qemu_max.S b/lib/cpus/aarch64/qemu_max.S new file mode 100644 index 000000000..8948fda70 --- /dev/null +++ b/lib/cpus/aarch64/qemu_max.S @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#include +#include +#include +#include + +func qemu_max_core_pwr_dwn + /* --------------------------------------------- + * Disable the Data Cache. + * --------------------------------------------- + */ + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + + /* --------------------------------------------- + * Flush L1 cache to L2. + * --------------------------------------------- + */ + mov x18, lr + mov x0, #DCCISW + bl dcsw_op_level1 + mov lr, x18 + ret +endfunc qemu_max_core_pwr_dwn + +func qemu_max_cluster_pwr_dwn + /* --------------------------------------------- + * Disable the Data Cache. + * --------------------------------------------- + */ + mrs x1, sctlr_el3 + bic x1, x1, #SCTLR_C_BIT + msr sctlr_el3, x1 + isb + + /* --------------------------------------------- + * Flush all caches to PoC. + * --------------------------------------------- + */ + mov x0, #DCCISW + b dcsw_op_all +endfunc qemu_max_cluster_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for QEMU "max". Must follow AAPCS. + */ +func qemu_max_errata_report + ret +endfunc qemu_max_errata_report +#endif + + /* --------------------------------------------- + * This function provides cpu specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.qemu_max_regs, "aS" +qemu_max_regs: /* The ascii list of register names to be reported */ + .asciz "" /* no registers to report */ + +func qemu_max_cpu_reg_dump + adr x6, qemu_max_regs + ret +endfunc qemu_max_cpu_reg_dump + + +/* cpu_ops for QEMU MAX */ +declare_cpu_ops qemu_max, QEMU_MAX_MIDR, CPU_NO_RESET_FUNC, \ + qemu_max_core_pwr_dwn, \ + qemu_max_cluster_pwr_dwn -- cgit v1.2.3 From 97bc7f0dcc398dd45f5fe2c979aa74a7999d6681 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Tue, 20 Apr 2021 17:05:04 -0500 Subject: Add "_arm" suffix to Makalu ELP CPU lib ELP processors can sometimes have different MIDR values or features so we are adding the "_arm" suffix to differentiate the reference implementation from other future versions. Signed-off-by: John Powell Change-Id: Ieea444288587c7c18a397d279ee4b22b7ad79e20 --- lib/cpus/aarch64/cortex_makalu_elp.S | 77 -------------------------------- lib/cpus/aarch64/cortex_makalu_elp_arm.S | 77 ++++++++++++++++++++++++++++++++ 2 files changed, 77 insertions(+), 77 deletions(-) delete mode 100644 lib/cpus/aarch64/cortex_makalu_elp.S create mode 100644 lib/cpus/aarch64/cortex_makalu_elp_arm.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_makalu_elp.S b/lib/cpus/aarch64/cortex_makalu_elp.S deleted file mode 100644 index e3a3e9de8..000000000 --- a/lib/cpus/aarch64/cortex_makalu_elp.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2021, Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_makalu_elp_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_MAKALU_ELP_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_makalu_elp_core_pwr_dwn - -#if REPORT_ERRATA -/* - * Errata printing function for Cortex Makalu ELP. Must follow AAPCS. - */ -func cortex_makalu_elp_errata_report - ret -endfunc cortex_makalu_elp_errata_report -#endif - -func cortex_makalu_elp_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - isb - ret -endfunc cortex_makalu_elp_reset_func - - /* --------------------------------------------- - * This function provides Cortex Makalu ELP- - * specific register information for crash - * reporting. It needs to return with x6 - * pointing to a list of register names in ascii - * and x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_makalu_elp_regs, "aS" -cortex_makalu_elp_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_makalu_elp_cpu_reg_dump - adr x6, cortex_makalu_elp_regs - mrs x8, CORTEX_MAKALU_ELP_CPUECTLR_EL1 - ret -endfunc cortex_makalu_elp_cpu_reg_dump - -declare_cpu_ops cortex_makalu_elp, CORTEX_MAKALU_ELP_MIDR, \ - cortex_makalu_elp_reset_func, \ - cortex_makalu_elp_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_makalu_elp_arm.S b/lib/cpus/aarch64/cortex_makalu_elp_arm.S new file mode 100644 index 000000000..fbbf20501 --- /dev/null +++ b/lib/cpus/aarch64/cortex_makalu_elp_arm.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Makalu ELP must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Makalu ELP supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_makalu_elp_arm_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_MAKALU_ELP_ARM_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_makalu_elp_arm_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Makalu ELP. Must follow AAPCS. + */ +func cortex_makalu_elp_arm_errata_report + ret +endfunc cortex_makalu_elp_arm_errata_report +#endif + +func cortex_makalu_elp_arm_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_makalu_elp_arm_reset_func + + /* --------------------------------------------- + * This function provides Cortex Makalu ELP- + * specific register information for crash + * reporting. It needs to return with x6 + * pointing to a list of register names in ascii + * and x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_makalu_elp_arm_regs, "aS" +cortex_makalu_elp_arm_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_makalu_elp_arm_cpu_reg_dump + adr x6, cortex_makalu_elp_arm_regs + mrs x8, CORTEX_MAKALU_ELP_ARM_CPUECTLR_EL1 + ret +endfunc cortex_makalu_elp_arm_cpu_reg_dump + +declare_cpu_ops cortex_makalu_elp_arm, CORTEX_MAKALU_ELP_ARM_MIDR, \ + cortex_makalu_elp_arm_reset_func, \ + cortex_makalu_elp_arm_core_pwr_dwn -- cgit v1.2.3 From 4324a14bf548f5c56edc48128aba1aca0da2edf5 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Mon, 5 Oct 2020 11:02:54 +0200 Subject: Add PIE support for AARCH32 Only BL32 (SP_min) is supported at the moment, BL1 and BL2_AT_EL3 are just stubbed with _pie_fixup_size=0. The changes are an adaptation for AARCH32 on what has been done for PIE support on AARCH64. The RELA_SECTION is redefined for AARCH32, as the created section is .rel.dyn and the symbols are .rel*. Change-Id: I92bafe70e6b77735f6f890f32f2b637b98cf01b9 Signed-off-by: Yann Gautier --- lib/aarch32/misc_helpers.S | 128 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 127 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/aarch32/misc_helpers.S b/lib/aarch32/misc_helpers.S index e9734ac2c..8b16f93cc 100644 --- a/lib/aarch32/misc_helpers.S +++ b/lib/aarch32/misc_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,8 @@ #include #include #include +#include +#include .globl smc .globl zeromem @@ -14,6 +16,9 @@ .globl memcpy4 .globl disable_mmu_icache_secure .globl disable_mmu_secure + .globl fixup_gdt_reloc + +#define PAGE_START_MASK ~(PAGE_SIZE_MASK) func smc /* @@ -187,3 +192,124 @@ func disable_mmu_icache_secure ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) b do_disable_mmu endfunc disable_mmu_icache_secure + +/* --------------------------------------------------------------------------- + * Helper to fixup Global Descriptor table (GDT) and dynamic relocations + * (.rel.dyn) at runtime. + * + * This function is meant to be used when the firmware is compiled with -fpie + * and linked with -pie options. We rely on the linker script exporting + * appropriate markers for start and end of the section. For GOT, we + * expect __GOT_START__ and __GOT_END__. Similarly for .rela.dyn, we expect + * __RELA_START__ and __RELA_END__. + * + * The function takes the limits of the memory to apply fixups to as + * arguments (which is usually the limits of the relocable BL image). + * r0 - the start of the fixup region + * r1 - the limit of the fixup region + * These addresses have to be 4KB page aligned. + * --------------------------------------------------------------------------- + */ + +/* Relocation codes */ +#define R_ARM_RELATIVE 23 + +func fixup_gdt_reloc + mov r6, r0 + mov r7, r1 + +#if ENABLE_ASSERTIONS + /* Test if the limits are 4K aligned */ + orr r0, r0, r1 + mov r1, #(PAGE_SIZE_MASK) + tst r0, r1 + ASM_ASSERT(eq) +#endif + /* + * Calculate the offset based on return address in lr. + * Assume that this function is called within a page at the start of + * fixup region. + */ + ldr r1, =PAGE_START_MASK + and r2, lr, r1 + subs r0, r2, r6 /* Diff(S) = Current Address - Compiled Address */ + beq 3f /* Diff(S) = 0. No relocation needed */ + + ldr r1, =__GOT_START__ + add r1, r1, r0 + ldr r2, =__GOT_END__ + add r2, r2, r0 + + /* + * GOT is an array of 32_bit addresses which must be fixed up as + * new_addr = old_addr + Diff(S). + * The new_addr is the address currently the binary is executing from + * and old_addr is the address at compile time. + */ +1: ldr r3, [r1] + + /* Skip adding offset if address is < lower limit */ + cmp r3, r6 + blo 2f + + /* Skip adding offset if address is > upper limit */ + cmp r3, r7 + bhi 2f + add r3, r3, r0 + str r3, [r1] + +2: add r1, r1, #4 + cmp r1, r2 + blo 1b + + /* Starting dynamic relocations. Use ldr to get RELA_START and END */ +3: ldr r1, =__RELA_START__ + add r1, r1, r0 + ldr r2, =__RELA_END__ + add r2, r2, r0 + + /* + * According to ELF-32 specification, the RELA data structure is as + * follows: + * typedef struct { + * Elf32_Addr r_offset; + * Elf32_Xword r_info; + * } Elf32_Rela; + * + * r_offset is address of reference + * r_info is symbol index and type of relocation (in this case + * code 23 which corresponds to R_ARM_RELATIVE). + * + * Size of Elf32_Rela structure is 8 bytes. + */ + + /* Skip R_ARM_NONE entry with code 0 */ +1: ldr r3, [r1, #4] + ands r3, r3, #0xff + beq 2f + +#if ENABLE_ASSERTIONS + /* Assert that the relocation type is R_ARM_RELATIVE */ + cmp r3, #R_ARM_RELATIVE + ASM_ASSERT(eq) +#endif + ldr r3, [r1] /* r_offset */ + add r3, r0, r3 /* Diff(S) + r_offset */ + ldr r4, [r3] + + /* Skip adding offset if address is < lower limit */ + cmp r4, r6 + blo 2f + + /* Skip adding offset if address is >= upper limit */ + cmp r4, r7 + bhs 2f + + add r4, r0, r4 + str r4, [r3] + +2: add r1, r1, #8 + cmp r1, r2 + blo 1b + bx lr +endfunc fixup_gdt_reloc -- cgit v1.2.3 From 12f6c0649732a35a7ed45ba350a963f09a5710ca Mon Sep 17 00:00:00 2001 From: Alexei Fedorov Date: Fri, 14 May 2021 11:21:56 +0100 Subject: fix(security): Set MDCR_EL3.MCCD bit This patch adds setting MDCR_EL3.MCCD in 'el3_arch_init_common' macro to disable cycle counting by PMCCNTR_EL0 in EL3 when FEAT_PMUv3p7 is implemented. This fixes failing test 'Leak PMU CYCLE counter values from EL3 on PSCI suspend SMC' on FVP models with 'has_v8_7_pmu_extension' parameter set to 1 or 2. Signed-off-by: Alexei Fedorov Change-Id: I2ad3ef501b31ee11306f76cb5a61032ecfd0fbda --- lib/el3_runtime/aarch64/context.S | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'lib') diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 7daf30da1..0ec9ffd5d 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -697,13 +697,14 @@ func save_gp_pmcr_pauth_regs str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] /* ---------------------------------------------------------- - * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, - * meaning that ARMv8-PMU is not implemented and PMCR_EL0 - * should be saved in non-secure context. + * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1 + * failed, meaning that FEAT_PMUv3p5/7 is not implemented and + * PMCR_EL0 should be saved in non-secure context. * ---------------------------------------------------------- */ + mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT) mrs x9, mdcr_el3 - tst x9, #MDCR_SCCD_BIT + tst x9, x10 bne 1f /* Secure Cycle Counter is not disabled */ @@ -792,13 +793,14 @@ func restore_gp_pmcr_pauth_regs /* ---------------------------------------------------------- * Back to Non-secure state. - * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, - * meaning that ARMv8-PMU is not implemented and PMCR_EL0 - * should be restored from non-secure context. + * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1 + * failed, meaning that FEAT_PMUv3p5/7 is not implemented and + * PMCR_EL0 should be restored from non-secure context. * ---------------------------------------------------------- */ + mov_imm x1, (MDCR_SCCD_BIT | MDCR_MCCD_BIT) mrs x0, mdcr_el3 - tst x0, #MDCR_SCCD_BIT + tst x0, x1 bne 2f ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] msr pmcr_el0, x0 -- cgit v1.2.3 From c6ac4df622befb5bb42ac136745094e1498c91d8 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Tue, 18 May 2021 15:23:31 -0500 Subject: fix: rename Matterhorn, Matterhorn ELP, and Klein CPUs This patch renames the Matterhorn, Matterhorn ELP, and Klein CPUs to Cortex A710, Cortex X2, and Cortex A510 respectively. Signed-off-by: John Powell Change-Id: I056d3114210db71c2840a24562b51caf2546e195 --- lib/cpus/aarch64/cortex_a510.S | 77 ++++++++++++++++++++++++++++ lib/cpus/aarch64/cortex_a710.S | 77 ++++++++++++++++++++++++++++ lib/cpus/aarch64/cortex_klein.S | 77 ---------------------------- lib/cpus/aarch64/cortex_matterhorn.S | 77 ---------------------------- lib/cpus/aarch64/cortex_matterhorn_elp_arm.S | 77 ---------------------------- lib/cpus/aarch64/cortex_x2.S | 77 ++++++++++++++++++++++++++++ 6 files changed, 231 insertions(+), 231 deletions(-) create mode 100644 lib/cpus/aarch64/cortex_a510.S create mode 100644 lib/cpus/aarch64/cortex_a710.S delete mode 100644 lib/cpus/aarch64/cortex_klein.S delete mode 100644 lib/cpus/aarch64/cortex_matterhorn.S delete mode 100644 lib/cpus/aarch64/cortex_matterhorn_elp_arm.S create mode 100644 lib/cpus/aarch64/cortex_x2.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S new file mode 100644 index 000000000..33103228a --- /dev/null +++ b/lib/cpus/aarch64/cortex_a510.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex A510 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_a510_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_A510_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A510_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a510_core_pwr_dwn + + /* + * Errata printing function for Cortex A510. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_a510_errata_report + ret +endfunc cortex_a510_errata_report +#endif + +func cortex_a510_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_a510_reset_func + + /* --------------------------------------------- + * This function provides Cortex-A510 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a510_regs, "aS" +cortex_a510_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a510_cpu_reg_dump + adr x6, cortex_a510_regs + mrs x8, CORTEX_A510_CPUECTLR_EL1 + ret +endfunc cortex_a510_cpu_reg_dump + +declare_cpu_ops cortex_a510, CORTEX_A510_MIDR, \ + cortex_a510_reset_func, \ + cortex_a510_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S new file mode 100644 index 000000000..4f979f8aa --- /dev/null +++ b/lib/cpus/aarch64/cortex_a710.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex A710 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_a710_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_A710_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_A710_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_a710_core_pwr_dwn + + /* + * Errata printing function for Cortex A710. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_a710_errata_report + ret +endfunc cortex_a710_errata_report +#endif + +func cortex_a710_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_a710_reset_func + + /* --------------------------------------------- + * This function provides Cortex-A710 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_a710_regs, "aS" +cortex_a710_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_a710_cpu_reg_dump + adr x6, cortex_a710_regs + mrs x8, CORTEX_A710_CPUECTLR_EL1 + ret +endfunc cortex_a710_cpu_reg_dump + +declare_cpu_ops cortex_a710, CORTEX_A710_MIDR, \ + cortex_a710_reset_func, \ + cortex_a710_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_klein.S b/lib/cpus/aarch64/cortex_klein.S deleted file mode 100644 index d3a8ab481..000000000 --- a/lib/cpus/aarch64/cortex_klein.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2020, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Klein must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Klein supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_klein_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_KLEIN_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_KLEIN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_KLEIN_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_klein_core_pwr_dwn - - /* - * Errata printing function for Cortex Klein. Must follow AAPCS. - */ -#if REPORT_ERRATA -func cortex_klein_errata_report - ret -endfunc cortex_klein_errata_report -#endif - -func cortex_klein_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - isb - ret -endfunc cortex_klein_reset_func - - /* --------------------------------------------- - * This function provides Cortex-Klein specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_klein_regs, "aS" -cortex_klein_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_klein_cpu_reg_dump - adr x6, cortex_klein_regs - mrs x8, CORTEX_KLEIN_CPUECTLR_EL1 - ret -endfunc cortex_klein_cpu_reg_dump - -declare_cpu_ops cortex_klein, CORTEX_KLEIN_MIDR, \ - cortex_klein_reset_func, \ - cortex_klein_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_matterhorn.S b/lib/cpus/aarch64/cortex_matterhorn.S deleted file mode 100644 index 4156f3cf8..000000000 --- a/lib/cpus/aarch64/cortex_matterhorn.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2020, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Matterhorn must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Matterhorn supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_matterhorn_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_MATTERHORN_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_MATTERHORN_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_MATTERHORN_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_matterhorn_core_pwr_dwn - - /* - * Errata printing function for Cortex Matterhorn. Must follow AAPCS. - */ -#if REPORT_ERRATA -func cortex_matterhorn_errata_report - ret -endfunc cortex_matterhorn_errata_report -#endif - -func cortex_matterhorn_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - isb - ret -endfunc cortex_matterhorn_reset_func - - /* --------------------------------------------- - * This function provides Cortex-Matterhorn specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_matterhorn_regs, "aS" -cortex_matterhorn_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_matterhorn_cpu_reg_dump - adr x6, cortex_matterhorn_regs - mrs x8, CORTEX_MATTERHORN_CPUECTLR_EL1 - ret -endfunc cortex_matterhorn_cpu_reg_dump - -declare_cpu_ops cortex_matterhorn, CORTEX_MATTERHORN_MIDR, \ - cortex_matterhorn_reset_func, \ - cortex_matterhorn_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S b/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S deleted file mode 100644 index b0f81a20a..000000000 --- a/lib/cpus/aarch64/cortex_matterhorn_elp_arm.S +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2021, ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include -#include -#include -#include -#include -#include - -/* Hardware handled coherency */ -#if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Matterhorn ELP ARM must be compiled with HW_ASSISTED_COHERENCY enabled" -#endif - -/* 64-bit only core */ -#if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Matterhorn ELP ARM supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" -#endif - - /* ---------------------------------------------------- - * HW will do the cache maintenance while powering down - * ---------------------------------------------------- - */ -func cortex_matterhorn_elp_arm_core_pwr_dwn - /* --------------------------------------------------- - * Enable CPU power down bit in power control register - * --------------------------------------------------- - */ - mrs x0, CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_MATTERHORN_ELP_ARM_CPUPWRCTLR_EL1, x0 - isb - ret -endfunc cortex_matterhorn_elp_arm_core_pwr_dwn - - /* - * Errata printing function for Cortex Matterhorn_elp_arm. Must follow AAPCS. - */ -#if REPORT_ERRATA -func cortex_matterhorn_elp_arm_errata_report - ret -endfunc cortex_matterhorn_elp_arm_errata_report -#endif - -func cortex_matterhorn_elp_arm_reset_func - /* Disable speculative loads */ - msr SSBS, xzr - isb - ret -endfunc cortex_matterhorn_elp_arm_reset_func - - /* --------------------------------------------- - * This function provides Cortex-Matterhorn_elp_arm specific - * register information for crash reporting. - * It needs to return with x6 pointing to - * a list of register names in ascii and - * x8 - x15 having values of registers to be - * reported. - * --------------------------------------------- - */ -.section .rodata.cortex_matterhorn_elp_arm_regs, "aS" -cortex_matterhorn_elp_arm_regs: /* The ascii list of register names to be reported */ - .asciz "cpuectlr_el1", "" - -func cortex_matterhorn_elp_arm_cpu_reg_dump - adr x6, cortex_matterhorn_elp_arm_regs - mrs x8, CORTEX_MATTERHORN_ELP_ARM_CPUECTLR_EL1 - ret -endfunc cortex_matterhorn_elp_arm_cpu_reg_dump - -declare_cpu_ops cortex_matterhorn_elp_arm, CORTEX_MATTERHORN_ELP_ARM_MIDR, \ - cortex_matterhorn_elp_arm_reset_func, \ - cortex_matterhorn_elp_arm_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S new file mode 100644 index 000000000..87a9bdf2b --- /dev/null +++ b/lib/cpus/aarch64/cortex_x2.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_x2_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_X2_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_x2_core_pwr_dwn + + /* + * Errata printing function for Cortex X2. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_x2_errata_report + ret +endfunc cortex_x2_errata_report +#endif + +func cortex_x2_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_x2_reset_func + + /* --------------------------------------------- + * This function provides Cortex X2 specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_x2_regs, "aS" +cortex_x2_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_x2_cpu_reg_dump + adr x6, cortex_x2_regs + mrs x8, CORTEX_X2_CPUECTLR_EL1 + ret +endfunc cortex_x2_cpu_reg_dump + +declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ + cortex_x2_reset_func, \ + cortex_x2_core_pwr_dwn -- cgit v1.2.3 From 2e61d6871cc310e9404fe5cfa10b9828f1c869a7 Mon Sep 17 00:00:00 2001 From: Olivier Deprez Date: Tue, 25 May 2021 12:06:03 +0200 Subject: fix: random typos in tf-a code base Signed-off-by: Olivier Deprez Change-Id: Id610f7e4398e799a2fbd74861274fd684c32db53 --- lib/cpus/aarch64/cpu_helpers.S | 4 ++-- lib/el3_runtime/aarch32/context_mgmt.c | 4 ++-- lib/el3_runtime/aarch64/context_mgmt.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 730b09beb..bd8f85f6d 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -144,7 +144,7 @@ endfunc do_cpu_reg_dump * If cpu_ops for the MIDR_EL1 cannot be found and * SUPPORT_UNKNOWN_MPID is enabled, it will try to look for a * default cpu_ops with an MIDR value of 0. - * (Implementation number 0x0 should be reseverd for software use + * (Implementation number 0x0 should be reserved for software use * and therefore no clashes should happen with that default value). * * Return : diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index 2443001b8..81d793b46 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -49,7 +49,7 @@ void cm_init(void) * * To prepare the register state for entry call cm_prepare_el3_exit() and * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to - * cm_e1_sysreg_context_restore(). + * cm_el1_sysregs_context_restore(). ******************************************************************************/ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) { diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index e0e429849..96023b694 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -60,7 +60,7 @@ void __init cm_init(void) * * To prepare the register state for entry call cm_prepare_el3_exit() and * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to - * cm_e1_sysreg_context_restore(). + * cm_el1_sysregs_context_restore(). ******************************************************************************/ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) { @@ -286,7 +286,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) /* * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2 - * and other EL2 registers are set up by cm_prepare_ns_entry() as they + * and other EL2 registers are set up by cm_prepare_el3_exit() as they * are not part of the stored cpu_context. */ write_ctx_reg(get_el1_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx); -- cgit v1.2.3 From 3f0bec7c888a56cd2277cdd7c6893de4f599ffc2 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Mon, 3 May 2021 13:37:13 -0500 Subject: errata: workaround for Cortex A77 errata 1791578 Cortex A77 erratum 1791578 is a Cat B erratum present in r0p0, r1p0, and r1p1 of the A77 processor core, it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60a63a3c982fc7708ac1c8b1 Signed-off-by: John Powell Change-Id: Ib4b963144f880002de308def12744b982d3df868 --- lib/cpus/aarch64/cortex_a77.S | 34 ++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 42 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S index 06b23d929..8c8f4d3e9 100644 --- a/lib/cpus/aarch64/cortex_a77.S +++ b/lib/cpus/aarch64/cortex_a77.S @@ -166,6 +166,34 @@ func check_errata_1946167 b cpu_rev_var_ls endfunc check_errata_1946167 + /* -------------------------------------------------- + * Errata Workaround for Cortex A77 Errata #1791578. + * This applies to revisions r0p0, r1p0, and r1p1 and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a77_1791578_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1791578 + cbz x0, 1f + + /* Set bit 2 in ACTLR2_EL1 */ + mrs x1, CORTEX_A77_ACTLR2_EL1 + orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2 + msr CORTEX_A77_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_a77_1791578_wa + +func check_errata_1791578 + /* Applies to r0p0, r1p0, and r1p1 right now */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_1791578 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A77. * Shall clobber: x0-x19 @@ -191,6 +219,11 @@ func cortex_a77_reset_func bl errata_a77_1946167_wa #endif +#if ERRATA_A77_1791578 + mov x0, x18 + bl errata_a77_1791578_wa +#endif + ret x19 endfunc cortex_a77_reset_func @@ -227,6 +260,7 @@ func cortex_a77_errata_report report_errata ERRATA_A77_1508412, cortex_a77, 1508412 report_errata ERRATA_A77_1925769, cortex_a77, 1925769 report_errata ERRATA_A77_1946167, cortex_a77, 1946167 + report_errata ERRATA_A77_1791578, cortex_a77, 1791578 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index fb3334676..924c8d65b 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -294,6 +294,10 @@ ERRATA_A77_1925769 ?=0 # only to revision <= r1p1 of the Cortex A77 cpu. ERRATA_A77_1946167 ?=0 +# Flag to apply erratum 1791578 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, and r1p1, it is still open. +ERRATA_A77_1791578 ?=0 + # Flag to apply erratum 1688305 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the A78 cpu. ERRATA_A78_1688305 ?=0 @@ -593,6 +597,10 @@ $(eval $(call add_define,ERRATA_A77_1925769)) $(eval $(call assert_boolean,ERRATA_A77_1946167)) $(eval $(call add_define,ERRATA_A77_1946167)) +# Process ERRATA_A77_1791578 flag +$(eval $(call assert_boolean,ERRATA_A77_1791578)) +$(eval $(call add_define,ERRATA_A77_1791578)) + # Process ERRATA_A78_1688305 flag $(eval $(call assert_boolean,ERRATA_A78_1688305)) $(eval $(call add_define,ERRATA_A78_1688305)) -- cgit v1.2.3 From 1a691455d9cb714a5dce80a2646567d5636a7779 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Fri, 30 Apr 2021 18:08:52 -0500 Subject: errata: workaround for Cortex A78 errata 1821534 Cortex A78 erratum 1821534 is a Cat B erratum present in r0p0 and r1p0 of the A78 processor core, it is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/603e3733492bde1625aa8780 Signed-off-by: John Powell Change-Id: I71057c4b9625cd9edc1a06946b453cf16ae5ea2c --- lib/cpus/aarch64/cortex_a78.S | 68 ++++++++++++++++++++++++++++++++----------- lib/cpus/cpu-ops.mk | 8 +++++ 2 files changed, 59 insertions(+), 17 deletions(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index f61726b46..8c5a45a7b 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -44,13 +44,13 @@ func check_errata_1688305 b cpu_rev_var_ls endfunc check_errata_1688305 - /* -------------------------------------------------- - * Errata Workaround for Cortex A78 Errata #1941498. - * This applies to revisions r0p0, r1p0, and r1p1. - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ +/* -------------------------------------------------- + * Errata Workaround for Cortex A78 Errata #1941498. + * This applies to revisions r0p0, r1p0, and r1p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ func errata_a78_1941498_wa /* Compare x0 against revision <= r1p1 */ mov x17, x30 @@ -72,16 +72,16 @@ func check_errata_1941498 b cpu_rev_var_ls endfunc check_errata_1941498 - /* -------------------------------------------------- - * Errata Workaround for A78 Erratum 1951500. - * This applies to revisions r1p0 and r1p1 of A78. - * The issue also exists in r0p0 but there is no fix - * in that revision. - * Inputs: - * x0: variant[4:7] and revision[0:3] of current cpu. - * Shall clobber: x0-x17 - * -------------------------------------------------- - */ +/* -------------------------------------------------- + * Errata Workaround for A78 Erratum 1951500. + * This applies to revisions r1p0 and r1p1 of A78. + * The issue also exists in r0p0 but there is no fix + * in that revision. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ func errata_a78_1951500_wa /* Compare x0 against revisions r1p0 - r1p1 */ mov x17, x30 @@ -126,6 +126,34 @@ func check_errata_1951500 b cpu_rev_var_range endfunc check_errata_1951500 +/* -------------------------------------------------- + * Errata Workaround for Cortex A78 Errata #1821534. + * This applies to revisions r0p0 and r1p0. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78_1821534_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_1821534 + cbz x0, 1f + + /* Set bit 2 in ACTLR2_EL1 */ + mrs x1, CORTEX_A78_ACTLR2_EL1 + orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2 + msr CORTEX_A78_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_a78_1821534_wa + +func check_errata_1821534 + /* Applies to r0p0 and r1p0 */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1821534 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A78 * ------------------------------------------------- @@ -150,6 +178,11 @@ func cortex_a78_reset_func bl errata_a78_1951500_wa #endif +#if ERRATA_A78_1821534 + mov x0, x18 + bl errata_a78_1821534_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -207,6 +240,7 @@ func cortex_a78_errata_report report_errata ERRATA_A78_1688305, cortex_a78, 1688305 report_errata ERRATA_A78_1941498, cortex_a78, 1941498 report_errata ERRATA_A78_1951500, cortex_a78, 1951500 + report_errata ERRATA_A78_1821534, cortex_a78, 1821534 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index fb3334676..541a2a2cf 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -307,6 +307,10 @@ ERRATA_A78_1941498 ?=0 # well but there is no workaround for that revision. ERRATA_A78_1951500 ?=0 +# Flag to apply erratum 1821534 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the A78 cpu. +ERRATA_A78_1821534 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=0 @@ -605,6 +609,10 @@ $(eval $(call add_define,ERRATA_A78_1941498)) $(eval $(call assert_boolean,ERRATA_A78_1951500)) $(eval $(call add_define,ERRATA_A78_1951500)) +# Process ERRATA_A78_1821534 flag +$(eval $(call assert_boolean,ERRATA_A78_1821534)) +$(eval $(call add_define,ERRATA_A78_1821534)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) -- cgit v1.2.3 From 0c5e7d1ce376cabcebebc43dbf238fe4482ab2dc Mon Sep 17 00:00:00 2001 From: Max Shvetsov Date: Mon, 22 Mar 2021 11:59:37 +0000 Subject: feat(sve): enable SVE for the secure world Enables SVE support for the secure world via ENABLE_SVE_FOR_SWD. ENABLE_SVE_FOR_SWD defaults to 0 and has to be explicitly set by the platform. SVE is configured during initial setup and then uses EL3 context save/restore routine to switch between SVE configurations for different contexts. Reset value of CPTR_EL3 changed to be most restrictive by default. Signed-off-by: Max Shvetsov Change-Id: I889fbbc2e435435d66779b73a2d90d1188bf4116 --- lib/el3_runtime/aarch64/context.S | 23 ++++++ lib/el3_runtime/aarch64/context_mgmt.c | 16 +++-- lib/extensions/sve/sve.c | 124 +++++---------------------------- 3 files changed, 53 insertions(+), 110 deletions(-) (limited to 'lib') diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 0ec9ffd5d..d610fd492 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -901,6 +901,29 @@ func el3_exit msr spsr_el3, x16 msr elr_el3, x17 +#if IMAGE_BL31 + /* ---------------------------------------------------------- + * Restore CPTR_EL3, ZCR_EL3 for SVE support. + * If SVE is not supported - skip the restoration. + * ZCR is only restored if SVE is supported and enabled. + * Synchronization is required before zcr_el3 is addressed. + * ---------------------------------------------------------- + */ + mrs x17, id_aa64pfr0_el1 + ubfx x17, x17, ID_AA64PFR0_SVE_SHIFT, ID_AA64PFR0_SVE_LENGTH + cbz x17, sve_not_enabled + + ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3] + msr cptr_el3, x19 + + ands x19, x19, #CPTR_EZ_BIT + beq sve_not_enabled + + isb + msr S3_6_C1_C2_0, x20 /* zcr_el3 */ +sve_not_enabled: +#endif + #if IMAGE_BL31 && DYNAMIC_WORKAROUND_CVE_2018_3639 /* ---------------------------------------------------------- * Restore mitigation state as it was on entry to EL3 diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 96023b694..7a25151c5 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -178,6 +178,18 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * indicated by the interrupt routing model for BL31. */ scr_el3 |= get_scr_el3_from_routing_model(security_state); + +#if ENABLE_SVE_FOR_NS + if (security_state == NON_SECURE) { + sve_enable(ctx); + } +#endif +#if ENABLE_SVE_FOR_SWD + if (security_state == SECURE) { + sve_enable(ctx); + } +#endif + #endif /* @@ -334,10 +346,6 @@ static void enable_extensions_nonsecure(bool el2_unused) amu_enable(el2_unused); #endif -#if ENABLE_SVE_FOR_NS - sve_enable(el2_unused); -#endif - #if ENABLE_MPAM_FOR_LOWER_ELS mpam_enable(el2_unused); #endif diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c index fa4ac7758..7043cc220 100644 --- a/lib/extensions/sve/sve.c +++ b/lib/extensions/sve/sve.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -11,7 +11,13 @@ #include #include -bool sve_supported(void) +/* + * Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation. + * VECTOR_SIZE = (LEN+1) * 128 + */ +#define CONVERT_SVE_LENGTH(x) (((x / 128) - 1)) + +static bool sve_supported(void) { uint64_t features; @@ -19,113 +25,19 @@ bool sve_supported(void) return (features & ID_AA64PFR0_SVE_MASK) == 1U; } -static void *disable_sve_hook(const void *arg) +void sve_enable(cpu_context_t *context) { - uint64_t cptr; - - if (!sve_supported()) - return (void *)-1; - - /* - * Disable SVE, SIMD and FP access for the Secure world. - * As the SIMD/FP registers are part of the SVE Z-registers, any - * use of SIMD/FP functionality will corrupt the SVE registers. - * Therefore it is necessary to prevent use of SIMD/FP support - * in the Secure world as well as SVE functionality. - */ - cptr = read_cptr_el3(); - cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT); - write_cptr_el3(cptr); - - /* - * No explicit ISB required here as ERET to switch to Secure - * world covers it - */ - return (void *)0; -} - -static void *enable_sve_hook(const void *arg) -{ - uint64_t cptr; - - if (!sve_supported()) - return (void *)-1; - - /* - * Enable SVE, SIMD and FP access for the Non-secure world. - */ - cptr = read_cptr_el3(); - cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT); - write_cptr_el3(cptr); - - /* - * No explicit ISB required here as ERET to switch to Non-secure - * world covers it - */ - return (void *)0; -} - -void sve_enable(bool el2_unused) -{ - uint64_t cptr; - - if (!sve_supported()) + if (!sve_supported()) { return; + } -#if CTX_INCLUDE_FPREGS - /* - * CTX_INCLUDE_FPREGS is not supported on SVE enabled systems. - */ - assert(0); -#endif - /* - * Update CPTR_EL3 to enable access to SVE functionality for the - * Non-secure world. - * NOTE - assumed that CPTR_EL3.TFP is set to allow access to - * the SIMD, floating-point and SVE support. - * - * CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality - * in the Non-secure world. - */ - cptr = read_cptr_el3(); - cptr |= CPTR_EZ_BIT; - write_cptr_el3(cptr); - - /* - * Need explicit ISB here to guarantee that update to ZCR_ELx - * and CPTR_EL2.TZ do not result in trap to EL3. - */ - isb(); - - /* - * Ensure lower ELs have access to full vector length. - */ - write_zcr_el3(ZCR_EL3_LEN_MASK); + u_register_t cptr_el3 = read_cptr_el3(); - if (el2_unused) { - /* - * Update CPTR_EL2 to enable access to SVE functionality - * for Non-secure world, EL2 and Non-secure EL1 and EL0. - * NOTE - assumed that CPTR_EL2.TFP is set to allow - * access to the SIMD, floating-point and SVE support. - * - * CPTR_EL2.TZ: Set to 0 to enable access to SVE support - * for EL2 and Non-secure EL1 and EL0. - */ - cptr = read_cptr_el2(); - cptr &= ~(CPTR_EL2_TZ_BIT); - write_cptr_el2(cptr); + /* Enable access to SVE functionality for all ELs. */ + cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); + write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3); - /* - * Ensure lower ELs have access to full vector length. - */ - write_zcr_el2(ZCR_EL2_LEN_MASK); - } - /* - * No explicit ISB required here as ERET to switch to - * Non-secure world covers it. - */ + /* Restrict maximum SVE vector length (SVE_VECTOR_LENGTH+1) * 128. */ + write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3, + (ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(512))); } - -SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook); -SUBSCRIBE_TO_EVENT(cm_entering_normal_world, enable_sve_hook); -- cgit v1.2.3 From 33e3e925415f36f81b593dc269d203ad2165e13e Mon Sep 17 00:00:00 2001 From: johpow01 Date: Mon, 3 May 2021 15:33:39 -0500 Subject: errata: workaround for Neoverse V1 errata 1791573 Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and r1p0 of the V1 processor core. It is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10 --- lib/cpus/aarch64/neoverse_v1.S | 47 +++++++++++++++++++++++++++++++++++++++++- lib/cpus/cpu-ops.mk | 8 +++++++ 2 files changed, 54 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 733629425..d461b10c4 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -21,6 +21,34 @@ #error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #1791573. + * This applies to revisions r0p0 and r1p0, fixed in r1p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_1791573_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1791573 + cbz x0, 1f + + /* Set bit 2 in ACTLR2_EL1 */ + mrs x1, NEOVERSE_V1_ACTLR2_EL1 + orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 + msr NEOVERSE_V1_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_neoverse_v1_1791573_wa + +func check_errata_1791573 + /* Applies to r0p0 and r1p0. */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1791573 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -42,6 +70,18 @@ endfunc neoverse_v1_core_pwr_dwn */ #if REPORT_ERRATA func neoverse_v1_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 + + ldp x8, x30, [sp], #16 ret endfunc neoverse_v1_errata_report #endif @@ -51,8 +91,13 @@ func neoverse_v1_reset_func /* Disable speculative loads */ msr SSBS, xzr - isb + +#if ERRATA_V1_1791573 + mov x0, x18 + bl errata_neoverse_v1_1791573_wa +#endif + ret x19 endfunc neoverse_v1_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b1747af9a..b34fed64a 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -372,6 +372,10 @@ ERRATA_N1_1868343 ?=0 # exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround. ERRATA_N1_1946160 ?=0 +# Flag to apply erratum 1791573 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. +ERRATA_V1_1791573 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -677,6 +681,10 @@ $(eval $(call add_define,ERRATA_N1_1868343)) $(eval $(call assert_boolean,ERRATA_N1_1946160)) $(eval $(call add_define,ERRATA_N1_1946160)) +# Process ERRATA_V1_1791573 flag +$(eval $(call assert_boolean,ERRATA_V1_1791573)) +$(eval $(call add_define,ERRATA_V1_1791573)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 182ce1015583ad05462f58ec0e0651529341b990 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Wed, 7 Oct 2020 16:38:37 -0500 Subject: errata: workaround for Neoverse V1 errata 1940577 Neoverse V1 erratum 1940577 is a Cat B erratum, present in some revisions of the V1 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r1p1 but this workaround only applies to revisions r1p0 - r1p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell Change-Id: I210ad7d8f31c81b6ac51b028dfbce75a725c11aa --- lib/cpus/aarch64/neoverse_v1.S | 61 ++++++++++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++ 2 files changed, 69 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index d461b10c4..cee0bb733 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -49,6 +49,61 @@ func check_errata_1791573 b cpu_rev_var_ls endfunc check_errata_1791573 + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Erratum #1940577 + * This applies to revisions r1p0 - r1p1 and is open. + * It also exists in r0p0 but there is no fix in that + * revision. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_1940577_wa + /* Compare x0 against revisions r1p0 - r1p1 */ + mov x17, x30 + bl check_errata_1940577 + cbz x0, 1f + + mov x0, #0 + msr S3_6_C15_C8_0, x0 + ldr x0, =0x10E3900002 + msr S3_6_C15_C8_2, x0 + ldr x0, =0x10FFF00083 + msr S3_6_C15_C8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_C15_C8_1, x0 + + mov x0, #1 + msr S3_6_C15_C8_0, x0 + ldr x0, =0x10E3800082 + msr S3_6_C15_C8_2, x0 + ldr x0, =0x10FFF00083 + msr S3_6_C15_C8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_C15_C8_1, x0 + + mov x0, #2 + msr S3_6_C15_C8_0, x0 + ldr x0, =0x10E3800200 + msr S3_6_C15_C8_2, x0 + ldr x0, =0x10FFF003E0 + msr S3_6_C15_C8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_C15_C8_1, x0 + + isb +1: + ret x17 +endfunc errata_neoverse_v1_1940577_wa + +func check_errata_1940577 + /* Applies to revisions r1p0 - r1p1. */ + mov x1, #0x10 + mov x2, #0x11 + b cpu_rev_var_range +endfunc check_errata_1940577 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -80,6 +135,7 @@ func neoverse_v1_errata_report * checking functions of each errata. */ report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 + report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 ldp x8, x30, [sp], #16 ret @@ -98,6 +154,11 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_1791573_wa #endif +#if ERRATA_V1_1940577 + mov x0, x18 + bl errata_neoverse_v1_1940577_wa +#endif + ret x19 endfunc neoverse_v1_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b34fed64a..6f80d2d4f 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -376,6 +376,10 @@ ERRATA_N1_1946160 ?=0 # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1791573 ?=0 +# Flag to apply erratum 1940577 workaround during reset. This erratum applies +# to revisions r1p0 and r1p1 of the Neoverse V1 cpu. +ERRATA_V1_1940577 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -685,6 +689,10 @@ $(eval $(call add_define,ERRATA_N1_1946160)) $(eval $(call assert_boolean,ERRATA_V1_1791573)) $(eval $(call add_define,ERRATA_V1_1791573)) +# Process ERRATA_V1_1940577 flag +$(eval $(call assert_boolean,ERRATA_V1_1940577)) +$(eval $(call add_define,ERRATA_V1_1940577)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 68ac5ed0493b24e6a0a178171a47db75a31cc423 Mon Sep 17 00:00:00 2001 From: Arunachalam Ganapathy Date: Thu, 8 Jul 2021 09:35:57 +0100 Subject: fix(el3_runtime): fix SVE and AMU extension enablement flags If SVE are enabled for both Non-secure and Secure world along with AMU extension, then it causes the TAM_BIT in CPTR_EL3 to be set upon exit from bl31. This restricts access to the AMU register set in normal world. This fix maintains consistency in both TAM_BIT and CPTR_EZ_BIT by saving and restoring CPTR_EL3 register from EL3 context. Signed-off-by: Arunachalam Ganapathy Change-Id: Id76ce1d27ee48bed65eb32392036377716aff087 --- lib/el3_runtime/aarch64/context.S | 7 +------ lib/el3_runtime/aarch64/context_mgmt.c | 37 ++++++++++++++++++++++------------ lib/extensions/amu/aarch64/amu.c | 9 +++++---- lib/extensions/sve/sve.c | 4 +++- 4 files changed, 33 insertions(+), 24 deletions(-) (limited to 'lib') diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index d610fd492..40e7ddfa1 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -903,16 +903,11 @@ func el3_exit #if IMAGE_BL31 /* ---------------------------------------------------------- - * Restore CPTR_EL3, ZCR_EL3 for SVE support. - * If SVE is not supported - skip the restoration. + * Restore CPTR_EL3. * ZCR is only restored if SVE is supported and enabled. * Synchronization is required before zcr_el3 is addressed. * ---------------------------------------------------------- */ - mrs x17, id_aa64pfr0_el1 - ubfx x17, x17, ID_AA64PFR0_SVE_SHIFT, ID_AA64PFR0_SVE_LENGTH - cbz x17, sve_not_enabled - ldp x19, x20, [sp, #CTX_EL3STATE_OFFSET + CTX_CPTR_EL3] msr cptr_el3, x19 diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c index 7a25151c5..7c6f953b2 100644 --- a/lib/el3_runtime/aarch64/context_mgmt.c +++ b/lib/el3_runtime/aarch64/context_mgmt.c @@ -25,6 +25,7 @@ #include #include +static void enable_extensions_secure(cpu_context_t *ctx); /******************************************************************************* * Context management library initialisation routine. This library is used by @@ -178,19 +179,13 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * indicated by the interrupt routing model for BL31. */ scr_el3 |= get_scr_el3_from_routing_model(security_state); - -#if ENABLE_SVE_FOR_NS - if (security_state == NON_SECURE) { - sve_enable(ctx); - } #endif -#if ENABLE_SVE_FOR_SWD + + /* Save the initialized value of CPTR_EL3 register */ + write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, read_cptr_el3()); if (security_state == SECURE) { - sve_enable(ctx); + enable_extensions_secure(ctx); } -#endif - -#endif /* * SCR_EL3.HCE: Enable HVC instructions if next execution state is @@ -335,7 +330,7 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep) * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise * it is zero. ******************************************************************************/ -static void enable_extensions_nonsecure(bool el2_unused) +static void enable_extensions_nonsecure(bool el2_unused, cpu_context_t *ctx) { #if IMAGE_BL31 #if ENABLE_SPE_FOR_LOWER_ELS @@ -343,7 +338,11 @@ static void enable_extensions_nonsecure(bool el2_unused) #endif #if ENABLE_AMU - amu_enable(el2_unused); + amu_enable(el2_unused, ctx); +#endif + +#if ENABLE_SVE_FOR_NS + sve_enable(ctx); #endif #if ENABLE_MPAM_FOR_LOWER_ELS @@ -352,6 +351,18 @@ static void enable_extensions_nonsecure(bool el2_unused) #endif } +/******************************************************************************* + * Enable architecture extensions on first entry to Secure world. + ******************************************************************************/ +static void enable_extensions_secure(cpu_context_t *ctx) +{ +#if IMAGE_BL31 +#if ENABLE_SVE_FOR_SWD + sve_enable(ctx); +#endif +#endif +} + /******************************************************************************* * The following function initializes the cpu_context for a CPU specified by * its `cpu_idx` for first use, and sets the initial entrypoint state as @@ -586,7 +597,7 @@ void cm_prepare_el3_exit(uint32_t security_state) write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL & ~(CNTHP_CTL_ENABLE_BIT)); } - enable_extensions_nonsecure(el2_unused); + enable_extensions_nonsecure(el2_unused, ctx); } cm_el1_sysregs_context_restore(security_state); diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c index 24c3737b7..295c0d569 100644 --- a/lib/extensions/amu/aarch64/amu.c +++ b/lib/extensions/amu/aarch64/amu.c @@ -46,7 +46,7 @@ bool amu_group1_supported(void) * Enable counters. This function is meant to be invoked * by the context management library before exiting from EL3. */ -void amu_enable(bool el2_unused) +void amu_enable(bool el2_unused, cpu_context_t *ctx) { uint64_t v; unsigned int amu_version = amu_get_version(); @@ -88,12 +88,13 @@ void amu_enable(bool el2_unused) } /* - * CPTR_EL3.TAM: Set to zero so that any accesses to + * Retrieve and update the CPTR_EL3 value from the context mentioned + * in 'ctx'. Set CPTR_EL3.TAM to zero so that any accesses to * the Activity Monitor registers do not trap to EL3. */ - v = read_cptr_el3(); + v = read_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3); v &= ~TAM_BIT; - write_cptr_el3(v); + write_ctx_reg(get_el3state_ctx(ctx), CTX_CPTR_EL3, v); /* Enable group 0 counters */ write_amcntenset0_el0(AMU_GROUP0_COUNTERS_MASK); diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c index 7043cc220..2702c30f3 100644 --- a/lib/extensions/sve/sve.c +++ b/lib/extensions/sve/sve.c @@ -27,11 +27,13 @@ static bool sve_supported(void) void sve_enable(cpu_context_t *context) { + u_register_t cptr_el3; + if (!sve_supported()) { return; } - u_register_t cptr_el3 = read_cptr_el3(); + cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3); /* Enable access to SVE functionality for all ELs. */ cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT); -- cgit v1.2.3 From f21693704a7bac275e12b44ae30fd210bc317175 Mon Sep 17 00:00:00 2001 From: Manish V Badarkhe Date: Fri, 2 Jul 2021 20:18:57 +0100 Subject: feat(sw_crc32): add software CRC32 support Added software CRC32 support in case platform doesn't support hardware CRC32. Platform must include necessary Zlib source files for compilation to use software CRC32 implementation. Change-Id: Iecb649b2edf951944b1a7e4c250c40fe7a3bde25 Signed-off-by: Manish V Badarkhe --- lib/zlib/tf_gunzip.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/zlib/tf_gunzip.c b/lib/zlib/tf_gunzip.c index fd56dfc7c..3ac80bc5b 100644 --- a/lib/zlib/tf_gunzip.c +++ b/lib/zlib/tf_gunzip.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2018-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,6 +9,7 @@ #include #include +#include #include #include @@ -100,3 +101,15 @@ int gunzip(uintptr_t *in_buf, size_t in_len, uintptr_t *out_buf, return ret; } + +/* Wrapper function to calculate CRC + * @crc: previous accumulated CRC + * @buf: buffer base address + * @size: size of the buffer + * + * Return calculated CRC32 value + */ +uint32_t tf_crc32(uint32_t crc, const unsigned char *buf, size_t size) +{ + return (uint32_t)crc32((unsigned long)crc, buf, size); +} -- cgit v1.2.3 From 4789cf66af0560900b088e03968bc2fc83d1f330 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Mon, 2 Aug 2021 13:22:32 -0500 Subject: errata: workaround for Neoverse V1 errata 1774420 Neoverse V1 erratum 1774420 is a Cat B erratum present in r0p0 and r1p0 of the V1 processor core. It is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: Lauren Wehrmeister Change-Id: I66e27b2518f73faeedd8615a1443a74b6a30f123 --- lib/cpus/aarch64/neoverse_v1.S | 40 +++++++++++++++++++++++++++++++++++++--- lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 45 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index cee0bb733..62b92b2c3 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2021, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,6 +21,34 @@ #error "Neoverse-V1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #1774420. + * This applies to revisions r0p0 and r1p0, fixed in r1p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_1774420_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1774420 + cbz x0, 1f + + /* Set bit 53 in CPUECTLR_EL1 */ + mrs x1, NEOVERSE_V1_CPUECTLR_EL1 + orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53 + msr NEOVERSE_V1_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_neoverse_v1_1774420_wa + +func check_errata_1774420 + /* Applies to r0p0 and r1p0. */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1774420 + /* -------------------------------------------------- * Errata Workaround for Neoverse V1 Errata #1791573. * This applies to revisions r0p0 and r1p0, fixed in r1p1. @@ -35,9 +63,9 @@ func errata_neoverse_v1_1791573_wa cbz x0, 1f /* Set bit 2 in ACTLR2_EL1 */ - mrs x1, NEOVERSE_V1_ACTLR2_EL1 + mrs x1, NEOVERSE_V1_ACTLR2_EL1 orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2 - msr NEOVERSE_V1_ACTLR2_EL1, x1 + msr NEOVERSE_V1_ACTLR2_EL1, x1 isb 1: ret x17 @@ -134,6 +162,7 @@ func neoverse_v1_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 @@ -149,6 +178,11 @@ func neoverse_v1_reset_func msr SSBS, xzr isb +#if ERRATA_V1_1774420 + mov x0, x18 + bl errata_neoverse_v1_1774420_wa +#endif + #if ERRATA_V1_1791573 mov x0, x18 bl errata_neoverse_v1_1791573_wa diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 6f80d2d4f..3de013935 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -372,6 +372,10 @@ ERRATA_N1_1868343 ?=0 # exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround. ERRATA_N1_1946160 ?=0 +# Flag to apply erratum 1774420 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. +ERRATA_V1_1774420 ?=0 + # Flag to apply erratum 1791573 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1791573 ?=0 @@ -685,6 +689,10 @@ $(eval $(call add_define,ERRATA_N1_1868343)) $(eval $(call assert_boolean,ERRATA_N1_1946160)) $(eval $(call add_define,ERRATA_N1_1946160)) +# Process ERRATA_V1_1774420 flag +$(eval $(call assert_boolean,ERRATA_V1_1774420)) +$(eval $(call add_define,ERRATA_V1_1774420)) + # Process ERRATA_V1_1791573 flag $(eval $(call assert_boolean,ERRATA_V1_1791573)) $(eval $(call add_define,ERRATA_V1_1791573)) -- cgit v1.2.3 From 143b19651bd7f4ff00757436fcd768b20aaf3eb7 Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Mon, 2 Aug 2021 14:40:08 -0500 Subject: errata: workaround for Neoverse V1 errata 1852267 Neoverse V1 erratum 1852267 is a Cat B erratum present in r0p0 and r1p0 of the V1 processor core. It is fixed in r1p1. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: Lauren Wehrmeister Change-Id: Ide5e0bc09371fbc91c2385ffdff74e604beb2dbe --- lib/cpus/aarch64/neoverse_v1.S | 34 ++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 42 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 62b92b2c3..38e9d3f92 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -77,6 +77,34 @@ func check_errata_1791573 b cpu_rev_var_ls endfunc check_errata_1791573 + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #1852267. + * This applies to revisions r0p0 and r1p0, fixed in r1p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_1852267_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1852267 + cbz x0, 1f + + /* Set bit 28 in ACTLR2_EL1 */ + mrs x1, NEOVERSE_V1_ACTLR2_EL1 + orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28 + msr NEOVERSE_V1_ACTLR2_EL1, x1 + isb +1: + ret x17 +endfunc errata_neoverse_v1_1852267_wa + +func check_errata_1852267 + /* Applies to r0p0 and r1p0. */ + mov x1, #0x10 + b cpu_rev_var_ls +endfunc check_errata_1852267 + /* -------------------------------------------------- * Errata Workaround for Neoverse V1 Erratum #1940577 * This applies to revisions r1p0 - r1p1 and is open. @@ -164,6 +192,7 @@ func neoverse_v1_errata_report */ report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 + report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 ldp x8, x30, [sp], #16 @@ -188,6 +217,11 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_1791573_wa #endif +#if ERRATA_V1_1852267 + mov x0, x18 + bl errata_neoverse_v1_1852267_wa +#endif + #if ERRATA_V1_1940577 mov x0, x18 bl errata_neoverse_v1_1940577_wa diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 3de013935..92a7f7505 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -380,6 +380,10 @@ ERRATA_V1_1774420 ?=0 # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1791573 ?=0 +# Flag to apply erratum 1852267 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. +ERRATA_V1_1852267 ?=0 + # Flag to apply erratum 1940577 workaround during reset. This erratum applies # to revisions r1p0 and r1p1 of the Neoverse V1 cpu. ERRATA_V1_1940577 ?=0 @@ -697,6 +701,10 @@ $(eval $(call add_define,ERRATA_V1_1774420)) $(eval $(call assert_boolean,ERRATA_V1_1791573)) $(eval $(call add_define,ERRATA_V1_1791573)) +# Process ERRATA_V1_1852267 flag +$(eval $(call assert_boolean,ERRATA_V1_1852267)) +$(eval $(call add_define,ERRATA_V1_1852267)) + # Process ERRATA_V1_1940577 flag $(eval $(call assert_boolean,ERRATA_V1_1940577)) $(eval $(call add_define,ERRATA_V1_1940577)) -- cgit v1.2.3 From 741dd04c812f0bd3015f8e934cb9da84e068040e Mon Sep 17 00:00:00 2001 From: laurenw-arm Date: Mon, 2 Aug 2021 15:00:15 -0500 Subject: errata: workaround for Neoverse V1 errata 1925756 Neoverse V1 erratum 1925756 is a Cat B erratum present in r0p0, r1p0, and r1p1 of the V1 processor core, and it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: Lauren Wehrmeister Change-Id: I6500dc98da92a7c405b9ae09d794d666e8f4ae52 --- lib/cpus/aarch64/neoverse_v1.S | 34 ++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 42 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 38e9d3f92..2e088a128 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -105,6 +105,34 @@ func check_errata_1852267 b cpu_rev_var_ls endfunc check_errata_1852267 + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #1925756. + * This applies to revisions <= r1p1. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_1925756_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1925756 + cbz x0, 1f + + /* Set bit 8 in CPUECTLR_EL1 */ + mrs x1, NEOVERSE_V1_CPUECTLR_EL1 + orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8 + msr NEOVERSE_V1_CPUECTLR_EL1, x1 + isb +1: + ret x17 +endfunc errata_neoverse_v1_1925756_wa + +func check_errata_1925756 + /* Applies to <= r1p1. */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_1925756 + /* -------------------------------------------------- * Errata Workaround for Neoverse V1 Erratum #1940577 * This applies to revisions r1p0 - r1p1 and is open. @@ -193,6 +221,7 @@ func neoverse_v1_errata_report report_errata ERRATA_V1_1774420, neoverse_v1, 1774420 report_errata ERRATA_V1_1791573, neoverse_v1, 1791573 report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 + report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 ldp x8, x30, [sp], #16 @@ -222,6 +251,11 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_1852267_wa #endif +#if ERRATA_V1_1925756 + mov x0, x18 + bl errata_neoverse_v1_1925756_wa +#endif + #if ERRATA_V1_1940577 mov x0, x18 bl errata_neoverse_v1_1940577_wa diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 92a7f7505..f48293274 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -384,6 +384,10 @@ ERRATA_V1_1791573 ?=0 # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1852267 ?=0 +# Flag to apply erratum 1925756 workaround during reset. This needs to be +# enabled for r0p0, r1p0, and r1p1 of the Neoverse V1 core, it is still open. +ERRATA_V1_1925756 ?=0 + # Flag to apply erratum 1940577 workaround during reset. This erratum applies # to revisions r1p0 and r1p1 of the Neoverse V1 cpu. ERRATA_V1_1940577 ?=0 @@ -705,6 +709,10 @@ $(eval $(call add_define,ERRATA_V1_1791573)) $(eval $(call assert_boolean,ERRATA_V1_1852267)) $(eval $(call add_define,ERRATA_V1_1852267)) +# Process ERRATA_V1_1925756 flag +$(eval $(call assert_boolean,ERRATA_V1_1925756)) +$(eval $(call add_define,ERRATA_V1_1925756)) + # Process ERRATA_V1_1940577 flag $(eval $(call assert_boolean,ERRATA_V1_1940577)) $(eval $(call add_define,ERRATA_V1_1940577)) -- cgit v1.2.3 From 1a8804c3834966f8177eb9211bb24f546420ba9b Mon Sep 17 00:00:00 2001 From: johpow01 Date: Mon, 2 Aug 2021 18:59:08 -0500 Subject: errata: workaround for Neoverse V1 errata 1966096 Neoverse V1 erratum 1966096 is a Cat B erratum present in the V1 processor core. This issue is present in revisions r0p0, r1p0, and r1p1, but the workaround only applies to r1p0 and r1p1, it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell Change-Id: Ic0b9a931e38da8a7000648e221481e17c253563b --- lib/cpus/aarch64/neoverse_v1.S | 44 +++++++++++++++++++++++++++++++++++++++++- lib/cpus/cpu-ops.mk | 9 +++++++++ 2 files changed, 52 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 2e088a128..f20202739 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021, ARM Limited. All rights reserved. + * Copyright (c) 2019-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -188,6 +188,42 @@ func check_errata_1940577 b cpu_rev_var_range endfunc check_errata_1940577 + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #1966096 + * This applies to revisions r1p0 - r1p1 and is open. + * It also exists in r0p0 but there is no workaround + * for that revision. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_1966096_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_1966096 + cbz x0, 1f + + /* Apply the workaround. */ + mov x0, #0x3 + msr S3_6_C15_C8_0, x0 + ldr x0, =0xEE010F12 + msr S3_6_C15_C8_2, x0 + ldr x0, =0xFFFF0FFF + msr S3_6_C15_C8_3, x0 + ldr x0, =0x80000000003FF + msr S3_6_C15_C8_1, x0 + isb + +1: + ret x17 +endfunc errata_neoverse_v1_1966096_wa + +func check_errata_1966096 + mov x1, #0x10 + mov x2, #0x11 + b cpu_rev_var_range +endfunc check_errata_1966096 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -223,6 +259,7 @@ func neoverse_v1_errata_report report_errata ERRATA_V1_1852267, neoverse_v1, 1852267 report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 + report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 ldp x8, x30, [sp], #16 ret @@ -261,6 +298,11 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_1940577_wa #endif +#if ERRATA_V1_1966096 + mov x0, x18 + bl errata_neoverse_v1_1966096_wa +#endif + ret x19 endfunc neoverse_v1_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index f48293274..4677f914c 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -392,6 +392,11 @@ ERRATA_V1_1925756 ?=0 # to revisions r1p0 and r1p1 of the Neoverse V1 cpu. ERRATA_V1_1940577 ?=0 +# Flag to apply erratum 1966096 workaround during reset. This erratum applies +# to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open. This issue +# exists in r0p0 as well but there is no workaround for that revision. +ERRATA_V1_1966096 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -717,6 +722,10 @@ $(eval $(call add_define,ERRATA_V1_1925756)) $(eval $(call assert_boolean,ERRATA_V1_1940577)) $(eval $(call add_define,ERRATA_V1_1940577)) +# Process ERRATA_V1_1966096 flag +$(eval $(call assert_boolean,ERRATA_V1_1966096)) +$(eval $(call add_define,ERRATA_V1_1966096)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 100d4029a926a7d0df28072d9674787c09e37d85 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Tue, 3 Aug 2021 14:35:20 -0500 Subject: errata: workaround for Neoverse V1 errata 2139242 Neoverse V1 erratum 2139242 is a Cat B erratum present in the V1 processor core. This issue is present in revisions r0p0, r1p0, and r1p1, and it is still open. SDEN can be found here: https://documentation-service.arm.com/static/60d499080320e92fa40b4625 Signed-off-by: John Powell Change-Id: I5c2e9beec72a64ac4131fb6dd76199821a934ebe --- lib/cpus/aarch64/neoverse_v1.S | 41 +++++++++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 49 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index f20202739..0bcf52a78 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -224,6 +224,41 @@ func check_errata_1966096 b cpu_rev_var_range endfunc check_errata_1966096 + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #2139242. + * This applies to revisions r0p0, r1p0, and r1p1, it + * is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_2139242_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2139242 + cbz x0, 1f + + /* Apply the workaround. */ + mov x0, #0x3 + msr S3_6_C15_C8_0, x0 + ldr x0, =0xEE720F14 + msr S3_6_C15_C8_2, x0 + ldr x0, =0xFFFF0FDF + msr S3_6_C15_C8_3, x0 + ldr x0, =0x40000005003FF + msr S3_6_C15_C8_1, x0 + isb + +1: + ret x17 +endfunc errata_neoverse_v1_2139242_wa + +func check_errata_2139242 + /* Applies to r0p0, r1p0, r1p1 */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2139242 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -260,6 +295,7 @@ func neoverse_v1_errata_report report_errata ERRATA_V1_1925756, neoverse_v1, 1925756 report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 + report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 ldp x8, x30, [sp], #16 ret @@ -303,6 +339,11 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_1966096_wa #endif +#if ERRATA_V1_2139242 + mov x0, x18 + bl errata_neoverse_v1_2139242_wa +#endif + ret x19 endfunc neoverse_v1_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 4677f914c..050a56e4f 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -397,6 +397,10 @@ ERRATA_V1_1940577 ?=0 # exists in r0p0 as well but there is no workaround for that revision. ERRATA_V1_1966096 ?=0 +# Flag to apply erratum 2139242 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. +ERRATA_V1_2139242 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -726,6 +730,10 @@ $(eval $(call add_define,ERRATA_V1_1940577)) $(eval $(call assert_boolean,ERRATA_V1_1966096)) $(eval $(call add_define,ERRATA_V1_1966096)) +# Process ERRATA_V1_2139242 flag +$(eval $(call assert_boolean,ERRATA_V1_2139242)) +$(eval $(call add_define,ERRATA_V1_2139242)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 8913047a52e646877812617a2d98cff99494487b Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 27 Jul 2021 00:39:40 -0700 Subject: feat(cpus): workaround for Cortex A78 AE erratum 1951502 Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions <= r0p1. It is still open. This erratum is avoided by inserting a DMB ST before acquire atomic instructions without release semantics through a series of writes to implementation defined system registers. SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900 Change-Id: I812c5a37cdd03486df8af6046d9fa988f6a0a098 Signed-off-by: Varun Wadekar --- lib/cpus/aarch64/cortex_a78_ae.S | 89 +++++++++++++++++++++++++++++++++++----- lib/cpus/cpu-ops.mk | 10 ++++- 2 files changed, 88 insertions(+), 11 deletions(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index 9aff9ac85..c8cccf278 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -1,5 +1,6 @@ /* * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,12 +17,73 @@ #error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* -------------------------------------------------- + * Errata Workaround for A78 AE Erratum 1951502. + * This applies to revisions r0p0 and r0p1 of A78 AE. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78_ae_1951502_wa + /* Compare x0 against revisions r0p0 - r0p1 */ + mov x17, x30 + bl check_errata_1951502 + cbz x0, 1f + + msr S3_6_c15_c8_0, xzr + ldr x0, =0x10E3900002 + msr S3_6_c15_c8_2, x0 + ldr x0, =0x10FFF00083 + msr S3_6_c15_c8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_c15_c8_1, x0 + + mov x0, #1 + msr S3_6_c15_c8_0, x0 + ldr x0, =0x10E3800082 + msr S3_6_c15_c8_2, x0 + ldr x0, =0x10FFF00083 + msr S3_6_c15_c8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_c15_c8_1, x0 + + mov x0, #2 + msr S3_6_c15_c8_0, x0 + ldr x0, =0x10E3800200 + msr S3_6_c15_c8_2, x0 + ldr x0, =0x10FFF003E0 + msr S3_6_c15_c8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_c15_c8_1, x0 + + isb +1: + ret x17 +endfunc errata_a78_ae_1951502_wa + +func check_errata_1951502 + /* Applies to revisions r0p0 and r0p1. */ + mov x1, #CPU_REV(0, 0) + mov x2, #CPU_REV(0, 1) + b cpu_rev_var_range +endfunc check_errata_1951502 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A78-AE * ------------------------------------------------- */ -#if ENABLE_AMU func cortex_a78_ae_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A78_AE_1951502 + mov x0, x18 + bl errata_a78_ae_1951502_wa +#endif + +#if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT @@ -39,11 +101,12 @@ func cortex_a78_ae_reset_func /* Enable group1 counters */ mov x0, #CORTEX_A78_AMU_GROUP1_MASK msr CPUAMCNTENSET1_EL0, x0 +#endif + isb - ret + ret x19 endfunc cortex_a78_ae_reset_func -#endif /* ------------------------------------------------------- * HW will do the cache maintenance while powering down @@ -66,6 +129,18 @@ endfunc cortex_a78_ae_core_pwr_dwn */ #if REPORT_ERRATA func cortex_a78_ae_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502 + + ldp x8, x30, [sp], #16 ret endfunc cortex_a78_ae_errata_report #endif @@ -89,12 +164,6 @@ func cortex_a78_ae_cpu_reg_dump ret endfunc cortex_a78_ae_cpu_reg_dump -#if ENABLE_AMU -#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func -#else -#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC -#endif - declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ - A78_AE_RESET_FUNC, \ + cortex_a78_ae_reset_func, \ cortex_a78_ae_core_pwr_dwn diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 050a56e4f..b36616760 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,6 +1,6 @@ # # Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. -# Copyright (c) 2020, NVIDIA Corporation. All rights reserved. +# Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -311,6 +311,10 @@ ERRATA_A78_1941498 ?=0 # well but there is no workaround for that revision. ERRATA_A78_1951500 ?=0 +# Flag to apply erratum 1951502 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. +ERRATA_A78_AE_1951502 ?=0 + # Flag to apply erratum 1821534 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the A78 cpu. ERRATA_A78_1821534 ?=0 @@ -646,6 +650,10 @@ $(eval $(call add_define,ERRATA_A78_1941498)) $(eval $(call assert_boolean,ERRATA_A78_1951500)) $(eval $(call add_define,ERRATA_A78_1951500)) +# Process ERRATA_A78_AE_1951502 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_1951502)) +$(eval $(call add_define,ERRATA_A78_AE_1951502)) + # Process ERRATA_A78_1821534 flag $(eval $(call assert_boolean,ERRATA_A78_1821534)) $(eval $(call add_define,ERRATA_A78_1821534)) -- cgit v1.2.3 From f4616efafbc1004f1330f515b898e7617e338875 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Wed, 7 Jul 2021 17:06:07 -0500 Subject: cpu: add support for Demeter CPU This patch adds the basic CPU library code to support the Demeter CPU. This CPU is based on the Makalu-ELP core so that CPU lib code was adapted to create this patch. Signed-off-by: John Powell Change-Id: Ib5740b748008a72788c557f0654d8d5e9ec0bb7f --- lib/cpus/aarch64/cortex_demeter.S | 77 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 lib/cpus/aarch64/cortex_demeter.S (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_demeter.S b/lib/cpus/aarch64/cortex_demeter.S new file mode 100644 index 000000000..9ad8b86fd --- /dev/null +++ b/lib/cpus/aarch64/cortex_demeter.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include +#include +#include +#include +#include +#include + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Demeter must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_demeter_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_DEMETER_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_DEMETER_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_demeter_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Demeter. Must follow AAPCS. + */ +func cortex_demeter_errata_report + ret +endfunc cortex_demeter_errata_report +#endif + +func cortex_demeter_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_demeter_reset_func + + /* --------------------------------------------- + * This function provides Cortex Demeter- + * specific register information for crash + * reporting. It needs to return with x6 + * pointing to a list of register names in ascii + * and x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_demeter_regs, "aS" +cortex_demeter_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_demeter_cpu_reg_dump + adr x6, cortex_demeter_regs + mrs x8, CORTEX_DEMETER_CPUECTLR_EL1 + ret +endfunc cortex_demeter_cpu_reg_dump + +declare_cpu_ops cortex_demeter, CORTEX_DEMETER_MIDR, \ + cortex_demeter_reset_func, \ + cortex_demeter_core_pwr_dwn -- cgit v1.2.3 From 47d6f5ff16d1f2ad009d630a381054b10fa0a06f Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 27 Jul 2021 02:32:29 -0700 Subject: feat(cpus): workaround for Cortex A78 AE erratum 1941500 Cortex A78 AE erratum 1941500 is a Cat B erratum that applies to revisions <= r0p1. It is still open. This erratum is avoided by by setting CPUECTLR_EL1[8] to 1. There is a small performance cost (<0.5%) for setting this bit. SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900 Change-Id: I2d72666468b146714a0340ba114ccf0f5165b39c Signed-off-by: Varun Wadekar --- lib/cpus/aarch64/cortex_a78_ae.S | 36 ++++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 44 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index c8cccf278..421c17433 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -17,6 +17,36 @@ #error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* -------------------------------------------------- + * Errata Workaround for A78 AE Erratum 1941500. + * This applies to revisions r0p0 and r0p1 of A78 AE. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78_ae_1941500_wa + /* Compare x0 against revisions r0p0 - r0p1 */ + mov x17, x30 + bl check_errata_1941500 + cbz x0, 1f + + /* Set bit 8 in ECTLR_EL1 */ + mrs x0, CORTEX_A78_AE_CPUECTLR_EL1 + bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 + msr CORTEX_A78_AE_CPUECTLR_EL1, x0 + isb +1: + ret x17 +endfunc errata_a78_ae_1941500_wa + +func check_errata_1941500 + /* Applies to revisions r0p0 and r0p1. */ + mov x1, #CPU_REV(0, 0) + mov x2, #CPU_REV(0, 1) + b cpu_rev_var_range +endfunc check_errata_1941500 + /* -------------------------------------------------- * Errata Workaround for A78 AE Erratum 1951502. * This applies to revisions r0p0 and r0p1 of A78 AE. @@ -78,6 +108,11 @@ func cortex_a78_ae_reset_func bl cpu_get_rev_var mov x18, x0 +#if ERRATA_A78_AE_1941500 + mov x0, x18 + bl errata_a78_ae_1941500_wa +#endif + #if ERRATA_A78_AE_1951502 mov x0, x18 bl errata_a78_ae_1951502_wa @@ -138,6 +173,7 @@ func cortex_a78_ae_errata_report * Report all errata. The revision-variant information is passed to * checking functions of each errata. */ + report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500 report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b36616760..e81471ec3 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -311,6 +311,10 @@ ERRATA_A78_1941498 ?=0 # well but there is no workaround for that revision. ERRATA_A78_1951500 ?=0 +# Flag to apply erratum 1941500 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. +ERRATA_A78_AE_1941500 ?=0 + # Flag to apply erratum 1951502 workaround during reset. This erratum applies # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_1951502 ?=0 @@ -650,6 +654,10 @@ $(eval $(call add_define,ERRATA_A78_1941498)) $(eval $(call assert_boolean,ERRATA_A78_1951500)) $(eval $(call add_define,ERRATA_A78_1951500)) +# Process ERRATA_A78_AE_1941500 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_1941500)) +$(eval $(call add_define,ERRATA_A78_AE_1941500)) + # Process ERRATA_A78_AE_1951502 flag $(eval $(call assert_boolean,ERRATA_A78_AE_1951502)) $(eval $(call add_define,ERRATA_A78_AE_1951502)) -- cgit v1.2.3 From 00bee997614f8a98737f4dc0a5ac9d96d2d28cf1 Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Wed, 11 Aug 2021 13:33:00 -0700 Subject: errata: workaround for Cortex-A78 errata 1952683 Cortex-A78 erratum 1952683 is a Cat B erratum present in r0p0 of the Cortex-A78 processor core, and it was fixed in r1p0. A78 SDEN : https://developer.arm.com/documentation/SDEN1401784/1400 Signed-off-by: nayanpatel-arm Change-Id: I77b03e695532cb13e8f8d3f00c43d973781ceeb0 --- lib/cpus/aarch64/cortex_a78.S | 50 +++++++++++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++++ 2 files changed, 58 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index 8c5a45a7b..3a74571f0 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -154,6 +154,50 @@ func check_errata_1821534 b cpu_rev_var_ls endfunc check_errata_1821534 +/* -------------------------------------------------- + * Errata Workaround for Cortex A78 Errata 1952683. + * This applies to revision r0p0. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78_1952683_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_1952683 + cbz x0, 1f + + ldr x0,=0x5 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xEEE10A10 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFEF0FFF + msr S3_6_c15_c8_3,x0 + ldr x0,=0x0010F000 + msr S3_6_c15_c8_4,x0 + ldr x0,=0x0010F000 + msr S3_6_c15_c8_5,x0 + ldr x0,=0x40000080023ff + msr S3_6_c15_c8_1,x0 + ldr x0,=0x6 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xEE640F34 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFEF0FFF + msr S3_6_c15_c8_3,x0 + ldr x0,=0x40000080023ff + msr S3_6_c15_c8_1,x0 + isb +1: + ret x17 +endfunc errata_a78_1952683_wa + +func check_errata_1952683 + /* Applies to r0p0 only */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_1952683 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A78 * ------------------------------------------------- @@ -183,6 +227,11 @@ func cortex_a78_reset_func bl errata_a78_1821534_wa #endif +#if ERRATA_A78_1952683 + mov x0, x18 + bl errata_a78_1952683_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -241,6 +290,7 @@ func cortex_a78_errata_report report_errata ERRATA_A78_1941498, cortex_a78, 1941498 report_errata ERRATA_A78_1951500, cortex_a78, 1951500 report_errata ERRATA_A78_1821534, cortex_a78, 1821534 + report_errata ERRATA_A78_1952683, cortex_a78, 1952683 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b36616760..717510388 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -319,6 +319,10 @@ ERRATA_A78_AE_1951502 ?=0 # to revisions r0p0 and r1p0 of the A78 cpu. ERRATA_A78_1821534 ?=0 +# Flag to apply erratum 1952683 workaround during reset. This erratum applies +# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0. +ERRATA_A78_1952683 ?=0 + # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=0 @@ -658,6 +662,10 @@ $(eval $(call add_define,ERRATA_A78_AE_1951502)) $(eval $(call assert_boolean,ERRATA_A78_1821534)) $(eval $(call add_define,ERRATA_A78_1821534)) +# Process ERRATA_A78_1952683 flag +$(eval $(call assert_boolean,ERRATA_A78_1952683)) +$(eval $(call add_define,ERRATA_A78_1952683)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) -- cgit v1.2.3 From fbcf54aeb970195ea2944cb7bbc704145ec8f07e Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Fri, 6 Aug 2021 16:39:48 -0700 Subject: errata: workaround for Cortex-A710 errata 1987031 Cortex-A710 erratum 1987031 is a Cat B erratum present in r0p0, r1p0, and r2p0 of the Cortex-A710 processor core, and it is still open. A710 SDEN: https://documentation-service.arm.com/static/61099dc59ebe3a7dbd3a8a88?token= Signed-off-by: nayanpatel-arm Change-Id: I9bcff306f82328ad5a0f6e9836020d23c07f7179 --- lib/cpus/aarch64/cortex_a710.S | 68 +++++++++++++++++++++++++++++++++++++++++- lib/cpus/cpu-ops.mk | 8 +++++ 2 files changed, 75 insertions(+), 1 deletion(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 4f979f8aa..39700350d 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -21,6 +21,49 @@ #error "Cortex A710 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +/* -------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 1987031. + * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. It is still + * open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a710_1987031_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_1987031 + cbz x0, 1f + + /* Apply instruction patching sequence */ + ldr x0,=0x6 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xF3A08002 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFF0F7FE + msr S3_6_c15_c8_3,x0 + ldr x0,=0x40000001003ff + msr S3_6_c15_c8_1,x0 + ldr x0,=0x7 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xBF200000 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFEF0000 + msr S3_6_c15_c8_3,x0 + ldr x0,=0x40000001003f3 + msr S3_6_c15_c8_1,x0 + isb +1: + ret x17 +endfunc errata_a710_1987031_wa + +func check_errata_1987031 + /* Applies to r0p0, r1p0 and r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_1987031 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -42,15 +85,38 @@ endfunc cortex_a710_core_pwr_dwn */ #if REPORT_ERRATA func cortex_a710_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A710_1987031, cortex_a710, 1987031 + + ldp x8, x30, [sp], #16 ret endfunc cortex_a710_errata_report #endif func cortex_a710_reset_func + mov x19, x30 + /* Disable speculative loads */ msr SSBS, xzr + + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A710_1987031 + mov x0, x18 + bl errata_a710_1987031_wa +#endif + isb - ret + ret x19 endfunc cortex_a710_reset_func /* --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b36616760..ed507c856 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -405,6 +405,10 @@ ERRATA_V1_1966096 ?=0 # to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. ERRATA_V1_2139242 ?=0 +# Flag to apply erratum 1987031 workaround during reset. This erratum applies +# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_1987031 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -742,6 +746,10 @@ $(eval $(call add_define,ERRATA_V1_1966096)) $(eval $(call assert_boolean,ERRATA_V1_2139242)) $(eval $(call add_define,ERRATA_V1_2139242)) +# Process ERRATA_A710_1987031 flag +$(eval $(call assert_boolean,ERRATA_A710_1987031)) +$(eval $(call add_define,ERRATA_A710_1987031)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From a64bcc2b4528962a3b11ac3798e36e52dca2787f Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Wed, 25 Aug 2021 17:35:15 -0700 Subject: errata: workaround for Cortex-A710 errata 2081180 Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0, and r2p0 of the Cortex-A710 processor core, and it is still open. A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000 Signed-off-by: nayanpatel-arm Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542 --- lib/cpus/aarch64/cortex_a710.S | 49 ++++++++++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++++ 2 files changed, 57 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 39700350d..469b430a9 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -64,6 +64,49 @@ func check_errata_1987031 b cpu_rev_var_ls endfunc check_errata_1987031 +/* -------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2081180. + * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. + * It is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a710_2081180_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2081180 + cbz x0, 1f + + /* Apply instruction patching sequence */ + ldr x0,=0x3 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xF3A08002 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFF0F7FE + msr S3_6_c15_c8_3,x0 + ldr x0,=0x10002001003FF + msr S3_6_c15_c8_1,x0 + ldr x0,=0x4 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xBF200000 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFEF0000 + msr S3_6_c15_c8_3,x0 + ldr x0,=0x10002001003F3 + msr S3_6_c15_c8_1,x0 + isb +1: + ret x17 +endfunc errata_a710_2081180_wa + +func check_errata_2081180 + /* Applies to r0p0, r1p0 and r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2081180 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -95,6 +138,7 @@ func cortex_a710_errata_report * checking functions of each errata. */ report_errata ERRATA_A710_1987031, cortex_a710, 1987031 + report_errata ERRATA_A710_2081180, cortex_a710, 2081180 ldp x8, x30, [sp], #16 ret @@ -115,6 +159,11 @@ func cortex_a710_reset_func bl errata_a710_1987031_wa #endif +#if ERRATA_A710_2081180 + mov x0, x18 + bl errata_a710_2081180_wa +#endif + isb ret x19 endfunc cortex_a710_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index ed507c856..83d31f996 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -409,6 +409,10 @@ ERRATA_V1_2139242 ?=0 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_1987031 ?=0 +# Flag to apply erratum 2081180 workaround during reset. This erratum applies +# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_2081180 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -750,6 +754,10 @@ $(eval $(call add_define,ERRATA_V1_2139242)) $(eval $(call assert_boolean,ERRATA_A710_1987031)) $(eval $(call add_define,ERRATA_A710_1987031)) +# Process ERRATA_A710_2081180 flag +$(eval $(call assert_boolean,ERRATA_A710_2081180)) +$(eval $(call add_define,ERRATA_A710_2081180)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 9380f754181a56abe20c3c4e9152b3604ae30c65 Mon Sep 17 00:00:00 2001 From: nayanpatel-arm Date: Fri, 6 Aug 2021 17:46:10 -0700 Subject: errata: workaround for Neoverse-N2 errata 2002655 Neoverse-N2 erratum 2002655 is a Cat B erratum present in r0p0 of the Neoverse-N2 processor core, and it is still open. Neoverse-N2 SDEN: https://documentation-service.arm.com/static/61098b4e3d73a34b640e32c9?token= Signed-off-by: nayanpatel-arm Change-Id: I1380418146807527abd97cdd4918265949ba5c01 --- lib/cpus/aarch64/neoverse_n2.S | 67 ++++++++++++++++++++++++++++++++++++++++-- lib/cpus/cpu-ops.mk | 8 +++++ 2 files changed, 73 insertions(+), 2 deletions(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 8d646cba5..44db0b3a3 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -19,11 +19,55 @@ #error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2002655. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n2_2002655_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2002655 + cbz x0, 1f + + /* Apply instruction patching sequence */ + ldr x0,=0x6 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xF3A08002 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFF0F7FE + msr S3_6_c15_c8_3,x0 + ldr x0,=0x40000001003ff + msr S3_6_c15_c8_1,x0 + ldr x0,=0x7 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xBF200000 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFEF0000 + msr S3_6_c15_c8_3,x0 + ldr x0,=0x40000001003f3 + msr S3_6_c15_c8_1,x0 + isb +1: + ret x17 +endfunc errata_n2_2002655_wa + +func check_errata_2002655 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2002655 + /* ------------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------------- */ func neoverse_n2_reset_func + mov x19, x30 + /* Check if the PE implements SSBS */ mrs x0, id_aa64pfr1_el1 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT) @@ -58,8 +102,16 @@ func neoverse_n2_reset_func msr NEOVERSE_N2_CPUECTLR_EL1, x0 #endif + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_N2_2002655 + mov x0, x18 + bl errata_n2_2002655_wa +#endif + isb - ret + ret x19 endfunc neoverse_n2_reset_func func neoverse_n2_core_pwr_dwn @@ -80,7 +132,18 @@ endfunc neoverse_n2_core_pwr_dwn * Errata printing function for Neoverse N2 cores. Must follow AAPCS. */ func neoverse_n2_errata_report - /* No errata reported for Neoverse N2 cores */ + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 + + ldp x8, x30, [sp], #16 ret endfunc neoverse_n2_errata_report #endif diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index e81471ec3..a46d3b6d0 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -380,6 +380,10 @@ ERRATA_N1_1868343 ?=0 # exists in revisions r0p0, r1p0, and r2p0 as well but there is no workaround. ERRATA_N1_1946160 ?=0 +# Flag to apply erratum 2002655 workaround during reset. This erratum applies +# to revisions r0p0 of the Neoverse-N2 cpu, it is still open. +ERRATA_N2_2002655 ?=0 + # Flag to apply erratum 1774420 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the Neoverse V1 core, and was fixed in r1p1. ERRATA_V1_1774420 ?=0 @@ -722,6 +726,10 @@ $(eval $(call add_define,ERRATA_N1_1868343)) $(eval $(call assert_boolean,ERRATA_N1_1946160)) $(eval $(call add_define,ERRATA_N1_1946160)) +# Process ERRATA_N2_2002655 flag +$(eval $(call assert_boolean,ERRATA_N2_2002655)) +$(eval $(call add_define,ERRATA_N2_2002655)) + # Process ERRATA_V1_1774420 flag $(eval $(call assert_boolean,ERRATA_V1_1774420)) $(eval $(call add_define,ERRATA_V1_1774420)) -- cgit v1.2.3 From 65e04f27d42c5eccdb3893e41e25363f396e42ed Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Tue, 30 Mar 2021 16:08:32 -0500 Subject: errata: workaround for Neoverse N2 erratum 2067956 Neoverse N2 erratum 2067956 is a Cat B erratum that applies to revision r0p0 and is still open. The workaround is to set CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode. This workaround works on revision r0p0. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Bipin Ravi Change-Id: Ie92d18a379c66675b5c1c50fd0b8dde130848b21 --- lib/cpus/aarch64/neoverse_n2.S | 40 ++++++++++++++++++++++++++++++++++++---- lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 44 insertions(+), 4 deletions(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 44db0b3a3..1ab5412b1 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -61,6 +61,32 @@ func check_errata_2002655 b cpu_rev_var_ls endfunc check_errata_2002655 +/* --------------------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2067956. + * This applies to revision r0p0 of Neoverse N2 and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------- + */ +func errata_n2_2067956_wa + /* Compare x0 against revision r0p0 */ + mov x17, x30 + bl check_errata_2067956 + cbz x0, 1f + mrs x1, NEOVERSE_N2_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 + msr NEOVERSE_N2_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_n2_2067956_wa + +func check_errata_2067956 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2067956 + /* ------------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------------- @@ -81,6 +107,11 @@ func neoverse_n2_reset_func orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 +#if ERRATA_N2_2067956 + mov x0, x18 + bl errata_n2_2067956_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -97,9 +128,9 @@ func neoverse_n2_reset_func #if NEOVERSE_Nx_EXTERNAL_LLC /* Some systems may have External LLC, core needs to be made aware */ - mrs x0, NEOVERSE_N2_CPUECTLR_EL1 - orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT - msr NEOVERSE_N2_CPUECTLR_EL1, x0 + mrs x0, NEOVERSE_N2_CPUECTLR_EL1 + orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT + msr NEOVERSE_N2_CPUECTLR_EL1, x0 #endif bl cpu_get_rev_var @@ -111,7 +142,7 @@ func neoverse_n2_reset_func #endif isb - ret x19 + ret x19 endfunc neoverse_n2_reset_func func neoverse_n2_core_pwr_dwn @@ -142,6 +173,7 @@ func neoverse_n2_errata_report * checking functions of each errata. */ report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 + report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 73f977b37..b8576e9b5 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -421,6 +421,10 @@ ERRATA_A710_1987031 ?=0 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2081180 ?=0 +# Flag to apply erratum 2067956 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2067956 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -774,6 +778,10 @@ $(eval $(call add_define,ERRATA_A710_1987031)) $(eval $(call assert_boolean,ERRATA_A710_2081180)) $(eval $(call add_define,ERRATA_A710_2081180)) +# Process ERRATA_N2_2067956 flag +$(eval $(call assert_boolean,ERRATA_N2_2067956)) +$(eval $(call add_define,ERRATA_N2_2067956)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 4618b2bfa7116371a5785a32f69ef2ea928f7cb7 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Wed, 31 Mar 2021 10:10:27 -0500 Subject: errata: workaround for Neoverse N2 erratum 2025414 Neoverse N2 erratum 2025414 is a Cat B erratum that applies to revision r0p0 and is still open. The workaround is to set CPUECLTR_EL1[8] to 1 which disables store issue prefetching. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Bipin Ravi Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a --- lib/cpus/aarch64/neoverse_n2.S | 43 +++++++++++++++++++++++++++++++++++++----- lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 46 insertions(+), 5 deletions(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 1ab5412b1..a745ca5d6 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -87,9 +87,36 @@ func check_errata_2067956 b cpu_rev_var_ls endfunc check_errata_2067956 - /* ------------------------------------------------- +/* --------------------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2025414. + * This applies to revision r0p0 of Neoverse N2 and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------- + */ +func errata_n2_2025414_wa + /* Compare x0 against revision r0p0 */ + mov x17, x30 + bl check_errata_2025414 + cbz x0, 1f + mrs x1, NEOVERSE_N2_CPUECTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT + msr NEOVERSE_N2_CPUECTLR_EL1, x1 + +1: + ret x17 +endfunc errata_n2_2025414_wa + +func check_errata_2025414 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2025414 + + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. - * ------------------------------------------------- + * ------------------------------------------- */ func neoverse_n2_reset_func mov x19, x30 @@ -112,6 +139,11 @@ func neoverse_n2_reset_func bl errata_n2_2067956_wa #endif +#if ERRATA_N2_2025414 + mov x0, x18 + bl errata_n2_2025414_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -146,10 +178,10 @@ func neoverse_n2_reset_func endfunc neoverse_n2_reset_func func neoverse_n2_core_pwr_dwn - /* --------------------------------------------- + /* --------------------------------------------------- * Enable CPU power down bit in power control register * No need to do cache maintenance here. - * --------------------------------------------- + * --------------------------------------------------- */ mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT @@ -174,6 +206,7 @@ func neoverse_n2_errata_report */ report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 + report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b8576e9b5..f93aecdd9 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -425,6 +425,10 @@ ERRATA_A710_2081180 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2067956 ?=0 +# Flag to apply erratum 2025414 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2025414 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -782,6 +786,10 @@ $(eval $(call add_define,ERRATA_A710_2081180)) $(eval $(call assert_boolean,ERRATA_N2_2067956)) $(eval $(call add_define,ERRATA_N2_2067956)) +# Process ERRATA_N2_2025414 flag +$(eval $(call assert_boolean,ERRATA_N2_2025414)) +$(eval $(call add_define,ERRATA_N2_2025414)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 213afde907a375f4f28ac1843b633ca83887f174 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Wed, 31 Mar 2021 16:45:40 -0500 Subject: errata: workaround for Cortex-A710 erratum 2055002 Cortex-A710 erratum 2055002 is a Cat B erratum that applies to revisions r1p0 & r2p0 and is still open. The workaround is to set CPUACTLR_EL1[46] to force L2 tag ECC inline correction mode. This workaround works on revision r1p0 & r2p0. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Bipin Ravi Change-Id: I67be1dce53c4651167d8cee33c116e73b9dafe81 --- lib/cpus/aarch64/cortex_a710.S | 38 +++++++++++++++++++++++++++++++++++--- lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 43 insertions(+), 3 deletions(-) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 469b430a9..ac2517c21 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -107,6 +107,32 @@ func check_errata_2081180 b cpu_rev_var_ls endfunc check_errata_2081180 +/* --------------------------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2055002. + * This applies to revision r1p0, r2p0 of Cortex-A710 and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------------- + */ +func errata_a710_2055002_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_2055002 + cbz x0, 1f + mrs x1, CORTEX_A710_CPUACTLR_EL1 + orr x1, x1, CORTEX_A710_CPUACTLR_EL1_BIT_46 + msr CORTEX_A710_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_a710_2055002_wa + +func check_errata_2055002 + /* Applies to r1p0, r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2055002 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -123,10 +149,10 @@ func cortex_a710_core_pwr_dwn ret endfunc cortex_a710_core_pwr_dwn +#if REPORT_ERRATA /* - * Errata printing function for Cortex A710. Must follow AAPCS. + * Errata printing function for Cortex-A710. Must follow AAPCS. */ -#if REPORT_ERRATA func cortex_a710_errata_report stp x8, x30, [sp, #-16]! @@ -139,6 +165,7 @@ func cortex_a710_errata_report */ report_errata ERRATA_A710_1987031, cortex_a710, 1987031 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 + report_errata ERRATA_A710_2055002, cortex_a710, 2055002 ldp x8, x30, [sp], #16 ret @@ -164,8 +191,13 @@ func cortex_a710_reset_func bl errata_a710_2081180_wa #endif +#if ERRATA_A710_2055002 + mov x0, x18 + bl errata_a710_2055002_wa +#endif + isb - ret x19 + ret x19 endfunc cortex_a710_reset_func /* --------------------------------------------- diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index f93aecdd9..fe66fbb9e 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -429,6 +429,10 @@ ERRATA_N2_2067956 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2025414 ?=0 +# Flag to apply erratum 2055002 workaround during reset. This erratum applies +# to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_2055002 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -790,6 +794,10 @@ $(eval $(call add_define,ERRATA_N2_2067956)) $(eval $(call assert_boolean,ERRATA_N2_2025414)) $(eval $(call add_define,ERRATA_N2_2025414)) +# Process ERRATA_A710_2055002 flag +$(eval $(call assert_boolean,ERRATA_A710_2055002)) +$(eval $(call add_define,ERRATA_A710_2055002)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From afc2ed63f9c83a3b7408d804cbe22f02d34d075d Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Wed, 31 Mar 2021 18:45:55 -0500 Subject: errata: workaround for Cortex-A710 erratum 2017096 Cortex-A710 erratum 2017096 is a Cat B erratum that applies to revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to set CPUECLTR_EL1[8] to 1 which disables store issue prefetching. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Bipin Ravi Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3 --- lib/cpus/aarch64/cortex_a710.S | 32 ++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 40 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index ac2517c21..75b7647bd 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -133,6 +133,33 @@ func check_errata_2055002 b cpu_rev_var_ls endfunc check_errata_2055002 +/* ------------------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2017096. + * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * ------------------------------------------------------------- + */ +func errata_a710_2017096_wa + /* Compare x0 against revision r0p0 to r2p0 */ + mov x17, x30 + bl check_errata_2017096 + cbz x0, 1f + mrs x1, CORTEX_A710_CPUECTLR_EL1 + orr x1, x1, CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT + msr CORTEX_A710_CPUECTLR_EL1, x1 + +1: + ret x17 +endfunc errata_a710_2017096_wa + +func check_errata_2017096 + /* Applies to r0p0, r1p0, r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2017096 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -166,6 +193,7 @@ func cortex_a710_errata_report report_errata ERRATA_A710_1987031, cortex_a710, 1987031 report_errata ERRATA_A710_2081180, cortex_a710, 2081180 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 + report_errata ERRATA_A710_2017096, cortex_a710, 2017096 ldp x8, x30, [sp], #16 ret @@ -196,6 +224,10 @@ func cortex_a710_reset_func bl errata_a710_2055002_wa #endif +#if ERRATA_A710_2017096 + mov x0, x18 + bl errata_a710_2017096_wa +#endif isb ret x19 endfunc cortex_a710_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index fe66fbb9e..a6305268a 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -433,6 +433,10 @@ ERRATA_N2_2025414 ?=0 # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 +# Flag to apply erratum 2017096 workaround during reset. This erratum applies +# to revision r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_2017096 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -798,6 +802,10 @@ $(eval $(call add_define,ERRATA_N2_2025414)) $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) +# Process ERRATA_A710_2017096 flag +$(eval $(call assert_boolean,ERRATA_A710_2017096)) +$(eval $(call add_define,ERRATA_A710_2017096)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- cgit v1.2.3 From 7cfae93227be77f137265e8de4f1331e5d7beb3a Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Mon, 30 Aug 2021 13:02:51 -0500 Subject: errata: workaround for Neoverse N2 erratum 2189731 Neoverse N2 erratum 2189731 is a Cat B erratum that applies to revision r0p0 and is still open. The workaround is to set CPUACTLR5_EL1[44] to 1 which will cause the CPP instruction to invalidate the hardware prefetcher state trained from any EL. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Bipin Ravi Change-Id: Iddc6a59adf9fa3cab560c46f2133e1f5a8b3ad03 --- lib/cpus/aarch64/neoverse_n2.S | 33 +++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 ++++++++ 2 files changed, 41 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index a745ca5d6..0df40766e 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -114,6 +114,33 @@ func check_errata_2025414 b cpu_rev_var_ls endfunc check_errata_2025414 +/* --------------------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2189731. + * This applies to revision r0p0 of Neoverse N2 and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------- + */ +func errata_n2_2189731_wa + /* Compare x0 against revision r0p0 */ + mov x17, x30 + bl check_errata_2189731 + cbz x0, 1f + mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 + msr NEOVERSE_N2_CPUACTLR5_EL1, x1 + +1: + ret x17 +endfunc errata_n2_2189731_wa + +func check_errata_2189731 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2189731 + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------- @@ -144,6 +171,11 @@ func neoverse_n2_reset_func bl errata_n2_2025414_wa #endif +#if ERRATA_N2_2189731 + mov x0, x18 + bl errata_n2_2189731_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -207,6 +239,7 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 + report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index a6305268a..e0fc1f7c7 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -429,6 +429,10 @@ ERRATA_N2_2067956 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2025414 ?=0 +# Flag to apply erratum 2189731 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2189731 ?=0 + # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 @@ -798,6 +802,10 @@ $(eval $(call add_define,ERRATA_N2_2067956)) $(eval $(call assert_boolean,ERRATA_N2_2025414)) $(eval $(call add_define,ERRATA_N2_2025414)) +# Process ERRATA_N2_2189731 flag +$(eval $(call assert_boolean,ERRATA_N2_2189731)) +$(eval $(call add_define,ERRATA_N2_2189731)) + # Process ERRATA_A710_2055002 flag $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) -- cgit v1.2.3 From 1cafb08debe7cb99968b38a070d25fee0cc9316d Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Wed, 1 Sep 2021 01:36:43 -0500 Subject: errata: workaround for Neoverse N2 erratum 2138956 Neoverse N2 erratum 2138956 is a Cat B erratum that applies to revision r0p0 and is still open. This erratum can be avoided by inserting a sequence of 16 DMB ST instructions prior to WFI or WFE. SDEN can be found here: https://developer.arm.com/documentation/SDEN1982442/latest Signed-off-by: Bipin Ravi Change-Id: I1aac87b3075992f875451e4767b21857f596d0b2 --- lib/cpus/aarch64/neoverse_n2.S | 49 ++++++++++++++++++++++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++++ 2 files changed, 57 insertions(+) (limited to 'lib') diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 0df40766e..9e7bbf7e6 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -141,6 +141,48 @@ func check_errata_2189731 b cpu_rev_var_ls endfunc check_errata_2189731 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2138956. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_n2_2138956_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2138956 + cbz x0, 1f + + /* Apply instruction patching sequence */ + ldr x0,=0x3 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xF3A08002 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFF0F7FE + msr S3_6_c15_c8_3,x0 + ldr x0,=0x10002001003FF + msr S3_6_c15_c8_1,x0 + ldr x0,=0x4 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xBF200000 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFEF0000 + msr S3_6_c15_c8_3,x0 + ldr x0,=0x10002001003F3 + msr S3_6_c15_c8_1,x0 + isb +1: + ret x17 +endfunc errata_n2_2138956_wa + +func check_errata_2138956 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2138956 + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------- @@ -176,6 +218,12 @@ func neoverse_n2_reset_func bl errata_n2_2189731_wa #endif + +#if ERRATA_N2_2138956 + mov x0, x18 + bl errata_n2_2138956_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -240,6 +288,7 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 + report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index e0fc1f7c7..584682edf 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -433,6 +433,10 @@ ERRATA_N2_2025414 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2189731 ?=0 +# Flag to apply erratum 2138956 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2138956 ?=0 + # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 @@ -806,6 +810,10 @@ $(eval $(call add_define,ERRATA_N2_2025414)) $(eval $(call assert_boolean,ERRATA_N2_2189731)) $(eval $(call add_define,ERRATA_N2_2189731)) +# Process ERRATA_N2_2138956 flag +$(eval $(call assert_boolean,ERRATA_N2_2138956)) +$(eval $(call add_define,ERRATA_N2_2138956)) + # Process ERRATA_A710_2055002 flag $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) -- cgit v1.2.3