1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
|
/* SPDX-License-Identifier: BSD-3-Clause */
/*
* Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Linaro Limited
*/
#ifndef SCMI_MSG_CLOCK_H
#define SCMI_MSG_CLOCK_H
#include <stdint.h>
#include <lib/utils_def.h>
#define SCMI_PROTOCOL_VERSION_CLOCK 0x20000U
/*
* Identifiers of the SCMI Clock Management Protocol commands
*/
enum scmi_clock_command_id {
SCMI_CLOCK_ATTRIBUTES = 0x003,
SCMI_CLOCK_DESCRIBE_RATES = 0x004,
SCMI_CLOCK_RATE_SET = 0x005,
SCMI_CLOCK_RATE_GET = 0x006,
SCMI_CLOCK_CONFIG_SET = 0x007,
};
/* Protocol attributes */
#define SCMI_CLOCK_CLOCK_COUNT_MASK GENMASK(15, 0)
#define SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK GENMASK(23, 16)
#define SCMI_CLOCK_PROTOCOL_ATTRIBUTES(_max_pending, _clk_count) \
((((_max_pending) << 16) & SCMI_CLOCK_MAX_PENDING_TRANSITIONS_MASK) | \
(((_clk_count) & SCMI_CLOCK_CLOCK_COUNT_MASK)))
struct scmi_clock_attributes_a2p {
uint32_t clock_id;
};
#define SCMI_CLOCK_NAME_LENGTH_MAX 16U
struct scmi_clock_attributes_p2a {
int32_t status;
uint32_t attributes;
char clock_name[SCMI_CLOCK_NAME_LENGTH_MAX];
};
/*
* Clock Rate Get
*/
struct scmi_clock_rate_get_a2p {
uint32_t clock_id;
};
struct scmi_clock_rate_get_p2a {
int32_t status;
uint32_t rate[2];
};
/*
* Clock Rate Set
*/
/* If set, set the new clock rate asynchronously */
#define SCMI_CLOCK_RATE_SET_ASYNC_POS 0
/* If set, do not send a delayed asynchronous response */
#define SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS 1
/* Round up, if set, otherwise round down */
#define SCMI_CLOCK_RATE_SET_ROUND_UP_POS 2
/* If set, the platform chooses the appropriate rounding mode */
#define SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS 3
#define SCMI_CLOCK_RATE_SET_ASYNC_MASK \
BIT(SCMI_CLOCK_RATE_SET_ASYNC_POS)
#define SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_MASK \
BIT(SCMI_CLOCK_RATE_SET_NO_DELAYED_RESPONSE_POS)
#define SCMI_CLOCK_RATE_SET_ROUND_UP_MASK \
BIT(SCMI_CLOCK_RATE_SET_ROUND_UP_POS)
#define SCMI_CLOCK_RATE_SET_ROUND_AUTO_MASK \
BIT(SCMI_CLOCK_RATE_SET_ROUND_AUTO_POS)
struct scmi_clock_rate_set_a2p {
uint32_t flags;
uint32_t clock_id;
uint32_t rate[2];
};
struct scmi_clock_rate_set_p2a {
int32_t status;
};
/*
* Clock Config Set
*/
#define SCMI_CLOCK_CONFIG_SET_ENABLE_POS 0
#define SCMI_CLOCK_CONFIG_SET_ENABLE_MASK \
BIT(SCMI_CLOCK_CONFIG_SET_ENABLE_POS)
struct scmi_clock_config_set_a2p {
uint32_t clock_id;
uint32_t attributes;
};
struct scmi_clock_config_set_p2a {
int32_t status;
};
/*
* Clock Describe Rates
*/
#define SCMI_CLOCK_RATE_FORMAT_RANGE 1U
#define SCMI_CLOCK_RATE_FORMAT_LIST 0U
#define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK GENMASK_32(31, 16)
#define SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS 16
#define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK BIT(12)
#define SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS 12
#define SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK GENMASK_32(11, 0)
#define SCMI_CLOCK_DESCRIBE_RATES_NUM_RATES_FLAGS(_count, _fmt, _rem_rates) \
( \
((_count) & SCMI_CLOCK_DESCRIBE_RATES_COUNT_MASK) | \
(((_rem_rates) << SCMI_CLOCK_DESCRIBE_RATES_REMAINING_POS) & \
SCMI_CLOCK_DESCRIBE_RATES_REMAINING_MASK) | \
(((_fmt) << SCMI_CLOCK_DESCRIBE_RATES_FORMAT_POS) & \
SCMI_CLOCK_DESCRIBE_RATES_FORMAT_MASK) \
)
struct scmi_clock_rate {
uint32_t low;
uint32_t high;
};
struct scmi_clock_describe_rates_a2p {
uint32_t clock_id;
uint32_t rate_index;
};
struct scmi_clock_describe_rates_p2a {
int32_t status;
uint32_t num_rates_flags;
struct scmi_clock_rate rates[];
};
#endif /* SCMI_MSG_CLOCK_H */
|
