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| author | Hao Liu <Hao.Liu@arm.com> | 2013-11-19 02:17:31 +0000 |
|---|---|---|
| committer | Hao Liu <Hao.Liu@arm.com> | 2013-11-19 02:17:31 +0000 |
| commit | 11a94f9ccaf29bb7cd073787d5cb6d130a38bf62 (patch) | |
| tree | 91b5e720e81e1b124d81ee11919f833d118e842e /include/clang/Basic | |
| parent | 2098d1a3b0114700093605ddd3c1435456698466 (diff) | |
| download | clang-11a94f9ccaf29bb7cd073787d5cb6d130a38bf62.tar.gz | |
Implement AArch64 neon instructions class SIMD lsone and SIMD lone-post.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@195079 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include/clang/Basic')
| -rw-r--r-- | include/clang/Basic/arm_neon.td | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td index e83978cb13..a09925469d 100644 --- a/include/clang/Basic/arm_neon.td +++ b/include/clang/Basic/arm_neon.td @@ -526,7 +526,7 @@ let isA64 = 1 in { //////////////////////////////////////////////////////////////////////////////// // Load/Store -// With additional QUl, Ql, Qd, Pl, QPl type. +// With additional QUl, Ql, d, Qd, Pl, QPl type. def LD1 : WInst<"vld1", "dc", "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsUcUsUiUlcsilhfdPcPsPlQPl">; def LD2 : WInst<"vld2", "2c", @@ -558,6 +558,33 @@ def ST1_X3 : WInst<"vst1_x3", "vp3", def ST1_X4 : WInst<"vst1_x4", "vp4", "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +// With additional QUl, Ql, d, Qd, Pl, QPl type. +def LD1_LANE : WInst<"vld1_lane", "dcdi", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def LD2_LANE : WInst<"vld2_lane", "2c2i", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def LD3_LANE : WInst<"vld3_lane", "3c3i", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def LD4_LANE : WInst<"vld4_lane", "4c4i", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def ST1_LANE : WInst<"vst1_lane", "vpdi", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def ST2_LANE : WInst<"vst2_lane", "vp2i", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def ST3_LANE : WInst<"vst3_lane", "vp3i", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def ST4_LANE : WInst<"vst4_lane", "vp4i", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; + +def LD1_DUP : WInst<"vld1_dup", "dc", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def LD2_DUP : WInst<"vld2_dup", "2c", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def LD3_DUP : WInst<"vld3_dup", "3c", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; +def LD4_DUP : WInst<"vld4_dup", "4c", + "QUcQUsQUiQUlQcQsQiQlQhQfQdQPcQPsQPlUcUsUiUlcsilhfdPcPsPl">; + //////////////////////////////////////////////////////////////////////////////// // Addition // With additional Qd type. |