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| author | Bill Wendling <isanbard@gmail.com> | 2013-12-08 00:02:49 +0000 |
|---|---|---|
| committer | Bill Wendling <isanbard@gmail.com> | 2013-12-08 00:02:49 +0000 |
| commit | 612f5bfeac5c4d923bb448b2f06e3aeab318130f (patch) | |
| tree | 365120cd9b4ef2959daf04b0afd30b77bac8494e /include | |
| parent | 917b328a7f565f9f3f0ae2067a8b97732efaa9f8 (diff) | |
| download | clang-612f5bfeac5c4d923bb448b2f06e3aeab318130f.tar.gz | |
Merging r196359:
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r196359 | kevinqin | 2013-12-03 23:53:09 -0800 (Tue, 03 Dec 2013) | 1 line
[AArch64 NEON] Add missing compare intrinsics.
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git-svn-id: https://llvm.org/svn/llvm-project/cfe/branches/release_34@196680 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'include')
| -rw-r--r-- | include/clang/Basic/arm_neon.td | 35 |
1 files changed, 19 insertions, 16 deletions
diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td index e7f95a21c1..9097edc4e6 100644 --- a/include/clang/Basic/arm_neon.td +++ b/include/clang/Basic/arm_neon.td @@ -732,28 +732,31 @@ def FSQRT : SInst<"vsqrt", "dd", "fdQfQd">; //////////////////////////////////////////////////////////////////////////////// // Comparison // With additional Qd, Ql, QPl type. -def VVCEQ : IOpInst<"vceq", "udd", "csifUcUsUiPcQcQsQiQfQUcQUsQUiQPcPlQPl", - OP_EQ>; -def FCAGE : IInst<"vcage", "udd", "fQfQd">; -def FCAGT : IInst<"vcagt", "udd", "fQfQd">; -def FCALE : IInst<"vcale", "udd", "fQfQd">; -def FCALT : IInst<"vcalt", "udd", "fQfQd">; +def FCAGE : IInst<"vcage", "udd", "fdQfQd">; +def FCAGT : IInst<"vcagt", "udd", "fdQfQd">; +def FCALE : IInst<"vcale", "udd", "fdQfQd">; +def FCALT : IInst<"vcalt", "udd", "fdQfQd">; // With additional Ql, QUl, Qd types. def CMTST : WInst<"vtst", "udd", "csiUcUsUiPcPsQcQsQiQUcQUsQUiQPcQPslUlQlQUlPlQPl">; +// With additional l, Ul,d, Qd, Ql, QUl, Qd types. def CFMEQ : SOpInst<"vceq", "udd", - "csifUcUsUiPcQcQsQiQlQfQUcQUsQUiQUlQPcQd", OP_EQ>; -def CFMGE : SOpInst<"vcge", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_GE>; -def CFMLE : SOpInst<"vcle", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_LE>; -def CFMGT : SOpInst<"vcgt", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_GT>; -def CFMLT : SOpInst<"vclt", "udd", "csifUcUsUiQcQsQiQlQfQUcQUsQUiQUlQd", OP_LT>; + "csilfUcUsUiUlPcQcdQdQsQiQfQUcQUsQUiQUlQlQPcPlQPl", OP_EQ>; +def CFMGE : SOpInst<"vcge", "udd", + "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_GE>; +def CFMLE : SOpInst<"vcle", "udd", + "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_LE>; +def CFMGT : SOpInst<"vcgt", "udd", + "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_GT>; +def CFMLT : SOpInst<"vclt", "udd", + "csilfUcUsUiUlQcQsQiQlQfQUcQUsQUiQUldQd", OP_LT>; def CMEQ : SInst<"vceqz", "ud", - "csifUcUsUiPcPsQcQsQiQlQfQUcQUsQUiQUlQPcQPsQd">; -def CMGE : SInst<"vcgez", "ud", "csifdQcQsQiQlQfQd">; -def CMLE : SInst<"vclez", "ud", "csifdQcQsQiQlQfQd">; -def CMGT : SInst<"vcgtz", "ud", "csifdQcQsQiQlQfQd">; -def CMLT : SInst<"vcltz", "ud", "csifdQcQsQiQlQfQd">; + "csilfUcUsUiUlPcPsPlQcQsQiQlQfQUcQUsQUiQUlQPcQPsdQdQPl">; +def CMGE : SInst<"vcgez", "ud", "csilfdQcQsQiQlQfQd">; +def CMLE : SInst<"vclez", "ud", "csilfdQcQsQiQlQfQd">; +def CMGT : SInst<"vcgtz", "ud", "csilfdQcQsQiQlQfQd">; +def CMLT : SInst<"vcltz", "ud", "csilfdQcQsQiQlQfQd">; //////////////////////////////////////////////////////////////////////////////// // Max/Min Integer |