diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/cpu_features_cache_info.h | 2 | ||||
| -rw-r--r-- | include/cpu_features_macros.h | 107 | ||||
| -rw-r--r-- | include/cpuinfo_aarch64.h | 104 | ||||
| -rw-r--r-- | include/cpuinfo_arm.h | 38 | ||||
| -rw-r--r-- | include/cpuinfo_mips.h | 4 | ||||
| -rw-r--r-- | include/cpuinfo_ppc.h | 2 | ||||
| -rw-r--r-- | include/cpuinfo_x86.h | 25 | ||||
| -rw-r--r-- | include/internal/bit_utils.h | 3 | ||||
| -rw-r--r-- | include/internal/cpuid_x86.h | 5 | ||||
| -rw-r--r-- | include/internal/filesystem.h | 3 | ||||
| -rw-r--r-- | include/internal/hwcaps.h | 50 | ||||
| -rw-r--r-- | include/internal/stack_line_reader.h | 2 | ||||
| -rw-r--r-- | include/internal/string_view.h | 3 | ||||
| -rw-r--r-- | include/internal/unix_features_aggregator.h | 60 |
14 files changed, 115 insertions, 293 deletions
diff --git a/include/cpu_features_cache_info.h b/include/cpu_features_cache_info.h index 1a61ee1..b7cc046 100644 --- a/include/cpu_features_cache_info.h +++ b/include/cpu_features_cache_info.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. diff --git a/include/cpu_features_macros.h b/include/cpu_features_macros.h index 4b231a1..2227160 100644 --- a/include/cpu_features_macros.h +++ b/include/cpu_features_macros.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -79,10 +79,6 @@ #define CPU_FEATURES_OS_WINDOWS #endif -#if (defined(__apple__) || defined(__APPLE__) || defined(__MACH__)) -#define CPU_FEATURES_OS_DARWIN -#endif - //////////////////////////////////////////////////////////////////////////////// // Compilers //////////////////////////////////////////////////////////////////////////////// @@ -122,95 +118,26 @@ // Use the following to check if a feature is known to be available at // compile time. See README.md for an example. #if defined(CPU_FEATURES_ARCH_X86) - -#if defined(__AES__) -#define CPU_FEATURES_COMPILED_X86_AES 1 -#else -#define CPU_FEATURES_COMPILED_X86_AES 0 -#endif // defined(__AES__) - -#if defined(__F16C__) -#define CPU_FEATURES_COMPILED_X86_F16C 1 -#else -#define CPU_FEATURES_COMPILED_X86_F16C 0 -#endif // defined(__F16C__) - -#if defined(__BMI__) -#define CPU_FEATURES_COMPILED_X86_BMI 1 -#else -#define CPU_FEATURES_COMPILED_X86_BMI 0 -#endif // defined(__BMI__) - -#if defined(__BMI2__) -#define CPU_FEATURES_COMPILED_X86_BMI2 1 -#else -#define CPU_FEATURES_COMPILED_X86_BMI2 0 -#endif // defined(__BMI2__) - -#if (defined(__SSE__) || (_M_IX86_FP >= 1)) -#define CPU_FEATURES_COMPILED_X86_SSE 1 -#else -#define CPU_FEATURES_COMPILED_X86_SSE 0 +#define CPU_FEATURES_COMPILED_X86_AES defined(__AES__) +#define CPU_FEATURES_COMPILED_X86_F16C defined(__F16C__) +#define CPU_FEATURES_COMPILED_X86_BMI defined(__BMI__) +#define CPU_FEATURES_COMPILED_X86_BMI2 defined(__BMI2__) +#define CPU_FEATURES_COMPILED_X86_SSE (defined(__SSE__) || (_M_IX86_FP >= 1)) +#define CPU_FEATURES_COMPILED_X86_SSE2 (defined(__SSE2__) || (_M_IX86_FP >= 2)) +#define CPU_FEATURES_COMPILED_X86_SSE3 defined(__SSE3__) +#define CPU_FEATURES_COMPILED_X86_SSSE3 defined(__SSSE3__) +#define CPU_FEATURES_COMPILED_X86_SSE4_1 defined(__SSE4_1__) +#define CPU_FEATURES_COMPILED_X86_SSE4_2 defined(__SSE4_2__) +#define CPU_FEATURES_COMPILED_X86_AVX defined(__AVX__) +#define CPU_FEATURES_COMPILED_x86_AVX2 defined(__AVX2__) #endif -#if (defined(__SSE2__) || (_M_IX86_FP >= 2)) -#define CPU_FEATURES_COMPILED_X86_SSE2 1 -#else -#define CPU_FEATURES_COMPILED_X86_SSE2 0 -#endif - -#if defined(__SSE3__) -#define CPU_FEATURES_COMPILED_X86_SSE3 1 -#else -#define CPU_FEATURES_COMPILED_X86_SSE3 0 -#endif // defined(__SSE3__) - -#if defined(__SSSE3__) -#define CPU_FEATURES_COMPILED_X86_SSSE3 1 -#else -#define CPU_FEATURES_COMPILED_X86_SSSE3 0 -#endif // defined(__SSSE3__) - -#if defined(__SSE4_1__) -#define CPU_FEATURES_COMPILED_X86_SSE4_1 1 -#else -#define CPU_FEATURES_COMPILED_X86_SSE4_1 0 -#endif // defined(__SSE4_1__) - -#if defined(__SSE4_2__) -#define CPU_FEATURES_COMPILED_X86_SSE4_2 1 -#else -#define CPU_FEATURES_COMPILED_X86_SSE4_2 0 -#endif // defined(__SSE4_2__) - -#if defined(__AVX__) -#define CPU_FEATURES_COMPILED_X86_AVX 1 -#else -#define CPU_FEATURES_COMPILED_X86_AVX 0 -#endif // defined(__AVX__) - -#if defined(__AVX2__) -#define CPU_FEATURES_COMPILED_X86_AVX2 1 -#else -#define CPU_FEATURES_COMPILED_X86_AVX2 0 -#endif // defined(__AVX2__) - -#endif // defined(CPU_FEATURES_ARCH_X86) - #if defined(CPU_FEATURES_ARCH_ANY_ARM) -#if defined(__ARM_NEON__) -#define CPU_FEATURES_COMPILED_ANY_ARM_NEON 1 -#else -#define CPU_FEATURES_COMPILED_ANY_ARM_NEON 0 -#endif // defined(__ARM_NEON__) -#endif // defined(CPU_FEATURES_ARCH_ANY_ARM) +#define CPU_FEATURES_COMPILED_ANY_ARM_NEON defined(__ARM_NEON__) +#endif #if defined(CPU_FEATURES_ARCH_MIPS) -#if defined(__mips_msa) -#define CPU_FEATURES_COMPILED_MIPS_MSA 1 -#else -#define CPU_FEATURES_COMPILED_MIPS_MSA 0 -#endif // defined(__mips_msa) -#endif // defined(CPU_FEATURES_ARCH_MIPS) +#define CPU_FEATURES_COMPILED_MIPS_MSA defined(__mips_msa) +#endif #endif // CPU_FEATURES_INCLUDE_CPU_FEATURES_MACROS_H_ diff --git a/include/cpuinfo_aarch64.h b/include/cpuinfo_aarch64.h index d85d46d..cd3a676 100644 --- a/include/cpuinfo_aarch64.h +++ b/include/cpuinfo_aarch64.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -15,62 +15,19 @@ #ifndef CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_ #define CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_ -#include "cpu_features_cache_info.h" #include "cpu_features_macros.h" +#include "cpu_features_cache_info.h" CPU_FEATURES_START_CPP_NAMESPACE typedef struct { - int fp : 1; // Floating-point. - int asimd : 1; // Advanced SIMD. - int evtstrm : 1; // Generic timer generated events. - int aes : 1; // Hardware-accelerated Advanced Encryption Standard. - int pmull : 1; // Polynomial multiply long. - int sha1 : 1; // Hardware-accelerated SHA1. - int sha2 : 1; // Hardware-accelerated SHA2-256. - int crc32 : 1; // Hardware-accelerated CRC-32. - int atomics : 1; // Armv8.1 atomic instructions. - int fphp : 1; // Half-precision floating point support. - int asimdhp : 1; // Advanced SIMD half-precision support. - int cpuid : 1; // Access to certain ID registers. - int asimdrdm : 1; // Rounding Double Multiply Accumulate/Subtract. - int jscvt : 1; // Support for JavaScript conversion. - int fcma : 1; // Floating point complex numbers. - int lrcpc : 1; // Support for weaker release consistency. - int dcpop : 1; // Data persistence writeback. - int sha3 : 1; // Hardware-accelerated SHA3. - int sm3 : 1; // Hardware-accelerated SM3. - int sm4 : 1; // Hardware-accelerated SM4. - int asimddp : 1; // Dot product instruction. - int sha512 : 1; // Hardware-accelerated SHA512. - int sve : 1; // Scalable Vector Extension. - int asimdfhm : 1; // Additional half-precision instructions. - int dit : 1; // Data independent timing. - int uscat : 1; // Unaligned atomics support. - int ilrcpc : 1; // Additional support for weaker release consistency. - int flagm : 1; // Flag manipulation instructions. - int ssbs : 1; // Speculative Store Bypass Safe PSTATE bit. - int sb : 1; // Speculation barrier. - int paca : 1; // Address authentication. - int pacg : 1; // Generic authentication. - int dcpodp : 1; // Data cache clean to point of persistence. - int sve2 : 1; // Scalable Vector Extension (version 2). - int sveaes : 1; // SVE AES instructions. - int svepmull : 1; // SVE polynomial multiply long instructions. - int svebitperm : 1; // SVE bit permute instructions. - int svesha3 : 1; // SVE SHA3 instructions. - int svesm4 : 1; // SVE SM4 instructions. - int flagm2 : 1; // Additional flag manipulation instructions. - int frint : 1; // Floating point to integer rounding. - int svei8mm : 1; // SVE Int8 matrix multiplication instructions. - int svef32mm : 1; // SVE FP32 matrix multiplication instruction. - int svef64mm : 1; // SVE FP64 matrix multiplication instructions. - int svebf16 : 1; // SVE BFloat16 instructions. - int i8mm : 1; // Int8 matrix multiplication instructions. - int bf16 : 1; // BFloat16 instructions. - int dgh : 1; // Data Gathering Hint instruction. - int rng : 1; // True random number generator support. - int bti : 1; // Branch target identification. + int fp : 1; // Floating-point. + int asimd : 1; // Advanced SIMD. + int aes : 1; // Hardware-accelerated Advanced Encryption Standard. + int pmull : 1; // Polynomial multiply long. + int sha1 : 1; // Hardware-accelerated SHA1. + int sha2 : 1; // Hardware-accelerated SHA2-256. + int crc32 : 1; // Hardware-accelerated CRC-32. // Make sure to update Aarch64FeaturesEnum below if you add a field here. } Aarch64Features; @@ -91,54 +48,11 @@ Aarch64Info GetAarch64Info(void); typedef enum { AARCH64_FP, AARCH64_ASIMD, - AARCH64_EVTSTRM, AARCH64_AES, AARCH64_PMULL, AARCH64_SHA1, AARCH64_SHA2, AARCH64_CRC32, - AARCH64_ATOMICS, - AARCH64_FPHP, - AARCH64_ASIMDHP, - AARCH64_CPUID, - AARCH64_ASIMDRDM, - AARCH64_JSCVT, - AARCH64_FCMA, - AARCH64_LRCPC, - AARCH64_DCPOP, - AARCH64_SHA3, - AARCH64_SM3, - AARCH64_SM4, - AARCH64_ASIMDDP, - AARCH64_SHA512, - AARCH64_SVE, - AARCH64_ASIMDFHM, - AARCH64_DIT, - AARCH64_USCAT, - AARCH64_ILRCPC, - AARCH64_FLAGM, - AARCH64_SSBS, - AARCH64_SB, - AARCH64_PACA, - AARCH64_PACG, - AARCH64_DCPODP, - AARCH64_SVE2, - AARCH64_SVEAES, - AARCH64_SVEPMULL, - AARCH64_SVEBITPERM, - AARCH64_SVESHA3, - AARCH64_SVESM4, - AARCH64_FLAGM2, - AARCH64_FRINT, - AARCH64_SVEI8MM, - AARCH64_SVEF32MM, - AARCH64_SVEF64MM, - AARCH64_SVEBF16, - AARCH64_I8MM, - AARCH64_BF16, - AARCH64_DGH, - AARCH64_RNG, - AARCH64_BTI, AARCH64_LAST_, } Aarch64FeaturesEnum; diff --git a/include/cpuinfo_arm.h b/include/cpuinfo_arm.h index 0952d7c..d15471f 100644 --- a/include/cpuinfo_arm.h +++ b/include/cpuinfo_arm.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -16,9 +16,8 @@ #define CPU_FEATURES_INCLUDE_CPUINFO_ARM_H_ #include <stdint.h> // uint32_t - -#include "cpu_features_cache_info.h" #include "cpu_features_macros.h" +#include "cpu_features_cache_info.h" CPU_FEATURES_START_CPP_NAMESPACE @@ -26,33 +25,30 @@ typedef struct { int swp : 1; // SWP instruction (atomic read-modify-write) int half : 1; // Half-word loads and stores int thumb : 1; // Thumb (16-bit instruction set) - int _26bit : 1; // "26 Bit" Model (Processor status register folded into - // program counter) + int _26bit : 1; // "26 Bit" Model (Processor status register folded into program counter) int fastmult : 1; // 32x32->64-bit multiplication int fpa : 1; // Floating point accelerator int vfp : 1; // Vector Floating Point. - int edsp : 1; // DSP extensions (the 'e' variant of the ARM9 CPUs, and all - // others above) - int java : 1; // Jazelle (Java bytecode accelerator) - int iwmmxt : 1; // Intel Wireless MMX Technology. - int crunch : 1; // MaverickCrunch coprocessor - int thumbee : 1; // ThumbEE - int neon : 1; // Advanced SIMD. - int vfpv3 : 1; // VFP version 3 + int edsp : 1; // DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above) + int java : 1; // Jazelle (Java bytecode accelerator) + int iwmmxt : 1; // Intel Wireless MMX Technology. + int crunch : 1; // MaverickCrunch coprocessor + int thumbee : 1; // ThumbEE + int neon : 1; // Advanced SIMD. + int vfpv3 : 1; // VFP version 3 int vfpv3d16 : 1; // VFP version 3 with 16 D-registers int tls : 1; // TLS register int vfpv4 : 1; // VFP version 4 with fast context switching int idiva : 1; // SDIV and UDIV hardware division in ARM mode. int idivt : 1; // SDIV and UDIV hardware division in Thumb mode. int vfpd32 : 1; // VFP with 32 D-registers - int lpae : 1; // Large Physical Address Extension (>4GB physical memory on - // 32-bit architecture) - int evtstrm : 1; // kernel event stream using generic architected timer - int aes : 1; // Hardware-accelerated Advanced Encryption Standard. - int pmull : 1; // Polynomial multiply long. - int sha1 : 1; // Hardware-accelerated SHA1. - int sha2 : 1; // Hardware-accelerated SHA2-256. - int crc32 : 1; // Hardware-accelerated CRC-32. + int lpae : 1; // Large Physical Address Extension (>4GB physical memory on 32-bit architecture) + int evtstrm : 1; // kernel event stream using generic architected timer + int aes : 1; // Hardware-accelerated Advanced Encryption Standard. + int pmull : 1; // Polynomial multiply long. + int sha1 : 1; // Hardware-accelerated SHA1. + int sha2 : 1; // Hardware-accelerated SHA2-256. + int crc32 : 1; // Hardware-accelerated CRC-32. // Make sure to update ArmFeaturesEnum below if you add a field here. } ArmFeatures; diff --git a/include/cpuinfo_mips.h b/include/cpuinfo_mips.h index 9e5e7fc..d82ae85 100644 --- a/include/cpuinfo_mips.h +++ b/include/cpuinfo_mips.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -15,8 +15,8 @@ #ifndef CPU_FEATURES_INCLUDE_CPUINFO_MIPS_H_ #define CPU_FEATURES_INCLUDE_CPUINFO_MIPS_H_ -#include "cpu_features_cache_info.h" #include "cpu_features_macros.h" +#include "cpu_features_cache_info.h" CPU_FEATURES_START_CPP_NAMESPACE diff --git a/include/cpuinfo_ppc.h b/include/cpuinfo_ppc.h index f691194..eaac7da 100644 --- a/include/cpuinfo_ppc.h +++ b/include/cpuinfo_ppc.h @@ -15,8 +15,8 @@ #ifndef CPU_FEATURES_INCLUDE_CPUINFO_PPC_H_ #define CPU_FEATURES_INCLUDE_CPUINFO_PPC_H_ -#include "cpu_features_cache_info.h" #include "cpu_features_macros.h" +#include "cpu_features_cache_info.h" #include "internal/hwcaps.h" CPU_FEATURES_START_CPP_NAMESPACE diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index 8d40f71..4d51b60 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -1,5 +1,4 @@ -// Copyright 2017 Google LLC -// Copyright 2020 Intel Corporation +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -32,7 +31,6 @@ typedef struct { int aes : 1; int erms : 1; int f16c : 1; - int fma4 : 1; int fma3 : 1; int vaes : 1; int vpclmulqdq : 1; @@ -50,7 +48,6 @@ typedef struct { int ssse3 : 1; int sse4_1 : 1; int sse4_2 : 1; - int sse4a : 1; int avx : 1; int avx2 : 1; @@ -70,13 +67,6 @@ typedef struct { int avx512vpopcntdq : 1; int avx512_4vnniw : 1; int avx512_4vbmi2 : 1; - int avx512_second_fma : 1; - int avx512_4fmaps : 1; - int avx512_bf16 : 1; - int avx512_vp2intersect : 1; - int amx_bf16 : 1; - int amx_tile : 1; - int amx_int8 : 1; int pclmulqdq : 1; int smx : 1; @@ -126,11 +116,7 @@ typedef enum { INTEL_ATOM_GMT, // GOLDMONT INTEL_KBL, // KABY LAKE INTEL_CFL, // COFFEE LAKE - INTEL_WHL, // WHISKEY LAKE INTEL_CNL, // CANNON LAKE - INTEL_ICL, // ICE LAKE - INTEL_TGL, // TIGER LAKE - INTEL_SPR, // SAPPHIRE RAPIDS AMD_HAMMER, // K8 AMD_K10, // K10 AMD_BOBCAT, // K14 @@ -161,7 +147,6 @@ typedef enum { X86_AES, X86_ERMS, X86_F16C, - X86_FMA4, X86_FMA3, X86_VAES, X86_VPCLMULQDQ, @@ -178,7 +163,6 @@ typedef enum { X86_SSSE3, X86_SSE4_1, X86_SSE4_2, - X86_SSE4A, X86_AVX, X86_AVX2, X86_AVX512F, @@ -196,13 +180,6 @@ typedef enum { X86_AVX512VPOPCNTDQ, X86_AVX512_4VNNIW, X86_AVX512_4VBMI2, - X86_AVX512_SECOND_FMA, - X86_AVX512_4FMAPS, - X86_AVX512_BF16, - X86_AVX512_VP2INTERSECT, - X86_AMX_BF16, - X86_AMX_TILE, - X86_AMX_INT8, X86_PCLMULQDQ, X86_SMX, X86_SGX, diff --git a/include/internal/bit_utils.h b/include/internal/bit_utils.h index 3467ff9..bc965cb 100644 --- a/include/internal/bit_utils.h +++ b/include/internal/bit_utils.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -18,7 +18,6 @@ #include <assert.h> #include <stdbool.h> #include <stdint.h> - #include "cpu_features_macros.h" CPU_FEATURES_START_CPP_NAMESPACE diff --git a/include/internal/cpuid_x86.h b/include/internal/cpuid_x86.h index 33327a4..754ca38 100644 --- a/include/internal/cpuid_x86.h +++ b/include/internal/cpuid_x86.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -26,8 +26,7 @@ typedef struct { uint32_t eax, ebx, ecx, edx; } Leaf; -// Returns the result of a call to the cpuid instruction. -Leaf GetCpuidLeaf(uint32_t leaf_id, int ecx); +Leaf CpuIdEx(uint32_t leaf_id, int ecx); // Returns the eax value of the XCR0 register. uint32_t GetXCR0Eax(void); diff --git a/include/internal/filesystem.h b/include/internal/filesystem.h index d8f2f6a..3378881 100644 --- a/include/internal/filesystem.h +++ b/include/internal/filesystem.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -19,7 +19,6 @@ #include <stddef.h> #include <stdint.h> - #include "cpu_features_macros.h" CPU_FEATURES_START_CPP_NAMESPACE diff --git a/include/internal/hwcaps.h b/include/internal/hwcaps.h index 62037c8..06a0f60 100644 --- a/include/internal/hwcaps.h +++ b/include/internal/hwcaps.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -17,9 +17,7 @@ #ifndef CPU_FEATURES_INCLUDE_INTERNAL_HWCAPS_H_ #define CPU_FEATURES_INCLUDE_INTERNAL_HWCAPS_H_ -#include <stdbool.h> #include <stdint.h> - #include "cpu_features_macros.h" CPU_FEATURES_START_CPP_NAMESPACE @@ -30,55 +28,11 @@ CPU_FEATURES_START_CPP_NAMESPACE // http://elixir.free-electrons.com/linux/latest/source/arch/arm64/include/uapi/asm/hwcap.h #define AARCH64_HWCAP_FP (1UL << 0) #define AARCH64_HWCAP_ASIMD (1UL << 1) -#define AARCH64_HWCAP_EVTSTRM (1UL << 2) #define AARCH64_HWCAP_AES (1UL << 3) #define AARCH64_HWCAP_PMULL (1UL << 4) #define AARCH64_HWCAP_SHA1 (1UL << 5) #define AARCH64_HWCAP_SHA2 (1UL << 6) #define AARCH64_HWCAP_CRC32 (1UL << 7) -#define AARCH64_HWCAP_ATOMICS (1UL << 8) -#define AARCH64_HWCAP_FPHP (1UL << 9) -#define AARCH64_HWCAP_ASIMDHP (1UL << 10) -#define AARCH64_HWCAP_CPUID (1UL << 11) -#define AARCH64_HWCAP_ASIMDRDM (1UL << 12) -#define AARCH64_HWCAP_JSCVT (1UL << 13) -#define AARCH64_HWCAP_FCMA (1UL << 14) -#define AARCH64_HWCAP_LRCPC (1UL << 15) -#define AARCH64_HWCAP_DCPOP (1UL << 16) -#define AARCH64_HWCAP_SHA3 (1UL << 17) -#define AARCH64_HWCAP_SM3 (1UL << 18) -#define AARCH64_HWCAP_SM4 (1UL << 19) -#define AARCH64_HWCAP_ASIMDDP (1UL << 20) -#define AARCH64_HWCAP_SHA512 (1UL << 21) -#define AARCH64_HWCAP_SVE (1UL << 22) -#define AARCH64_HWCAP_ASIMDFHM (1UL << 23) -#define AARCH64_HWCAP_DIT (1UL << 24) -#define AARCH64_HWCAP_USCAT (1UL << 25) -#define AARCH64_HWCAP_ILRCPC (1UL << 26) -#define AARCH64_HWCAP_FLAGM (1UL << 27) -#define AARCH64_HWCAP_SSBS (1UL << 28) -#define AARCH64_HWCAP_SB (1UL << 29) -#define AARCH64_HWCAP_PACA (1UL << 30) -#define AARCH64_HWCAP_PACG (1UL << 31) - -#define AARCH64_HWCAP2_DCPODP (1UL << 0) -#define AARCH64_HWCAP2_SVE2 (1UL << 1) -#define AARCH64_HWCAP2_SVEAES (1UL << 2) -#define AARCH64_HWCAP2_SVEPMULL (1UL << 3) -#define AARCH64_HWCAP2_SVEBITPERM (1UL << 4) -#define AARCH64_HWCAP2_SVESHA3 (1UL << 5) -#define AARCH64_HWCAP2_SVESM4 (1UL << 6) -#define AARCH64_HWCAP2_FLAGM2 (1UL << 7) -#define AARCH64_HWCAP2_FRINT (1UL << 8) -#define AARCH64_HWCAP2_SVEI8MM (1UL << 9) -#define AARCH64_HWCAP2_SVEF32MM (1UL << 10) -#define AARCH64_HWCAP2_SVEF64MM (1UL << 11) -#define AARCH64_HWCAP2_SVEBF16 (1UL << 12) -#define AARCH64_HWCAP2_I8MM (1UL << 13) -#define AARCH64_HWCAP2_BF16 (1UL << 14) -#define AARCH64_HWCAP2_DGH (1UL << 15) -#define AARCH64_HWCAP2_RNG (1UL << 16) -#define AARCH64_HWCAP2_BTI (1UL << 17) // http://elixir.free-electrons.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h #define ARM_HWCAP_SWP (1UL << 0) @@ -171,8 +125,6 @@ typedef struct { } HardwareCapabilities; HardwareCapabilities CpuFeatures_GetHardwareCapabilities(void); -bool CpuFeatures_IsHwCapsSet(const HardwareCapabilities hwcaps_mask, - const HardwareCapabilities hwcaps); typedef struct { char platform[64]; // 0 terminated string diff --git a/include/internal/stack_line_reader.h b/include/internal/stack_line_reader.h index 39c1b8b..c540f6b 100644 --- a/include/internal/stack_line_reader.h +++ b/include/internal/stack_line_reader.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. diff --git a/include/internal/string_view.h b/include/internal/string_view.h index 64fed40..aa3779c 100644 --- a/include/internal/string_view.h +++ b/include/internal/string_view.h @@ -1,4 +1,4 @@ -// Copyright 2017 Google LLC +// Copyright 2017 Google Inc. // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -19,7 +19,6 @@ #include <stdbool.h> #include <stddef.h> #include <string.h> - #include "cpu_features_macros.h" CPU_FEATURES_START_CPP_NAMESPACE diff --git a/include/internal/unix_features_aggregator.h b/include/internal/unix_features_aggregator.h new file mode 100644 index 0000000..77661d4 --- /dev/null +++ b/include/internal/unix_features_aggregator.h @@ -0,0 +1,60 @@ +// Copyright 2017 Google Inc. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// CapabilityConfig provides a way to map cpu features to hardware caps and +// /proc/cpuinfo flags. We then provide functions to update capabilities from +// either source. +#ifndef CPU_FEATURES_INCLUDE_INTERNAL_LINUX_FEATURES_AGGREGATOR_H_ +#define CPU_FEATURES_INCLUDE_INTERNAL_LINUX_FEATURES_AGGREGATOR_H_ + +#include <ctype.h> +#include <stdint.h> +#include "cpu_features_macros.h" +#include "internal/hwcaps.h" +#include "internal/string_view.h" + +CPU_FEATURES_START_CPP_NAMESPACE + +// Use the following macro to declare setter functions to be used in +// CapabilityConfig. +#define DECLARE_SETTER(FeatureType, FeatureName) \ + static void set_##FeatureName(void* const features, bool value) { \ + ((FeatureType*)features)->FeatureName = value; \ + } + +// Describes the relationship between hardware caps and /proc/cpuinfo flags. +typedef struct { + const HardwareCapabilities hwcaps_mask; + const char* const proc_cpuinfo_flag; + void (*set_bit)(void* const, bool); // setter for the corresponding bit. +} CapabilityConfig; + +// For every config, looks into flags_line for the presence of the +// corresponding proc_cpuinfo_flag, calls `set_bit` accordingly. +// Note: features is a pointer to the underlying Feature struct. +void CpuFeatures_SetFromFlags(const size_t configs_size, + const CapabilityConfig* configs, + const StringView flags_line, + void* const features); + +// For every config, looks into hwcaps for the presence of the feature. Calls +// `set_bit` with true if the hardware capability is found. +// Note: features is a pointer to the underlying Feature struct. +void CpuFeatures_OverrideFromHwCaps(const size_t configs_size, + const CapabilityConfig* configs, + const HardwareCapabilities hwcaps, + void* const features); + +CPU_FEATURES_END_CPP_NAMESPACE +#endif // CPU_FEATURES_INCLUDE_INTERNAL_LINUX_FEATURES_AGGREGATOR_H_ |