diff options
author | Marat Dukhan <marat@fb.com> | 2018-12-19 01:38:28 -0800 |
---|---|---|
committer | Marat Dukhan <marat@fb.com> | 2018-12-19 01:38:28 -0800 |
commit | a281cc9278b0ccaf8cfd607e8cbc56d194029b9d (patch) | |
tree | e3f06ceefdd1dca7e445dbf2907c2ffd53f2e35d | |
parent | 8ecabcea22d67f6ce39283f8ad7449cf1d398b33 (diff) | |
download | cpuinfo-a281cc9278b0ccaf8cfd607e8cbc56d194029b9d.tar.gz |
Huawei Mate 20 mock test
-rw-r--r-- | CMakeLists.txt | 5 | ||||
-rwxr-xr-x | scripts/android-arm64-mock.sh | 2 | ||||
-rwxr-xr-x | scripts/android-armv7-mock.sh | 2 | ||||
-rw-r--r-- | src/arm/cache.c | 123 | ||||
-rw-r--r-- | src/arm/linux/aarch32-isa.c | 28 | ||||
-rw-r--r-- | src/arm/linux/aarch64-isa.c | 14 | ||||
-rw-r--r-- | src/arm/linux/api.h | 1 | ||||
-rw-r--r-- | src/arm/linux/init.c | 2 | ||||
-rw-r--r-- | test/arm-cache.cc | 50 | ||||
-rw-r--r-- | test/build.prop/huawei-mate-20.log | 276 | ||||
-rw-r--r-- | test/cpuinfo/huawei-mate-20.armeabi.log | 79 | ||||
-rw-r--r-- | test/cpuinfo/huawei-mate-20.log | 72 | ||||
-rw-r--r-- | test/mock/huawei-mate-20.cc | 844 | ||||
-rw-r--r-- | test/mock/huawei-mate-20.h | 4329 |
14 files changed, 5799 insertions, 28 deletions
diff --git a/CMakeLists.txt b/CMakeLists.txt index 4edc26d..414a330 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -564,6 +564,11 @@ IF(CPUINFO_SUPPORTED_PLATFORM AND CPUINFO_BUILD_MOCK_TESTS) TARGET_LINK_LIBRARIES(huawei-mate-10-test PRIVATE cpuinfo_mock gtest) ADD_TEST(huawei-mate-10-test huawei-mate-10-test) + ADD_EXECUTABLE(huawei-mate-20-test test/mock/huawei-mate-20.cc) + TARGET_INCLUDE_DIRECTORIES(huawei-mate-20-test BEFORE PRIVATE test/mock) + TARGET_LINK_LIBRARIES(huawei-mate-20-test PRIVATE cpuinfo_mock gtest) + ADD_TEST(huawei-mate-20-test huawei-mate-20-test) + ADD_EXECUTABLE(huawei-p8-lite-test test/mock/huawei-p8-lite.cc) TARGET_INCLUDE_DIRECTORIES(huawei-p8-lite-test BEFORE PRIVATE test/mock) TARGET_LINK_LIBRARIES(huawei-p8-lite-test PRIVATE cpuinfo_mock gtest) diff --git a/scripts/android-arm64-mock.sh b/scripts/android-arm64-mock.sh index 326053d..a5ad2e2 100755 --- a/scripts/android-arm64-mock.sh +++ b/scripts/android-arm64-mock.sh @@ -15,6 +15,7 @@ adb push build/android/arm64-v8a/galaxy-s9-us-test /data/local/tmp/galaxy-s9-us- adb push build/android/arm64-v8a/huawei-mate-8-test /data/local/tmp/huawei-mate-8-test adb push build/android/arm64-v8a/huawei-mate-9-test /data/local/tmp/huawei-mate-9-test adb push build/android/arm64-v8a/huawei-mate-10-test /data/local/tmp/huawei-mate-10-test +adb push build/android/arm64-v8a/huawei-mate-20-test /data/local/tmp/huawei-mate-20-test adb push build/android/arm64-v8a/huawei-p8-lite-test /data/local/tmp/huawei-p8-lite-test adb push build/android/arm64-v8a/huawei-p9-lite-test /data/local/tmp/huawei-p9-lite-test adb push build/android/arm64-v8a/huawei-p20-pro-test /data/local/tmp/huawei-p20-pro-test @@ -53,6 +54,7 @@ adb shell "/data/local/tmp/galaxy-s9-us-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-mate-8-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-mate-9-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-mate-10-test --gtest_color=yes" +adb shell "/data/local/tmp/huawei-mate-20-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-p8-lite-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-p9-lite-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-p20-pro-test --gtest_color=yes" diff --git a/scripts/android-armv7-mock.sh b/scripts/android-armv7-mock.sh index 1d45a67..1bcf23d 100755 --- a/scripts/android-armv7-mock.sh +++ b/scripts/android-armv7-mock.sh @@ -34,6 +34,7 @@ adb push build/android/armeabi-v7a/huawei-honor-6-test /data/local/tmp/huawei-ho adb push build/android/armeabi-v7a/huawei-mate-8-test /data/local/tmp/huawei-mate-8-test adb push build/android/armeabi-v7a/huawei-mate-9-test /data/local/tmp/huawei-mate-9-test adb push build/android/armeabi-v7a/huawei-mate-10-test /data/local/tmp/huawei-mate-10-test +adb push build/android/armeabi-v7a/huawei-mate-20-test /data/local/tmp/huawei-mate-20-test adb push build/android/armeabi-v7a/huawei-p8-lite-test /data/local/tmp/huawei-p8-lite-test adb push build/android/armeabi-v7a/huawei-p9-lite-test /data/local/tmp/huawei-p9-lite-test adb push build/android/armeabi-v7a/huawei-p20-pro-test /data/local/tmp/huawei-p20-pro-test @@ -108,6 +109,7 @@ adb shell "/data/local/tmp/huawei-honor-6-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-mate-8-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-mate-9-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-mate-10-test --gtest_color=yes" +adb shell "/data/local/tmp/huawei-mate-20-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-p8-lite-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-p9-lite-test --gtest_color=yes" adb shell "/data/local/tmp/huawei-p20-pro-test --gtest_color=yes" diff --git a/src/arm/cache.c b/src/arm/cache.c index c972a2d..5ada7d9 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -690,10 +690,12 @@ void cpuinfo_arm_decode_cache( * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * | Snapdragon 845 | 4(+4) | 32K | 32K | 128K | 2M | [1], sysfs | * | Exynos 9810 | 4(+4) | ? | ? | None | 512K | [2] | + * | Kirin 980 | 4(+4) | 32K | 32K | 128K | 4M | [3] | * +--------------------+-------+-----------+-----------+-----------+----------+------------+ * * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc * [2] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results + * [3] https://en.wikichip.org/wiki/hisilicon/kirin/980 */ if (midr_is_qualcomm_cortex_a55_silver(midr)) { /* Qualcomm-modified Cortex-A55 in Snapdragon 710 / 845 */ @@ -712,22 +714,22 @@ void cpuinfo_arm_decode_cache( *l1i = (struct cpuinfo_cache) { .size = 32 * 1024, .associativity = 4, - .line_size = 64 + .line_size = 64, }; *l1d = (struct cpuinfo_cache) { .size = 32 * 1024, .associativity = 4, - .line_size = 64 + .line_size = 64, }; *l2 = (struct cpuinfo_cache) { .size = 128 * 1024, .associativity = 4, - .line_size = 64 + .line_size = 64, }; *l3 = (struct cpuinfo_cache) { .size = l3_size, .associativity = 16, - .line_size = 64 + .line_size = 64, }; } else { /* Standard Cortex-A55 */ @@ -735,18 +737,44 @@ void cpuinfo_arm_decode_cache( *l1i = (struct cpuinfo_cache) { .size = 32 * 1024, .associativity = 4, - .line_size = 64 + .line_size = 64, }; *l1d = (struct cpuinfo_cache) { .size = 32 * 1024, .associativity = 4, - .line_size = 64 - }; - *l2 = (struct cpuinfo_cache) { - .size = 512 * 1024, - .associativity = 16, - .line_size = 64 + .line_size = 64, }; + if (chipset->series == cpuinfo_arm_chipset_series_samsung_exynos) { + *l2 = (struct cpuinfo_cache) { + .size = 512 * 1024, + /* DynamIQ */ + .associativity = 16, + .line_size = 64, + }; + } else { + uint32_t l3_size = 1024 * 1024; + switch (chipset->series) { + case cpuinfo_arm_chipset_series_hisilicon_kirin: + /* Kirin 980: 4M L3 cache */ + if (chipset->model == 980) { + l3_size = 4 * 1024 * 1024; + } + break; + default: + break; + } + *l2 = (struct cpuinfo_cache) { + .size = 128 * 1024, + .associativity = 4, + .line_size = 64, + }; + *l3 = (struct cpuinfo_cache) { + .size = l3_size, + /* DynamIQ */ + .associativity = 16, + .line_size = 64, + }; + } } break; case cpuinfo_uarch_cortex_a57: @@ -1018,6 +1046,79 @@ void cpuinfo_arm_decode_cache( }; break; } + case cpuinfo_uarch_cortex_a76: + { + /* + * ARM Cortex-A76 Core Technical Reference Manual + * A6.1. About the L1 memory system + * The L1 memory system consists of separate instruction and data caches. Both have a fixed size of 64KB. + * + * A6.1.1 L1 instruction-side memory system + * The L1 instruction memory system has the following key features: + * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, + * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * - Fixed cache line length of 64 bytes. + * + * A6.1.2 L1 data-side memory system + * The L1 data memory system has the following features: + * - Virtually Indexed, Physically Tagged (VIPT), which behaves as a Physically Indexed, + * Physically Tagged (PIPT) 4-way set-associative L1 data cache. + * - Fixed cache line length of 64 bytes. + * - Pseudo-LRU cache replacement policy. + * + * A7.1 About the L2 memory system + * The L2 memory subsystem consist of: + * - An 8-way set associative L2 cache with a configurable size of 128KB, 256KB or 512KB. + * Cache lines have a fixed length of 64 bytes. + * - Strictly inclusive with L1 data cache. Weakly inclusive with L1 instruction cache. + * - Dynamic biased replacement policy. + * - Modified Exclusive Shared Invalid (MESI) coherency. + * + * +--------------------+-------+-----------+-----------+-----------+----------+------------+ + * | Processor model | Cores | L1D cache | L1I cache | L2 cache | L3 cache | Reference | + * +--------------------+-------+-----------+-----------+-----------+----------+------------+ + * | Kirin 980 | 4(+4) | 64K | 64K | 512K | 4M | [1], [2] | + * +--------------------+-------+-----------+-----------+-----------+----------+------------+ + * + * [1] https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm + * [2] https://en.wikichip.org/wiki/hisilicon/kirin/980 + */ + uint32_t l2_size = 256 * 1024; + uint32_t l3_size = 1024 * 1024; + switch (chipset->series) { + case cpuinfo_arm_chipset_series_hisilicon_kirin: + /* Kirin 980: 512K L2 cache + 4M L3 cache */ + if (chipset->model == 980) { + l2_size = 512 * 1024; + l3_size = 4 * 1024 * 1024; + } + break; + default: + break; + } + *l1i = (struct cpuinfo_cache) { + .size = 64 * 1024, + .associativity = 4, + .line_size = 64, + }; + *l1d = (struct cpuinfo_cache) { + .size = 64 * 1024, + .associativity = 4, + .line_size = 64, + }; + *l2 = (struct cpuinfo_cache) { + .size = l2_size, + .associativity = 8, + .line_size = 64, + .flags = CPUINFO_CACHE_INCLUSIVE, + }; + *l3 = (struct cpuinfo_cache) { + .size = l3_size, + .associativity = 16, + .line_size = 64, + }; + break; + } #if CPUINFO_ARCH_ARM && !defined(__ARM_ARCH_8A__) case cpuinfo_uarch_scorpion: /* diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index 1a6d8a4..d552ca2 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -30,6 +30,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( uint32_t midr, uint32_t architecture_version, uint32_t architecture_flags, + const struct cpuinfo_arm_chipset chipset[restrict static 1], struct cpuinfo_arm_isa isa[restrict static 1]) { if (architecture_version >= 8) { @@ -52,29 +53,26 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->neon = true; /* - * NEON FP16 compute extension is not indicated in /proc/cpuinfo. + * NEON FP16 compute extension and VQRDMLAH/VQRDMLSH instructions are not indicated in /proc/cpuinfo. * Use a MIDR-based heuristic to whitelist processors known to support it: - * - Processors with Qualcomm-modified Cortex-A75 and Cortex-A55 cores + * - Processors with Qualcomm-modified Cortex-A55 cores + * - Processors with Qualcomm-modified Cortex-A75 cores + * - Processors with Qualcomm-modified Cortex-A76 cores + * - Kirin 980 processor */ switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */ case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */ - case UINT32_C(0x51008040): /* Qualcomm Cortex-A76 */ + case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ isa->fp16arith = true; - break; - } - - /* - * NEON VQRDMLAH/VQRDMLSH instructions are not indicated in /proc/cpuinfo. - * Use a MIDR-based heuristic to whitelist processors known to support it: - * - Processors with Qualcomm-modified Cortex-A75 and Cortex-A55 cores - */ - switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { - case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */ - case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */ - case UINT32_C(0x51008040): /* Qualcomm Cortex-A76 */ isa->rdm = true; break; + default: + if (chipset->series == cpuinfo_arm_chipset_series_hisilicon_kirin && chipset->model == 980) { + isa->fp16arith = true; + isa->rdm = true; + } + break; } } else { /* ARMv7 or lower: use feature flags to detect optional features */ diff --git a/src/arm/linux/aarch64-isa.c b/src/arm/linux/aarch64-isa.c index 697a047..462aee5 100644 --- a/src/arm/linux/aarch64-isa.c +++ b/src/arm/linux/aarch64-isa.c @@ -41,16 +41,28 @@ void cpuinfo_arm64_linux_decode_isa_from_proc_cpuinfo( } else if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDHP) { cpuinfo_log_warning("FP16 arithmetics disabled: detected support only for SIMD operations"); } - /* Qualcomm Kryo 385 may have buggy kernel configuration that doesn't report VQRDMLAH/VQRDMLSH instructions */ + /* + * Many phones ship with an old kernel configuration that doesn't report + * SQRDMLAH/SQRDMLSH/UQRDMLAH/UQRDMLSH instructions. + * Use a MIDR-based heuristic to whitelist processors known to support it: + * - Processors with Qualcomm-modified Cortex-A55 cores + * - Processors with Qualcomm-modified Cortex-A75 cores + * - Processors with Qualcomm-modified Cortex-A76 cores + * - Kirin 980 processor + */ switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { case UINT32_C(0x51008020): /* Kryo 385 Gold (Cortex-A75) */ case UINT32_C(0x51008030): /* Kryo 385 Silver (Cortex-A55) */ + case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ isa->rdm = true; break; default: if (features & CPUINFO_ARM_LINUX_FEATURE_ASIMDRDM) { isa->rdm = true; } + if (chipset->series == cpuinfo_arm_chipset_series_hisilicon_kirin && chipset->model == 980) { + isa->rdm = true; + } break; } if (features & CPUINFO_ARM_LINUX_FEATURE_JSCVT) { diff --git a/src/arm/linux/api.h b/src/arm/linux/api.h index 36e3200..73d56df 100644 --- a/src/arm/linux/api.h +++ b/src/arm/linux/api.h @@ -261,6 +261,7 @@ CPUINFO_INTERNAL bool cpuinfo_arm_linux_parse_proc_cpuinfo( uint32_t midr, uint32_t architecture_version, uint32_t architecture_flags, + const struct cpuinfo_arm_chipset chipset[restrict static 1], struct cpuinfo_arm_isa isa[restrict static 1]); #elif CPUINFO_ARCH_ARM64 CPUINFO_INTERNAL uint32_t cpuinfo_arm_linux_hwcap_from_getauxval(void); diff --git a/src/arm/linux/init.c b/src/arm/linux/init.c index 23dc762..a297f63 100644 --- a/src/arm/linux/init.c +++ b/src/arm/linux/init.c @@ -273,7 +273,7 @@ void cpuinfo_arm_linux_init(void) { cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa_features, isa_features2, last_midr, last_architecture_version, last_architecture_flags, - &cpuinfo_isa); + &chipset, &cpuinfo_isa); #elif CPUINFO_ARCH_ARM64 /* getauxval is always available on ARM64 Android */ const uint32_t isa_features = cpuinfo_arm_linux_hwcap_from_getauxval(); diff --git a/test/arm-cache.cc b/test/arm-cache.cc index a0af6f0..a58b826 100644 --- a/test/arm-cache.cc +++ b/test/arm-cache.cc @@ -1326,6 +1326,56 @@ TEST(HISILICON, kirin_970) { EXPECT_EQ(0, little_l3.size); } +TEST(HISILICON, kirin_980) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_hisilicon, + .series = cpuinfo_arm_chipset_series_hisilicon_kirin, + .model = 980, + }; + + struct cpuinfo_cache big_l1i = { 0 }; + struct cpuinfo_cache big_l1d = { 0 }; + struct cpuinfo_cache big_l2 = { 0 }; + struct cpuinfo_cache big_l3 = { 0 }; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a76, 2, UINT32_C(0x481FD400), + &chipset, 0, 2, + &big_l1i, &big_l1d, &big_l2, &big_l3); + + struct cpuinfo_cache middle_l1i = { 0 }; + struct cpuinfo_cache middle_l1d = { 0 }; + struct cpuinfo_cache middle_l2 = { 0 }; + struct cpuinfo_cache middle_l3 = { 0 }; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a76, 2, UINT32_C(0x481FD400), + &chipset, 1, 2, + &middle_l1i, &middle_l1d, &middle_l2, &middle_l3); + + struct cpuinfo_cache little_l1i = { 0 }; + struct cpuinfo_cache little_l1d = { 0 }; + struct cpuinfo_cache little_l2 = { 0 }; + struct cpuinfo_cache little_l3 = { 0 }; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a55, 4, UINT32_C(0x411FD050), + &chipset, 2, 4, + &little_l1i, &little_l1d, &little_l2, &little_l3); + + EXPECT_EQ(64 * 1024, big_l1i.size); + EXPECT_EQ(64 * 1024, big_l1d.size); + EXPECT_EQ(512 * 1024, big_l2.size); + EXPECT_EQ(4 * 1024 * 1024, big_l3.size); + + EXPECT_EQ(64 * 1024, middle_l1i.size); + EXPECT_EQ(64 * 1024, middle_l1d.size); + EXPECT_EQ(512 * 1024, middle_l2.size); + EXPECT_EQ(4 * 1024 * 1024, middle_l3.size); + + EXPECT_EQ(32 * 1024, little_l1i.size); + EXPECT_EQ(32 * 1024, little_l1d.size); + EXPECT_EQ(128 * 1024, little_l2.size); + EXPECT_EQ(4 * 1024 * 1024, little_l3.size); +} + #if CPUINFO_ARCH_ARM TEST(NVIDIA, tegra_ap20h) { const struct cpuinfo_arm_chipset chipset = { diff --git a/test/build.prop/huawei-mate-20.log b/test/build.prop/huawei-mate-20.log new file mode 100644 index 0000000..8555cc7 --- /dev/null +++ b/test/build.prop/huawei-mate-20.log @@ -0,0 +1,276 @@ + +# begin build properties +# autogenerated by buildinfo.sh +ro.build.id=NRD90M +### +ro.build.version.incremental=eng.root.20180112.175428 +ro.build.version.sdk=24 +ro.build.version.preview_sdk=0 +ro.build.version.codename=REL +ro.build.version.all_codenames=REL +ro.build.version.release=7.0 +ro.build.version.security_patch=2017-12-05 +ro.build.version.base_os= +ro.build.date=Fri Jan 12 17:54:28 CST 2018 +ro.build.date.utc=1515750868 +ro.build.type=user +ro.build.user=root +ro.build.host=lxh +ro.build.tags=release-keys +ro.build.flavor=k500_lgt_511-user +ro.product.model=T5c +ro.product.brand=LEAGOO +ro.product.name=T5c +ro.product.device=T5c +ro.product.board=k500_lgt_511_vmm +# ro.product.cpu.abi and ro.product.cpu.abi2 are obsolete, +# use ro.product.cpu.abilist instead. +ro.product.cpu.abi=x86_64 +ro.product.cpu.abilist=x86_64,x86,armeabi-v7a,armeabi,arm64-v8a +ro.product.cpu.abilist32=x86,armeabi-v7a,armeabi +ro.product.cpu.abilist64=x86_64,arm64-v8a +ro.product.manufacturer=LEAGOO +ro.product.locale=en-US +ro.wifi.channels= +ro.board.platform=sp9853i +# ro.build.product is obsolete; use ro.product.device +ro.build.product=T5c +# Do not try to parse description, fingerprint, or thumbprint +ro.build.description=k500_lgt_511-user 7.0 NRD90M eng.root.20180112.175428 release-keys +ro.build.fingerprint=LEAGOO/T5c/T5c:7.0/NRD90M/01121754:user/release-keys +ro.build.characteristics=nosdcard +# end build properties +# +# from device/sprd/isharkl2/k500_lgt_511/system.prop +# +# Default density config +ro.product.hardware=k500_lgt_511_v1.0.0 +# Set Opengl ES Version 3.2 +ro.opengles.version=196610 + + +#enable audio nr tuning +ro.audio_tunning.nr=1 + +#enable audio dual spk tuning +ro.audio_tunning.dual_spk=0 + + +ro.fm.chip.port.UART.androidm=false + +persist.sys.cam.eois.dc.back=false +persist.sys.cam.eois.dc.front=false +persist.sys.cam.eois.dv.back=true +persist.sys.cam.eois.dv.front=false +persist.sys.cam.pipviv=false + +persist.sys.cam.battery.flash=15 + +#FRP property for pst device +ro.frp.pst=/dev/block/platform/sdio_emmc/by-name/persist + +persist.sys.cam.refocus.enable=false +persist.sys.cam.ba.blur.version=0 +persist.sys.cam.api.version=1 + +persist.sys.blending.enable=true + +persist.sys.sprd.refocus.bokeh=true +qemu.hw.mainkeys=0 + +#Enable sdcardfs feature +ro.sys.sdcardfs=true +persist.sys.sdcardfs=force_on +persist.bindcore.hdr=_4_0_1_2_3 + +#disable partial update +debug.hwui.use_partial_updates=false + +persist.sys.fp.ck.period=3 +# +# from device/sprd/isharkl2/k500_lgt_511/custom_config/custom.prop +# +ro.macro.custom.leagoo=true +ro.com.google.clientidbase=android-leagoo +ro.build.display.id=LEAGOO_T5c_OS2.1_E_20180112 +ro.build.display.spid=SC9853_K500_LGT_511_V2.2_20180112 +ro.build.display.spid.customer=LEAGOO_T5c_OS2.1_E_20180112 +ro.leagoo.baseband.version=LEAGOO T5c_OS2.1 +ro.product.bt.name=LEAGOO T5c +ro.leagoo.storage.ui=true +ro.modify.settings.icon=true +ro.lock.disable.statusbar=true +ro.leagoo.power.ui=true +ro.message.wake.up.screen=false +ro.sim.no.switch.languages=true +ro.test.playsound.outside=true +ro.hide.smart.control=true +persist.sys.fp.ck.period=3 +ro.single.point.y.index=150 +ro.email.signatures.same=true +ro.modify.message.notify=true +ro.temp.ntc=true +ro.disable.sound.effects=true +ro.not.support.menu.key=true +ro.not.support.back.key=true +ro.not.support.home.key=true +ro.ram.display.config.3gb=true +ro.rm.calllog.geocode=true +ro.preload.media.internel=true +ro.support.video.dream=true +# +# ADDITIONAL_BUILD_PROPERTIES +# +persist.radio.modem.config=TL_LF_TD_W_G,W_G +persist.radio.modem.workmode=9,255 +ro.radio.modem.capability=TL_LF_TD_W_G,W_G +ro.dalvik.vm.isa.arm=x86 +ro.enable.native.bridge.exec=1 +ro.dalvik.vm.isa.arm64=x86_64 +ro.enable.native.bridge.exec64=1 +ro.sys.prc_compatibility=1 +ro.hwui.layer_cache_size=48 +ro.hwui.r_buffer_cache_size=8 +ro.hwui.path_cache_size=32 +ro.hwui.gradient_cache_size=1 +ro.hwui.drop_shadow_cache_size=6 +ro.hwui.texture_cache_flushrate=0.4 +ro.hwui.text_small_cache_width=1024 +ro.hwui.text_small_cache_height=1024 +ro.hwui.text_large_cache_width=2048 +ro.hwui.text_large_cache_height=1024 +dalvik.vm.sprd_usejitprofiles=false +ro.config.notification_sound=LEAGOO-Pops.mp3 +ro.config.alarm_alert=Alarm_Classic.ogg +ro.config.ringtone=LEAGOO-Turkish.mp3 +ro.config.ringtone0=LEAGOO-Turkish.mp3 +ro.config.ringtone1=LEAGOO-Turkish.mp3 +ro.config.message_sound0=Argon.ogg +ro.config.message_sound1=Argon.ogg +ro.config.message_sound=pixiedust.ogg +ro.product.locale.language=en +ro.product.locale.region=US +persist.sys.timezone=Asia/Calcutta +persist.sys.defaulttimezone=Asia/Calcutta +ro.product.first_api_level=24 +ro.carrier=unknown +rild.libpath=/system/lib64/libsprd-ril.so +ro.radio.modemtype=l +ro.telephony.default_network=9 +keyguard.no_require_sim=true +ro.com.android.dataroaming=false +ro.simlock.unlock.autoshow=1 +ro.simlock.unlock.bynv=0 +ro.simlock.onekey.lock=0 +persist.sys.engpc.disable=1 +persist.sys.sprd.modemreset=1 +ro.product.partitionpath=/dev/block/platform/sdio_emmc/by-name/ +ro.modem.l.dev=/proc/cptl/ +ro.modem.l.tty=/dev/stty_lte +ro.modem.l.diag=/dev/sdiag_lte +ro.modem.l.log=/dev/slog_lte +ro.modem.l.assert=/dev/spipe_lte2 +ro.modem.l.fixnv_size=0xc8000 +ro.modem.l.runnv_size=0xe8000 +ro.sp.log=/dev/slog_pm +persist.modem.l.nvp=l_ +persist.modem.l.enable=1 +ro.storage.flash_type=2 +sys.internal.emulated=1 +persist.storage.type=2 +ro.storage.install2internal=0 +drm.service.enabled=true +persist.sys.sprd.wcnreset=1 +persist.sys.start_udpdatastall=0 +persist.sys.apr.enabled=0 +persist.sys.ag.enable=false +ro.adb.secure=1 +persist.sys.apr.intervaltime=1 +persist.sys.apr.testgroup=CSSLAB +persist.sys.apr.autoupload=1 +ro.modem.l.eth=seth_lte +ro.modem.l.snd=1 +ro.modem.l.loop=/dev/spipe_lte0 +ro.modem.l.nv=/dev/spipe_lte1 +ro.modem.l.vbc=/dev/spipe_lte6 +ro.modem.l.id=0 +persist.sys.heartbeat.enable=1 +persist.sys.powerHint.enable=1 +persist.ylog.modem.shutdownlog=1 +persist.sys.cam.photo.gallery=true +persist.sys.ucam.puzzle=false +persist.sys.ucam.edit=false +persist.sys.cam.timestamp=false +persist.sys.cam.gif=false +persist.sys.cam.scenery=false +persist.sys.cam.vgesture=false +persist.sys.cam.gps=true +persist.sys.cam.normalhdr=true +persist.sys.cam.sfv.alter=true +persist.sys.cam.arcsoft.filter=true +persist.sys.cam.filter.highfps=true +persist.sys.cam.new.wideangle=true +persist.sys.cam.3dnr=true +persist.sys.bsservice.enable=1 +ro.wcn.hardware.product=marlin2 +ro.bt.bdaddr_path=/data/misc/bluedroid/btmac.txt +persist.sys.volte.enable=true +ro.trim.config=true +persist.sys.vilte.socket=ap +persist.dbg.wfc_avail_ovr=1 +persist.sys.vowifi.voice=cp +ro.modem.wcn.enable=1 +ro.modem.wcn.diag=/dev/slog_wcn +ro.modem.wcn.id=1 +ro.modem.wcn.count=1 +ro.modem.l.count=2 +persist.msms.phone_count=2 +persist.radio.multisim.config=dsds +ro.modem.gnss.diag=/dev/slog_gnss +persist.sys.support.vt=true +persist.sys.csvt=false +persist.radio.ssda.mode=csfb +ro.wcn.gpschip=ge2 +ro.hotspot.enabled=1 +reset_default_http_response=true +ro.void_charge_tip=true +ro.softaplte.coexist=true +ro.vowifi.softap.ee_warning=false +persist.sys.wifi.pocketmode=true +ro.wcn=enabled +ro.softap.whitelist=true +ro.btwifisoftap.coexist=true +persist.wifi.func.hidessid=true +ro.wifi.softap.maxstanum=10 +ro.wifi.signal.optimized=true +ro.support.auto.roam=disabled +ro.wifip2p.coexist=true +persist.sys.notify.light.color=1 +persist.sys.charging.tone=1 +persist.support.fingerprint=true +persist.sprd.fp.lockapp=true +persist.sprd.fp.launchapp=true +persist.sys.volte.mode=Normal +ro.setupwizard.mode=OPTIONAL +ro.com.google.gmsversion=7.0_r12 +ro.launcher.circleslide=true +ro.launcher.shakewallpaper=true +ro.launcher.defaultfoldername=true +ro.launcher.unreadinfo=true +ro.launcher.dynamicicon=true +ro.launcher.dynamicclock=true +ro.launcher.dynamiccalendar=true +ril.sim.phone_ex.start=true +persist.netmon.linger=10000 +persist.sys.dalvik.vm.lib.2=libart.so +dalvik.vm.isa.x86_64.variant=silvermont +dalvik.vm.isa.x86_64.features=default +dalvik.vm.isa.x86.variant=silvermont +dalvik.vm.isa.x86.features=default +net.bt.name=Android +dalvik.vm.stack-trace-file=/data/anr/traces.txt + +# begin redstonefota properties +ro.redstone.version=LEAGOO_T5c_OS2.1_E_20180112 +# end fota properties +ro.expect.recovery_id=0x0041a640e4805f06ee66e08584f90e9343c058db000000000000000000000000 diff --git a/test/cpuinfo/huawei-mate-20.armeabi.log b/test/cpuinfo/huawei-mate-20.armeabi.log new file mode 100644 index 0000000..f9541d4 --- /dev/null +++ b/test/cpuinfo/huawei-mate-20.armeabi.log @@ -0,0 +1,79 @@ +processor : 0 +model name : ARMv8 Processor rev 0 (v8l) +BogoMIPS : 3.84 +Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd05 +CPU revision : 0 + +processor : 1 +model name : ARMv8 Processor rev 0 (v8l) +BogoMIPS : 3.84 +Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd05 +CPU revision : 0 + +processor : 2 +model name : ARMv8 Processor rev 0 (v8l) +BogoMIPS : 3.84 +Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd05 +CPU revision : 0 + +processor : 3 +model name : ARMv8 Processor rev 0 (v8l) +BogoMIPS : 3.84 +Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd05 +CPU revision : 0 + +processor : 4 +model name : ARMv8 Processor rev 0 (v8l) +BogoMIPS : 3.84 +Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x48 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd40 +CPU revision : 0 + +processor : 5 +model name : ARMv8 Processor rev 0 (v8l) +BogoMIPS : 3.84 +Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x48 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd40 +CPU revision : 0 + +processor : 6 +model name : ARMv8 Processor rev 0 (v8l) +BogoMIPS : 3.84 +Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x48 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd40 +CPU revision : 0 + +processor : 7 +model name : ARMv8 Processor rev 0 (v8l) +BogoMIPS : 3.84 +Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32 +CPU implementer : 0x48 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd40 +CPU revision : 0 diff --git a/test/cpuinfo/huawei-mate-20.log b/test/cpuinfo/huawei-mate-20.log new file mode 100644 index 0000000..c6b7f9d --- /dev/null +++ b/test/cpuinfo/huawei-mate-20.log @@ -0,0 +1,72 @@ +processor : 0 +BogoMIPS : 3.84 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd05 +CPU revision : 0 + +processor : 1 +BogoMIPS : 3.84 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd05 +CPU revision : 0 + +processor : 2 +BogoMIPS : 3.84 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd05 +CPU revision : 0 + +processor : 3 +BogoMIPS : 3.84 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp +CPU implementer : 0x41 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd05 +CPU revision : 0 + +processor : 4 +BogoMIPS : 3.84 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp +CPU implementer : 0x48 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd40 +CPU revision : 0 + +processor : 5 +BogoMIPS : 3.84 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp +CPU implementer : 0x48 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd40 +CPU revision : 0 + +processor : 6 +BogoMIPS : 3.84 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp +CPU implementer : 0x48 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd40 +CPU revision : 0 + +processor : 7 +BogoMIPS : 3.84 +Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp +CPU implementer : 0x48 +CPU architecture: 8 +CPU variant : 0x1 +CPU part : 0xd40 +CPU revision : 0 + diff --git a/test/mock/huawei-mate-20.cc b/test/mock/huawei-mate-20.cc new file mode 100644 index 0000000..e3d4d36 --- /dev/null +++ b/test/mock/huawei-mate-20.cc @@ -0,0 +1,844 @@ +#include <gtest/gtest.h> + +#include <cpuinfo.h> +#include <cpuinfo-mock.h> + + +TEST(PROCESSORS, count) { + ASSERT_EQ(8, cpuinfo_get_processors_count()); +} + +TEST(PROCESSORS, non_null) { + ASSERT_TRUE(cpuinfo_get_processors()); +} + +TEST(PROCESSORS, smt_id) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + ASSERT_EQ(0, cpuinfo_get_processor(i)->smt_id); + } +} + +TEST(PROCESSORS, core) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + ASSERT_EQ(cpuinfo_get_core(i), cpuinfo_get_processor(i)->core); + } +} + +TEST(PROCESSORS, cluster) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + switch (i) { + case 0: + case 1: + ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_processor(i)->cluster); + break; + case 2: + case 3: + ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_processor(i)->cluster); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(cpuinfo_get_cluster(2), cpuinfo_get_processor(i)->cluster); + break; + } + } +} + +TEST(PROCESSORS, package) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_processor(i)->package); + } +} + +TEST(PROCESSORS, linux_id) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + switch (i) { + case 0: + case 1: + ASSERT_EQ(i + 6, cpuinfo_get_processor(i)->linux_id); + break; + case 2: + case 3: + ASSERT_EQ(i + 2, cpuinfo_get_processor(i)->linux_id); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(i - 4, cpuinfo_get_processor(i)->linux_id); + break; + } + } +} + +TEST(PROCESSORS, l1i) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + ASSERT_EQ(cpuinfo_get_l1i_cache(i), cpuinfo_get_processor(i)->cache.l1i); + } +} + +TEST(PROCESSORS, l1d) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + ASSERT_EQ(cpuinfo_get_l1d_cache(i), cpuinfo_get_processor(i)->cache.l1d); + } +} + +TEST(PROCESSORS, l2) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + ASSERT_EQ(cpuinfo_get_l2_cache(i), cpuinfo_get_processor(i)->cache.l2); + } +} + +TEST(PROCESSORS, l3) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + ASSERT_EQ(cpuinfo_get_l3_cache(0), cpuinfo_get_processor(i)->cache.l3); + } +} + +TEST(PROCESSORS, l4) { + for (uint32_t i = 0; i < cpuinfo_get_processors_count(); i++) { + ASSERT_FALSE(cpuinfo_get_processor(i)->cache.l4); + } +} + +TEST(CORES, count) { + ASSERT_EQ(8, cpuinfo_get_cores_count()); +} + +TEST(CORES, non_null) { + ASSERT_TRUE(cpuinfo_get_cores()); +} + +TEST(CORES, processor_start) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + ASSERT_EQ(i, cpuinfo_get_core(i)->processor_start); + } +} + +TEST(CORES, processor_count) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + ASSERT_EQ(1, cpuinfo_get_core(i)->processor_count); + } +} + +TEST(CORES, core_id) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + ASSERT_EQ(i, cpuinfo_get_core(i)->core_id); + } +} + +TEST(CORES, cluster) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + switch (i) { + case 0: + case 1: + ASSERT_EQ(cpuinfo_get_cluster(0), cpuinfo_get_core(i)->cluster); + break; + case 2: + case 3: + ASSERT_EQ(cpuinfo_get_cluster(1), cpuinfo_get_core(i)->cluster); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(cpuinfo_get_cluster(2), cpuinfo_get_core(i)->cluster); + break; + } + } +} + +TEST(CORES, package) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_core(i)->package); + } +} + +TEST(CORES, vendor) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_core(i)->vendor); + } +} + +TEST(CORES, uarch) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + switch (i) { + case 0: + case 1: + case 2: + case 3: + ASSERT_EQ(cpuinfo_uarch_cortex_a76, cpuinfo_get_core(i)->uarch); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(cpuinfo_uarch_cortex_a55, cpuinfo_get_core(i)->uarch); + break; + } + } +} + +TEST(CORES, midr) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + switch (i) { + case 0: + case 1: + case 2: + case 3: + ASSERT_EQ(UINT32_C(0x481FD400), cpuinfo_get_core(i)->midr); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(UINT32_C(0x411FD050), cpuinfo_get_core(i)->midr); + break; + } + } +} + +TEST(CORES, DISABLED_frequency) { + for (uint32_t i = 0; i < cpuinfo_get_cores_count(); i++) { + switch (i) { + case 0: + case 1: + ASSERT_EQ(UINT64_C(2600000000), cpuinfo_get_core(i)->frequency); + break; + case 2: + case 3: + ASSERT_EQ(UINT64_C(1901000000), cpuinfo_get_core(i)->frequency); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(UINT64_C(1805000000), cpuinfo_get_core(i)->frequency); + break; + } + } +} + +TEST(CLUSTERS, count) { + ASSERT_EQ(3, cpuinfo_get_clusters_count()); +} + +TEST(CLUSTERS, non_null) { + ASSERT_TRUE(cpuinfo_get_clusters()); +} + +TEST(CLUSTERS, processor_start) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + switch (i) { + case 0: + ASSERT_EQ(0, cpuinfo_get_cluster(i)->processor_start); + break; + case 1: + ASSERT_EQ(2, cpuinfo_get_cluster(i)->processor_start); + break; + case 2: + ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_start); + break; + } + } +} + +TEST(CLUSTERS, processor_count) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + switch (i) { + case 0: + case 1: + ASSERT_EQ(2, cpuinfo_get_cluster(i)->processor_count); + break; + case 2: + ASSERT_EQ(4, cpuinfo_get_cluster(i)->processor_count); + break; + } + } +} + +TEST(CLUSTERS, core_start) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + switch (i) { + case 0: + ASSERT_EQ(0, cpuinfo_get_cluster(i)->core_start); + break; + case 1: + ASSERT_EQ(2, cpuinfo_get_cluster(i)->core_start); + break; + case 2: + ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_start); + break; + } + } +} + +TEST(CLUSTERS, core_count) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + switch (i) { + case 0: + case 1: + ASSERT_EQ(2, cpuinfo_get_cluster(i)->core_count); + break; + case 2: + ASSERT_EQ(4, cpuinfo_get_cluster(i)->core_count); + break; + } + } +} + +TEST(CLUSTERS, cluster_id) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + ASSERT_EQ(i, cpuinfo_get_cluster(i)->cluster_id); + } +} + +TEST(CLUSTERS, package) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + ASSERT_EQ(cpuinfo_get_package(0), cpuinfo_get_cluster(i)->package); + } +} + +TEST(CLUSTERS, vendor) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + ASSERT_EQ(cpuinfo_vendor_arm, cpuinfo_get_cluster(i)->vendor); + } +} + +TEST(CLUSTERS, uarch) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + switch (i) { + case 0: + ASSERT_EQ(cpuinfo_uarch_cortex_a76, cpuinfo_get_cluster(i)->uarch); + break; + case 1: + ASSERT_EQ(cpuinfo_uarch_cortex_a76, cpuinfo_get_cluster(i)->uarch); + break; + case 2: + ASSERT_EQ(cpuinfo_uarch_cortex_a55, cpuinfo_get_cluster(i)->uarch); + break; + } + } +} + +TEST(CLUSTERS, midr) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + switch (i) { + case 0: + ASSERT_EQ(UINT32_C(0x481FD400), cpuinfo_get_cluster(i)->midr); + break; + case 1: + ASSERT_EQ(UINT32_C(0x481FD400), cpuinfo_get_cluster(i)->midr); + break; + case 2: + ASSERT_EQ(UINT32_C(0x411FD050), cpuinfo_get_cluster(i)->midr); + break; + } + } +} + +TEST(CLUSTERS, DISABLED_frequency) { + for (uint32_t i = 0; i < cpuinfo_get_clusters_count(); i++) { + switch (i) { + case 0: + ASSERT_EQ(UINT64_C(2600000000), cpuinfo_get_core(i)->frequency); + break; + case 1: + ASSERT_EQ(UINT64_C(1901000000), cpuinfo_get_core(i)->frequency); + break; + case 2: + ASSERT_EQ(UINT64_C(1805000000), cpuinfo_get_core(i)->frequency); + break; + } + } +} + +TEST(PACKAGES, count) { + ASSERT_EQ(1, cpuinfo_get_packages_count()); +} + +TEST(PACKAGES, name) { + for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { + ASSERT_EQ("HiSilicon Kirin 980", + std::string(cpuinfo_get_package(i)->name, + strnlen(cpuinfo_get_package(i)->name, CPUINFO_PACKAGE_NAME_MAX))); + } +} + +TEST(PACKAGES, processor_start) { + for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { + ASSERT_EQ(0, cpuinfo_get_package(i)->processor_start); + } +} + +TEST(PACKAGES, processor_count) { + for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { + ASSERT_EQ(8, cpuinfo_get_package(i)->processor_count); + } +} + +TEST(PACKAGES, core_start) { + for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { + ASSERT_EQ(0, cpuinfo_get_package(i)->core_start); + } +} + +TEST(PACKAGES, core_count) { + for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { + ASSERT_EQ(8, cpuinfo_get_package(i)->core_count); + } +} + +TEST(PACKAGES, cluster_start) { + for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { + ASSERT_EQ(0, cpuinfo_get_package(i)->cluster_start); + } +} + +TEST(PACKAGES, cluster_count) { + for (uint32_t i = 0; i < cpuinfo_get_packages_count(); i++) { + ASSERT_EQ(3, cpuinfo_get_package(i)->cluster_count); + } +} + +TEST(ISA, thumb) { + #if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb()); + #elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb()); + #endif +} + +TEST(ISA, thumb2) { + #if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_thumb2()); + #elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_thumb2()); + #endif +} + +TEST(ISA, armv5e) { + #if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v5e()); + #elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v5e()); + #endif +} + +TEST(ISA, armv6) { + #if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6()); + #elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6()); + #endif +} + +TEST(ISA, armv6k) { + #if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v6k()); + #elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v6k()); + #endif +} + +TEST(ISA, armv7) { + #if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7()); + #elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7()); + #endif +} + +TEST(ISA, armv7mp) { + #if CPUINFO_ARCH_ARM + ASSERT_TRUE(cpuinfo_has_arm_v7mp()); + #elif CPUINFO_ARCH_ARM64 + ASSERT_FALSE(cpuinfo_has_arm_v7mp()); + #endif +} + +TEST(ISA, idiv) { + ASSERT_TRUE(cpuinfo_has_arm_idiv()); +} + +TEST(ISA, vfpv2) { + ASSERT_FALSE(cpuinfo_has_arm_vfpv2()); +} + +TEST(ISA, vfpv3) { + ASSERT_TRUE(cpuinfo_has_arm_vfpv3()); +} + +TEST(ISA, vfpv3_d32) { + ASSERT_TRUE(cpuinfo_has_arm_vfpv3_d32()); +} + +TEST(ISA, vfpv3_fp16) { + ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16()); +} + +TEST(ISA, vfpv3_fp16_d32) { + ASSERT_TRUE(cpuinfo_has_arm_vfpv3_fp16_d32()); +} + +TEST(ISA, vfpv4) { + ASSERT_TRUE(cpuinfo_has_arm_vfpv4()); +} + +TEST(ISA, vfpv4_d32) { + ASSERT_TRUE(cpuinfo_has_arm_vfpv4_d32()); +} + +TEST(ISA, wmmx) { + ASSERT_FALSE(cpuinfo_has_arm_wmmx()); +} + +TEST(ISA, wmmx2) { + ASSERT_FALSE(cpuinfo_has_arm_wmmx2()); +} + +TEST(ISA, neon) { + ASSERT_TRUE(cpuinfo_has_arm_neon()); +} + +TEST(ISA, neon_fp16) { + ASSERT_TRUE(cpuinfo_has_arm_neon_fp16()); +} + +TEST(ISA, neon_fma) { + ASSERT_TRUE(cpuinfo_has_arm_neon_fma()); +} + +TEST(ISA, atomics) { + #if CPUINFO_ARCH_ARM + ASSERT_FALSE(cpuinfo_has_arm_atomics()); + #elif CPUINFO_ARCH_ARM64 + ASSERT_TRUE(cpuinfo_has_arm_atomics()); + #endif +} + +TEST(ISA, neon_rdm) { + ASSERT_TRUE(cpuinfo_has_arm_neon_rdm()); +} + +TEST(ISA, fp16_arith) { + ASSERT_TRUE(cpuinfo_has_arm_fp16_arith()); +} + +TEST(ISA, jscvt) { + ASSERT_FALSE(cpuinfo_has_arm_jscvt()); +} + +TEST(ISA, fcma) { + ASSERT_FALSE(cpuinfo_has_arm_fcma()); +} + +TEST(ISA, aes) { + ASSERT_TRUE(cpuinfo_has_arm_aes()); +} + +TEST(ISA, sha1) { + ASSERT_TRUE(cpuinfo_has_arm_sha1()); +} + +TEST(ISA, sha2) { + ASSERT_TRUE(cpuinfo_has_arm_sha2()); +} + +TEST(ISA, pmull) { + ASSERT_TRUE(cpuinfo_has_arm_pmull()); +} + +TEST(ISA, crc32) { + ASSERT_TRUE(cpuinfo_has_arm_crc32()); +} + +TEST(L1I, count) { + ASSERT_EQ(8, cpuinfo_get_l1i_caches_count()); +} + +TEST(L1I, non_null) { + ASSERT_TRUE(cpuinfo_get_l1i_caches()); +} + +TEST(L1I, size) { + for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { + switch (i) { + case 0: + case 1: + case 2: + case 3: + ASSERT_EQ(64 * 1024, cpuinfo_get_l1i_cache(i)->size); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(32 * 1024, cpuinfo_get_l1i_cache(i)->size); + break; + } + } +} + +TEST(L1I, associativity) { + for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { + ASSERT_EQ(4, cpuinfo_get_l1i_cache(i)->associativity); + } +} + +TEST(L1I, sets) { + for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { + ASSERT_EQ(cpuinfo_get_l1i_cache(i)->size, + cpuinfo_get_l1i_cache(i)->sets * cpuinfo_get_l1i_cache(i)->line_size * cpuinfo_get_l1i_cache(i)->partitions * cpuinfo_get_l1i_cache(i)->associativity); + } +} + +TEST(L1I, partitions) { + for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { + ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->partitions); + } +} + +TEST(L1I, line_size) { + for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { + ASSERT_EQ(64, cpuinfo_get_l1i_cache(i)->line_size); + } +} + +TEST(L1I, flags) { + for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { + ASSERT_EQ(0, cpuinfo_get_l1i_cache(i)->flags); + } +} + +TEST(L1I, processors) { + for (uint32_t i = 0; i < cpuinfo_get_l1i_caches_count(); i++) { + ASSERT_EQ(i, cpuinfo_get_l1i_cache(i)->processor_start); + ASSERT_EQ(1, cpuinfo_get_l1i_cache(i)->processor_count); + } +} + +TEST(L1D, count) { + ASSERT_EQ(8, cpuinfo_get_l1d_caches_count()); +} + +TEST(L1D, non_null) { + ASSERT_TRUE(cpuinfo_get_l1d_caches()); +} + +TEST(L1D, size) { + for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { + switch (i) { + case 0: + case 1: + case 2: + case 3: + ASSERT_EQ(64 * 1024, cpuinfo_get_l1d_cache(i)->size); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(32 * 1024, cpuinfo_get_l1d_cache(i)->size); + break; + } + } +} + +TEST(L1D, associativity) { + for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { + ASSERT_EQ(4, cpuinfo_get_l1d_cache(i)->associativity); + } +} + +TEST(L1D, sets) { + for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { + ASSERT_EQ(cpuinfo_get_l1d_cache(i)->size, + cpuinfo_get_l1d_cache(i)->sets * cpuinfo_get_l1d_cache(i)->line_size * cpuinfo_get_l1d_cache(i)->partitions * cpuinfo_get_l1d_cache(i)->associativity); + } +} + +TEST(L1D, partitions) { + for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { + ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->partitions); + } +} + +TEST(L1D, line_size) { + for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { + ASSERT_EQ(64, cpuinfo_get_l1d_cache(i)->line_size); + } +} + +TEST(L1D, flags) { + for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { + ASSERT_EQ(0, cpuinfo_get_l1d_cache(i)->flags); + } +} + +TEST(L1D, processors) { + for (uint32_t i = 0; i < cpuinfo_get_l1d_caches_count(); i++) { + ASSERT_EQ(i, cpuinfo_get_l1d_cache(i)->processor_start); + ASSERT_EQ(1, cpuinfo_get_l1d_cache(i)->processor_count); + } +} + +TEST(L2, count) { + ASSERT_EQ(8, cpuinfo_get_l2_caches_count()); +} + +TEST(L2, non_null) { + ASSERT_TRUE(cpuinfo_get_l2_caches()); +} + +TEST(L2, size) { + for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { + switch (i) { + case 0: + case 1: + case 2: + case 3: + ASSERT_EQ(512 * 1024, cpuinfo_get_l2_cache(i)->size); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(128 * 1024, cpuinfo_get_l2_cache(i)->size); + break; + } + } +} + +TEST(L2, associativity) { + for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { + switch (i) { + case 0: + case 1: + case 2: + case 3: + ASSERT_EQ(8, cpuinfo_get_l2_cache(i)->associativity); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(4, cpuinfo_get_l2_cache(i)->associativity); + break; + } + } +} + +TEST(L2, sets) { + for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { + ASSERT_EQ(cpuinfo_get_l2_cache(i)->size, + cpuinfo_get_l2_cache(i)->sets * cpuinfo_get_l2_cache(i)->line_size * cpuinfo_get_l2_cache(i)->partitions * cpuinfo_get_l2_cache(i)->associativity); + } +} + +TEST(L2, partitions) { + for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { + ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->partitions); + } +} + +TEST(L2, line_size) { + for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { + ASSERT_EQ(64, cpuinfo_get_l2_cache(i)->line_size); + } +} + +TEST(L2, flags) { + for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { + switch (i) { + case 0: + case 1: + case 2: + case 3: + ASSERT_EQ(CPUINFO_CACHE_INCLUSIVE, cpuinfo_get_l2_cache(i)->flags); + break; + case 4: + case 5: + case 6: + case 7: + ASSERT_EQ(0, cpuinfo_get_l2_cache(i)->flags); + break; + } + } +} + +TEST(L2, processors) { + for (uint32_t i = 0; i < cpuinfo_get_l2_caches_count(); i++) { + ASSERT_EQ(i, cpuinfo_get_l2_cache(i)->processor_start); + ASSERT_EQ(1, cpuinfo_get_l2_cache(i)->processor_count); + } +} + +TEST(L3, count) { + ASSERT_EQ(1, cpuinfo_get_l3_caches_count()); +} + +TEST(L3, non_null) { + ASSERT_TRUE(cpuinfo_get_l3_caches()); +} + +TEST(L3, size) { + for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { + ASSERT_EQ(4 * 1024 * 1024, cpuinfo_get_l3_cache(i)->size); + } +} + +TEST(L3, associativity) { + for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { + ASSERT_EQ(16, cpuinfo_get_l3_cache(i)->associativity); + } +} + +TEST(L3, sets) { + for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { + ASSERT_EQ(cpuinfo_get_l3_cache(i)->size, + cpuinfo_get_l3_cache(i)->sets * cpuinfo_get_l3_cache(i)->line_size * cpuinfo_get_l3_cache(i)->partitions * cpuinfo_get_l3_cache(i)->associativity); + } +} + +TEST(L3, partitions) { + for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { + ASSERT_EQ(1, cpuinfo_get_l3_cache(i)->partitions); + } +} + +TEST(L3, line_size) { + for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { + ASSERT_EQ(64, cpuinfo_get_l3_cache(i)->line_size); + } +} + +TEST(L3, flags) { + for (uint32_t i = 0; i < cpuinfo_get_l3_caches_count(); i++) { + ASSERT_EQ(0, cpuinfo_get_l3_cache(i)->flags); + } +} + +TEST(L4, none) { + ASSERT_EQ(0, cpuinfo_get_l4_caches_count()); + ASSERT_FALSE(cpuinfo_get_l4_caches()); +} + +#include <huawei-mate-20.h> + +int main(int argc, char* argv[]) { +#if CPUINFO_ARCH_ARM + cpuinfo_set_hwcap(UINT32_C(0x0037B0D6)); + cpuinfo_set_hwcap2(UINT32_C(0x0000001F)); +#elif CPUINFO_ARCH_ARM64 + cpuinfo_set_hwcap(UINT32_C(0x000007FF)); +#endif + cpuinfo_mock_filesystem(filesystem); +#ifdef __ANDROID__ + cpuinfo_mock_android_properties(properties); +#endif + cpuinfo_initialize(); + ::testing::InitGoogleTest(&argc, argv); + return RUN_ALL_TESTS(); +} diff --git a/test/mock/huawei-mate-20.h b/test/mock/huawei-mate-20.h new file mode 100644 index 0000000..70e04dd --- /dev/null +++ b/test/mock/huawei-mate-20.h @@ -0,0 +1,4329 @@ +struct cpuinfo_mock_file filesystem[] = { +#if CPUINFO_ARCH_ARM64 + { + .path = "/proc/cpuinfo", + .size = 1608, + .content = + "processor\t: 0\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 1\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 2\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 3\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 4\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 5\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 6\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 7\n" + "BogoMIPS\t: 3.84\n" + "Features\t: fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n", + }, +#elif CPUINFO_ARCH_ARM + { + .path = "/proc/cpuinfo", + .size = 2231, + .content = + "processor\t: 0\n" + "model name\t: ARMv8 Processor rev 0 (v8l)\n" + "BogoMIPS\t: 3.84\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 1\n" + "model name\t: ARMv8 Processor rev 0 (v8l)\n" + "BogoMIPS\t: 3.84\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 2\n" + "model name\t: ARMv8 Processor rev 0 (v8l)\n" + "BogoMIPS\t: 3.84\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 3\n" + "model name\t: ARMv8 Processor rev 0 (v8l)\n" + "BogoMIPS\t: 3.84\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x41\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd05\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 4\n" + "model name\t: ARMv8 Processor rev 0 (v8l)\n" + "BogoMIPS\t: 3.84\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 5\n" + "model name\t: ARMv8 Processor rev 0 (v8l)\n" + "BogoMIPS\t: 3.84\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 6\n" + "model name\t: ARMv8 Processor rev 0 (v8l)\n" + "BogoMIPS\t: 3.84\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n" + "\n" + "processor\t: 7\n" + "model name\t: ARMv8 Processor rev 0 (v8l)\n" + "BogoMIPS\t: 3.84\n" + "Features\t: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt lpae evtstrm aes pmull sha1 sha2 crc32\n" + "CPU implementer\t: 0x48\n" + "CPU architecture: 8\n" + "CPU variant\t: 0x1\n" + "CPU part\t: 0xd40\n" + "CPU revision\t: 0\n", + }, +#endif + { + .path = "/sys/devices/system/cpu/isolated", + .size = 1, + .content = "\n", + }, + { + .path = "/sys/devices/system/cpu/kernel_max", + .size = 2, + .content = "7\n", + }, + { + .path = "/sys/devices/system/cpu/modalias", + .size = 81, + .content = "cpu:type:aarch64:feature:,0000,0001,0002,0003,0004,0005,0006,0007,0008,0009,000A\n", + }, + { + .path = "/sys/devices/system/cpu/offline", + .size = 1, + .content = "\n", + }, + { + .path = "/sys/devices/system/cpu/online", + .size = 4, + .content = "0-7\n", + }, + { + .path = "/sys/devices/system/cpu/possible", + .size = 4, + .content = "0-7\n", + }, + { + .path = "/sys/devices/system/cpu/present", + .size = 4, + .content = "0-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpuidle/current_driver", + .size = 25, + .content = "hisi_middle_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpuidle/current_governor_ro", + .size = 5, + .content = "menu\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpuidle/driver/name", + .size = 25, + .content = "hisi_little_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/affected_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1805000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "830000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_transition_latency", + .size = 8, + .content = "2000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/related_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies", + .size = 87, + .content = "830000 980000 1056000 1152000 1248000 1325000 1421000 1517000 1613000 1709000 1805000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors", + .size = 77, + .content = "interactive conservative ondemand userspace powersave performance schedutil \n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq", + .size = 7, + .content = "830000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/scaling_driver", + .size = 11, + .content = "cpufreq-dt\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/time_in_state", + .size = 139, + .content = + "830000 210230\n" + "980000 5490\n" + "1056000 388\n" + "1152000 777\n" + "1248000 3390\n" + "1325000 800\n" + "1421000 1754\n" + "1517000 673\n" + "1613000 6759\n" + "1709000 1696\n" + "1805000 5590\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/total_trans", + .size = 5, + .content = "9006\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/cpufreq/stats/trans_table", + .size = 1481, + .content = + " From : To\n" + " : 830000 980000 1056000 1152000 1248000 1325000 1421000 1517000 1613000 1709000 1805000 \n" + " 830000: 0 756 0 0 506 65 78 25 374 38 0 \n" + " 980000: 610 0 82 89 211 31 105 12 248 15 0 \n" + " 1056000: 37 33 0 18 55 11 19 5 47 3 0 \n" + " 1152000: 65 56 13 0 96 23 48 14 108 5 0 \n" + " 1248000: 310 133 34 60 0 85 202 18 226 11 0 \n" + " 1325000: 96 49 11 34 24 0 72 20 137 13 0 \n" + " 1421000: 154 74 21 72 41 43 0 107 221 14 0 \n" + " 1517000: 54 21 4 21 6 21 30 0 159 4 0 \n" + " 1613000: 517 281 63 134 140 177 193 119 0 131 19 \n" + " 1709000: 0 0 0 0 0 0 0 0 178 0 266 \n" + " 1805000: 0 0 0 0 0 0 0 0 75 210 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1", + .size = 19, + .content = "0x00000000411fd050\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/regs/identification/revidr_el1", + .size = 19, + .content = "0x000000000000000f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/core_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/core_siblings", + .size = 3, + .content = "0f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/core_siblings_list", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/physical_package_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings", + .size = 3, + .content = "01\n", + }, + { + .path = "/sys/devices/system/cpu/cpu0/topology/thread_siblings_list", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpuidle/driver/name", + .size = 25, + .content = "hisi_little_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/affected_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1805000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "830000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/cpuinfo_transition_latency", + .size = 8, + .content = "2000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/related_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_frequencies", + .size = 87, + .content = "830000 980000 1056000 1152000 1248000 1325000 1421000 1517000 1613000 1709000 1805000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_available_governors", + .size = 77, + .content = "interactive conservative ondemand userspace powersave performance schedutil \n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_cur_freq", + .size = 7, + .content = "830000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/scaling_driver", + .size = 11, + .content = "cpufreq-dt\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/time_in_state", + .size = 139, + .content = + "830000 210358\n" + "980000 5510\n" + "1056000 388\n" + "1152000 777\n" + "1248000 3404\n" + "1325000 800\n" + "1421000 1760\n" + "1517000 673\n" + "1613000 6759\n" + "1709000 1696\n" + "1805000 5590\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/total_trans", + .size = 5, + .content = "9017\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/cpufreq/stats/trans_table", + .size = 1481, + .content = + " From : To\n" + " : 830000 980000 1056000 1152000 1248000 1325000 1421000 1517000 1613000 1709000 1805000 \n" + " 830000: 0 758 0 0 509 65 78 25 374 38 0 \n" + " 980000: 612 0 82 89 211 31 105 12 248 15 0 \n" + " 1056000: 37 33 0 18 55 11 19 5 47 3 0 \n" + " 1152000: 65 56 13 0 96 23 48 14 108 5 0 \n" + " 1248000: 312 133 34 60 0 85 203 18 226 11 0 \n" + " 1325000: 96 49 11 34 24 0 72 20 137 13 0 \n" + " 1421000: 155 74 21 72 41 43 0 107 221 14 0 \n" + " 1517000: 54 21 4 21 6 21 30 0 159 4 0 \n" + " 1613000: 517 281 63 134 140 177 193 119 0 131 19 \n" + " 1709000: 0 0 0 0 0 0 0 0 178 0 266 \n" + " 1805000: 0 0 0 0 0 0 0 0 75 210 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/regs/identification/midr_el1", + .size = 19, + .content = "0x00000000411fd050\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/regs/identification/revidr_el1", + .size = 19, + .content = "0x000000000000000f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/topology/core_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/topology/core_siblings", + .size = 3, + .content = "0f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/topology/core_siblings_list", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/topology/physical_package_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/topology/thread_siblings", + .size = 3, + .content = "02\n", + }, + { + .path = "/sys/devices/system/cpu/cpu1/topology/thread_siblings_list", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpuidle/driver/name", + .size = 25, + .content = "hisi_little_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/affected_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1805000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "830000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/cpuinfo_transition_latency", + .size = 8, + .content = "2000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/related_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_frequencies", + .size = 87, + .content = "830000 980000 1056000 1152000 1248000 1325000 1421000 1517000 1613000 1709000 1805000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_available_governors", + .size = 77, + .content = "interactive conservative ondemand userspace powersave performance schedutil \n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_cur_freq", + .size = 8, + .content = "1421000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/scaling_driver", + .size = 11, + .content = "cpufreq-dt\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/time_in_state", + .size = 139, + .content = + "830000 210488\n" + "980000 5536\n" + "1056000 394\n" + "1152000 777\n" + "1248000 3410\n" + "1325000 800\n" + "1421000 1764\n" + "1517000 673\n" + "1613000 6759\n" + "1709000 1696\n" + "1805000 5590\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/total_trans", + .size = 5, + .content = "9030\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/cpufreq/stats/trans_table", + .size = 1481, + .content = + " From : To\n" + " : 830000 980000 1056000 1152000 1248000 1325000 1421000 1517000 1613000 1709000 1805000 \n" + " 830000: 0 762 0 0 510 65 79 25 374 38 0 \n" + " 980000: 614 0 83 89 212 31 105 12 248 15 0 \n" + " 1056000: 38 33 0 18 55 11 19 5 47 3 0 \n" + " 1152000: 65 56 13 0 96 23 48 14 108 5 0 \n" + " 1248000: 313 133 34 60 0 85 203 18 226 11 0 \n" + " 1325000: 96 49 11 34 24 0 72 20 137 13 0 \n" + " 1421000: 156 74 21 72 41 43 0 107 221 14 0 \n" + " 1517000: 54 21 4 21 6 21 30 0 159 4 0 \n" + " 1613000: 517 281 63 134 140 177 193 119 0 131 19 \n" + " 1709000: 0 0 0 0 0 0 0 0 178 0 266 \n" + " 1805000: 0 0 0 0 0 0 0 0 75 210 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/regs/identification/midr_el1", + .size = 19, + .content = "0x00000000411fd050\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/regs/identification/revidr_el1", + .size = 19, + .content = "0x000000000000000f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/core_id", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/core_siblings", + .size = 3, + .content = "0f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/core_siblings_list", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/physical_package_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/thread_siblings", + .size = 3, + .content = "04\n", + }, + { + .path = "/sys/devices/system/cpu/cpu2/topology/thread_siblings_list", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpuidle/driver/name", + .size = 25, + .content = "hisi_little_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/affected_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1805000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "830000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/cpuinfo_transition_latency", + .size = 8, + .content = "2000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/related_cpus", + .size = 8, + .content = "0 1 2 3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_frequencies", + .size = 87, + .content = "830000 980000 1056000 1152000 1248000 1325000 1421000 1517000 1613000 1709000 1805000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_available_governors", + .size = 77, + .content = "interactive conservative ondemand userspace powersave performance schedutil \n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_cur_freq", + .size = 7, + .content = "980000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/scaling_driver", + .size = 11, + .content = "cpufreq-dt\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/time_in_state", + .size = 139, + .content = + "830000 210606\n" + "980000 5556\n" + "1056000 394\n" + "1152000 785\n" + "1248000 3428\n" + "1325000 800\n" + "1421000 1764\n" + "1517000 673\n" + "1613000 6765\n" + "1709000 1696\n" + "1805000 5590\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/total_trans", + .size = 5, + .content = "9047\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/cpufreq/stats/trans_table", + .size = 1481, + .content = + " From : To\n" + " : 830000 980000 1056000 1152000 1248000 1325000 1421000 1517000 1613000 1709000 1805000 \n" + " 830000: 0 767 0 0 511 65 79 25 375 38 0 \n" + " 980000: 616 0 83 89 213 31 106 12 248 15 0 \n" + " 1056000: 38 33 0 18 55 11 19 5 47 3 0 \n" + " 1152000: 66 56 13 0 96 23 48 14 108 5 0 \n" + " 1248000: 316 133 34 60 0 85 203 18 226 11 0 \n" + " 1325000: 96 49 11 34 24 0 72 20 137 13 0 \n" + " 1421000: 156 74 21 73 41 43 0 107 221 14 0 \n" + " 1517000: 54 21 4 21 6 21 30 0 159 4 0 \n" + " 1613000: 518 281 63 134 140 177 193 119 0 131 19 \n" + " 1709000: 0 0 0 0 0 0 0 0 178 0 266 \n" + " 1805000: 0 0 0 0 0 0 0 0 75 210 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/regs/identification/midr_el1", + .size = 19, + .content = "0x00000000411fd050\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/regs/identification/revidr_el1", + .size = 19, + .content = "0x000000000000000f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/core_id", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/core_siblings", + .size = 3, + .content = "0f\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/core_siblings_list", + .size = 4, + .content = "0-3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/physical_package_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/thread_siblings", + .size = 3, + .content = "08\n", + }, + { + .path = "/sys/devices/system/cpu/cpu3/topology/thread_siblings_list", + .size = 2, + .content = "3\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpuidle/driver/name", + .size = 25, + .content = "hisi_middle_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/affected_cpus", + .size = 4, + .content = "4 5\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1901000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "826000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/cpuinfo_transition_latency", + .size = 8, + .content = "2000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/related_cpus", + .size = 4, + .content = "4 5\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_frequencies", + .size = 95, + .content = "826000 903000 1018000 1114000 1210000 1306000 1402000 1517000 1594000 1671000 1805000 1901000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_available_governors", + .size = 77, + .content = "interactive conservative ondemand userspace powersave performance schedutil \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_cur_freq", + .size = 7, + .content = "826000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/scaling_driver", + .size = 11, + .content = "cpufreq-dt\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/time_in_state", + .size = 149, + .content = + "826000 217030\n" + "903000 393\n" + "1018000 728\n" + "1114000 316\n" + "1210000 200\n" + "1306000 1820\n" + "1402000 386\n" + "1517000 784\n" + "1594000 159\n" + "1671000 9174\n" + "1805000 1695\n" + "1901000 5547\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/total_trans", + .size = 5, + .content = "5719\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/cpufreq/stats/trans_table", + .size = 1733, + .content = + " From : To\n" + " : 826000 903000 1018000 1114000 1210000 1306000 1402000 1517000 1594000 1671000 1805000 1901000 \n" + " 826000: 0 133 201 0 2 517 8 41 9 238 58 0 \n" + " 903000: 111 0 44 14 0 97 17 9 2 17 2 0 \n" + " 1018000: 189 40 0 41 7 146 18 7 4 62 2 0 \n" + " 1114000: 60 10 32 0 15 110 10 6 0 26 2 0 \n" + " 1210000: 32 9 16 6 0 68 5 9 0 19 3 0 \n" + " 1306000: 287 73 125 121 56 0 55 250 11 84 17 0 \n" + " 1402000: 39 10 18 26 16 29 0 16 25 38 8 0 \n" + " 1517000: 80 6 18 18 29 16 20 0 6 195 11 0 \n" + " 1594000: 27 6 8 0 6 10 5 7 0 27 2 0 \n" + " 1671000: 383 26 54 45 36 86 87 54 41 0 116 19 \n" + " 1805000: 0 0 0 0 0 0 0 0 0 182 0 148 \n" + " 1901000: 0 0 0 0 0 0 0 0 0 58 109 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/regs/identification/midr_el1", + .size = 19, + .content = "0x00000000481fd400\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/regs/identification/revidr_el1", + .size = 19, + .content = "0x0000000000000001\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_siblings", + .size = 3, + .content = "30\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/core_siblings_list", + .size = 4, + .content = "4-5\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/thread_siblings", + .size = 3, + .content = "10\n", + }, + { + .path = "/sys/devices/system/cpu/cpu4/topology/thread_siblings_list", + .size = 2, + .content = "4\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpuidle/driver/name", + .size = 25, + .content = "hisi_middle_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/affected_cpus", + .size = 4, + .content = "4 5\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "1901000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_min_freq", + .size = 7, + .content = "826000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/cpuinfo_transition_latency", + .size = 8, + .content = "2000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/related_cpus", + .size = 4, + .content = "4 5\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_frequencies", + .size = 95, + .content = "826000 903000 1018000 1114000 1210000 1306000 1402000 1517000 1594000 1671000 1805000 1901000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_available_governors", + .size = 77, + .content = "interactive conservative ondemand userspace powersave performance schedutil \n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_cur_freq", + .size = 7, + .content = "826000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/scaling_driver", + .size = 11, + .content = "cpufreq-dt\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/time_in_state", + .size = 149, + .content = + "826000 217210\n" + "903000 393\n" + "1018000 728\n" + "1114000 316\n" + "1210000 200\n" + "1306000 1820\n" + "1402000 386\n" + "1517000 784\n" + "1594000 159\n" + "1671000 9174\n" + "1805000 1695\n" + "1901000 5547\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/total_trans", + .size = 5, + .content = "5719\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/cpufreq/stats/trans_table", + .size = 1733, + .content = + " From : To\n" + " : 826000 903000 1018000 1114000 1210000 1306000 1402000 1517000 1594000 1671000 1805000 1901000 \n" + " 826000: 0 133 201 0 2 517 8 41 9 238 58 0 \n" + " 903000: 111 0 44 14 0 97 17 9 2 17 2 0 \n" + " 1018000: 189 40 0 41 7 146 18 7 4 62 2 0 \n" + " 1114000: 60 10 32 0 15 110 10 6 0 26 2 0 \n" + " 1210000: 32 9 16 6 0 68 5 9 0 19 3 0 \n" + " 1306000: 287 73 125 121 56 0 55 250 11 84 17 0 \n" + " 1402000: 39 10 18 26 16 29 0 16 25 38 8 0 \n" + " 1517000: 80 6 18 18 29 16 20 0 6 195 11 0 \n" + " 1594000: 27 6 8 0 6 10 5 7 0 27 2 0 \n" + " 1671000: 383 26 54 45 36 86 87 54 41 0 116 19 \n" + " 1805000: 0 0 0 0 0 0 0 0 0 182 0 148 \n" + " 1901000: 0 0 0 0 0 0 0 0 0 58 109 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/regs/identification/midr_el1", + .size = 19, + .content = "0x00000000481fd400\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/regs/identification/revidr_el1", + .size = 19, + .content = "0x0000000000000001\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/core_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/core_siblings", + .size = 3, + .content = "30\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/core_siblings_list", + .size = 4, + .content = "4-5\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/physical_package_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/thread_siblings", + .size = 3, + .content = "20\n", + }, + { + .path = "/sys/devices/system/cpu/cpu5/topology/thread_siblings_list", + .size = 2, + .content = "5\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpuidle/driver/name", + .size = 22, + .content = "hisi_big_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/affected_cpus", + .size = 4, + .content = "6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2600000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_min_freq", + .size = 8, + .content = "1460000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/cpuinfo_transition_latency", + .size = 8, + .content = "2000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/related_cpus", + .size = 4, + .content = "6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_frequencies", + .size = 105, + .content = "1460000 1594000 1671000 1767000 1863000 1959000 2036000 2112000 2208000 2304000 2420000 2496000 2600000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_available_governors", + .size = 77, + .content = "interactive conservative ondemand userspace powersave performance schedutil \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_cur_freq", + .size = 8, + .content = "1460000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/scaling_driver", + .size = 11, + .content = "cpufreq-dt\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/time_in_state", + .size = 162, + .content = + "1460000 224532\n" + "1594000 224\n" + "1671000 266\n" + "1767000 2223\n" + "1863000 566\n" + "1959000 1390\n" + "2036000 544\n" + "2112000 476\n" + "2208000 427\n" + "2304000 636\n" + "2420000 312\n" + "2496000 189\n" + "2600000 6810\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/total_trans", + .size = 5, + .content = "2998\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/cpufreq/stats/trans_table", + .size = 2005, + .content = + " From : To\n" + " : 1460000 1594000 1671000 1767000 1863000 1959000 2036000 2112000 2208000 2304000 2420000 2496000 2600000 \n" + " 1460000: 0 84 30 352 17 32 4 4 4 18 1 11 26 \n" + " 1594000: 62 0 16 74 1 6 3 3 2 1 1 2 4 \n" + " 1671000: 57 16 0 95 0 2 0 2 0 4 0 3 7 \n" + " 1767000: 171 32 89 0 34 209 5 14 4 13 10 13 35 \n" + " 1863000: 31 7 4 12 0 32 3 0 2 0 2 4 8 \n" + " 1959000: 104 18 23 39 29 0 61 71 3 7 5 9 23 \n" + " 2036000: 39 2 9 15 5 32 0 17 20 2 1 3 11 \n" + " 2112000: 8 2 2 7 5 13 25 0 54 4 1 0 16 \n" + " 2208000: 14 2 6 5 3 10 4 10 0 50 5 3 6 \n" + " 2304000: 21 5 3 4 3 15 8 7 13 0 40 4 8 \n" + " 2420000: 5 2 0 7 4 8 8 1 2 7 0 7 43 \n" + " 2496000: 10 3 0 3 1 13 8 5 2 5 7 0 24 \n" + " 2600000: 62 2 4 16 3 20 27 3 12 19 21 22 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/regs/identification/midr_el1", + .size = 19, + .content = "0x00000000481fd400\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/regs/identification/revidr_el1", + .size = 19, + .content = "0x0000000000000001\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_id", + .size = 2, + .content = "0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_siblings", + .size = 3, + .content = "c0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/core_siblings_list", + .size = 4, + .content = "6-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/physical_package_id", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/thread_siblings", + .size = 3, + .content = "40\n", + }, + { + .path = "/sys/devices/system/cpu/cpu6/topology/thread_siblings_list", + .size = 2, + .content = "6\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpuidle/driver/name", + .size = 22, + .content = "hisi_big_cluster_idle\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/affected_cpus", + .size = 4, + .content = "6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_max_freq", + .size = 8, + .content = "2600000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_min_freq", + .size = 8, + .content = "1460000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/cpuinfo_transition_latency", + .size = 8, + .content = "2000000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/related_cpus", + .size = 4, + .content = "6 7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_frequencies", + .size = 105, + .content = "1460000 1594000 1671000 1767000 1863000 1959000 2036000 2112000 2208000 2304000 2420000 2496000 2600000 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_available_governors", + .size = 77, + .content = "interactive conservative ondemand userspace powersave performance schedutil \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_cur_freq", + .size = 8, + .content = "1460000\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/scaling_driver", + .size = 11, + .content = "cpufreq-dt\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/time_in_state", + .size = 162, + .content = + "1460000 224720\n" + "1594000 224\n" + "1671000 266\n" + "1767000 2223\n" + "1863000 566\n" + "1959000 1390\n" + "2036000 544\n" + "2112000 476\n" + "2208000 427\n" + "2304000 636\n" + "2420000 312\n" + "2496000 189\n" + "2600000 6810\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/total_trans", + .size = 5, + .content = "2998\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/cpufreq/stats/trans_table", + .size = 2005, + .content = + " From : To\n" + " : 1460000 1594000 1671000 1767000 1863000 1959000 2036000 2112000 2208000 2304000 2420000 2496000 2600000 \n" + " 1460000: 0 84 30 352 17 32 4 4 4 18 1 11 26 \n" + " 1594000: 62 0 16 74 1 6 3 3 2 1 1 2 4 \n" + " 1671000: 57 16 0 95 0 2 0 2 0 4 0 3 7 \n" + " 1767000: 171 32 89 0 34 209 5 14 4 13 10 13 35 \n" + " 1863000: 31 7 4 12 0 32 3 0 2 0 2 4 8 \n" + " 1959000: 104 18 23 39 29 0 61 71 3 7 5 9 23 \n" + " 2036000: 39 2 9 15 5 32 0 17 20 2 1 3 11 \n" + " 2112000: 8 2 2 7 5 13 25 0 54 4 1 0 16 \n" + " 2208000: 14 2 6 5 3 10 4 10 0 50 5 3 6 \n" + " 2304000: 21 5 3 4 3 15 8 7 13 0 40 4 8 \n" + " 2420000: 5 2 0 7 4 8 8 1 2 7 0 7 43 \n" + " 2496000: 10 3 0 3 1 13 8 5 2 5 7 0 24 \n" + " 2600000: 62 2 4 16 3 20 27 3 12 19 21 22 0 \n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/regs/identification/midr_el1", + .size = 19, + .content = "0x00000000481fd400\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/regs/identification/revidr_el1", + .size = 19, + .content = "0x0000000000000001\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_id", + .size = 2, + .content = "1\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_siblings", + .size = 3, + .content = "c0\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/core_siblings_list", + .size = 4, + .content = "6-7\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/physical_package_id", + .size = 2, + .content = "2\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/thread_siblings", + .size = 3, + .content = "80\n", + }, + { + .path = "/sys/devices/system/cpu/cpu7/topology/thread_siblings_list", + .size = 2, + .content = "7\n", + }, + { NULL }, +}; +#ifdef __ANDROID__ +struct cpuinfo_mock_property properties[] = { + { + .key = "aaudio.mmap_exclusive_policy", + .value = "2", + }, + { + .key = "aaudio.mmap_policy", + .value = "2", + }, + { + .key = "bastet.service.enable", + .value = "true", + }, + { + .key = "bg_fsck.pgid", + .value = "438", + }, + { + .key = "bt.dpbap.enable", + .value = "1", + }, + { + .key = "bt.max.hfpclient.connections", + .value = "2", + }, + { + .key = "config.disable_consumerir", + .value = "false", + }, + { + .key = "dalvik.vm.appimageformat", + .value = "lz4", + }, + { + .key = "dalvik.vm.boot-dex2oat-threads", + .value = "4", + }, + { + .key = "dalvik.vm.checkjni", + .value = "false", + }, + { + .key = "dalvik.vm.dex2oat-Xms", + .value = "64m", + }, + { + .key = "dalvik.vm.dex2oat-Xmx", + .value = "512m", + }, + { + .key = "dalvik.vm.dex2oat-minidebuginfo", + .value = "true", + }, + { + .key = "dalvik.vm.dex2oat-threads", + .value = "4", + }, + { + .key = "dalvik.vm.dexopt.secondary", + .value = "true", + }, + { + .key = "dalvik.vm.heapgrowthlimit", + .value = "384m", + }, + { + .key = "dalvik.vm.heapsize", + .value = "512m", + }, + { + .key = "dalvik.vm.heapstartsize", + .value = "8m", + }, + { + .key = "dalvik.vm.heaptargetutilization", + .value = "0.75", + }, + { + .key = "dalvik.vm.image-dex2oat-Xms", + .value = "64m", + }, + { + .key = "dalvik.vm.image-dex2oat-Xmx", + .value = "64m", + }, + { + .key = "dalvik.vm.image-dex2oat-threads", + .value = "4", + }, + { + .key = "dalvik.vm.isa.arm.features", + .value = "default", + }, + { + .key = "dalvik.vm.isa.arm.variant", + .value = "cortex-a15", + }, + { + .key = "dalvik.vm.isa.arm64.features", + .value = "default", + }, + { + .key = "dalvik.vm.isa.arm64.variant", + .value = "generic", + }, + { + .key = "dalvik.vm.stack-trace-dir", + .value = "/data/anr", + }, + { + .key = "dalvik.vm.stack-trace-file", + .value = "/data/anr/traces.txt", + }, + { + .key = "dalvik.vm.usejit", + .value = "true", + }, + { + .key = "dalvik.vm.usejitprofiles", + .value = "true", + }, + { + .key = "debug.aps.current_battery", + .value = "100", + }, + { + .key = "debug.aps.enable", + .value = "0", + }, + { + .key = "debug.aps.lcd_fps_scence", + .value = "60", + }, + { + .key = "debug.aps.process.name", + .value = "", + }, + { + .key = "debug.aps.scene_num", + .value = "5", + }, + { + .key = "debug.atrace.tags.enableflags", + .value = "0", + }, + { + .key = "debug.force_rtl", + .value = "0", + }, + { + .key = "debug.sf.disable_backpressure", + .value = "1", + }, + { + .key = "debug.sf.latch_unsignaled", + .value = "1", + }, + { + .key = "dev.action_boot_completed", + .value = "true", + }, + { + .key = "dev.bootcomplete", + .value = "1", + }, + { + .key = "drm.service.enabled", + .value = "true", + }, + { + .key = "fw.max_users", + .value = "4", + }, + { + .key = "fw.show_multiuserui", + .value = "1", + }, + { + .key = "gsm.check_is_single_pdp_sub1", + .value = "false", + }, + { + .key = "gsm.current.phone-type", + .value = "1,1", + }, + { + .key = "gsm.dualcards.switch", + .value = "false", + }, + { + .key = "gsm.fastdormancy.mode", + .value = "0", + }, + { + .key = "gsm.fastdormancy.screen", + .value = "2", + }, + { + .key = "gsm.fastdormancy.time_scroff", + .value = "4000", + }, + { + .key = "gsm.hw.fdn.activated2", + .value = "false", + }, + { + .key = "gsm.hw.operator.iso-country", + .value = "", + }, + { + .key = "gsm.hw.operator.isroaming", + .value = "false", + }, + { + .key = "gsm.hw.operator.numeric", + .value = "", + }, + { + .key = "gsm.network.type", + .value = "Unknown,Unknown", + }, + { + .key = "gsm.nvcfg.resetrild", + .value = "0", + }, + { + .key = "gsm.nvcfg.rildrestarting", + .value = "0", + }, + { + .key = "gsm.operator.alpha", + .value = ",", + }, + { + .key = "gsm.operator.iso-country", + .value = ",", + }, + { + .key = "gsm.operator.isroaming", + .value = "false,false", + }, + { + .key = "gsm.operator.numeric", + .value = ",", + }, + { + .key = "gsm.sigcust.configured", + .value = "true", + }, + { + .key = "gsm.sim.c_card.plmn", + .value = "", + }, + { + .key = "gsm.sim.hw_atr", + .value = "null", + }, + { + .key = "gsm.sim.hw_atr1", + .value = "null", + }, + { + .key = "gsm.sim.operator.alpha", + .value = ",", + }, + { + .key = "gsm.sim.operator.iso-country", + .value = ",", + }, + { + .key = "gsm.sim.operator.numeric", + .value = ",", + }, + { + .key = "gsm.sim.preiccid_0", + .value = "", + }, + { + .key = "gsm.sim.preiccid_1", + .value = "", + }, + { + .key = "gsm.sim.state", + .value = "ABSENT,ABSENT", + }, + { + .key = "gsm.sim.updatenitz", + .value = "-1", + }, + { + .key = "gsm.sim1.type", + .value = "-1", + }, + { + .key = "gsm.sim2.type", + .value = "-1", + }, + { + .key = "gsm.version.baseband", + .value = "21C10B675S000C000,21C10B675S000C000", + }, + { + .key = "gsm.version.ril-impl", + .value = "android infineon balong-ril 1.0", + }, + { + .key = "hw.hicure.dns_fail_count", + .value = "64", + }, + { + .key = "hw.lcd.density", + .value = "480", + }, + { + .key = "hw.wifi.dns_stat", + .value = "125,25,119878,1,384874", + }, + { + .key = "hw.wifipro.uid_dns_fail_count", + .value = "1000-2/10026-6/10090-5/10011-18/10089-19/10084-2/10071-8/10074-4", + }, + { + .key = "hwouc.hwpatch.version", + .value = "", + }, + { + .key = "hwservicemanager.ready", + .value = "true", + }, + { + .key = "init.svc.CameraDaemon", + .value = "running", + }, + { + .key = "init.svc.ITouchservice", + .value = "running", + }, + { + .key = "init.svc.activityrecognition_1_1", + .value = "running", + }, + { + .key = "init.svc.adbd", + .value = "running", + }, + { + .key = "init.svc.applogcat", + .value = "stopped", + }, + { + .key = "init.svc.aptouch", + .value = "running", + }, + { + .key = "init.svc.audioserver", + .value = "running", + }, + { + .key = "init.svc.bastetd", + .value = "running", + }, + { + .key = "init.svc.bootanim", + .value = "stopped", + }, + { + .key = "init.svc.cameraserver", + .value = "running", + }, + { + .key = "init.svc.chargelogcat", + .value = "stopped", + }, + { + .key = "init.svc.chargemonitor", + .value = "running", + }, + { + .key = "init.svc.cust_from_init", + .value = "stopped", + }, + { + .key = "init.svc.display-hal-1-0", + .value = "running", + }, + { + .key = "init.svc.displayeffect-1-2", + .value = "running", + }, + { + .key = "init.svc.displayengine-hal-1-1", + .value = "running", + }, + { + .key = "init.svc.dms-hal-1-0", + .value = "running", + }, + { + .key = "init.svc.dpeservice", + .value = "running", + }, + { + .key = "init.svc.drm", + .value = "running", + }, + { + .key = "init.svc.dubai-hal-1-1", + .value = "running", + }, + { + .key = "init.svc.dubaid", + .value = "running", + }, + { + .key = "init.svc.emcomd", + .value = "running", + }, + { + .key = "init.svc.eventslogcat", + .value = "stopped", + }, + { + .key = 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+ .value = "true", + }, + { + .key = "ro.connectivity.chiptype", + .value = "hisi", + }, + { + .key = "ro.connectivity.sub_chiptype", + .value = "hi1103", + }, + { + .key = "ro.control.sleeplog", + .value = "true", + }, + { + .key = "ro.crypto.state", + .value = "encrypted", + }, + { + .key = "ro.crypto.type", + .value = "file", + }, + { + .key = "ro.cust.cdrom", + .value = "/product/region_comm/oversea/cdrom/autorun.iso", + }, + { + .key = "ro.dalvik.vm.native.bridge", + .value = "0", + }, + { + .key = "ro.debuggable", + .value = "0", + }, + { + .key = "ro.device_owner", + .value = "false", + }, + { + .key = "ro.dual.sim.phone", + .value = "true", + }, + { + .key = "ro.expect.recovery_id", + .value = "0x9fa8e68d6518086e768455a638403afc84a17d88000000000000000000000000", + }, + { + .key = "ro.facebook.partnerid", + .value = "huawei:3ed03d0-8ce2-42fa-a449-b9443817d7b4", + }, + { + .key = "ro.frp.pst", + .value = "/dev/block/bootdevice/by-name/frp", + }, + { + .key = "ro.gpu_turbo", + .value = "", + }, + { + .key = "ro.hardware", + .value = "kirin980", + }, + { + .key = "ro.hardware.audio.primary", + .value = "hisi", + }, + { + .key = "ro.huawei.cust.drm.fl_only", + .value = "false", + }, + { + .key = "ro.huawei.cust.oma", + .value = "false", + }, + { + .key = "ro.huawei.cust.oma_drm", + .value = "true", + }, + { + .key = "ro.huawei.remount.check", + .value = "verify_success", + }, + { + .key = "ro.hw.base_all_groupversion", + .value = "G1.0", + }, + { + .key = "ro.hw.country", + .value = "la", + }, + { + .key = "ro.hw.custPath", + .value = "/cust/hw/la", + }, + { + .key = "ro.hw.cust_all_groupversion", + .value = "NA", + }, + { + .key = "ro.hw.hota.is_hwinit_cust_exists", + .value = "false", + }, + { + .key = "ro.hw.hota.is_hwinit_exists", + .value = "false", + }, + { + .key = "ro.hw.hota.is_hwinit_preload_exists", + .value = "false", + }, + { + .key = "ro.hw.mirrorlink.enable", + .value = "true", + }, + { + .key = "ro.hw.oemName", + .value = "HMA-L29", + }, + { + .key = "ro.hw.preload_all_groupversion", + .value = "G1.0", + }, + { + .key = "ro.hw.vendor", + .value = "hw", + }, + { + .key = "ro.hwcamera.aimovie_enable", + .value = "0", + }, + { + .key = "ro.hwcamera.frontzoom_enable", + .value = "0", + }, + { + .key = "ro.hwcamera.modesuggest_enable", + .value = "true", + }, + { + .key = "ro.hwcamera.smartzoom_enable", + .value = "false", + }, + { + .key = "ro.hwcamera.use.videosize.1080p", + .value = "true", + }, + { + .key = "ro.hwtracking.com.booking", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.facebook.appmanager", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.facebook.katana", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.facebook.orca", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.facebook.services", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.facebook.system", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.gameloft.android.GloftANPH", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.gameloft.android.GloftDBMF", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.gameloft.android.GloftDMKF", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.gameloft.android.GloftPDMF", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.gameloft.android.GloftSMIF", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.google.android.apps.docs.editors.docs", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.google.android.apps.docs.editors.sheets", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.google.android.apps.docs.editors.slides", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.huawei.autoinstallapkfrommcc", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.igg.android.lordsmobile", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.netflix.mediaclient", + .value = "huawei_preload_default", + }, + { + .key = "ro.hwtracking.com.netflix.partner.activation", + .value = "huawei_preload_default", + }, + { + .key = "ro.logd.size.stats", + .value = "64K", + }, + { + .key = "ro.logsystem.usertype", + .value = "6", + }, + { + .key = "ro.magic.api.version", + .value = "0.1", + }, + { + .key = "ro.oba.version", + .value = "NO_OBA_VERSION", + }, + { + .key = "ro.odm.build.fingerprint", + .value = "Huawei/Atlanta/Atlanta_HMA-L29:9/PPR1.180610.011/20180913215553:user/release-keys", + }, + { + .key = "ro.odm.ca_product_version", + .value = "HMA-L29", + }, + { + .key = "ro.odm.radio.nvcfg_normalization", + .value = "true", + }, + { + .key = "ro.oem_unlock_supported", + .value = "1", + }, + { + .key = "ro.opa.eligible_device", + .value = "true", + }, + { + .key = "ro.opengles.version", + .value = "196610", + }, + { + .key = "ro.patch.baseline.version", + .value = "2.0", + }, + { + .key = "ro.product.CustCVersion", + .value = "C605", + }, + { + .key = "ro.product.CustDVersion", + .value = "D1", + }, + { + .key = "ro.product.board", + .value = "HMA", + }, + { + .key = "ro.product.brand", + .value = "HUAWEI", + }, + { + .key = "ro.product.cpu.abi", + .value = "arm64-v8a", + }, + { + .key = "ro.product.cpu.abilist", + .value = "arm64-v8a,armeabi-v7a,armeabi", + }, + { + .key = "ro.product.cpu.abilist32", + .value = "armeabi-v7a,armeabi", + }, + { + .key = "ro.product.cpu.abilist64", + .value = "arm64-v8a", + }, + { + .key = "ro.product.device", + .value = "HWHMA", + }, + { + .key = "ro.product.fingerprintName", + .value = "HUAWEI-Z114", + }, + { + .key = "ro.product.first_api_level", + .value = "28", + }, + { + .key = "ro.product.hardwareversion", + .value = "HL1HIMAM", + }, + { + .key = "ro.product.imeisv", + .value = "02", + }, + { + .key = "ro.product.locale", + .value = "es-AR", + }, + { + .key = "ro.product.locale.language", + .value = "en", + }, + { + .key = "ro.product.locale.region", + .value = "US", + }, + { + .key = "ro.product.manufacturer", + .value = "HUAWEI", + }, + { + .key = "ro.product.model", + .value = "HMA-L29", + }, + { + .key = "ro.product.name", + .value = "HMA-L29", + }, + { + .key = "ro.product.odm.brand", + .value = "Huawei", + }, + { + .key = "ro.product.odm.device", + .value = "Atlanta", + }, + { + .key = "ro.product.odm.name", + .value = "Atlanta", + }, + { + .key = "ro.product.vendor.brand", + .value = "kirin980", + }, + { + .key = "ro.product.vendor.device", + .value = "kirin980", + }, + { + .key = "ro.product.vendor.manufacturer", + .value = "HUAWEI", + }, + { + .key = "ro.product.vendor.model", + .value = "kirin980", + }, + { + .key = "ro.product.vendor.name", + .value = "kirin980", + }, + { + .key = "ro.prop.hwkeychain_switch", + .value = "true", + }, + { + .key = "ro.property_service.version", + .value = "2", + }, + { + .key = "ro.quick_broadcast_cardstatus", + .value = "false", + }, + { + .key = "ro.revision", + .value = "0", + }, + { + .key = "ro.ril.ecclist", + .value = "112,911,#911,*911", + }, + { + .key = "ro.runmode", + .value = "normal", + }, + { + .key = "ro.secure", + .value = "1", + }, + { + .key = "ro.serialno", + .value = "MUN0218A29000006", + }, + { + .key = "ro.setupwizard.mode", + .value = "OPTIONAL", + }, + { + .key = "ro.setupwizard.wifi_on_exit", + .value = "false", + }, + { + .key = "ro.sf.enable_backpressure_opt", + .value = "0", + }, + { + .key = "ro.sf.lcd_density", + .value = "480", + }, + { + .key = "ro.sys.powerup_reason", + .value = "NORMAL", + }, + { + .key = "ro.syssvccallrecord.enable", + .value = "true", + }, + { + .key = "ro.sysui.show.normal.layout", + .value = "true", + }, + { + .key = "ro.telephony.default_network", + .value = "9", + }, + { + .key = "ro.treble.enabled", + .value = "true", + }, + { + .key = "ro.vendor.build.date", + .value = "Thu Sep 13 21:57:23 CST 2018", + }, + { + .key = "ro.vendor.build.date.utc", + .value = "1536847043", + }, + { + .key = "ro.vendor.build.fingerprint", + .value = "kirin980/kirin980/kirin980:9/PPR1.180610.011/jenkins09132155:user/release-keys", + }, + { + .key = "ro.vendor.build.security_patch", + .value = "2018-06-19", + }, + { + .key = "ro.vndk.version", + .value = "28", + }, + { + .key = "ro.wifi.channels", + .value = "", + }, + { + .key = "ro.zygote", + .value = "zygote64_32", + }, + { + .key = "security.perf_harden", + .value = "1", + }, + { + .key = "selinux.restorecon_recursive", + .value = "/data/misc_ce/0", + }, + { + .key = "service.bootanim.exit", + .value = "1", + }, + { + .key = "service.bootanim.stop", + .value = "1", + }, + { + .key = "service.sf.present_timestamp", + .value = "1", + }, + { + .key = "sys.2dsdr.pkgname", + .value = "*", + }, + { + .key = "sys.2dsdr.startratio", + .value = "1.0", + }, + { + .key = "sys.aps.maxFlingVelocity", + .value = "75", + }, + { + .key = "sys.aps.support", + .value = "34177027", + }, + { + .key = "sys.aps.version", + .value = "5.1.2-9.0.0.14", + }, + { + .key = "sys.boot.reason", + .value = "shutdown,", + }, + { + .key = "sys.boot_completed", + .value = "1", + }, + { + .key = "sys.defaultapn.enabled", + .value = "true", + }, + { + .key = "sys.fingerprint.deviceId", + .value = "0", + }, + { + .key = "sys.hisi.pmom.service.enable", + .value = "false", + }, + { + .key = "sys.huawei.thermal.enable", + .value = "true", + }, + { + .key = "sys.hw_boot_success", + .value = "1", + }, + { + .key = "sys.hwsholder.count", + .value = "0", + }, + { + .key = "sys.iaware.cpuset.screenoff.bg", + .value = "0-3", + }, + { + .key = "sys.iaware.cpuset.screenoff.boost", + .value = "0-7", + }, + { + .key = "sys.iaware.cpuset.screenoff.fg", + .value = "0-7", + }, + { + .key = "sys.iaware.cpuset.screenoff.kbg", + .value = "0-3", + }, + { + .key = "sys.iaware.cpuset.screenoff.sysbg", + .value = "0-3", + }, + { + .key = "sys.iaware.cpuset.screenoff.taboost", + .value = "", + }, + { + .key = "sys.iaware.cpuset.screenoff.topapp", + .value = "0-7", + }, + { + .key = "sys.iaware.cpuset.screenon.bg", + .value = "2-3", + }, + { + .key = "sys.iaware.cpuset.screenon.boost", + .value = "4-7", + }, + { + .key = "sys.iaware.cpuset.screenon.fg", + .value = "0-7", + }, + { + .key = "sys.iaware.cpuset.screenon.kbg", + .value = "2-3,5", + }, + { + .key = "sys.iaware.cpuset.screenon.sysbg", + .value = "0-3", + }, + { + .key = "sys.iaware.cpuset.screenon.taboost", + .value = "4-7", + }, + { + .key = "sys.iaware.cpuset.screenon.topapp", + .value = "0-7", + }, + { + .key = "sys.iaware.cpuset.vron.bg", + .value = "0-2", + }, + { + .key = "sys.iaware.cpuset.vron.boost", + .value = "4-7", + }, + { + .key = "sys.iaware.cpuset.vron.fg", + .value = "0-2,4-7", + }, + { + .key = "sys.iaware.cpuset.vron.kbg", + .value = "0-2", + }, + { + .key = "sys.iaware.cpuset.vron.sysbg", + .value = "0-2", + }, + { + .key = "sys.iaware.cpuset.vron.taboost", + .value = "", + }, + { + .key = "sys.iaware.cpuset.vron.topapp", + .value = "0-7", + }, + { + .key = "sys.iaware.eas.on", + .value = "true", + }, + { + .key = "sys.iaware.empty_app_percent", + .value = "67", + }, + { + .key = "sys.iaware.switch_set_success", + .value = "true", + }, + { + .key = "sys.iaware.type", + .value = "255", + }, + { + .key = "sys.iswifihotspoton", + .value = "false", + }, + { + .key = "sys.logbootcomplete", + .value = "1", + }, + { + .key = "sys.oem_unlock_allowed", + .value = "0", + }, + { + .key = "sys.pg.pre_rescue_boot_count", + .value = "1", + }, + { + .key = "sys.rescue_boot_count", + .value = "1", + }, + { + .key = "sys.resettype", + .value = "others:BR_POWERON_CHARGE", + }, + { + .key = "sys.retaildemo.enabled", + .value = "0", + }, + { + .key = "sys.runtime_data.hiddenapi.enable", + .value = "true", + }, + { + .key = "sys.settingsprovider_ready", + .value = "1", + }, + { + .key = "sys.show_google_nlp", + .value = "true", + }, + { + .key = "sys.super_power_save", + .value = "false", + }, + { + .key = "sys.sysctl.extra_free_kbytes", + .value = "28400", + }, + { + .key = "sys.sysctl.tcp_def_init_rwnd", + .value = "60", + }, + { + .key = "sys.thermal.vr_fps", + .value = "0", + }, + { + .key = "sys.thermal.vr_ratio_height", + .value = "0", + }, + { + .key = "sys.thermal.vr_ratio_width", + .value = "0", + }, + { + .key = "sys.thermal.vr_warning_level", + .value = "0", + }, + { + .key = "sys.uidcpupower", + .value = "", + }, + { + .key = "sys.usb.config", + .value = "hisuite,mtp,mass_storage,adb", + }, + { + .key = "sys.usb.configfs", + .value = "1", + }, + { + .key = "sys.usb.controller", + .value = "ff100000.dwc3", + }, + { + .key = "sys.usb.ffs.ready", + .value = "1", + }, + { + .key = "sys.usb.ffs_hdb.ready", + .value = "0", + }, + { + .key = "sys.usb.mtp.device_type", + .value = "3", + }, + { + .key = "sys.usb.state", + .value = "hisuite,mtp,mass_storage,adb", + }, + { + .key = "sys.user.0.ce_available", + .value = "true", + }, + { + .key = "system_init.hwextdeviceservice", + .value = "1", + }, + { + .key = "vold.crypto_unencrypt_updatedir", + .value = "/data/update", + }, + { + .key = "vold.cryptsd.keystate", + .value = "lock", + }, + { + .key = "vold.has_adoptable", + .value = "0", + }, + { + .key = "vold.has_quota", + .value = "0", + }, + { + .key = "vold.has_reserved", + .value = "1", + }, + { + .key = "vold.post_fs_data_done", + .value = "1", + }, + { + .key = "wifi.interface", + .value = "wlan0", + }, + { NULL }, +}; +#endif /* __ANDROID__ */ |