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authorMarat Dukhan <maratek@gmail.com>2017-09-25 10:30:39 -0700
committerGitHub <noreply@github.com>2017-09-25 10:30:39 -0700
commit8132a8c5100d7cf423dc3f35547fa8dd157f794c (patch)
tree90509eece71e62a89a1d3ea3673c76aec88b8a02 /README.md
parentb5826b3311ccdcd114d4a86a5f21df5c0dd0dbb9 (diff)
downloadcpuinfo-8132a8c5100d7cf423dc3f35547fa8dd157f794c.tar.gz
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cpuinfo is a library to detect essential for performance optimization information about host CPU.
+## Examples
+
+Detect if target is a 32-bit or 64-bit ARM system:
+
+```c
+#if CPUINFO_ARCH_ARM || CPUINFO_ARCH_ARM64
+ /* 32-bit ARM-specific code here */
+#endif
+```
+
+Check if the host CPU support ARM NEON
+```c
+cpuinfo_initialize();
+#if CPUINFO_ARCH_ARM
+ if (cpuinfo_isa.neon) {
+ neon_implementation(arguments);
+ }
+#endif
+```
+
+Check if the host CPU supports x86 AVX
+```c
+cpuinfo_initialize();
+#if CPUINFO_ARCH_X86 || CPUINFO_ARCH_X86_64
+ if (cpuinfo_isa.avx) {
+ avx_implementation(arguments);
+ }
+#endif
+```
+
+Check if the thread runs on a Cortex-A53 core
+```c
+cpuinfo_initialize();
+if (cpuinfo_current_core()->uarch == cpuinfo_uarch_cortex_a53) {
+ cortex_a53_implementation(arguments);
+}
+```
+
+Get the size of level 1 data cache on the fastest core in the processor (e.g. big core in big.LITTLE ARM systems):
+```c
+cpuinfo_initialize();
+const size_t l1_size = cpuinfo_processors[0].l1d->size;
+```
+
+Pin thread to cores sharing L2 cache with the current core (Linux or Android)
+```c
+cpuinfo_initialize();
+cpu_set_t cpu_set;
+CPU_ZERO(&cpu_set);
+const struct cpuinfo_cache* current_l2 = cpuinfo_current_processor()->l2;
+for (uint32_t i = 0; i < current_l2->processor_count; i++) {
+ CPU_SET(cpuinfo_processors[current_l2->processor_start + i].linux_id, &cpu_set);
+}
+pthread_setaffinity_np(pthread_self(), sizeof(cpu_set_t), &cpu_set);
+```
+
## Exposed information
- [x] Processor (SoC) name
- [x] Integrated GPU name (Android only)