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| author | Ashkan Aliabadi <ashkan.aliabadi@gmail.com> | 2020-05-24 22:33:14 -0700 |
|---|---|---|
| committer | Ashkan Aliabadi <ashkan.aliabadi@gmail.com> | 2020-05-24 22:33:14 -0700 |
| commit | a27ca5bf8b555530c3c5fd5432c7df506d14e15c (patch) | |
| tree | 0e83a6847e29031b74326c514cf3c7f4cd9517fa /src/arm/linux/aarch32-isa.c | |
| parent | 19b9316c71e4e45b170a664bf62ddefd7ac9feb5 (diff) | |
| download | cpuinfo-a27ca5bf8b555530c3c5fd5432c7df506d14e15c.tar.gz | |
Upstream cpuinfo updates in XNNPACK as of XNNPACK:33fcf7895be9cd64fef52c6e99a48d4dbc3f4b8b
Diffstat (limited to 'src/arm/linux/aarch32-isa.c')
| -rw-r--r-- | src/arm/linux/aarch32-isa.c | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index 6aedda3..64dd168 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -77,18 +77,24 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( /* * NEON VDOT instructions are not indicated in /proc/cpuinfo. - * Use a MIDR-based heuristic to whitelist processors known to support it: - * - Processors with Qualcomm-modified Cortex-A76 cores - * - Kirin 980 processor + * Use a MIDR-based heuristic to whitelist processors known to support it. */ switch (midr & (CPUINFO_ARM_MIDR_IMPLEMENTER_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { + case UINT32_C(0x4100D0B0): /* Cortex-A76 */ + case UINT32_C(0x4100D0D0): /* Cortex-A77 */ + case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ + case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ case UINT32_C(0x51008040): /* Kryo 485 Gold (Cortex-A76) */ + case UINT32_C(0x51008050): /* Kryo 485 Silver (Cortex-A55) */ + case UINT32_C(0x53000030): /* Exynos-M4 */ + case UINT32_C(0x53000040): /* Exynos-M5 */ isa->dot = true; break; - default: - if (chipset->series == cpuinfo_arm_chipset_series_hisilicon_kirin && chipset->model == 980) { - isa->dot = true; - } + case UINT32_C(0x4100D050): /* Cortex A55: revision 1 or later only */ + isa->dot = !!(midr_get_variant(midr) >= 1); + break; + case UINT32_C(0x4100D0A0): /* Cortex A75: revision 2 or later only */ + isa->dot = !!(midr_get_variant(midr) >= 2); break; } } else { |