Detect big.LITTLE ARM systems

1 files changed, 31 insertions, 22 deletions

diff --git a/src/arm/uarch.c b/src/arm/uarch.c
index e565f1f..28dbece 100644
--- a/src/arm/uarch.c
+++ b/src/arm/uarch.c
@@ -1,22 +1,22 @@
 #include <stdint.h>
 
 #include <arm/api.h>
+#include <arm/midr.h>
 #include <log.h>
 
 
 void cpuinfo_arm_decode_vendor_uarch(
-	uint32_t cpu_implementer,
-	uint32_t cpu_part,
+	uint32_t midr,
 #if CPUINFO_ARCH_ARM
 	bool has_vfpv4,
 #endif /* CPUINFO_ARCH_ARM */
 	enum cpuinfo_vendor vendor[restrict static 1],
 	enum cpuinfo_uarch uarch[restrict static 1])
 {
-	switch (cpu_implementer) {
+	switch (midr_get_implementer(midr)) {
 		case 'A':
 			*vendor = cpuinfo_vendor_arm;
-			switch (cpu_part) {
+			switch (midr_get_part(midr)) {
 #if CPUINFO_ARCH_ARM
 				case 0xC05:
 					*uarch = cpuinfo_uarch_cortex_a5;
@@ -49,6 +49,9 @@ void cpuinfo_arm_decode_vendor_uarch(
 				case 0xD04:
 					*uarch = cpuinfo_uarch_cortex_a35;
 					break;
+				case 0xD05:
+					*uarch = cpuinfo_uarch_cortex_a55;
+					break;
 				case 0xD07:
 					*uarch = cpuinfo_uarch_cortex_a57;
 					break;
@@ -58,8 +61,12 @@ void cpuinfo_arm_decode_vendor_uarch(
 				case 0xD09:
 					*uarch = cpuinfo_uarch_cortex_a73;
 					break;
+				case 0xD0A:
+					*uarch = cpuinfo_uarch_cortex_a75;
+					break;
 				default:
-					switch (cpu_part >> 8) {
+					switch (midr_get_part(midr) >> 8) {
+#if CPUINFO_ARCH_ARM
 						case 7:
 							*uarch = cpuinfo_uarch_arm7;
 							break;
@@ -69,38 +76,39 @@ void cpuinfo_arm_decode_vendor_uarch(
 						case 11:
 							*uarch = cpuinfo_uarch_arm11;
 							break;
+#endif /* CPUINFO_ARCH_ARM */
 						default:
-							cpuinfo_log_warning("unknown ARM CPU part 0x%03"PRIx32" ignored", cpu_part);
+							cpuinfo_log_warning("unknown ARM CPU part 0x%03"PRIx32" ignored", midr_get_part(midr));
 					}
 			}
 			break;
 		case 'C':
 			*vendor = cpuinfo_vendor_cavium;
-			switch (cpu_part) {
+			switch (midr_get_part(midr)) {
 				case 0x0A1:
 					*uarch = cpuinfo_uarch_thunderx;
 					break;
 				default:
-					cpuinfo_log_warning("unknown Cavium CPU part 0x%03"PRIx32" ignored", cpu_part);
+					cpuinfo_log_warning("unknown Cavium CPU part 0x%03"PRIx32" ignored", midr_get_part(midr));
 			}
 			break;
 #if CPUINFO_ARCH_ARM
 		case 'i':
 			*vendor = cpuinfo_vendor_intel;
-			switch (cpu_part >> 8) {
+			switch (midr_get_part(midr_get_part(midr)) >> 8) {
 				case 2: /* PXA 210/25X/26X */
 				case 4: /* PXA 27X */
 				case 6: /* PXA 3XX */
 					*uarch = cpuinfo_uarch_xscale;
 					break;
 				default:
-					cpuinfo_log_warning("unknown Intel CPU part 0x%03"PRIx32" ignored", cpu_part);
+					cpuinfo_log_warning("unknown Intel CPU part 0x%03"PRIx32" ignored", midr_get_part(midr));
 			}
 			break;
 #endif /* CPUINFO_ARCH_ARM */
 		case 'N':
 			*vendor = cpuinfo_vendor_nvidia;
-			switch (cpu_part) {
+			switch (midr_get_part(midr)) {
 				case 0x000:
 					*uarch = cpuinfo_uarch_denver;
 					break;
@@ -113,12 +121,12 @@ void cpuinfo_arm_decode_vendor_uarch(
 					*uarch = cpuinfo_uarch_denver;
 					break;
 				default:
-					cpuinfo_log_warning("unknown nVidia CPU part 0x%03"PRIx32" ignored", cpu_part);
+					cpuinfo_log_warning("unknown nVidia CPU part 0x%03"PRIx32" ignored", midr_get_part(midr));
 			}
 			break;
 		case 'Q':
 			*vendor = cpuinfo_vendor_qualcomm;
-			switch (cpu_part) {
+			switch (midr_get_part(midr)) {
 #if CPUINFO_ARCH_ARM
 				case 0x00F:
 					/* Mostly Scorpions, but some Cortex A5 may report this value as well */
@@ -138,40 +146,41 @@ void cpuinfo_arm_decode_vendor_uarch(
 					*uarch = cpuinfo_uarch_krait;
 					break;
 #endif /* CPUINFO_ARCH_ARM */
-				case 0x205: /* Low-power Kryo "Silver" */
-				case 0x211: /* High-performance Kryo "Gold" */
+				case 0x201: /* Qualcomm Snapdragon 821: Low-power Kryo "Silver" */
+				case 0x205: /* Qualcomm Snapdragon 820 & 821: High-performance Kryo "Gold" */
+				case 0x211: /* Qualcomm Snapdragon 820: Low-power Kryo "Silver" */
 					*uarch = cpuinfo_uarch_kryo;
 					break;
-				case 0x800: /* Low-power Kryo 280 -> Cortex-A53 */
+				case 0x800: /* Low-power Kryo 280 "Silver" -> Cortex-A53 */
 					*vendor = cpuinfo_vendor_arm;
 					*uarch = cpuinfo_uarch_cortex_a53;
 					break;
-				case 0x801: /* High-performance Kryo 280 -> Cortex-A73 */
+				case 0x801: /* High-performance Kryo 280 "Gold" -> Cortex-A73 */
 					*vendor = cpuinfo_vendor_arm;
 					*uarch = cpuinfo_uarch_cortex_a73;
 					break;
 				default:
-					cpuinfo_log_warning("unknown Qualcomm CPU part 0x%03"PRIx32" ignored", cpu_part);
+					cpuinfo_log_warning("unknown Qualcomm CPU part 0x%03"PRIx32" ignored", midr_get_part(midr));
 			}
 			break;
 		case 'S':
 			*vendor = cpuinfo_vendor_samsung;
-			switch (cpu_part) {
+			switch (midr_get_part(midr)) {
 				case 0x001:
 					*uarch = cpuinfo_uarch_mongoose;
 					break;
 				default:
-					cpuinfo_log_warning("unknown Samsung CPU part 0x%03"PRIx32" ignored", cpu_part);
+					cpuinfo_log_warning("unknown Samsung CPU part 0x%03"PRIx32" ignored", midr_get_part(midr));
 			}
 			break;
 #if CPUINFO_ARCH_ARM
 		case 'V':
 			*vendor = cpuinfo_vendor_marvell;
-			cpuinfo_log_warning("unknown Marvell CPU part 0x%03"PRIx32" ignored", cpu_part);
+			cpuinfo_log_warning("unknown Marvell CPU part 0x%03"PRIx32" ignored", midr_get_part(midr));
 			break;
 #endif /* CPUINFO_ARCH_ARM */
 		default:
 			cpuinfo_log_warning("unknown CPU implementer '%c' (0x%02"PRIx32") with CPU part 0x%03"PRIx32" ignored",
-				(char) cpu_implementer, cpu_implementer, cpu_part);
+				(char) midr_get_implementer(midr), midr_get_implementer(midr), midr_get_part(midr));
 	}
 }