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| author | Marat Dukhan <marat@fb.com> | 2018-06-04 11:31:26 -0700 |
|---|---|---|
| committer | Marat Dukhan <marat@fb.com> | 2018-06-04 11:31:26 -0700 |
| commit | 51ca20b18b77f0ceafca43a7397078c8d81a2ea7 (patch) | |
| tree | 8482651b341ab468fcebfa03521213324512cf9c /src/arm | |
| parent | 771e9fef6c5bdd8eb3468d61ca79c8094cb1982a (diff) | |
| download | cpuinfo-51ca20b18b77f0ceafca43a7397078c8d81a2ea7.tar.gz | |
Fix detection of L3 cache size on Cortex-A55/A75
Diffstat (limited to 'src/arm')
| -rw-r--r-- | src/arm/cache.c | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/src/arm/cache.c b/src/arm/cache.c index cbf1733..b026cec 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -692,7 +692,18 @@ void cpuinfo_arm_decode_cache( * [2] https://www.anandtech.com/show/12478/exynos-9810-handson-awkward-first-results */ if (midr_is_qualcomm_cortex_a55_silver(midr)) { - /* Qualcomm-modified Cortex-A55 in Snapdragon 845 */ + /* Qualcomm-modified Cortex-A55 in Snapdragon 710 / 845 */ + uint32_t l3_size = 1024 * 1024; + switch (chipset->series) { + case cpuinfo_arm_chipset_series_qualcomm_snapdragon: + /* Snapdragon 845: 2M L3 cache */ + if (chipset->model == 845) { + l3_size = 2 * 1024 * 1024; + } + break; + default: + break; + } *l1i = (struct cpuinfo_cache) { .size = 32 * 1024, @@ -710,7 +721,7 @@ void cpuinfo_arm_decode_cache( .line_size = 64 }; *l3 = (struct cpuinfo_cache) { - .size = 2 * 1024 * 1024, + .size = l3_size, .associativity = 16, .line_size = 64 }; @@ -970,6 +981,17 @@ void cpuinfo_arm_decode_cache( * * [1] https://www.anandtech.com/show/12114/qualcomm-announces-snapdragon-845-soc */ + uint32_t l3_size = 1024 * 1024; + switch (chipset->series) { + case cpuinfo_arm_chipset_series_qualcomm_snapdragon: + /* Snapdragon 845: 2M L3 cache */ + if (chipset->model == 845) { + l3_size = 2 * 1024 * 1024; + } + break; + default: + break; + } *l1i = (struct cpuinfo_cache) { .size = 64 * 1024, .associativity = 4, @@ -986,7 +1008,7 @@ void cpuinfo_arm_decode_cache( .line_size = 64 }; *l3 = (struct cpuinfo_cache) { - .size = 2 * 1024 * 1024, + .size = l3_size, .associativity = 16, .line_size = 64 }; |