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| author | Ashkan Aliabadi <ashkan.aliabadi@gmail.com> | 2020-06-01 18:23:11 -0700 |
|---|---|---|
| committer | Ashkan Aliabadi <ashkan.aliabadi@gmail.com> | 2020-06-01 18:23:11 -0700 |
| commit | 7e4c0099cc84b744d3844c9811f2470c50d6dcbf (patch) | |
| tree | da7192694f1b9b98b599b7e385a55bfd72d50e8e /src/arm | |
| parent | 5cefcd6293e6881754c2c53f99e95b159d2d8aa5 (diff) | |
| download | cpuinfo-7e4c0099cc84b744d3844c9811f2470c50d6dcbf.tar.gz | |
Upstream cpuinfo updates as of XNNPACK:5d67652eb23c2e94ffeeafd3e82a41745eb3ce41
Diffstat (limited to 'src/arm')
| -rw-r--r-- | src/arm/cache.c | 1 | ||||
| -rw-r--r-- | src/arm/mach/init.c | 9 | ||||
| -rw-r--r-- | src/arm/midr.h | 6 | ||||
| -rw-r--r-- | src/arm/uarch.c | 4 |
4 files changed, 17 insertions, 3 deletions
diff --git a/src/arm/cache.c b/src/arm/cache.c index 666ad78..446b02b 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -1115,7 +1115,6 @@ void cpuinfo_arm_decode_cache( break; } case cpuinfo_uarch_cortex_a76: - case cpuinfo_uarch_cortex_a76ae: { /* * ARM Cortex-A76 Core Technical Reference Manual diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c index bd27259..058cfc2 100644 --- a/src/arm/mach/init.c +++ b/src/arm/mach/init.c @@ -347,6 +347,15 @@ void cpuinfo_arm_mach_init(void) { cpuinfo_isa.fp16arith = true; } + /* + * There does not yet seem to exist an OS mechanism to detect support for + * ARMv8.2 optional dot-product instructions, so we currently whitelist CPUs + * known to support these instruction. + */ + if (cpu_family == CPUFAMILY_ARM_LIGHTNING_THUNDER) { + cpuinfo_isa.dot = true; + } + uint32_t num_clusters = 1; for (uint32_t i = 0; i < mach_topology.cores; i++) { cores[i] = (struct cpuinfo_core) { diff --git a/src/arm/midr.h b/src/arm/midr.h index d5a28e3..34d7780 100644 --- a/src/arm/midr.h +++ b/src/arm/midr.h @@ -189,22 +189,28 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x4100D0A0): /* Cortex-A75 */ case UINT32_C(0x4100D090): /* Cortex-A73 */ case UINT32_C(0x4100D080): /* Cortex-A72 */ +#if CPUINFO_ARCH_ARM case UINT32_C(0x4100C0F0): /* Cortex-A15 */ case UINT32_C(0x4100C0E0): /* Cortex-A17 */ case UINT32_C(0x4100C0D0): /* Rockchip RK3288 cores */ case UINT32_C(0x4100C0C0): /* Cortex-A12 */ +#endif /* CPUINFO_ARCH_ARM */ /* These cores are always in big role */ return 5; case UINT32_C(0x4100D070): /* Cortex-A57 */ /* Cortex-A57 can be in LITTLE role w.r.t. Denver 2, or in big role w.r.t. Cortex-A53 */ return 4; +#if CPUINFO_ARCH_ARM64 case UINT32_C(0x4100D060): /* Cortex-A65 */ +#endif /* CPUINFO_ARCH_ARM64 */ case UINT32_C(0x4100D050): /* Cortex-A55 */ case UINT32_C(0x4100D030): /* Cortex-A53 */ /* Cortex-A53 is usually in LITTLE role, but can be in big role w.r.t. Cortex-A35 */ return 2; case UINT32_C(0x4100D040): /* Cortex-A35 */ +#if CPUINFO_ARCH_ARM case UINT32_C(0x4100C070): /* Cortex-A7 */ +#endif /* CPUINFO_ARCH_ARM */ case UINT32_C(0x51008050): /* Kryo 485 Silver */ case UINT32_C(0x51008030): /* Kryo 385 Silver */ case UINT32_C(0x51008010): /* Kryo 260 / 280 Silver */ diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 63b1a55..55b61df 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -88,8 +88,8 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD0D: *uarch = cpuinfo_uarch_cortex_a77; break; - case 0xD0E: - *uarch = cpuinfo_uarch_cortex_a76ae; + case 0xD0E: /* Cortex-A76AE */ + *uarch = cpuinfo_uarch_cortex_a76; break; #if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) case 0xD4A: |