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| author | Miao Wang <miaowang@google.com> | 2020-07-27 03:41:02 +0000 |
|---|---|---|
| committer | Automerger Merge Worker <android-build-automerger-merge-worker@system.gserviceaccount.com> | 2020-07-27 03:41:02 +0000 |
| commit | 1733879c53e64c65e898dd74ed97d1cfd5ae3a87 (patch) | |
| tree | 0715b1f533508a2b66f5f8e5cdfb28a0ed125b5f /src/arm | |
| parent | d1e7941bf1db7c32b5e201ba3934d7ee3de25acb (diff) | |
| parent | dbd3560b95a5347e83db52eda315a8f15313ad68 (diff) | |
| download | cpuinfo-1733879c53e64c65e898dd74ed97d1cfd5ae3a87.tar.gz | |
Patch cpuinfo based on XNNPACK cpuinfo.patch am: c51afc47f2 am: 86e235ad4a am: a762baf70f am: a4c3c2247f am: dbd3560b95
Original change: https://android-review.googlesource.com/c/platform/external/cpuinfo/+/1371148
Change-Id: I3a15e946a719b90ef2bb79eacd2ef40cb873825a
Diffstat (limited to 'src/arm')
| -rw-r--r-- | src/arm/cache.c | 1 | ||||
| -rw-r--r-- | src/arm/linux/aarch32-isa.c | 1 | ||||
| -rw-r--r-- | src/arm/mach/init.c | 1 | ||||
| -rw-r--r-- | src/arm/midr.h | 1 | ||||
| -rw-r--r-- | src/arm/uarch.c | 3 |
5 files changed, 6 insertions, 1 deletions
diff --git a/src/arm/cache.c b/src/arm/cache.c index 70f11fd..e9102ed 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -1106,7 +1106,6 @@ void cpuinfo_arm_decode_cache( break; } case cpuinfo_uarch_cortex_a76: - case cpuinfo_uarch_cortex_a76ae: { /* * ARM Cortex-A76 Core Technical Reference Manual diff --git a/src/arm/linux/aarch32-isa.c b/src/arm/linux/aarch32-isa.c index 92095e1..6e659f5 100644 --- a/src/arm/linux/aarch32-isa.c +++ b/src/arm/linux/aarch32-isa.c @@ -43,6 +43,7 @@ void cpuinfo_arm_linux_decode_isa_from_proc_cpuinfo( isa->armv6k = true; isa->armv7 = true; isa->armv7mp = true; + isa->armv8 = true; isa->thumb = true; isa->thumb2 = true; isa->idiv = true; diff --git a/src/arm/mach/init.c b/src/arm/mach/init.c index bd27259..b6c4a7b 100644 --- a/src/arm/mach/init.c +++ b/src/arm/mach/init.c @@ -307,6 +307,7 @@ void cpuinfo_arm_mach_init(void) { case CPU_TYPE_ARM: switch (cpu_subtype) { case CPU_SUBTYPE_ARM_V8: + cpuinfo_isa.armv8 = true; cpuinfo_isa.aes = true; cpuinfo_isa.sha1 = true; cpuinfo_isa.sha2 = true; diff --git a/src/arm/midr.h b/src/arm/midr.h index d5a28e3..3d3aaa9 100644 --- a/src/arm/midr.h +++ b/src/arm/midr.h @@ -183,6 +183,7 @@ inline static uint32_t midr_score_core(uint32_t midr) { case UINT32_C(0x51008000): /* Kryo 260 / 280 Gold */ case UINT32_C(0x51002050): /* Kryo Gold */ case UINT32_C(0x4800D400): /* Cortex-A76 (HiSilicon) */ + case UINT32_C(0x4100D410): /* Cortex-A78 */ case UINT32_C(0x4100D0D0): /* Cortex-A77 */ case UINT32_C(0x4100D0E0): /* Cortex-A76AE */ case UINT32_C(0x4100D0B0): /* Cortex-A76 */ diff --git a/src/arm/uarch.c b/src/arm/uarch.c index e5e3cbc..e8b4c5e 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -91,6 +91,9 @@ void cpuinfo_arm_decode_vendor_uarch( case 0xD0E: *uarch = cpuinfo_uarch_cortex_a76ae; break; + case 0xD41: /* Cortex-A78 */ + *uarch = cpuinfo_uarch_cortex_a78; + break; #if CPUINFO_ARCH_ARM64 && !defined(__ANDROID__) case 0xD4A: *uarch = cpuinfo_uarch_neoverse_e1; |