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| author | Marat Dukhan <marat@fb.com> | 2018-03-07 11:07:48 -0800 |
|---|---|---|
| committer | Marat Dukhan <marat@fb.com> | 2018-03-07 11:07:48 -0800 |
| commit | a750f2a581125ede1c16cfe973a8cc249952414f (patch) | |
| tree | 0364c44f542eee4770247d8ef2b45b8260ce1654 /src | |
| parent | 9100a64a3d1188ac26db5a8de5a243ddaf37866e (diff) | |
| download | cpuinfo-a750f2a581125ede1c16cfe973a8cc249952414f.tar.gz | |
Update ARM uArch maps
Diffstat (limited to 'src')
| -rw-r--r-- | src/arm/cache.c | 3 | ||||
| -rw-r--r-- | src/arm/uarch.c | 38 |
2 files changed, 36 insertions, 5 deletions
diff --git a/src/arm/cache.c b/src/arm/cache.c index 1e7d841..005bb4d 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -922,7 +922,8 @@ void cpuinfo_arm_decode_cache( .line_size = 64 }; break; - case cpuinfo_uarch_mongoose: + case cpuinfo_uarch_mongoose_m1: + case cpuinfo_uarch_mongoose_m2: /* * - "Moving past branch prediction we can see some elements of how the cache is set up for the L1 I$, * namely 64 KB split into four sets with 128-byte line sizes for 128 cache lines per set" [1] diff --git a/src/arm/uarch.c b/src/arm/uarch.c index d04ed52..2e8d70f 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -184,18 +184,48 @@ void cpuinfo_arm_decode_vendor_uarch( *vendor = cpuinfo_vendor_arm; *uarch = cpuinfo_uarch_cortex_a53; break; + case 0x802: /* High-performance Kryo 385 "Gold" -> Cortex-A75 */ + *vendor = cpuinfo_vendor_arm; + *uarch = cpuinfo_uarch_cortex_a75; + break; + case 0x803: /* Low-power Kryo 385 "Silver" -> Cortex-A55 */ + *vendor = cpuinfo_vendor_arm; + *uarch = cpuinfo_uarch_cortex_a55; + break; default: cpuinfo_log_warning("unknown Qualcomm CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); } break; case 'S': *vendor = cpuinfo_vendor_samsung; - switch (midr_get_part(midr)) { - case 0x001: - *uarch = cpuinfo_uarch_mongoose; + switch (midr & (CPUINFO_ARM_MIDR_VARIANT_MASK | CPUINFO_ARM_MIDR_PART_MASK)) { + case 0x00100010: + /* + * Exynos 8890 MIDR = 0x531F0011, assume Mongoose M1 has: + * - CPU variant 0x1 + * - CPU part 0x001 + */ + *uarch = cpuinfo_uarch_mongoose_m1; + break; + case 0x00400010: + /* + * Exynos 8895 MIDR = 0x534F0010, assume Mongoose M2 has: + * - CPU variant 0x4 + * - CPU part 0x001 + */ + *uarch = cpuinfo_uarch_mongoose_m2; + break; + case 0x00100020: + /* + * Exynos 9810 MIDR = 0x531F0020, assume Mongoose M3 has: + * - CPU variant 0x1 + * - CPU part 0x002 + */ + *uarch = cpuinfo_uarch_mongoose_m3; break; default: - cpuinfo_log_warning("unknown Samsung CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); + cpuinfo_log_warning("unknown Samsung CPU variant 0x%01"PRIx32" part 0x%03"PRIx32" ignored", + midr_get_variant(midr), midr_get_part(midr)); } break; #if CPUINFO_ARCH_ARM |