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author | Marat Dukhan <marat@fb.com> | 2018-05-10 00:17:57 -0700 |
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committer | Marat Dukhan <marat@fb.com> | 2018-05-10 00:17:57 -0700 |
commit | 0d4f07df6cad2645eb41834ff452138f130844e2 (patch) | |
tree | 08d6309083506da0a38c70e2cb14210c060bc1a5 /test | |
parent | 8541691439abcbf906e1cb42a843e833cecd4f57 (diff) | |
download | cpuinfo-0d4f07df6cad2645eb41834ff452138f130844e2.tar.gz |
Add test case for cache size on RK3368
Diffstat (limited to 'test')
-rw-r--r-- | test/arm-cache.cc | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/test/arm-cache.cc b/test/arm-cache.cc index eeaabd3..4be8816 100644 --- a/test/arm-cache.cc +++ b/test/arm-cache.cc @@ -1499,3 +1499,39 @@ TEST(NVIDIA, tegra_t210) { EXPECT_EQ(2 * 1024 * 1024, l2.size); EXPECT_EQ(0, l3.size); } + +TEST(ROCKCHIP, rk3368) { + const struct cpuinfo_arm_chipset chipset = { + .vendor = cpuinfo_arm_chipset_vendor_rockchip, + .series = cpuinfo_arm_chipset_series_rockchip_rk, + .model = 3368, + }; + + struct cpuinfo_cache big_l1i = { 0 }; + struct cpuinfo_cache big_l1d = { 0 }; + struct cpuinfo_cache big_l2 = { 0 }; + struct cpuinfo_cache big_l3 = { 0 }; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), + &chipset, 0, 8, + &big_l1i, &big_l1d, &big_l2, &big_l3); + + struct cpuinfo_cache little_l1i = { 0 }; + struct cpuinfo_cache little_l1d = { 0 }; + struct cpuinfo_cache little_l2 = { 0 }; + struct cpuinfo_cache little_l3 = { 0 }; + cpuinfo_arm_decode_cache( + cpuinfo_uarch_cortex_a53, 4, UINT32_C(0x410FD033), + &chipset, 1, 8, + &little_l1i, &little_l1d, &little_l2, &little_l3); + + EXPECT_EQ(32 * 1024, big_l1i.size); + EXPECT_EQ(32 * 1024, big_l1d.size); + EXPECT_EQ(512 * 1024, big_l2.size); + EXPECT_EQ(0, big_l3.size); + + EXPECT_EQ(32 * 1024, little_l1i.size); + EXPECT_EQ(32 * 1024, little_l1d.size); + EXPECT_EQ(256 * 1024, little_l2.size); + EXPECT_EQ(0, little_l3.size); +} |