From 1e6c8c99d27f2b5eb9d2e6231055c6a4115b85e5 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Sun, 13 May 2018 20:24:07 -0700 Subject: Detect Denver 2 as a separate uarch --- src/arm/cache.c | 1 + src/arm/uarch.c | 7 +------ 2 files changed, 2 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/arm/cache.c b/src/arm/cache.c index d64bfee..cbf1733 100644 --- a/src/arm/cache.c +++ b/src/arm/cache.c @@ -1093,6 +1093,7 @@ void cpuinfo_arm_decode_cache( } break; case cpuinfo_uarch_denver: + case cpuinfo_uarch_denver2: /* * The Denver chip includes a 128KB, 4-way level 1 instruction cache, a 64KB, 4-way level 2 data cache, * and a 2MB, 16-way level 2 cache, all of which can service both cores. [1] diff --git a/src/arm/uarch.c b/src/arm/uarch.c index 048a780..652fb66 100644 --- a/src/arm/uarch.c +++ b/src/arm/uarch.c @@ -149,12 +149,7 @@ void cpuinfo_arm_decode_vendor_uarch( *uarch = cpuinfo_uarch_denver; break; case 0x003: - /* - * Nvidia Denver 2. - * Few details are known about Denver 2, and known details are no different that Denver 1, - * so consider them the same microarchitecture. - */ - *uarch = cpuinfo_uarch_denver; + *uarch = cpuinfo_uarch_denver2; break; default: cpuinfo_log_warning("unknown Nvidia CPU part 0x%03"PRIx32" ignored", midr_get_part(midr)); -- cgit v1.2.3