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| author | Pankaj Mistry <pmistry@nvidia.com> | 2021-10-05 17:16:39 -0700 |
|---|---|---|
| committer | Pankaj Mistry <pmistry@nvidia.com> | 2021-10-06 09:54:05 -0700 |
| commit | e225eb0bec7f20656255041f6ea147584114cbc1 (patch) | |
| tree | 43871f599541aaf04b84d9f6854718158fed1dd4 /include/spirv/unified1/spirv.h | |
| parent | ae217c17809fadb232ec94b29304b4afcd417bb4 (diff) | |
| download | SPIRV-Headers-e225eb0bec7f20656255041f6ea147584114cbc1.tar.gz | |
Define a new Image operand bit mask for non constant offsets
For details refer to https://gitlab.khronos.org/spirv/SPIR-V/-/issues/639
As part of the commit following changes have been introduced:
1. Added a separate section in spirv xml to reserve vendor specific bit masks.
2. Added a new image operand bit mask to support non constant offsets in textureGatherOffsets as defined in GL_NV_gpu_shader5
Diffstat (limited to 'include/spirv/unified1/spirv.h')
| -rw-r--r-- | include/spirv/unified1/spirv.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/spirv/unified1/spirv.h b/include/spirv/unified1/spirv.h index 1443963..bb6c68d 100644 --- a/include/spirv/unified1/spirv.h +++ b/include/spirv/unified1/spirv.h @@ -357,6 +357,7 @@ typedef enum SpvImageOperandsShift_ { SpvImageOperandsVolatileTexelKHRShift = 11, SpvImageOperandsSignExtendShift = 12, SpvImageOperandsZeroExtendShift = 13, + SpvImageOperandsOffsetsShift = 16, SpvImageOperandsMax = 0x7fffffff, } SpvImageOperandsShift; @@ -380,6 +381,7 @@ typedef enum SpvImageOperandsMask_ { SpvImageOperandsVolatileTexelKHRMask = 0x00000800, SpvImageOperandsSignExtendMask = 0x00001000, SpvImageOperandsZeroExtendMask = 0x00002000, + SpvImageOperandsOffsetsMask = 0x00010000, } SpvImageOperandsMask; typedef enum SpvFPFastMathModeShift_ { |