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2021-01-25Add SPV_KHR_workgroup_memory_explicit_layoutCaio Marcelo de Oliveira Filho
2021-01-22Merge pull request #191 from dneto0/reorder-enums-in-specJohn Kessenich
Push FPDenormMode, FPOperationMode to the end
2021-01-20Push FPDenormMode, FPOperationMode to the endDavid Neto
This is a cosmetic change for the benefit of generating the SPIR-V spec. It reorders the "FP Denorm Mode" and "FP Operation Mode" so they are the last sections in chapter 3 before the instruction listing. They become 3.37 and 3.38. The idea is to preserve the section numbering for earlier sections. For example, keep 3.31 as the Capability section.
2021-01-20Merge pull request #176 from MrSidims/private/MrSidims/OtherExtensionsJohn Kessenich
Upstream several Intel extensions
2021-01-20Apply suggestions to Intel extensions PRDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Update generated filesDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Add SPV_INTEL_long_constant_composite extensionDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Add SPV_INTEL_loop_fuse extensionDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Add SPV_INTEL_fpga_cluster_attributes and SPV_INTEL_fp_fast_math_modeDmitry Sidorov
Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fpga_cluster_attributes.asciidoc https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fp_fast_math_mode.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Update SPV_INTEL_fpga_loop_controls extensionDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Update SPV_INTEL_kernel_attributes extensionDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Update SPV_INTEL_function_pointers extensionDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_float_controls2 extensionDmitry Sidorov
Spec: https://github.com/intel/llvm/blob/39fa9b0cbfbae88327118990a05c5b387b56d2ef/sycl/doc/extensions/SPIRV/SPV_INTEL_float_controls2.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_vector_compute extensionDmitry Sidorov
Spec: https://github.com/intel/llvm/blob/e185a6b49e4bc9806a799b774977f1196b24f0d6/sycl/doc/extensions/SPIRV/SPV_INTEL_vector_compute.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_fpga_memory_accesses extensionDmitry Sidorov
Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_accesses.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_io_pipes extensionDmitry Sidorov
Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_io_pipes.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_variable_length_array extensionDmitry Sidorov
Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_variable_length_array.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_usm_storage_classes extensionDmitry Sidorov
Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_usm_storage_classes.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_arbitrary_precision_integers extensionsDmitry Sidorov
Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_int.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_inline_assembly extensionDmitry Sidorov
Spec: https://github.com/intel/llvm/blob/sycl/sycl/doc/extensions/SPIRV/SPV_INTEL_inline_assembly.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Upstream SPV_INTEL_fpga_buffer_location extensionDmitry Sidorov
Spec: https://github.com/intel/llvm/blob/2237b42035f31cb10b16d4f9abaeed45bed98587/sycl/doc/extensions/SPIRV/SPV_INTEL_fpga_buffer_location.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2020-11-27Merge pull request #184 from dgkoch/dkoch_remove_hittkhrRaun Krisch
remove HitTKHR alias
2020-11-26remove HitTKHRDaniel Koch
It was not added to the SPV_KHR_ray_tracing extension since it is just an alias of RayTMaxKHR.
2020-11-23Merge pull request #180 from dneto0/issue-179David Neto
MeshShadingNV enables builtins PrimitiveId, Layer, and ViewportIndex
2020-11-23MeshShadingNV enables builtins PrimitiveId, Layer, and ViewportIndexDavid Neto
Fixes #179 See extension SPV_NV_mesh_shader
2020-11-23Merge pull request #182 from dgkoch/khr_rt_finalRaun Krisch
Updates to final ray tracing extensions
2020-11-20de-alias/reassign OpIgnoreIntersectionKHR/OpTerminateRayKHRDaniel Koch
vulkan/vulkan#2374
2020-11-20Raytracing and Rayquery updates for finalalelenv
2020-11-20Updated headers for new trace/executeCallable and acceleration structure cast.alelenv
2020-11-04Reserve additional loop control bit for Intel extension (NoFusionINTEL) (#175)Mike Kinsner
2020-11-02Add EmbarkStudios/rust-gpu to vendor list. (#174)XAMPPRocky
2020-10-23Bump revision to 4, for SPIR-V 1.5.John Kessenich
2020-10-19Add SPV_EXT_shader_image_int64 (#170)Tobski
Co-authored-by: Arkadiusz Sarwa <arkadiusz.sarwa@amd.com>
2020-10-19Added SPV_KHR_fragment_shading_rate (#172)Tobski
2020-10-12 Register the Xenia emulator as a generator (#171)Triang3l
2020-09-26Register the Messiah SPIR-V CodeGen (#169)Yuwen Wu
2020-09-10Register the ANGLE compiler (#168)Shahbaz Youssefi
2020-09-08Rebuild of latest headers, which slightly moves OpTerminateInvocationJohn Kessenich
2020-08-03Reserve SPIR-V token range for upcoming Intel extensions. (#165)Mariusz Merecki
2020-07-29Update BUILD.bazel and BUILD.gn (#166)alan-baker
* Export NonSemantic.ClspvReflection.h for both * Add exports for the extended instruction sets in the unified1 directory (for use in SPIRV-Tools)
2020-07-29Publish the headers for the clspv embedded reflection non-semantic extended ↵alan-baker
instruction set (#164) * Clspv non-semantic reflection instruction set * Version 1
2020-07-29Update the registry in spir-v.xml to modernize and split out opcodes. (#156)John Kessenich
2020-07-21Support SPV_KHR_terminate_invocation (#163)alan-baker
* Support SPV_KHR_terminate_invocation * Fix order in spirv.core.grammar.json Co-authored-by: David Neto <dneto@google.com>
2020-07-21Merge pull request #162 from vkushwaha-nv/SPV_EXT_shader_atomic_floatJohn Kessenich
Add changes for SPV_EXT_shader_atomic_float
2020-07-19Add changes for SPV_EXT_shader_atomic_floatVikram Kushwaha
2020-07-06Merge pull request #160 from dj2/reg_tintDavid Neto
Register the Tint compiler
2020-06-26Register the Tint compilerdan sinclair
2020-06-01Merge pull request #159 from dneto0/fix-quotesJohn Kessenich
spir-v.xml: Use plain ASCII quotes in comment
2020-06-01spir-v.xml: Use plain ASCII quotes in commentDavid Neto
Avoids parse error on Windows-based Python3.
2020-05-29Merge pull request #158 from mkinsner/mkinsner/fpfastmath_allocation_mechanismJohn Kessenich
Propose bit allocation mechanism for the FP Fast Math Mode bitfield
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 19:47:28 +0000