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2021-11-10Merge pull request #251 from MrSidims/private/MrSidims/FunctionPointerINTELRaun Krisch
Rename ConstFunctionPointerINTEL to ConstantFunctionPointerINTEL
2021-11-03Merge pull request #250 from kpet/clspv-reflection-subgroupsRaun Krisch
Add SpecConstantSubgroupMaxSize to the clspv reflection non-semantic instruction set
2021-11-03Rename ConstFunctionPointerINTEL to ConstantFunctionPointerINTELDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-10-25Add SpecConstantSubgroupMaxSize to the clspv reflection non-semantic ↵Kévin Petit
instruction set Signed-off-by: Kévin Petit <kpet@free.fr>
2021-10-21Implement header definitions for SPV_NV_bindless_texturePankaj Mistry
2021-10-06Define a new Image operand bit mask for non constant offsetsPankaj Mistry
For details refer to https://gitlab.khronos.org/spirv/SPIR-V/-/issues/639 As part of the commit following changes have been introduced: 1. Added a separate section in spirv xml to reserve vendor specific bit masks. 2. Added a new image operand bit mask to support non constant offsets in textureGatherOffsets as defined in GL_NV_gpu_shader5
2021-09-16Remove 'Kernel' capability from fast-math flagsGraeme Leese
The use of these flags (the FPFastMath decoration) is already protected by the capability, so it isn't needed to protect the individual values as well.
2021-08-16spirv.core.grammar: Remove duplicate OpArbitraryFloatPowNINTEL declarationMarijn Suijten
An identical declaration of `OpArbitraryFloatPowNINTEL` exists just above, with the exact same opcode and operands.
2021-08-11Merge pull request #233 from NikitaRudenkoIntel/optRaun Krisch
Fix minor details in SPV_INTEL_optnone extension
2021-08-10Add support for SPV_NV_ray_tracing_motion_blur.alelenv
2021-07-28Fix minor details in SPV_INTEL_optnone extensionNikita Rudenko
Spec: https://github.com/intel/llvm/pull/3198
2021-07-28Implement SPV_INTEL_optnone extension (#230)Nikita Rudenko
Spec: https://github.com/intel/llvm/pull/3198
2021-07-20Correct grammar for LocalSizeHintIdGraeme Leese
It is described in the spec as being the "same as LocalSizeHint mode, but using <id> operands instead of literals", but the grammar had a single <id> operand instead of the 3 literals for LocalSizeHint.
2021-07-14Merge pull request #227 from kpet/fix-integer-dot-product-grammarRaun Krisch
Fix grammar for PackedVectorFormat
2021-07-09Add missing capabilities and '"version" : "None"' to QuantizationModes and ↵Mariusz Merecki
OverflowModes enumerants
2021-07-07Fix grammar for PackedVectorFormatKevin Petit
PackedVectorFormat4x8BitKHR should be enabled by the SPV_KHR_integer_dot_product extension that first introduced it and not the DotProductInput4x8BitPackedKHR as per the extension specification. See http://htmlpreview.github.io/?https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/KHR/SPV_KHR_integer_dot_product.html Signed-off-by: Kevin Petit <kevin.petit@arm.com>
2021-06-30Merge pull request #224 from Fznamznon/upstream-debug-module-extRaun Krisch
Upstream SPV_INTEL_debug_module extension
2021-06-25Upstream SPV_INTEL_debug_moduleMariya Podchishchaeva
Spec https://github.com/intel/llvm/pull/3976
2021-06-23add support for SPV_KHR_bit_instructionsBen Ashbaugh
2021-06-23Merge pull request #219 from cmarcelo/SPV_EXT_shader_atomic_float16_addRaun Krisch
Add header changes for SPV_EXT_shader_atomic_float16_add
2021-06-16Support SPV_KHR_integer_dot_productDavid Neto
Signed-off-by: David Neto <dneto@google.com> Signed-off-by: Kevin Petit <kevin.petit@arm.com> Change-Id: Icd243bb9c2a6f8a40713db215a6ca5946ea7abb3
2021-06-16Add header changes for SPV_EXT_shader_atomic_float16_addJason Ekstrand
2021-06-16Fix two ordering problems.John Kessenich
2021-06-09Merge pull request #213 from alan-baker/SPV_KHR_subgroup_uniform_control_flowRaun Krisch
Support SPV_KHR_subgroup_uniform_control_flow
2021-06-09Merge pull request #217 from StuartDBrady/add-C++-for-OpenCL-langRaun Krisch
Add CPP_for_OpenCL to grammar
2021-06-09Merge pull request #177 from MrSidims/private/MrSidims/APRaun Krisch
Upstream ac_fixed and hls_float Intel extensions
2021-06-09Add CPP_for_OpenCL to grammarStuart Brady
2021-06-07Support SPV_KHR_subgroup_uniform_control_flowDavid Neto
2021-06-03Update arbitrary float cast interfacesArtem Gindinson
Signed-off-by: Artem Gindinson <artem.gindinson@intel.com>
2021-05-14Fix OpTypeBufferSurfaceINTEL token description (#207)Nikita Rudenko
Fix OpTypeBufferSurfaceINTEL token description
2021-04-23Add VectorComputeINTEL as enabling capability for Private StorageClassNikita Rudenko
According to spec: https://github.com/intel/llvm/pull/1612
2021-03-31Upstream AP Intel extensionsDmitry Sidorov
SPV_INTEL_arbitrary_precision_floating_point and SPV_INTEL_arbitrary_precision_fixed_point extensions are being upstreamed. Specs: https://github.com/intel/llvm/blob/2f6e965e686354fbb25f9c177a667a646de302eb/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_fixed_point.asciidoc https://github.com/intel/llvm/blob/bd86b218f749ea0e20ddc18c42db491faf54014a/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_floating_point.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-03-24Add NonSemantic.Vulkan.DebugInfo.100 JSON/headerbaldurk
2021-03-05Support SPV_KHR_expect_assumeDavid Neto
2021-03-05Support SPV_KHR_linkonce_odrDavid Neto
2021-03-01Change operand name in OpReadClockKHR to match extensionAlan Baker
* The grammar was not updated when revision 3 of SPV_KHR_shader_clock was published * That revision renamed the *Execution* operand to *Scope*
2021-02-19Merge pull request #193 from bashbaug/DebugInfoFlags-NoneJohn Kessenich
add None as a possible value for DebugInfoFlags
2021-02-10Merge pull request #190 from dneto0/check-enumerant-orderingJohn Kessenich
Header generator: Check enumerant ordering
2021-01-27Add header changes for SPV_EXT_shader_atomic_float_min_maxJason Ekstrand
2021-01-27Re-run buildSpvHeaders to fix indentationJason Ekstrand
2021-01-27Header generator: Check enumerant orderingDavid Neto
In the grammar, enforce ordering rules: - Instructions must appear in order of their opcode - Non-instructions: each successive enumerant within a single kind must appear in order - Reorder enumerants Subgroup*MaskKHR enums to satisfy the rule.
2021-01-27add generated headersBen Ashbaugh
2021-01-27add None as a possible value for DebugInfoFlagsBen Ashbaugh
2021-01-25Add SPV_KHR_workgroup_memory_explicit_layoutCaio Marcelo de Oliveira Filho
2021-01-20Push FPDenormMode, FPOperationMode to the endDavid Neto
This is a cosmetic change for the benefit of generating the SPIR-V spec. It reorders the "FP Denorm Mode" and "FP Operation Mode" so they are the last sections in chapter 3 before the instruction listing. They become 3.37 and 3.38. The idea is to preserve the section numbering for earlier sections. For example, keep 3.31 as the Capability section.
2021-01-20Apply suggestions to Intel extensions PRDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Update generated filesDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Add SPV_INTEL_long_constant_composite extensionDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Add SPV_INTEL_loop_fuse extensionDmitry Sidorov
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
2021-01-20Add SPV_INTEL_fpga_cluster_attributes and SPV_INTEL_fp_fast_math_modeDmitry Sidorov
Spec: https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fpga_cluster_attributes.asciidoc https://github.com/KhronosGroup/SPIRV-Registry/blob/7d96a31cf56c60de76a6ae7a26ace3c7bfd999bf/extensions/INTEL/SPV_INTEL_fp_fast_math_mode.asciidoc Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 02:46:23 +0000