Age | Commit message (Collapse) | Author |
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- Run on Linux, macOS and Windows
- Check that the headers install works
- Check the example can be built
- Check the header generation tool can be built
- Generate headers and check they match the committed files
- Mention the requirement to install the header generation tool in README
Change-Id: I8385b3931064ad677d7aa49b2514cea9b4602168
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
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Signed-off-by: David Neto <dneto@google.com>
Signed-off-by: Kevin Petit <kevin.petit@arm.com>
Change-Id: Icd243bb9c2a6f8a40713db215a6ca5946ea7abb3
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Upstream ac_fixed and hls_float Intel extensions
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Fixes warnings in AppleClang
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This matches the CMakeLists.txt file in the project root.
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SPV_INTEL_arbitrary_precision_floating_point and
SPV_INTEL_arbitrary_precision_fixed_point extensions are
being upstreamed.
Specs:
https://github.com/intel/llvm/blob/2f6e965e686354fbb25f9c177a667a646de302eb/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_fixed_point.asciidoc
https://github.com/intel/llvm/blob/bd86b218f749ea0e20ddc18c42db491faf54014a/sycl/doc/extensions/SPIRV/SPV_INTEL_arbitrary_precision_floating_point.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
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In the grammar, enforce ordering rules:
- Instructions must appear in order of their opcode
- Non-instructions: each successive enumerant within a single kind must
appear in order
- Reorder enumerants Subgroup*MaskKHR enums to satisfy the rule.
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This is a cosmetic change for the benefit of generating the SPIR-V spec.
It reorders the "FP Denorm Mode" and "FP Operation Mode" so they are
the last sections in chapter 3 before the instruction listing.
They become 3.37 and 3.38. The idea is to preserve the section numbering
for earlier sections. For example, keep 3.31 as the Capability section.
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Spec:
https://github.com/intel/llvm/blob/39fa9b0cbfbae88327118990a05c5b387b56d2ef/sycl/doc/extensions/SPIRV/SPV_INTEL_float_controls2.asciidoc
Signed-off-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
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instruction set (#164)
* Clspv non-semantic reflection instruction set
* Version 1
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Add SPV_KHR_ray_{tracing,query} to headers
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and update copyright notices
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instruction sets (#143)
* Add JSON grammars for extened instruction sets
Add AMD extended instruction sets
Add DebugInfo
Add OpenCL.DebugInfo.100
* Add script to generate C headers from extinst grammar
This is cloned then adapted from the same-named script in SPIRV-Tools
(contributed under same authorship but different copyright).
Invoke the script as part of the overall header generation script.
* Add generated C header for extended instruction sets
Add for DebugInfo and OpenCLDebugInfo
Add for AMD vendor extended instruction sets
* Update the README for extinst header generation
* Fix header include guard to match directory structure
* Ensure generated header ends in newline
* Fix typo in file reference
* Fix name of AMD_shader_explicit_vertex_parameter.h
* Avoid duplicate generation
* Split Revision and Version enum values by newlines
Per code review request
* Convert C header generator driver to Python3
* Fix README for Python3 for extinst header generation
* Use 4-space in generated headers, consistently
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This seems to have gotten dropped in the latest update.
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Each instruction belongs to exactly one instruction class.
@exclude will put in the headers, but not in the specification.
Reserved is for instructions that are both to be reserved in the
specification and not yet put into another printing class.
(It is okay to establish a printing class for a reserved instruction.)
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weren't any until SPIR-V 1.4 release, now there are two.
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type. Currently only implemented in C-based printers.
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- SPV_KHR_float_controls
- SPV_KHR_no_integer_wrap_decoration
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This adds support of C# in buildHeaders.
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Use /usr/bin/env to avoid hardcoding path to bash
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* SPV_GOOGLE_decorate_string
* SPV_GOOGLE_hlsl_functionality1
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