diff options
Diffstat (limited to 'original/uapi/asm-x86')
| -rw-r--r-- | original/uapi/asm-x86/asm/bpf_perf_event.h | 1 | ||||
| -rw-r--r-- | original/uapi/asm-x86/asm/kvm_para.h | 1 | ||||
| -rw-r--r-- | original/uapi/asm-x86/asm/processor-flags.h | 12 |
3 files changed, 12 insertions, 2 deletions
diff --git a/original/uapi/asm-x86/asm/bpf_perf_event.h b/original/uapi/asm-x86/asm/bpf_perf_event.h new file mode 100644 index 0000000..3097758 --- /dev/null +++ b/original/uapi/asm-x86/asm/bpf_perf_event.h @@ -0,0 +1 @@ +#include <asm-generic/bpf_perf_event.h> diff --git a/original/uapi/asm-x86/asm/kvm_para.h b/original/uapi/asm-x86/asm/kvm_para.h index 554aa8f..09cc064 100644 --- a/original/uapi/asm-x86/asm/kvm_para.h +++ b/original/uapi/asm-x86/asm/kvm_para.h @@ -110,5 +110,4 @@ struct kvm_vcpu_pv_apf_data { #define KVM_PV_EOI_ENABLED KVM_PV_EOI_MASK #define KVM_PV_EOI_DISABLED 0x0 - #endif /* _UAPI_ASM_X86_KVM_PARA_H */ diff --git a/original/uapi/asm-x86/asm/processor-flags.h b/original/uapi/asm-x86/asm/processor-flags.h index 6f33553..bcba3c6 100644 --- a/original/uapi/asm-x86/asm/processor-flags.h +++ b/original/uapi/asm-x86/asm/processor-flags.h @@ -78,7 +78,12 @@ #define X86_CR3_PWT _BITUL(X86_CR3_PWT_BIT) #define X86_CR3_PCD_BIT 4 /* Page Cache Disable */ #define X86_CR3_PCD _BITUL(X86_CR3_PCD_BIT) -#define X86_CR3_PCID_MASK _AC(0x00000fff,UL) /* PCID Mask */ + +#define X86_CR3_PCID_BITS 12 +#define X86_CR3_PCID_MASK (_AC((1UL << X86_CR3_PCID_BITS) - 1, UL)) + +#define X86_CR3_PCID_NOFLUSH_BIT 63 /* Preserve old PCID */ +#define X86_CR3_PCID_NOFLUSH _BITULL(X86_CR3_PCID_NOFLUSH_BIT) /* * Intel CPU features in CR4 @@ -105,6 +110,8 @@ #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) +#define X86_CR4_UMIP_BIT 11 /* enable UMIP support */ +#define X86_CR4_UMIP _BITUL(X86_CR4_UMIP_BIT) #define X86_CR4_LA57_BIT 12 /* enable 5-level page tables */ #define X86_CR4_LA57 _BITUL(X86_CR4_LA57_BIT) #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ @@ -152,5 +159,8 @@ #define CX86_ARR_BASE 0xc4 #define CX86_RCR_BASE 0xdc +#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \ + X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \ + X86_CR0_PG) #endif /* _UAPI_ASM_X86_PROCESSOR_FLAGS_H */ |