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| author | Shai Barack <shayba@google.com> | 2015-04-17 09:07:12 -0700 |
|---|---|---|
| committer | Shai Barack <shayba@google.com> | 2015-04-17 09:09:43 -0700 |
| commit | 7a2faed4a1ef04d83af961907468a35c2204c51a (patch) | |
| tree | f417e15c294be6cd4bcea1c8ab2d98abb961befe | |
| parent | 35fd3a02a2a39ed61e8b0bfea1f20417866fc0f1 (diff) | |
| download | leveldb-7a2faed4a1ef04d83af961907468a35c2204c51a.tar.gz | |
LevelDB atomic_pointer support for AMD64
Change-Id: I7a9b2ef8e78a34b8d6a2ce26d363feeda7ed56a9
| -rw-r--r-- | leveldb-1.18/port/atomic_pointer.h | 21 |
1 files changed, 16 insertions, 5 deletions
diff --git a/leveldb-1.18/port/atomic_pointer.h b/leveldb-1.18/port/atomic_pointer.h index 073dbf4..df6b215 100644 --- a/leveldb-1.18/port/atomic_pointer.h +++ b/leveldb-1.18/port/atomic_pointer.h @@ -35,6 +35,8 @@ #define ARCH_CPU_X86_FAMILY 1 #elif defined(__ARMEL__) #define ARCH_CPU_ARM_FAMILY 1 +#elif defined(__aarch64__) +#define ARCH_CPU_ARM64_FAMILY 1 #elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__) #define ARCH_CPU_PPC_FAMILY 1 #elif defined(__mips__) @@ -94,12 +96,10 @@ inline void MemoryBarrier() { } #define LEVELDB_HAVE_MEMORY_BARRIER -// PPC -#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__) +// ARM64 +#elif defined(ARCH_CPU_ARM64_FAMILY) inline void MemoryBarrier() { - // TODO for some powerpc expert: is there a cheaper suitable variant? - // Perhaps by having separate barriers for acquire and release ops. - asm volatile("sync" : : : "memory"); + asm volatile("dmb sy" : : : "memory"); } #define LEVELDB_HAVE_MEMORY_BARRIER @@ -110,6 +110,15 @@ inline void MemoryBarrier() { } #define LEVELDB_HAVE_MEMORY_BARRIER +// PPC +#elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__) +inline void MemoryBarrier() { + // TODO for some powerpc expert: is there a cheaper suitable variant? + // Perhaps by having separate barriers for acquire and release ops. + asm volatile("sync" : : : "memory"); +} +#define LEVELDB_HAVE_MEMORY_BARRIER + #endif // AtomicPointer built using platform-specific MemoryBarrier() @@ -224,7 +233,9 @@ class AtomicPointer { #undef LEVELDB_HAVE_MEMORY_BARRIER #undef ARCH_CPU_X86_FAMILY #undef ARCH_CPU_ARM_FAMILY +#undef ARCH_CPU_ARM64_FAMILY #undef ARCH_CPU_PPC_FAMILY +#undef ARCH_CPU_MIPS_FAMILY } // namespace port } // namespace leveldb |