libchrome: Uprev the library to r369476 from Chromium

Pulled the latest and greatest version of libchrome from Chromium.

The merge was done against r369476 which corresponds to git commit
0471d0e2e2ef4a544a63481a389e1df33ea7c00a of Jan 14, 2016

Notable changes are:
- base::scoped_ptr<T> is now almost identical to std::unique_ptr<T>
  No Pass() method, now std::move() is used on scoped pointers
- basictypes.h is removed and custom int types such as int32 are now
  replaced with the standard int32_t and similar from <stdint.h>
- String utility functions are cleaned up/refactored. Now all are in
  base:: namespace, many now return values rather than take pointers
  for results, ambiguous Booleans are replaced with enums, such as:
    base::StartsWithASCII(current_url, "https://", false);
  now is:
    base::StartsWith(current_url, "https://",
                     base::CompareCase::INSENSITIVE_ASCII);
- COMPILE_ASSERT() is now replaced with standard static_assert()
- Numeric range constants such as kuint64max are removed in favor of
  standard <limits> constructs such as std::numeric_limits<uint64_t>::max()
- base::Value and derived classes use scoped_ptr<> more and support
  for raw pointers to base::Value is deprecated and/or removed in
  many places.
- base::MessageLoopProxy is completely removed (was marked deprecated before)
- base::MessageLoop::Quit() and QuitClosure are renamed to QuitWhenIdle
  and QuitWhenIdleClosure for more semantic clarity.

Change-Id: I1f5436d253a0a32b2299160a76993752d818736f

1 files changed, 20 insertions, 12 deletions

diff --git a/base/cpu.cc b/base/cpu.cc
index ef3309dad1..7135445664 100644
--- a/base/cpu.cc
+++ b/base/cpu.cc
@@ -4,12 +4,15 @@
 
 #include "base/cpu.h"
 
+#include <limits.h>
+#include <stddef.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
 
 #include <algorithm>
 
-#include "base/basictypes.h"
+#include "base/macros.h"
 #include "base/strings/string_piece.h"
 #include "build/build_config.h"
 
@@ -43,7 +46,7 @@ CPU::CPU()
     has_sse41_(false),
     has_sse42_(false),
     has_avx_(false),
-    has_avx_hardware_(false),
+    has_avx2_(false),
     has_aesni_(false),
     has_non_stop_time_stamp_counter_(false),
     has_broken_neon_(false),
@@ -72,7 +75,7 @@ void __cpuid(int cpu_info[4], int info_type) {
 
 void __cpuid(int cpu_info[4], int info_type) {
   __asm__ volatile (
-    "cpuid \n\t"
+    "cpuid\n"
     : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])
     : "a"(info_type)
   );
@@ -82,11 +85,12 @@ void __cpuid(int cpu_info[4], int info_type) {
 
 // _xgetbv returns the value of an Intel Extended Control Register (XCR).
 // Currently only XCR0 is defined by Intel so |xcr| should always be zero.
-uint64 _xgetbv(uint32 xcr) {
-  uint32 eax, edx;
+uint64_t _xgetbv(uint32_t xcr) {
+  uint32_t eax, edx;
 
-  __asm__ volatile ("xgetbv" : "=a" (eax), "=d" (edx) : "c" (xcr));
-  return (static_cast<uint64>(edx) << 32) | eax;
+  __asm__ volatile (
+    "xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
+  return (static_cast<uint64_t>(edx) << 32) | eax;
 }
 
 #endif  // !_MSC_VER
@@ -110,7 +114,7 @@ class LazyCpuInfoValue {
              revision = 0;
     const struct {
       const char key[17];
-      unsigned *result;
+      unsigned int* result;
     } kUnsignedValues[] = {
       {"CPU implementer", &implementer},
       {"CPU architecture", &architecture},
@@ -156,7 +160,7 @@ class LazyCpuInfoValue {
 
           // The string may have leading "0x" or not, so we use strtoul to
           // handle that.
-          char *endptr;
+          char* endptr;
           std::string value(value_sp.as_string());
           unsigned long int result = strtoul(value.c_str(), &endptr, 0);
           if (*endptr == 0 && result <= UINT_MAX) {
@@ -211,7 +215,11 @@ void CPU::Initialize() {
 
   // Interpret CPU feature information.
   if (num_ids > 0) {
+    int cpu_info7[4] = {0};
     __cpuid(cpu_info, 1);
+    if (num_ids >= 7) {
+      __cpuid(cpu_info7, 7);
+    }
     signature_ = cpu_info[0];
     stepping_ = cpu_info[0] & 0xf;
     model_ = ((cpu_info[0] >> 4) & 0xf) + ((cpu_info[0] >> 12) & 0xf0);
@@ -226,8 +234,6 @@ void CPU::Initialize() {
     has_ssse3_ = (cpu_info[2] & 0x00000200) != 0;
     has_sse41_ = (cpu_info[2] & 0x00080000) != 0;
     has_sse42_ = (cpu_info[2] & 0x00100000) != 0;
-    has_avx_hardware_ =
-                 (cpu_info[2] & 0x10000000) != 0;
     // AVX instructions will generate an illegal instruction exception unless
     //   a) they are supported by the CPU,
     //   b) XSAVE is supported by the CPU and
@@ -239,11 +245,12 @@ void CPU::Initialize() {
     // Because of that, we also test the XSAVE bit because its description in
     // the CPUID documentation suggests that it signals xgetbv support.
     has_avx_ =
-        has_avx_hardware_ &&
+        (cpu_info[2] & 0x10000000) != 0 &&
         (cpu_info[2] & 0x04000000) != 0 /* XSAVE */ &&
         (cpu_info[2] & 0x08000000) != 0 /* OSXSAVE */ &&
         (_xgetbv(0) & 6) == 6 /* XSAVE enabled by kernel */;
     has_aesni_ = (cpu_info[2] & 0x02000000) != 0;
+    has_avx2_ = has_avx_ && (cpu_info7[1] & 0x00000020) != 0;
   }
 
   // Get the brand string of the cpu.
@@ -275,6 +282,7 @@ void CPU::Initialize() {
 }
 
 CPU::IntelMicroArchitecture CPU::GetIntelMicroArchitecture() const {
+  if (has_avx2()) return AVX2;
   if (has_avx()) return AVX;
   if (has_sse42()) return SSE42;
   if (has_sse41()) return SSE41;