Delay 5ms after FW SW reset command due to clock instability.

This was preventing reliable FW download.

Change-Id: I28e5cb1e5855974f51578f5d45f2c581a75b2d07

1 files changed, 6 insertions, 0 deletions

diff --git a/src/phDnldNfc.c b/src/phDnldNfc.c
index 54d5b87..96f48dd 100644..100755
--- a/src/phDnldNfc.c
+++ b/src/phDnldNfc.c
@@ -39,6 +39,7 @@
 ################################################################################
 */
 #include <stdlib.h>
+#include <unistd.h>
 #include <phNfcConfig.h>
 #include <phNfcCompId.h>
 #include <phNfcIoctlCode.h>
@@ -2213,6 +2214,11 @@ phDnldNfc_Send_Complete (
             {
                 psDnldContext->resp_length = 0;
                 psDnldContext->dnld_retry = 0;
+                /* clock unstable after SW reset command, especially on UART
+                 * platform because of its sensitivity to clock. Experimentally
+                 * we found clock unstable for 750us. Delay for 5ms to be sure.
+                 */
+                usleep(5000);
                 status = phDnldNfc_Set_Seq(psDnldContext,
                                                 DNLD_SEQ_UPDATE);
             }