diff options
| -rw-r--r-- | include/libyuv/cpu_id.h | 2 | ||||
| -rw-r--r-- | source/cpu_id.cc | 1 | ||||
| -rw-r--r-- | unit_test/cpu_test.cc | 17 | ||||
| -rw-r--r-- | unit_test/testdata/mips.txt | 7 | ||||
| -rw-r--r-- | unit_test/testdata/mips_loongson2k.txt | 5 | ||||
| -rw-r--r-- | unit_test/testdata/mips_loongson3.txt | 10 | ||||
| -rw-r--r-- | unit_test/testdata/mips_loongson_mmi.txt | 7 | ||||
| -rw-r--r-- | unit_test/testdata/mips_msa.txt | 7 |
8 files changed, 55 insertions, 1 deletions
diff --git a/include/libyuv/cpu_id.h b/include/libyuv/cpu_id.h index b01cd25c..3e27cc10 100644 --- a/include/libyuv/cpu_id.h +++ b/include/libyuv/cpu_id.h @@ -71,6 +71,8 @@ static __inline int TestCpuFlag(int test_flag) { // Internal function for parsing /proc/cpuinfo. LIBYUV_API int ArmCpuCaps(const char* cpuinfo_name); +LIBYUV_API +int MipsCpuCaps(const char* cpuinfo_name); // For testing, allow CPU flags to be disabled. // ie MaskCpuFlags(~kCpuHasSSSE3) to disable SSSE3. diff --git a/source/cpu_id.cc b/source/cpu_id.cc index 047b0acc..936d7d34 100644 --- a/source/cpu_id.cc +++ b/source/cpu_id.cc @@ -163,7 +163,6 @@ LIBYUV_API SAFEBUFFERS int ArmCpuCaps(const char* cpuinfo_name) { } // TODO(fbarchard): Consider read_msa_ir(). -// TODO(fbarchard): Add unittest. LIBYUV_API SAFEBUFFERS int MipsCpuCaps(const char* cpuinfo_name) { char cpuinfo_line[512]; int flag = 0x0; diff --git a/unit_test/cpu_test.cc b/unit_test/cpu_test.cc index bc7af2f1..7264de08 100644 --- a/unit_test/cpu_test.cc +++ b/unit_test/cpu_test.cc @@ -160,6 +160,23 @@ TEST_F(LibYUVBaseTest, TestLinuxNeon) { #endif } +TEST_F(LibYUVBaseTest, TestLinuxMipsMsaMmi) { + if (FileExists("../../unit_test/testdata/mips.txt")) { + printf("Note: testing to load \"../../unit_test/testdata/mips.txt\"\n"); + + EXPECT_EQ(0, MipsCpuCaps("../../unit_test/testdata/mips.txt")); + EXPECT_EQ(kCpuHasMMI, + MipsCpuCaps("../../unit_test/testdata/mips_loongson3.txt")); + EXPECT_EQ(kCpuHasMMI, + MipsCpuCaps("../../unit_test/testdata/mips_loongson_mmi.txt")); + EXPECT_EQ(kCpuHasMSA, MipsCpuCaps("../../unit_test/testdata/mips_msa.txt")); + EXPECT_EQ(kCpuHasMMI | kCpuHasMSA, + MipsCpuCaps("../../unit_test/testdata/mips_loongson2k.txt")); + } else { + printf("WARNING: unable to load \"../../unit_test/testdata/mips.txt\"\n"); + } +} + // TODO(fbarchard): Fix clangcl test of cpuflags. #ifdef _MSC_VER TEST_F(LibYUVBaseTest, DISABLED_TestSetCpuFlags) { diff --git a/unit_test/testdata/mips.txt b/unit_test/testdata/mips.txt new file mode 100644 index 00000000..d9f28cbf --- /dev/null +++ b/unit_test/testdata/mips.txt @@ -0,0 +1,7 @@ +system type : generic-loongson-machine +machine : loongson,generic +processor : 0 + +isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 +ASEs implemented : vz +shadow register sets : 1 diff --git a/unit_test/testdata/mips_loongson2k.txt b/unit_test/testdata/mips_loongson2k.txt new file mode 100644 index 00000000..8a88d38f --- /dev/null +++ b/unit_test/testdata/mips_loongson2k.txt @@ -0,0 +1,5 @@ +system type : Loongson2K-SBC +machine : loongson,LS2k1000-EVP +processor : 0 +cpu model : Loongson-2K V0.3 FPU V0.1 +BogoMIPS : 1980.41 diff --git a/unit_test/testdata/mips_loongson3.txt b/unit_test/testdata/mips_loongson3.txt new file mode 100644 index 00000000..1f540b12 --- /dev/null +++ b/unit_test/testdata/mips_loongson3.txt @@ -0,0 +1,10 @@ +system type : generic-loongson-machine +machine : Unknown +processor : 0 +cpu model : ICT Loongson-3 V0.9 FPU V0.1 +model name : ICT Loongson-3A R3 (Loongson-3A3000) @ 1500MHz +BogoMIPS : 2990.15 + +isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 +ASEs implemented : dsp dsp2 vz +shadow register sets : 1 diff --git a/unit_test/testdata/mips_loongson_mmi.txt b/unit_test/testdata/mips_loongson_mmi.txt new file mode 100644 index 00000000..0f10b8bb --- /dev/null +++ b/unit_test/testdata/mips_loongson_mmi.txt @@ -0,0 +1,7 @@ +system type : generic-loongson-machine +machine : loongson,generic +processor : 0 + +isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 +ASEs implemented : vz loongson-mmi loongson-ext +shadow register sets : 1 diff --git a/unit_test/testdata/mips_msa.txt b/unit_test/testdata/mips_msa.txt new file mode 100644 index 00000000..ac930615 --- /dev/null +++ b/unit_test/testdata/mips_msa.txt @@ -0,0 +1,7 @@ +system type : generic-loongson-machine +machine : loongson,generic +processor : 0 + +isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 +ASEs implemented : vz msa +shadow register sets : 1 |