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Diffstat (limited to 'source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp')
-rw-r--r--source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp115
1 files changed, 33 insertions, 82 deletions
diff --git a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
index cbf3e7dfc..9d178dd97 100644
--- a/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
+++ b/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp
@@ -207,10 +207,8 @@ EmulateInstructionMIPS64::CreateInstance(const ArchSpec &arch,
}
bool EmulateInstructionMIPS64::SetTargetTriple(const ArchSpec &arch) {
- if (arch.GetTriple().getArch() == llvm::Triple::mips64 ||
- arch.GetTriple().getArch() == llvm::Triple::mips64el)
- return true;
- return false;
+ return arch.GetTriple().getArch() == llvm::Triple::mips64 ||
+ arch.GetTriple().getArch() == llvm::Triple::mips64el;
}
const char *EmulateInstructionMIPS64::GetRegisterName(unsigned reg_num,
@@ -1240,10 +1238,7 @@ bool EmulateInstructionMIPS64::Emulate_LD(llvm::MCInst &insn) {
Context context;
context.type = eContextRegisterLoad;
- if (!WriteRegister(context, &reg_info_src, data_src))
- return false;
-
- return true;
+ return WriteRegister(context, &reg_info_src, data_src);
}
return false;
@@ -1262,11 +1257,8 @@ bool EmulateInstructionMIPS64::Emulate_LUI(llvm::MCInst &insn) {
context.SetImmediateSigned(imm);
context.type = eContextImmediate;
- if (WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_zero_mips64 + rt,
- imm))
- return true;
-
- return false;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF,
+ dwarf_zero_mips64 + rt, imm);
}
bool EmulateInstructionMIPS64::Emulate_DSUBU_DADDU(llvm::MCInst &insn) {
@@ -1394,11 +1386,8 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops(llvm::MCInst &insn) {
context.type = eContextRelativeBranchImmediate;
context.SetImmediate(offset);
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
/*
@@ -1633,11 +1622,8 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops(llvm::MCInst &insn) {
context.type = eContextRelativeBranchImmediate;
context.SetImmediate(offset);
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BC(llvm::MCInst &insn) {
@@ -1659,11 +1645,8 @@ bool EmulateInstructionMIPS64::Emulate_BC(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
static int IsAdd64bitOverflow(int64_t a, int64_t b) {
@@ -1747,11 +1730,8 @@ bool EmulateInstructionMIPS64::Emulate_BXX_3ops_C(llvm::MCInst &insn) {
context.type = eContextRelativeBranchImmediate;
context.SetImmediate(current_inst_size + offset);
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
/*
@@ -1814,11 +1794,8 @@ bool EmulateInstructionMIPS64::Emulate_BXX_2ops_C(llvm::MCInst &insn) {
context.type = eContextRelativeBranchImmediate;
context.SetImmediate(current_inst_size + offset);
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_J(llvm::MCInst &insn) {
@@ -1841,10 +1818,8 @@ bool EmulateInstructionMIPS64::Emulate_J(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64, pc))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ pc);
}
bool EmulateInstructionMIPS64::Emulate_JAL(llvm::MCInst &insn) {
@@ -1973,11 +1948,8 @@ bool EmulateInstructionMIPS64::Emulate_JIC(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_JR(llvm::MCInst &insn) {
@@ -1998,11 +1970,8 @@ bool EmulateInstructionMIPS64::Emulate_JR(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- rs_val))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ rs_val);
}
/*
@@ -2052,11 +2021,8 @@ bool EmulateInstructionMIPS64::Emulate_FP_branch(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BC1EQZ(llvm::MCInst &insn) {
@@ -2091,11 +2057,8 @@ bool EmulateInstructionMIPS64::Emulate_BC1EQZ(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BC1NEZ(llvm::MCInst &insn) {
@@ -2130,11 +2093,8 @@ bool EmulateInstructionMIPS64::Emulate_BC1NEZ(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
/*
@@ -2193,11 +2153,8 @@ bool EmulateInstructionMIPS64::Emulate_3D_branch(llvm::MCInst &insn) {
Context context;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BNZB(llvm::MCInst &insn) {
@@ -2288,11 +2245,8 @@ bool EmulateInstructionMIPS64::Emulate_MSA_Branch_DF(llvm::MCInst &insn,
Context context;
context.type = eContextRelativeBranchImmediate;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_BNZV(llvm::MCInst &insn) {
@@ -2334,11 +2288,8 @@ bool EmulateInstructionMIPS64::Emulate_MSA_Branch_V(llvm::MCInst &insn,
Context context;
context.type = eContextRelativeBranchImmediate;
- if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
- target))
- return false;
-
- return true;
+ return WriteRegisterUnsigned(context, eRegisterKindDWARF, dwarf_pc_mips64,
+ target);
}
bool EmulateInstructionMIPS64::Emulate_LDST_Imm(llvm::MCInst &insn) {
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 03:01:00 +0000