Incremental squash-merge of aosp/dev to aosp/master

Bug: http://b/31320715

This merges commit d3221fcdce064148886034527a19dbd77743f9e2 from
aosp/dev including r283496.

Test: Build AOSP and run RenderScript tests (host tests for slang and
libbcc, RsTest, CTS)

Change-Id: I2cabd64cfa333498a4fec52bdf14eafb59676e14

8 files changed, 286 insertions, 3 deletions

diff --git a/lib/CodeGen/SafeStack.cpp b/lib/CodeGen/SafeStack.cpp
index 19cd59b9dba7..4a1b9958a5b5 100644
--- a/lib/CodeGen/SafeStack.cpp
+++ b/lib/CodeGen/SafeStack.cpp
@@ -530,7 +530,7 @@ Value *SafeStack::moveStaticAllocasToUnsafeStack(
     unsigned Align =
         std::max(DL->getPrefTypeAlignment(Ty), StackGuardSlot->getAlignment());
     SSL.addObject(StackGuardSlot, getStaticAllocaAllocationSize(StackGuardSlot),
-                  Align, SSC.getLiveRange(StackGuardSlot));
+                  Align, SSC.getFullLiveRange());
   }
 
   for (Argument *Arg : ByValArguments) {
diff --git a/lib/CodeGen/SafeStackColoring.cpp b/lib/CodeGen/SafeStackColoring.cpp
index 709614f57e7d..795eb8d27191 100644
--- a/lib/CodeGen/SafeStackColoring.cpp
+++ b/lib/CodeGen/SafeStackColoring.cpp
@@ -25,7 +25,9 @@ static cl::opt<bool> ClColoring("safe-stack-coloring",
                                 cl::Hidden, cl::init(true));
 
 const StackColoring::LiveRange &StackColoring::getLiveRange(AllocaInst *AI) {
-  return LiveRanges[AllocaNumbering[AI]];
+  const auto IT = AllocaNumbering.find(AI);
+  assert(IT != AllocaNumbering.end());
+  return LiveRanges[IT->second];
 }
 
 bool StackColoring::readMarker(Instruction *I, bool *IsStart) {
diff --git a/lib/CodeGen/SafeStackLayout.cpp b/lib/CodeGen/SafeStackLayout.cpp
index b8190e0f2153..fb433c1856a6 100644
--- a/lib/CodeGen/SafeStackLayout.cpp
+++ b/lib/CodeGen/SafeStackLayout.cpp
@@ -100,7 +100,8 @@ void StackLayout::layoutObject(StackObject &Obj) {
   }
 
   // Split starting and ending regions if necessary.
-  for (StackRegion &R : Regions) {
+  for (unsigned i = 0; i < Regions.size(); ++i) {
+    StackRegion &R = Regions[i];
     if (Start > R.Start && Start < R.End) {
       StackRegion R0 = R;
       R.Start = R0.End = Start;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index f2c548d6e0c3..25ccd95a433e 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -102,6 +102,11 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
   case ISD::CONCAT_VECTORS:
                          Res = PromoteIntRes_CONCAT_VECTORS(N); break;
 
+  case ISD::ANY_EXTEND_VECTOR_INREG:
+  case ISD::SIGN_EXTEND_VECTOR_INREG:
+  case ISD::ZERO_EXTEND_VECTOR_INREG:
+                         Res = PromoteIntRes_EXTEND_VECTOR_INREG(N); break;
+
   case ISD::SIGN_EXTEND:
   case ISD::ZERO_EXTEND:
   case ISD::ANY_EXTEND:  Res = PromoteIntRes_INT_EXTEND(N); break;
@@ -3333,6 +3338,25 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CONCAT_VECTORS(SDNode *N) {
   return DAG.getNode(ISD::BUILD_VECTOR, dl, NOutVT, Ops);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
+  EVT VT = N->getValueType(0);
+  EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
+  assert(NVT.isVector() && "This type must be promoted to a vector type");
+
+  SDLoc dl(N);
+
+  // For operands whose TypeAction is to promote, the promoted node to construct
+  // a new *_EXTEND_VECTOR_INREG node.
+  if (getTypeAction(N->getOperand(0).getValueType())
+      == TargetLowering::TypePromoteInteger) {
+    SDValue Promoted = GetPromotedInteger(N->getOperand(0));
+    return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
+  }
+
+  // Directly extend to the appropriate transform-to type.
+  return DAG.getNode(N->getOpcode(), dl, NVT, N->getOperand(0));
+}
+
 SDValue DAGTypeLegalizer::PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N) {
   EVT OutVT = N->getValueType(0);
   EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 84ad8f83d906..95e3576d6166 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -242,6 +242,7 @@ private:
   SDValue PromoteIntRes_VECTOR_SHUFFLE(SDNode *N);
   SDValue PromoteIntRes_BUILD_VECTOR(SDNode *N);
   SDValue PromoteIntRes_SCALAR_TO_VECTOR(SDNode *N);
+  SDValue PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N);
   SDValue PromoteIntRes_INSERT_VECTOR_ELT(SDNode *N);
   SDValue PromoteIntRes_CONCAT_VECTORS(SDNode *N);
   SDValue PromoteIntRes_BITCAST(SDNode *N);
diff --git a/test/CodeGen/X86/promote-vec3.ll b/test/CodeGen/X86/promote-vec3.ll
new file mode 100644
index 000000000000..96e24109e99d
--- /dev/null
+++ b/test/CodeGen/X86/promote-vec3.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE41
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX_ANY
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX_ANY
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX_X86_64
+
+define <3 x i16> @zext_i8(<3 x i8>) {
+; SSE3-LABEL: zext_i8:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $0, %eax, %xmm0
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $1, %eax, %xmm0
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $2, %eax, %xmm0
+; SSE3-NEXT:    pxor %xmm1, %xmm1
+; SSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
+; SSE3-NEXT:    movd %xmm0, %eax
+; SSE3-NEXT:    pextrw $2, %xmm0, %edx
+; SSE3-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE3-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE3-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; SSE3-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; SSE3-NEXT:    retl
+;
+; SSE41-LABEL: zext_i8:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pxor %xmm0, %xmm0
+; SSE41-NEXT:    pinsrb $0, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pinsrb $4, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pinsrb $8, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    movd %xmm0, %eax
+; SSE41-NEXT:    pextrw $2, %xmm0, %edx
+; SSE41-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE41-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE41-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; SSE41-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; SSE41-NEXT:    retl
+;
+; AVX_ANY-LABEL: zext_i8:
+; AVX_ANY:       # BB#0:
+; AVX_ANY-NEXT:    vpxor %xmm0, %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $0, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vmovd %xmm0, %eax
+; AVX_ANY-NEXT:    vpextrw $2, %xmm0, %edx
+; AVX_ANY-NEXT:    vpextrw $4, %xmm0, %ecx
+; AVX_ANY-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX_ANY-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; AVX_ANY-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; AVX_ANY-NEXT:    retl
+;
+; AVX_X86_64-LABEL: zext_i8:
+; AVX_X86_64:       # BB#0:
+; AVX_X86_64-NEXT:    vmovd %edi, %xmm0
+; AVX_X86_64-NEXT:    vpinsrd $1, %esi, %xmm0, %xmm0
+; AVX_X86_64-NEXT:    vpinsrd $2, %edx, %xmm0, %xmm0
+; AVX_X86_64-NEXT:    vpand {{.*}}(%rip), %xmm0, %xmm0
+; AVX_X86_64-NEXT:    vmovd %xmm0, %eax
+; AVX_X86_64-NEXT:    vpextrw $2, %xmm0, %edx
+; AVX_X86_64-NEXT:    vpextrw $4, %xmm0, %ecx
+; AVX_X86_64-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX_X86_64-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; AVX_X86_64-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; AVX_X86_64-NEXT:    retq
+  %2 = zext <3 x i8> %0 to <3 x i16>
+  ret <3 x i16> %2
+}
+
+define <3 x i16> @sext_i8(<3 x i8>) {
+; SSE3-LABEL: sext_i8:
+; SSE3:       # BB#0:
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $0, %eax, %xmm0
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $1, %eax, %xmm0
+; SSE3-NEXT:    movzbl {{[0-9]+}}(%esp), %eax
+; SSE3-NEXT:    pinsrw $2, %eax, %xmm0
+; SSE3-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSE3-NEXT:    psrad $16, %xmm0
+; SSE3-NEXT:    movd %xmm0, %eax
+; SSE3-NEXT:    pextrw $2, %xmm0, %edx
+; SSE3-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE3-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE3-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; SSE3-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; SSE3-NEXT:    retl
+;
+; SSE41-LABEL: sext_i8:
+; SSE41:       # BB#0:
+; SSE41-NEXT:    pinsrb $0, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pinsrb $4, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pinsrb $8, {{[0-9]+}}(%esp), %xmm0
+; SSE41-NEXT:    pslld $24, %xmm0
+; SSE41-NEXT:    psrad $24, %xmm0
+; SSE41-NEXT:    movd %xmm0, %eax
+; SSE41-NEXT:    pextrw $2, %xmm0, %edx
+; SSE41-NEXT:    pextrw $4, %xmm0, %ecx
+; SSE41-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; SSE41-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; SSE41-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; SSE41-NEXT:    retl
+;
+; AVX_ANY-LABEL: sext_i8:
+; AVX_ANY:       # BB#0:
+; AVX_ANY-NEXT:    vpinsrb $0, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $4, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpinsrb $8, {{[0-9]+}}(%esp), %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpslld $24, %xmm0, %xmm0
+; AVX_ANY-NEXT:    vpsrad $24, %xmm0, %xmm0
+; AVX_ANY-NEXT:    vmovd %xmm0, %eax
+; AVX_ANY-NEXT:    vpextrw $2, %xmm0, %edx
+; AVX_ANY-NEXT:    vpextrw $4, %xmm0, %ecx
+; AVX_ANY-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX_ANY-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; AVX_ANY-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; AVX_ANY-NEXT:    retl
+;
+; AVX_X86_64-LABEL: sext_i8:
+; AVX_X86_64:       # BB#0:
+; AVX_X86_64-NEXT:    vmovd %edi, %xmm0
+; AVX_X86_64-NEXT:    vpinsrd $1, %esi, %xmm0, %xmm0
+; AVX_X86_64-NEXT:    vpinsrd $2, %edx, %xmm0, %xmm0
+; AVX_X86_64-NEXT:    vpslld $24, %xmm0, %xmm0
+; AVX_X86_64-NEXT:    vpsrad $24, %xmm0, %xmm0
+; AVX_X86_64-NEXT:    vmovd %xmm0, %eax
+; AVX_X86_64-NEXT:    vpextrw $2, %xmm0, %edx
+; AVX_X86_64-NEXT:    vpextrw $4, %xmm0, %ecx
+; AVX_X86_64-NEXT:    # kill: %AX<def> %AX<kill> %EAX<kill>
+; AVX_X86_64-NEXT:    # kill: %DX<def> %DX<kill> %EDX<kill>
+; AVX_X86_64-NEXT:    # kill: %CX<def> %CX<kill> %ECX<kill>
+; AVX_X86_64-NEXT:    retq
+  %2 = sext <3 x i8> %0 to <3 x i16>
+  ret <3 x i16> %2
+}
diff --git a/test/Transforms/SafeStack/coloring-ssp.ll b/test/Transforms/SafeStack/coloring-ssp.ll
new file mode 100644
index 000000000000..d71babe200df
--- /dev/null
+++ b/test/Transforms/SafeStack/coloring-ssp.ll
@@ -0,0 +1,34 @@
+; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s
+
+; %x and %y share a stack slot between them, but not with the stack guard.
+define void @f() safestack sspreq {
+; CHECK-LABEL: define void @f
+entry:
+; CHECK:  %[[USP:.*]] = load i8*, i8** @__safestack_unsafe_stack_ptr
+; CHECK:   getelementptr i8, i8* %[[USP]], i32 -16
+
+; CHECK:  %[[A:.*]] = getelementptr i8, i8* %[[USP]], i32 -8
+; CHECK:  %[[StackGuardSlot:.*]] = bitcast i8* %[[A]] to i8**
+; CHECK:  store i8* %{{.*}}, i8** %[[StackGuardSlot]]
+
+  %x = alloca i64, align 8
+  %y = alloca i64, align 8
+  %x0 = bitcast i64* %x to i8*
+  %y0 = bitcast i64* %y to i8*
+
+  call void @llvm.lifetime.start(i64 -1, i8* %x0)
+; CHECK:  getelementptr i8, i8* %[[USP]], i32 -16
+  call void @capture64(i64* %x)
+  call void @llvm.lifetime.end(i64 -1, i8* %x0)
+
+  call void @llvm.lifetime.start(i64 -1, i8* %y0)
+; CHECK:  getelementptr i8, i8* %[[USP]], i32 -16
+  call void @capture64(i64* %y)
+  call void @llvm.lifetime.end(i64 -1, i8* %y0)
+
+  ret void
+}
+
+declare void @llvm.lifetime.start(i64, i8* nocapture)
+declare void @llvm.lifetime.end(i64, i8* nocapture)
+declare void @capture64(i64*)
diff --git a/test/Transforms/SafeStack/layout-region-split.ll b/test/Transforms/SafeStack/layout-region-split.ll
new file mode 100644
index 000000000000..ceb18bb70c20
--- /dev/null
+++ b/test/Transforms/SafeStack/layout-region-split.ll
@@ -0,0 +1,84 @@
+; Regression test for safestack layout. Used to fail with asan.
+; RUN: opt -safe-stack -S -mtriple=x86_64-pc-linux-gnu < %s -o - | FileCheck %s
+
+define void @f() safestack {
+; CHECK-LABEL: define void @f
+entry:
+; CHECK:  %[[USP:.*]] = load i8*, i8** @__safestack_unsafe_stack_ptr
+; CHECK:   getelementptr i8, i8* %[[USP]], i32 -224
+
+  %x0 = alloca i8, align 16
+  %x1 = alloca i8, align 16
+  %x2 = alloca i8, align 16
+  %x3 = alloca i8, align 16
+  %x4 = alloca i8, align 16
+  %x5 = alloca i8, align 16
+  %x6 = alloca i8, align 16
+  %x7 = alloca i8, align 16
+  %x8 = alloca i8, align 16
+  %x9 = alloca i8, align 16
+  %x10 = alloca i8, align 16
+  %x11 = alloca i8, align 16
+  %x12 = alloca i8, align 16
+  %x13 = alloca i8, align 16
+  %y0 = alloca i8, align 2
+  %y1 = alloca i8, align 2
+  %y2 = alloca i8, align 2
+  %y3 = alloca i8, align 2
+  %y4 = alloca i8, align 2
+  %y5 = alloca i8, align 2
+  %y6 = alloca i8, align 2
+  %y7 = alloca i8, align 2
+  %y8 = alloca i8, align 2
+
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -16
+  call void @capture8(i8* %x0)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -32
+  call void @capture8(i8* %x1)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -48
+  call void @capture8(i8* %x2)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -64
+  call void @capture8(i8* %x3)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -80
+  call void @capture8(i8* %x4)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -96
+  call void @capture8(i8* %x5)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -112
+  call void @capture8(i8* %x6)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -128
+  call void @capture8(i8* %x7)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -144
+  call void @capture8(i8* %x8)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -160
+  call void @capture8(i8* %x9)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -176
+  call void @capture8(i8* %x10)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -192
+  call void @capture8(i8* %x11)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -208
+  call void @capture8(i8* %x12)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -224
+  call void @capture8(i8* %x13)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -2
+  call void @capture8(i8* %y0)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -4
+  call void @capture8(i8* %y1)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -6
+  call void @capture8(i8* %y2)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -8
+  call void @capture8(i8* %y3)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -10
+  call void @capture8(i8* %y4)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -12
+  call void @capture8(i8* %y5)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -14
+  call void @capture8(i8* %y6)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -18
+  call void @capture8(i8* %y7)
+; CHECK: getelementptr i8, i8* %[[USP]], i32 -20
+  call void @capture8(i8* %y8)
+
+  ret void
+}
+
+declare void @capture8(i8*)