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| author | Ahmed Bougacha <ahmed.bougacha@gmail.com> | 2016-05-31 18:50:25 +0000 |
|---|---|---|
| committer | Pirama Arumuga Nainar <pirama@google.com> | 2016-06-08 12:53:50 -0700 |
| commit | 72bbf14fe49e57a011ce3c628d6dca0aa603bd11 (patch) | |
| tree | 63bb0808643290884757dee1a391d25e0f40c535 | |
| parent | 2d36ca48fac1c897182807d77b90b74c44ea6cd3 (diff) | |
| download | llvm-72bbf14fe49e57a011ce3c628d6dca0aa603bd11.tar.gz | |
[CodeGen] Promote FMINNAN/FMAXNAN like other binops.nougat-dev
We think it's OK to generate half fminnan because it's legal for the
transform-to type (f32; r245196). However, PromoteFloatRes was missing
the case; simply promote like the other binops, including minnum.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@271317 91177308-0d34-0410-b5e6-96231b3b80d8
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/fp16-promote.ll | 34 |
2 files changed, 36 insertions, 0 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 6c0193a76732..309402eba1ac 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -1868,6 +1868,8 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) { // Binary FP Operations case ISD::FADD: case ISD::FDIV: + case ISD::FMAXNAN: + case ISD::FMINNAN: case ISD::FMAXNUM: case ISD::FMINNUM: case ISD::FMUL: diff --git a/test/CodeGen/ARM/fp16-promote.ll b/test/CodeGen/ARM/fp16-promote.ll index 2a2eb8d2b6ba..ec815d213647 100644 --- a/test/CodeGen/ARM/fp16-promote.ll +++ b/test/CodeGen/ARM/fp16-promote.ll @@ -642,6 +642,40 @@ define void @test_maxnum(half* %p, half* %q) #0 { ret void } +; CHECK-ALL-LABEL: test_minnan: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vmin.f32 +; CHECK-NOVFP: bl __aeabi_fcmpge +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL: bl __aeabi_f2h +define void @test_minnan(half* %p) #0 { + %a = load half, half* %p, align 2 + %c = fcmp ult half %a, 1.0 + %r = select i1 %c, half %a, half 1.0 + store half %r, half* %p + ret void +} + +; CHECK-ALL-LABEL: test_maxnan: +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-FP16: vcvtb.f32.f16 +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-LIBCALL: bl __aeabi_h2f +; CHECK-VFP: vmax.f32 +; CHECK-NOVFP: bl __aeabi_fcmple +; CHECK-FP16: vcvtb.f16.f32 +; CHECK-LIBCALL: bl __aeabi_f2h +define void @test_maxnan(half* %p) #0 { + %a = load half, half* %p, align 2 + %c = fcmp ugt half %a, 1.0 + %r = select i1 %c, half %a, half 1.0 + store half %r, half* %p + ret void +} + ; CHECK-FP16-LABEL: test_copysign: ; CHECK-FP16: vcvtb.f32.f16 ; CHECK-FP16: vcvtb.f32.f16 |