aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/WebAssembly/WebAssembly.td
diff options
context:
space:
mode:
authorPirama Arumuga Nainar <pirama@google.com>2016-03-03 15:48:50 -0800
committerPirama Arumuga Nainar <pirama@google.com>2016-03-03 16:08:14 -0800
commitf3ef5332fa3f4d5ec72c178a2b19dac363a19383 (patch)
treeb335b029f55ecd8145638c9d723e3680f098d516 /lib/Target/WebAssembly/WebAssembly.td
parent4310bcf018d080c679c61f59d2db434ccf06a412 (diff)
downloadllvm-f3ef5332fa3f4d5ec72c178a2b19dac363a19383.tar.gz
Update aosp/master LLVM for rebase to r256229
http://b/26987366 Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
Diffstat (limited to 'lib/Target/WebAssembly/WebAssembly.td')
-rw-r--r--lib/Target/WebAssembly/WebAssembly.td66
1 files changed, 66 insertions, 0 deletions
diff --git a/lib/Target/WebAssembly/WebAssembly.td b/lib/Target/WebAssembly/WebAssembly.td
new file mode 100644
index 000000000000..551ad9345154
--- /dev/null
+++ b/lib/Target/WebAssembly/WebAssembly.td
@@ -0,0 +1,66 @@
+//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// \brief This is a target description file for the WebAssembly architecture,
+/// which is also known as "wasm".
+///
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Target-independent interfaces which we are implementing
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/Target.td"
+
+//===----------------------------------------------------------------------===//
+// WebAssembly Subtarget features.
+//===----------------------------------------------------------------------===//
+
+def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
+ "Enable 128-bit SIMD">;
+
+//===----------------------------------------------------------------------===//
+// Architectures.
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Register File Description
+//===----------------------------------------------------------------------===//
+
+include "WebAssemblyRegisterInfo.td"
+
+//===----------------------------------------------------------------------===//
+// Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+include "WebAssemblyInstrInfo.td"
+
+def WebAssemblyInstrInfo : InstrInfo;
+
+//===----------------------------------------------------------------------===//
+// WebAssembly Processors supported.
+//===----------------------------------------------------------------------===//
+
+// Minimal Viable Product.
+def : ProcessorModel<"mvp", NoSchedModel, []>;
+
+// Generic processor: latest stable version.
+def : ProcessorModel<"generic", NoSchedModel, []>;
+
+// Latest and greatest experimental version of WebAssembly. Bugs included!
+def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
+
+//===----------------------------------------------------------------------===//
+// Target Declaration
+//===----------------------------------------------------------------------===//
+
+def WebAssembly : Target {
+ let InstructionSet = WebAssemblyInstrInfo;
+}