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author | Pirama Arumuga Nainar <pirama@google.com> | 2016-10-20 17:56:36 +0000 |
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committer | Stephen Hines <srhines@google.com> | 2016-10-25 01:00:19 -0700 |
commit | f3ca3afcd05d585f6a2b7c2f432b7c0b8dd5f1a3 (patch) | |
tree | f1a91ba36dba529eb6317e37b76394b1b62557c2 /lib | |
parent | bfb28599d323cca7e86f80507e7bfcadfeea178a (diff) | |
download | llvm-f3ca3afcd05d585f6a2b7c2f432b7c0b8dd5f1a3.tar.gz |
Fix *_EXTEND_VECTOR_INREG legalization
Summary:
While promoting *_EXTEND_VECTOR_INREG nodes whose inputs are already
promoted, perform the appropriate sign extension for the promoted node
before doing the *_EXTEND_VECTOR_INREG operation. If not, the undefined
high-order bits of the promoted operand may (a) be garbage inc ase of
zext) or (b) contribute the wrong sign-bit (in case of sext)
Updated the promote-vec3.ll test after this change. The diff shows
explicit zeroing in case of zext and intermediate sign extension in case
of sext.
Reviewers: RKSimon
Subscribers: llvm-commits, srhines
Differential Revision: https://reviews.llvm.org/D25790
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284752 91177308-0d34-0410-b5e6-96231b3b80d8
Change-Id: I64ef63d3920357e2818593e0d4ed0bdb41db3949
(cherry picked from commit a61ffbf0a65ae44cd90216e23b3b4ad5cb230381)
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 25ccd95a433e..ddd998bd1f20 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -3345,11 +3345,27 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) { SDLoc dl(N); - // For operands whose TypeAction is to promote, the promoted node to construct - // a new *_EXTEND_VECTOR_INREG node. + // For operands whose TypeAction is to promote, extend the promoted node + // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion + // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to + // type.. if (getTypeAction(N->getOperand(0).getValueType()) == TargetLowering::TypePromoteInteger) { - SDValue Promoted = GetPromotedInteger(N->getOperand(0)); + SDValue Promoted; + + switch(N->getOpcode()) { + case ISD::SIGN_EXTEND_VECTOR_INREG: + Promoted = SExtPromotedInteger(N->getOperand(0)); + break; + case ISD::ZERO_EXTEND_VECTOR_INREG: + Promoted = ZExtPromotedInteger(N->getOperand(0)); + break; + case ISD::ANY_EXTEND_VECTOR_INREG: + Promoted = GetPromotedInteger(N->getOperand(0)); + break; + default: + llvm_unreachable("Node has unexpected Opcode"); + } return DAG.getNode(N->getOpcode(), dl, NVT, Promoted); } |