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2021-02-12[LSC] Add LOCAL_LICENSE_KINDS to external/llvmBob Badour
Added SPDX-license-identifier-Apache-2.0 to: soong/Android.bp Added SPDX-license-identifier-Apache-2.0 SPDX-license-identifier-BSD SPDX-license-identifier-MIT SPDX-license-identifier-NCSA legacy_permissive legacy_unencumbered to: Android.bp Added SPDX-license-identifier-BSD SPDX-license-identifier-MIT SPDX-license-identifier-NCSA legacy_permissive legacy_unencumbered to: lib/Android.bp Added SPDX-license-identifier-BSD SPDX-license-identifier-MIT SPDX-license-identifier-NCSA legacy_unencumbered to: lib/Support/Android.bp Added SPDX-license-identifier-NCSA to: lib/Analysis/Android.bp lib/AsmParser/Android.bp lib/Bitcode/Android.bp lib/Bitcode/Reader/Android.bp lib/Bitcode/Writer/Android.bp lib/CodeGen/Android.bp lib/CodeGen/AsmPrinter/Android.bp lib/CodeGen/GlobalISel/Android.bp lib/CodeGen/MIRParser/Android.bp lib/CodeGen/SelectionDAG/Android.bp lib/DebugInfo/Android.bp lib/DebugInfo/CodeView/Android.bp lib/DebugInfo/DWARF/Android.bp lib/DebugInfo/PDB/Android.bp lib/DebugInfo/Symbolize/Android.bp lib/ExecutionEngine/Android.bp lib/ExecutionEngine/Interpreter/Android.bp lib/ExecutionEngine/MCJIT/Android.bp lib/ExecutionEngine/Orc/Android.bp lib/ExecutionEngine/RuntimeDyld/Android.bp lib/IR/Android.bp lib/IRReader/Android.bp lib/LTO/Android.bp lib/LibDriver/Android.bp lib/Linker/Android.bp lib/MC/Android.bp lib/MC/MCDisassembler/Android.bp lib/MC/MCParser/Android.bp lib/Object/Android.bp lib/ObjectYAML/Android.bp lib/Option/Android.bp lib/Passes/Android.bp lib/ProfileData/Android.bp lib/ProfileData/Coverage/Android.bp lib/TableGen/Android.bp lib/Target/AArch64/Android.bp lib/Target/AArch64/AsmParser/Android.bp lib/Target/AArch64/Disassembler/Android.bp lib/Target/AArch64/InstPrinter/Android.bp lib/Target/AArch64/MCTargetDesc/Android.bp lib/Target/AArch64/TargetInfo/Android.bp lib/Target/AArch64/Utils/Android.bp lib/Target/ARM/Android.bp lib/Target/ARM/AsmParser/Android.bp lib/Target/ARM/Disassembler/Android.bp lib/Target/ARM/InstPrinter/Android.bp lib/Target/ARM/MCTargetDesc/Android.bp lib/Target/ARM/TargetInfo/Android.bp lib/Target/Mips/Android.bp lib/Target/Mips/AsmParser/Android.bp lib/Target/Mips/Disassembler/Android.bp lib/Target/Mips/InstPrinter/Android.bp lib/Target/Mips/MCTargetDesc/Android.bp lib/Target/Mips/TargetInfo/Android.bp lib/Target/X86/Android.bp lib/Target/X86/AsmParser/Android.bp lib/Target/X86/Disassembler/Android.bp lib/Target/X86/InstPrinter/Android.bp lib/Target/X86/MCTargetDesc/Android.bp lib/Target/X86/TargetInfo/Android.bp lib/Target/X86/Utils/Android.bp lib/Transforms/Android.bp lib/Transforms/Hello/Android.bp lib/Transforms/IPO/Android.bp lib/Transforms/InstCombine/Android.bp lib/Transforms/Instrumentation/Android.bp lib/Transforms/ObjCARC/Android.bp lib/Transforms/Scalar/Android.bp lib/Transforms/Utils/Android.bp lib/Transforms/Vectorize/Android.bp utils/FileCheck/Android.bp utils/TableGen/Android.bp utils/count/Android.bp utils/not/Android.bp utils/yaml-bench/Android.bp Added SPDX-license-identifier-NCSA legacy_permissive to: lib/Target/Android.bp Added SPDX-license-identifier-NCSA legacy_unencumbered to: lib/Fuzzer/Android.bp Bug: 68860345 Bug: 151177513 Bug: 151953481 Test: m all Exempt-From-Owner-Approval: janitorial work Change-Id: I311edfa9e746d2076b64e1e36e5886d78aa046e7
2020-11-11Add product_available to product available modulesJustin Yun
vendor_available modules were available to product modules. However, not all vendor_available modules are required to be available to product modules. Some modules want to be available only to product modules but not vendor modules. To cover the requirement, we separate product_available from vendor_available. vendor_available will not provide product available module. Bug: 150902910 Test: build Change-Id: I3fcce553f52fe98542b7c44711a75fc7d633997f
2020-07-02Make libbcinfo buildable for native_bridgeVictor Khimenko
Bug: http://b/153609531 Test: m libbcinfo.native_bridge Change-Id: Ieada18ce1f69fa241b4244ca06139d86aa35c15d
2018-10-23Start reserving x18 by default on Android targets.Peter Collingbourne
This is a backport of LLVM r340889 to the external/llvm tree, the goal being to make RenderScript's JITed code reserve x18 as well. Change-Id: I1225f7d489387a39707d6888dc5e5d4d5b49b460
2018-07-11Add unittests to {ARM | AArch64}TargetParser.Zijiao Ma
Add unittest to {ARM | AArch64}TargetParser,and by the way correct problems as below: 1.Correct a incorrect indexing problem in AArch64TargetParser. The architecture enumeration is shared across ARM and AArch64 in original implementation.But In the code,I just used the index which was offset by the ARM, and this would index into the array incorrectly. To make AArch64 has its own arch enum,or we will do a lot of slowly iterating. 2.Correct a spelling error. The parameter of llvm::AArch64::getArchExtName. 3.Correct a writing mistake, in llvm::ARM::parseArchISA. Differential Revision: https://reviews.llvm.org/D21785 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276957 91177308-0d34-0410-b5e6-96231b3b80d8
2017-10-16Mark llvm headers and libLLVMSupport as vendor_availableJiyong Park
They are depended by libbcinfo which is a VNDK-SP library. Since they are headers and static library, vendor_available: true is enough. Bug: 64425518 Bug: 64395154 Test: BOARD_VNDK_VERSION=current m -j libbcinfo.vendor Merged-In: I4415abb6779776758e780a008c560cbb4ef2c020 Change-Id: I4415abb6779776758e780a008c560cbb4ef2c020 (cherry picked from commit 55404a0d1fd034d6f5b41aa2e1f2c4aea541330a)
2017-06-12[AArch64] Add fallback in FastISel fp16 conversionsI-Jui (Ray) Sung
Summary: - Fix assertion failures on F16 to/from int types in FastISel by falling back to regular ISel - Add a testcase of various conversion cases with FastISel (-O0) Reviewers: kristof.beyls, jmolloy, SjoerdMeijer Reviewed By: SjoerdMeijer Subscribers: SjoerdMeijer, llvm-commits, srhines, pirama, aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D33734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305127 91177308-0d34-0410-b5e6-96231b3b80d8 (cherry picked from commit dedc24f891c1b93171865ed5e9c3a75d82a600c7) Change-Id: Id45a99255124b518f221b6ad8016198277b923cb
2016-12-13Rearrange header librariesColin Cross
Use a header library for the LLVM headers. External libraries can depend on the headers by depending on llvm-headers. All modules in LLVM get all the headers, including the autogenerated ones, except for the few that opt-out in order to allow tblgen to compile and generate the generated headers. Test: mma -j Change-Id: I5e0a58fdf9ade97337222822ddf8596a197aa442
2016-12-02Convert the rest of llvm to Android.bpColin Cross
A few makefiles still exist in external/llvm/*.mk, they are referenced outside external/llvm but no longer used by anything in external/llvm. Test: m -j checkbuild Change-Id: I8227d8feeac7314c237d2d3379b473dc0ee03ded
2016-12-01Convert libLLVM to Android.bpColin Cross
Test: m -j checkbuild Test: external/llvm/android_test.sh Test: compare symbols for out/host/linux-x86/lib64/libLLVM.so and prebuilts/sdk/tools/linux/lib64/libLLVM.so, only difference is removed RTTI symbols Change-Id: Iead18820cf19c678365978ee3b13e1fd9336e305
2016-10-24Update aosp/master LLVM for rebase to r275480Pirama Arumuga Nainar
Bug: http://b/31320715 This merges commit 7dcf7f03e005379ef2f06db96aa93f06186b66d5 from aosp/dev. Test: Build AOSP and run RenderScript tests (host tests for slang and libbcc, RsTest, CTS) Change-Id: Iaf3738f74312d875e69f61d604ac058f381a2a1a
2016-10-05Disable some clang-tidy checks.Chih-Hung Hsieh
Clang-tidy segmentation fault on llvm-nm.cpp, X86ISelLowering.cpp, etc. Bug: 31559947 Bug: 31938382 Bug: 31938645 Test: make with WITH_TIDY=1 and WITH_TIDY_CHECKS=* Change-Id: I0da80c3b1870f9017ed70d81f8cb36e1fe6ac4ac
2016-03-03Update aosp/master LLVM for rebase to r256229Pirama Arumuga Nainar
http://b/26987366 Change-Id: I1f29c4676a8abe633ab5707dded58d846c973d50
2015-09-02Stop checking HOST_OS, whitelist windows modulesDan Willemsen
Bug: 23566667 Change-Id: If7a149c047ccd36c7789eda3c29d6cc8977ca6d6
2015-07-08Update aosp/master LLVM for rebase to r239765Pirama Arumuga Nainar
Bug: 20140355: This rebase pulls the upstream fix for the spurious warnings mentioned in the bug. Change-Id: I7fd24253c50f4d48d900875dcf43ce3f1721a3da
2015-05-20Update aosp/master LLVM with patches for fp16Pirama Arumuga Nainar
Cherry-pick LLVM revisions r235191, r235215, r235220, r235341, r235363, r235530, r235609, r235610, r237004 r235191 has a required bug-fix and the rest are all related to fp16. Change-Id: I7fe8da5ffd8f2c06150885a54769abd18c3a04c6
2015-05-14Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
2015-04-13Remove duplicate.Ying Wang
This fixes build warnings: build/core/binary.mk:494: target `out/host/linux-x86/obj/STATIC_LIBRARIES/libLLVMARMCodeGen_intermediates/ARMGenCodeEmitter.inc' given more than once in the same rule. build/core/binary.mk:494: target `out/target/product/shamu/obj/STATIC_LIBRARIES/libLLVMARMCodeGen_intermediates/ARMGenCodeEmitter.inc' given more than once in the same rule. Change-Id: I4691fe616c1e13a4cc18ceaf3b64a3f2b9a5cd87
2015-04-09Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar
Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
2015-03-23Update aosp/master LLVM for rebase to r230699.Stephen Hines
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
2014-12-02Update aosp/master LLVM for rebase to r222494.Stephen Hines
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
2014-10-24Merge in the following upstream patches to resolve Cortex-A57 crashes.Stephen Hines
r214957 r215233 r216455 r216721 r217682 r217689 r217690 r217735 Change-Id: Ia53b88591471325df132caf26e1087510a65ce36
2014-10-17Bring in fixes for Cortex-A53 errata + build updates.Stephen Hines
Bug: 18034609 Change-Id: I2cf0094eb9df801a84274ff29018431d75da89dd
2014-07-21Update LLVM for rebase to r212749.Stephen Hines
Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
2014-06-04Updated the makefiles to use AArch64 name.Chris Wailes
The makefiles had previously used the name Arm64 for the AArch64 libraries. This patch changes all of makefiles to use the correct name for the backend. Change-Id: Ida062b1173b719b6d2519618827c3a67ede8b479
2014-05-29Update LLVM for 3.5 rebase (r209712).Stephen Hines
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
2014-04-24Update to LLVM 3.5a.Stephen Hines
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
2014-03-14Make LLVM build on AArch64.Tim Murray
bug 13343378 Change-Id: I4152d2437a144645fa0b5a425b7bfdcb3a2a5594
2014-02-18am b7485134: am 449fc261: Merge "llvm: convert makefiles to support multilib ↵Colin Cross
build" * commit 'b7485134a2cbecc47904988b4cfde24019ac4fa1': llvm: convert makefiles to support multilib build
2014-02-13Update LLVM for merge to 3.4.Stephen Hines
Update config.h files. Add RS SubtargetFeature for +long64 on ARM devices. Adjust Android.mk for added/removed files: + Delinearization.cpp - PathNumbering.cpp - PathProfileInfo.cpp - PathProfileVerifier.cpp - ProfileDataLoader.cpp - ProfileDataLoaderPass.cpp - ProfileEstimatorPass.cpp - ProfileInfo.cpp - ProfileInfoLoader.cpp - ProfileInfoLoaderPass.cpp - ProfileVerifierPass.cpp + LiveRegUnits.cpp - ShrinkWrapping.cpp + StackMaps.cpp - StrongPHIElimination.cpp + DIEHash.cpp + LegacyPassManager.cpp + ELF.cpp + Unicode.cpp - MipsOptimizeMathLibCalls.cpp - MipsELFStreamer.cpp + MipsTargetStreamer.cpp - EdgeProfiling.cpp + DataFlowSanitizer.cpp + DebugIR.cpp - OptimalEdgeProfiling.cpp - PathProfiling.cpp - ProfilingUtils.cpp - BasicBlockPlacement.cpp + LoopRerollPass.cpp + PartiallyInlineLibCalls.cpp + SampleProfile.cpp + GlobalStatus.cpp Change-Id: I17dcf0bf53a1720acd8226ae3e30d84993562a91
2014-02-11Merge remote-tracking branch 'upstream/release_34' into merge-20140211Stephen Hines
Conflicts: lib/Linker/LinkModules.cpp lib/Support/Unix/Signals.inc Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
2014-02-06llvm: convert makefiles to support multilib buildColin Cross
Convert makefiles to allow for building two architectures at the same time. This will also cause make checkbuild to build the target libraries for all supported architectures. Change-Id: Ia5e6fe5b1186a67753faafd3532ed4cb280a8b10
2013-12-20Merging r197492:Bill Wendling
------------------------------------------------------------------------ r197492 | dyatkovskiy | 2013-12-17 04:07:33 -0800 (Tue, 17 Dec 2013) | 26 lines Fix for PR18045: http://llvm.org/bugs/show_bug.cgi?id=18045 Short issue description: For X86 machines with sse < sse4.1 we got failures for some particular load/store vector sequences: $ clang-trunk -m32 -O2 test-case.c fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850, 0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82] [ID=58] 0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43] 0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23] 0x41dcb10: i32 = undef [ID=2] The reason is that EltsFromConsecutiveLoads could emit such load instruction both before and after legalize stage. Though this instruction is not legal for machines with SSSE3 and lower. The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we check whether nodes it emits are legal. P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8), perhaps I'll slow with response, so you better reject this commit. Thanks! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197779 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-14Merging r197228:Bill Wendling
------------------------------------------------------------------------ r197228 | d0k | 2013-12-13 05:40:24 -0800 (Fri, 13 Dec 2013) | 8 lines X86: When lowering shl_parts, don't emit shift amounts larger than the bit width. While it's safe for the X86-specific shift nodes, dag combining will kill generic nodes. Insert an AND to make it safe, isel will nuke it as x86's shift instructions have an implicit AND. Fixes PR16108, which contains a contraption to hit this case in between constant folders. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197321 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12Merging r-197100:Bill Wendling
------------------------------------------------------------------------ r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line Remove unused multiclass from PPCInstrInfo.td ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197131 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12Merging r197100:Bill Wendling
------------------------------------------------------------------------ r197100 | hfinkel | 2013-12-11 16:23:29 -0800 (Wed, 11 Dec 2013) | 1 line Remove unused multiclass from PPCInstrInfo.td ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197130 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-12Merging r197089:Bill Wendling
------------------------------------------------------------------------ r197089 | hfinkel | 2013-12-11 15:12:25 -0800 (Wed, 11 Dec 2013) | 6 lines Fix the PPC subsumes-predicate check For one predicate to subsume another, they must both check the same condition register. Failure to check this prerequisite was causing miscompiles. Fixes PR18003. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@197126 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-10Merging r196806:Bill Wendling
------------------------------------------------------------------------ r196806 | apazos | 2013-12-09 11:29:14 -0800 (Mon, 09 Dec 2013) | 11 lines Fix pattern match for movi with 0D result Patch by Jiangning Liu. With some test case changes: - intrinsic test added to the existing /test/CodeGen/AArch64/neon-aba-abd.ll. - New test cases to cover movi 1D scenario without using the intrinsic in test/CodeGen/AArch64/neon-mov.ll. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196872 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-09Merge rest of r196210. Some bits strayed into r196701, turning 3.4 red. ThisTim Northover
should fix the issue. ------------------------------------------------------------------------ r196210 | haoliu | 2013-12-03 06:06:55 +0000 (Tue, 03 Dec 2013) | 3 lines [AArch64]Add missing floating point convert, round and misc intrinsics. E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196772 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-09Merge r196725 (conflicts on same API as before):Tim Northover
------------------------------------------------------------------------ r196725 | tnorthover | 2013-12-08 15:56:50 +0000 (Sun, 08 Dec 2013) | 19 lines ARM: fix folding of stack-adjustment (yet again). When trying to eliminate an "sub sp, sp, #N" instruction by folding it into an existing push/pop using dummy registers, we need to account for the fact that this might affect precisely how "fp" gets set in the prologue. We were attempting this, but assuming that *whenever* we performed a fold it would make a difference. This is false, for example, in: push {r4, r7, lr} add fp, sp, #4 vpush {d8} sub sp, sp, #8 we can fold the "sub" into the "vpush", forming "vpush {d7, d8}". However, in that case the "add fp" instruction mustn't change, which we were getting wrong before. Should fix PR18160. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196769 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-09Merging r196751:Bill Wendling
------------------------------------------------------------------------ r196751 | venkatra | 2013-12-08 20:02:15 -0800 (Sun, 08 Dec 2013) | 3 lines [Sparc]: Implement getSetCCResultType() in SparcTargetLowering so that umulo/smulo can be lowered on sparcv9 without an assertion error. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196766 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-09Merging r196755:Bill Wendling
------------------------------------------------------------------------ r196755 | venkatra | 2013-12-08 21:13:25 -0800 (Sun, 08 Dec 2013) | 2 lines [SPARCV9]: Adjust the resultant pointer of DYNAMIC_STACKALLOC with the stack BIAS on sparcV9. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196764 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-09Merging r196735:Bill Wendling
------------------------------------------------------------------------ r196735 | venkatra | 2013-12-08 14:06:07 -0800 (Sun, 08 Dec 2013) | 3 lines [SparcV9]: Expand MULHU/MULHS:i64 and UMUL_LOHI/SMUL_LOHI:i64 on sparcv9. This fixes PR18150. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196744 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-08Merging r196493. Simple conflict due to change API of updatedTim Northover
function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196717 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-08Merging r196588:Bill Wendling
------------------------------------------------------------------------ r196588 | weimingz | 2013-12-06 09:56:48 -0800 (Fri, 06 Dec 2013) | 7 lines Bug 18149: [AArch32] VSel instructions has no ARMCC field The current peephole optimizing for compare inst assumes an instr that uses CPSR has an MO for ARM Cond code.However, for VSEL instructions (vseqeq, vselgt, vselgt, vselvs), there is no such operand nor do they support the modification of Cond Code. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196704 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-08Merging r196533:Bill Wendling
------------------------------------------------------------------------ r196533 | apazos | 2013-12-05 13:07:49 -0800 (Thu, 05 Dec 2013) | 3 lines Implemented vget/vset_lane_f16 intrinsics ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196701 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-08Merging r196456:Bill Wendling
------------------------------------------------------------------------ r196456 | jiangning | 2013-12-04 18:12:01 -0800 (Wed, 04 Dec 2013) | 2 lines For AArch64, add missing register cost calculation for big value types like v4i64 and v8i64. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196700 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-08Merging r196362:Bill Wendling
------------------------------------------------------------------------ r196362 | kevinqin | 2013-12-04 00:02:34 -0800 (Wed, 04 Dec 2013) | 1 line [AArch64 Neon] Add ACLE intrinsic vceqz_f64. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196699 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-08Merging r196360:Bill Wendling
------------------------------------------------------------------------ r196360 | kevinqin | 2013-12-03 23:53:28 -0800 (Tue, 03 Dec 2013) | 1 line [AArch64 NEON] Add missing compare intrinsics. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196697 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-08Merging r196208:Bill Wendling
------------------------------------------------------------------------ r196208 | haoliu | 2013-12-02 21:58:30 -0800 (Mon, 02 Dec 2013) | 3 lines AArch64: add missing ACLE intrinsics mapping to general arithmetic operation from VFP instructions. E.g. float64x1_t vadd_f64(float64x1_t a, float64x1_t b) -> FADD Dd, Dn, Dm. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196693 91177308-0d34-0410-b5e6-96231b3b80d8
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