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author | Petr Machata <pmachata@redhat.com> | 2013-09-26 14:03:14 +0200 |
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committer | Petr Machata <pmachata@redhat.com> | 2013-09-26 14:03:14 +0200 |
commit | 5aca651fdb40a3591a3b245092866fca22ef525d (patch) | |
tree | 893619690e15fc8773667c50a7a0757b64e09d1e /TODO | |
parent | cae76962c7e0ec6119952addb36d1cf8d19f5228 (diff) | |
download | ltrace-5aca651fdb40a3591a3b245092866fca22ef525d.tar.gz |
Update TODO
Diffstat (limited to 'TODO')
-rw-r--r-- | TODO | 14 |
1 files changed, 14 insertions, 0 deletions
@@ -133,6 +133,20 @@ | typedef ulong = uint8_t; | +** Support for ARM/AARCH64 types + - ARM and AARCH64 both support half-precision floating point + - there are two different half-precision formats, IEEE 754-2008 + and "alternative". Both have 10 bits of mantissa and 5 bits of + exponent, and differ only in how exponent==0x1F is handled. In + IEEE format, we get NaN's and infinities; in alternative + format, this encodes normalized value -1S × 2¹⁶ × (1.mant) + - The Floating-Point Control Register, FPCR, controls: — The + half-precision format where applicable, FPCR.AHP bit. + - AARCH64 supports fixed-point interpretation of {,double}words + - e.g. fixed(int, X) (int interpreted as a decimal number with X + binary digits of fraction). + - AARCH64 supports 128-bit quad words in SIMD + ** Some more functions in vect might be made to take const* Or even marked __attribute__((pure)). |