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author | Mike Lockwood <lockwood@android.com> | 2010-04-30 08:30:05 -0400 |
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committer | Mike Lockwood <lockwood@android.com> | 2010-04-30 08:30:05 -0400 |
commit | e815c52e5e4dd0bae3113d2409097160f27348c6 (patch) | |
tree | 211cbe7ad42c7c119f5b195f5287db301e4388c0 | |
parent | 751a4435c3ef705b0e31faa14c75b9e2fd859959 (diff) | |
download | oprofile-e815c52e5e4dd0bae3113d2409097160f27348c6.tar.gz |
Fix ARM7 build.
Change-Id: I7c07811f0e124b24f8be17c17c41061f045f4c4f
Signed-off-by: Mike Lockwood <lockwood@android.com>
-rw-r--r-- | opcontrol/opcontrol.cpp | 76 |
1 files changed, 38 insertions, 38 deletions
diff --git a/opcontrol/opcontrol.cpp b/opcontrol/opcontrol.cpp index 4cfc595..b5b82b6 100644 --- a/opcontrol/opcontrol.cpp +++ b/opcontrol/opcontrol.cpp @@ -198,87 +198,87 @@ struct event_info { "Exception taken"}, {0x0A, 0, "EXC_EXECUTED", "Exception return architecturally executed"}, - {0x0B, "CID_WRITE", + {0x0B, 0, "CID_WRITE", "Instruction that writes to the Context ID Register architecturally" "executed"}, - {0x0C, "PC_WRITE", + {0x0C, 0, "PC_WRITE", "SW change of PC, architecturally executed (not by exceptions)"}, - {0x0D, "PC_IMM_BRANCH", + {0x0D, 0, "PC_IMM_BRANCH", "Immediate branch instruction executed (taken or not)"}, - {0x0E, "PC_PROC_RETURN", + {0x0E, 0, "PC_PROC_RETURN", "Procedure return architecturally executed (not by exceptions)"}, - {0x0F, "UNALIGNED_ACCESS", + {0x0F, 0, "UNALIGNED_ACCESS", "Unaligned access architecturally executed"}, - {0x10, "PC_BRANCH_MIS_PRED", + {0x10, 0, "PC_BRANCH_MIS_PRED", "Branch mispredicted or not predicted. Counts pipeline flushes because of" "misprediction"}, - {0x12, "PC_BRANCH_MIS_USED", + {0x12, 0, "PC_BRANCH_MIS_USED", "Branch or change in program flow that could have been predicted"}, - {0x40, "WRITE_BUFFER_FULL", + {0x40, 0, "WRITE_BUFFER_FULL", "Any write buffer full cycle"}, - {0x41, "L2_STORE_MERGED", + {0x41, 0, "L2_STORE_MERGED", "Any store that is merged in L2 cache"}, - {0x42, "L2_STORE_BUFF", + {0x42, 0, "L2_STORE_BUFF", "Any bufferable store from load/store to L2 cache"}, - {0x43, "L2_ACCESS", + {0x43, 0, "L2_ACCESS", "Any access to L2 cache"}, - {0x44, "L2_CACH_MISS", + {0x44, 0, "L2_CACH_MISS", "Any cacheable miss in L2 cache"}, - {0x45, "AXI_READ_CYCLES", + {0x45, 0, "AXI_READ_CYCLES", "Number of cycles for an active AXI read"}, - {0x46, "AXI_WRITE_CYCLES", + {0x46, 0, "AXI_WRITE_CYCLES", "Number of cycles for an active AXI write"}, - {0x47, "MEMORY_REPLAY", + {0x47, 0, "MEMORY_REPLAY", "Any replay event in the memory subsystem"}, - {0x48, "UNALIGNED_ACCESS_REPLAY", + {0x48, 0, "UNALIGNED_ACCESS_REPLAY", "Unaligned access that causes a replay"}, - {0x49, "L1_DATA_MISS", + {0x49, 0, "L1_DATA_MISS", "L1 data cache miss as a result of the hashing algorithm"}, - {0x4A, "L1_INST_MISS", + {0x4A, 0, "L1_INST_MISS", "L1 instruction cache miss as a result of the hashing algorithm"}, - {0x4B, "L1_DATA_COLORING", + {0x4B, 0, "L1_DATA_COLORING", "L1 data access in which a page coloring alias occurs"}, - {0x4C, "L1_NEON_DATA", + {0x4C, 0, "L1_NEON_DATA", "NEON data access that hits L1 cache"}, - {0x4D, "L1_NEON_CACH_DATA", + {0x4D, 0, "L1_NEON_CACH_DATA", "NEON cacheable data access that hits L1 cache"}, - {0x4E, "L2_NEON", + {0x4E, 0, "L2_NEON", "L2 access as a result of NEON memory access"}, - {0x4F, "L2_NEON_HIT", + {0x4F, 0, "L2_NEON_HIT", "Any NEON hit in L2 cache"}, - {0x50, "L1_INST", + {0x50, 0, "L1_INST", "Any L1 instruction cache access, excluding CP15 cache accesses"}, - {0x51, "PC_RETURN_MIS_PRED", + {0x51, 0, "PC_RETURN_MIS_PRED", "Return stack misprediction at return stack pop" "(incorrect target address)"}, - {0x52, "PC_BRANCH_FAILED", + {0x52, 0, "PC_BRANCH_FAILED", "Branch prediction misprediction"}, - {0x53, "PC_BRANCH_TAKEN", + {0x53, 0, "PC_BRANCH_TAKEN", "Any predicted branch that is taken"}, - {0x54, "PC_BRANCH_EXECUTED", + {0x54, 0, "PC_BRANCH_EXECUTED", "Any taken branch that is executed"}, - {0x55, "OP_EXECUTED", + {0x55, 0, "OP_EXECUTED", "Number of operations executed" "(in instruction or mutli-cycle instruction)"}, - {0x56, "CYCLES_INST_STALL", + {0x56, 0, "CYCLES_INST_STALL", "Cycles where no instruction available"}, - {0x57, "CYCLES_INST", + {0x57, 0, "CYCLES_INST", "Number of instructions issued in a cycle"}, - {0x58, "CYCLES_NEON_DATA_STALL", + {0x58, 0, "CYCLES_NEON_DATA_STALL", "Number of cycles the processor waits on MRC data from NEON"}, - {0x59, "CYCLES_NEON_INST_STALL", + {0x59, 0, "CYCLES_NEON_INST_STALL", "Number of cycles the processor waits on NEON instruction queue or" "NEON load queue"}, - {0x5A, "NEON_CYCLES", + {0x5A, 0, "NEON_CYCLES", "Number of cycles NEON and integer processors are not idle"}, - {0x70, "PMU0_EVENTS", + {0x70, 0, "PMU0_EVENTS", "Number of events from external input source PMUEXTIN[0]"}, - {0x71, "PMU1_EVENTS", + {0x71, 0, "PMU1_EVENTS", "Number of events from external input source PMUEXTIN[1]"}, - {0x72, "PMU_EVENTS", + {0x72, 0, "PMU_EVENTS", "Number of events from both external input sources PMUEXTIN[0]" "and PMUEXTIN[1]"}, - {0xFF, "CPU_CYCLES", + {0xFF, 0, "CPU_CYCLES", "Number of CPU cycles"}, #endif }; |