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authorJeff Brown <jeffbrown@google.com>2011-02-02 14:00:44 -0800
committerJeff Brown <jeffbrown@google.com>2011-02-03 17:04:57 -0800
commit7a33c86eb98056ef0570c99e713214f8dc56b6ef (patch)
tree42c2be01c82f40fc93ab80d23c600b79985528dc /libop
parentb415faba7482dd7ee3335f0f1518333554e3da0d (diff)
downloadoprofile-7a33c86eb98056ef0570c99e713214f8dc56b6ef.tar.gz
Sync with oprofile CVS HEAD from Jan 11, 2011.
There have been a few patches to oprofile for newer ARM architectures since 0.9.6. Pruned out irrelevant auto-generated files from the previous dump so this is closer to being a mirror of the actual oprofile repository. Change-Id: I889053d30aae433a199a0a18585c66b88ff8de14
Diffstat (limited to 'libop')
-rw-r--r--libop/Makefile.in623
-rw-r--r--libop/op_cpu_type.c34
-rw-r--r--libop/op_cpu_type.h18
-rw-r--r--libop/op_events.c4
-rw-r--r--libop/op_hw_specific.h77
-rw-r--r--libop/op_xml_events.c20
-rw-r--r--libop/op_xml_out.c1
-rw-r--r--libop/op_xml_out.h1
-rw-r--r--libop/tests/Makefile.in601
-rw-r--r--libop/tests/alloc_counter_tests.c8
10 files changed, 136 insertions, 1251 deletions
diff --git a/libop/Makefile.in b/libop/Makefile.in
deleted file mode 100644
index a91b612..0000000
--- a/libop/Makefile.in
+++ /dev/null
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diff --git a/libop/op_cpu_type.c b/libop/op_cpu_type.c
index 4633fd1..ea3a530 100644
--- a/libop/op_cpu_type.c
+++ b/libop/op_cpu_type.c
@@ -87,10 +87,41 @@ static struct cpu_descr const cpu_descrs[MAX_CPU_TYPE] = {
{ "ARM Cortex-A9", "arm/armv7-ca9", CPU_ARM_V7_CA9, 7 },
{ "MIPS 74K", "mips/74K", CPU_MIPS_74K, 4},
{ "MIPS 1004K", "mips/1004K", CPU_MIPS_1004K, 2},
+ { "AMD64 family12h", "x86-64/family12h", CPU_FAMILY12H, 4 },
+ { "AMD64 family14h", "x86-64/family14h", CPU_FAMILY14H, 4 },
+ { "AMD64 family15h", "x86-64/family15h", CPU_FAMILY15H, 6 },
+ { "Intel Westmere microarchitecture", "i386/westmere", CPU_WESTMERE, 4 },
};
static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
+int op_cpu_variations(op_cpu cpu_type)
+{
+ switch (cpu_type) {
+ case CPU_ARCH_PERFMON:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+
+op_cpu op_cpu_base_type(op_cpu cpu_type)
+{
+ /* All the processors that support CPU_ARCH_PERFMON */
+ switch (cpu_type) {
+ case CPU_CORE_2:
+ case CPU_CORE_I7:
+ case CPU_ATOM:
+ case CPU_NEHALEM:
+ case CPU_WESTMERE:
+ return CPU_ARCH_PERFMON;
+ default:
+ /* assume processor in a class by itself */
+ return cpu_type;
+ }
+}
+
op_cpu op_get_cpu_type(void)
{
int cpu_type = CPU_NO_GOOD;
@@ -115,6 +146,9 @@ op_cpu op_get_cpu_type(void)
cpu_type = op_get_cpu_number(str);
+ if (op_cpu_variations(cpu_type))
+ cpu_type = op_cpu_specific_type(cpu_type);
+
fclose(fp);
return cpu_type;
diff --git a/libop/op_cpu_type.h b/libop/op_cpu_type.h
index 990e213..381b3c7 100644
--- a/libop/op_cpu_type.h
+++ b/libop/op_cpu_type.h
@@ -84,10 +84,28 @@ typedef enum {
CPU_ARM_V7_CA9, /**< ARM Cortex-A9 */
CPU_MIPS_74K, /**< MIPS 74K */
CPU_MIPS_1004K, /**< MIPS 1004K */
+ CPU_FAMILY12H, /**< AMD family 12h */
+ CPU_FAMILY14H, /**< AMD family 14h */
+ CPU_FAMILY15H, /**< AMD family 15h */
+ CPU_WESTMERE, /* Intel Westmere microarchitecture */
MAX_CPU_TYPE
} op_cpu;
/**
+ * the CPU lowest common denominator
+ *
+ * returns 1 if there are variations for the base cpu type;
+ */
+int op_cpu_variations(op_cpu cpu_type);
+
+/**
+ * get the CPU lowest common denominator
+ *
+ * returns cpu_type if cpu_type does not have a lowest common denominator.
+ */
+op_cpu op_cpu_base_type(op_cpu cpu_type);
+
+/**
* get the CPU type from the kernel
*
* returns CPU_NO_GOOD if the CPU could not be identified.
diff --git a/libop/op_events.c b/libop/op_events.c
index c3fcf57..4546dda 100644
--- a/libop/op_events.c
+++ b/libop/op_events.c
@@ -971,7 +971,11 @@ void op_default_event(op_cpu cpu_type, struct op_default_event_descr * descr)
case CPU_ATOM:
case CPU_CORE_I7:
case CPU_NEHALEM:
+ case CPU_WESTMERE:
case CPU_MIPS_LOONGSON2:
+ case CPU_FAMILY12H:
+ case CPU_FAMILY14H:
+ case CPU_FAMILY15H:
descr->name = "CPU_CLK_UNHALTED";
break;
diff --git a/libop/op_hw_specific.h b/libop/op_hw_specific.h
index 57d8149..36c06b3 100644
--- a/libop/op_hw_specific.h
+++ b/libop/op_hw_specific.h
@@ -56,39 +56,50 @@ static inline unsigned arch_cpuid_1(int code)
return val;
}
+static inline unsigned int cpuid_signature()
+{
+ return arch_cpuid_1(1);
+}
+
+static inline unsigned int cpu_model(unsigned int eax)
+{
+ unsigned model = (eax & 0xf0) >> 4;
+ unsigned ext_model = (eax & 0xf0000) >> 12;
+ return ext_model + model;
+}
+
+static inline unsigned int cpu_family(unsigned int eax)
+{
+ unsigned family = (eax & 0xf00) >> 8;
+ unsigned ext_family = (eax & 0xff00000) >> 20;
+ return ext_family + family;
+}
+
+static inline unsigned int cpu_stepping(unsigned int eax)
+{
+ return (eax & 0xf);
+}
+
/* Work around Nehalem spec update AAJ79: CPUID incorrectly indicates
unhalted reference cycle architectural event is supported. We assume
steppings after C0 report correct data in CPUID. */
static inline void workaround_nehalem_aaj79(unsigned *ebx)
{
- union {
- unsigned eax;
- struct {
- unsigned stepping : 4;
- unsigned model : 4;
- unsigned family : 4;
- unsigned type : 2;
- unsigned res : 2;
- unsigned ext_model : 4;
- unsigned ext_family : 8;
- unsigned res2 : 4;
- };
- } v;
- unsigned model;
+ unsigned eax;
if (!cpuid_vendor("GenuineIntel"))
return;
- arch_cpuid_1(1);
- model = (v.ext_model << 4) + v.model;
- if (v.family != 6 || model != 26 || v.stepping > 4)
+ eax = cpuid_signature();
+ if (cpu_family(eax) != 6 || cpu_model(eax) != 26
+ || cpu_stepping(eax) > 4)
return;
*ebx |= (1 << 2); /* disable unsupported event */
}
static inline unsigned arch_get_filter(op_cpu cpu_type)
{
- if (cpu_type == CPU_ARCH_PERFMON) {
+ if (op_cpu_base_type(cpu_type) == CPU_ARCH_PERFMON) {
unsigned ebx, eax;
#ifdef __PIC__
__asm__ __volatile__ (
@@ -111,7 +122,7 @@ static inline unsigned arch_get_filter(op_cpu cpu_type)
static inline int arch_num_counters(op_cpu cpu_type)
{
- if (cpu_type == CPU_ARCH_PERFMON) {
+ if (op_cpu_base_type(cpu_type) == CPU_ARCH_PERFMON) {
unsigned v = arch_cpuid_1(0xa);
return (v >> 8) & 0xff;
}
@@ -124,6 +135,30 @@ static inline unsigned arch_get_counter_mask(void)
return num_to_mask((v >> 8) & 0xff);
}
+static inline op_cpu op_cpu_specific_type(op_cpu cpu_type)
+{
+ if (cpu_type == CPU_ARCH_PERFMON) {
+ /* Already know is Intel family 6, so just check the model. */
+ int model = cpu_model(cpuid_signature());
+ switch(model) {
+ case 0x0f:
+ case 0x16:
+ case 0x17:
+ case 0x1d:
+ return CPU_CORE_2;
+ case 0x1a:
+ case 0x1e:
+ case 0x2e:
+ return CPU_CORE_I7;
+ case 0x1c:
+ return CPU_ATOM;
+ case 0x25:
+ return CPU_WESTMERE;
+ }
+ }
+ return cpu_type;
+}
+
#else
static inline unsigned arch_get_filter(op_cpu cpu_type)
@@ -147,4 +182,8 @@ static inline unsigned arch_get_counter_mask(void)
return 0;
}
+static inline op_cpu op_cpu_specific_type(op_cpu cpu_type)
+{
+ return cpu_type;
+}
#endif
diff --git a/libop/op_xml_events.c b/libop/op_xml_events.c
index 67fc0a5..1fcb01e 100644
--- a/libop/op_xml_events.c
+++ b/libop/op_xml_events.c
@@ -21,14 +21,15 @@ static char buffer[MAX_BUFFER];
void open_xml_events(char const * title, char const * doc, op_cpu the_cpu_type)
{
- char const * schema_version = "1.0";
+ char const * schema_version = "1.1";
buffer[0] = '\0';
cpu_type = the_cpu_type;
- open_xml_element(HELP_EVENTS, 0, buffer, MAX_BUFFER);
+ open_xml_element(HELP_EVENTS, 1, buffer, MAX_BUFFER);
+ init_xml_str_attr(SCHEMA_VERSION, schema_version, buffer, MAX_BUFFER);
+ close_xml_element(NONE, 1, buffer, MAX_BUFFER);
open_xml_element(HELP_HEADER, 1, buffer, MAX_BUFFER);
init_xml_str_attr(HELP_TITLE, title, buffer, MAX_BUFFER);
- init_xml_str_attr(SCHEMA_VERSION, schema_version, buffer, MAX_BUFFER);
init_xml_str_attr(HELP_DOC, doc, buffer, MAX_BUFFER);
close_xml_element(NONE, 0, buffer, MAX_BUFFER);
printf("%s", buffer);
@@ -76,10 +77,23 @@ void xml_help_for_event(struct op_event const * event)
buffer, MAX_BUFFER);
if (has_nested) {
+ char um_type[10];
close_xml_element(NONE, 1, buffer, MAX_BUFFER);
open_xml_element(HELP_UNIT_MASKS, 1, buffer, MAX_BUFFER);
init_xml_int_attr(HELP_DEFAULT_MASK, event->unit->default_mask,
buffer, MAX_BUFFER);
+ switch (event->unit->unit_type_mask){
+ case utm_bitmask:
+ strncpy(um_type, "bitmask", sizeof(um_type));
+ break;
+ case utm_exclusive:
+ strncpy(um_type, "exclusive", sizeof(um_type));
+ break;
+ case utm_mandatory:
+ strncpy(um_type, "mandatory", sizeof(um_type));
+ break;
+ }
+ init_xml_str_attr(HELP_UNIT_MASKS_CATEGORY, um_type, buffer, MAX_BUFFER);
close_xml_element(NONE, 1, buffer, MAX_BUFFER);
for (i = 0; i < event->unit->num; i++) {
open_xml_element(HELP_UNIT_MASK, 1, buffer, MAX_BUFFER);
diff --git a/libop/op_xml_out.c b/libop/op_xml_out.c
index b12919e..f6d9042 100644
--- a/libop/op_xml_out.c
+++ b/libop/op_xml_out.c
@@ -80,6 +80,7 @@ char const * xml_tag_map[] = {
"ext",
"unit_masks",
"default",
+ "category",
"unit_mask",
"mask",
"desc"
diff --git a/libop/op_xml_out.h b/libop/op_xml_out.h
index b0188b2..4fb06df 100644
--- a/libop/op_xml_out.h
+++ b/libop/op_xml_out.h
@@ -54,6 +54,7 @@ typedef enum {
HELP_EXT,
HELP_UNIT_MASKS,
HELP_DEFAULT_MASK,
+ HELP_UNIT_MASKS_CATEGORY,
HELP_UNIT_MASK,
HELP_UNIT_MASK_VALUE,
HELP_UNIT_MASK_DESC
diff --git a/libop/tests/Makefile.in b/libop/tests/Makefile.in
deleted file mode 100644
index 3755df4..0000000
--- a/libop/tests/Makefile.in
+++ /dev/null
@@ -1,601 +0,0 @@
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-# @configure_input@
-
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-# gives unlimited permission to copy and/or distribute it,
-# with or without modifications, as long as this notice is preserved.
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diff --git a/libop/tests/alloc_counter_tests.c b/libop/tests/alloc_counter_tests.c
index e2cdd04..5aeb605 100644
--- a/libop/tests/alloc_counter_tests.c
+++ b/libop/tests/alloc_counter_tests.c
@@ -108,10 +108,8 @@ static char const * const events_p4_2[] = {
static char const * const events_mips_34k[] = {
/* fail_to_alloc_counter: w/o 2006-8-03 Jeremiah Lott patch, see
* ChangeLog */
- "INSTRUCTIONS:500:0:1:1",
- "JR_31_INSN_EXECED:500:0:1:1",
- "BRANCH_INSNS_LAUNCHED:500:0:1:1",
- "L2_MISSES:500:0:1:1",
+ "DTLB_MISSES:500:0:1:1",
+ "JR_31_INSNS:500:0:1:1",
NULL
};
@@ -125,7 +123,7 @@ static struct allocated_counter const tests[] = {
{ CPU_PPRO, events_ppro_5, { 1, 0 }, no_failure },
{ CPU_P4, events_p4_1, { 3, 7, 0, 4, 2, 6, 1, 5 }, no_failure },
{ CPU_P4, events_p4_2, { -1 }, fail_to_alloc_counter },
- { CPU_MIPS_34K, events_mips_34k, { 1, 0, 2, 3 }, no_failure },
+ { CPU_MIPS_34K, events_mips_34k, { 1, 0 }, no_failure },
{ CPU_NO_GOOD, 0, { 0 }, 0 }
};