diff options
Diffstat (limited to 'events/mips/74K/events.h')
| -rw-r--r-- | events/mips/74K/events.h | 247 |
1 files changed, 247 insertions, 0 deletions
diff --git a/events/mips/74K/events.h b/events/mips/74K/events.h new file mode 100644 index 0000000..ef3a6df --- /dev/null +++ b/events/mips/74K/events.h @@ -0,0 +1,247 @@ +// events from file events/mips/74K/events + {0x0, CTR(0) | CTR(1) | CTR(2) | CTR(3), 0, "CYCLES", + "0-0 Cycles"}, + {0x1, CTR(0) | CTR(1) | CTR(2) | CTR(3), 0, "INSTRUCTIONS", + "1-0 Instructions graduated"}, + {0x2, CTR(0) | CTR(2), 0, "PREDICTED_JR_31", + "2-0 JR $31 (return) instructions predicted including speculative instructions"}, + {0x3, CTR(0) | CTR(2), 0, "REDIRECT_STALLS", + "3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception"}, + {0x4, CTR(0) | CTR(2), 0, "ITLB_ACCESSES", + "4-0 Instruction micro-TLB accesses"}, + {0x6, CTR(0) | CTR(2), 0, "ICACHE_ACCESSES", + "6-0 Instruction cache accesses including speculative instructions"}, + {0x7, CTR(0) | CTR(2), 0, "ICACHE_MISS_STALLS", + "7-0 Instruction cache miss stall cycles"}, + {0x8, CTR(0) | CTR(2), 0, "UNCACHED_IFETCH_STALLS", + "8-0 Uncached instruction fetch stall cycles"}, + {0x9, CTR(0) | CTR(2), 0, "IFU_REPLAYS", + "9-0 Replays within the IFU due to full Instruction Buffer"}, + {0xb, CTR(0) | CTR(2), 0, "IFU_IDU_MISS_PRED_UPSTREAM_CYCLES", + "11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch"}, + {0xc, CTR(0) | CTR(2), 0, "IFU_IDU_CLOGED_DOWNSTREAM_CYCLES", + "12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS"}, + {0xd, CTR(0) | CTR(2), 0, "DDQ0_FULL_DR_STALLS", + "13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full"}, + {0xe, CTR(0) | CTR(2), 0, "ALCB_FULL_DR_STALLS", + "14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full"}, + {0xf, CTR(0) | CTR(2), 0, "CLDQ_FULL_DR_STALLS", + "15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full"}, + {0x10, CTR(0) | CTR(2), 0, "ALU_EMPTY_CYCLES", + "16-0 DDQ0 (ALU out-of-order dispatch queue) empty cycles"}, + {0x11, CTR(0) | CTR(2), 0, "ALU_OPERANDS_NOT_READY_CYCLES", + "17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready"}, + {0x12, CTR(0) | CTR(2), 0, "ALU_NO_ISSUES_CYCLES", + "18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy"}, + {0x13, CTR(0) | CTR(2), 0, "ALU_BUBBLE_CYCLES", + "19-0 DDQ0 (ALU out-of-order dispatch queue) bubbles due to MFC1 data write"}, + {0x14, CTR(0) | CTR(2), 0, "SINGLE_ISSUE_CYCLES", + "20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles"}, + {0x15, CTR(0) | CTR(2), 0, "OOO_ALU_ISSUE_CYCLES", + "21-0 Out-of-order ALU issue cycles (issued instruction is not the oldest in the pool)"}, + {0x16, CTR(0) | CTR(2), 0, "JALR_JALR_HB_INSNS", + "22-0 Graduated JALR/JALR.HB instructions"}, + {0x17, CTR(0) | CTR(2), 0, "DCACHE_LOAD_ACCESSES", + "23-0 Counts all accesses to the data cache caused by load instructions"}, + {0x18, CTR(0) | CTR(2), 0, "DCACHE_WRITEBACKS", + "24-0 Data cache writebacks"}, + {0x19, CTR(0) | CTR(2), 0, "JTLB_DATA_ACCESSES", + "25-0 Joint TLB data (non-instruction) accesses"}, + {0x1a, CTR(0) | CTR(2), 0, "LOAD_STORE_REPLAYS", + "26-0 Load/store generated replays - load/store follows too closely a matching CACHEOP"}, + {0x1b, CTR(0) | CTR(2), 0, "LOAD_STORE_BLOCKED_CYCLES", + "27-0 Load/store graduation blocked cycles due to CP1/2 store data not ready, SYNC/SYNCI/SC/CACHEOP at the head, or FSB/LDQ/WBB/ITU FIFO full"}, + {0x1c, CTR(0) | CTR(2), 0, "L2_CACHE_WRITEBACKS", + "28-0 L2 Cache Writebacks"}, + {0x1d, CTR(0) | CTR(2), 0, "L2_CACHE_MISSES", + "29-0 L2 Cache Misses"}, + {0x1e, CTR(0) | CTR(2), 0, "FSB_FULL_STALLS", + "30-0 Pipe stall cycles due to FSB full"}, + {0x1f, CTR(0) | CTR(2), 0, "LDQ_FULL_STALLS", + "31-0 Pipe stall cycles due to LDQ full"}, + {0x20, CTR(0) | CTR(2), 0, "WBB_FULL_STALLS", + "32-0 Pipe stall cycles due to WBB full"}, + {0x23, CTR(0) | CTR(2), 0, "LOAD_MISS_CONSUMER_REPLAYS", + "35-0 Replays following optimistic issue of instruction dependent on load which missed, counted only when the dependent instruction graduates"}, + {0x24, CTR(0) | CTR(2), 0, "JR_NON_31_INSNS", + "36-0 jr $xx (not $31) instructions graduated (at same cost as a mispredict)"}, + {0x25, CTR(0) | CTR(2), 0, "BRANCH_INSNS", + "37-0 Branch instructions graduated, excluding CP1/CP2 conditional branches"}, + {0x26, CTR(0) | CTR(2), 0, "BRANCH_LIKELY_INSNS", + "38-0 Branch likely instructions graduated including CP1 and CP2 branch likely instructions"}, + {0x27, CTR(0) | CTR(2), 0, "COND_BRANCH_INSNS", + "39-0 Conditional branches graduated"}, + {0x28, CTR(0) | CTR(2), 0, "INTEGER_INSNS", + "40-0 Integer instructions graduated including NOP, SSNOP, MOVCI, and EHB"}, + {0x29, CTR(0) | CTR(2), 0, "LOAD_INSNS", + "41-0 Loads graduated including CP1 ans CP2 loads"}, + {0x2a, CTR(0) | CTR(2), 0, "J_JAL_INSNS", + "42-0 J/JAL graduated"}, + {0x2b, CTR(0) | CTR(2), 0, "NOP_INSNS", + "43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB"}, + {0x2c, CTR(0) | CTR(2), 0, "DSP_INSNS", + "44-0 DSP instructions graduated"}, + {0x2d, CTR(0) | CTR(2), 0, "DSP_BRANCH_INSNS", + "45-0 DSP branch instructions graduated"}, + {0x2e, CTR(0) | CTR(2), 0, "UNCACHED_LOAD_INSNS", + "46-0 Uncached loads graduated"}, + {0x31, CTR(0) | CTR(2), 0, "EJTAG_INSN_TRIGGERS", + "49-0 EJTAG instruction triggerpoints"}, + {0x32, CTR(0) | CTR(2), 0, "CP1_BRANCH_MISPREDICTIONS", + "50-0 CP1 branches mispredicted"}, + {0x33, CTR(0) | CTR(2), 0, "SC_INSNS", + "51-0 SC instructions graduated"}, + {0x34, CTR(0) | CTR(2), 0, "PREFETCH_INSNS", + "52-0 Prefetch instructions graduated"}, + {0x35, CTR(0) | CTR(2), 0, "NO_INSN_CYCLES", + "53-0 No instructions graduated cycles"}, + {0x36, CTR(0) | CTR(2), 0, "ONE_INSN_CYCLES", + "54-0 One instruction graduated cycles"}, + {0x37, CTR(0) | CTR(2), 0, "GFIFO_BLOCKED_CYCLES", + "55-0 GFIFO blocked cycles"}, + {0x38, CTR(0) | CTR(2), 0, "MISPREDICTION_STALLS", + "56-0 Cycles from the time of a pipe kill due to mispredict until the first new instruction graduates"}, + {0x39, CTR(0) | CTR(2), 0, "MISPREDICTED_BRANCH_INSNS_CYCLES", + "57-0 Mispredicted branch instruction graduation cycles without the delay slot"}, + {0x3a, CTR(0) | CTR(2), 0, "EXCEPTIONS_TAKEN", + "58-0 Exceptions taken"}, + {0x3b, CTR(0) | CTR(2), 0, "COREEXTEND_EVENTS", + "59-0 Implementation specific CorExtend events"}, + {0x3e, CTR(0) | CTR(2), 0, "ISPRAM_EVENTS", + "62-0 Implementation specific ISPRAM events"}, + {0x3f, CTR(0) | CTR(2), 0, "L2_CACHE_SINGLE_BIT_ERRORS", + "63-0 Single bit errors corrected in L2"}, + {0x40, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_0", + "64-0 Implementation specific system event 0"}, + {0x41, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_2", + "65-0 Implementation specific system event 2"}, + {0x42, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_4", + "66-0 Implementation specific system event 4"}, + {0x43, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_6", + "67-0 Implementation specific system event 6"}, + {0x44, CTR(0) | CTR(2), 0, "OCP_ALL_REQUESTS", + "68-0 All OCP requests accepted"}, + {0x45, CTR(0) | CTR(2), 0, "OCP_READ_REQUESTS", + "69-0 OCP read requests accepted"}, + {0x46, CTR(0) | CTR(2), 0, "OCP_WRITE_REQUESTS", + "70-0 OCP write requests accepted"}, + {0x4a, CTR(0) | CTR(2), 0, "FSB_LESS_25_FULL", + "74-0 FSB < 25% full"}, + {0x4b, CTR(0) | CTR(2), 0, "LDQ_LESS_25_FULL", + "75-0 LDQ < 25% full"}, + {0x4c, CTR(0) | CTR(2), 0, "WBB_LESS_25_FULL", + "76-0 WBB < 25% full"}, + {0x402, CTR(1) | CTR(3), 0, "JR_31_MISPREDICTIONS", + "2-1 JR $31 (return) instructions mispredicted"}, + {0x403, CTR(1) | CTR(3), 0, "JR_31_NO_PREDICTIONS", + "3-1 JR $31 (return) instructions not predicted"}, + {0x404, CTR(1) | CTR(3), 0, "ITLB_MISSES", + "4-1 Instruction micro-TLB misses"}, + {0x405, CTR(1) | CTR(3), 0, "JTLB_INSN_MISSES", + "5-1 Joint TLB instruction misses"}, + {0x406, CTR(1) | CTR(3), 0, "ICACHE_MISSES", + "6-1 Instruction cache misses, includes misses from fetch-ahead and speculation"}, + {0x408, CTR(1) | CTR(3), 0, "PDTRACE_BACK_STALLS", + "8-1 PDtrace back stalls"}, + {0x409, CTR(1) | CTR(3), 0, "KILLED_FETCH_SLOTS", + "9-1 Valid fetch slots killed due to taken branches/jumps or stalling instructions"}, + {0x40b, CTR(1) | CTR(3), 0, "IFU_IDU_NO_FETCH_CYCLES", + "11-1 Cycles IFU-IDU gate open but no instructions fetched by IFU"}, + {0x40d, CTR(1) | CTR(3), 0, "DDQ1_FULL_DR_STALLS", + "13-1 DR stage stall cycles due to DDQ1 (AGEN out-of-order dispatch queue) full"}, + {0x40e, CTR(1) | CTR(3), 0, "AGCB_FULL_DR_STALLS", + "14-1 DR stage stall cycles due to AGCB (AGEN completion buffers) full"}, + {0x40f, CTR(1) | CTR(3), 0, "IODQ_FULL_DR_STALLS", + "15-1 DR stage stall cycles due to IODQ (data comming back from IO) full"}, + {0x410, CTR(1) | CTR(3), 0, "AGEN_EMPTY_CYCLES", + "16-1 DDQ1 (AGEN out-of-order dispatch queue) empty cycles"}, + {0x411, CTR(1) | CTR(3), 0, "AGEN_OPERANDS_NOT_READY_CYCLES", + "17-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready"}, + {0x412, CTR(1) | CTR(3), 0, "AGEN_NO_ISSUES_CYCLES", + "18-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, non-issued stores blocking ready to issue loads, or non-issued CACHEOPs blocking ready to issue loads"}, + {0x413, CTR(1) | CTR(3), 0, "AGEN_BUBBLE_CYCLES", + "19-1 DDQ1 (AGEN out-of-order dispatch queue) bubbles due to MFC2 data write or cache access from FSB"}, + {0x414, CTR(1) | CTR(3), 0, "DUAL_ISSUE_CYCLES", + "20-1 Both DDQ0 (ALU out-of-order dispatch queue) and DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles"}, + {0x415, CTR(1) | CTR(3), 0, "OOO_AGEN_ISSUE_CYCLES", + "21-1 Out-of-order AGEN issue cycles (issued instruction is not the oldest in the pool)"}, + {0x416, CTR(1) | CTR(3), 0, "DCACHE_LINE_REFILL_REQUESTS", + "22-1 Data cache line loads (line refill requests)"}, + {0x417, CTR(1) | CTR(3), 0, "DCACHE_ACCESSES", + "23-1 Data cache accesses"}, + {0x418, CTR(1) | CTR(3), 0, "DCACHE_MISSES", + "24-1 Data cache misses"}, + {0x419, CTR(1) | CTR(3), 0, "JTLB_DATA_MISSES", + "25-1 Joint TLB data (non-instruction) misses"}, + {0x41a, CTR(1) | CTR(3), 0, "VA_TRANSALTION_CORNER_CASES", + "26-1 Virtual memory address translation synonyms, homonyms, and aliases (loads/stores treated as miss in the cache)"}, + {0x41b, CTR(1) | CTR(3), 0, "LOAD_STORE_NO_FILL_REQUESTS", + "27-1 Load/store graduations not resulting in a bus request because misses at integer pipe graduation turn into hit or merge with outstanding fill request"}, + {0x41c, CTR(1) | CTR(3), 0, "L2_CACHE_ACCESSES", + "28-1 Accesses to the L2 cache"}, + {0x41d, CTR(1) | CTR(3), 0, "L2_CACHE_MISS_CYCLES", + "29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline"}, + {0x41e, CTR(1) | CTR(3), 0, "FSB_OVER_50_FULL", + "30-1 FSB > 50% full"}, + {0x41f, CTR(1) | CTR(3), 0, "LDQ_OVER_50_FULL", + "31-1 LDQ > 50% full"}, + {0x420, CTR(1) | CTR(3), 0, "WBB_OVER_50_FULL", + "32-1 WBB > 50% full"}, + {0x423, CTR(1) | CTR(3), 0, "CP1_CP2_LOAD_INSNS", + "35-1 CP1/CP2 load instructions graduated"}, + {0x424, CTR(1) | CTR(3), 0, "MISPREDICTED_JR_31_INSNS", + "36-1 jr $31 instructions graduated after mispredict"}, + {0x425, CTR(1) | CTR(3), 0, "CP1_CP2_COND_BRANCH_INSNS", + "37-1 CP1/CP2 conditional branch instructions graduated"}, + {0x426, CTR(1) | CTR(3), 0, "MISPREDICTED_BRANCH_LIKELY_INSNS", + "38-1 Mispredicted branch likely instructions graduated"}, + {0x427, CTR(1) | CTR(3), 0, "MISPREDICTED_BRANCH_INSNS", + "39-1 Mispredicted branches graduated"}, + {0x428, CTR(1) | CTR(3), 0, "FPU_INSNS", + "40-1 FPU instructions graduated"}, + {0x429, CTR(1) | CTR(3), 0, "STORE_INSNS", + "41-1 Store instructions graduated including CP1 ans CP2 stores"}, + {0x42a, CTR(1) | CTR(3), 0, "MIPS16_INSNS", + "42-1 MIPS16 instructions graduated"}, + {0x42b, CTR(1) | CTR(3), 0, "NT_MUL_DIV_INSNS", + "43-1 Integer multiply/divide instructions graduated"}, + {0x42c, CTR(1) | CTR(3), 0, "ALU_DSP_SATURATION_INSNS", + "44-1 ALU-DSP graduated, result was saturated"}, + {0x42d, CTR(1) | CTR(3), 0, "MDU_DSP_SATURATION_INSNS", + "45-1 MDU-DSP graduated, result was saturated"}, + {0x42e, CTR(1) | CTR(3), 0, "UNCACHED_STORE_INSNS", + "46-1 Uncached stores graduated"}, + {0x433, CTR(1) | CTR(3), 0, "FAILED_SC_INSNS", + "51-1 SC instructions failed"}, + {0x434, CTR(1) | CTR(3), 0, "CACHE_HIT_PREFETCH_INSNS", + "52-1 PREFETCH instructions which did nothing, because they hit in the cache"}, + {0x435, CTR(1) | CTR(3), 0, "LOAD_MISS_INSNS", + "53-1 Cacheable load instructions that miss in the cache graduated"}, + {0x436, CTR(1) | CTR(3), 0, "TWO_INSNS_CYCLES", + "54-1 Two instructions graduated cycles"}, + {0x437, CTR(1) | CTR(3), 0, "CP1_CP2_STORE_INSNS", + "55-1 CP1/CP2 Store graduated"}, + {0x43a, CTR(1) | CTR(3), 0, "GRADUATION_REPLAYS", + "58-1 Replays initiated from graduation"}, + {0x43e, CTR(1) | CTR(3), 0, "DSPRAM_EVENTS", + "62-1 Implementation specific events from the DSPRAM block"}, + {0x440, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_1", + "64-1 Implementation specific system event 1"}, + {0x441, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_3", + "65-1 Implementation specific system event 3"}, + {0x442, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_5", + "66-1 Implementation specific system event 5"}, + {0x443, CTR(0) | CTR(2), 0, "SYSTEM_EVENT_7", + "67-1 Implementation specific system event 7"}, + {0x444, CTR(0) | CTR(2), 0, "OCP_ALL_CACHEABLE_REQUESTS", + "68-1 All OCP cacheable requests accepted"}, + {0x445, CTR(0) | CTR(2), 0, "OCP_READ_CACHEABLE_REQUESTS", + "69-1 OCP cacheable read request accepted"}, + {0x446, CTR(0) | CTR(2), 0, "OCP_WRITE_CACHEABLE_REQUESTS", + "70-1 OCP cacheable write request accepted"}, + {0x44a, CTR(0) | CTR(2), 0, "FSB_25_50_FULL", + "74-1 FSB 25-50% full"}, + {0x44b, CTR(0) | CTR(2), 0, "LDQ_25_50_FULL", + "75-1 LDQ 25-50% full"}, + {0x44c, CTR(0) | CTR(2), 0, "WBB_25_50_FULL", + "76-1 WBB 25-50% full"}, |