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-rw-r--r--events/Makefile.am9
-rw-r--r--events/Makefile.in450
-rw-r--r--events/alpha/ev4/events18
-rw-r--r--events/alpha/ev4/unit_masks4
-rw-r--r--events/alpha/ev5/events49
-rw-r--r--events/alpha/ev5/unit_masks4
-rw-r--r--events/alpha/ev6/events11
-rw-r--r--events/alpha/ev6/unit_masks4
-rw-r--r--events/alpha/ev67/events27
-rw-r--r--events/alpha/ev67/unit_masks4
-rw-r--r--events/alpha/pca56/events2
-rw-r--r--events/alpha/pca56/unit_masks3
-rw-r--r--events/arm/armv7-ca9/events50
-rw-r--r--events/arm/armv7-ca9/unit_masks4
-rw-r--r--events/arm/armv7-common/events22
-rw-r--r--events/arm/armv7-common/unit_masks4
-rw-r--r--events/arm/armv7/events21
-rw-r--r--events/avr32/events27
-rw-r--r--events/avr32/unit_masks4
-rw-r--r--events/i386/arch_perfmon/events10
-rw-r--r--events/i386/arch_perfmon/unit_masks11
-rw-r--r--events/i386/athlon/events27
-rw-r--r--events/i386/athlon/unit_masks11
-rw-r--r--events/i386/atom/events80
-rw-r--r--events/i386/atom/unit_masks120
-rw-r--r--events/i386/core/events115
-rw-r--r--events/i386/core/unit_masks67
-rw-r--r--events/i386/core_2/events137
-rw-r--r--events/i386/core_2/unit_masks195
-rw-r--r--events/i386/core_i7/events6
-rw-r--r--events/i386/core_i7/unit_masks1
-rw-r--r--events/i386/nehalem/events107
-rw-r--r--events/i386/nehalem/unit_masks372
-rw-r--r--events/i386/p4-ht/events25
-rw-r--r--events/i386/p4-ht/unit_masks79
-rw-r--r--events/i386/p4/events44
-rw-r--r--events/i386/p4/unit_masks127
-rw-r--r--events/i386/p6_mobile/events115
-rw-r--r--events/i386/p6_mobile/unit_masks47
-rw-r--r--events/i386/pii/events80
-rw-r--r--events/i386/pii/unit_masks34
-rw-r--r--events/i386/piii/events80
-rw-r--r--events/i386/piii/unit_masks36
-rw-r--r--events/i386/ppro/events70
-rw-r--r--events/i386/ppro/unit_masks13
-rw-r--r--events/i386/westmere/events88
-rw-r--r--events/i386/westmere/unit_masks307
-rw-r--r--events/ia64/ia64/events3
-rw-r--r--events/ia64/ia64/unit_masks4
-rw-r--r--events/ia64/itanium/events5
-rw-r--r--events/ia64/itanium/unit_masks4
-rw-r--r--events/ia64/itanium2/events267
-rw-r--r--events/ia64/itanium2/unit_masks465
-rw-r--r--events/mips/1004K/events173
-rw-r--r--events/mips/1004K/unit_masks5
-rw-r--r--events/mips/20K/events21
-rw-r--r--events/mips/20K/unit_masks5
-rw-r--r--events/mips/24K/events144
-rw-r--r--events/mips/24K/unit_masks5
-rw-r--r--events/mips/25K/events81
-rw-r--r--events/mips/25K/unit_masks5
-rw-r--r--events/mips/34K/events158
-rw-r--r--events/mips/34K/unit_masks5
-rw-r--r--events/mips/5K/events36
-rw-r--r--events/mips/5K/unit_masks5
-rw-r--r--events/mips/74K/events159
-rw-r--r--events/mips/74K/unit_masks5
-rw-r--r--events/mips/loongson2/events34
-rw-r--r--events/mips/loongson2/unit_masks4
-rw-r--r--events/mips/r10000/events36
-rw-r--r--events/mips/r10000/unit_masks5
-rw-r--r--events/mips/r12000/events35
-rw-r--r--events/mips/r12000/unit_masks7
-rw-r--r--events/mips/rm7000/events34
-rw-r--r--events/mips/rm7000/unit_masks5
-rw-r--r--events/mips/rm9000/events32
-rw-r--r--events/mips/rm9000/unit_masks5
-rw-r--r--events/mips/sb1/events73
-rw-r--r--events/mips/sb1/unit_masks5
-rw-r--r--events/mips/vr5432/events14
-rw-r--r--events/mips/vr5432/unit_masks5
-rw-r--r--events/mips/vr5500/events16
-rw-r--r--events/mips/vr5500/unit_masks5
-rw-r--r--events/ppc/7450/events39
-rw-r--r--events/ppc/7450/unit_masks4
-rw-r--r--events/ppc/e300/events40
-rw-r--r--events/ppc/e300/unit_masks4
-rw-r--r--events/ppc/e500/events83
-rw-r--r--events/ppc/e500/unit_masks4
-rw-r--r--events/ppc/e500v2/events83
-rw-r--r--events/ppc/e500v2/unit_masks4
-rw-r--r--events/ppc64/970/event_mappings494
-rw-r--r--events/ppc64/970/events505
-rw-r--r--events/ppc64/970/unit_masks4
-rw-r--r--events/ppc64/970MP/event_mappings519
-rw-r--r--events/ppc64/970MP/events530
-rw-r--r--events/ppc64/970MP/unit_masks9
-rw-r--r--events/ppc64/cell-be/events517
-rw-r--r--events/ppc64/cell-be/unit_masks137
-rw-r--r--events/ppc64/ibm-compat-v1/event_mappings82
-rw-r--r--events/ppc64/ibm-compat-v1/events91
-rw-r--r--events/ppc64/ibm-compat-v1/unit_masks9
-rw-r--r--events/ppc64/pa6t/event_mappings48
-rw-r--r--events/ppc64/pa6t/events52
-rw-r--r--events/ppc64/pa6t/unit_masks4
-rw-r--r--events/ppc64/power4/event_mappings634
-rw-r--r--events/ppc64/power4/events645
-rw-r--r--events/ppc64/power4/unit_masks5
-rw-r--r--events/ppc64/power5++/event_mappings1140
-rw-r--r--events/ppc64/power5++/events1151
-rw-r--r--events/ppc64/power5++/unit_masks4
-rw-r--r--events/ppc64/power5+/event_mappings1232
-rw-r--r--events/ppc64/power5+/events1242
-rw-r--r--events/ppc64/power5+/unit_masks4
-rw-r--r--events/ppc64/power5/event_mappings1192
-rw-r--r--events/ppc64/power5/events1202
-rw-r--r--events/ppc64/power5/unit_masks4
-rw-r--r--events/ppc64/power6/event_mappings1201
-rw-r--r--events/ppc64/power6/events1211
-rw-r--r--events/ppc64/power6/unit_masks9
-rw-r--r--events/ppc64/power7/event_mappings2020
-rw-r--r--events/ppc64/power7/events2027
-rw-r--r--events/ppc64/power7/unit_masks9
-rw-r--r--events/rtc/events3
-rw-r--r--events/rtc/unit_masks4
-rw-r--r--events/x86-64/family10/events241
-rw-r--r--events/x86-64/family10/unit_masks374
-rw-r--r--events/x86-64/family11h/events132
-rw-r--r--events/x86-64/family11h/unit_masks220
-rw-r--r--events/x86-64/family12h/events23
-rw-r--r--events/x86-64/family12h/unit_masks30
-rw-r--r--events/x86-64/family14h/events23
-rw-r--r--events/x86-64/family14h/unit_masks30
-rw-r--r--events/x86-64/family15h/events16
-rw-r--r--events/x86-64/family15h/unit_masks16
-rw-r--r--events/x86-64/hammer/events125
-rw-r--r--events/x86-64/hammer/unit_masks186
137 files changed, 24138 insertions, 470 deletions
diff --git a/events/Makefile.am b/events/Makefile.am
index aaaacb7..475c4d3 100644
--- a/events/Makefile.am
+++ b/events/Makefile.am
@@ -17,6 +17,7 @@ event_files = \
i386/atom/events i386/atom/unit_masks \
i386/core_i7/events i386/core_i7/unit_masks \
i386/nehalem/events i386/nehalem/unit_masks \
+ i386/westmere/events i386/westmere/unit_masks \
ia64/ia64/events ia64/ia64/unit_masks \
ia64/itanium2/events ia64/itanium2/unit_masks \
ia64/itanium/events ia64/itanium/unit_masks \
@@ -35,10 +36,15 @@ event_files = \
x86-64/hammer/events x86-64/hammer/unit_masks \
x86-64/family10/events x86-64/family10/unit_masks \
x86-64/family11h/events x86-64/family11h/unit_masks \
+ x86-64/family12h/events x86-64/family12h/unit_masks \
+ x86-64/family14h/events x86-64/family14h/unit_masks \
+ x86-64/family15h/events x86-64/family15h/unit_masks \
arm/xscale1/events arm/xscale1/unit_masks \
arm/xscale2/events arm/xscale2/unit_masks \
arm/armv6/events arm/armv6/unit_masks \
+ arm/armv7-common/events arm/armv7-common/unit_masks \
arm/armv7/events arm/armv7/unit_masks \
+ arm/armv7-ca9/events arm/armv7-ca9/unit_masks \
arm/mpcore/events arm/mpcore/unit_masks \
avr32/events avr32/unit_masks \
mips/20K/events mips/20K/unit_masks \
@@ -53,6 +59,9 @@ event_files = \
mips/r12000/events mips/r12000/unit_masks \
mips/vr5432/events mips/vr5432/unit_masks \
mips/vr5500/events mips/vr5500/unit_masks \
+ mips/loongson2/events mips/loongson2/unit_masks \
+ mips/1004K/events mips/1004K/unit_masks \
+ mips/74K/events mips/74K/unit_masks \
ppc/7450/events ppc/7450/unit_masks \
ppc/e500/events ppc/e500/unit_masks \
ppc/e500v2/events ppc/e500v2/unit_masks \
diff --git a/events/Makefile.in b/events/Makefile.in
deleted file mode 100644
index ce7c3b3..0000000
--- a/events/Makefile.in
+++ /dev/null
@@ -1,450 +0,0 @@
-# Makefile.in generated by automake 1.9.6 from Makefile.am.
-# @configure_input@
-
-# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
-# 2003, 2004, 2005 Free Software Foundation, Inc.
-# This Makefile.in is free software; the Free Software Foundation
-# gives unlimited permission to copy and/or distribute it,
-# with or without modifications, as long as this notice is preserved.
-
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY, to the extent permitted by law; without
-# even the implied warranty of MERCHANTABILITY or FITNESS FOR A
-# PARTICULAR PURPOSE.
-
-@SET_MAKE@
-srcdir = @srcdir@
-top_srcdir = @top_srcdir@
-VPATH = @srcdir@
-pkgdatadir = $(datadir)/@PACKAGE@
-pkglibdir = $(libdir)/@PACKAGE@
-pkgincludedir = $(includedir)/@PACKAGE@
-top_builddir = ..
-am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd
-INSTALL = @INSTALL@
-install_sh_DATA = $(install_sh) -c -m 644
-install_sh_PROGRAM = $(install_sh) -c
-install_sh_SCRIPT = $(install_sh) -c
-INSTALL_HEADER = $(INSTALL_DATA)
-transform = $(program_transform_name)
-NORMAL_INSTALL = :
-PRE_INSTALL = :
-POST_INSTALL = :
-NORMAL_UNINSTALL = :
-PRE_UNINSTALL = :
-POST_UNINSTALL = :
-build_triplet = @build@
-host_triplet = @host@
-subdir = events
-DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in
-ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
-am__aclocal_m4_deps = $(top_srcdir)/m4/binutils.m4 \
- $(top_srcdir)/m4/builtinexpect.m4 \
- $(top_srcdir)/m4/cellspubfdsupport.m4 \
- $(top_srcdir)/m4/compileroption.m4 \
- $(top_srcdir)/m4/configmodule.m4 \
- $(top_srcdir)/m4/copyifchange.m4 $(top_srcdir)/m4/docbook.m4 \
- $(top_srcdir)/m4/extradirs.m4 $(top_srcdir)/m4/findkernel.m4 \
- $(top_srcdir)/m4/kerneloption.m4 \
- $(top_srcdir)/m4/kernelversion.m4 \
- $(top_srcdir)/m4/mallocattribute.m4 \
- $(top_srcdir)/m4/poptconst.m4 \
- $(top_srcdir)/m4/precompiledheader.m4 $(top_srcdir)/m4/qt.m4 \
- $(top_srcdir)/m4/resultyn.m4 $(top_srcdir)/m4/sstream.m4 \
- $(top_srcdir)/m4/typedef.m4 $(top_srcdir)/configure.in
-am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
- $(ACLOCAL_M4)
-mkinstalldirs = $(install_sh) -d
-CONFIG_HEADER = $(top_builddir)/config.h
-CONFIG_CLEAN_FILES =
-SOURCES =
-DIST_SOURCES =
-DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST)
-ACLOCAL = @ACLOCAL@
-AMDEP_FALSE = @AMDEP_FALSE@
-AMDEP_TRUE = @AMDEP_TRUE@
-AMTAR = @AMTAR@
-AR = @AR@
-AUTOCONF = @AUTOCONF@
-AUTOHEADER = @AUTOHEADER@
-AUTOMAKE = @AUTOMAKE@
-AWK = @AWK@
-BFD_LIBS = @BFD_LIBS@
-BUILD_JVMPI_AGENT_FALSE = @BUILD_JVMPI_AGENT_FALSE@
-BUILD_JVMPI_AGENT_TRUE = @BUILD_JVMPI_AGENT_TRUE@
-BUILD_JVMTI_AGENT_FALSE = @BUILD_JVMTI_AGENT_FALSE@
-BUILD_JVMTI_AGENT_TRUE = @BUILD_JVMTI_AGENT_TRUE@
-CAT_ENTRY_END = @CAT_ENTRY_END@
-CAT_ENTRY_START = @CAT_ENTRY_START@
-CC = @CC@
-CCDEPMODE = @CCDEPMODE@
-CFLAGS = @CFLAGS@
-CPP = @CPP@
-CPPFLAGS = @CPPFLAGS@
-CXX = @CXX@
-CXXCPP = @CXXCPP@
-CXXDEPMODE = @CXXDEPMODE@
-CXXFLAGS = @CXXFLAGS@
-CYGPATH_W = @CYGPATH_W@
-DATE = @DATE@
-DEFS = @DEFS@
-DEPDIR = @DEPDIR@
-DOCBOOK_ROOT = @DOCBOOK_ROOT@
-ECHO = @ECHO@
-ECHO_C = @ECHO_C@
-ECHO_N = @ECHO_N@
-ECHO_T = @ECHO_T@
-EGREP = @EGREP@
-EXEEXT = @EXEEXT@
-EXTRA_CFLAGS_MODULE = @EXTRA_CFLAGS_MODULE@
-F77 = @F77@
-FFLAGS = @FFLAGS@
-INSTALL_DATA = @INSTALL_DATA@
-INSTALL_PROGRAM = @INSTALL_PROGRAM@
-INSTALL_SCRIPT = @INSTALL_SCRIPT@
-INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@
-JAVA_HOMEDIR = @JAVA_HOMEDIR@
-KINC = @KINC@
-KSRC = @KSRC@
-KVERS = @KVERS@
-LD = @LD@
-LDFLAGS = @LDFLAGS@
-LIBERTY_LIBS = @LIBERTY_LIBS@
-LIBOBJS = @LIBOBJS@
-LIBS = @LIBS@
-LIBTOOL = @LIBTOOL@
-LN_S = @LN_S@
-LTLIBOBJS = @LTLIBOBJS@
-MAKEINFO = @MAKEINFO@
-MOC = @MOC@
-MODINSTALLDIR = @MODINSTALLDIR@
-OBJEXT = @OBJEXT@
-OPROFILE_DIR = @OPROFILE_DIR@
-OPROFILE_MODULE_ARCH = @OPROFILE_MODULE_ARCH@
-OP_CFLAGS = @OP_CFLAGS@
-OP_CXXFLAGS = @OP_CXXFLAGS@
-OP_DOCDIR = @OP_DOCDIR@
-PACKAGE = @PACKAGE@
-PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@
-PACKAGE_NAME = @PACKAGE_NAME@
-PACKAGE_STRING = @PACKAGE_STRING@
-PACKAGE_TARNAME = @PACKAGE_TARNAME@
-PACKAGE_VERSION = @PACKAGE_VERSION@
-PATH_SEPARATOR = @PATH_SEPARATOR@
-POPT_LIBS = @POPT_LIBS@
-PTRDIFF_T_TYPE = @PTRDIFF_T_TYPE@
-QT_INCLUDES = @QT_INCLUDES@
-QT_LDFLAGS = @QT_LDFLAGS@
-QT_LIB = @QT_LIB@
-QT_VERSION = @QT_VERSION@
-RANLIB = @RANLIB@
-SET_MAKE = @SET_MAKE@
-SHELL = @SHELL@
-SIZE_T_TYPE = @SIZE_T_TYPE@
-STRIP = @STRIP@
-UIC = @UIC@
-VERSION = @VERSION@
-XML_CATALOG = @XML_CATALOG@
-XSLTPROC = @XSLTPROC@
-XSLTPROC_FLAGS = @XSLTPROC_FLAGS@
-X_CFLAGS = @X_CFLAGS@
-X_EXTRA_LIBS = @X_EXTRA_LIBS@
-X_LIBS = @X_LIBS@
-X_PRE_LIBS = @X_PRE_LIBS@
-ac_ct_AR = @ac_ct_AR@
-ac_ct_CC = @ac_ct_CC@
-ac_ct_CXX = @ac_ct_CXX@
-ac_ct_F77 = @ac_ct_F77@
-ac_ct_RANLIB = @ac_ct_RANLIB@
-ac_ct_STRIP = @ac_ct_STRIP@
-am__fastdepCC_FALSE = @am__fastdepCC_FALSE@
-am__fastdepCC_TRUE = @am__fastdepCC_TRUE@
-am__fastdepCXX_FALSE = @am__fastdepCXX_FALSE@
-am__fastdepCXX_TRUE = @am__fastdepCXX_TRUE@
-am__include = @am__include@
-am__leading_dot = @am__leading_dot@
-am__quote = @am__quote@
-am__tar = @am__tar@
-am__untar = @am__untar@
-bindir = @bindir@
-build = @build@
-build_alias = @build_alias@
-build_cpu = @build_cpu@
-build_os = @build_os@
-build_vendor = @build_vendor@
-datadir = @datadir@
-exec_prefix = @exec_prefix@
-have_qt_FALSE = @have_qt_FALSE@
-have_qt_TRUE = @have_qt_TRUE@
-have_xsltproc_FALSE = @have_xsltproc_FALSE@
-have_xsltproc_TRUE = @have_xsltproc_TRUE@
-host = @host@
-host_alias = @host_alias@
-host_cpu = @host_cpu@
-host_os = @host_os@
-host_vendor = @host_vendor@
-includedir = @includedir@
-infodir = @infodir@
-install_sh = @install_sh@
-kernel_support_FALSE = @kernel_support_FALSE@
-kernel_support_TRUE = @kernel_support_TRUE@
-libdir = @libdir@
-libexecdir = @libexecdir@
-localstatedir = @localstatedir@
-mandir = @mandir@
-mkdir_p = @mkdir_p@
-oldincludedir = @oldincludedir@
-prefix = @prefix@
-program_transform_name = @program_transform_name@
-sbindir = @sbindir@
-sharedstatedir = @sharedstatedir@
-sysconfdir = @sysconfdir@
-target_alias = @target_alias@
-topdir = @topdir@
-event_files = \
- alpha/ev4/events alpha/ev4/unit_masks \
- alpha/ev5/events alpha/ev5/unit_masks \
- alpha/ev67/events alpha/ev67/unit_masks \
- alpha/ev6/events alpha/ev6/unit_masks \
- alpha/pca56/events alpha/pca56/unit_masks \
- i386/athlon/events i386/athlon/unit_masks \
- i386/core_2/events i386/core_2/unit_masks \
- i386/p4/events i386/p4-ht/events \
- i386/p4-ht/unit_masks i386/p4/unit_masks \
- i386/pii/events i386/pii/unit_masks \
- i386/piii/events i386/piii/unit_masks \
- i386/ppro/events i386/ppro/unit_masks \
- i386/p6_mobile/events i386/p6_mobile/unit_masks \
- i386/core/events i386/core/unit_masks \
- i386/arch_perfmon/events i386/arch_perfmon/unit_masks \
- i386/atom/events i386/atom/unit_masks \
- i386/core_i7/events i386/core_i7/unit_masks \
- i386/nehalem/events i386/nehalem/unit_masks \
- ia64/ia64/events ia64/ia64/unit_masks \
- ia64/itanium2/events ia64/itanium2/unit_masks \
- ia64/itanium/events ia64/itanium/unit_masks \
- ppc64/power4/events ppc64/power4/event_mappings ppc64/power4/unit_masks \
- ppc64/power5/events ppc64/power5/event_mappings ppc64/power5/unit_masks \
- ppc64/power5+/events ppc64/power5+/event_mappings ppc64/power5+/unit_masks \
- ppc64/power5++/events ppc64/power5++/event_mappings ppc64/power5++/unit_masks \
- ppc64/power6/events ppc64/power6/event_mappings ppc64/power6/unit_masks \
- ppc64/power7/events ppc64/power7/event_mappings ppc64/power7/unit_masks \
- ppc64/970/events ppc64/970/event_mappings ppc64/970/unit_masks \
- ppc64/970MP/events ppc64/970MP/event_mappings ppc64/970MP/unit_masks \
- ppc64/ibm-compat-v1/events ppc64/ibm-compat-v1/event_mappings ppc64/ibm-compat-v1/unit_masks \
- ppc64/pa6t/events ppc64/pa6t/event_mappings ppc64/pa6t/unit_masks \
- ppc64/cell-be/events ppc64/cell-be/unit_masks \
- rtc/events rtc/unit_masks \
- x86-64/hammer/events x86-64/hammer/unit_masks \
- x86-64/family10/events x86-64/family10/unit_masks \
- x86-64/family11h/events x86-64/family11h/unit_masks \
- arm/xscale1/events arm/xscale1/unit_masks \
- arm/xscale2/events arm/xscale2/unit_masks \
- arm/armv6/events arm/armv6/unit_masks \
- arm/armv7/events arm/armv7/unit_masks \
- arm/mpcore/events arm/mpcore/unit_masks \
- avr32/events avr32/unit_masks \
- mips/20K/events mips/20K/unit_masks \
- mips/24K/events mips/24K/unit_masks \
- mips/25K/events mips/25K/unit_masks \
- mips/34K/events mips/34K/unit_masks \
- mips/5K/events mips/5K/unit_masks \
- mips/rm7000/events mips/rm7000/unit_masks \
- mips/rm9000/events mips/rm9000/unit_masks \
- mips/sb1/events mips/sb1/unit_masks \
- mips/r10000/events mips/r10000/unit_masks \
- mips/r12000/events mips/r12000/unit_masks \
- mips/vr5432/events mips/vr5432/unit_masks \
- mips/vr5500/events mips/vr5500/unit_masks \
- ppc/7450/events ppc/7450/unit_masks \
- ppc/e500/events ppc/e500/unit_masks \
- ppc/e500v2/events ppc/e500v2/unit_masks \
- ppc/e300/events ppc/e300/unit_masks
-
-EXTRA_DIST = $(event_files)
-all: all-am
-
-.SUFFIXES:
-$(srcdir)/Makefile.in: $(srcdir)/Makefile.am $(am__configure_deps)
- @for dep in $?; do \
- case '$(am__configure_deps)' in \
- *$$dep*) \
- cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh \
- && exit 0; \
- exit 1;; \
- esac; \
- done; \
- echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign events/Makefile'; \
- cd $(top_srcdir) && \
- $(AUTOMAKE) --foreign events/Makefile
-.PRECIOUS: Makefile
-Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
- @case '$?' in \
- *config.status*) \
- cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \
- *) \
- echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \
- cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \
- esac;
-
-$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES)
- cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
-
-$(top_srcdir)/configure: $(am__configure_deps)
- cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
-$(ACLOCAL_M4): $(am__aclocal_m4_deps)
- cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh
-
-mostlyclean-libtool:
- -rm -f *.lo
-
-clean-libtool:
- -rm -rf .libs _libs
-
-distclean-libtool:
- -rm -f libtool
-uninstall-info-am:
-tags: TAGS
-TAGS:
-
-ctags: CTAGS
-CTAGS:
-
-
-distdir: $(DISTFILES)
- $(mkdir_p) $(distdir)/alpha/ev4 $(distdir)/alpha/ev5 $(distdir)/alpha/ev6 $(distdir)/alpha/ev67 $(distdir)/alpha/pca56 $(distdir)/arm/armv6 $(distdir)/arm/armv7 $(distdir)/arm/mpcore $(distdir)/arm/xscale1 $(distdir)/arm/xscale2 $(distdir)/avr32 $(distdir)/i386/arch_perfmon $(distdir)/i386/athlon $(distdir)/i386/atom $(distdir)/i386/core $(distdir)/i386/core_2 $(distdir)/i386/core_i7 $(distdir)/i386/nehalem $(distdir)/i386/p4 $(distdir)/i386/p4-ht $(distdir)/i386/p6_mobile $(distdir)/i386/pii $(distdir)/i386/piii $(distdir)/i386/ppro $(distdir)/ia64/ia64 $(distdir)/ia64/itanium $(distdir)/ia64/itanium2 $(distdir)/mips/20K $(distdir)/mips/24K $(distdir)/mips/25K $(distdir)/mips/34K $(distdir)/mips/5K $(distdir)/mips/r10000 $(distdir)/mips/r12000 $(distdir)/mips/rm7000 $(distdir)/mips/rm9000 $(distdir)/mips/sb1 $(distdir)/mips/vr5432 $(distdir)/mips/vr5500 $(distdir)/ppc/7450 $(distdir)/ppc/e300 $(distdir)/ppc/e500 $(distdir)/ppc/e500v2 $(distdir)/ppc64/970 $(distdir)/ppc64/970MP $(distdir)/ppc64/cell-be $(distdir)/ppc64/ibm-compat-v1 $(distdir)/ppc64/pa6t $(distdir)/ppc64/power4 $(distdir)/ppc64/power5 $(distdir)/ppc64/power5+ $(distdir)/ppc64/power5++ $(distdir)/ppc64/power6 $(distdir)/ppc64/power7 $(distdir)/rtc $(distdir)/x86-64/family10 $(distdir)/x86-64/family11h $(distdir)/x86-64/hammer
- @srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \
- topsrcdirstrip=`echo "$(top_srcdir)" | sed 's|.|.|g'`; \
- list='$(DISTFILES)'; for file in $$list; do \
- case $$file in \
- $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \
- $(top_srcdir)/*) file=`echo "$$file" | sed "s|^$$topsrcdirstrip/|$(top_builddir)/|"`;; \
- esac; \
- if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \
- dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \
- if test "$$dir" != "$$file" && test "$$dir" != "."; then \
- dir="/$$dir"; \
- $(mkdir_p) "$(distdir)$$dir"; \
- else \
- dir=''; \
- fi; \
- if test -d $$d/$$file; then \
- if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \
- cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \
- fi; \
- cp -pR $$d/$$file $(distdir)$$dir || exit 1; \
- else \
- test -f $(distdir)/$$file \
- || cp -p $$d/$$file $(distdir)/$$file \
- || exit 1; \
- fi; \
- done
-check-am: all-am
-check: check-am
-all-am: Makefile
-installdirs:
-install: install-am
-install-exec: install-exec-am
-install-data: install-data-am
-uninstall: uninstall-am
-
-install-am: all-am
- @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am
-
-installcheck: installcheck-am
-install-strip:
- $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \
- install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \
- `test -z '$(STRIP)' || \
- echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install
-mostlyclean-generic:
-
-clean-generic:
-
-distclean-generic:
- -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES)
-
-maintainer-clean-generic:
- @echo "This command is intended for maintainers to use"
- @echo "it deletes files that may require special tools to rebuild."
-clean: clean-am
-
-clean-am: clean-generic clean-libtool mostlyclean-am
-
-distclean: distclean-am
- -rm -f Makefile
-distclean-am: clean-am distclean-generic distclean-libtool
-
-dvi: dvi-am
-
-dvi-am:
-
-html: html-am
-
-info: info-am
-
-info-am:
-
-install-data-am: install-data-local
-
-install-exec-am:
-
-install-info: install-info-am
-
-install-man:
-
-installcheck-am:
-
-maintainer-clean: maintainer-clean-am
- -rm -f Makefile
-maintainer-clean-am: distclean-am maintainer-clean-generic
-
-mostlyclean: mostlyclean-am
-
-mostlyclean-am: mostlyclean-generic mostlyclean-libtool
-
-pdf: pdf-am
-
-pdf-am:
-
-ps: ps-am
-
-ps-am:
-
-uninstall-am: uninstall-info-am uninstall-local
-
-.PHONY: all all-am check check-am clean clean-generic clean-libtool \
- distclean distclean-generic distclean-libtool distdir dvi \
- dvi-am html html-am info info-am install install-am \
- install-data install-data-am install-data-local install-exec \
- install-exec-am install-info install-info-am install-man \
- install-strip installcheck installcheck-am installdirs \
- maintainer-clean maintainer-clean-generic mostlyclean \
- mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
- uninstall uninstall-am uninstall-info-am uninstall-local
-
-
-install-data-local:
- for i in ${event_files} ; do \
- dir=`dirname $$i` ; \
- mkdir -p $(DESTDIR)$(pkgdatadir)/$$dir ; \
- $(INSTALL_DATA) $(top_srcdir)/events/$$i $(DESTDIR)$(pkgdatadir)/$$i ; \
- done
-
-uninstall-local:
- for i in ${event_files} ; do \
- dir=`dirname $$i` ; \
- archdir=`dirname $$dir` ; \
- if test -f $(DESTDIR)$(pkgdatadir)/$$i ; then \
- rm $(DESTDIR)$(pkgdatadir)/$$i ; \
- fi; \
- if test -d $(DESTDIR)$(pkgdatadir)/$$dir ; then \
- rmdir --ignore-fail-on-non-empty $(DESTDIR)$(pkgdatadir)/$$dir ; \
- fi; \
- if test $$archdir != "." -a -d $(DESTDIR)$(pkgdatadir)/$$archdir ; then \
- rmdir --ignore-fail-on-non-empty $(DESTDIR)$(pkgdatadir)/$$archdir ; \
- fi; \
- done
-# Tell versions [3.59,3.63) of GNU make to not export all variables.
-# Otherwise a system limit (for SysV at least) may be exceeded.
-.NOEXPORT:
diff --git a/events/alpha/ev4/events b/events/alpha/ev4/events
new file mode 100644
index 0000000..8b193d1
--- /dev/null
+++ b/events/alpha/ev4/events
@@ -0,0 +1,18 @@
+# Alpha EV4 events.
+#
+event:0x00 counters:0 um:zero minimum:4096 name:ISSUES : Total issues divided by 2
+event:0x02 counters:0 um:zero minimum:4096 name:PIPELINE_DRY : Nothing issued, no valid I-stream data
+event:0x04 counters:0 um:zero minimum:4096 name:LOAD_INSNS : All load instructions
+event:0x06 counters:0 um:zero minimum:4096 name:PIPELINE_FROZEN : Nothing issued, resource conflict
+event:0x08 counters:0 um:zero minimum:4096 name:BRANCH_INSNS : All branches (conditional, unconditional, jsr, hw_rei)
+event:0x0a counters:0 um:zero minimum:4096 name:CYCLES : Total cycles
+event:0x0b counters:0 um:zero minimum:4096 name:PAL_MODE : Cycles while in PALcode environment
+event:0x0c counters:0 um:zero minimum:4096 name:NON_ISSUES : Total nonissues divided by 2
+event:0x10 counters:0 um:zero minimum:256 name:DCACHE_MISSES : Total D-cache misses
+event:0x11 counters:0 um:zero minimum:256 name:ICACHE_MISSES : Total I-cache misses
+event:0x12 counters:0 um:zero minimum:256 name:DUAL_ISSUE_CYCLES : Cycles of dual issue
+event:0x13 counters:0 um:zero minimum:256 name:BRANCH_MISPREDICTS : Branch mispredicts (conditional, jsr, hw_rei)
+event:0x14 counters:0 um:zero minimum:256 name:FP_INSNS : FP operate instructions (not br, load, store)
+event:0x15 counters:0 um:zero minimum:256 name:INTEGER_OPERATE : Integer operate instructions
+event:0x16 counters:0 um:zero minimum:256 name:STORE_INSNS : Store instructions
+# There's also EXTERNAL, by which we could monitor the 21066/21068 bus controller.
diff --git a/events/alpha/ev4/unit_masks b/events/alpha/ev4/unit_masks
new file mode 100644
index 0000000..bc77cc8
--- /dev/null
+++ b/events/alpha/ev4/unit_masks
@@ -0,0 +1,4 @@
+# Alpha EV4 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/alpha/ev5/events b/events/alpha/ev5/events
new file mode 100644
index 0000000..709e06a
--- /dev/null
+++ b/events/alpha/ev5/events
@@ -0,0 +1,49 @@
+# Alpha EV5 events
+#
+event:0x00 counters:0,2 um:zero minimum:256 name:CYCLES : Total cycles
+event:0x01 counters:0 um:zero minimum:256 name:ISSUES : Total issues
+event:0x02 counters:1 um:zero minimum:256 name:NON_ISSUE_CYCLES : Nothing issued, pipeline frozen
+event:0x03 counters:1 um:zero minimum:256 name:SPLIT_ISSUE_CYCLES : Some but not all issuable instructions issued
+event:0x04 counters:1 um:zero minimum:256 name:PIPELINE_DRY : Nothing issued, pipeline dry
+event:0x05 counters:1 um:zero minimum:256 name:REPLAY_TRAP : Replay traps (ldu, wb/maf, litmus test)
+event:0x06 counters:1 um:zero minimum:256 name:SINGLE_ISSUE_CYCLES : Single issue cycles
+event:0x07 counters:1 um:zero minimum:256 name:DUAL_ISSUE_CYCLES : Dual issue cycles
+event:0x08 counters:1 um:zero minimum:256 name:TRIPLE_ISSUE_CYCLES : Triple issue cycles
+event:0x09 counters:1 um:zero minimum:256 name:QUAD_ISSUE_CYCLES : Quad issue cycles
+event:0x0a counters:1 um:zero minimum:256 name:FLOW_CHANGE : Flow change (meaning depends on counter 2)
+# ??? This one's dependent on the value in PCSEL2: If measuring PC_MISPR,
+# this is jsr-ret instructions, if measuring BRANCH_MISPREDICTS, this is
+# conditional branches, otherwise this is all branch insns, including hw_rei.
+event:0x0b counters:1 um:zero minimum:256 name:INTEGER_OPERATE : Integer operate instructions
+event:0x0c counters:1 um:zero minimum:256 name:FP_INSNS : FP operate instructions (not br, load, store)
+# FIXME: Bug carried over
+event:0x0c counters:1 um:zero minimum:256 name:LOAD_INSNS : Load instructions
+event:0x0d counters:1 um:zero minimum:256 name:STORE_INSNS : Store instructions
+event:0x0e counters:1 um:zero minimum:256 name:ICACHE_ACCESS : Instruction cache access
+event:0x0f um:zero minimum:256 name:DCACHE_ACCESS : Data cache access
+event:0x10 counters:2 um:zero minimum:256 name:LONG_STALLS : Stalls longer than 15 cycles
+event:0x11 counters:2 um:zero minimum:256 name:PC_MISPR : PC mispredicts
+event:0x12 counters:2 um:zero minimum:256 name:BRANCH_MISPREDICTS : Branch mispredicts
+event:0x13 counters:2 um:zero minimum:256 name:ICACHE_MISSES : Instruction cache misses
+event:0x14 counters:2 um:zero minimum:256 name:ITB_MISS : Instruction TLB miss
+event:0x15 counters:2 um:zero minimum:256 name:DCACHE_MISSES : Data cache misses
+event:0x16 counters:2 um:zero minimum:256 name:DTB_MISS : Data TLB miss
+event:0x17 counters:2 um:zero minimum:256 name:LOADS_MERGED : Loads merged in MAF
+event:0x18 counters:2 um:zero minimum:256 name:LDU_REPLAYS : LDU replay traps
+event:0x19 counters:2 um:zero minimum:256 name:WB_MAF_FULL_REPLAYS : WB/MAF full replay traps
+event:0x1a counters:2 um:zero minimum:256 name:MEM_BARRIER : Memory barrier instructions
+event:0x1b counters:2 um:zero minimum:256 name:LOAD_LOCKED : LDx/L instructions
+event:0x1c counters:1 um:zero minimum:256 name:SCACHE_ACCESS : S-cache access
+event:0x1d counters:1 um:zero minimum:256 name:SCACHE_READ : S-cache read
+event:0x1e counters:1,2 um:zero minimum:256 name:SCACHE_WRITE : S-cache write
+event:0x1f counters:1 um:zero minimum:256 name:SCACHE_VICTIM : S-cache victim
+event:0x20 counters:2 um:zero minimum:256 name:SCACHE_MISS : S-cache miss
+event:0x21 counters:2 um:zero minimum:256 name:SCACHE_READ_MISS : S-cache read miss
+event:0x22 counters:2 um:zero minimum:256 name:SCACHE_WRITE_MISS : S-cache write miss
+event:0x23 counters:2 um:zero minimum:256 name:SCACHE_SH_WRITE : S-cache shared writes
+event:0x24 counters:1 um:zero minimum:256 name:BCACHE_HIT : B-cache hit
+event:0x25 counters:1 um:zero minimum:256 name:BCACHE_VICTIM : B-cache victim
+event:0x26 counters:2 um:zero minimum:256 name:BCACHE_MISS : B-cache miss
+event:0x27 counters:1 um:zero minimum:256 name:SYS_REQ : System requests
+event:0x28 counters:2 um:zero minimum:256 name:SYS_INV : System invalidates
+event:0x29 counters:2 um:zero minimum:256 name:SYS_READ_REQ : System read requests
diff --git a/events/alpha/ev5/unit_masks b/events/alpha/ev5/unit_masks
new file mode 100644
index 0000000..4f24fa9
--- /dev/null
+++ b/events/alpha/ev5/unit_masks
@@ -0,0 +1,4 @@
+# Alpha EV-5 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/alpha/ev6/events b/events/alpha/ev6/events
new file mode 100644
index 0000000..2039cef
--- /dev/null
+++ b/events/alpha/ev6/events
@@ -0,0 +1,11 @@
+# Alpha EV6 events
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Total cycles
+event:0x01 counters:1 um:zero minimum:500 name:RETIRED : Retired instructions
+event:0x02 counters:1 um:zero minimum:500 name:COND_BRANCHES : Retired conditional branches
+event:0x03 counters:1 um:zero minimum:500 name:BRANCH_MISPREDICTS : Retired branch mispredicts
+event:0x04 counters:1 um:zero minimum:500 name:DTB_MISS : Retired DTB single misses * 2
+event:0x05 counters:1 um:zero minimum:500 name:DTB_DD_MISS : Retired DTB double double misses
+event:0x06 counters:1 um:zero minimum:500 name:ITB_MISS : Retired ITB misses
+event:0x07 counters:1 um:zero minimum:500 name:UNALIGNED_TRAP : Retired unaligned traps
+event:0x08 counters:1 um:zero minimum:500 name:REPLAY_TRAP : Replay traps
diff --git a/events/alpha/ev6/unit_masks b/events/alpha/ev6/unit_masks
new file mode 100644
index 0000000..bbe38c6
--- /dev/null
+++ b/events/alpha/ev6/unit_masks
@@ -0,0 +1,4 @@
+# Alpha EV-6 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/alpha/ev67/events b/events/alpha/ev67/events
new file mode 100644
index 0000000..b603871
--- /dev/null
+++ b/events/alpha/ev67/events
@@ -0,0 +1,27 @@
+# Alpha EV-67 Events
+#
+event:0x00 counters:0 um:zero minimum:500 name:CYCLES : Total cycles
+event:0x01 counters:1 um:zero minimum:500 name:DELAYED_CYCLES : Cycles of delayed retire pointer advance
+# FIXME: bug carried over
+event:0x00 counters:0,1 um:zero minimum:500 name:RETIRED : Retired instructions
+event:0x02 counters:1 um:zero minimum:500 name:BCACHE_MISS : Bcache misses/long probe latency
+event:0x03 counters:1 um:zero minimum:500 name:MBOX_REPLAY : Mbox replay traps
+# FIXME: all the below used PM_CTR
+event:0x04 counters:0 um:zero minimum:500 name:STALLED_0 : PCTR0 triggered; stalled between fetch and map stages
+event:0x05 counters:0 um:zero minimum:500 name:TAKEN_0 : PCTR0 triggered; branch was not mispredicted and taken
+event:0x06 counters:0 um:zero minimum:500 name:MISPREDICT_0 : PCTR0 triggered; branch was mispredicted
+event:0x07 counters:0 um:zero minimum:500 name:ITB_MISS_0 : PCTR0 triggered; ITB miss
+event:0x08 counters:0 um:zero minimum:500 name:DTB_MISS_0 : PCTR0 triggered; DTB miss
+event:0x09 counters:0 um:zero minimum:500 name:REPLAY_0 : PCTR0 triggered; replay trap
+event:0x0a counters:0 um:zero minimum:500 name:LOAD_STORE_0 : PCTR0 triggered; load-store order replay trap
+event:0x0b counters:0 um:zero minimum:500 name:ICACHE_MISS_0 : PCTR0 triggered; Icache miss
+event:0x0c counters:0 um:zero minimum:500 name:UNALIGNED_0 : PCTR0 triggered; unaligned load/store trap
+event:0x0d counters:0 um:zero minimum:500 name:STALLED_1 : PCTR1 triggered; stalled between fetch and map stages
+event:0x0e counters:0 um:zero minimum:500 name:TAKEN_1 : PCTR1 triggered; branch was not mispredicted and taken
+event:0x0f counters:0 um:zero minimum:500 name:MISPREDICT_1 : PCTR1 triggered; branch was mispredicted
+event:0x10 counters:0 um:zero minimum:500 name:ITB_MISS_1 : PCTR1 triggered; ITB miss
+event:0x11 counters:0 um:zero minimum:500 name:DTB_MISS_1 : PCTR1 triggered; DTB miss
+event:0x12 counters:0 um:zero minimum:500 name:REPLAY_1 : PCTR1 triggered; replay trap
+event:0x13 counters:0 um:zero minimum:500 name:LOAD_STORE_1 : PCTR1 triggered; load-store order replay trap
+event:0x14 counters:0 um:zero minimum:500 name:ICACHE_MISS_1 : PCTR1 triggered; Icache miss
+event:0x15 counters:0 um:zero minimum:500 name:UNALIGNED_1 : PCTR1 triggered; unaligned load/store trap
diff --git a/events/alpha/ev67/unit_masks b/events/alpha/ev67/unit_masks
new file mode 100644
index 0000000..3461e49
--- /dev/null
+++ b/events/alpha/ev67/unit_masks
@@ -0,0 +1,4 @@
+# Alpha EV-67 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/alpha/pca56/events b/events/alpha/pca56/events
new file mode 100644
index 0000000..334babe
--- /dev/null
+++ b/events/alpha/pca56/events
@@ -0,0 +1,2 @@
+# PCA-56
+# FIXME: no events ? What's going on here Falk ?
diff --git a/events/alpha/pca56/unit_masks b/events/alpha/pca56/unit_masks
new file mode 100644
index 0000000..2b807b7
--- /dev/null
+++ b/events/alpha/pca56/unit_masks
@@ -0,0 +1,3 @@
+# Alpha PCA-56 possible unit masks
+#
+# FIXME: any events ...?
diff --git a/events/arm/armv7-ca9/events b/events/arm/armv7-ca9/events
new file mode 100644
index 0000000..c1e4084
--- /dev/null
+++ b/events/arm/armv7-ca9/events
@@ -0,0 +1,50 @@
+# ARM Cortex A9 events
+# From Cortex A9 TRM
+#
+include:arm/armv7-common
+event:0x40 counters:1,2,3,4,5,6 um:zero minimum:500 name:JAVA_BC_EXEC : Number of Java bytecodes decoded, including speculative ones
+event:0x41 counters:1,2,3,4,5,6 um:zero minimum:500 name:JAVA_SFTBC_EXEC : Number of software Java bytecodes decoded, including speculative ones
+event:0x42 counters:1,2,3,4,5,6 um:zero minimum:500 name:JAVA_BB_EXEC : Number of Jazelle taken branches executed, including those flushed due to a previous load/store which aborts late
+
+event:0x50 counters:1,2,3,4,5,6 um:zero minimum:500 name:CO_LF_MISS : Number of coherent linefill requests which miss in all other CPUs, meaning that the request is sent to external memory
+event:0x51 counters:1,2,3,4,5,6 um:zero minimum:500 name:CO_LF_HIT : Number of coherent linefill requests which hit in another CPU, meaning that the linefill data is fetched directly from the relevant cache
+
+event:0x60 counters:1,2,3,4,5,6 um:zero minimum:500 name:IC_DEP_STALL : Number of cycles where CPU is ready to accept new instructions but does not receive any because of the instruction side not being able to provide any and the instruction cache is currently performing at least one linefill
+event:0x61 counters:1,2,3,4,5,6 um:zero minimum:500 name:DC_DEP_STALL : Number of cycles where CPU has some instructions that it cannot issue to any pipeline and the LSU has at least one pending linefill request but no pending TLB requests
+event:0x63 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_PASS : Number of STREX instructions architecturally executed and passed
+event:0x64 counters:1,2,3,4,5,6 um:zero minimum:500 name:STREX_FAILS : Number of STREX instructions architecturally executed and failed
+event:0x65 counters:1,2,3,4,5,6 um:zero minimum:500 name:DATA_EVICT : Number of eviction requests due to a linefill in the data cache
+event:0x66 counters:1,2,3,4,5,6 um:zero minimum:500 name:ISS_NO_DISP : Number of cycles where the issue stage does not dispatch any instruction
+event:0x67 counters:1,2,3,4,5,6 um:zero minimum:500 name:ISS_EMPTY : Number of cycles where the issue stage is empty
+event:0x68 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_RENAME : Number of instructions going through the Register Renaming stage
+
+event:0x6E counters:1,2,3,4,5,6 um:zero minimum:500 name:PRD_FN_RET : Number of procedure returns whose condition codes do not fail, excluding all exception returns
+
+event:0x70 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_MAIN_EXEC : Number of instructions being executed in main execution pipeline of the CPU, the multiply pipeline and the ALU pipeline
+event:0x71 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_SND_EXEC : Number of instructions being executed in the second execution pipeline (ALU) of the CPU
+event:0x72 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_LSU : Number of instructions being executed in the Load/Store unit
+event:0x73 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_FP_RR : Number of floating-point instructions going through the Register Rename stage
+event:0x74 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_NEON_RR : Number of NEON instructions going through the Register Rename stage
+
+event:0x80 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_PLD : Number of cycles where CPU is stalled because PLD slots are all full
+event:0x81 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_WRITE : Number of cycles where CPU is stalled because data side is full and executing writes to external memory
+event:0x82 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_TLB : Number of cycles where CPU is stalled because of main TLB misses on requests issued by the instruction side
+event:0x83 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_TLB : Number of cycles where CPU is stalled because of main TLB misses on requests issued by the data side
+event:0x84 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_INS_UTLB : Number of cycles where CPU is stalled because of micro TLB misses on the instruction side
+event:0x85 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DATA_ULTB : Number of cycles where CPU is stalled because of micro TLB misses on the data side
+event:0x86 counters:1,2,3,4,5,6 um:zero minimum:500 name:STALL_DMB : Number of cycles where CPU is stalled due to executed of a DMB memory barrier
+
+event:0x8A counters:1,2,3,4,5,6 um:zero minimum:500 name:CLK_INT_EN : Number of cycles during which the integer core clock is enabled
+event:0x8B counters:1,2,3,4,5,6 um:zero minimum:500 name:CLK_DE_EN : Number of cycles during which the Data Engine clock is enabled
+
+event:0x90 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_ISB : Number of ISB instructions architecturally executed
+event:0x91 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_DSB : Number of DSB instructions architecturally executed
+event:0x92 counters:1,2,3,4,5,6 um:zero minimum:500 name:INS_DMB : Number of DMB instructions speculatively executed
+event:0x93 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXT_IRQ : Number of external interrupts executed by the processor
+
+event:0xA0 counters:1,2,3,4,5,6 um:zero minimum:500 name:PLE_CL_REQ_CMP : PLE cache line request completed
+event:0xA1 counters:1,2,3,4,5,6 um:zero minimum:500 name:PLE_CL_REQ_SKP : PLE cache line request skipped
+event:0xA2 counters:1,2,3,4,5,6 um:zero minimum:500 name:PLE_FIFO_FLSH : PLE FIFO flush
+event:0xA3 counters:1,2,3,4,5,6 um:zero minimum:500 name:PLE_REQ_COMP : PLE request completed
+event:0xA4 counters:1,2,3,4,5,6 um:zero minimum:500 name:PLE_FIFO_OF : PLE FIFO overflow
+event:0xA5 counters:1,2,3,4,5,6 um:zero minimum:500 name:PLE_REQ_PRG : PLE request programmed
diff --git a/events/arm/armv7-ca9/unit_masks b/events/arm/armv7-ca9/unit_masks
new file mode 100644
index 0000000..4027469
--- /dev/null
+++ b/events/arm/armv7-ca9/unit_masks
@@ -0,0 +1,4 @@
+# ARM V7 PMNC possible unit masks
+#
+name:zero type:mandatory default:0x00
+ 0x00 No unit mask
diff --git a/events/arm/armv7-common/events b/events/arm/armv7-common/events
new file mode 100644
index 0000000..c4fe8c7
--- /dev/null
+++ b/events/arm/armv7-common/events
@@ -0,0 +1,22 @@
+# ARM V7 events
+# From ARM ARM
+#
+event:0x00 counters:1,2,3,4,5,6 um:zero minimum:500 name:PMNC_SW_INCR : Software increment of PMNC registers
+event:0x01 counters:1,2,3,4,5,6 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory
+event:0x02 counters:1,2,3,4,5,6 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
+event:0x03 counters:1,2,3,4,5,6 um:zero minimum:500 name:DCACHE_REFILL : Data R/W operation that causes a refill from cache or normal cacheable memory
+event:0x04 counters:1,2,3,4,5,6 um:zero minimum:500 name:DCACHE_ACCESS : Data R/W from cache
+event:0x05 counters:1,2,3,4,5,6 um:zero minimum:500 name:DTLB_REFILL : Data R/W that causes a TLB refill
+event:0x06 counters:1,2,3,4,5,6 um:zero minimum:500 name:DREAD : Data read architecturally executed (note: architecturally executed = for instructions that are unconditional or that pass the condition code)
+event:0x07 counters:1,2,3,4,5,6 um:zero minimum:500 name:DWRITE : Data write architecturally executed
+event:0x08 counters:1,2,3,4,5,6 um:zero minimum:500 name:INSTR_EXECUTED : All executed instructions
+event:0x09 counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_TAKEN : Exception taken
+event:0x0A counters:1,2,3,4,5,6 um:zero minimum:500 name:EXC_EXECUTED : Exception return architecturally executed
+event:0x0B counters:1,2,3,4,5,6 um:zero minimum:500 name:CID_WRITE : Instruction that writes to the Context ID Register architecturally executed
+event:0x0C counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_WRITE : SW change of PC, architecturally executed (not by exceptions)
+event:0x0D counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_IMM_BRANCH : Immediate branch instruction executed (taken or not)
+event:0x0E counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_PROC_RETURN : Procedure return architecturally executed (not by exceptions)
+event:0x0F counters:1,2,3,4,5,6 um:zero minimum:500 name:UNALIGNED_ACCESS : Unaligned access architecturally executed
+event:0x10 counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_BRANCH_MIS_PRED : Branch mispredicted or not predicted. Counts pipeline flushes because of misprediction
+event:0x12 counters:1,2,3,4,5,6 um:zero minimum:500 name:PC_BRANCH_MIS_USED : Branch or change in program flow that could have been predicted
+event:0xFF counters:0 um:zero minimum:500 name:CPU_CYCLES : Number of CPU cycles
diff --git a/events/arm/armv7-common/unit_masks b/events/arm/armv7-common/unit_masks
new file mode 100644
index 0000000..4027469
--- /dev/null
+++ b/events/arm/armv7-common/unit_masks
@@ -0,0 +1,4 @@
+# ARM V7 PMNC possible unit masks
+#
+name:zero type:mandatory default:0x00
+ 0x00 No unit mask
diff --git a/events/arm/armv7/events b/events/arm/armv7/events
index ffecf2b..d6d9227 100644
--- a/events/arm/armv7/events
+++ b/events/arm/armv7/events
@@ -1,24 +1,7 @@
# ARM V7 events
# From Cortex A8 DDI (ARM DDI 0344B, revision r1p1)
#
-event:0x00 counters:1,2,3,4 um:zero minimum:500 name:PMNC_SW_INCR : Software increment of PMNC registers
-event:0x01 counters:1,2,3,4 um:zero minimum:500 name:IFETCH_MISS : Instruction fetch misses from cache or normal cacheable memory
-event:0x02 counters:1,2,3,4 um:zero minimum:500 name:ITLB_MISS : Instruction fetch misses from TLB
-event:0x03 counters:1,2,3,4 um:zero minimum:500 name:DCACHE_REFILL : Data R/W operation that causes a refill from cache or normal cacheable memory
-event:0x04 counters:1,2,3,4 um:zero minimum:500 name:DCACHE_ACCESS : Data R/W from cache
-event:0x05 counters:1,2,3,4 um:zero minimum:500 name:DTLB_REFILL : Data R/W that causes a TLB refill
-event:0x06 counters:1,2,3,4 um:zero minimum:500 name:DREAD : Data read architecturally executed (note: architecturally executed = for instructions that are unconditional or that pass the condition code)
-event:0x07 counters:1,2,3,4 um:zero minimum:500 name:DWRITE : Data write architecturally executed
-event:0x08 counters:1,2,3,4 um:zero minimum:500 name:INSTR_EXECUTED : All executed instructions
-event:0x09 counters:1,2,3,4 um:zero minimum:500 name:EXC_TAKEN : Exception taken
-event:0x0A counters:1,2,3,4 um:zero minimum:500 name:EXC_EXECUTED : Exception return architecturally executed
-event:0x0B counters:1,2,3,4 um:zero minimum:500 name:CID_WRITE : Instruction that writes to the Context ID Register architecturally executed
-event:0x0C counters:1,2,3,4 um:zero minimum:500 name:PC_WRITE : SW change of PC, architecturally executed (not by exceptions)
-event:0x0D counters:1,2,3,4 um:zero minimum:500 name:PC_IMM_BRANCH : Immediate branch instruction executed (taken or not)
-event:0x0E counters:1,2,3,4 um:zero minimum:500 name:PC_PROC_RETURN : Procedure return architecturally executed (not by exceptions)
-event:0x0F counters:1,2,3,4 um:zero minimum:500 name:UNALIGNED_ACCESS : Unaligned access architecturally executed
-event:0x10 counters:1,2,3,4 um:zero minimum:500 name:PC_BRANCH_MIS_PRED : Branch mispredicted or not predicted. Counts pipeline flushes because of misprediction
-event:0x12 counters:1,2,3,4 um:zero minimum:500 name:PC_BRANCH_MIS_USED : Branch or change in program flow that could have been predicted
+include:arm/armv7-common
event:0x40 counters:1,2,3,4 um:zero minimum:500 name:WRITE_BUFFER_FULL : Any write buffer full cycle
event:0x41 counters:1,2,3,4 um:zero minimum:500 name:L2_STORE_MERGED : Any store that is merged in L2 cache
event:0x42 counters:1,2,3,4 um:zero minimum:500 name:L2_STORE_BUFF : Any bufferable store from load/store to L2 cache
@@ -49,5 +32,3 @@ event:0x5A counters:1,2,3,4 um:zero minimum:500 name:NEON_CYCLES : Number of cyc
event:0x70 counters:1,2,3,4 um:zero minimum:500 name:PMU0_EVENTS : Number of events from external input source PMUEXTIN[0]
event:0x71 counters:1,2,3,4 um:zero minimum:500 name:PMU1_EVENTS : Number of events from external input source PMUEXTIN[1]
event:0x72 counters:1,2,3,4 um:zero minimum:500 name:PMU_EVENTS : Number of events from both external input sources PMUEXTIN[0] and PMUEXTIN[1]
-event:0xFF counters:0 um:zero minimum:500 name:CPU_CYCLES : Number of CPU cycles
-
diff --git a/events/avr32/events b/events/avr32/events
new file mode 100644
index 0000000..489d914
--- /dev/null
+++ b/events/avr32/events
@@ -0,0 +1,27 @@
+# AVR32 events
+#
+event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
+event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall due to data dependency
+event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of Instruction TLB misses
+event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of Data TLB misses
+event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
+event:0x06 counters:1,2 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted
+event:0x07 counters:1,2 um:zero minimum:500 name:INSN_EXECUTED : instructions executed
+event:0x08 counters:1,2 um:zero minimum:500 name:DCACHE_WBUF_FULL : data cache write buffers full
+event:0x09 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_WBUF_FULL : cycles stalled due to data cache write buffers full
+event:0x0a counters:1,2 um:zero minimum:500 name:DCACHE_READ_MISS : data cache read miss
+event:0x0b counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_READ_MISS : cycles stalled due to data cache read miss
+event:0x0c counters:1,2 um:zero minimum:500 name:WRITE_ACCESS : write access
+event:0x0d counters:1,2 um:zero minimum:500 name:CYCLES_WRITE_ACCESS : cycles when write access is ongoing
+event:0x0e counters:1,2 um:zero minimum:500 name:READ_ACCESS : read access
+event:0x0f counters:1,2 um:zero minimum:500 name:CYCLES_READ_ACCESS : cycles when read access is ongoing
+event:0x10 counters:1,2 um:zero minimum:500 name:CACHE_STALL : read or write access that stalled
+event:0x11 counters:1,2 um:zero minimum:500 name:CYCLES_CACHE_STALL : cycles stalled doing read or write access
+event:0x12 counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS : data cache access
+event:0x13 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_ACCESS : cycles when data cache access is ongoing
+event:0x14 counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache line writeback
+event:0x15 counters:1,2 um:zero minimum:500 name:ACCUMULATOR_HIT : accumulator cache hit
+event:0x16 counters:1,2 um:zero minimum:500 name:ACCUMULATOR_MISS : accumulator cache miss
+event:0x17 counters:1,2 um:zero minimum:500 name:BTB_HIT : branch target buffer hit
+event:0xff counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
diff --git a/events/avr32/unit_masks b/events/avr32/unit_masks
new file mode 100644
index 0000000..37d9839
--- /dev/null
+++ b/events/avr32/unit_masks
@@ -0,0 +1,4 @@
+# AVR32 performance counters possible unit masks
+#
+name:zero type:mandatory default:0x00
+ 0x00 No unit mask
diff --git a/events/i386/arch_perfmon/events b/events/i386/arch_perfmon/events
new file mode 100644
index 0000000..960e3bb
--- /dev/null
+++ b/events/i386/arch_perfmon/events
@@ -0,0 +1,10 @@
+#
+# Intel Architectural events as of arch perfmon v2
+#
+event:0x3c counters:cpuid um:zero minimum:6000 filter:0 name:CPU_CLK_UNHALTED : Clock cycles when not halted
+event:0x3c counters:cpuid um:one minimum:6000 filter:2 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
+event:0xc0 counters:cpuid um:zero minimum:6000 filter:1 name:INST_RETIRED : number of instructions retired
+event:0x2e counters:cpuid um:x41 minimum:6000 filter:4 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
+event:0x2e counters:cpuid um:x4f minimum:6000 filter:3 name:LLC_REFS : Last level cache demand requests from this core
+event:0xc4 counters:cpuid um:zero minimum:500 filter:5 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:cpuid um:zero minimum:500 filter:6 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
diff --git a/events/i386/arch_perfmon/unit_masks b/events/i386/arch_perfmon/unit_masks
new file mode 100644
index 0000000..ab123ad
--- /dev/null
+++ b/events/i386/arch_perfmon/unit_masks
@@ -0,0 +1,11 @@
+# Intel architectural perfmon unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:one type:mandatory default:0x1
+ 0x1 No unit mask
+name:x41 type:mandatory default:0x41
+ 0x41 No unit mask
+name:x4f type:mandatory default:0x4f
+ 0x4f No unit mask
+# \ No newline at end of file
diff --git a/events/i386/athlon/events b/events/i386/athlon/events
new file mode 100644
index 0000000..830f4f7
--- /dev/null
+++ b/events/i386/athlon/events
@@ -0,0 +1,27 @@
+# Athlon Events
+#
+event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSNS : Retired instructions (includes exceptions, interrupts, resyncs)
+event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_OPS : Retired Ops
+event:0x80 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_FETCHES : Instruction cache fetches
+event:0x81 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
+event:0x42 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_L2 : Data cache refills from L2
+event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_SYSTEM : Data cache refills from system
+event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_WRITEBACKS : Data cache write backs
+event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCHES : Retired branches (conditional, unconditional, exceptions, interrupts)
+event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCHES_MISPREDICTED : Retired branches mispredicted
+event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCHES : Retired taken branches
+event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCHES_MISPREDICTED : Retired taken branches mispredicted
+event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISSES_L2_DTLD_HITS : L1 DTLB misses and L2 DTLB hits
+event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_AND_L2_DTLB_MISSES : L1 and L2 DTLB misses
+event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_DATA_REFS : Misaligned data references
+event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISSES_L2_ITLB_HITS : L1 ITLB misses (and L2 ITLB hits)
+event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_AND_L2_ITLB_MISSES : L1 and L2 ITLB misses
+event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers
+event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_RESYNC_BRANCHES : Retired resync branches (only non-control transfer branches counted)
+event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED : Interrupts masked cycles (IF=0)
+event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_PENDING : Interrupts masked while pending cycles (INTR while IF=0)
+event:0xcf counters:0,1,2,3 um:zero minimum:10 name:HARDWARE_INTERRUPTS : Number of taken hardware interrupts
+# There are other events, but they were removed from the architecture manuals
diff --git a/events/i386/athlon/unit_masks b/events/i386/athlon/unit_masks
new file mode 100644
index 0000000..b5b0da8
--- /dev/null
+++ b/events/i386/athlon/unit_masks
@@ -0,0 +1,11 @@
+# Athlon possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:moesi type:bitmask default:0x1f
+ 0x10 (M)odified cache state
+ 0x08 (O)wner cache state
+ 0x04 (E)xclusive cache state
+ 0x02 (S)hared cache state
+ 0x01 (I)nvalid cache state
+ 0x1f All cache states
diff --git a/events/i386/atom/events b/events/i386/atom/events
new file mode 100644
index 0000000..ed93445
--- /dev/null
+++ b/events/i386/atom/events
@@ -0,0 +1,80 @@
+#
+# Intel Atom (Silverthorne) events
+#
+# architectural perfmon events
+event:0x3c counters:0,1 um:cpu_clk_unhalted minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
+event:0x3c counters:0,1 um:one minimum:6000 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
+event:0xc0 counters:0,1 um:one minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0x2e counters:0,1 um:x41 minimum:6000 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
+event:0x2e counters:0,1 um:x4f minimum:6000 name:LLC_REFS : Last level cache demand requests from this core
+event:0xc4 counters:0,1 um:br_inst_retired minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
+#
+event:0x02 counters:0,1 um:store_forwards minimum:6000 name:STORE_FORWARDS : Good store forwards
+event:0x06 counters:0,1 um:segment_reg_loads minimum:6000 name:SEGMENT_REG_LOADS : Number of segment register loads
+event:0x07 counters:0,1 um:simd_prefetch minimum:6000 name:PREFETCH : Streaming SIMD Extensions (SSE) Prefetch instructions executed
+event:0x08 counters:0,1 um:data_tlb_misses minimum:6000 name:DATA_TLB_MISSES : Memory accesses that missed the DTLB
+event:0x0C counters:0,1 um:page_walks minimum:6000 name:PAGE_WALKS : Page walks
+event:0x10 counters:0,1 um:x87_comp_ops_exe minimum:6000 name:X87_COMP_OPS_EXE : Floating point computational micro-ops
+event:0x11 counters:0,1 um:fp_assist minimum:6000 name:FP_ASSIST : Floating point assists
+event:0x12 counters:0,1 um:mul minimum:6000 name:MUL : Multiply operations
+event:0x13 counters:0,1 um:div minimum:6000 name:DIV : Divide operations
+event:0x14 counters:0,1 um:one minimum:6000 name:CYCLES_DIV_BUSY : Cycles the driver is busy
+event:0x21 counters:0,1 um:core minimum:6000 name:CORE : Cycles L2 address bus is in use
+event:0x22 counters:0,1 um:core minimum:6000 name:L2_DBUS_BUSY : Cycles the L2 cache data bus is busy
+event:0x24 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_IN : L2 cache misses
+event:0x25 counters:0,1 um:core minimum:500 name:L2_M_LINES_IN : L2 cache line modifications
+event:0x26 counters:0,1 um:core,prefetch minimum:500 name:L2_LINES_OUT : L2 cache lines evicted
+event:0x27 counters:0,1 um:core,prefetch minimum:500 name:L2_M_LINES_OUT : Modified lines evicted from the L2 cache
+event:0x28 counters:0,1 um:core,mesi minimum:6000 name:L2_IFETCH : L2 cacheable instruction fetch requests
+event:0x29 counters:0,1 um:core,prefetch,mesi minimum:6000 name:L2_LD : L2 cache reads
+event:0x2A counters:0,1 um:core,mesi minimum:6000 name:L2_ST : L2 store requests
+event:0x2B counters:0,1 um:core,mesi minimum:6000 name:L2_LOCK : L2 locked accesses
+event:0x2E counters:0,1 um:l2_rqsts,core,prefetch,mesi minimum:6000 name:L2_RQSTS : L2 cache requests
+event:0x30 counters:0,1 um:core,prefetch,mesi minimum:500 name:L2_REJECT_BUSQ : Rejected L2 cache requests
+event:0x32 counters:0,1 um:core minimum:6000 name:L2_NO_REQ : Cycles no L2 cache requests are pending
+event:0x3A counters:0,1 um:zero minimum:6000 name:EIST_TRANS : Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions
+event:0x3B counters:0,1 um:thermal_trip minimum:6000 name:THERMAL_TRIP : Number of thermal trips
+event:0x40 counters:0,1 um:l1d_cache minimum:6000 name:L1D_CACHE : L1d Cache accesses
+event:0x60 counters:0,1 um:core,agent minimum:6000 name:BUS_REQUEST_OUTSTANDING : Outstanding cacheable data read bus requests duration
+event:0x61 counters:0,1 um:agent minimum:6000 name:BUS_BNR_DRV : Number of Bus Not Ready signals asserted
+event:0x62 counters:0,1 um:agent minimum:6000 name:BUS_DRDY_CLOCKS : Bus cycles when data is sent on the bus
+event:0x63 counters:0,1 um:core,agent minimum:6000 name:BUS_LOCK_CLOCKS : Bus cycles when a LOCK signal is asserted.
+event:0x64 counters:0,1 um:core minimum:6000 name:BUS_DATA_RCV : Bus cycles while processor receives data
+event:0x65 counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_BRD : Burst read bus transactions
+event:0x66 counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_RFO : RFO bus transactions
+event:0x67 counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_WB : Explicit writeback bus transactions
+event:0x68 counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_IFETCH : Instruction-fetch bus transactions.
+event:0x69 counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_INVAL : Invalidate bus transactions
+event:0x6A counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_PWR : Partial write bus transaction.
+event:0x6B counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_P : Partial bus transactions
+event:0x6C counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_IO : IO bus transactions
+event:0x6D counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_DEF : Deferred bus transactions
+event:0x6E counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_BURST : Burst (full cache-line) bus transactions.
+event:0x6F counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_MEM : Memory bus transactions
+event:0x70 counters:0,1 um:core,agent minimum:500 name:BUS_TRANS_ANY : All bus transactions
+event:0x77 counters:0,1 um:core,mesi minimum:500 name:EXT_SNOOP : External snoops
+event:0x7A counters:0,1 um:agent minimum:500 name:BUS_HIT_DRV : HIT signal asserted
+event:0x7B counters:0,1 um:agent minimum:500 name:BUS_HITM_DRV : HITM signal asserted
+event:0x7D counters:0,1 um:core minimum:500 name:BUSQ_EMPTY : Bus queue is empty
+event:0x7E counters:0,1 um:core,agent minimum:6000 name:SNOOP_STALL_DRV : Bus stalled for snoops
+event:0x7F counters:0,1 um:core minimum:6000 name:BUS_IO_WAIT : IO requests waiting in the bus queue
+event:0x80 counters:0,1 um:icache minimum:6000 name:ICACHE : Instruction cache accesses
+event:0x82 counters:0,1 um:itlb minimum:6000 name:ITLB : ITLB events
+event:0xAA counters:0,1 um:macro_insts minimum:6000 name:MACRO_INSTS : instructions decoded
+event:0xB0 counters:0,1 um:simd_uops_exec minimum:6000 name:SIMD_UOPS_EXEC : SIMD micro-ops executed
+event:0xB1 counters:0,1 um:simd_sat_uop_exec minimum:6000 name:SIMD_SAT_UOP_EXEC : SIMD saturated arithmetic micro-ops executed
+event:0xB3 counters:0,1 um:simd_uop_type_exec minimum:6000 name:SIMD_UOP_TYPE_EXEC : SIMD packed microops executed
+event:0xC2 counters:0,1 um:uops_retired minimum:6000 name:UOPS_RETIRED : Micro-ops retired
+event:0xC3 counters:0,1 um:one minimum:6000 name:MACHINE_CLEARS : Self-Modifying Code detected
+event:0xC6 counters:0,1 um:cycles_int_masked minimum:6000 name:CYCLES_INT_MASKED : Cycles during which interrupts are disabled
+event:0xC7 counters:0,1 um:simd_inst_retired minimum:6000 name:SIMD_INST_RETIRED : Retired Streaming SIMD Extensions (SSE) instructions
+event:0xC8 counters:0,1 um:zero minimum:6000 name:HW_INT_RCV : Hardware interrupts received
+event:0xCA counters:0,1 um:simd_comp_inst_retired minimum:6000 name:SIMD_COMP_INST_RETIRED : Retired computational Streaming SIMD Extensions (SSE) instructions.
+event:0xCB counters:0,1 um:mem_load_retired minimum:6000 name:MEM_LOAD_RETIRED : Retired loads
+event:0xCD counters:0,1 um:zero minimum:6000 name:SIMD_ASSIST : SIMD assists invoked
+event:0xCE counters:0,1 um:zero minimum:6000 name:SIMD_INSTR_RETIRED : SIMD Instructions retired
+event:0xCF counters:0,1 um:zero minimum:6000 name:SIMD_SAT_INSTR_RETIRED : Saturated arithmetic instructions retired
+event:0xE0 counters:0,1 um:zero minimum:6000 name:BR_INST_DECODED : Branch instructions decoded
+event:0xE4 counters:0,1 um:zero minimum:6000 name:BOGUS_BR : Bogus branches
+event:0xE6 counters:0,1 um:one minimum:6000 name:BACLEARS : BACLEARS asserted
diff --git a/events/i386/atom/unit_masks b/events/i386/atom/unit_masks
new file mode 100644
index 0000000..acaec23
--- /dev/null
+++ b/events/i386/atom/unit_masks
@@ -0,0 +1,120 @@
+#
+# Intel Atom (Silverthorne) unit masks
+#
+include:i386/arch_perfmon
+name:store_forwards type:mandatory default:0x81
+ 0x81 good Good store forwards
+name:segment_reg_loads type:mandatory default:0x00
+ 0x00 any Number of segment register loads
+name:simd_prefetch type:bitmask default:0x01
+ 0x01 prefetcht0 Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed
+ 0x06 sw_l2 Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed
+ 0x08 prefetchnta Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed
+name:data_tlb_misses type:bitmask default:0x07
+ 0x07 dtlb_miss Memory accesses that missed the DTLB
+ 0x05 dtlb_miss_ld DTLB misses due to load operations
+ 0x09 l0_dtlb_miss_ld L0_DTLB misses due to load operations
+ 0x06 dtlb_miss_st DTLB misses due to store operations
+name:page_walks type:bitmask default:0x03
+ 0x03 walks Number of page-walks executed
+ 0x03 cycles Duration of page-walks in core cycles
+name:x87_comp_ops_exe type:bitmask default:0x81
+ 0x01 s Floating point computational micro-ops executed
+ 0x81 ar Floating point computational micro-ops retired
+name:fp_assist type:mandatory default:0x81
+ 0x81 ar Floating point assists
+name:mul type:bitmask default:0x01
+ 0x01 s Multiply operations executed
+ 0x81 ar Multiply operations retired
+name:div type:bitmask default:0x01
+ 0x01 s Divide operations executed
+ 0x81 ar Divide operations retired
+name:l2_rqsts type:bitmask default:0x41
+ 0x41 i_state L2 cache demand requests from this core that missed the L2
+ 0x4F mesi L2 cache demand requests from this core
+name:cpu_clk_unhalted type:bitmask default:0x00
+ 0x00 core_p Core cycles when core is not halted
+ 0x01 bus Bus cycles when core is not halted
+ 0x02 no_other Bus cycles when core is active and the other is halted
+name:l1d_cache type:bitmask default:0x21
+ 0x21 ld L1 Cacheable Data Reads
+ 0x22 st L1 Cacheable Data Writes
+name:icache type:bitmask default:0x03
+ 0x03 accesses Instruction fetches
+ 0x02 misses Icache miss
+name:itlb type:bitmask default:0x04
+ 0x04 flush ITLB flushes
+ 0x02 misses ITLB misses
+name:macro_insts type:exclusive default:0x03
+ 0x02 cisc_decoded CISC macro instructions decoded
+ 0x03 all_decoded All Instructions decoded
+name:simd_uops_exec type:exclusive default:0x80
+ 0x00 s SIMD micro-ops executed (excluding stores)
+ 0x80 ar SIMD micro-ops retired (excluding stores)
+name:simd_sat_uop_exec type:bitmask default:0x00
+ 0x00 s SIMD saturated arithmetic micro-ops executed
+ 0x80 ar SIMD saturated arithmetic micro-ops retired
+name:simd_uop_type_exec type:bitmask default:0x01
+ 0x01 s SIMD packed multiply microops executed
+ 0x81 ar SIMD packed multiply microops retired
+ 0x02 s SIMD packed shift micro-ops executed
+ 0x82 ar SIMD packed shift micro-ops retired
+ 0x04 s SIMD pack micro-ops executed
+ 0x84 ar SIMD pack micro-ops retired
+ 0x08 s SIMD unpack micro-ops executed
+ 0x88 ar SIMD unpack micro-ops retired
+ 0x10 s SIMD packed logical microops executed
+ 0x90 ar SIMD packed logical microops retired
+ 0x20 s SIMD packed arithmetic micro-ops executed
+ 0xA0 ar SIMD packed arithmetic micro-ops retired
+name:uops_retired type:mandatory default:0x10
+ 0x10 any Micro-ops retired
+name:br_inst_retired type:bitmask default:0x00
+ 0x00 any Retired branch instructions
+ 0x01 pred_not_taken Retired branch instructions that were predicted not-taken
+ 0x02 mispred_not_taken Retired branch instructions that were mispredicted not-taken
+ 0x04 pred_taken Retired branch instructions that were predicted taken
+ 0x08 mispred_taken Retired branch instructions that were mispredicted taken
+ 0x0A mispred Retired mispredicted branch instructions (precise event)
+ 0x0C taken Retired taken branch instructions
+ 0x0F any1 Retired branch instructions
+name:cycles_int_masked type:bitmask default:0x01
+ 0x01 cycles_int_masked Cycles during which interrupts are disabled
+ 0x02 cycles_int_pending_and_masked Cycles during which interrupts are pending and disabled
+name:simd_inst_retired type:bitmask default:0x01
+ 0x01 packed_single Retired Streaming SIMD Extensions (SSE) packed-single instructions
+ 0x02 scalar_single Retired Streaming SIMD Extensions (SSE) scalar-single instructions
+ 0x04 packed_double Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions
+ 0x08 scalar_double Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions
+ 0x10 vector Retired Streaming SIMD Extensions 2 (SSE2) vector instructions
+ 0x1F any Retired Streaming SIMD instructions
+name:simd_comp_inst_retired type:bitmask default:0x01
+ 0x01 packed_single Retired computational Streaming SIMD Extensions (SSE) packed-single instructions
+ 0x02 scalar_single Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions
+ 0x04 packed_double Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions
+ 0x08 scalar_double Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions
+name:mem_load_retired type:bitmask default:0x01
+ 0x01 l2_hit Retired loads that hit the L2 cache (precise event)
+ 0x02 l2_miss Retired loads that miss the L2 cache (precise event)
+ 0x04 dtlb_miss Retired loads that miss the DTLB (precise event)
+name:thermal_trip type:mandatory default:0xc0
+ 0xc0 thermal_trip Number of thermal trips.
+# 18-11
+name:core type:bitmask default:0x180
+ 0x180 all All cores.
+ 0x080 this This Core.
+# 18-12
+name:agent type:bitmask default:0x00
+ 0x00 this This agent
+ 0x40 any Include any agents
+# 18-13
+name:prefetch type:bitmask default:0x60
+ 0x60 all All inclusive
+ 0x20 hw Hardware prefetch only
+ 0x00 exclude_hw Exclude hardware prefetch
+# 18-14
+name:mesi type:bitmask default:0x0f
+ 0x08 modified Counts modified state
+ 0x04 exclusive Counts exclusive state
+ 0x02 shared Counts shared state
+ 0x01 invalid Counts invalid state
diff --git a/events/i386/core/events b/events/i386/core/events
new file mode 100644
index 0000000..4f2fe80
--- /dev/null
+++ b/events/i386/core/events
@@ -0,0 +1,115 @@
+# Core Solo / Duo events
+#
+# Architectural events
+#
+event:0x3c counters:0,1 um:nonhlt minimum:6000 name:CPU_CLK_UNHALTED : Unhalted clock cycles
+event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0x2e counters:0,1 um:mesi minimum:6000 name:L2_RQSTS : number of L2 requests
+#
+# Model specific events
+#
+event:0x03 counters:0,1 um:zero minimum:500 name:LD_BLOCKS : number of store buffer blocks
+event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles
+event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
+event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
+event:0x07 counters:0,1 um:kni_prefetch minimum:500 name:EMON_KNI_PREF_DISPATCHED : number of SSE pre-fetch/weakly ordered insns retired
+event:0x10 counters:0 um:zero minimum:3000 name:FLOPS : number of computational FP operations executed
+event:0x11 counters:1 um:zero minimum:500 name:FP_ASSIST : number of FP exceptions handled by microcode
+event:0x12 counters:1 um:zero minimum:1000 name:MUL : number of multiplies
+event:0x13 counters:1 um:zero minimum:500 name:DIV : number of divides
+event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
+event:0x21 counters:0,1 um:zero minimum:500 name:L2_ADS : number of L2 address strobes
+event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
+event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
+event:0x24 counters:0,1 um:zero minimum:500 name:L2_LINES_IN : number of allocated lines in L2
+event:0x25 counters:0,1 um:zero minimum:500 name:L2_M_LINES_INM : number of modified lines allocated in L2
+event:0x26 counters:0,1 um:zero minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
+event:0x27 counters:0,1 um:zero minimum:500 name:L2_M_LINES_OUTM : number of modified lines removed from L2
+event:0x28 counters:0,1 um:mesi minimum:500 name:L2_IFETCH : number of L2 instruction fetches
+event:0x29 counters:0,1 um:mesi minimum:500 name:L2_LD : number of L2 data loads
+event:0x2a counters:0,1 um:mesi minimum:500 name:L2_ST : number of L2 data stores
+event:0x30 counters:0,1 um:mesi minimum:500 name:L2_REJECT_CYCLES : Cycles L2 is busy and rejecting new requests
+event:0x32 counters:0,1 um:mesi minimum:500 name:L2_NO_REQUEST_CYCLES : Cycles there is no request to access L2
+event:0x3a counters:0,1 um:est_trans minimum:500 name:EST_TRANS_ALL : Intel(tm) Enhanced SpeedStep(r) Technology transitions
+event:0x3b counters:0,1 um:xc0 minimum:500 name:THERMAL_TRIP : Duration in a thremal trip based on the current core clock
+event:0x40 counters:0,1 um:mesi minimum:500 name:DCACHE_CACHE_LD : L1 cacheable data read operations
+event:0x41 counters:0,1 um:mesi minimum:500 name:DCACHE_CACHE_ST : L1 cacheable data write operations
+event:0x42 counters:0,1 um:mesi minimum:500 name:DCACHE_CACHE_LOCK : L1 cacheable lock read operations to invalid state
+event:0x43 counters:0,1 um:one minimum:500 name:DATA_MEM_REFS : all L1 memory references, cachable and non
+event:0x44 counters:0,1 um:two minimum:500 name:DATA_MEM_CACHE_REFS : L1 data cacheable read and write operations
+event:0x45 counters:0,1 um:x0f minimum:500 name:DCACHE_REPL : L1 data cache line replacements
+event:0x46 counters:0,1 um:zero minimum:500 name:DCACHE_M_REPL : L1 data M-state cache line allocated
+event:0x47 counters:0,1 um:zero minimum:500 name:DCACHE_M_EVICT : L1 data M-state cache line evicted
+event:0x48 counters:0,1 um:dc_pend_miss minimum:500 name:DCACHE_PEND_MISS : Weighted cycles of L1 miss outstanding
+event:0x49 counters:0,1 um:zero minimum:500 name:DTLB_MISS : Data references that missed TLB
+event:0x4b counters:0,1 um:sse_miss minimum:500 name:SSE_PREF_MISS : SSE instructions that missed all caches
+event:0x4f counters:0,1 um:zero minimum:500 name:L1_PREF_REQ : L1 prefetch requests due to DCU cache misses
+#
+event:0x60 counters:0,1 um:zero minimum:500 name:BUS_REQ_OUTSTANDING : weighted number of outstanding bus requests
+event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : External bus cycles this processor is driving BNR pin
+event:0x62 counters:0,1 um:zero minimum:500 name:BUS_DRDY_CLOCKS : External bus cycles DRDY is asserted
+event:0x63 counters:0,1 um:zero minimum:500 name:BUS_LOCK_CLOCKS : External bus cycles LOCK is asserted
+event:0x64 counters:0,1 um:x40 minimum:500 name:BUS_DATA_RCV : External bus cycles this processor is receiving data
+event:0x65 counters:0,1 um:zero minimum:500 name:BUS_TRAN_BRD : number of burst read transactions
+event:0x66 counters:0,1 um:zero minimum:500 name:BUS_TRAN_RFO : number of completed read for ownership transactions
+event:0x67 counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_WB : number of completed writeback transactions
+event:0x68 counters:0,1 um:zero minimum:500 name:BUS_TRAN_IFETCH : number of completed instruction fetch transactions
+event:0x69 counters:0,1 um:zero minimum:500 name:BUS_TRAN_INVAL : number of completed invalidate transactions
+event:0x6a counters:0,1 um:zero minimum:500 name:BUS_TRAN_PWR : number of completed partial write transactions
+event:0x6b counters:0,1 um:zero minimum:500 name:BUS_TRANS_P : number of completed partial transactions
+event:0x6c counters:0,1 um:zero minimum:500 name:BUS_TRANS_IO : number of completed I/O transactions
+event:0x6d counters:0,1 um:x20 minimum:500 name:BUS_TRANS_DEF : number of completed defer transactions
+event:0x6e counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_BURST : number of completed burst transactions
+event:0x6f counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_MEM : number of completed memory transactions
+event:0x70 counters:0,1 um:xc0 minimum:500 name:BUS_TRAN_ANY : number of any completed bus transactions
+event:0x77 counters:0,1 um:zero minimum:500 name:BUS_SNOOPS : External bus cycles
+event:0x78 counters:0,1 um:one minimum:500 name:DCU_SNOOP_TO_SHARE : DCU snoops to share-state L1 cache line due to L1 misses
+event:0x7d counters:0,1 um:zero minimum:500 name:BUS_NOT_IN_USE : Number of cycles there is no transaction from the core
+event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : Number of bus cycles during bus snoop stall
+event:0x80 counters:0,1 um:zero minimum:500 name:ICACHE_READS : number of instruction fetches
+event:0x81 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : number of instruction fetch misses
+event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
+event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
+event:0x88 counters:0,1 um:zero minimum:3000 name:BR_INST_EXEC : Branch instructions executed (not necessarily retired)
+event:0x89 counters:0,1 um:zero minimum:3000 name:BR_MISSP_EXEC : Branch instructions executed that were mispredicted at execution
+event:0x8a counters:0,1 um:zero minimum:3000 name:BR_BAC_MISSP_EXEC : Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x8b counters:0,1 um:zero minimum:3000 name:BR_CND_EXEC : Conditional Branch instructions executed
+event:0x8c counters:0,1 um:zero minimum:3000 name:BR_CND_MISSP_EXEC : Conditional Branch instructions executed that were mispredicted
+event:0x8d counters:0,1 um:zero minimum:3000 name:BR_IND_EXEC : Indirect Branch instructions executed
+event:0x8e counters:0,1 um:zero minimum:3000 name:BR_IND_MISSP_EXEC : Indirect Branch instructions executed that were mispredicted
+event:0x8f counters:0,1 um:zero minimum:3000 name:BR_RET_EXEC : Return Branch instructions executed
+event:0x90 counters:0,1 um:zero minimum:3000 name:BR_RET_MISSP_EXEC : Return Branch instructions executed that were mispredicted at Execution
+event:0x91 counters:0,1 um:zero minimum:3000 name:BR_RET_BAC_MISSP_EXEC :Return Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x92 counters:0,1 um:zero minimum:3000 name:BR_CALL_EXEC : CALL instruction executed
+event:0x93 counters:0,1 um:zero minimum:3000 name:BR_CALL_MISSP_EXEC : CALL instruction executed and miss predicted
+event:0x94 counters:0,1 um:zero minimum:3000 name:BR_IND_CALL_EXEC : Indirect CALL instruction executed
+event:0xa2 counters:0,1 um:zero minimum:500 name:RESOURCE_STALLS : cycles during resource related stalls
+event:0xb0 counters:0,1 um:zero minimum:500 name:MMX_INSTR_EXEC : number of MMX instructions executed (not MOVQ and MOVD)
+event:0xb1 counters:0,1 um:zero minimum:3000 name:SIMD_SAT_INSTR_EXEC : number of SIMD saturating instructions executed
+event:0xb3 counters:0,1 um:mmx_instr_type_exec minimum:3000 name:MMX_INSTR_TYPE_EXEC : number of MMX packing instructions
+event:0xc1 counters:0 um:zero minimum:3000 name:COMP_FLOP_RET : number of computational FP operations retired
+event:0xc2 counters:0,1 um:zero minimum:6000 name:UOPS_RETIRED : number of UOPs retired
+event:0xc3 counters:0,1 um:zero minimum:500 name:SMC_DETECTED : number of times self-modifying code condition is detected
+event:0xc4 counters:0,1 um:zero minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired
+event:0xc6 counters:0,1 um:zero minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled
+event:0xc7 counters:0,1 um:zero minimum:500 name:CYCLES_INT_PENDING_AND_MASKED : cycles interrupts are disabled with pending interrupts
+event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RX : number of hardware interrupts received
+event:0xc9 counters:0,1 um:zero minimum:500 name:BR_TAKEN_RETIRED : number of taken branches retired
+event:0xca counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_TAKEN_RET : number of taken mispredictions branches retired
+event:0xcc counters:0,1 um:mmx_trans minimum:3000 name:FP_MMX_TRANS : MMX-floating point transitions
+event:0xcd counters:0,1 um:zero minimum:500 name:MMX_ASSIST : number of EMMS instructions executed
+event:0xce counters:0,1 um:zero minimum:3000 name:MMX_INSTR_RET : number of MMX instructions retired
+event:0xd0 counters:0,1 um:zero minimum:6000 name:INST_DECODED : number of instructions decoded
+event:0xd7 counters:0,1 um:zero minimum:3000 name:ESP_UOPS : Number of ESP folding instructions decoded
+event:0xd8 counters:0,1 um:sse_sse2_inst_retired minimum:3000 name:EMON_SSE_SSE2_INST_RETIRED : Streaming SIMD Extensions Instructions Retired
+event:0xd9 counters:0,1 um:sse_sse2_inst_retired minimum:3000 name:EMON_SSE_SSE2_COMP_INST_RETIRED : Computational SSE Instructions Retired
+event:0xda counters:0,1 um:fused minimum:3000 name:EMON_FUSED_UOPS_RET : Number of retired fused micro-ops
+event:0xdb counters:0,1 um:zero minimum:3000 name:EMON_UNFUSION : Number of unfusion events in the ROB, happened on a FP exception to a fused uOp
+event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded
+event:0xe2 counters:0,1 um:zero minimum:500 name:BTB_MISSES : number of branches that miss the BTB
+event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches
+event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted
+event:0xf0 counters:0,1 um:zero minimum:3000 name:EMON_PREF_RQSTS_UP : Number of upward prefetches issued
+event:0xf8 counters:0,1 um:zero minimum:3000 name:EMON_PREF_RQSTS_DN : Number of downward prefetches issued
diff --git a/events/i386/core/unit_masks b/events/i386/core/unit_masks
new file mode 100644
index 0000000..28da01e
--- /dev/null
+++ b/events/i386/core/unit_masks
@@ -0,0 +1,67 @@
+# Core Solo / Core Duo possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:one type:mandatory default:0x1
+ 0x1 No unit mask
+name:two type:mandatory default:0x2
+ 0x2 No unit mask
+name:x0f type:mandatory default:0xf
+ 0xf No unit mask
+name:x20 type:mandatory default:0x20
+ 0x20 No unit mask
+name:x40 type:mandatory default:0x40
+ 0x40 No unit mask
+name:xc0 type:mandatory default:0xc0
+ 0xc0 No unit mask
+name:nonhlt type:exclusive default:0x0
+ 0x0 Unhalted core cycles
+ 0x1 Unhalted bus cycles
+ 0x2 Unhalted bus cycles of this core while the other core is halted
+name:mesi type:bitmask default:0x0f
+ 0x08 (M)odified cache state
+ 0x04 (E)xclusive cache state
+ 0x02 (S)hared cache state
+ 0x01 (I)nvalid cache state
+ 0x0f All cache states
+ 0x10 HW prefetched line only
+ 0x20 all prefetched line w/o regarding mask 0x10.
+name:est_trans type:exclusive default:0x00
+ 0x00 any transitions
+ 0x10 Intel(tm) Enhanced SpeedStep(r) Technology frequency transitions
+ 0x20 any transactions
+name:kni_prefetch type:exclusive default:0x0
+ 0x00 prefetch NTA
+ 0x01 prefetch T1
+ 0x02 prefetch T2
+ 0x03 weakly-ordered stores
+# this bitmask can seems weirds but is correct, note there is no way to only
+# count scalar SIMD instructions
+name:sse_sse2_inst_retired type:exclusive default:0x0
+ 0x00 SSE Packed Single
+ 0x01 SSE Scalar-Single
+ 0x02 SSE2 Packed-Double
+ 0x03 SSE2 Scalar-Double
+name:mmx_instr_type_exec type:bitmask default:0x3f
+ 0x01 MMX packed multiplies
+ 0x02 MMX packed shifts
+ 0x04 MMX pack operations
+ 0x08 MMX unpack operations
+ 0x10 MMX packed logical
+ 0x20 MMX packed arithmetic
+ 0x3f all of the above
+name:mmx_trans type:exclusive default:0x0
+ 0x00 MMX->float operations
+ 0x01 float->MMX operations
+name:fused type:exclusive default:0x0
+ 0x00 All fused micro-ops
+ 0x01 Only load+Op micro-ops
+ 0x02 Only std+sta micro-ops
+name:dc_pend_miss type:exclusive default:0x0
+ 0x00 Weighted cycles
+ 0x01 Duration of cycles
+name:sse_miss type:exclusive default:0x0
+ 0x00 PREFETCHNTA
+ 0x01 PREFETCHT1
+ 0x02 PREFETCHT2
+ 0x03 SSE streaming store instructions
diff --git a/events/i386/core_2/events b/events/i386/core_2/events
new file mode 100644
index 0000000..d7c2ffd
--- /dev/null
+++ b/events/i386/core_2/events
@@ -0,0 +1,137 @@
+# Core 2 events
+#
+# Architectural events
+#
+event:0x3c counters:0,1 um:nonhlt minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
+event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED_ANY_P : number of instructions retired
+event:0x2e counters:0,1 um:core_prefetch_mesi minimum:500 name:L2_RQSTS : number of L2 cache requests
+event:0x2e counters:0,1 um:x41 minimum:6000 name:LLC_MISSES : L2 cache demand requests from this core that missed the L2
+event:0x2e counters:0,1 um:x4f minimum:6000 name:LLC_REFS : L2 cache demand requests from this core
+#
+# Model specific events
+#
+event:0x03 counters:0,1 um:load_block minimum:500 name:LOAD_BLOCK : events pertaining to loads
+event:0x04 counters:0,1 um:store_block minimum:500 name:STORE_BLOCK : events pertaining to stores
+event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
+event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
+event:0x07 counters:0,1 um:sse_prefetch minimum:500 name:SSE_PRE_EXEC : number of SSE pre-fetch/weakly ordered insns retired
+event:0x08 counters:0,1 um:dtlb_miss minimum:500 name:DTLB_MISSES : DTLB miss events
+event:0x09 counters:0,1 um:memory_dis minimum:1000 name:MEMORY_DISAMBIGUATION : Memory disambiguation reset cycles.
+event:0x0c counters:0,1 um:page_walks minimum:500 name:PAGE_WALKS : Page table walk events
+event:0x10 counters:0,1 um:zero minimum:3000 name:FLOPS : number of FP computational micro-ops executed
+event:0x11 counters:0,1 um:zero minimum:500 name:FP_ASSIST : number of FP assists
+event:0x12 counters:0,1 um:zero minimum:1000 name:MUL : number of multiplies
+event:0x13 counters:0,1 um:zero minimum:500 name:DIV : number of divides
+event:0x14 counters:0,1 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
+event:0x18 counters:0,1 um:zero minimum:1000 name:IDLE_DURING_DIV : cycles divider is busy and all other execution units are idle.
+event:0x19 counters:0,1 um:delayed_bypass minimum:1000 name:DELAYED_BYPASS : Delayed bypass events
+event:0x21 counters:0,1 um:core minimum:500 name:L2_ADS : Cycles the L2 address bus is in use.
+event:0x23 counters:0,1 um:core minimum:500 name:L2_DBUS_BUSY_RD : Cycles the L2 transfers data to the core.
+event:0x24 counters:0,1 um:core_prefetch minimum:500 name:L2_LINES_IN : number of allocated lines in L2
+event:0x25 counters:0,1 um:core minimum:500 name:L2_M_LINES_IN : number of modified lines allocated in L2
+event:0x26 counters:0,1 um:core_prefetch minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
+event:0x27 counters:0,1 um:core_prefetch minimum:500 name:L2_M_LINES_OUT : number of modified lines removed from L2
+event:0x28 counters:0,1 um:core_mesi minimum:500 name:L2_IFETCH : number of L2 cacheable instruction fetches
+event:0x29 counters:0,1 um:core_prefetch_mesi minimum:500 name:L2_LD : number of L2 data loads
+event:0x2a counters:0,1 um:core_mesi minimum:500 name:L2_ST : number of L2 data stores
+event:0x2b counters:0,1 um:core_mesi minimum:500 name:L2_LOCK : number of locked L2 data accesses
+event:0x30 counters:0,1 um:core_prefetch_mesi minimum:500 name:L2_REJECT_BUSQ : Rejected L2 cache requests
+event:0x32 counters:0,1 um:core minimum:500 name:L2_NO_REQ : Cycles no L2 cache requests are pending
+event:0x3a counters:0,1 um:zero minimum:500 name:EIST_TRANS_ALL : Intel(tm) Enhanced SpeedStep(r) Technology transitions
+event:0x3b counters:0,1 um:xc0 minimum:500 name:THERMAL_TRIP : Number of thermal trips
+event:0x40 counters:0,1 um:mesi minimum:500 name:L1D_CACHE_LD : L1 cacheable data read operations
+event:0x41 counters:0,1 um:mesi minimum:500 name:L1D_CACHE_ST : L1 cacheable data write operations
+event:0x42 counters:0,1 um:mesi minimum:500 name:L1D_CACHE_LOCK : L1 cacheable lock read operations
+event:0x42 counters:0,1 um:x10 minimum:500 name:L1D_CACHE_LOCK_DURATION : Duration of L1 data cacheable locked operations
+event:0x43 counters:0,1 um:x10 minimum:500 name:L1D_ALL_REF : All references to the L1 data cache
+event:0x43 counters:0,1 um:two minimum:500 name:L1D_ALL_CACHE_REF : L1 data cacheable reads and writes
+event:0x45 counters:0,1 um:x0f minimum:500 name:L1D_REPL : Cache lines allocated in the L1 data cache
+event:0x46 counters:0,1 um:zero minimum:500 name:L1D_M_REPL : Modified cache lines allocated in the L1 data cache
+event:0x47 counters:0,1 um:zero minimum:500 name:L1D_M_EVICT : Modified cache lines evicted from the L1 data cache
+event:0x48 counters:0,1 um:zero minimum:500 name:L1D_PEND_MISS : Total number of outstanding L1 data cache misses at any cycle
+event:0x49 counters:0,1 um:l1d_split minimum:500 name:L1D_SPLIT : Cache line split load/stores
+event:0x4b counters:0,1 um:sse_miss minimum:500 name:SSE_PREF_MISS : SSE instructions that missed all caches
+event:0x4c counters:0,1 um:zero minimum:500 name:LOAD_HIT_PRE : Load operations conflicting with a software prefetch to the same address
+event:0x4e counters:0,1 um:x10 minimum:500 name:L1D_PREFETCH : L1 data cache prefetch requests
+#
+event:0x60 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_REQ_OUTSTANDING : Outstanding cacheable data read bus requests duration
+event:0x61 counters:0,1 um:bus_agents minimum:500 name:BUS_BNR_DRV : Number of Bus Not Ready signals asserted
+event:0x62 counters:0,1 um:bus_agents minimum:500 name:BUS_DRDY_CLOCKS : Bus cycles when data is sent on the bus
+event:0x63 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_LOCK_CLOCKS : Bus cycles when a LOCK signal is asserted
+event:0x64 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_DATA_RCV : Bus cycles while processor receives data
+event:0x65 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_BRD : Burst read bus transactions
+event:0x66 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_RFO : number of completed read for ownership transactions
+event:0x67 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_WB : number of explicit writeback bus transactions
+event:0x68 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_IFETCH : number of instruction fetch transactions
+event:0x69 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_INVAL : number of invalidate transactions
+event:0x6a counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_PWR : number of partial write bus transactions
+event:0x6b counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRANS_P : number of partial bus transactions
+event:0x6c counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRANS_IO : number of I/O bus transactions
+event:0x6d counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRANS_DEF : number of completed defer transactions
+event:0x6e counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_BURST : number of completed burst transactions
+event:0x6f counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_MEM : number of completed memory transactions
+event:0x70 counters:0,1 um:core_and_bus_agents minimum:500 name:BUS_TRAN_ANY : number of any completed bus transactions
+event:0x77 counters:0,1 um:bus_agents_and_snoop minimum:500 name:EXT_SNOOP : External snoops
+event:0x78 counters:0,1 um:core_and_snoop minimum:500 name:CMP_SNOOP : L1 data cache is snooped by other core
+event:0x7a counters:0,1 um:bus_agents minimum:500 name:BUS_HIT_DRV : HIT signal asserted
+event:0x7b counters:0,1 um:bus_agents minimum:500 name:BUS_HITM_DRV : HITM signal asserted
+event:0x7d counters:0,1 um:core minimum:500 name:BUSQ_EMPTY : Bus queue is empty
+event:0x7e counters:0,1 um:core_and_bus_agents minimum:500 name:SNOOP_STALL_DRV : Bus stalled for snoops
+event:0x7f counters:0,1 um:core minimum:500 name:BUS_IO_WAIT : IO requests waiting in the bus queue
+event:0x80 counters:0,1 um:zero minimum:500 name:L1I_READS : number of instruction fetches
+event:0x81 counters:0,1 um:zero minimum:500 name:L1I_MISSES : number of instruction fetch misses
+event:0x82 counters:0,1 um:itlb_miss minimum:500 name:ITLB : number of ITLB misses
+event:0x83 counters:0,1 um:two minimum:500 name:INST_QUEUE_FULL : cycles during which the instruction queue is full
+event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
+event:0x88 counters:0,1 um:zero minimum:3000 name:BR_INST_EXEC : Branch instructions executed (not necessarily retired)
+event:0x89 counters:0,1 um:zero minimum:3000 name:BR_MISSP_EXEC : Branch instructions executed that were mispredicted at execution
+event:0x8a counters:0,1 um:zero minimum:3000 name:BR_BAC_MISSP_EXEC : Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x8b counters:0,1 um:zero minimum:3000 name:BR_CND_EXEC : Conditional Branch instructions executed
+event:0x8c counters:0,1 um:zero minimum:3000 name:BR_CND_MISSP_EXEC : Conditional Branch instructions executed that were mispredicted
+event:0x8d counters:0,1 um:zero minimum:3000 name:BR_IND_EXEC : Indirect Branch instructions executed
+event:0x8e counters:0,1 um:zero minimum:3000 name:BR_IND_MISSP_EXEC : Indirect Branch instructions executed that were mispredicted
+event:0x8f counters:0,1 um:zero minimum:3000 name:BR_RET_EXEC : Return Branch instructions executed
+event:0x90 counters:0,1 um:zero minimum:3000 name:BR_RET_MISSP_EXEC : Return Branch instructions executed that were mispredicted at Execution
+event:0x91 counters:0,1 um:zero minimum:3000 name:BR_RET_BAC_MISSP_EXEC :Return Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x92 counters:0,1 um:zero minimum:3000 name:BR_CALL_EXEC : CALL instruction executed
+event:0x93 counters:0,1 um:zero minimum:3000 name:BR_CALL_MISSP_EXEC : CALL instruction executed and miss predicted
+event:0x94 counters:0,1 um:zero minimum:3000 name:BR_IND_CALL_EXEC : Indirect CALL instruction executed
+event:0x97 counters:0,1 um:zero minimum:3000 name:BR_TKN_BUBBLE_1 : Branch predicted taken with bubble 1
+event:0x98 counters:0,1 um:zero minimum:3000 name:BR_TKN_BUBBLE_2 : Branch predicted taken with bubble 2
+event:0xa0 counters:0,1 um:zero minimum:1000 name:RS_UOPS_DISPATCHED : Micro-ops dispatched for execution
+# Set both the CMASK and INV fields to 1 -- which causes the counter to
+# increment on cycles in which fewer than 1 uop dispatches. i.e. stall cycles.
+# It's a bit of a hack, but passes through the oprofile infrastructure just
+# fine.
+event:0x18000a0 counters:0,1 um:zero minimum:1000 name:RS_UOPS_DISPATCHED_NONE : No Micro-ops dispatched for execution
+event:0xaa counters:0,1 um:macro_insts minimum:500 name:MACRO_INSTS : instructions decoded
+event:0xab counters:0,1 um:esp minimum:500 name:ESP : ESP register events
+event:0xb0 counters:0,1 um:zero minimum:500 name:SIMD_UOPS_EXEC : SIMD micro-ops executed (excluding stores)
+event:0xb1 counters:0,1 um:zero minimum:3000 name:SIMD_SAT_UOP_EXEC : number of SIMD saturating instructions executed
+event:0xb3 counters:0,1 um:simd_instr_type_exec minimum:3000 name:SIMD_UOP_TYPE_EXEC : number of SIMD packing instructions
+event:0xc0 counters:0,1 um:inst_retired minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0xc1 counters:0,1 um:x87_ops_retired minimum:500 name:X87_OPS_RETIRED : number of computational FP operations retired
+event:0xc2 counters:0,1 um:uops_retired minimum:6000 name:UOPS_RETIRED : number of UOPs retired
+event:0xc3 counters:0,1 um:machine_nukes minimum:500 name:MACHINE_NUKES_SMC : number of pipeline flushing events
+event:0xc4 counters:0,1 um:br_inst_retired minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
+event:0xc6 counters:0,1 um:cycles_int_masked minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled
+event:0xc7 counters:0,1 um:simd_inst_retired minimum:500 name:SIMD_INST_RETIRED : SSE/SSE2 instructions retired
+event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RCV : number of hardware interrupts received
+event:0xc9 counters:0 um:zero minimum:500 name:ITLB_MISS_RETIRED : Retired instructions that missed the ITLB
+event:0xca counters:0,1 um:simd_comp_inst_retired minimum:500 name:SIMD_COMP_INST_RETIRED : Retired computational SSE/SSE2 instructions
+event:0xcb counters:0 um:mem_load_retired minimum:500 name:MEM_LOAD_RETIRED : Retired loads
+event:0xcc counters:0,1 um:mmx_trans minimum:3000 name:FP_MMX_TRANS : MMX-floating point transitions
+event:0xcd counters:0,1 um:zero minimum:500 name:MMX_ASSIST : number of EMMS instructions executed
+event:0xce counters:0,1 um:zero minimum:500 name:SIMD_INSTR_RET : number of SIMD instructions retired
+event:0xcf counters:0,1 um:zero minimum:500 name:SIMD_SAT_INSTR_RET : number of saturated arithmetic instructions retired
+event:0xd2 counters:0,1 um:rat_stalls minimum:6000 name:RAT_STALLS : Partial register stall cycles
+event:0xd4 counters:0,1 um:seg_regs minimum:500 name:SEG_RENAME_STALLS : Segment rename stalls
+event:0xd5 counters:0,1 um:seg_regs minimum:500 name:SEG_RENAMES : Segment renames
+event:0xdc counters:0,1 um:resource_stalls minimum:3000 name:RESOURCE_STALLS : Cycles during which resource stalls occur
+event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded
+event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches
+event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted
+event:0xf0 counters:0,1 um:zero minimum:3000 name:PREF_RQSTS_UP : Number of upward prefetches issued
+event:0xf8 counters:0,1 um:zero minimum:3000 name:PREF_RQSTS_DN : Number of downward prefetches issued
diff --git a/events/i386/core_2/unit_masks b/events/i386/core_2/unit_masks
new file mode 100644
index 0000000..d528f17
--- /dev/null
+++ b/events/i386/core_2/unit_masks
@@ -0,0 +1,195 @@
+# Core 2 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+#name:one type:mandatory default:0x1
+# 0x1 No unit mask
+name:two type:mandatory default:0x2
+ 0x2 No unit mask
+name:x0f type:mandatory default:0xf
+ 0xf No unit mask
+name:x10 type:mandatory default:0x10
+ 0x10 No unit mask
+#name:x20 type:mandatory default:0x20
+# 0x20 No unit mask
+#name:x40 type:mandatory default:0x40
+# 0x40 No unit mask
+name:x41 type:mandatory default:0x41
+ 0x41 No unit mask
+name:x4f type:mandatory default:0x4f
+ 0x4f No unit mask
+name:xc0 type:mandatory default:0xc0
+ 0xc0 No unit mask
+name:nonhlt type:exclusive default:0x0
+ 0x0 Unhalted core cycles
+ 0x1 Unhalted bus cycles
+ 0x2 Unhalted bus cycles of this core while the other core is halted
+name:mesi type:bitmask default:0x0f
+ 0x08 (M)ESI: Modified
+ 0x04 M(E)SI: Exclusive
+ 0x02 ME(S)I: Shared
+ 0x01 MES(I): Invalid
+name:sse_prefetch type:exclusive default:0x0
+ 0x00 prefetch NTA instructions executed.
+ 0x01 prefetch T1 instructions executed.
+ 0x02 prefetch T1 and T2 instructions executed.
+ 0x03 SSE weakly-ordered stores
+name:simd_instr_type_exec type:bitmask default:0x3f
+ 0x01 SIMD packed multiplies
+ 0x02 SIMD packed shifts
+ 0x04 SIMD pack operations
+ 0x08 SIMD unpack operations
+ 0x10 SIMD packed logical
+ 0x20 SIMD packed arithmetic
+ 0x3f all of the above
+name:mmx_trans type:bitmask default:0x3
+ 0x01 float->MMX transitions
+ 0x02 MMX->float transitions
+name:sse_miss type:exclusive default:0x0
+ 0x00 PREFETCHNTA
+ 0x01 PREFETCHT0
+ 0x02 PREFETCHT1/PREFETCHT2
+name:load_block type:bitmask default:0x3e
+ 0x02 STA Loads blocked by a preceding store with unknown address.
+ 0x04 STD Loads blocked by a preceding store with unknown data.
+ 0x08 OVERLAP_STORE Loads that partially overlap an earlier store, or 4K aliased with a previous store.
+ 0x10 UNTIL_RETIRE Loads blocked until retirement.
+ 0x20 L1D Loads blocked by the L1 data cache.
+name:store_block type:bitmask default:0x0b
+ 0x01 SB_DRAIN_CYCLES Cycles while stores are blocked due to store buffer drain.
+ 0x02 ORDER Cycles while store is waiting for a preceding store to be globally observed.
+ 0x08 NOOP A store is blocked due to a conflict with an external or internal snoop.
+name:dtlb_miss type:bitmask default:0x0f
+ 0x01 ANY Memory accesses that missed the DTLB.
+ 0x02 MISS_LD DTLB misses due to load operations.
+ 0x04 L0_MISS_LD L0 DTLB misses due to load operations.
+ 0x08 MISS_ST TLB misses due to store operations.
+name:memory_dis type:exclusive default:0x01
+ 0x01 RESET Memory disambiguation reset cycles.
+ 0x02 SUCCESS Number of loads that were successfully disambiguated.
+name:page_walks type:exclusive default:0x02
+ 0x01 COUNT Number of page-walks executed.
+ 0x02 CYCLES Duration of page-walks in core cycles.
+name:delayed_bypass type:exclusive default:0x00
+ 0x00 FP Delayed bypass to FP operation.
+ 0x01 SIMD Delayed bypass to SIMD operation.
+ 0x02 LOAD Delayed bypass to load operation.
+name:core type:exclusive default:0x40
+ 0xc0 All cores
+ 0x40 This core
+name:core_prefetch type:bitmask default:0x70
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x30 prefetch: all inclusive
+ 0x10 prefetch: Hardware prefetch only
+ 0x00 prefetch: exclude hardware prefetch
+name:core_mesi type:bitmask default:0x4f
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x08 (M)ESI: Modified
+ 0x04 M(E)SI: Exclusive
+ 0x02 ME(S)I: Shared
+ 0x01 MES(I): Invalid
+name:core_prefetch_mesi type:bitmask default:0x7f
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x30 prefetch: all inclusive
+ 0x10 prefetch: Hardware prefetch only
+ 0x00 prefetch: exclude hardware prefetch
+ 0x08 (M)ESI: Modified
+ 0x04 M(E)SI: Exclusive
+ 0x02 ME(S)I: Shared
+ 0x01 MES(I): Invalid
+name:l1d_split type:exclusive default:0x1
+ 0x1 split loads
+ 0x2 split stores
+name:bus_agents type:exclusive default:0x00
+ 0x00 this agent
+ 0x20 include all agents
+name:core_and_bus_agents type:bitmask default:0x40
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x00 bus: this agent
+ 0x20 bus: include all agents
+name:bus_agents_and_snoop type:bitmask default:0x0b
+ 0x00 bus: this agent
+ 0x20 bus: include all agents
+ 0x08 snoop: HITM snoops
+ 0x02 snoop: HIT snoops
+ 0x01 snoop: CLEAN snoops
+name:core_and_snoop type:bitmask default:0x40
+ 0xc0 core: all cores
+ 0x40 core: this core
+ 0x01 snoop: CMP2I snoops
+ 0x02 snoop: CMP2S snoops
+name:itlb_miss type:bitmask default:0x12
+ 0x02 ITLB small page misses
+ 0x10 ITLB large page misses
+ 0x40 ITLB flushes
+name:macro_insts type:bitmask default:0x09
+ 0x01 Instructions decoded
+ 0x08 CISC Instructions decoded
+name:esp type:bitmask default:0x01
+ 0x01 ESP register content synchronizations
+ 0x02 ESP register automatic additions
+name:inst_retired type:bitmask default:0x00
+ 0x00 Any
+ 0x01 Loads
+ 0x02 Stores
+ 0x04 Other
+name:x87_ops_retired type:exclusive default:0xfe
+ 0x01 FXCH instructions retired
+ 0xfe Retired floating-point computational operations (precise)
+name:uops_retired type:bitmask default:0x0f
+ 0x01 Fused load+op or load+indirect branch retired
+ 0x02 Fused store address + data retired
+ 0x04 Retired instruction pairs fused into one micro-op
+ 0x07 Fused micro-ops retired
+ 0x08 Non-fused micro-ops retired
+ 0x0f Micro-ops retired
+name:machine_nukes type:bitmask default:0x05
+ 0x01 Self-Modifying Code detected
+ 0x04 Execution pipeline restart due to memory ordering conflict or memory disambiguation misprediction
+name:br_inst_retired type:bitmask default:0xa
+ 0x01 predicted not-taken
+ 0x02 mispredicted not-taken
+ 0x04 predicted taken
+ 0x08 mispredicted taken
+name:cycles_int_masked type:exclusive default:0x02
+ 0x01 Interrupts disabled
+ 0x02 Interrupts pending and disabled
+name:simd_inst_retired type:bitmask default:0x1f
+ 0x01 Retired SSE packed-single instructions
+ 0x02 Retired SSE scalar-single instructions
+ 0x04 Retired SSE2 packed-double instructions
+ 0x08 Retired SSE2 scalar-double instructions
+ 0x10 Retired SSE2 vector integer instructions
+ 0x1f Retired Streaming SIMD instructions (precise event)
+name:simd_comp_inst_retired type:bitmask default:0xf
+ 0x01 Retired computational SSE packed-single instructions
+ 0x02 Retired computational SSE scalar-single instructions
+ 0x04 Retired computational SSE2 packed-double instructions
+ 0x08 Retired computational SSE2 scalar-double instructions
+name:mem_load_retired type:exclusive default:0x01
+ 0x01 Retired loads that miss the L1 data cache (precise event)
+ 0x02 L1 data cache line missed by retired loads (precise event)
+ 0x04 Retired loads that miss the L2 cache (precise event)
+ 0x08 L2 cache line missed by retired loads (precise event)
+ 0x10 Retired loads that miss the DTLB (precise event)
+name:rat_stalls type:bitmask default:0xf
+ 0x01 ROB read port
+ 0x02 Partial register
+ 0x04 Flag
+ 0x08 FPU status word
+ 0x0f All RAT
+name:seg_regs type:bitmask default:0x0f
+ 0x01 ES
+ 0x02 DS
+ 0x04 FS
+ 0x08 GS
+name:resource_stalls type:bitmask default:0x0f
+ 0x01 when the ROB is full
+ 0x02 during which the RS is full
+ 0x04 during which the pipeline has exceeded the load or store limit or is waiting to commit all stores
+ 0x08 due to FPU control word write
+ 0x10 due to branch misprediction
diff --git a/events/i386/core_i7/events b/events/i386/core_i7/events
new file mode 100644
index 0000000..ab53422
--- /dev/null
+++ b/events/i386/core_i7/events
@@ -0,0 +1,6 @@
+#
+# Intel Core i7 "Bloomfield" / Xeon EP 75xx events
+# right now this is only the shared events included for the Nehalem core,
+# but later we'll add here the uncore events specific to this chip
+#
+include:i386/nehalem
diff --git a/events/i386/core_i7/unit_masks b/events/i386/core_i7/unit_masks
new file mode 100644
index 0000000..ffc35d3
--- /dev/null
+++ b/events/i386/core_i7/unit_masks
@@ -0,0 +1 @@
+include:i386/nehalem
diff --git a/events/i386/nehalem/events b/events/i386/nehalem/events
new file mode 100644
index 0000000..f3471f6
--- /dev/null
+++ b/events/i386/nehalem/events
@@ -0,0 +1,107 @@
+#
+# Intel "Nehalem" microarchitecture (Core i7; Xeon 75xx etc.) core events
+# the uncore (memory controller/QPI) events are in separate files because
+# they vary between implementations (right now they are not implemented
+# in oprofile)
+#
+# Note the minimum counts are not discovered experimentally and could be likely
+# lowered in many cases without ill effect.
+#
+event:0x3c counters:0,1,2,3 um:zero minimum:6000 name:CPU_CLK_UNHALTED : Clock cycles when not halted
+event:0x3c counters:0,1,2,2 um:one minimum:6000 name:UNHALTED_REFERENCE_CYCLES : Unhalted reference cycles
+event:0x2e counters:0,1,2,3 um:x41 minimum:6000 name:LLC_MISSES : Last level cache demand requests from this core that missed the LLC
+event:0x2e counters:0,1,2,3 um:x4f minimum:6000 name:LLC_REFS : Last level cache demand requests from this core
+event:0xc0 counters:0,1,2,3 um:inst_retired minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0xc4 counters:0,1,2,3 um:br_inst_retired minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1,2,3 um:br_misp_retired minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired (precise)
+#
+event:0x02 counters:0,1,2,3 um:sb_forward minimum:6000 name:SB_FORWARD : Counts the number of store forwards.
+event:0x03 counters:0,1,2,3 um:load_block minimum:6000 name:LOAD_BLOCK : Counts the number of loads blocked
+event:0x04 counters:0,1,2,3 um:sb_drain minimum:6000 name:SB_DRAIN : Counts the cycles of store buffer drains.
+event:0x05 counters:0,1,2,3 um:misalign_mem_ref minimum:6000 name:MISALIGN_MEM_REF : Counts the number of misaligned load references
+event:0x06 counters:0,1,2,3 um:store_blocks minimum:6000 name:STORE_BLOCKS : This event counts the number of load operations delayed caused by preceding stores.
+event:0x07 counters:0,1,2,3 um:one minimum:6000 name:PARTIAL_ADDRESS_ALIAS : Counts false dependency due to partial address aliasing
+event:0x08 counters:0,1,2,3 um:dtlb_load_misses minimum:6000 name:DTLB_LOAD_MISSES : Counts dtlb page walks
+event:0x09 counters:0,1,2,3 um:memory_disambiguration minimum:6000 name:MEMORY_DISAMBIGURATION : Counts memory disambiguration events
+event:0x0B counters:0,1,2,3 um:mem_inst_retired minimum:6000 name:MEM_INST_RETIRED : Counts the number of instructions with an architecturally-visible load/store retired on the architected path.
+event:0x0C counters:0,1,2,3 um:mem_store_retired minimum:6000 name:MEM_STORE_RETIRED : The event counts the number of retired stores that missed the DTLB. The DTLB miss is not counted if the store operation causes a fault. Does not count prefetches. Counts both primary and secondary misses to the TLB
+event:0x0E counters:0,1,2,3 um:uops_issued minimum:6000 name:UOPS_ISSUED : Counts the number of Uops issued by the Register Allocation Table to the Reservation Station, i.e. the UOPs issued from the front end to the back end.
+event:0x0F counters:0,1,2,3 um:mem_uncore_retired minimum:6000 name:MEM_UNCORE_RETIRED : Counts number of memory load instructions retired where the memory reference hit modified data in another core
+event:0x10 counters:0,1,2,3 um:fp_comp_ops_exe minimum:6000 name:FP_COMP_OPS_EXE : Counts the number of FP Computational Uops Executed.
+event:0x12 counters:0,1,2,3 um:simd_int_128 minimum:6000 name:SIMD_INT_128 : Counts number of 128 bit SIMD integer operations.
+event:0x13 counters:0,1,2,3 um:load_dispatch minimum:6000 name:LOAD_DISPATCH : Counts number of loads dispatched from the Reservation Station that bypass.
+event:0x14 counters:0,1,2,3 um:arith minimum:6000 name:ARITH : Counts division cycles and number of multiplies. Includes integer and FP, but excludes DPPS/MPSAD.
+event:0x17 counters:0,1,2,3 um:one minimum:6000 name:INST_QUEUE_WRITES : Counts the number of instructions written into the instruction queue every cycle.
+event:0x18 counters:0,1,2,3 um:inst_decoded minimum:6000 name:INST_DECODED : Counts number of instructions that require decoder 0 to be decoded. Usually, this means that the instruction maps to more than 1 uop
+event:0x19 counters:0,1,2,3 um:one minimum:6000 name:TWO_UOP_INSTS_DECODED : An instruction that generates two uops was decoded
+event:0x1D counters:0,1,2,3 um:hw_int minimum:100 name:HW_INT : Counts hardware interrupt events.
+event:0x1E counters:0,1,2,3 um:one minimum:6000 name:INST_QUEUE_WRITE_CYCLES : This event counts the number of cycles during which instructions are written to the instruction queue. Dividing this counter by the number of instructions written to the instruction queue (INST_QUEUE_WRITES) yields the average number of instructions decoded each cycle. If this number is less than four and the pipe stalls, this indicates that the decoder is failing to decode enough instructions per cycle to sustain the 4-wide pipeline.
+event:0x24 counters:0,1,2,3 um:l2_rqsts minimum:500 name:L2_RQSTS : Counts number of L2 data loads
+event:0x26 counters:0,1,2,3 um:l2_data_rqsts minimum:500 name:L2_DATA_RQSTS : More L2 data loads.
+event:0x27 counters:0,1,2,3 um:l2_write minimum:500 name:L2_WRITE : Counts number of L2 writes
+event:0x28 counters:0,1,2,3 um:l1d_wb_l2 minimum:500 name:L1D_WB_L2 : Counts number of L1 writebacks to the L2.
+event:0x2E counters:0,1,2,3 um:longest_lat_cache minimum:6000 name:LONGEST_LAT_CACHE : Count LLC cache reference latencies.
+event:0x3C counters:0,1,2,3 um:cpu_clk_unhalted minimum:6000 name:CPU_CLK_UNHALTED : Counts the number of thread cycles while the thread is not in a halt state.
+event:0x3D counters:0,1,2,3 um:one minimum:6000 name:UOPS_DECODED_DEC0 : Counts micro-ops decoded by decoder 0.
+event:0x40 counters:0,1 um:l1d_cache_ld minimum:6000 name:L1D_CACHE_LD : Counts L1 data cache read requests.
+event:0x41 counters:0,1 um:l1d_cache_st minimum:6000 name:L1D_CACHE_ST : Counts L1 data cache stores.
+event:0x42 counters:0,1 um:l1d_cache_lock minimum:6000 name:L1D_CACHE_LOCK : Counts retired load locks in the L1D cache.
+event:0x43 counters:0,1 um:l1d_all_ref minimum:6000 name:L1D_ALL_REF : Counts all references to the L1 data cache,
+event:0x49 counters:0,1,2,3 um:dtlb_misses minimum:6000 name:DTLB_MISSES : Counts the number of misses in the STLB
+event:0x4B counters:0,1,2,3 um:sse_mem_exec minimum:6000 name:SSE_MEM_EXEC : Counts number of SSE instructions which missed the L1 data cache.
+event:0x4C counters:0,1,2,3 um:one minimum:6000 name:LOAD_HIT_PRE : Counts load operations sent to the L1 data cache while a previous SSE prefetch instruction to the same cache line has started prefetching but has not yet finished.
+event:0x4D counters:0,1,2,3 um:one minimum:6000 name:SFENCE_CYCLES : Counts store fence cycles
+event:0x4E counters:0,1,2,3 um:l1d_prefetch minimum:6000 name:L1D_PREFETCH : Counts number of hardware prefetch requests.
+event:0x4F counters:0,1,2,3 um:ept minimum:6000 name:EPT : Counts Extended Page Directory Entry accesses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.
+event:0x51 counters:0,1 um:l1d minimum:6000 name:L1D : Counts the number of lines brought from/to the L1 data cache.
+event:0x52 counters:0,1,2,3 um:one minimum:6000 name:L1D_CACHE_PREFETCH_LOCK_FB_HIT : Counts the number of cacheable load lock speculated instructions accepted into the fill buffer.
+event:0x53 counters:0,1,2,3 um:one minimum:6000 name:L1D_CACHE_LOCK_FB_HIT : Counts the number of cacheable load lock speculated or retired instructions accepted into the fill buffer.
+event:0x60 counters:0,1,2,3 um:offcore_requests_outstanding minimum:6000 name:OFFCORE_REQUESTS_OUTSTANDING : Counts weighted cycles of offcore requests.
+event:0x63 counters:0,1 um:cache_lock_cycles minimum:6000 name:CACHE_LOCK_CYCLES : Cycle count during which the L1/L2 caches are locked. A lock is asserted when there is a locked memory access, due to uncacheable memory, a locked operation that spans two cache lines, or a page walk from an uncacheable page table.
+event:0x6C counters:0,1,2,3 um:one minimum:6000 name:IO_TRANSACTIONS : Counts the number of completed I/O transactions.
+event:0x80 counters:0,1,2,3 um:l1i minimum:6000 name:L1I : Counts L1i instruction cache accesses.
+event:0x81 counters:0,1,2,3 um:ifu_ivc minimum:6000 name:IFU_IVC : Instruction Fetch unit events
+event:0x82 counters:0,1,2,3 um:large_itlb minimum:6000 name:LARGE_ITLB : Counts number of large ITLB accesses
+event:0x83 counters:0,1,2,3 um:one minimum:6000 name:L1I_OPPORTUNISTIC_HITS : Opportunistic hits in streaming.
+event:0x85 counters:0,1,2,3 um:itlb_misses minimum:6000 name:ITLB_MISSES : Counts the number of ITLB misses in various variants
+event:0x87 counters:0,1,2,3 um:ild_stall minimum:6000 name:ILD_STALL : Cycles Instruction Length Decoder stalls
+event:0x88 counters:0,1,2,3 um:br_inst_exec minimum:6000 name:BR_INST_EXEC : Counts the number of near branch instructions executed, but not necessarily retired.
+event:0x89 counters:0,1,2,3 um:br_misp_exec minimum:6000 name:BR_MISP_EXEC : Counts the number of mispredicted conditional near branch instructions executed, but not necessarily retired.
+event:0xA2 counters:0,1,2,3 um:resource_stalls minimum:6000 name:RESOURCE_STALLS : Counts the number of Allocator resource related stalls. Includes register renaming buffer entries, memory buffer entries. In addition to resource related stalls, this event counts some other events. Includes stalls arising during branch misprediction recovery, such as if retirement of the mispredicted branch is delayed and stalls arising while store buffer is draining from synchronizing operations.
+event:0xA6 counters:0,1,2,3 um:one minimum:6000 name:MACRO_INSTS : Counts the number of instructions decoded that are macro-fused but not necessarily executed or retired.
+event:0xA7 counters:0,1,2,3 um:one minimum:6000 name:BACLEAR_FORCE_IQ : Counts number of times a BACLEAR was forced by the Instruction Queue. The IQ is also responsible for providing conditional branch prediciton direction based on a static scheme and dynamic data provided by the L2 Branch Prediction Unit. If the conditional branch target is not found in the Target Array and the IQ predicts that the branch is taken, then the IQ will force the Branch Address Calculator to issue a BACLEAR. Each BACLEAR asserted by the BAC generates approximately an 8 cycle bubble in the instruction fetch pipeline.
+event:0xA8 counters:0,1,2,3 um:one minimum:6000 name:LSD : Counts the number of micro-ops delivered by loop stream detector
+event:0xAE counters:0,1,2,3 um:one minimum:6000 name:ITLB_FLUSH : Counts the number of ITLB flushes
+event:0xB0 counters:0,1,2,3 um:offcore_requests minimum:6000 name:OFFCORE_REQUESTS : Counts number of offcore data requests.
+event:0xB1 counters:0,1,2,3 um:uops_executed minimum:6000 name:UOPS_EXECUTED : Counts number of Uops executed that were issued on various ports
+event:0xB2 counters:0,1,2,3 um:one minimum:6000 name:OFFCORE_REQUESTS_SQ_FULL : Counts number of cycles the SQ is full to handle off-core requests.
+event:0xB3 counters:0,1,2,3 um:snoopq_requests_outstanding minimum:6000 name:SNOOPQ_REQUESTS_OUTSTANDING : Counts weighted cycles of snoopq requests.
+event:0xB7 counters:0,1,2,3 um:one minimum:6000 name:OOF_CORE_RESPONSE_0 : Off-core Response Performance Monitoring in the Processor Core. Requires special setup.
+event:0xB8 counters:0,1,2,3 um:snoop_response minimum:6000 name:SNOOP_RESPONSE : Counts HIT snoop response sent by this thread in response to a snoop request.
+event:0xBA counters:0,1,2,3 um:pic_accesses minimum:6000 name:PIC_ACCESSES : Counts number of TPR accesses
+event:0xC2 counters:0,1,2,3 um:uops_retired minimum:6000 name:UOPS_RETIRED : Counts the number of micro-ops retired, (macro-fused=1, micro-fused=2, others=1; maximum count of 8 per cycle). Most instructions are composed of one or two microops. Some instructions are decoded into longer sequences such as repeat instructions, floating point transcendental instructions, and assists
+event:0xC3 counters:0,1,2,3 um:machine_clears minimum:6000 name:MACHINE_CLEARS : Counts the cycles machine clear is asserted.
+event:0xC7 counters:0,1,2,3 um:ssex_uops_retired minimum:6000 name:SSEX_UOPS_RETIRED : Counts SIMD packed single-precision floating point Uops retired.
+event:0xC8 counters:0,1,2,3 um:x20 minimum:6000 name:ITLB_MISS_RETIRED : Counts the number of retired instructions that missed the ITLB when the instruction was fetched.
+event:0xCB counters:0,1,2,3 um:mem_load_retired minimum:6000 name:MEM_LOAD_RETIRED : Counts number of retired loads.
+event:0xCC counters:0,1,2,3 um:fp_mmx_trans minimum:6000 name:FP_MMX_TRANS : Counts transitions between MMX and x87 state.
+event:0xD0 counters:0,1,2,3 um:macro_insts minimum:6000 name:MACRO_INSTS : Counts the number of instructions decoded, (but not necessarily executed or retired).
+event:0xD1 counters:0,1,2,3 um:uops_decoded minimum:6000 name:UOPS_DECODED : Counts the number of Uops decoded by various subsystems.
+event:0xD2 counters:0,1,2,3 um:rat_stalls minimum:6000 name:RAT_STALLS : Counts the number of cycles during which execution stalled due to several reason
+event:0xD4 counters:0,1,2,3 um:one minimum:6000 name:SEG_RENAME_STALLS : Counts the number of stall cycles due to the lack of renaming resources for the ES, DS, FS, and GS segment registers. If a segment is renamed but not retired and a second update to the same segment occurs, a stall occurs in the front-end of the pipeline until the renamed segment retires.
+event:0xD5 counters:0,1,2,3 um:one minimum:6000 name:ES_REG_RENAMES : Counts the number of times the ES segment register is renamed.
+event:0xDB counters:0,1,2,3 um:one minimum:6000 name:UOP_UNFUSION : Counts unfusion events due to floating point exception to a fused uop.
+event:0xE0 counters:0,1,2,3 um:one minimum:6000 name:BR_INST_DECODED : Counts the number of branch instructions decoded.
+event:0xE4 counters:0,1,2,3 um:one minimum:6000 name:BOGUS_BR : Counts the number of bogus branches.
+event:0xE5 counters:0,1,2,3 um:one minimum:6000 name:BPU_MISSED_CALL_RET : Counts number of times the Branch Prediciton Unit missed predicting a call or return branch.
+event:0xE6 counters:0,1,2,3 um:baclear minimum:6000 name:BACLEAR : Counts the number of times the front end is resteered,
+event:0xE8 counters:0,1,2,3 um:bpu_clears minimum:6000 name:BPU_CLEARS : Counts Branch Prediction Unit clears.
+event:0xF0 counters:0,1,2,3 um:l2_transactions minimum:6000 name:L2_TRANSACTIONS : Counts L2 transactions
+event:0xF1 counters:0,1,2,3 um:l2_lines_in minimum:6000 name:L2_LINES_IN : Counts the number of cache lines allocated in the L2 cache in various states.
+event:0xF2 counters:0,1,2,3 um:l2_lines_out minimum:6000 name:L2_LINES_OUT : Counts L2 cache lines evicted.
+event:0xF3 counters:0,1,2,3 um:l2_hw_prefetch minimum:6000 name:L2_HW_PREFETCH : Count L2 HW prefetcher events
+event:0xF4 counters:0,1,2,3 um:sq_misc minimum:6000 name:SQ_MISC : Counts events in the Super Queue below the L2.
+event:0xF6 counters:0,1,2,3 um:one minimum:6000 name:SQ_FULL_STALL_CYCLES : Counts cycles the Super Queue is full. Neither of the threads on this core will be able to access the uncore.
+event:0xF7 counters:0,1,2,3 um:fp_assist minimum:6000 name:FP_ASSIST : Counts the number of floating point operations executed that required micro-code assist intervention.
+event:0xF8 counters:0,1,2,3 um:one minimum:6000 name:SEGMENT_REG_LOADS : Counts number of segment register loads
+event:0xFD counters:0,1,2,3 um:simd_int_64 minimum:6000 name:SIMD_INT_64 : Counts number of SID integer 64 bit packed multiply operations.
diff --git a/events/i386/nehalem/unit_masks b/events/i386/nehalem/unit_masks
new file mode 100644
index 0000000..d800e5d
--- /dev/null
+++ b/events/i386/nehalem/unit_masks
@@ -0,0 +1,372 @@
+#
+# Unit masks for the Intel "Nehalem" micro architecture
+# (Intel Core i7 "Bloomfield"; Xeon 75xx)
+#
+include:i386/arch_perfmon
+name:sb_forward type:mandatory default:0x01
+ 0x01 any Counts the number of store forwards
+name:load_block type:bitmask default:0x01
+ 0x01 std Counts the number of loads blocked by a preceding store with unknown data
+ 0x04 address_offset Counts the number of loads blocked by a preceding store address
+name:sb_drain type:mandatory default:0x01
+ 0x01 cycles Counts the cycles of store buffer drains
+name:misalign_mem_ref type:bitmask default:0x03
+ 0x01 load Counts the number of misaligned load references
+ 0x02 store Counts the number of misaligned store references
+ 0x03 any Counts the number of misaligned memory references
+name:store_blocks type:bitmask default:0x0f
+ 0x01 not_sta This event counts the number of load operations delayed caused by preceding stores whose addresses are known but whose data is unknown, and preceding stores that conflict with the load but which incompletely overlap the load
+ 0x02 sta This event counts load operations delayed caused by preceding stores whose addresses are unknown (STA block)
+ 0x04 at_ret Counts number of loads delayed with at-Retirement block code
+ 0x08 l1d_block Cacheable loads delayed with L1D block code
+ 0x0F any All loads delayed due to store blocks
+name:dtlb_load_misses type:bitmask default:0x01
+ 0x01 any Counts all load misses that cause a page walk
+ 0x02 walk_completed Counts number of completed page walks due to load miss in the STLB
+ 0x10 stlb_hit Number of cache load STLB hits
+ 0x20 pde_miss Number of DTLB cache load misses where the low part of the linear to physical address translation was missed
+ 0x40 pdp_miss Number of DTLB cache load misses where the high part of the linear to physical address translation was missed
+ 0x80 large_walk_completed Counts number of completed large page walks due to load miss in the STLB
+name:memory_disambiguration type:bitmask default:0x01
+ 0x01 reset Counts memory disambiguration reset cycles
+ 0x02 success Counts the number of loads that memory disambiguration succeeded
+ 0x04 watchdog Counts the number of times the memory disambiguration watchdog kicked in
+ 0x08 watch_cycles Counts the cycles that the memory disambiguration watchdog is active
+name:mem_inst_retired type:bitmask default:0x01
+ 0x01 loads Counts the number of instructions with an architecturally-visible store retired on the architected path
+ 0x02 stores Counts the number of instructions with an architecturally-visible store retired on the architected path
+name:mem_store_retired type:mandatory default:0x01
+ 0x01 dtlb_miss The event counts the number of retired stores that missed the DTLB
+name:uops_issued type:bitmask default:0x01
+ 0x01 any Counts the number of Uops issued by the Register Allocation Table to the Reservation Station, i
+ 0x01 stalled_cycles Counts the number of cycles no Uops issued by the Register Allocation Table to the Reservation Station, i
+ 0x02 fused Counts the number of fused Uops that were issued from the Register Allocation Table to the Reservation Station
+name:mem_uncore_retired type:bitmask default:0x02
+ 0x02 other_core_l2_hitm Counts number of memory load instructions retired where the memory reference hit modified data in a sibling core residing on the same socket
+ 0x08 remote_cache_local_home_hit Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and HIT in a remote socket's cache
+ 0x10 remote_dram Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and was remotely homed
+ 0x20 local_dram Counts number of memory load instructions retired where the memory reference missed the L1, L2 and LLC caches and required a local socket memory reference
+name:fp_comp_ops_exe type:bitmask default:0x01
+ 0x01 x87 Counts the number of FP Computational Uops Executed
+ 0x02 mmx Counts number of MMX Uops executed
+ 0x04 sse_fp Counts number of SSE and SSE2 FP uops executed
+ 0x08 sse2_integer Counts number of SSE2 integer uops executed
+ 0x10 sse_fp_packed Counts number of SSE FP packed uops executed
+ 0x20 sse_fp_scalar Counts number of SSE FP scalar uops executed
+ 0x40 sse_single_precision Counts number of SSE* FP single precision uops executed
+ 0x80 sse_double_precision Counts number of SSE* FP double precision uops executed
+name:simd_int_128 type:bitmask default:0x01
+ 0x01 packed_mpy Counts number of 128 bit SIMD integer multiply operations
+ 0x02 packed_shift Counts number of 128 bit SIMD integer shift operations
+ 0x04 pack Counts number of 128 bit SIMD integer pack operations
+ 0x08 unpack Counts number of 128 bit SIMD integer unpack operations
+ 0x10 packed_logical Counts number of 128 bit SIMD integer logical operations
+ 0x20 packed_arith Counts number of 128 bit SIMD integer arithmetic operations
+ 0x40 shuffle_move Counts number of 128 bit SIMD integer shuffle and move operations
+name:load_dispatch type:bitmask default:0x07
+ 0x01 rs Counts number of loads dispatched from the Reservation Station that bypass the Memory Order Buffer
+ 0x02 rs_delayed Counts the number of delayed RS dispatches at the stage latch
+ 0x04 mob Counts the number of loads dispatched from the Reservation Station to the Memory Order Buffer
+ 0x07 any Counts all loads dispatched from the Reservation Station
+name:arith type:bitmask default:0x01
+ 0x01 cycles_div_busy Counts the number of cycles the divider is busy executing divide or square root operations
+ 0x02 mul Counts the number of multiply operations executed
+name:inst_decoded type:mandatory default:0x01
+ 0x01 dec0 Counts number of instructions that require decoder 0 to be decoded
+name:hw_int type:bitmask default:0x01
+ 0x01 rcv Number of interrupt received
+ 0x02 cycles_masked Number of cycles interrupt are masked
+ 0x04 cycles_pending_and_masked Number of cycles interrupts are pending and masked
+name:l2_rqsts type:bitmask default:0x01
+ 0x01 ld_hit Counts number of loads that hit the L2 cache
+ 0x02 ld_miss Counts the number of loads that miss the L2 cache
+ 0x03 loads Counts all L2 load requests
+ 0x04 rfo_hit Counts the number of store RFO requests that hit the L2 cache
+ 0x08 rfo_miss Counts the number of store RFO requests that miss the L2 cache
+ 0x0C rfos Counts all L2 store RFO requests
+ 0x10 ifetch_hit Counts number of instruction fetches that hit the L2 cache
+ 0x20 ifetch_miss Counts number of instruction fetches that miss the L2 cache
+ 0x30 ifetches Counts all instruction fetches
+ 0x40 prefetch_hit Counts L2 prefetch hits for both code and data
+ 0x80 prefetch_miss Counts L2 prefetch misses for both code and data
+ 0xC0 prefetches Counts all L2 prefetches for both code and data
+ 0xAA miss Counts all L2 misses for both code and data
+ 0xFF references Counts all L2 requests for both code and data
+name:l2_data_rqsts type:bitmask default:0xff
+ 0x01 i_state Counts number of L2 data demand loads where the cache line to be loaded is in the I (invalid) state, i
+ 0x02 s_state Counts number of L2 data demand loads where the cache line to be loaded is in the S (shared) state
+ 0x04 e_state Counts number of L2 data demand loads where the cache line to be loaded is in the E (exclusive) state
+ 0x08 m_state Counts number of L2 data demand loads where the cache line to be loaded is in the M (modified) state
+ 0x0F mesi Counts all L2 data demand requests
+ 0x10 i_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the I (invalid) state, i
+ 0x20 s_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the S (shared) state
+ 0x40 e_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the E (exclusive) state
+ 0x80 m_state Counts number of L2 prefetch data loads where the cache line to be loaded is in the M (modified) state
+ 0xF0 mesi Counts all L2 prefetch requests
+ 0xFF any Counts all L2 data requests
+name:l2_write type:bitmask default:0x01
+ 0x01 i_state Counts number of L2 demand store RFO requests where the cache line to be loaded is in the I (invalid) state, i
+ 0x02 s_state Counts number of L2 store RFO requests where the cache line to be loaded is in the S (shared) state
+ 0x04 e_state Counts number of L2 store RFO requests where the cache line to be loaded is in the E (exclusive) state
+ 0x08 m_state Counts number of L2 store RFO requests where the cache line to be loaded is in the M (modified) state
+ 0x0E hit Counts number of L2 store RFO requests where the cache line to be loaded is in either the S, E or M states
+ 0x0F mesi Counts all L2 store RFO requests
+ 0x10 i_state Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the I (invalid) state, i
+ 0x20 s_state Counts number of L2 lock RFO requests where the cache line to be loaded is in the S (shared) state
+ 0x40 e_state Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the E (exclusive) state
+ 0x80 m_state Counts number of L2 demand lock RFO requests where the cache line to be loaded is in the M (modified) state
+ 0xE0 hit Counts number of L2 demand lock RFO requests where the cache line to be loaded is in either the S, E, or M state
+ 0xF0 mesi Counts all L2 demand lock RFO requests
+name:l1d_wb_l2 type:bitmask default:0x01
+ 0x01 i_state Counts number of L1 writebacks to the L2 where the cache line to be written is in the I (invalid) state, i
+ 0x02 s_state Counts number of L1 writebacks to the L2 where the cache line to be written is in the S state
+ 0x04 e_state Counts number of L1 writebacks to the L2 where the cache line to be written is in the E (exclusive) state
+ 0x08 m_state Counts number of L1 writebacks to the L2 where the cache line to be written is in the M (modified) state
+ 0x0F mesi Counts all L1 writebacks to the L2
+name:longest_lat_cache type:bitmask default:0x4F
+ 0x4F reference This event counts requests originating from the core that reference a cache line in the last level cache
+ 0x41 miss This event counts each cache miss condition for references to the last level cache
+name:cpu_clk_unhalted type:bitmask default:0x00
+ 0x00 thread_p Counts the number of thread cycles while the thread is not in a halt state
+ 0x01 ref_p Increments at the frequency of a slower reference clock when not halted
+name:l1d_cache_ld type:bitmask default:0x01
+ 0x01 i_state Counts L1 data cache read requests where the cache line to be loaded is in the I (invalid) state, i
+ 0x02 s_state Counts L1 data cache read requests where the cache line to be loaded is in the S (shared) state
+ 0x04 e_state Counts L1 data cache read requests where the cache line to be loaded is in the E (exclusive) state
+ 0x08 m_state Counts L1 data cache read requests where the cache line to be loaded is in the M (modified) state
+ 0x0F mesi Counts L1 data cache read requests
+name:l1d_cache_st type:bitmask default:0x01
+ 0x01 i_state Counts L1 data cache store RFO requests where the cache line to be loaded is in the I state
+ 0x02 s_state Counts L1 data cache store RFO requests where the cache line to be loaded is in the S (shared) state
+ 0x04 e_state Counts L1 data cache store RFO requests where the cache line to be loaded is in the E (exclusive) state
+ 0x08 m_state Counts L1 data cache store RFO requests where cache line to be loaded is in the M (modified) state
+ 0x0F mesi Counts L1 data cache store RFO requests
+name:l1d_cache_lock type:bitmask default:0x01
+ 0x01 hit Counts retired load locks that hit in the L1 data cache or hit in an already allocated fill buffer
+ 0x02 s_state Counts L1 data cache retired load locks that hit the target cache line in the shared state
+ 0x04 e_state Counts L1 data cache retired load locks that hit the target cache line in the exclusive state
+ 0x08 m_state Counts L1 data cache retired load locks that hit the target cache line in the modified state
+name:l1d_all_ref type:bitmask default:0x01
+ 0x01 any Counts all references (uncached, speculated and retired) to the L1 data cache, including all loads and stores with any memory types
+ 0x02 cacheable Counts all data reads and writes (speculated and retired) from cacheable memory, including locked operations
+#name:l1d_pend_miss type:mandatory default:0x02
+# 0x02 load_buffers_full Counts cycles of L1 data cache load fill buffers full
+name:dtlb_misses type:bitmask default:0x01
+ 0x01 any Counts the number of misses in the STLB which causes a page walk
+ 0x02 walk_completed Counts number of misses in the STLB which resulted in a completed page walk
+ 0x10 stlb_hit Counts the number of DTLB first level misses that hit in the second level TLB
+ 0x20 pde_miss Number of DTLB cache misses where the low part of the linear to physical address translation was missed
+ 0x40 pdp_miss Number of DTLB misses where the high part of the linear to physical address translation was missed
+ 0x80 large_walk_completed Counts number of completed large page walks due to misses in the STLB
+name:sse_mem_exec type:bitmask default:0x01
+ 0x01 nta Counts number of SSE NTA prefetch/weakly-ordered instructions which missed the L1 data cache
+ 0x08 streaming_stores Counts number of SSE nontemporal stores
+name:l1d_prefetch type:bitmask default:0x01
+ 0x01 requests Counts number of hardware prefetch requests dispatched out of the prefetch FIFO
+ 0x02 miss Counts number of hardware prefetch requests that miss the L1D
+ 0x04 triggers Counts number of prefetch requests triggered by the Finite State Machine and pushed into the prefetch FIFO
+name:ept type:bitmask default:0x02
+ 0x02 epde_miss Counts Extended Page Directory Entry misses
+ 0x04 epdpe_hit Counts Extended Page Directory Pointer Entry hits
+ 0x08 epdpe_miss Counts Extended Page Directory Pointer Entry misses
+name:l1d type:bitmask default:0x01
+ 0x01 repl Counts the number of lines brought into the L1 data cache
+ 0x02 m_repl Counts the number of modified lines brought into the L1 data cache
+ 0x04 m_evict Counts the number of modified lines evicted from the L1 data cache due to replacement
+ 0x08 m_snoop_evict Counts the number of modified lines evicted from the L1 data cache due to snoop HITM intervention
+name:offcore_requests_outstanding type:bitmask default:0x01
+ 0x01 read_data Counts weighted cycles of offcore demand data read requests
+ 0x02 read_code Counts weighted cycles of offcore demand code read requests
+ 0x04 rfo Counts weighted cycles of offcore demand RFO requests
+ 0x08 read Counts weighted cycles of offcore read requests of any kind
+name:cache_lock_cycles type:bitmask default:0x01
+ 0x01 l1d_l2 Cycle count during which the L1D and L2 are locked
+ 0x02 l1d Counts the number of cycles that cacheline in the L1 data cache unit is locked
+name:l1i type:bitmask default:0x01
+ 0x01 hits Counts all instruction fetches that hit the L1 instruction cache
+ 0x02 misses Counts all instruction fetches that miss the L1I cache
+ 0x03 reads Counts all instruction fetches, including uncacheable fetches that bypass the L1I
+ 0x04 cycles_stalled Cycle counts for which an instruction fetch stalls due to a L1I cache miss, ITLB miss or ITLB fault
+name:ifu_ivc type:bitmask default:0x01
+ 0x01 full Instruction Fetche unit victim cache full
+ 0x02 l1i_eviction L1 Instruction cache evictions
+name:large_itlb type:mandatory default:0x01
+ 0x01 hit Counts number of large ITLB hits
+name:itlb_misses type:bitmask default:0x01
+ 0x01 any Counts the number of misses in all levels of the ITLB which causes a page walk
+ 0x02 walk_completed Counts number of misses in all levels of the ITLB which resulted in a completed page walk
+ 0x04 walk_cycles Counts ITLB miss page walk cycles
+ 0x04 pmh_busy_cycles Counts PMH busy cycles
+ 0x10 stlb_hit Counts the number of ITLB misses that hit in the second level TLB
+ 0x20 pde_miss Number of ITLB misses where the low part of the linear to physical address translation was missed
+ 0x40 pdp_miss Number of ITLB misses where the high part of the linear to physical address translation was missed
+ 0x80 large_walk_completed Counts number of completed large page walks due to misses in the STLB
+name:ild_stall type:bitmask default:0x0f
+ 0x01 lcp Cycles Instruction Length Decoder stalls due to length changing prefixes: 66, 67 or REX
+ 0x02 mru Instruction Length Decoder stall cycles due to Brand Prediction Unit (PBU) Most Recently Used (MRU) bypass
+ 0x04 iq_full Stall cycles due to a full instruction queue
+ 0x08 regen Counts the number of regen stalls
+ 0x0F any Counts any cycles the Instruction Length Decoder is stalled
+name:br_inst_exec type:bitmask default:0x7f
+ 0x01 cond Counts the number of conditional near branch instructions executed, but not necessarily retired
+ 0x02 direct Counts all unconditional near branch instructions excluding calls and indirect branches
+ 0x04 indirect_non_call Counts the number of executed indirect near branch instructions that are not calls
+ 0x07 non_calls Counts all non call near branch instructions executed, but not necessarily retired
+ 0x08 return_near Counts indirect near branches that have a return mnemonic
+ 0x10 direct_near_call Counts unconditional near call branch instructions, excluding non call branch, executed
+ 0x20 indirect_near_call Counts indirect near calls, including both register and memory indirect, executed
+ 0x30 near_calls Counts all near call branches executed, but not necessarily retired
+ 0x40 taken Counts taken near branches executed, but not necessarily retired
+ 0x7F any Counts all near executed branches (not necessarily retired)
+name:br_misp_exec type:bitmask default:0x7f
+ 0x01 cond Counts the number of mispredicted conditional near branch instructions executed, but not necessarily retired
+ 0x02 direct Counts mispredicted macro unconditional near branch instructions, excluding calls and indirect branches (should always be 0)
+ 0x04 indirect_non_call Counts the number of executed mispredicted indirect near branch instructions that are not calls
+ 0x07 non_calls Counts mispredicted non call near branches executed, but not necessarily retired
+ 0x08 return_near Counts mispredicted indirect branches that have a rear return mnemonic
+ 0x10 direct_near_call Counts mispredicted non-indirect near calls executed, (should always be 0)
+ 0x20 indirect_near_call Counts mispredicted indirect near calls exeucted, including both register and memory indirect
+ 0x30 near_calls Counts all mispredicted near call branches executed, but not necessarily retired
+ 0x40 taken Counts executed mispredicted near branches that are taken, but not necessarily retired
+ 0x7F any Counts the number of mispredicted near branch instructions that were executed, but not necessarily retired
+name:resource_stalls type:bitmask default:0x01
+ 0x01 any Counts the number of Allocator resource related stalls
+ 0x02 load Counts the cycles of stall due to lack of load buffer for load operation
+ 0x04 rs_full This event counts the number of cycles when the number of instructions in the pipeline waiting for execution reaches the limit the processor can handle
+ 0x08 store This event counts the number of cycles that a resource related stall will occur due to the number of store instructions reaching the limit of the pipeline, (i
+ 0x10 rob_full Counts the cycles of stall due to reorder buffer full
+ 0x20 fpcw Counts the number of cycles while execution was stalled due to writing the floating-point unit (FPU) control word
+ 0x40 mxcsr Stalls due to the MXCSR register rename occurring to close to a previous MXCSR rename
+ 0x80 other Counts the number of cycles while execution was stalled due to other resource issues
+name:offcore_requests type:bitmask default:0x80
+ 0x01 demand_read_data Counts number of offcore demand data read requests
+ 0x02 demand_read_code Counts number of offcore demand code read requests
+ 0x04 demand_rfo Counts number of offcore demand RFO requests
+ 0x08 any_read Counts number of offcore read requests
+ 0x10 any_rfo Counts number of offcore RFO requests
+ 0x20 uncached_mem Counts number of offcore uncached memory requests
+ 0x40 l1d_writeback Counts number of L1D writebacks to the uncore
+ 0x80 any Counts all offcore requests
+name:uops_executed type:bitmask default:0x3f
+ 0x01 port0 Counts number of Uops executed that were issued on port 0
+ 0x02 port1 Counts number of Uops executed that were issued on port 1
+ 0x04 port2_core Counts number of Uops executed that were issued on port 2
+ 0x08 port3_core Counts number of Uops executed that were issued on port 3
+ 0x10 port4_core Counts number of Uops executed that where issued on port 4
+ 0x20 port5 Counts number of Uops executed that where issued on port 5
+ 0x40 port015 Counts number of Uops executed that where issued on port 0, 1, or 5
+ 0x80 port234 Counts number of Uops executed that where issued on port 2, 3, or 4
+name:snoopq_requests_outstanding type:bitmask default:0x01
+ 0x01 data Counts weighted cycles of snoopq requests for data
+ 0x02 invalidate Counts weighted cycles of snoopq invalidate requests
+ 0x04 code Counts weighted cycles of snoopq requests for code
+name:snoop_response type:bitmask default:0x01
+ 0x01 hit Counts HIT snoop response sent by this thread in response to a snoop request
+ 0x02 hite Counts HIT E snoop response sent by this thread in response to a snoop request
+ 0x04 hitm Counts HIT M snoop response sent by this thread in response to a snoop request
+name:pic_accesses type:bitmask default:0x01
+ 0x01 tpr_reads Counts number of TPR reads
+ 0x02 tpr_writes Counts number of TPR writes
+name:inst_retired type:bitmask default:0x01
+ 0x01 any_p instructions retired
+ 0x02 x87 Counts the number of floating point computational operations retired: floating point computational operations executed by the assist handler and sub-operations of complex floating point instructions like transcendental instructions
+name:uops_retired type:bitmask default:0x01
+ 0x01 any Counts the number of micro-ops retired, (macro-fused=1, micro-fused=2, others=1; maximum count of 8 per cycle)
+ 0x02 retire_slots Counts the number of retirement slots used each cycle
+ 0x04 macro_fused Counts number of macro-fused uops retired
+name:machine_clears type:bitmask default:0x01
+ 0x01 cycles Counts the cycles machine clear is asserted
+ 0x02 mem_order Counts the number of machine clears due to memory order conflicts
+ 0x04 smc Counts the number of times that a program writes to a code section
+ 0x10 fusion_assist Counts the number of macro-fusion assists
+name:br_inst_retired type:bitmask default:0x00
+ 0x00 all_branches See Table A-1
+ 0x01 conditional Counts the number of conditional branch instructions retired
+ 0x02 near_call Counts the number of direct & indirect near unconditional calls retired
+ 0x04 all_branches Counts the number of branch instructions retired
+name:br_misp_retired type:bitmask default:0x00
+ 0x00 all_branches See Table A-1
+ 0x02 near_call Counts mispredicted direct & indirect near unconditional retired calls
+name:ssex_uops_retired type:bitmask default:0x01
+ 0x01 packed_single Counts SIMD packed single-precision floating point Uops retired
+ 0x02 scalar_single Counts SIMD calar single-precision floating point Uops retired
+ 0x04 packed_double Counts SIMD packed double-precision floating point Uops retired
+ 0x08 scalar_double Counts SIMD scalar double-precision floating point Uops retired
+ 0x10 vector_integer Counts 128-bit SIMD vector integer Uops retired
+name:mem_load_retired type:bitmask default:0x01
+ 0x01 l1d_hit Counts number of retired loads that hit the L1 data cache
+ 0x02 l2_hit Counts number of retired loads that hit the L2 data cache
+ 0x04 llc_unshared_hit Counts number of retired loads that hit their own, unshared lines in the LLC cache
+ 0x08 other_core_l2_hit_hitm Counts number of retired loads that hit in a sibling core's L2 (on die core)
+ 0x10 llc_miss Counts number of retired loads that miss the LLC cache
+ 0x40 hit_lfb Counts number of retired loads that miss the L1D and the address is located in an allocated line fill buffer and will soon be committed to cache
+ 0x80 dtlb_miss Counts the number of retired loads that missed the DTLB
+name:fp_mmx_trans type:bitmask default:0x03
+ 0x01 to_fp Counts the first floating-point instruction following any MMX instruction
+ 0x02 to_mmx Counts the first MMX instruction following a floating-point instruction
+ 0x03 any Counts all transitions from floating point to MMX instructions and from MMX instructions to floating point instructions
+name:macro_insts type:mandatory default:0x01
+ 0x01 decoded Counts the number of instructions decoded, (but not necessarily executed or retired)
+name:uops_decoded type:bitmask default:0x0e
+ 0x02 ms Counts the number of Uops decoded by the Microcode Sequencer, MS
+ 0x04 esp_folding Counts number of stack pointer (ESP) instructions decoded: push , pop , call , ret, etc
+ 0x08 esp_sync Counts number of stack pointer (ESP) sync operations where an ESP instruction is corrected by adding the ESP offset register to the current value of the ESP register
+name:rat_stalls type:bitmask default:0x0f
+ 0x01 flags Counts the number of cycles during which execution stalled due to several reasons, one of which is a partial flag register stall
+ 0x02 registers This event counts the number of cycles instruction execution latency became longer than the defined latency because the instruction used a register that was partially written by previous instruction
+ 0x04 rob_read_port Counts the number of cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the out-of-order pipeline
+ 0x08 scoreboard Counts the cycles where we stall due to microarchitecturally required serialization
+ 0x0F any Counts all Register Allocation Table stall cycles due to: Cycles when ROB read port stalls occurred, which did not allow new micro-ops to enter the execution pipe
+name:baclear type:bitmask default:0x01
+ 0x01 clear Counts the number of times the front end is resteered, mainly when the Branch Prediction Unit cannot provide a correct prediction and this is corrected by the Branch Address Calculator at the front end
+ 0x02 bad_target Counts number of Branch Address Calculator clears (BACLEAR) asserted due to conditional branch instructions in which there was a target hit but the direction was wrong
+name:bpu_clears type:bitmask default:0x03
+ 0x01 early Counts early (normal) Branch Prediction Unit clears: BPU predicted a taken branch after incorrectly assuming that it was not taken
+ 0x02 late Counts late Branch Prediction Unit clears due to Most Recently Used conflicts
+ 0x03 any Counts all BPU clears
+name:l2_transactions type:bitmask default:0x80
+ 0x01 load Counts L2 load operations due to HW prefetch or demand loads
+ 0x02 rfo Counts L2 RFO operations due to HW prefetch or demand RFOs
+ 0x04 ifetch Counts L2 instruction fetch operations due to HW prefetch or demand ifetch
+ 0x08 prefetch Counts L2 prefetch operations
+ 0x10 l1d_wb Counts L1D writeback operations to the L2
+ 0x20 fill Counts L2 cache line fill operations due to load, RFO, L1D writeback or prefetch
+ 0x40 wb Counts L2 writeback operations to the LLC
+ 0x80 any Counts all L2 cache operations
+name:l2_lines_in type:bitmask default:0x07
+ 0x02 s_state Counts the number of cache lines allocated in the L2 cache in the S (shared) state
+ 0x04 e_state Counts the number of cache lines allocated in the L2 cache in the E (exclusive) state
+ 0x07 any Counts the number of cache lines allocated in the L2 cache
+name:l2_lines_out type:bitmask default:0x0f
+ 0x01 demand_clean Counts L2 clean cache lines evicted by a demand request
+ 0x02 demand_dirty Counts L2 dirty (modified) cache lines evicted by a demand request
+ 0x04 prefetch_clean Counts L2 clean cache line evicted by a prefetch request
+ 0x08 prefetch_dirty Counts L2 modified cache line evicted by a prefetch request
+ 0x0F any Counts all L2 cache lines evicted for any reason
+name:l2_hw_prefetch type:bitmask default:0x01
+ 0x01 hit Count L2 HW prefetcher detector hits
+ 0x02 alloc Count L2 HW prefetcher allocations
+ 0x04 data_trigger Count L2 HW data prefetcher triggered
+ 0x08 code_trigger Count L2 HW code prefetcher triggered
+ 0x10 dca_trigger Count L2 HW DCA prefetcher triggered
+ 0x20 kick_start Count L2 HW prefetcher kick started
+name:sq_misc type:bitmask default:0x01
+ 0x01 promotion Counts the number of L2 secondary misses that hit the Super Queue
+ 0x02 promotion_post_go Counts the number of L2 secondary misses during the Super Queue filling L2
+ 0x04 lru_hints Counts number of Super Queue LRU hints sent to L3
+ 0x08 fill_dropped Counts the number of SQ L2 fills dropped due to L2 busy
+ 0x10 split_lock Counts the number of SQ lock splits across a cache line
+name:fp_assist type:bitmask default:0x01
+ 0x01 all Counts the number of floating point operations executed that required micro-code assist intervention
+ 0x02 output Counts number of floating point micro-code assist when the output value (destination register) is invalid
+ 0x04 input Counts number of floating point micro-code assist when the input value (one of the source operands to an FP instruction) is invalid
+name:simd_int_64 type:bitmask default:0x01
+ 0x01 packed_mpy Counts number of SID integer 64 bit packed multiply operations
+ 0x02 packed_shift Counts number of SID integer 64 bit packed shift operations
+ 0x04 pack Counts number of SID integer 64 bit pack operations
+ 0x08 unpack Counts number of SID integer 64 bit unpack operations
+ 0x10 packed_logical Counts number of SID integer 64 bit logical operations
+ 0x20 packed_arith Counts number of SID integer 64 bit arithmetic operations
+ 0x40 shuffle_move Counts number of SID integer 64 bit shift or move operations
+name:x20 type:mandatory default:0x20
+ 0x20 No unit mask
diff --git a/events/i386/p4-ht/events b/events/i386/p4-ht/events
new file mode 100644
index 0000000..00c6bc9
--- /dev/null
+++ b/events/i386/p4-ht/events
@@ -0,0 +1,25 @@
+# Pentium IV HyperThreading events
+#
+# NOTE: events cannot currently be 0x00 due to event binding checks in
+# driver
+#
+event:0x1d counters:0 um:global_power_events minimum:6000 name:GLOBAL_POWER_EVENTS : time during which processor is not stopped
+event:0x01 counters:3 um:branch_retired minimum:6000 name:BRANCH_RETIRED : retired branches
+event:0x02 counters:3 um:mispred_branch_retired minimum:6000 name:MISPRED_BRANCH_RETIRED : retired mispredicted branches
+event:0x04 counters:0 um:bpu_fetch_request minimum:6000 name:BPU_FETCH_REQUEST : instruction fetch requests from the branch predict unit
+event:0x05 counters:0 um:itlb_reference minimum:6000 name:ITLB_REFERENCE : translations using the instruction translation lookaside buffer
+event:0x06 counters:2 um:memory_cancel minimum:6000 name:MEMORY_CANCEL : cancelled requesets in data cache address control unit
+event:0x07 counters:2 um:memory_complete minimum:6000 name:MEMORY_COMPLETE : completed split
+event:0x08 counters:2 um:load_port_replay minimum:6000 name:LOAD_PORT_REPLAY : replayed events at the load port
+event:0x09 counters:2 um:store_port_replay minimum:6000 name:STORE_PORT_REPLAY : replayed events at the store port
+event:0x0a counters:0 um:mob_load_replay minimum:6000 name:MOB_LOAD_REPLAY : replayed loads from the memory order buffer
+event:0x0c counters:0 um:bsq_cache_reference minimum:6000 name:BSQ_CACHE_REFERENCE : cache references seen by the bus unit
+event:0x12 counters:3 um:x87_assist minimum:6000 name:X87_ASSIST : retired x87 instructions which required special handling
+event:0x1c counters:3 um:machine_clear minimum:6000 name:MACHINE_CLEAR : cycles with entire machine pipeline cleared
+event:0x1e counters:1 um:tc_ms_xfer minimum:6000 name:TC_MS_XFER : number of times uops deliver changed from TC to MS ROM
+event:0x1f counters:1 um:uop_queue_writes minimum:6000 name:UOP_QUEUE_WRITES : number of valid uops written to the uop queue
+event:0x23 counters:3 um:instr_retired minimum:6000 name:INSTR_RETIRED : retired instructions
+event:0x24 counters:3 um:uops_retired minimum:6000 name:UOPS_RETIRED : retired uops
+event:0x25 counters:3 um:uop_type minimum:6000 name:UOP_TYPE : type of uop tagged by front-end tagging
+event:0x26 counters:1 um:branch_type minimum:6000 name:RETIRED_MISPRED_BRANCH_TYPE : retired mispredicted branched, selected by type
+event:0x27 counters:1 um:branch_type minimum:6000 name:RETIRED_BRANCH_TYPE : retired branches, selected by type
diff --git a/events/i386/p4-ht/unit_masks b/events/i386/p4-ht/unit_masks
new file mode 100644
index 0000000..8bfc6fa
--- /dev/null
+++ b/events/i386/p4-ht/unit_masks
@@ -0,0 +1,79 @@
+# Pentium IV HyperThreading possible unit masks
+#
+name:branch_retired type:bitmask default:0x0c
+ 0x01 branch not-taken predicted
+ 0x02 branch not-taken mispredicted
+ 0x04 branch taken predicted
+ 0x08 branch taken mispredicted
+name:mispred_branch_retired type:bitmask default:0x01
+ 0x01 retired instruction is non-bogus
+# FIXME: 0 count nothing, 0xff count more than 0x01, docs says it's a bitmask:
+# something wrong in documentation ?
+name:bpu_fetch_request type:bitmask default:0x01
+ 0x01 trace cache lookup miss
+name:itlb_reference type:bitmask default:0x07
+ 0x01 ITLB hit
+ 0x02 ITLB miss
+ 0x04 uncacheable ITLB hit
+name:memory_cancel type:bitmask default:0x08
+ 0x04 replayed because no store request buffer available
+ 0x08 conflicts due to 64k aliasing
+name:memory_complete type:bitmask default:0x03
+ 0x01 load split completed, excluding UC/WC loads
+ 0x02 any split stores completed
+ 0x04 uncacheable load split completed
+ 0x08 uncacheable store split complete
+name:load_port_replay type:mandatory default:0x02
+ 0x02 split load
+name:store_port_replay type:mandatory default:0x02
+ 0x02 split store
+name:mob_load_replay type:bitmask default:0x3a
+ 0x02 replay cause: unknown store address
+ 0x08 replay cause: unknown store data
+ 0x10 replay cause: partial overlap between load and store
+ 0x20 replay cause: mismatched low 4 bits between load and store addr
+name:bsq_cache_reference type:bitmask default:0x073f
+ 0x01 read 2nd level cache hit shared
+ 0x02 read 2nd level cache hit exclusive
+ 0x04 read 2nd level cache hit modified
+ 0x08 read 3rd level cache hit shared
+ 0x10 read 3rd level cache hit exclusive
+ 0x20 read 3rd level cache hit modified
+ 0x100 read 2nd level cache miss
+ 0x200 read 3rd level cache miss
+ 0x400 writeback lookup from DAC misses 2nd level cache
+name:x87_assist type:bitmask default:0x1f
+ 0x01 handle FP stack underflow
+ 0x02 handle FP stack overflow
+ 0x04 handle x87 output overflow
+ 0x08 handle x87 output underflow
+ 0x10 handle x87 input assist
+name:machine_clear type:bitmask default:0x01
+ 0x01 count a portion of cycles the machine is cleared for any cause
+ 0x04 count each time the machine is cleared due to memory ordering issues
+ 0x40 count each time the machine is cleared due to self modifying code
+name:global_power_events type:mandatory default:0x01
+ 0x01 mandatory
+name:tc_ms_xfer type:mandatory default:0x01
+ 0x01 count TC to MS transfers
+name:uop_queue_writes type:bitmask default:0x07
+ 0x01 count uops written to queue from TC build mode
+ 0x02 count uops written to queue from TC deliver mode
+ 0x04 count uops written to queue from microcode ROM
+name:instr_retired type:bitmask default:0x01
+ 0x01 count non-bogus instructions which are not tagged
+ 0x02 count non-bogus instructions which are tagged
+ 0x04 count bogus instructions which are not tagged
+ 0x08 count bogus instructions which are tagged
+name:uops_retired type:bitmask default:0x01
+ 0x01 count marked uops which are non-bogus
+ 0x02 count marked uops which are bogus
+name:uop_type type:bitmask default:0x02
+ 0x02 count uops which are load operations
+ 0x04 count uops which are store operations
+name:branch_type type:bitmask default:0x1f
+ 0x01 count unconditional jumps
+ 0x02 count conditional jumps
+ 0x04 count call branches
+ 0x08 count return branches
+ 0x10 count indirect jumps
diff --git a/events/i386/p4/events b/events/i386/p4/events
new file mode 100644
index 0000000..2978fd5
--- /dev/null
+++ b/events/i386/p4/events
@@ -0,0 +1,44 @@
+# Pentium IV events
+#
+# NOTE: events cannot currently be 0x00 due to event binding checks in
+# driver
+#
+event:0x1d counters:0,4 um:global_power_events minimum:3000 name:GLOBAL_POWER_EVENTS : time during which processor is not stopped
+event:0x01 counters:3,7 um:branch_retired minimum:3000 name:BRANCH_RETIRED : retired branches
+event:0x02 counters:3,7 um:mispred_branch_retired minimum:3000 name:MISPRED_BRANCH_RETIRED : retired mispredicted branches
+event:0x04 counters:0,4 um:bpu_fetch_request minimum:3000 name:BPU_FETCH_REQUEST : instruction fetch requests from the branch predict unit
+event:0x05 counters:0,4 um:itlb_reference minimum:3000 name:ITLB_REFERENCE : translations using the instruction translation lookaside buffer
+event:0x06 counters:2,6 um:memory_cancel minimum:3000 name:MEMORY_CANCEL : cancelled requesets in data cache address control unit
+event:0x07 counters:2,6 um:memory_complete minimum:3000 name:MEMORY_COMPLETE : completed split
+event:0x08 counters:2,6 um:load_port_replay minimum:3000 name:LOAD_PORT_REPLAY : replayed events at the load port
+event:0x09 counters:2,6 um:store_port_replay minimum:3000 name:STORE_PORT_REPLAY : replayed events at the store port
+event:0x0a counters:0,4 um:mob_load_replay minimum:3000 name:MOB_LOAD_REPLAY : replayed loads from the memory order buffer
+event:0x0c counters:0,4 um:bsq_cache_reference minimum:3000 name:BSQ_CACHE_REFERENCE : cache references seen by the bus unit
+# intel doc vol 3 table A-1 P4 and xeon with cpuid signature < 0xf27 doen't allow MSR_FSB_ESCR1 so on only counter 0 is available
+event:0x0d counters:0 um:ioq minimum:3000 name:IOQ_ALLOCATION : bus transactions
+# FIXME the unit mask associated is known to get different behavior between cpu
+# step id, it need to be documented in P4 events doc
+event:0x0e counters:4 um:ioq minimum:3000 name:IOQ_ACTIVE_ENTRIES : number of entries in the IOQ which are active
+event:0x10 counters:0 um:bsq minimum:3000 name:BSQ_ALLOCATION : allocations in the bus sequence unit
+event:0x12 counters:3,7 um:x87_assist minimum:3000 name:X87_ASSIST : retired x87 instructions which required special handling
+event:0x1c counters:3,7 um:machine_clear minimum:3000 name:MACHINE_CLEAR : cycles with entire machine pipeline cleared
+event:0x1e counters:1,5 um:tc_ms_xfer minimum:3000 name:TC_MS_XFER : number of times uops deliver changed from TC to MS ROM
+event:0x1f counters:1,5 um:uop_queue_writes minimum:3000 name:UOP_QUEUE_WRITES : number of valid uops written to the uop queue
+event:0x23 counters:3,7 um:instr_retired minimum:3000 name:INSTR_RETIRED : retired instructions
+event:0x24 counters:3,7 um:uops_retired minimum:3000 name:UOPS_RETIRED : retired uops
+event:0x25 counters:3,7 um:uop_type minimum:3000 name:UOP_TYPE : type of uop tagged by front-end tagging
+event:0x26 counters:1,5 um:branch_type minimum:3000 name:RETIRED_MISPRED_BRANCH_TYPE : retired mispredicted branched, selected by type
+event:0x27 counters:1,5 um:branch_type minimum:3000 name:RETIRED_BRANCH_TYPE : retired branches, selected by type
+event:0x03 counters:1,5 um:tc_deliver_mode minimum:3000 name:TC_DELIVER_MODE : duration (in clock cycles) in the trace cache and decode engine
+event:0x0b counters:0,4 um:page_walk_type minimum:3000 name:PAGE_WALK_TYPE : page walks by the page miss handler
+event:0x0f counters:0,4 um:fsb_data_activity minimum:3000 name:FSB_DATA_ACTIVITY : DRDY or DBSY events on the front side bus
+event:0x11 counters:4 um:bsq minimum:3000 name:BSQ_ACTIVE_ENTRIES : number of entries in the bus sequence unit which are active
+event:0x13 counters:2,6 um:flame_uop minimum:3000 name:SSE_INPUT_ASSIST : input assists requested for SSE or SSE2 operands
+event:0x14 counters:2,6 um:flame_uop minimum:3000 name:PACKED_SP_UOP : packed single precision uops
+event:0x15 counters:2,6 um:flame_uop minimum:3000 name:PACKED_DP_UOP : packed double precision uops
+event:0x16 counters:2,6 um:flame_uop minimum:3000 name:SCALAR_SP_UOP : scalar single precision uops
+event:0x17 counters:2,6 um:flame_uop minimum:3000 name:SCALAR_DP_UOP : scalar double presision uops
+event:0x18 counters:2,6 um:flame_uop minimum:3000 name:64BIT_MMX_UOP : 64 bit integer SIMD MMX uops
+event:0x19 counters:2,6 um:flame_uop minimum:3000 name:128BIT_MMX_UOP : 128 bit integer SIMD SSE2 uops
+event:0x1a counters:2,6 um:flame_uop minimum:3000 name:X87_FP_UOP : x87 floating point uops
+event:0x1b counters:2,6 um:x87_simd_moves_uop minimum:3000 name:X87_SIMD_MOVES_UOP : x87 FPU, MMX, SSE, or SSE2 loads, stores and reg-to-reg moves
diff --git a/events/i386/p4/unit_masks b/events/i386/p4/unit_masks
new file mode 100644
index 0000000..7946fdd
--- /dev/null
+++ b/events/i386/p4/unit_masks
@@ -0,0 +1,127 @@
+# Pentium IV possible unit masks
+#
+name:branch_retired type:bitmask default:0x0c
+ 0x01 branch not-taken predicted
+ 0x02 branch not-taken mispredicted
+ 0x04 branch taken predicted
+ 0x08 branch taken mispredicted
+name:mispred_branch_retired type:bitmask default:0x01
+ 0x01 retired instruction is non-bogus
+# FIXME: 0 count nothing, 0xff count more than 0x01, docs says it's a bitmask:
+# something wrong in documentation ?
+name:bpu_fetch_request type:bitmask default:0x01
+ 0x01 trace cache lookup miss
+name:itlb_reference type:bitmask default:0x07
+ 0x01 ITLB hit
+ 0x02 ITLB miss
+ 0x04 uncacheable ITLB hit
+name:memory_cancel type:bitmask default:0x08
+ 0x04 replayed because no store request buffer available
+ 0x08 conflicts due to 64k aliasing
+name:memory_complete type:bitmask default:0x03
+ 0x01 load split completed, excluding UC/WC loads
+ 0x02 any split stores completed
+ 0x04 uncacheable load split completed
+ 0x08 uncacheable store split complete
+name:load_port_replay type:mandatory default:0x02
+ 0x02 split load
+name:store_port_replay type:mandatory default:0x02
+ 0x02 split store
+name:mob_load_replay type:bitmask default:0x3a
+ 0x02 replay cause: unknown store address
+ 0x08 replay cause: unknown store data
+ 0x10 replay cause: partial overlap between load and store
+ 0x20 replay cause: mismatched low 4 bits between load and store addr
+name:bsq_cache_reference type:bitmask default:0x073f
+ 0x01 read 2nd level cache hit shared
+ 0x02 read 2nd level cache hit exclusive
+ 0x04 read 2nd level cache hit modified
+ 0x08 read 3rd level cache hit shared
+ 0x10 read 3rd level cache hit exclusive
+ 0x20 read 3rd level cache hit modified
+ 0x100 read 2nd level cache miss
+ 0x200 read 3rd level cache miss
+ 0x400 writeback lookup from DAC misses 2nd level cache
+name:ioq type:bitmask default:0xefe1
+ 0x01 bus request type bit 0
+ 0x02 bus request type bit 1
+ 0x04 bus request type bit 2
+ 0x08 bus request type bit 3
+ 0x10 bus request type bit 4
+ 0x20 count read entries
+ 0x40 count write entries
+ 0x80 count UC memory access entries
+ 0x100 count WC memory access entries
+ 0x200 count write-through memory access entries
+ 0x400 count write-protected memory access entries
+ 0x800 count WB memory access entries
+ 0x2000 count own store requests
+ 0x4000 count other / DMA store requests
+ 0x8000 count HW/SW prefetch requests
+name:bsq type:bitmask default:0x21
+ 0x01 (r)eq (t)ype (e)ncoding, bit 0: see next bit
+ 0x02 rte bit 1: 00=read, 01=read invalidate, 10=write, 11=writeback
+ 0x04 req len bit 0
+ 0x08 req len bit 1
+ 0x20 request type is input (0=output)
+ 0x40 request type is bus lock
+ 0x80 request type is cacheable
+ 0x100 request type is 8-byte chunk split across 8-byte boundary
+ 0x200 request type is demand (0=prefetch)
+ 0x400 request type is ordered
+ 0x800 (m)emory (t)ype (e)ncoding, bit 0: see next bits
+ 0x1000 mte bit 1: see next bits
+ 0x2000 mte bit 2: 000=UC, 001=USWC, 100=WT, 101=WP, 110=WB
+name:x87_assist type:bitmask default:0x1f
+ 0x01 handle FP stack underflow
+ 0x02 handle FP stack overflow
+ 0x04 handle x87 output overflow
+ 0x08 handle x87 output underflow
+ 0x10 handle x87 input assist
+name:machine_clear type:bitmask default:0x01
+ 0x01 count a portion of cycles the machine is cleared for any cause
+ 0x04 count each time the machine is cleared due to memory ordering issues
+ 0x40 count each time the machine is cleared due to self modifying code
+name:global_power_events type:mandatory default:0x01
+ 0x01 mandatory
+name:tc_ms_xfer type:mandatory default:0x01
+ 0x01 count TC to MS transfers
+name:uop_queue_writes type:bitmask default:0x07
+ 0x01 count uops written to queue from TC build mode
+ 0x02 count uops written to queue from TC deliver mode
+ 0x04 count uops written to queue from microcode ROM
+name:instr_retired type:bitmask default:0x01
+ 0x01 count non-bogus instructions which are not tagged
+ 0x02 count non-bogus instructions which are tagged
+ 0x04 count bogus instructions which are not tagged
+ 0x08 count bogus instructions which are tagged
+name:uops_retired type:bitmask default:0x01
+ 0x01 count marked uops which are non-bogus
+ 0x02 count marked uops which are bogus
+name:uop_type type:bitmask default:0x02
+ 0x02 count uops which are load operations
+ 0x04 count uops which are store operations
+name:branch_type type:bitmask default:0x1f
+ 0x01 count unconditional jumps
+ 0x02 count conditional jumps
+ 0x04 count call branches
+ 0x08 count return branches
+ 0x10 count indirect jumps
+name:tc_deliver_mode type:bitmask default:0x04
+ 0x04 processor is in deliver mode
+ 0x20 processor is in build mode
+name:page_walk_type type:bitmask default:0x01
+ 0x01 page walk for data TLB miss
+ 0x02 page walk for instruction TLB miss
+name:fsb_data_activity type:bitmask default:0x3f
+ 0x01 count when this processor drives data onto bus
+ 0x02 count when this processor reads data from bus
+ 0x04 count when data is on bus but not sampled by this processor
+ 0x08 count when this processor reserves bus for driving
+ 0x10 count when other reserves bus and this processor will sample
+ 0x20 count when other reserves bus and this processor will not sample
+name:flame_uop type:mandatory default:0x8000
+ 0x8000 count all uops of this type
+name:x87_simd_moves_uop type:bitmask default:0x18
+ 0x08 count all x87 SIMD store/move uops
+ 0x10 count all x87 SIMD load uops
diff --git a/events/i386/p6_mobile/events b/events/i386/p6_mobile/events
new file mode 100644
index 0000000..86de7bb
--- /dev/null
+++ b/events/i386/p6_mobile/events
@@ -0,0 +1,115 @@
+# Pentium M events
+#
+event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted, and not in a thermal trip
+event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non
+event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU
+event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU
+event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU
+event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
+event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches
+event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
+event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
+event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
+event:0x28 counters:0,1 um:mesi minimum:500 name:L2_IFETCH : number of L2 instruction fetches
+event:0x29 counters:0,1 um:mesi minimum:500 name:L2_LD : number of L2 data loads
+event:0x2a counters:0,1 um:mesi minimum:500 name:L2_ST : number of L2 data stores
+event:0x24 counters:0,1 um:zero minimum:500 name:L2_LINES_IN : number of allocated lines in L2
+event:0x26 counters:0,1 um:zero minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
+event:0x25 counters:0,1 um:zero minimum:500 name:L2_M_LINES_INM : number of modified lines allocated in L2
+event:0x27 counters:0,1 um:zero minimum:500 name:L2_M_LINES_OUTM : number of modified lines removed from L2
+event:0x2e counters:0,1 um:mesi minimum:500 name:L2_RQSTS : number of L2 requests
+event:0x21 counters:0,1 um:zero minimum:500 name:L2_ADS : number of L2 address strobes
+event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
+event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
+event:0x62 counters:0,1 um:ebl minimum:500 name:BUS_DRDY_CLOCKS : number of clocks DRDY is asserted
+event:0x63 counters:0,1 um:ebl minimum:500 name:BUS_LOCK_CLOCKS : number of clocks LOCK is asserted
+event:0x60 counters:0,1 um:zero minimum:500 name:BUS_REQ_OUTSTANDING : number of outstanding bus requests
+event:0x65 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BRD : number of burst read transactions
+event:0x66 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_RFO : number of read for ownership transactions
+event:0x67 counters:0,1 um:ebl minimum:500 name:BUS_TRANS_WB : number of write back transactions
+event:0x68 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_IFETCH : number of instruction fetch transactions
+event:0x69 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_INVAL : number of invalidate transactions
+event:0x6a counters:0,1 um:ebl minimum:500 name:BUS_TRAN_PWR : number of partial write transactions
+event:0x6b counters:0,1 um:ebl minimum:500 name:BUS_TRANS_P : number of partial transactions
+event:0x6c counters:0,1 um:ebl minimum:500 name:BUS_TRANS_IO : number of I/O transactions
+event:0x6d counters:0,1 um:ebl minimum:500 name:BUS_TRANS_DEF : number of deferred transactions
+event:0x6e counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BURST : number of burst transactions
+event:0x70 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_ANY : number of all transactions
+event:0x6f counters:0,1 um:ebl minimum:500 name:BUS_TRAN_MEM : number of memory transactions
+event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data
+event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin
+event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin
+event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin
+event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall
+event:0xc1 counters:0 um:zero minimum:3000 name:COMP_FLOP_RET : number of computational FP operations retired
+event:0x10 counters:0 um:zero minimum:3000 name:FLOPS : number of computational FP operations executed
+event:0x11 counters:1 um:zero minimum:500 name:FP_ASSIST : number of FP exceptions handled by microcode
+event:0x12 counters:1 um:zero minimum:1000 name:MUL : number of multiplies
+event:0x13 counters:1 um:zero minimum:500 name:DIV : number of divides
+event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
+event:0x03 counters:0,1 um:zero minimum:500 name:LD_BLOCKS : number of store buffer blocks
+event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles
+event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
+event:0x07 counters:0,1 um:kni_prefetch minimum:500 name:EMON_KNI_PREF_DISPATCHED : number of KNI pre-fetch/weakly ordered insns dispatched
+event:0x4b counters:0,1 um:kni_prefetch minimum:500 name:EMON_KNI_PREF_MISS : number of KNI pre-fetch/weakly ordered insns that miss all caches
+event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0xc2 counters:0,1 um:zero minimum:6000 name:UOPS_RETIRED : number of UOPs retired
+# Errata lists INST_DECODE as not accurate. See 25266507.pdf.
+event:0xd0 counters:0,1 um:zero minimum:6000 name:INST_DECODED : number of instructions decoded
+event:0xd8 counters:0,1 um:sse_sse2_inst_retired minimum:3000 name:EMON_SSE_SSE2_INST_RETIRED : Streaming SIMD Extensions Instructions Retired
+event:0xd9 counters:0,1 um:sse_sse2_inst_retired minimum:3000 name:EMON_SSE_SSE2_COMP_INST_RETIRED : Computational SSE Instructions Retired
+event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RX : number of hardware interrupts received
+event:0xc6 counters:0,1 um:zero minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled
+event:0xc7 counters:0,1 um:zero minimum:500 name:CYCLES_INT_PENDING_AND_MASKED : cycles interrupts are disabled with pending interrupts
+event:0xc4 counters:0,1 um:zero minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired
+event:0xc9 counters:0,1 um:zero minimum:500 name:BR_TAKEN_RETIRED : number of taken branches retired
+event:0xca counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_TAKEN_RET : number of taken mispredictions branches retired
+event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded
+event:0xe2 counters:0,1 um:zero minimum:500 name:BTB_MISSES : number of branches that miss the BTB
+event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches
+event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted
+event:0xa2 counters:0,1 um:zero minimum:500 name:RESOURCE_STALLS : cycles during resource related stalls
+event:0xd2 counters:0,1 um:zero minimum:500 name:PARTIAL_RAT_STALLS : cycles or events for partial stalls
+event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
+event:0xb1 counters:0,1 um:zero minimum:3000 name:MMX_SAT_INSTR_EXEC : number of MMX saturating instructions executed
+event:0xb2 counters:0,1 um:mmx_uops minimum:3000 name:MMX_UOPS_EXEC : number of MMX UOPS executed
+event:0xb3 counters:0,1 um:mmx_instr_type_exec minimum:3000 name:MMX_INSTR_TYPE_EXEC : number of MMX packing instructions
+event:0xcc counters:0,1 um:mmx_trans minimum:3000 name:FP_MMX_TRANS : MMX-floating point transitions
+event:0xcd counters:0,1 um:zero minimum:500 name:MMX_ASSIST : number of EMMS instructions executed
+event:0xce counters:0,1 um:zero minimum:3000 name:MMX_INSTR_RET : number of MMX instructions retired
+#
+# Pentium M Specific events from A-7
+#
+#
+# Power Management
+event:0x58 counters:0,1 um:freq minimum:3000 name:EMON_EST_TRANS : Number of Enhanced Intel SpeedStep
+# Errata lists EMON_THERMAL_TRIP as not accurate. See 25266507.pdf.
+event:0x59 counters:0,1 um:zero minimum:3000 name:EMON_THERMAL_TRIP : Duration/Occurrences in thermal trip
+#
+# BPU
+event:0x88 counters:0,1 um:zero minimum:3000 name:BR_INST_EXEC : Branch instructions executed (not necessarily retired)
+event:0x89 counters:0,1 um:zero minimum:3000 name:BR_MISSP_EXEC : Branch instructions executed that were mispredicted at execution
+event:0x8a counters:0,1 um:zero minimum:3000 name:BR_BAC_MISSP_EXEC : Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x8b counters:0,1 um:zero minimum:3000 name:BR_CND_EXEC : Conditional Branch instructions executed
+event:0x8c counters:0,1 um:zero minimum:3000 name:BR_CND_MISSP_EXEC : Conditional Branch instructions executed that were mispredicted
+event:0x8d counters:0,1 um:zero minimum:3000 name:BR_IND_EXEC : Indirect Branch instructions executed
+event:0x8e counters:0,1 um:zero minimum:3000 name:BR_IND_MISSP_EXEC : Indirect Branch instructions executed that were mispredicted
+event:0x8f counters:0,1 um:zero minimum:3000 name:BR_RET_EXEC : Return Branch instructions executed
+event:0x90 counters:0,1 um:zero minimum:3000 name:BR_RET_MISSP_EXEC : Return Branch instructions executed that were mispredicted at Execution
+event:0x91 counters:0,1 um:zero minimum:3000 name:BR_RET_BAC_MISSP_EXEC :Return Branch instructions executed that were mispredicted at Front End (BAC)
+event:0x92 counters:0,1 um:zero minimum:3000 name:BR_CALL_EXEC : CALL instruction executed
+event:0x93 counters:0,1 um:zero minimum:3000 name:BR_CALL_MISSP_EXEC : CALL instruction executed and miss predicted
+event:0x94 counters:0,1 um:zero minimum:3000 name:BR_IND_CALL_EXEC : Indirect CALL instruction executed
+#
+# Decoder
+event:0xce counters:0,1 um:zero minimum:3000 name:EMON_SIMD_INSTR_RETIRED : Number of retired MMX instructions
+event:0xd3 counters:0,1 um:zero minimum:3000 name:EMON_SYNCH_UOPS : Sync micro-ops
+event:0xd7 counters:0,1 um:zero minimum:3000 name:EMON_SYNCH_UOPS : Total number of micro-ops
+event:0xda counters:0,1 um:fused minimum:3000 name:EMON_FUSED_UOPS_RET : Number of retired fused micro-ops
+event:0xdb counters:0,1 um:zero minimum:3000 name:EMON_UNFUSION : Number of unfusion events in the ROB, happened on a FP exception to a fused uOp
+#
+# Prefetcher
+event:0xf0 counters:0,1 um:zero minimum:3000 name:EMON_PREF_RQSTS_UP : Number of upward prefetches issued
+event:0xf8 counters:0,1 um:zero minimum:3000 name:EMON_PREF_RQSTS_DN : Number of downward prefetches issued
diff --git a/events/i386/p6_mobile/unit_masks b/events/i386/p6_mobile/unit_masks
new file mode 100644
index 0000000..2905a2b
--- /dev/null
+++ b/events/i386/p6_mobile/unit_masks
@@ -0,0 +1,47 @@
+# Pentium M possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:mesi type:bitmask default:0x0f
+ 0x08 (M)odified cache state
+ 0x04 (E)xclusive cache state
+ 0x02 (S)hared cache state
+ 0x01 (I)nvalid cache state
+ 0x0f All cache states
+ 0x10 HW prefetched line only
+ 0x20 all prefetched line w/o regarding mask 0x10.
+name:ebl type:exclusive default:0x20
+ 0x00 self-generated transactions
+ 0x20 any transactions
+name:kni_prefetch type:exclusive default:0x0
+ 0x00 prefetch NTA
+ 0x01 prefetch T1
+ 0x02 prefetch T2
+ 0x03 weakly-ordered stores
+# this bitmask can seems weirds but is correct, note there is no way to only
+# count scalar SIMD instructions
+name:sse_sse2_inst_retired type:exclusive default:0x0
+ 0x00 SSE Packed Single
+ 0x01 SSE Scalar-Single
+ 0x02 SSE2 Packed-Double
+ 0x03 SSE2 Scalar-Double
+name:mmx_uops type:mandatory default:0xf
+ 0x0f mandatory
+name:mmx_instr_type_exec type:bitmask default:0x3f
+ 0x01 MMX packed multiplies
+ 0x02 MMX packed shifts
+ 0x04 MMX pack operations
+ 0x08 MMX unpack operations
+ 0x10 MMX packed logical
+ 0x20 MMX packed arithmetic
+ 0x3f all of the above
+name:mmx_trans type:exclusive default:0x0
+ 0x00 MMX->float operations
+ 0x01 float->MMX operations
+name:freq type:exclusive default:0x0
+ 0x00 All transitions
+ 0x02 Only Frequency transitions
+name:fused type:exclusive default:0x0
+ 0x00 All fused micro-ops
+ 0x01 Only load+Op micro-ops
+ 0x02 Only std+sta micro-ops
diff --git a/events/i386/pii/events b/events/i386/pii/events
new file mode 100644
index 0000000..c5b3beb
--- /dev/null
+++ b/events/i386/pii/events
@@ -0,0 +1,80 @@
+# Pentium II events
+#
+event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted
+event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non
+event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU
+event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU
+event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU
+event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
+event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches
+event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
+event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
+event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
+event:0x28 counters:0,1 um:mesi minimum:500 name:L2_IFETCH : number of L2 instruction fetches
+event:0x29 counters:0,1 um:mesi minimum:500 name:L2_LD : number of L2 data loads
+event:0x2a counters:0,1 um:mesi minimum:500 name:L2_ST : number of L2 data stores
+event:0x24 counters:0,1 um:zero minimum:500 name:L2_LINES_IN : number of allocated lines in L2
+event:0x26 counters:0,1 um:zero minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
+event:0x25 counters:0,1 um:zero minimum:500 name:L2_M_LINES_INM : number of modified lines allocated in L2
+event:0x27 counters:0,1 um:zero minimum:500 name:L2_M_LINES_OUTM : number of modified lines removed from L2
+event:0x2e counters:0,1 um:mesi minimum:500 name:L2_RQSTS : number of L2 requests
+event:0x21 counters:0,1 um:zero minimum:500 name:L2_ADS : number of L2 address strobes
+event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
+event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
+event:0x62 counters:0,1 um:ebl minimum:500 name:BUS_DRDY_CLOCKS : number of clocks DRDY is asserted
+event:0x63 counters:0,1 um:ebl minimum:500 name:BUS_LOCK_CLOCKS : number of clocks LOCK is asserted
+event:0x60 counters:0,1 um:zero minimum:500 name:BUS_REQ_OUTSTANDING : number of outstanding bus requests
+event:0x65 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BRD : number of burst read transactions
+event:0x66 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_RFO : number of read for ownership transactions
+event:0x67 counters:0,1 um:ebl minimum:500 name:BUS_TRANS_WB : number of write back transactions
+event:0x68 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_IFETCH : number of instruction fetch transactions
+event:0x69 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_INVAL : number of invalidate transactions
+event:0x6a counters:0,1 um:ebl minimum:500 name:BUS_TRAN_PWR : number of partial write transactions
+event:0x6b counters:0,1 um:ebl minimum:500 name:BUS_TRANS_P : number of partial transactions
+event:0x6c counters:0,1 um:ebl minimum:500 name:BUS_TRANS_IO : number of I/O transactions
+event:0x6d counters:0,1 um:ebl minimum:500 name:BUS_TRANS_DEF : number of deferred transactions
+event:0x6e counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BURST : number of burst transactions
+event:0x70 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_ANY : number of all transactions
+event:0x6f counters:0,1 um:ebl minimum:500 name:BUS_TRAN_MEM : number of memory transactions
+event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data
+event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin
+event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin
+event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin
+event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall
+event:0xc1 counters:0 um:zero minimum:3000 name:COMP_FLOP_RET : number of computational FP operations retired
+event:0x10 counters:0 um:zero minimum:3000 name:FLOPS : number of computational FP operations executed
+event:0x11 counters:1 um:zero minimum:500 name:FP_ASSIST : number of FP exceptions handled by microcode
+event:0x12 counters:1 um:zero minimum:1000 name:MUL : number of multiplies
+event:0x13 counters:1 um:zero minimum:500 name:DIV : number of divides
+event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
+event:0x03 counters:0,1 um:zero minimum:500 name:LD_BLOCKS : number of store buffer blocks
+event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles
+event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
+event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0xc2 counters:0,1 um:zero minimum:6000 name:UOPS_RETIRED : number of UOPs retired
+event:0xd0 counters:0,1 um:zero minimum:6000 name:INST_DECODED : number of instructions decoded
+event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RX : number of hardware interrupts received
+event:0xc6 counters:0,1 um:zero minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled
+event:0xc7 counters:0,1 um:zero minimum:500 name:CYCLES_INT_PENDING_AND_MASKED : cycles interrupts are disabled with pending interrupts
+event:0xc4 counters:0,1 um:zero minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired
+event:0xc9 counters:0,1 um:zero minimum:500 name:BR_TAKEN_RETIRED : number of taken branches retired
+event:0xca counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_TAKEN_RET : number of taken mispredictions branches retired
+event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded
+event:0xe2 counters:0,1 um:zero minimum:500 name:BTB_MISSES : number of branches that miss the BTB
+event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches
+event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted
+event:0xa2 counters:0,1 um:zero minimum:500 name:RESOURCE_STALLS : cycles during resource related stalls
+event:0xd2 counters:0,1 um:zero minimum:500 name:PARTIAL_RAT_STALLS : cycles or events for partial stalls
+event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
+event:0xb0 counters:0,1 um:zero minimum:3000 name:MMX_INSTR_EXEC : number of MMX instructions executed
+event:0xb1 counters:0,1 um:zero minimum:3000 name:MMX_SAT_INSTR_EXEC : number of MMX saturating instructions executed
+event:0xb2 counters:0,1 um:mmx_uops minimum:3000 name:MMX_UOPS_EXEC : number of MMX UOPS executed
+event:0xb3 counters:0,1 um:mmx_instr_type_exec minimum:3000 name:MMX_INSTR_TYPE_EXEC : number of MMX packing instructions
+event:0xcc counters:0,1 um:mmx_trans minimum:3000 name:FP_MMX_TRANS : MMX-floating point transitions
+event:0xcd counters:0,1 um:zero minimum:500 name:MMX_ASSIST : number of EMMS instructions executed
+event:0xce counters:0,1 um:zero minimum:3000 name:MMX_INSTR_RET : number of MMX instructions retired
+event:0xd4 counters:0,1 um:seg_rename minimum:500 name:SEG_RENAME_STALLS : number of segment register renaming stalls
+event:0xd5 counters:0,1 um:seg_rename minimum:500 name:SEG_REG_RENAMES : number of segment register renames
+event:0xd6 counters:0,1 um:zero minimum:500 name:RET_SEG_RENAMES : number of segment register rename events retired
diff --git a/events/i386/pii/unit_masks b/events/i386/pii/unit_masks
new file mode 100644
index 0000000..cd55867
--- /dev/null
+++ b/events/i386/pii/unit_masks
@@ -0,0 +1,34 @@
+# Pentium II possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:mesi type:bitmask default:0x0f
+ 0x08 (M)odified cache state
+ 0x04 (E)xclusive cache state
+ 0x02 (S)hared cache state
+ 0x01 (I)nvalid cache state
+ 0x0f All cache states
+name:ebl type:exclusive default:0x20
+ 0x00 self-generated transactions
+ 0x20 any transactions
+name:mmx_uops type:mandatory default:0xf
+ 0x0f mandatory
+name:mmx_instr_type_exec type:bitmask default:0x3f
+ 0x01 MMX packed multiplies
+ 0x02 MMX packed shifts
+ 0x04 MMX pack operations
+ 0x08 MMX unpack operations
+ 0x10 MMX packed logical
+ 0x20 MMX packed arithmetic
+ 0x3f all of the above
+name:mmx_trans type:exclusive default:0x0
+ 0x00 MMX->float operations
+ 0x01 float->MMX operations
+name:seg_rename type:bitmask default:0xf
+ 0x1 ES register
+ 0x2 DS register
+ 0x4 FS register
+# IA manual says this is actually FS again - no mention in errata
+# but test show that is really a typo error from IA manual
+ 0x8 GS register
+ 0xf ES, DS, FS, GS registers
diff --git a/events/i386/piii/events b/events/i386/piii/events
new file mode 100644
index 0000000..e5bb41f
--- /dev/null
+++ b/events/i386/piii/events
@@ -0,0 +1,80 @@
+# Pentium III events
+#
+event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted
+event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non
+event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU
+event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU
+event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU
+event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
+event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches
+event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
+event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
+event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
+event:0x28 counters:0,1 um:mesi minimum:500 name:L2_IFETCH : number of L2 instruction fetches
+event:0x29 counters:0,1 um:mesi minimum:500 name:L2_LD : number of L2 data loads
+event:0x2a counters:0,1 um:mesi minimum:500 name:L2_ST : number of L2 data stores
+event:0x24 counters:0,1 um:zero minimum:500 name:L2_LINES_IN : number of allocated lines in L2
+event:0x26 counters:0,1 um:zero minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
+event:0x25 counters:0,1 um:zero minimum:500 name:L2_M_LINES_INM : number of modified lines allocated in L2
+event:0x27 counters:0,1 um:zero minimum:500 name:L2_M_LINES_OUTM : number of modified lines removed from L2
+event:0x2e counters:0,1 um:mesi minimum:500 name:L2_RQSTS : number of L2 requests
+event:0x21 counters:0,1 um:zero minimum:500 name:L2_ADS : number of L2 address strobes
+event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
+event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
+event:0x62 counters:0,1 um:ebl minimum:500 name:BUS_DRDY_CLOCKS : number of clocks DRDY is asserted
+event:0x63 counters:0,1 um:ebl minimum:500 name:BUS_LOCK_CLOCKS : number of clocks LOCK is asserted
+event:0x60 counters:0,1 um:zero minimum:500 name:BUS_REQ_OUTSTANDING : number of outstanding bus requests
+event:0x65 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BRD : number of burst read transactions
+event:0x66 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_RFO : number of read for ownership transactions
+event:0x67 counters:0,1 um:ebl minimum:500 name:BUS_TRANS_WB : number of write back transactions
+event:0x68 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_IFETCH : number of instruction fetch transactions
+event:0x69 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_INVAL : number of invalidate transactions
+event:0x6a counters:0,1 um:ebl minimum:500 name:BUS_TRAN_PWR : number of partial write transactions
+event:0x6b counters:0,1 um:ebl minimum:500 name:BUS_TRANS_P : number of partial transactions
+event:0x6c counters:0,1 um:ebl minimum:500 name:BUS_TRANS_IO : number of I/O transactions
+event:0x6d counters:0,1 um:ebl minimum:500 name:BUS_TRANS_DEF : number of deferred transactions
+event:0x6e counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BURST : number of burst transactions
+event:0x70 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_ANY : number of all transactions
+event:0x6f counters:0,1 um:ebl minimum:500 name:BUS_TRAN_MEM : number of memory transactions
+event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data
+event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin
+event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin
+event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin
+event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall
+event:0xc1 counters:0 um:zero minimum:3000 name:COMP_FLOP_RET : number of computational FP operations retired
+event:0x10 counters:0 um:zero minimum:3000 name:FLOPS : number of computational FP operations executed
+event:0x11 counters:1 um:zero minimum:500 name:FP_ASSIST : number of FP exceptions handled by microcode
+event:0x12 counters:1 um:zero minimum:1000 name:MUL : number of multiplies
+event:0x13 counters:1 um:zero minimum:500 name:DIV : number of divides
+event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
+event:0x03 counters:0,1 um:zero minimum:500 name:LD_BLOCKS : number of store buffer blocks
+event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles
+event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
+event:0x07 counters:0,1 um:kni_prefetch minimum:500 name:EMON_KNI_PREF_DISPATCHED : number of KNI pre-fetch/weakly ordered insns dispatched
+event:0x4b counters:0,1 um:kni_prefetch minimum:500 name:EMON_KNI_PREF_MISS : number of KNI pre-fetch/weakly ordered insns that miss all caches
+event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0xc2 counters:0,1 um:zero minimum:6000 name:UOPS_RETIRED : number of UOPs retired
+event:0xd0 counters:0,1 um:zero minimum:6000 name:INST_DECODED : number of instructions decoded
+event:0xd8 counters:0,1 um:kni_inst_retired minimum:3000 name:EMON_KNI_INST_RETIRED : number of KNI instructions retired
+event:0xd9 counters:0,1 um:kni_inst_retired minimum:3000 name:EMON_KNI_COMP_INST_RET : number of KNI computation instructions retired
+event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RX : number of hardware interrupts received
+event:0xc6 counters:0,1 um:zero minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled
+event:0xc7 counters:0,1 um:zero minimum:500 name:CYCLES_INT_PENDING_AND_MASKED : cycles interrupts are disabled with pending interrupts
+event:0xc4 counters:0,1 um:zero minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired
+event:0xc9 counters:0,1 um:zero minimum:500 name:BR_TAKEN_RETIRED : number of taken branches retired
+event:0xca counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_TAKEN_RET : number of taken mispredictions branches retired
+event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded
+event:0xe2 counters:0,1 um:zero minimum:500 name:BTB_MISSES : number of branches that miss the BTB
+event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches
+event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted
+event:0xa2 counters:0,1 um:zero minimum:500 name:RESOURCE_STALLS : cycles during resource related stalls
+event:0xd2 counters:0,1 um:zero minimum:500 name:PARTIAL_RAT_STALLS : cycles or events for partial stalls
+event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
+event:0xb1 counters:0,1 um:zero minimum:3000 name:MMX_SAT_INSTR_EXEC : number of MMX saturating instructions executed
+event:0xb2 counters:0,1 um:mmx_uops minimum:3000 name:MMX_UOPS_EXEC : number of MMX UOPS executed
+event:0xb3 counters:0,1 um:mmx_instr_type_exec minimum:3000 name:MMX_INSTR_TYPE_EXEC : number of MMX packing instructions
+event:0xcc counters:0,1 um:mmx_trans minimum:3000 name:FP_MMX_TRANS : MMX-floating point transitions
+event:0xcd counters:0,1 um:zero minimum:500 name:MMX_ASSIST : number of EMMS instructions executed
+event:0xce counters:0,1 um:zero minimum:3000 name:MMX_INSTR_RET : number of MMX instructions retired
diff --git a/events/i386/piii/unit_masks b/events/i386/piii/unit_masks
new file mode 100644
index 0000000..6fea980
--- /dev/null
+++ b/events/i386/piii/unit_masks
@@ -0,0 +1,36 @@
+# Pentium III possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:mesi type:bitmask default:0x0f
+ 0x08 (M)odified cache state
+ 0x04 (E)xclusive cache state
+ 0x02 (S)hared cache state
+ 0x01 (I)nvalid cache state
+ 0x0f All cache states
+name:ebl type:exclusive default:0x20
+ 0x00 self-generated transactions
+ 0x20 any transactions
+name:kni_prefetch type:exclusive default:0x0
+ 0x00 prefetch NTA
+ 0x01 prefetch T1
+ 0x02 prefetch T2
+ 0x03 weakly-ordered stores
+# this bitmask can seems weirds but is correct, note there is no way to only
+# count scalar SIMD instructions
+name:kni_inst_retired type:exclusive default:0x0
+ 0x00 packed and scalar
+ 0x01 packed
+name:mmx_uops type:mandatory default:0xf
+ 0x0f mandatory
+name:mmx_instr_type_exec type:bitmask default:0x3f
+ 0x01 MMX packed multiplies
+ 0x02 MMX packed shifts
+ 0x04 MMX pack operations
+ 0x08 MMX unpack operations
+ 0x10 MMX packed logical
+ 0x20 MMX packed arithmetic
+ 0x3f all of the above
+name:mmx_trans type:exclusive default:0x0
+ 0x00 MMX->float operations
+ 0x01 float->MMX operations
diff --git a/events/i386/ppro/events b/events/i386/ppro/events
new file mode 100644
index 0000000..8182bc3
--- /dev/null
+++ b/events/i386/ppro/events
@@ -0,0 +1,70 @@
+# Pentium Pro events
+#
+event:0x79 counters:0,1 um:zero minimum:6000 name:CPU_CLK_UNHALTED : clocks processor is not halted
+event:0x43 counters:0,1 um:zero minimum:500 name:DATA_MEM_REFS : all memory references, cachable and non
+event:0x45 counters:0,1 um:zero minimum:500 name:DCU_LINES_IN : total lines allocated in the DCU
+event:0x46 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_IN : number of M state lines allocated in DCU
+event:0x47 counters:0,1 um:zero minimum:500 name:DCU_M_LINES_OUT : number of M lines evicted from the DCU
+event:0x48 counters:0,1 um:zero minimum:500 name:DCU_MISS_OUTSTANDING : number of cycles while DCU miss outstanding
+event:0x80 counters:0,1 um:zero minimum:500 name:IFU_IFETCH : number of non/cachable instruction fetches
+event:0x81 counters:0,1 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
+event:0x85 counters:0,1 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses
+event:0x86 counters:0,1 um:zero minimum:500 name:IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x87 counters:0,1 um:zero minimum:500 name:ILD_STALL : cycles instruction length decoder is stalled
+event:0x28 counters:0,1 um:mesi minimum:500 name:L2_IFETCH : number of L2 instruction fetches
+event:0x29 counters:0,1 um:mesi minimum:500 name:L2_LD : number of L2 data loads
+event:0x2a counters:0,1 um:mesi minimum:500 name:L2_ST : number of L2 data stores
+event:0x24 counters:0,1 um:zero minimum:500 name:L2_LINES_IN : number of allocated lines in L2
+event:0x26 counters:0,1 um:zero minimum:500 name:L2_LINES_OUT : number of recovered lines from L2
+event:0x25 counters:0,1 um:zero minimum:500 name:L2_M_LINES_INM : number of modified lines allocated in L2
+event:0x27 counters:0,1 um:zero minimum:500 name:L2_M_LINES_OUTM : number of modified lines removed from L2
+event:0x2e counters:0,1 um:mesi minimum:500 name:L2_RQSTS : number of L2 requests
+event:0x21 counters:0,1 um:zero minimum:500 name:L2_ADS : number of L2 address strobes
+event:0x22 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY : number of cycles data bus was busy
+event:0x23 counters:0,1 um:zero minimum:500 name:L2_DBUS_BUSY_RD : cycles data bus was busy in xfer from L2 to CPU
+event:0x62 counters:0,1 um:ebl minimum:500 name:BUS_DRDY_CLOCKS : number of clocks DRDY is asserted
+event:0x63 counters:0,1 um:ebl minimum:500 name:BUS_LOCK_CLOCKS : number of clocks LOCK is asserted
+event:0x60 counters:0,1 um:zero minimum:500 name:BUS_REQ_OUTSTANDING : number of outstanding bus requests
+event:0x65 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BRD : number of burst read transactions
+event:0x66 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_RFO : number of read for ownership transactions
+event:0x67 counters:0,1 um:ebl minimum:500 name:BUS_TRANS_WB : number of write back transactions
+event:0x68 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_IFETCH : number of instruction fetch transactions
+event:0x69 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_INVAL : number of invalidate transactions
+event:0x6a counters:0,1 um:ebl minimum:500 name:BUS_TRAN_PWR : number of partial write transactions
+event:0x6b counters:0,1 um:ebl minimum:500 name:BUS_TRANS_P : number of partial transactions
+event:0x6c counters:0,1 um:ebl minimum:500 name:BUS_TRANS_IO : number of I/O transactions
+event:0x6d counters:0,1 um:ebl minimum:500 name:BUS_TRANS_DEF : number of deferred transactions
+event:0x6e counters:0,1 um:ebl minimum:500 name:BUS_TRAN_BURST : number of burst transactions
+event:0x70 counters:0,1 um:ebl minimum:500 name:BUS_TRAN_ANY : number of all transactions
+event:0x6f counters:0,1 um:ebl minimum:500 name:BUS_TRAN_MEM : number of memory transactions
+event:0x64 counters:0,1 um:zero minimum:500 name:BUS_DATA_RCV : bus cycles this processor is receiving data
+event:0x61 counters:0,1 um:zero minimum:500 name:BUS_BNR_DRV : bus cycles this processor is driving BNR pin
+event:0x7a counters:0,1 um:zero minimum:500 name:BUS_HIT_DRV : bus cycles this processor is driving HIT pin
+event:0x7b counters:0,1 um:zero minimum:500 name:BUS_HITM_DRV : bus cycles this processor is driving HITM pin
+event:0x7e counters:0,1 um:zero minimum:500 name:BUS_SNOOP_STALL : cycles during bus snoop stall
+event:0xc1 counters:0 um:zero minimum:3000 name:COMP_FLOP_RET : number of computational FP operations retired
+event:0x10 counters:0 um:zero minimum:3000 name:FLOPS : number of computational FP operations executed
+event:0x11 counters:1 um:zero minimum:500 name:FP_ASSIST : number of FP exceptions handled by microcode
+event:0x12 counters:1 um:zero minimum:1000 name:MUL : number of multiplies
+event:0x13 counters:1 um:zero minimum:500 name:DIV : number of divides
+event:0x14 counters:0 um:zero minimum:1000 name:CYCLES_DIV_BUSY : cycles divider is busy
+event:0x03 counters:0,1 um:zero minimum:500 name:LD_BLOCKS : number of store buffer blocks
+event:0x04 counters:0,1 um:zero minimum:500 name:SB_DRAINS : number of store buffer drain cycles
+event:0x05 counters:0,1 um:zero minimum:500 name:MISALIGN_MEM_REF : number of misaligned data memory references
+event:0xc0 counters:0,1 um:zero minimum:6000 name:INST_RETIRED : number of instructions retired
+event:0xc2 counters:0,1 um:zero minimum:6000 name:UOPS_RETIRED : number of UOPs retired
+event:0xd0 counters:0,1 um:zero minimum:6000 name:INST_DECODED : number of instructions decoded
+event:0xc8 counters:0,1 um:zero minimum:500 name:HW_INT_RX : number of hardware interrupts received
+event:0xc6 counters:0,1 um:zero minimum:500 name:CYCLES_INT_MASKED : cycles interrupts are disabled
+event:0xc7 counters:0,1 um:zero minimum:500 name:CYCLES_INT_PENDING_AND_MASKED : cycles interrupts are disabled with pending interrupts
+event:0xc4 counters:0,1 um:zero minimum:500 name:BR_INST_RETIRED : number of branch instructions retired
+event:0xc5 counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_RETIRED : number of mispredicted branches retired
+event:0xc9 counters:0,1 um:zero minimum:500 name:BR_TAKEN_RETIRED : number of taken branches retired
+event:0xca counters:0,1 um:zero minimum:500 name:BR_MISS_PRED_TAKEN_RET : number of taken mispredictions branches retired
+event:0xe0 counters:0,1 um:zero minimum:500 name:BR_INST_DECODED : number of branch instructions decoded
+event:0xe2 counters:0,1 um:zero minimum:500 name:BTB_MISSES : number of branches that miss the BTB
+event:0xe4 counters:0,1 um:zero minimum:500 name:BR_BOGUS : number of bogus branches
+event:0xe6 counters:0,1 um:zero minimum:500 name:BACLEARS : number of times BACLEAR is asserted
+event:0xa2 counters:0,1 um:zero minimum:500 name:RESOURCE_STALLS : cycles during resource related stalls
+event:0xd2 counters:0,1 um:zero minimum:500 name:PARTIAL_RAT_STALLS : cycles or events for partial stalls
+event:0x06 counters:0,1 um:zero minimum:500 name:SEGMENT_REG_LOADS : number of segment register loads
diff --git a/events/i386/ppro/unit_masks b/events/i386/ppro/unit_masks
new file mode 100644
index 0000000..959b8b5
--- /dev/null
+++ b/events/i386/ppro/unit_masks
@@ -0,0 +1,13 @@
+# Pentium Pro possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:mesi type:bitmask default:0x0f
+ 0x08 (M)odified cache state
+ 0x04 (E)xclusive cache state
+ 0x02 (S)hared cache state
+ 0x01 (I)nvalid cache state
+ 0x0f All cache states
+name:ebl type:exclusive default:0x20
+ 0x00 self-generated transactions
+ 0x20 any transactions
diff --git a/events/i386/westmere/events b/events/i386/westmere/events
new file mode 100644
index 0000000..d919867
--- /dev/null
+++ b/events/i386/westmere/events
@@ -0,0 +1,88 @@
+#
+# Intel "Westmere" microarchitecture core events.
+#
+# See http://ark.intel.com/ for help in identifying Westmere based CPUs
+#
+# Note the minimum counts are not discovered experimentally and could be likely
+# lowered in many cases without ill effect.
+#
+include:i386/arch_perfmon
+event:0x03 counters:0,1,2,3 um:x02 minimum:200000 name:LOAD_BLOCK : Loads that partially overlap an earlier store
+event:0x04 counters:0,1,2,3 um:x07 minimum:200000 name:SB_DRAIN : All Store buffer stall cycles
+event:0x05 counters:0,1,2,3 um:x02 minimum:200000 name:MISALIGN_MEM_REF : Misaligned store references
+event:0x06 counters:0,1,2,3 um:store_blocks minimum:200000 name:STORE_BLOCKS : Loads delayed with at-Retirement block code
+event:0x07 counters:0,1,2,3 um:x01 minimum:200000 name:PARTIAL_ADDRESS_ALIAS : False dependencies due to partial address aliasing
+event:0x08 counters:0,1,2,3 um:dtlb_load_misses minimum:200000 name:DTLB_LOAD_MISSES : DTLB load misses
+event:0x0b counters:0,1,2,3 um:mem_inst_retired minimum:2000000 name:MEM_INST_RETIRED : Memory instructions retired above 0 clocks (Precise Event)
+event:0x0c counters:0,1,2,3 um:x01 minimum:200000 name:MEM_STORE_RETIRED : Retired stores that miss the DTLB (Precise Event)
+event:0x0e counters:0,1,2,3 um:uops_issued minimum:2000000 name:UOPS_ISSUED : Uops issued
+event:0x0f counters:0,1,2,3 um:mem_uncore_retired minimum:40000 name:MEM_UNCORE_RETIRED : Load instructions retired that HIT modified data in sibling core (Precise Event)
+event:0x10 counters:0,1,2,3 um:fp_comp_ops_exe minimum:2000000 name:FP_COMP_OPS_EXE : MMX Uops
+event:0x12 counters:0,1,2,3 um:simd_int_128 minimum:200000 name:SIMD_INT_128 : 128 bit SIMD integer pack operations
+event:0x13 counters:0,1,2,3 um:load_dispatch minimum:2000000 name:LOAD_DISPATCH : All loads dispatched
+event:0x14 counters:0,1,2,3 um:arith minimum:2000000 name:ARITH : Cycles the divider is busy
+event:0x17 counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITES : Instructions written to instruction queue.
+event:0x18 counters:0,1,2,3 um:x01 minimum:2000000 name:INST_DECODED : Instructions that must be decoded by decoder 0
+event:0x19 counters:0,1,2,3 um:x01 minimum:2000000 name:TWO_UOP_INSTS_DECODED : Two Uop instructions decoded
+event:0x1e counters:0,1,2,3 um:x01 minimum:2000000 name:INST_QUEUE_WRITE_CYCLES : Cycles instructions are written to the instruction queue
+event:0x20 counters:0,1,2,3 um:x01 minimum:2000000 name:LSD_OVERFLOW : Loops that can't stream from the instruction queue
+event:0x24 counters:0,1,2,3 um:l2_rqsts minimum:200000 name:L2_RQSTS : L2 instruction fetch hits
+event:0x26 counters:0,1,2,3 um:l2_data_rqsts minimum:200000 name:L2_DATA_RQSTS : All L2 data requests
+event:0x27 counters:0,1,2,3 um:l2_write minimum:100000 name:L2_WRITE : L2 demand lock RFOs in E state
+event:0x28 counters:0,1,2,3 um:l1d_wb_l2 minimum:100000 name:L1D_WB_L2 : L1 writebacks to L2 in E state
+event:0x2e counters:0,1,2,3 um:longest_lat_cache minimum:100000 name:LONGEST_LAT_CACHE : Longest latency cache miss
+event:0x3c counters:0,1,2,3 um:cpu_clk_unhalted minimum:100000 name:CPU_CLK_UNHALTED : Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
+event:0x49 counters:0,1,2,3 um:dtlb_misses minimum:200000 name:DTLB_MISSES : DTLB misses
+event:0x4c counters:0,1 um:x01 minimum:200000 name:LOAD_HIT_PRE : Load operations conflicting with software prefetches
+event:0x4e counters:0,1 um:l1d_prefetch minimum:200000 name:L1D_PREFETCH : L1D hardware prefetch misses
+event:0x4f counters:0,1,2,3 um:x10 minimum:2000000 name:EPT : Extended Page Table walk cycles
+event:0x51 counters:0,1 um:l1d minimum:2000000 name:L1D : L1D cache lines replaced in M state
+event:0x52 counters:0,1 um:x01 minimum:2000000 name:L1D_CACHE_PREFETCH_LOCK_FB_HIT : L1D prefetch load lock accepted in fill buffer
+event:0x60 counters:0 um:offcore_requests_outstanding minimum:2000000 name:OFFCORE_REQUESTS_OUTSTANDING : Outstanding offcore reads
+event:0x63 counters:0,1 um:cache_lock_cycles minimum:2000000 name:CACHE_LOCK_CYCLES : Cycles L1D locked
+event:0x6c counters:0,1,2,3 um:x01 minimum:2000000 name:IO_TRANSACTIONS : I/O transactions
+event:0x80 counters:0,1,2,3 um:l1i minimum:2000000 name:L1I : L1I instruction fetch stall cycles
+event:0x82 counters:0,1,2,3 um:x01 minimum:200000 name:LARGE_ITLB : Large ITLB hit
+event:0x85 counters:0,1,2,3 um:itlb_misses minimum:200000 name:ITLB_MISSES : ITLB miss
+event:0x87 counters:0,1,2,3 um:ild_stall minimum:2000000 name:ILD_STALL : Any Instruction Length Decoder stall cycles
+event:0x88 counters:0,1,2,3 um:br_inst_exec minimum:200000 name:BR_INST_EXEC : Branch instructions executed
+event:0x89 counters:0,1,2,3 um:br_misp_exec minimum:20000 name:BR_MISP_EXEC : Mispredicted branches executed
+event:0xa2 counters:0,1,2,3 um:resource_stalls minimum:2000000 name:RESOURCE_STALLS : Resource related stall cycles
+event:0xa6 counters:0,1,2,3 um:x01 minimum:2000000 name:MACRO_INSTS : Macro-fused instructions decoded
+event:0xa7 counters:0,1,2,3 um:x01 minimum:2000000 name:BACLEAR_FORCE_IQ : Instruction queue forced BACLEAR
+event:0xa8 counters:0,1,2,3 um:x01 minimum:2000000 name:LSD : Cycles when uops were delivered by the LSD
+event:0xae counters:0,1,2,3 um:x01 minimum:2000000 name:ITLB_FLUSH : ITLB flushes
+event:0xb0 counters:0,1,2,3 um:offcore_requests minimum:100000 name:OFFCORE_REQUESTS : All offcore requests
+event:0xb1 counters:0,1,2,3 um:uops_executed minimum:2000000 name:UOPS_EXECUTED : Cycles Uops executed on any port (core count)
+event:0xb2 counters:0,1,2,3 um:x01 minimum:100000 name:OFFCORE_REQUESTS_SQ_FULL : Offcore requests blocked due to Super Queue full
+event:0xb3 counters:0 um:snoopq_requests_outstanding minimum:2000000 name:SNOOPQ_REQUESTS_OUTSTANDING : Outstanding snoop code requests
+event:0xb4 counters:0,1,2,3 um:snoopq_requests minimum:100000 name:SNOOPQ_REQUESTS : Snoop code requests
+event:0xb7 counters:2 um:x01 minimum:100000 name:OFFCORE_RESPONSE_ANY_DATA : REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM
+event:0xb8 counters:0,1,2,3 um:snoop_response minimum:100000 name:SNOOP_RESPONSE : Thread responded HIT to snoop
+event:0xbb counters:1 um:x01 minimum:100000 name:OFFCORE_RESPONSE_ANY_DATA : REQUEST = ANY_DATA read and RESPONSE = ANY_CACHE_DRAM
+event:0xc0 counters:0,1,2,3 um:inst_retired minimum:2000000 name:INST_RETIRED : Instructions retired (Programmable counter and Precise Event)
+event:0xc2 counters:0,1,2,3 um:uops_retired minimum:2000000 name:UOPS_RETIRED : Cycles Uops are being retired
+event:0xc3 counters:0,1,2,3 um:machine_clears minimum:20000 name:MACHINE_CLEARS : Cycles machine clear asserted
+event:0xc4 counters:0,1,2,3 um:br_inst_retired minimum:200000 name:BR_INST_RETIRED : Retired branch instructions (Precise Event)
+event:0xc5 counters:0,1,2,3 um:br_misp_retired minimum:20000 name:BR_MISP_RETIRED : Mispredicted retired branch instructions (Precise Event)
+event:0xc7 counters:0,1,2,3 um:ssex_uops_retired minimum:200000 name:SSEX_UOPS_RETIRED : SIMD Packed-Double Uops retired (Precise Event)
+event:0xc8 counters:0,1,2,3 um:x20 minimum:200000 name:ITLB_MISS_RETIRED : Retired instructions that missed the ITLB (Precise Event)
+event:0xcb counters:0,1,2,3 um:mem_load_retired minimum:200000 name:MEM_LOAD_RETIRED : Retired loads that miss the DTLB (Precise Event)
+event:0xcc counters:0,1,2,3 um:fp_mmx_trans minimum:2000000 name:FP_MMX_TRANS : All Floating Point to and from MMX transitions
+event:0xd0 counters:0,1,2,3 um:x01 minimum:2000000 name:MACRO_INSTS : Instructions decoded
+event:0xd1 counters:0,1,2,3 um:uops_decoded minimum:2000000 name:UOPS_DECODED : Stack pointer instructions decoded
+event:0xd2 counters:0,1,2,3 um:rat_stalls minimum:2000000 name:RAT_STALLS : All RAT stall cycles
+event:0xd4 counters:0,1,2,3 um:x01 minimum:2000000 name:SEG_RENAME_STALLS : Segment rename stall cycles
+event:0xd5 counters:0,1,2,3 um:x01 minimum:2000000 name:ES_REG_RENAMES : ES segment renames
+event:0xdb counters:0,1,2,3 um:x01 minimum:2000000 name:UOP_UNFUSION : Uop unfusions due to FP exceptions
+event:0xe0 counters:0,1,2,3 um:x01 minimum:2000000 name:BR_INST_DECODED : Branch instructions decoded
+event:0xe5 counters:0,1,2,3 um:x01 minimum:2000000 name:BPU_MISSED_CALL_RET : Branch prediction unit missed call or return
+event:0xe6 counters:0,1,2,3 um:baclear minimum:2000000 name:BACLEAR : BACLEAR asserted with bad target address
+event:0xe8 counters:0,1,2,3 um:bpu_clears minimum:2000000 name:BPU_CLEARS : Early Branch Prediction Unit clears
+event:0xf0 counters:0,1,2,3 um:l2_transactions minimum:200000 name:L2_TRANSACTIONS : All L2 transactions
+event:0xf1 counters:0,1,2,3 um:l2_lines_in minimum:100000 name:L2_LINES_IN : L2 lines alloacated
+event:0xf2 counters:0,1,2,3 um:l2_lines_out minimum:100000 name:L2_LINES_OUT : L2 lines evicted
+event:0xf4 counters:0,1,2,3 um:sq_misc minimum:2000000 name:SQ_MISC : Super Queue LRU hints sent to LLC
+event:0xf6 counters:0,1,2,3 um:x01 minimum:2000000 name:SQ_FULL_STALL_CYCLES : Super Queue full stall cycles
+event:0xf7 counters:0,1,2,3 um:fp_assist minimum:20000 name:FP_ASSIST : X87 Floating point assists (Precise Event)
+event:0xfd counters:0,1,2,3 um:simd_int_64 minimum:200000 name:SIMD_INT_64 : SIMD integer 64 bit pack operations
diff --git a/events/i386/westmere/unit_masks b/events/i386/westmere/unit_masks
new file mode 100644
index 0000000..66665da
--- /dev/null
+++ b/events/i386/westmere/unit_masks
@@ -0,0 +1,307 @@
+#
+# Unit masks for the Intel "Westmere" micro architecture
+#
+# See http://ark.intel.com/ for help in identifying Westmere based CPUs
+#
+include:i386/arch_perfmon
+
+name:x01 type:mandatory default:0x01
+ 0x01 No unit mask
+name:x02 type:mandatory default:0x02
+ 0x02 No unit mask
+name:x07 type:mandatory default:0x07
+ 0x07 No unit mask
+name:x10 type:mandatory default:0x10
+ 0x10 No unit mask
+name:x20 type:mandatory default:0x20
+ 0x20 No unit mask
+name:arith type:bitmask default:0x01
+ 0x01 cycles_div_busy Cycles the divider is busy
+ 0x02 mul Multiply operations executed
+name:baclear type:bitmask default:0x01
+ 0x01 clear BACLEAR asserted, regardless of cause
+ 0x02 bad_target BACLEAR asserted with bad target address
+name:bpu_clears type:bitmask default:0x01
+ 0x01 early Early Branch Prediction Unit clears
+ 0x02 late Late Branch Prediction Unit clears
+name:br_inst_exec type:bitmask default:0x7f
+ 0x01 cond Conditional branch instructions executed
+ 0x02 direct Unconditional branches executed
+ 0x04 indirect_non_call Indirect non call branches executed
+ 0x07 non_calls All non call branches executed
+ 0x08 return_near Indirect return branches executed
+ 0x10 direct_near_call Unconditional call branches executed
+ 0x20 indirect_near_call Indirect call branches executed
+ 0x30 near_calls Call branches executed
+ 0x40 taken Taken branches executed
+ 0x7f any Branch instructions executed
+name:br_inst_retired type:bitmask default:0x04
+ 0x01 conditional Retired conditional branch instructions (Precise Event)
+ 0x02 near_call Retired near call instructions (Precise Event)
+ 0x04 all_branches Retired branch instructions (Precise Event)
+name:br_misp_exec type:bitmask default:0x7f
+ 0x01 cond Mispredicted conditional branches executed
+ 0x02 direct Mispredicted unconditional branches executed
+ 0x04 indirect_non_call Mispredicted indirect non call branches executed
+ 0x07 non_calls Mispredicted non call branches executed
+ 0x08 return_near Mispredicted return branches executed
+ 0x10 direct_near_call Mispredicted non call branches executed
+ 0x20 indirect_near_call Mispredicted indirect call branches executed
+ 0x30 near_calls Mispredicted call branches executed
+ 0x40 taken Mispredicted taken branches executed
+ 0x7f any Mispredicted branches executed
+name:br_misp_retired type:bitmask default:0x04
+ 0x01 conditional Mispredicted conditional retired branches (Precise Event)
+ 0x02 near_call Mispredicted near retired calls (Precise Event)
+ 0x04 all_branches Mispredicted retired branch instructions (Precise Event)
+name:cache_lock_cycles type:bitmask default:0x01
+ 0x01 l1d_l2 Cycles L1D and L2 locked
+ 0x02 l1d Cycles L1D locked
+name:cpu_clk_unhalted type:bitmask default:0x00
+ 0x00 thread_p Cycles when thread is not halted (programmable counter)
+ 0x01 ref_p Reference base clock (133 Mhz) cycles when thread is not halted (programmable counter)
+name:dtlb_load_misses type:bitmask default:0x01
+ 0x01 any DTLB load misses
+ 0x02 walk_completed DTLB load miss page walks complete
+ 0x04 walk_cycles DTLB load miss page walk cycles
+ 0x10 stlb_hit DTLB second level hit
+ 0x20 pde_miss DTLB load miss caused by low part of address
+ 0x80 large_walk_completed DTLB load miss large page walks
+name:dtlb_misses type:bitmask default:0x01
+ 0x01 any DTLB misses
+ 0x02 walk_completed DTLB miss page walks
+ 0x04 walk_cycles DTLB miss page walk cycles
+ 0x10 stlb_hit DTLB first level misses but second level hit
+ 0x20 pde_miss DTLB misses casued by low part of address
+ 0x80 large_walk_completed DTLB miss large page walks
+name:fp_assist type:bitmask default:0x01
+ 0x01 all X87 Floating point assists (Precise Event)
+ 0x02 output X87 Floating point assists for invalid output value (Precise Event)
+ 0x04 input X87 Floating poiint assists for invalid input value (Precise Event)
+name:fp_comp_ops_exe type:bitmask default:0x01
+ 0x01 x87 Computational floating-point operations executed
+ 0x02 mmx MMX Uops
+ 0x04 sse_fp SSE and SSE2 FP Uops
+ 0x08 sse2_integer SSE2 integer Uops
+ 0x10 sse_fp_packed SSE FP packed Uops
+ 0x20 sse_fp_scalar SSE FP scalar Uops
+ 0x40 sse_single_precision SSE* FP single precision Uops
+ 0x80 sse_double_precision SSE* FP double precision Uops
+name:fp_mmx_trans type:bitmask default:0x03
+ 0x01 to_fp Transitions from MMX to Floating Point instructions
+ 0x02 to_mmx Transitions from Floating Point to MMX instructions
+ 0x03 any All Floating Point to and from MMX transitions
+name:ild_stall type:bitmask default:0x0f
+ 0x01 lcp Length Change Prefix stall cycles
+ 0x02 mru Stall cycles due to BPU MRU bypass
+ 0x04 iq_full Instruction Queue full stall cycles
+ 0x08 regen Regen stall cycles
+ 0x0f any Any Instruction Length Decoder stall cycles
+name:inst_retired type:bitmask default:0x01
+ 0x01 any_p Instructions retired (Programmable counter and Precise Event)
+ 0x02 x87 Retired floating-point operations (Precise Event)
+ 0x04 mmx Retired MMX instructions (Precise Event)
+name:itlb_misses type:bitmask default:0x01
+ 0x01 any ITLB miss
+ 0x02 walk_completed ITLB miss page walks
+ 0x04 walk_cycles ITLB miss page walk cycles
+ 0x80 large_walk_completed ITLB miss large page walks
+name:l1d type:bitmask default:0x01
+ 0x01 repl L1 data cache lines allocated
+ 0x02 m_repl L1D cache lines allocated in the M state
+ 0x04 m_evict L1D cache lines replaced in M state
+ 0x08 m_snoop_evict L1D snoop eviction of cache lines in M state
+name:l1d_prefetch type:bitmask default:0x01
+ 0x01 requests L1D hardware prefetch requests
+ 0x02 miss L1D hardware prefetch misses
+ 0x04 triggers L1D hardware prefetch requests triggered
+name:l1d_wb_l2 type:bitmask default:0x0f
+ 0x01 i_state L1 writebacks to L2 in I state (misses)
+ 0x02 s_state L1 writebacks to L2 in S state
+ 0x04 e_state L1 writebacks to L2 in E state
+ 0x08 m_state L1 writebacks to L2 in M state
+ 0x0f mesi All L1 writebacks to L2
+name:l1i type:bitmask default:0x01
+ 0x01 hits L1I instruction fetch hits
+ 0x02 misses L1I instruction fetch misses
+ 0x03 reads L1I Instruction fetches
+ 0x04 cycles_stalled L1I instruction fetch stall cycles
+name:l2_data_rqsts type:bitmask default:0xff
+ 0x01 demand_i_state L2 data demand loads in I state (misses)
+ 0x02 demand_s_state L2 data demand loads in S state
+ 0x04 demand_e_state L2 data demand loads in E state
+ 0x08 demand_m_state L2 data demand loads in M state
+ 0x0f demand_mesi L2 data demand requests
+ 0x10 prefetch_i_state L2 data prefetches in the I state (misses)
+ 0x20 prefetch_s_state L2 data prefetches in the S state
+ 0x40 prefetch_e_state L2 data prefetches in E state
+ 0x80 prefetch_m_state L2 data prefetches in M state
+ 0xf0 prefetch_mesi All L2 data prefetches
+ 0xff any All L2 data requests
+name:l2_lines_in type:bitmask default:0x07
+ 0x02 s_state L2 lines allocated in the S state
+ 0x04 e_state L2 lines allocated in the E state
+ 0x07 any L2 lines alloacated
+name:l2_lines_out type:bitmask default:0x0f
+ 0x01 demand_clean L2 lines evicted by a demand request
+ 0x02 demand_dirty L2 modified lines evicted by a demand request
+ 0x04 prefetch_clean L2 lines evicted by a prefetch request
+ 0x08 prefetch_dirty L2 modified lines evicted by a prefetch request
+ 0x0f any L2 lines evicted
+name:l2_rqsts type:bitmask default:0x01
+ 0x01 ld_hit L2 load hits
+ 0x02 ld_miss L2 load misses
+ 0x03 loads L2 requests
+ 0x04 rfo_hit L2 RFO hits
+ 0x08 rfo_miss L2 RFO misses
+ 0x0c rfos L2 RFO requests
+ 0x10 ifetch_hit L2 instruction fetch hits
+ 0x20 ifetch_miss L2 instruction fetch misses
+ 0x30 ifetches L2 instruction fetches
+ 0x40 prefetch_hit L2 prefetch hits
+ 0x80 prefetch_miss L2 prefetch misses
+ 0xaa miss All L2 misses
+ 0xc0 prefetches All L2 prefetches
+ 0xff references All L2 requests
+name:l2_transactions type:bitmask default:0x80
+ 0x01 load L2 Load transactions
+ 0x02 rfo L2 RFO transactions
+ 0x04 ifetch L2 instruction fetch transactions
+ 0x08 prefetch L2 prefetch transactions
+ 0x10 l1d_wb L1D writeback to L2 transactions
+ 0x20 fill L2 fill transactions
+ 0x40 wb L2 writeback to LLC transactions
+ 0x80 any All L2 transactions
+name:l2_write type:bitmask default:0x01
+ 0x01 rfo_i_state L2 demand store RFOs in I state (misses)
+ 0x02 rfo_s_state L2 demand store RFOs in S state
+ 0x08 rfo_m_state L2 demand store RFOs in M state
+ 0x0e rfo_hit All L2 demand store RFOs that hit the cache
+ 0x0f rfo_mesi All L2 demand store RFOs
+ 0x10 lock_i_state L2 demand lock RFOs in I state (misses)
+ 0x20 lock_s_state L2 demand lock RFOs in S state
+ 0x40 lock_e_state L2 demand lock RFOs in E state
+ 0x80 lock_m_state L2 demand lock RFOs in M state
+ 0xe0 lock_hit All demand L2 lock RFOs that hit the cache
+ 0xf0 lock_mesi All demand L2 lock RFOs
+name:load_dispatch type:bitmask default:0x07
+ 0x01 rs Loads dispatched that bypass the MOB
+ 0x02 rs_delayed Loads dispatched from stage 305
+ 0x04 mob Loads dispatched from the MOB
+ 0x07 any All loads dispatched
+name:longest_lat_cache type:bitmask default:0x01
+ 0x01 miss Longest latency cache miss
+ 0x02 reference Longest latency cache reference
+name:machine_clears type:bitmask default:0x01
+ 0x01 cycles Cycles machine clear asserted
+ 0x02 mem_order Execution pipeline restart due to Memory ordering conflicts
+ 0x04 smc Self-Modifying Code detected
+name:mem_inst_retired type:bitmask default:0x01
+ 0x01 loads Instructions retired which contains a load (Precise Event)
+ 0x02 stores Instructions retired which contains a store (Precise Event)
+ 0x10 latency_above_threshold_0 Memory instructions retired above 0 clocks (Precise Event) (MSR_INDEX: 0x03F6 MSR_VALUE: 0x0000)
+name:mem_load_retired type:bitmask default:0x01
+ 0x01 l1d_hit Retired loads that hit the L1 data cache (Precise Event)
+ 0x02 l2_hit Retired loads that hit the L2 cache (Precise Event)
+ 0x04 llc_unshared_hit Retired loads that hit valid versions in the LLC cache (Precise Event)
+ 0x08 other_core_l2_hit_hitm Retired loads that hit sibling core's L2 in modified or unmodified states (Precise Event)
+ 0x10 llc_miss Retired loads that miss the LLC cache (Precise Event)
+ 0x40 hit_lfb Retired loads that miss L1D and hit an previously allocated LFB (Precise Event)
+ 0x80 dtlb_miss Retired loads that miss the DTLB (Precise Event)
+name:mem_uncore_retired type:bitmask default:0x02
+ 0x02 local_hitm Load instructions retired that HIT modified data in sibling core (Precise Event)
+ 0x04 remote_hitm Retired loads that hit remote socket in modified state (Precise Event)
+ 0x08 local_dram_and_remote_cache_hit Load instructions retired local dram and remote cache HIT data sources (Precise Event)
+ 0x10 remote_dram Load instructions retired remote DRAM and remote home-remote cache HITM (Precise Event)
+ 0x80 uncacheable Load instructions retired IO (Precise Event)
+name:offcore_requests type:bitmask default:0x80
+ 0x01 demand_read_data Offcore demand data read requests
+ 0x02 demand_read_code Offcore demand code read requests
+ 0x04 demand_rfo Offcore demand RFO requests
+ 0x08 any_read Offcore read requests
+ 0x10 any_rfo Offcore RFO requests
+ 0x40 l1d_writeback Offcore L1 data cache writebacks
+ 0x80 any All offcore requests
+name:offcore_requests_outstanding type:bitmask default:0x08
+ 0x01 demand_read_data Outstanding offcore demand data reads
+ 0x02 demand_read_code Outstanding offcore demand code reads
+ 0x04 demand_rfo Outstanding offcore demand RFOs
+ 0x08 any_read Outstanding offcore reads
+name:rat_stalls type:bitmask default:0x0f
+ 0x01 flags Flag stall cycles
+ 0x02 registers Partial register stall cycles
+ 0x04 rob_read_port ROB read port stalls cycles
+ 0x08 scoreboard Scoreboard stall cycles
+ 0x0f any All RAT stall cycles
+name:resource_stalls type:bitmask default:0x01
+ 0x01 any Resource related stall cycles
+ 0x02 load Load buffer stall cycles
+ 0x04 rs_full Reservation Station full stall cycles
+ 0x08 store Store buffer stall cycles
+ 0x10 rob_full ROB full stall cycles
+ 0x20 fpcw FPU control word write stall cycles
+ 0x40 mxcsr MXCSR rename stall cycles
+ 0x80 other Other Resource related stall cycles
+name:simd_int_128 type:bitmask default:0x01
+ 0x01 packed_mpy 128 bit SIMD integer multiply operations
+ 0x02 packed_shift 128 bit SIMD integer shift operations
+ 0x04 pack 128 bit SIMD integer pack operations
+ 0x08 unpack 128 bit SIMD integer unpack operations
+ 0x10 packed_logical 128 bit SIMD integer logical operations
+ 0x20 packed_arith 128 bit SIMD integer arithmetic operations
+ 0x40 shuffle_move 128 bit SIMD integer shuffle/move operations
+name:simd_int_64 type:bitmask default:0x01
+ 0x01 packed_mpy SIMD integer 64 bit packed multiply operations
+ 0x02 packed_shift SIMD integer 64 bit shift operations
+ 0x04 pack SIMD integer 64 bit pack operations
+ 0x08 unpack SIMD integer 64 bit unpack operations
+ 0x10 packed_logical SIMD integer 64 bit logical operations
+ 0x20 packed_arith SIMD integer 64 bit arithmetic operations
+ 0x40 shuffle_move SIMD integer 64 bit shuffle/move operations
+name:snoopq_requests type:bitmask default:0x01
+ 0x01 data Snoop data requests
+ 0x02 invalidate Snoop invalidate requests
+ 0x04 code Snoop code requests
+name:snoopq_requests_outstanding type:bitmask default:0x01
+ 0x01 data Outstanding snoop data requests
+ 0x02 invalidate Outstanding snoop invalidate requests
+ 0x04 code Outstanding snoop code requests
+name:snoop_response type:bitmask default:0x01
+ 0x01 hit Thread responded HIT to snoop
+ 0x02 hite Thread responded HITE to snoop
+ 0x04 hitm Thread responded HITM to snoop
+name:sq_misc type:bitmask default:0x04
+ 0x04 lru_hints Super Queue LRU hints sent to LLC
+ 0x10 split_lock Super Queue lock splits across a cache line
+name:ssex_uops_retired type:bitmask default:0x01
+ 0x01 packed_single SIMD Packed-Single Uops retired (Precise Event)
+ 0x02 scalar_single SIMD Scalar-Single Uops retired (Precise Event)
+ 0x04 packed_double SIMD Packed-Double Uops retired (Precise Event)
+ 0x08 scalar_double SIMD Scalar-Double Uops retired (Precise Event)
+ 0x10 vector_integer SIMD Vector Integer Uops retired (Precise Event)
+name:store_blocks type:bitmask default:0x04
+ 0x04 at_ret Loads delayed with at-Retirement block code
+ 0x08 l1d_block Cacheable loads delayed with L1D block code
+name:uops_decoded type:bitmask default:0x01
+ 0x01 stall_cycles Cycles no Uops are decoded
+ 0x02 ms_cycles_active Uops decoded by Microcode Sequencer
+ 0x04 esp_folding Stack pointer instructions decoded
+ 0x08 esp_sync Stack pointer sync operations
+name:uops_executed type:bitmask default:0x3f
+ 0x01 port0 Uops executed on port 0
+ 0x02 port1 Uops executed on port 1
+ 0x04 port2_core Uops executed on port 2 (core count)
+ 0x08 port3_core Uops executed on port 3 (core count)
+ 0x10 port4_core Uops executed on port 4 (core count)
+ 0x1f core_active_cycles_no_port5 Cycles Uops executed on ports 0-4 (core count)
+ 0x20 port5 Uops executed on port 5
+ 0x3f core_active_cycles Cycles Uops executed on any port (core count)
+ 0x40 port015 Uops issued on ports 0, 1 or 5
+ 0x80 port234_core Uops issued on ports 2, 3 or 4
+name:uops_issued type:bitmask default:0x01
+ 0x01 any Uops issued
+ 0x02 fused Fused Uops issued
+name:uops_retired type:bitmask default:0x01
+ 0x01 active_cycles Cycles Uops are being retired
+ 0x02 retire_slots Retirement slots used (Precise Event)
+ 0x04 macro_fused Macro-fused Uops retired (Precise Event)
diff --git a/events/ia64/ia64/events b/events/ia64/ia64/events
new file mode 100644
index 0000000..8ae41dd
--- /dev/null
+++ b/events/ia64/ia64/events
@@ -0,0 +1,3 @@
+# IA-64 events
+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles
+event:0x08 counters:0,1,2,3 um:zero minimum:500 name:IA64_INST_RETIRED : IA-64 Instructions Retired
diff --git a/events/ia64/ia64/unit_masks b/events/ia64/ia64/unit_masks
new file mode 100644
index 0000000..7dd854a
--- /dev/null
+++ b/events/ia64/ia64/unit_masks
@@ -0,0 +1,4 @@
+# IA-64 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ia64/itanium/events b/events/ia64/itanium/events
new file mode 100644
index 0000000..b0ce10f
--- /dev/null
+++ b/events/ia64/itanium/events
@@ -0,0 +1,5 @@
+# IA-64 Itanium 1 events
+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles
+event:0x08 counters:0,1 um:zero minimum:500 name:IA64_INST_RETIRED : IA-64 Instructions Retired
+event:0x15 counters:0,1,2,3 um:zero minimum:500 name:IA32_INST_RETIRED : IA-32 Instructions Retired
+# FIXME: itanium doc describe a lot of other events, should we add them w/o any testing ?
diff --git a/events/ia64/itanium/unit_masks b/events/ia64/itanium/unit_masks
new file mode 100644
index 0000000..6a9f77b
--- /dev/null
+++ b/events/ia64/itanium/unit_masks
@@ -0,0 +1,4 @@
+# IA-64 Itanium 1 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ia64/itanium2/events b/events/ia64/itanium2/events
new file mode 100644
index 0000000..c979022
--- /dev/null
+++ b/events/ia64/itanium2/events
@@ -0,0 +1,267 @@
+# IA-64 Itanium 2 events
+
+# IA64_2 Basic Events, Table 11-1
+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:CPU_CYCLES : CPU Cycles
+event:0x08 counters:0,1,2,3 um:zero minimum:500 name:IA64_INST_RETIRED : IA-64 Instructions Retired
+event:0x59 counters:0,1,2,3 um:zero minimum:5000 name:IA32_INST_RETIRED : IA-32 Instructions Retired
+event:0x07 counters:0,1,2,3 um:zero minimum:500 name:IA32_ISA_TRANSITIONS : Itanium to/from IA-32 ISA Transitions
+
+# IA64_2 Instruction Disperal Events, Table 11-3
+event:0x49 counters:0,1,2,3 um:zero minimum:5000 name:DISP_STALLED : Number of cycles dispersal stalled
+event:0x4d counters:0,1,2,3 um:zero minimum:5000 name:INST_DISPERSED : Syllables Dispersed from REN to REG stage
+event:0x4e counters:0,1,2,3 um:syll_not_dispersed minimum:5000 name:SYLL_NOT_DISPERSED : Syllables not dispersed
+event:0x4f counters:0,1,2,3 um:syll_overcount minimum:5000 name:SYLL_OVERCOUNT : Syllables overcounted
+
+# IA64_2 Instruction Execution Events, Table 11-4
+event:0x58 counters:0,1,2,3 um:alat_capacity_miss minimum:5000 name:ALAT_CAPACITY_MISS : ALAT Entry Replaced
+event:0x06 counters:0,1,2,3 um:zero minimum:5000 name:FP_FAILED_FCHKF : Failed fchkf
+event:0x05 counters:0,1,2,3 um:zero minimum:5000 name:FP_FALSE_SIRSTALL : SIR stall without a trap
+event:0x0b counters:0,1,2,3 um:zero minimum:5000 name:FP_FLUSH_TO_ZERO : Result Flushed to Zero
+event:0x09 counters:0,1,2,3 um:zero minimum:5000 name:FP_OPS_RETIRED : Retired FP operations
+event:0x03 counters:0,1,2,3 um:zero minimum:5000 name:FP_TRUE_SIRSTALL : SIR stall asserted and leads to a trap
+event:0x08 counters:0,1,2,3 um:tagged_inst_retired minimum:5000 name:IA64_TAGGED_INST_RETIRED : Retired Tagged Instructions
+event:0x56 counters:0,1,2,3 um:alat_capacity_miss minimum:5000 name:INST_CHKA_LDC_ALAT : Advanced Check Loads
+event:0x57 counters:0,1,2,3 um:alat_capacity_miss minimum:5000 name:INST_FAILED_CHKA_LDC_ALAT : Failed Advanced Check Loads
+event:0x55 counters:0,1,2,3 um:alat_capacity_miss minimum:5000 name:INST_FAILED_CHKS_RETIRED : Failed Speculative Check Loads
+# To avoid duplication from other tables the following events commented out
+#event:0xcd counters:0,1,2,3 um:zero minimum:5000 name:LOADS_RETIRED : Retired Loads
+#event:0xce counters:0,1,2,3 um:zero minimum:5000 name:MISALIGNED_LOADS_RETIRED : Retired Misaligned Load Instructions
+#event:0xcf counters:0,1,2,3 um:zero minimum:5000 name:UC_LOADS_RETIRED : Retired Uncacheable Loads
+#event:0xd1 counters:0,1,2,3 um:zero minimum:5000 name:STORES_RETIRED : Retired Stores
+#event:0xd2 counters:0,1,2,3 um:zero minimum:5000 name:MISALIGNED_STORES_RETIRED : Retired Misaligned Store Instructions
+#event:0xd0 counters:0,1,2,3 um:zero minimum:5000 name:UC_STORES_RETIRED : Retired Uncacheable Stores
+event:0x50 counters:0,1,2,3 um:zero minimum:5000 name:NOPS_RETIRED : Retired NOP Instructions
+event:0x51 counters:0,1,2,3 um:zero minimum:5000 name:PREDICATE_SQUASHED_RETIRED : Instructions Squashed Due to Predicate Off`
+
+# IA64_2 Stall Events, Table 11-6
+event:0x00 counters:0,1,2,3 um:back_end_bubble minimum:5000 name:BACK_END_BUBBLE : Full pipe bubbles in main pipe
+event:0x02 counters:0,1,2,3 um:be_exe_bubble minimum:5000 name:BE_EXE_BUBBLE : Full pipe bubbles in main pipe due to Execution unit stalls
+event:0x04 counters:0,1,2,3 um:be_flush_bubble minimum:5000 name:BE_FLUSH_BUBBLE : Full pipe bubbles in main pipe due to flushes
+event:0xca counters:0,1,2,3 um:be_l1d_fpu_bubble minimum:5000 name:BE_L1D_FPU_BUBBLE : Full pipe bubbles in main pipe due to FP or L1 dcache
+# To avoid duplication from other tables the following events commented out
+#event:0x72 counters:0,1,2,3 um:be_lost_bw_due_to_fe minimum:5000 name:BE_LOST_BW_DUE_TO_FE : Invalid bundles if BE not stalled for other reasons
+event:0x01 counters:0,1,2,3 um:be_rse_bubble minimum:5000 name:BE_RSE_BUBBLE : Full pipe bubbles in main pipe due to RSE stalls
+event:0x71 counters:0,1,2,3 um:fe_bubble minimum:5000 name:FE_BUBBLE : Bubbles seen by FE
+event:0x70 counters:0,1,2,3 um:fe_lost minimum:5000 name:FE_LOST_BW : Invalid bundles at the entrance to IB
+event:0x73 counters:0,1,2,3 um:fe_lost minimum:5000 name:IDEAL_BE_LOST_BW_DUE_TO_FE : Invalid bundles at the exit from IB
+
+# IA64_2 Branch Events, Table 11-7
+event:0x61 counters:0,1,2,3 um:be_br_mispredict_detail minimum:5000 name:BE_BR_MISPRED_DETAIL : BE branch misprediction detail
+event:0x11 counters:0,1,2,3 um:zero minimum:5000 name:BRANCH_EVENT : Branch Event Captured
+event:0x5b counters:0,1,2,3 um:br_mispred_detail minimum:5000 name:BR_MISPRED_DETAIL : Branch Mispredict Detail
+event:0x68 counters:0,1,2,3 um:br_mispredict_detail2 minimum:5000 name:BR_MISPRED_DETAIL2 : FE Branch Mispredict Detail (Unknown path component)
+event:0x54 counters:0,1,2,3 um:br_path_pred minimum:5000 name:BR_PATH_PRED : FE Branch Path Prediction Detail
+event:0x6a counters:0,1,2,3 um:br_path_pred2 minimum:5000 name:BR_PATH_PRED2 : FE Branch Path Prediction Detail (Unknown prediction component)
+event:0x63 counters:0,1,2,3 um:encbr_mispred_detail minimum:5000 name:ENCBR_MISPRED_DETAIL : Number of encoded branches retired
+
+# IA64_2 L1 Instruction Cache and Prefetch Events, Table 11-8
+event:0x46 counters:0,1,2,3 um:zero minimum:5000 name:ISB_BUNPAIRS_IN : Bundle pairs written from L2 into FE
+event:0x43 counters:0,1,2,3 um:zero minimum:5000 name:L1I_EAR_EVENTS : Instruction EAR Events
+event:0x66 counters:0,1,2,3 um:zero minimum:5000 name:L1I_FETCH_ISB_HIT : "\"Just-in-time\" instruction fetch hitting in and being bypassed from ISB
+event:0x65 counters:0,1,2,3 um:zero minimum:5000 name:L1I_FETCH_RAB_HIT : Instruction fetch hitting in RAB
+event:0x41 counters:0,1,2,3 um:zero minimum:5000 name:L1I_FILLS : L1 Instruction Cache Fills
+event:0x44 counters:0,1,2,3 um:zero minimum:5000 name:L1I_PREFETCHES : Instruction Prefetch Requests
+event:0x42 counters:0,1,2,3 um:zero minimum:5000 name:L2_INST_DEMAND_READS : L1 Instruction Cache and ISB Misses
+event:0x67 counters:0,1,2,3 um:l1i_prefetch_stall minimum:5000 name:L1I_PREFETCH_STALL : Why prefetch pipeline is stalled?
+event:0x4b counters:0,1,2,3 um:zero minimum:5000 name:L1I_PURGE : L1ITLB purges handled by L1I
+event:0x69 counters:0,1,2,3 um:zero minimum:5000 name:L1I_PVAB_OVERFLOW : PVAB overflow
+event:0x64 counters:0,1,2,3 um:zero minimum:5000 name:L1I_RAB_ALMOST_FULL : Is RAB almost full?
+event:0x60 counters:0,1,2,3 um:zero minimum:500 name:L1I_RAB_FULL : Is RAB full?
+event:0x40 counters:0,1,2,3 um:zero minimum:5000 name:L1I_READS : L1 Instruction Cache Read
+event:0x4a counters:0,1,2,3 um:zero minimum:5000 name:L1I_SNOOP : Snoop requests handled by L1I
+event:0x5f counters:0,1,2,3 um:zero minimum:5000 name:L1I_STRM_PREFETCHES : L1 Instruction Cache line prefetch requests
+event:0x45 counters:0,1,2,3 um:zero minimum:5000 name:L2_INST_PREFETCHES : Instruction Prefetch Requests
+
+# IA64_2 L1 Data Cache Events, Table 11-10
+event:0xc8 counters:0,1,2,3 um:zero minimum:5000 name:DATA_EAR_EVENTS : Data Cache EAR Events
+# To avoid duplication from other tables the following events commented out
+#event:0xc2 counters:0,1,2,3 um:zero minimum:5000 name:L1D_READS_SET0 : L1 Data Cache Reads
+#event:0xc3 counters:0,1,2,3 um:zero minimum:5000 name:DATA_REFERENCES_SET0 : Data memory references issued to memory pipeline
+#event:0xc4 counters:0,1,2,3 um:zero minimum:5000 name:L1D_READS_SET1 : L1 Data Cache Reads
+#event:0xc5 counters:0,1,2,3 um:zero minimum:5000 name:DATA_REFERENCES_SET1 : Data memory references issued to memory pipeline
+#event:0xc7 counters:0,1,2,3 um:l1d_read_misses minimum:5000 name:L1D_READ_MISSES : L1 Data Cache Read Misses
+
+# IA64_2 L1 Data Cache Set 0 Events, Table 11-11
+event:0xc0 counters:1 um:zero minimum:5000 name:L1DTLB_TRANSFER : L1DTLB misses that hit in the L2DTLB for accesses counted in L1D_READS
+event:0xc1 counters:1 um:zero minimum:5000 name:L2DTLB_MISSES : L2DTLB Misses
+event:0xc2 counters:1 um:zero minimum:5000 name:L1D_READS_SET0 : L1 Data Cache Reads
+event:0xc3 counters:1 um:zero minimum:5000 name:DATA_REFERENCES_SET0 : Data memory references issued to memory pipeline
+
+# IA64_2 L1 Data Cache Set 1 Events, Table 11-12
+event:0xc4 counters:1 um:zero minimum:5000 name:L1D_READS_SET1 : L1 Data Cache Reads
+event:0xc5 counters:1 um:zero minimum:5000 name:DATA_REFERENCES_SET1 : Data memory references issued to memory pipeline
+event:0xc7 counters:1 um:l1d_read_misses minimum:5000 name:L1D_READ_MISSES : L1 Data Cache Read Misses
+
+# IA64_2 L1 Data Cache Set 2 Events, Table 11-13
+event:0xca counters:1 um:be_l1d_fpu_bubble minimum:5000 name:BE_L1D_FPU_BUBBLE : Full pipe bubbles in main pipe due to FP or L1 dcache
+
+# IA64_2 L1 Data Cache Set 3 Events, Table 11-14
+event:0xcd counters:1 um:zero minimum:5000 name:LOADS_RETIRED : Retired Loads
+event:0xce counters:1 um:zero minimum:5000 name:MISALIGNED_LOADS_RETIRED : Retired Misaligned Load Instructions
+event:0xcf counters:1 um:zero minimum:5000 name:UC_LOADS_RETIRED : Retired Uncacheable Loads
+
+# IA64_2 L1 Data Cache Set 4 Events, Table 11-15
+event:0xd1 counters:1 um:zero minimum:5000 name:STORES_RETIRED : Retired Stores
+event:0xd2 counters:1 um:zero minimum:5000 name:MISALIGNED_STORES_RETIRED : Retired Misaligned Store Instructions
+event:0xd0 counters:1 um:zero minimum:5000 name:UC_STORES_RETIRED : Retired Uncacheable Stores
+
+# IA64_2 L2 Unified Cache Events, Table 11-16
+# To avoid duplication from other tables the following events commented out
+#event:0xb9 counters:0,1,2,3 um:zero minimum:5000 name:L2_BAD_LINES_SELECTED : Valid line replaced when invalid line is available
+#event:0xb8 counters:0,1,2,3 um:l2_bypass minimum:5000 name:L2_BYPASS : Count bypass
+#event:0xb2 counters:0,1,2,3 um:l2_data_references minimum:5000 name:L2_DATA_REFERENCES : Data read/write access to L2
+event:0xbf counters:0,1,2,3 um:zero minimum:5000 name:L2_FILLB_FULL : L2D Fill buffer is full
+#event:0xb4 counters:0,1,2,3 um:l2_force_recirc minimum:5000 name:L2_FORCE_RECIRC : Forced recirculates
+event:0xba counters:0,1,2,3 um:recirc_ifetch minimum:5000 name:L2_GOT_RECIRC_IFETCH : Instruction fetch recirculates received by L2D
+#event:0xb6 counters:0,1,2,3 um:zero minimum:5000 name:L2_GOT_RECIRC_OZQ_ACC : Counts number of OZQ accesses recirculated back to L1D
+#event:0xa1 counters:0,1,2,3 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
+#event:0xa5 counters:0,1,2,3 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
+#event:0xa9 counters:0,1,2,3 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
+#event:0xad counters:0,1,2,3 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
+event:0xb9 counters:0,1,2,3 um:recirc_ifetch minimum:5000 name:L2_ISSUED_RECIRC_IFETCH : Instruction fetch recirculates issued by L2D
+#event:0xb5 counters:0,1,2,3 um:zero minimum:5000 name:L2_ISSUED_RECIRC_OZQ_ACC : Count number of times a recirculate issue was attempted and not preempted
+#event:0xb0 counters:0,1,2,3 um:l2_l3_access_cancel minimum:5000 name:L2_L3ACCESS_CANCEL : Canceled L3 accesses
+event:0xcb counters:0,1,2,3 um:zero minimum:5000 name:L2_MISSES : L2 Misses
+event:0xb8 counters:0,1,2,3 um:l2_ops_issued minimum:5000 name:L2_OPS_ISSUED : Different operations issued by L2D
+#event:0xbd counters:0,1,2,3 um:zero minimum:5000 name:L2_OZDB_FULL : L2D OZQ is full
+#event:0xa2 counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
+#event:0xa6 counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
+#event:0xaa counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
+#event:0xae counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
+#event:0xa0 counters:0,1,2,3 um:l2_ozq_cancels0 minimum:5000 name:L2_OZQ_CANCELS0 : L2 OZQ cancels
+#event:0xac counters:0,1,2,3 um:l2_ozq_cancels1 minimum:5000 name:L2_OZQ_CANCELS1 : L2 OZQ cancels
+#event:0xa8 counters:0,1,2,3 um:l2_ozq_cancels2 minimum:5000 name:L2_OZQ_CANCELS2 : L2 OZQ cancels
+#event:0xbc counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_FULL : L2D OZQ is full
+#event:0xa3 counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
+#event:0xa7 counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
+#event:0xab counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
+#event:0xaf counters:0,1,2,3 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
+#event:0xb1 counters:0,1,2,3 um:zero minimum:5000 name:L2_REFERENCES : Requests made from L2
+#event:0xba counters:0,1,2,3 um:zero minimum:5000 name:L2_STORE_HIT_SHARED : Store hit a shared line
+#event:0xb7 counters:0,1,2,3 um:zero minimum:5000 name:L2_SYNTH_PROBE : Synthesized Probe
+#event:0xbe counters:0,1,2,3 um:zero minimum:5000 name:L2_VICTIMB_FULL : L2D victim buffer is full
+
+# IA64_2 L2 Cache Events Set 0, Table 11-18
+# FIXME all sorts of restrictions on how these can be combined
+event:0xa1 counters:0 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
+event:0xa5 counters:0 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
+event:0xa9 counters:0 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
+event:0xad counters:0 um:l2_ifet_cancels minimum:5000 name:L2_IFET_CANCELS : Instruction fetch cancels by the L2.
+event:0xa2 counters:0 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
+event:0xa6 counters:0 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
+event:0xaa counters:0 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
+event:0xae counters:0 um:zero minimum:5000 name:L2_OZQ_ACQUIRE : Clocks with acquire ordering attribute existed in L2 OZQ
+event:0xa0 counters:0 um:l2_ozq_cancels0 minimum:5000 name:L2_OZQ_CANCELS0 : L2 OZQ cancels
+event:0xac counters:0 um:l2_ozq_cancels1 minimum:5000 name:L2_OZQ_CANCELS1 : L2 OZQ cancels
+event:0xa8 counters:0 um:l2_ozq_cancels2 minimum:5000 name:L2_OZQ_CANCELS2 : L2 OZQ cancels
+event:0xa3 counters:0 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
+event:0xa7 counters:0 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
+event:0xab counters:0 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
+event:0xaf counters:0 um:zero minimum:5000 name:L2_OZQ_RELEASE : Clocks with release ordering attribute existed in L2 OZQ
+
+# IA64_2 L2 Cache Events Set 1, Table 11-19
+# manual states that L2_L3ACCESS_CANCEL must be measured in PMD4.
+# FIXME Don't have any way of enforcing the constraints
+# so only l2_l3_access_cancel allowed.
+event:0xb0 counters:0 um:l2_l3_access_cancel minimum:5000 name:L2_L3ACCESS_CANCEL : Canceled L3 accesses
+#event:0xb2 counters:0,1,2,3 um:l2_data_references minimum:5000 name:L2_DATA_REFERENCES : Data read/write access to L2
+#event:0xb1 counters:0,1,2,3 um:zero minimum:5000 name:L2_REFERENCES : Requests made from L2
+
+# IA64_2 L2 Cache Events Set 2, Table 11-20
+# manual states that L2_FORCE_RECIRC must be measured in PMD4.
+# FIXME Don't have anyway of enforcing thes constraint
+# so only L2_FORCE_RECIRC allowed.
+event:0xb4 counters:0 um:l2_force_recirc minimum:5000 name:L2_FORCE_RECIRC : Forced recirculates
+#event:0xb5 counters:0,1,2,3 um:zero minimum:5000 name:L2_ISSUED_RECIRC_OZQ_ACC : Count number of times a recirculate issue was attempted and not preempted
+#event:0xb6 counters:0,1,2,3 um:zero minimum:5000 name:L2_GOT_RECIRC_OZQ_ACC : Counts number of OZQ accesses recirculated back to L1D
+#event:0xb7 counters:0,1,2,3 um:zero minimum:5000 name:L2_SYNTH_PROBE : Synthesized Probe
+
+# IA64_2 L2 Cache Events Set 3, Table 11-21
+# The manual states that all events in this set share the same umask.
+event:0xb9 counters:0 um:zero minimum:5000 name:L2_BAD_LINES_SELECTED : Valid line replaced when invalid line is available
+event:0xb8 counters:0 um:l2_bypass minimum:5000 name:L2_BYPASS : Count bypass
+event:0xba counters:0 um:zero minimum:5000 name:L2_STORE_HIT_SHARED : Store hit a shared line
+
+# IA64_2 L2 Cache Events Set 4, Table 11-22
+# The manual states one of the following needs to be in pmd4 and these events
+# share the same umask.
+event:0xba counters:0 um:recirc_ifetch minimum:5000 name:L2_GOT_RECIRC_IFETCH : Instruction fetch recirculates received by L2D
+event:0xb9 counters:0 um:recirc_ifetch minimum:5000 name:L2_ISSUED_RECIRC_IFETCH : Instruction fetch recirculates issued by L2D
+event:0xb8 counters:0 um:l2_ops_issued minimum:5000 name:L2_OPS_ISSUED : Different operations issued by L2D
+
+# IA64_2 L2 Cache Events Set 5, Table 11-23
+# manual states one of the following needs to be in pmd4 and
+# these events share the same umask
+event:0xbc counters:0 um:zero minimum:5000 name:L2_OZQ_FULL : L2D OZQ is full
+event:0xbd counters:0 um:zero minimum:5000 name:L2_OZDB_FULL : L2D OZQ is full
+event:0xbe counters:0 um:zero minimum:5000 name:L2_VICTIMB_FULL : L2D victim buffer is full
+event:0xbf counters:0 um:zero minimum:5000 name:L2_FILLB_FULL : L2D Fill buffer is full
+
+# IA64_2 L3 Cache Events, Table 11-24
+event:0xdf counters:0,1,2,3 um:zero minimum:5000 name:L3_LINES_REPLACED : Cache Lines Replaced
+event:0xdc counters:0,1,2,3 um:zero minimum:5000 name:L3_MISSES : L3 Misses
+event:0xdb counters:0,1,2,3 um:zero minimum:5000 name:L3_REFERENCES : L3 References
+event:0xdd counters:0,1,2,3 um:l3_reads minimum:5000 name:L3_READS : L3 Reads
+event:0xde counters:0,1,2,3 um:l3_writes minimum:5000 name:L3_WRITES : L3 Writes
+
+# IA64_2 System Events, Table 11-26
+event:0x13 counters:0,1,2,3 um:zero minimum:5000 name:CPU_CPL_CHANGES : Privilege Level Changes
+event:0x52 counters:0,1,2,3 um:zero minimum:5000 name:DATA_DEBUG_REGISTER_FAULT : Fault due to data debug reg. Match to load/store instruction
+event:0xc6 counters:0,1,2,3 um:zero minimum:5000 name:DATA_DEBUG_REGISTER_MATCHES : Data debug register matches data address of memory reference
+event:0x9e counters:0,1,2,3 um:extern_dp_pins_0_to_3 minimum:5000 name:EXTERN_DP_PINS_0_TO_3 : DP pins 0-3 asserted
+event:0x9f counters:0,1,2,3 um:extern_dp_pins_4_to_5 minimum:5000 name:EXTERN_DP_PINS_4_TO_5 : DP pins 4-5 asserted
+event:0x53 counters:0,1,2,3 um:zero minimum:5000 name:SERIALIZATION_EVENTS : Number of srlz.I instructions
+
+# IA64_2 TLB Events, Table 11-28
+event:0xc9 counters:0,1,2,3 um:zero minimum:5000 name:DTLB_INSERTS_HPW : Hardware Page Walker Installs to DTLB"
+event:0x2c counters:0,1,2,3 um:zero minimum:500 name:DTLB_INSERTS_HPW_RETIRED : VHPT entries inserted into DTLB by HW PW
+event:0x2d counters:0,1,2,3 um:zero minimum:500 name:HPW_DATA_REFERENCES : Data memory references to VHPT
+#event:0xc1 counters:1 um:zero minimum:5000 name:L2DTLB_MISSES : L2DTLB Misses
+event:0x48 counters:0,1,2,3 um:zero minimum:5000 name:L1ITLB_INSERTS_HPW : L1ITLB Hardware Page Walker Inserts
+event:0x47 counters:0,1,2,3 um:itlb_misses_fetch minimum:5000 name:ITLB_MISSES_FETCH : ITLB Misses Demand Fetch
+#event:0xc0 counters:1 um:zero minimum:5000 name:L1DTLB_TRANSFER : L1DTLB misses that hit in the L2DTLB for accesses counted in L1D_READS
+
+# IA64_2 System Bus Events, Table 11-30
+event:0x87 counters:0,1,2,3 um:bus minimum:5000 name:BUS_ALL : Bus Transactions
+event:0x9c counters:0,1,2,3 um:zero minimum:5000 name:BUS_BRQ_LIVE_REQ_HI : BRQ Live Requests (two most-significant-bit of the 5-bit outstanding BRQ request count)
+event:0x9b counters:0,1,2,3 um:zero minimum:5000 name:BUS_BRQ_LIVE_REQ_LO : BRQ Live Requests (three least-significant-bit of the 5-bit outstanding BRQ request count
+event:0x9d counters:0,1,2,3 um:zero minimum:5000 name:BUS_BRQ_REQ_INSERTED : BRQ Requests Inserted
+event:0x88 counters:0,1,2,3 um:zero minimum:5000 name:BUS_DATA_CYCLE : Valid data cycle on the Bus
+event:0x84 counters:0,1,2,3 um:zero minimum:5000 name:BUS_HITM : Bus Hit Modified Line Transactions
+event:0x90 counters:0,1,2,3 um:bus minimum:5000 name:BUS_IO : IA-32 Compatible IO Bus Transactions
+event:0x98 counters:0,1,2,3 um:zero minimum:5000 name:BUS_IOQ_LIVE_REQ_HI : Inorder Bus Queue Requests (two most-significant-bit of the 4-bit outstanding IOQ request count)
+event:0x97 counters:0,1,2,3 um:zero minimum:5000 name:BUS_IOQ_LIVE_REQ_LO : Inorder Bus Queue Requests (two least-significant-bit of the 4-bit outstanding IOQ request count)
+event:0x93 counters:0,1,2,3 um:bus_lock minimum:5000 name:BUS_LOCK : IA-32 Compatible Bus Lock Transactions
+event:0x8e counters:0,1,2,3 um:bus_backsnp_req minimum:5000 name:BUS_BACKSNP_REQ : Bus Back Snoop Requests
+event:0x8a counters:0,1,2,3 um:bus_memory minimum:5000 name:BUS_MEMORY : Bus Memory Transactions
+event:0x8b counters:0,1,2,3 um:bus_mem_read minimum:5000 name:BUS_MEM_READ : Full Cache line D/I memory RD, RD invalidate, and BRIL
+event:0x94 counters:0,1,2,3 um:zero minimum:5000 name:BUS_MEM_READ_OUT_HI : Outstanding memory RD transactions
+event:0x95 counters:0,1,2,3 um:zero minimum:5000 name:BUS_MEM_READ_OUT_LO : Outstanding memory RD transactions
+event:0x9a counters:0,1,2,3 um:zero minimum:5000 name:BUS_OOQ_LIVE_REQ_HI : Out-of-order Bus Queue Requests (two most-significant-bit of the 4-bit outstanding OOQ request count)
+event:0x99 counters:0,1,2,3 um:zero minimum:5000 name:BUS_OOQ_LIVE_REQ_LO : Out-of-order Bus Queue Requests (three least-significant-bit of the 4-bit outstanding OOQ request count)
+event:0x8c counters:0,1,2,3 um:bus minimum:5000 name:BUS_RD_DATA : Bus Read Data Transactions
+event:0x80 counters:0,1,2,3 um:zero minimum:5000 name:BUS_RD_HIT : Bus Read Hit Clean Non-local Cache Transactions
+event:0x81 counters:0,1,2,3 um:zero minimum:5000 name:BUS_RD_HITM : Bus Read Hit Modified Non-local Cache Transactions
+event:0x83 counters:0,1,2,3 um:zero minimum:5000 name:BUS_RD_INVAL_ALL_HITM : Bus BIL or BRIL Transaction Results in HITM
+event:0x82 counters:0,1,2,3 um:zero minimum:5000 name:BUS_RD_INVAL_HITM : Bus BIL Transaction Results in HITM
+event:0x91 counters:0,1,2,3 um:bus minimum:5000 name:BUS_RD_IO : IA-32 Compatible IO Read Transactions
+event:0x8d counters:0,1,2,3 um:bus minimum:5000 name:BUS_RD_PRTL : Bus Read Partial Transactions
+event:0x96 counters:0,1,2,3 um:zero minimum:5000 name:BUS_SNOOPQ_REQ : Bus Snoop Queue Requests
+event:0x86 counters:0,1,2,3 um:bus minimum:5000 name:BUS_SNOOPS : Bus Snoops Total
+event:0x85 counters:0,1,2,3 um:bus_snoop minimum:5000 name:BUS_SNOOPS_HITM : Bus Snoops HIT Modified Cache Line
+event:0x8f counters:0,1,2,3 um:bus_snoop minimum:5000 name:BUS_SNOOP_STALL_CYCLES : Bus Snoop Stall Cycles (from any agent)
+event:0x92 counters:0,1,2,3 um:bus_wr_wb minimum:5000 name:BUS_WR_WB : Bus Write Back Transactions
+event:0x89 counters:0,1,2,3 um:mem_read_current minimum:5000 name:MEM_READ_CURRENT : Current Mem Read Transactions On Bus
+
+# RSE Events, Table 11-34
+event:0x2b counters:0,1,2,3 um:zero minimum:500 name:RSE_CURRENT_REGS_2_TO_0 : Current RSE registers
+event:0x2a counters:0,1,2,3 um:zero minimum:500 name:RSE_CURRENT_REGS_5_TO_3 : Current RSE registers
+event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RSE_CURRENT_REGS_6 : Current RSE registers
+event:0x29 counters:0,1,2,3 um:zero minimum:500 name:RSE_DIRTY_REGS_2_TO_0 : Dirty RSE registers
+event:0x28 counters:0,1,2,3 um:zero minimum:500 name:RSE_DIRTY_REGS_5_TO_3 : Dirty RSE registers
+event:0x24 counters:0,1,2,3 um:zero minimum:500 name:RSE_DIRTY_REGS_6 : Dirty RSE registers
+event:0x32 counters:0,1,2,3 um:zero minimum:500 name:RSE_EVENT_RETIRED : Retired RSE operations
+event:0x20 counters:0,1,2,3 um:rse_references_retired minimum:500 name:RSE_REFERENCES_RETIRED : RSE Accesses
+
+# IA64 Performance Monitors Ordered by Code, Table 11-36
+event:0xbb counters:0,1,2,3 um:zero minimum:5000 name:TAGGED_L2_DATA_RETURN_POR : Tagged L2 Data Return Ports 0/1
diff --git a/events/ia64/itanium2/unit_masks b/events/ia64/itanium2/unit_masks
new file mode 100644
index 0000000..bc74f5d
--- /dev/null
+++ b/events/ia64/itanium2/unit_masks
@@ -0,0 +1,465 @@
+# IA-64 Itanium 2 possible unit masks
+#
+# The information for the following entries for the Itanium 2
+# came from Intel Itanium 2 Processor Reference Manual For
+# Software Development and Optimization, June 2002, Document
+# number 251110-001.
+
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+
+# CPU_IA64_2 Table 11-37, 11-72
+name:alat_capacity_miss type:bitmask default:0x03
+ 0x1 INT
+ 0x2 FP
+ 0x3 ALL
+
+# CPU_IA64_2 Table 11-38
+name:back_end_bubble type:exclusive default:0x00
+ 0x0 ALL
+ 0x1 FE
+ 0x2 L1D_FPU_RSE
+
+# CPU_IA64_2 Table 11-39
+name:be_br_mispredict_detail type:exclusive default:0x00
+ 0x0 ANY
+ 0x1 STG
+ 0x2 ROT
+ 0x3 PFS
+
+# CPU_IA64_2 Table 11-40
+name:be_exe_bubble type:exclusive default:0x00
+ 0x0 ALL
+ 0x1 GRALL
+ 0x2 FRALL
+ 0x3 PR
+ 0x4 ARCR
+ 0x5 GRCR
+ 0x6 CANCEL
+ 0x7 BANK_SWITCH
+ 0x8 ARCR_PR_CANCEL_BANK
+
+# CPU_IA64_2 Table 11-41
+name:be_flush_bubble type:exclusive default:0x00
+ 0x0 ALL
+ 0x1 BRU
+ 0x2 XPN
+
+# CPU_IA64_2 Table 11-42
+name:be_l1d_fpu_bubble type:exclusive default:0x00
+ 0x0 ALL
+ 0x1 FPU
+ 0x2 L1D
+ 0x3 L1D_FULLSTBUF
+ 0x4 L1D_DCURECIR
+ 0x5 L1D_HPW
+ 0x7 L1D_FILLCONF
+ 0x8 L1D_DCS
+ 0x9 L1D_L2BPRESS
+ 0xa L1D_TLB
+ 0xb L1D_LDCONF
+ 0xc L1D_LDCHK
+ 0xd L1D_NAT
+ 0xe L1D_STBUFRECIR
+ 0xf L1D_NATCONF
+
+# CPU_IA64_2 Table 11-43
+# FIXME: events using this is commented out in events
+#name:be_lost_bw_due_to_fe type:exclusive default:0x00
+# 0x0 ALL
+# 0x1 FEFLUSH
+# 0x4 UNREACHED
+# 0x5 IBFULL
+# 0x6 IMISS
+# 0x7 TLBMISS
+# 0x8 FILL_RECIRC
+# 0x9 BI
+# 0xa BRQ
+# 0xb PLP
+# 0xc BR_ILOCK
+# 0xd BUBBLE
+
+# CPU_IA64_2 Table 11-44
+name:be_rse_bubble type:exclusive default:0x00
+ 0x0 ALL
+ 0x1 BANK_SWITCH
+ 0x2 AR_DEP
+ 0x3 OVERFLOW
+ 0x4 UNDERFLOW
+ 0x5 LOADRS
+
+# CPU_IA64_2 Table 11-45
+name:br_mispred_detail type:exclusive default:0x00
+ 0x0 ALL.ALL_PRED
+ 0x1 ALL.CORRECT_PRED
+ 0x2 ALL.WRONG_PATH
+ 0x3 ALL.WRONG_TARGET
+ 0x4 IPREL.ALL_PRED
+ 0x5 IPREL.CORRECT_PRED
+ 0x6 IPREL.WRONG_PATH
+ 0x7 IPREL.WRONG_TARGET
+ 0x8 RETURN.ALL_PRED
+ 0x9 RETURN.CORRECT_PRED
+ 0xa RETURN.WRONG_PATH
+ 0xb RETURN.WRONG_TARGET
+ 0xc NRETIND.ALL_PRED
+ 0xd NRETIND.CORRECT_PRED
+ 0xe NRETIND.WRONG_PATH
+ 0xf NRETIND.WRONG_TARGET
+
+# CPU_IA64_2 Table 11-46
+name:br_mispredict_detail2 type:exclusive default:0x00
+ 0x0 ALL.ALL_UNKNOWN_PRED
+ 0x1 ALL.UKNOWN_PATH_CORRECT_PRED
+ 0x2 ALL.UKNOWN_PATH_WRONG_PATH
+ 0x4 IPREL.ALL_UNKNOWN_PRED
+ 0x5 IPREL.UNKNOWN_PATH_CORRECT_PRED
+ 0x6 IPREL.UNKNOWN_PATH_WRONG_PATH
+ 0x8 RETURN.ALL_UNKNOWN_PRED
+ 0x9 RETURN.UNKNOWN_PATH_CORRECT_PRED
+ 0xa RETURN.UNKNOWN_PATH_WRONG_PATH
+ 0xc NRETIND.ALL_UNKNOWN_PRED
+ 0xd NRETIND.UNKNOWN_PATH_CORRECT_PRED
+ 0xe NRETIND.UNKNOWN_PATH_WRONG_PATH
+
+# CPU_IA64_2 Table 11-47
+name:br_path_pred type:exclusive default:0x00
+ 0x0 ALL.MISPRED_NOTTAKEN
+ 0x1 ALL.MISPRED_TAKEN
+ 0x2 ALL.OKPRED_NOTTAKEN
+ 0x3 ALL.OKPRED_TAKEN
+ 0x4 IPREL.MISPRED_NOTTAKEN
+ 0x5 IPREL.MISPRED_TAKEN
+ 0x6 IPREL.OKPRED_NOTTAKEN
+ 0x7 IPREL.OKPRED_TAKEN
+ 0x8 RETURN.MISPRED_NOTTAKEN
+ 0x9 RETURN.MISPRED_TAKEN
+ 0xa RETURN.OKPRED_NOTTAKEN
+ 0xb RETURN.OKPRED_TAKEN
+ 0xc NRETIND.MISPRED_NOTTAKEN
+ 0xd NRETIND.MISPRED_TAKEN
+ 0xe NRETIND.OKPRED_NOTTAKEN
+ 0xf NRETIND.OKPRED_TAKEN
+
+# CPU_IA64_2 Table 11-48
+name:br_path_pred2 type:exclusive default:0x00
+ 0x0 ALL.UNKNOWNPRED_NOTTAKEN
+ 0x1 ALL.UNKNOWNPRED_TAKEN
+ 0x4 IPREL.UNKNOWNPRED_NOTTAKEN
+ 0x5 IPREL.UNKNOWNPRED__TAKEN
+ 0x8 RETURN.UNKNOWNPRED_NOTTAKEN
+ 0x9 RETURN.UNKNOWNPRED_TAKEN
+ 0xc NRETIND.UNKNOWNPRED_NOTTAKEN
+ 0xd NRETIND.UNKNOWNPRED_TAKEN
+
+# CPU_IA64_2 Table 11-49, 11-51, 11-55, 11-56, 11-57, 11-58
+name:bus type:exclusive default:0x03
+ 0x1 IO
+ 0x2 SELF
+ 0x3 ANY
+
+# CPU_IA64_2 Table 11-50 b0001
+name:bus_backsnp_req type:mandatory default:0x01
+ 0x1 0x0
+
+# CPU_IA64_2 Table 11-52
+name:bus_lock type:exclusive default:0x03
+ 0x2 SELF
+ 0x3 ANY
+
+# CPU_IA64_2 Table 11-53
+name:bus_memory type:exclusive default:0x0f
+ 0x5 EQ_128BYTEIO
+ 0x6 EQ_128BYTE_SELF
+ 0x7 EQ_128BYTE_ANY
+ 0x9 LT_128BYTEIO
+ 0xa LT_128BYTE_SELF
+ 0xb LT_128BYTE_ANY
+ 0xd ALL IO
+ 0xe ALL SELF
+ 0xf ALL ANY
+
+# CPU_IA64_2 Table 11-54
+name:bus_mem_read type:exclusive default:0x0f
+ 0x1 BIL IO
+ 0x2 BIL SELF
+ 0x3 BIL ANY
+ 0x5 BRL IO
+ 0x6 BRL SELF
+ 0x7 BRL_ANY
+ 0x9 BRIL IO
+ 0xa BRIL SELF
+ 0xb BRIL ANY
+ 0xd ALL IO
+ 0xe ALL SELF
+ 0xf ALL ANY
+
+# CPU_IA64_2 Table 11-59, 11-60
+name:bus_snoop type:exclusive default:0x03
+ 0x2 SELF
+ 0x3 ANY
+
+# CPU_IA64_2 Table 11-61
+name:bus_wr_wb type:exclusive default:0x0f
+ 0x5 EQ_128BYTE IO
+ 0x6 EQ_128BYTE SELF
+ 0x7 EQ_128BYTE ANY
+ 0xa CCASTOUT SELF
+ 0xb CCASTOUT ANY
+ 0xd ALL IO
+ 0xe ALL SELF
+ 0xf ALL ANY
+
+# CPU_IA64_2 Table 11-62
+name:encbr_mispred_detail type:exclusive default:0x0
+ 0x0 ALL.ALL_PRED
+ 0x1 ALL.CORRECT_PRED
+ 0x2 ALL.WRONG_PATH
+ 0x3 ALL.WRONG_TARGET
+ 0x8 OVERSUB.ALL_PRED
+ 0x9 OVERSUB.CORRECT_PRED
+ 0xa OVERSUB.CORRECT_PRED
+ 0xb OVERSUB.WRONGPATH
+ 0xc ALL2.ALL_PRED
+ 0xd ALL2.CORRECT_PRED
+ 0xe ALL2.WRONG_PATH
+ 0xf ALL2.WRONG_TARGET
+
+# CPU_IA64_2 Table 11-63
+name:extern_dp_pins_0_to_3 type:bitmask default:0xf
+ 0x1 PIN0
+ 0x2 PIN1
+ 0x4 PIN2
+ 0x8 PIN3
+ 0xf ALL
+
+# CPU_IA64_2 Table 11-64
+name:extern_dp_pins_4_to_5 type:bitmask default:0x03
+ 0x1 PIN4
+ 0x2 PIN5
+ 0xf ALL
+
+# CPU_IA64_2 Table 11-65
+name:fe_bubble type:exclusive default:0x0
+ 0x0 ALL
+ 0x1 FEFLUSH
+ 0x3 GROUP1
+ 0x4 GROUP2
+ 0x5 IBFULL
+ 0x6 IMISS
+ 0x7 TLBMISS
+ 0x8 FILL_RECIRC
+ 0x9 BRANCH
+ 0xa GROUP3
+ 0xb ALLBUT_FEFLUSH_BUBBLE
+ 0xc ALLBUT_IBFULL
+ 0xd BUBBLE
+
+# CPU_IA64_2 Table 11-66, 11-69*/
+name:fe_lost type:exclusive default:0x0
+ 0x0 ALL
+ 0x1 FEFLUSH
+ 0x4 UNREACHED
+ 0x5 IBFULL
+ 0x6 IMISS
+ 0x7 TLBMISS
+ 0x8 FILL_RECIRC
+ 0x9 BI
+ 0xa BRQ
+ 0xb PLP
+ 0xc BR_ILOCK
+ 0xd BUBBLE
+
+# CPU_IA64_2 Table 11-67, 11-79, 11-86, 11-90, 11-92 b0000
+# FIXME: events using this is commented out in events
+#name:this type:exclusive default:0x0
+# 0x0 THIS
+
+# CPU_IA64_2 Table 11-68
+name:tagged_inst_retired type:exclusive default:0x0
+ 0x0 IBRP0_PMB8
+ 0x1 IBRP1_PMB9
+ 0x2 IBRP2_PMC8
+ 0x3 IBRP3_PMC9
+
+# CPU_IA64_2 Table 11-73
+name:itlb_misses_fetch type:exclusive default:0x3
+ 0x1 L1ITLB
+ 0x2 L2ITLB
+ 0x3 ALL
+
+# CPU_IA64_2 Table 11-74
+name:l1d_read_misses type:exclusive default:0x0
+ 0x0 ALL
+ 0x1 RSE_FILL
+
+# CPU_IA64_2 Table 11-75
+name:l1i_prefetch_stall type:exclusive default:0x3
+ 0x2 FLOW
+ 0x3 ALL
+
+# CPU_IA64_2 Table 11-76, 11-91 b0000
+# FIXME: events using this is commented out in events
+#name:l2_lines type:exclusive default:0x0
+# 0x0 ANY
+
+# CPU_IA64_2 Table 11-77
+name:l2_bypass type:exclusive default:0x0
+ 0x0 L2_DATA1
+ 0x1 L2_DATA2
+ 0x2 L3_DATA1
+ 0x4 L2_INST1
+ 0x5 L2_INST2
+ 0x6 L3_INST1
+
+# CPU_IA64_2 Table 11-78
+# FIXME: events using this is commented out in events
+#name:l2_data_references type:bitmask default:0x3
+# 0x1 L2_DATA_READS
+# 0x2 L2_DATA_WRITES
+# 0x3 L2_ALL
+
+# CPU_IA64_2 Table 11-80
+name:l2_force_recirc type:exclusive default:0x0
+ 0x0 ANY
+ 0x1 SMC_HIT
+ 0x2 L1W
+ 0x4 TAG_NOTOK
+ 0x5 TRAN_PREF
+ 0x6 SNP_OR_L3
+ 0x8 VIC_PEND
+ 0x9 FILL_HIT
+ 0xa IPF_MISS
+ 0xb VIC_BUF_FULL
+ 0xc OZQ_MISS
+ 0xd SAME_INDEX
+ 0xe FRC_RECIRC
+
+# CPU_IA64_2 Table 11-81, 11-83 b1000
+name:recirc_ifetch type:mandatory default:0x8
+ 0x8 default:0x0} } };
+
+# CPU_IA64_2 Table 11-82
+name:l2_ifet_cancels type:exclusive default:0x0
+ 0x0 ANY
+ 0x2 BYPASS
+ 0x4 DIDNT_RECIR
+ 0x5 RECIRC_OVER_SUB
+ 0x6 ST_FILL_WB
+ 0x7 DATA_RD
+ 0x8 PREEMPT
+ 0xc CHG_PRIO
+ 0xd IFETCH_BYP
+
+# CPU_IA64_2 Table 11-84
+name:l2_l3_access_cancel type:exclusive default:0x9
+ 0x1 SPEC_L3_BYP
+ 0x2 FILLD_FULL
+ 0x5 UC_BLOCKED
+ 0x6 INV_L3_BYP
+ 0x8 EBL_REJECT
+ 0x9 ANY
+ 0xa DFETCH
+ 0xb IFETCH
+
+# CPU_IA64_2 Table 11-85
+name:l2_ops_issued type:exclusive default:0x8
+ 0x8 INT_LOAD
+ 0x9 FP_LOAD
+ 0xa RMW
+ 0xb STORE
+ 0xc NST_NLD
+
+# CPU_IA64_2 Table 11-87
+name:l2_ozq_cancels0 type:exclusive default:0x0
+ 0x0 ANY
+ 0x1 LATE_SPEC_BYP
+ 0x2 LATE_RELEASE
+ 0x3 LATE_ACQUIRE
+ 0x4 LATE_BYP_EFFRELEASE
+
+# CPU_IA64_2 Table 11-88
+name:l2_ozq_cancels1 type:exclusive default:0x1
+ 0x0 REL
+ 0x1 BANK_CONF
+ 0x2 L2D_ST_MAT
+ 0x4 SYNC
+ 0x5 HPW_IFETCH_CONF
+ 0x6 CANC_L2M_ST
+ 0x7 L1_FILL_CONF
+ 0x8 ST_FILL_CONF
+ 0x9 CCV
+ 0xa SEM
+ 0xb L2M_ST_MAT
+ 0xc MFA
+ 0xd L2A_ST_MAT
+ 0xe L1DF_L2M
+ 0xf ECC
+
+# CPU_IA64_2 Table 11-89
+name:l2_ozq_cancels2 type:exclusive default:0x0
+ 0x0 RECIRC_OVER_SUB
+ 0x1 CANC_L2C_ST
+ 0x2 L2C_ST_MAT
+ 0x3 SCRUB
+ 0x4 ACQ
+ 0x5 READ_WB_CONF
+ 0x6 OZ_DATA_CONF
+ 0x8 L2FILL_ST_CONF
+ 0x9 DIDNT_RECIRC
+ 0xa WEIRD
+ 0xc OVER_SUB
+ 0xd CANC_L2D_ST
+ 0xf D_IFET
+
+# CPU_IA64_2 Table 11-93
+name:l3_reads type:exclusive default:0x3
+ 0x1 DINST_FETCH.HIT
+ 0x2 DINST_FETCH.MISS
+ 0x3 DINST_FETCH.ALL
+ 0x5 INST_FETCH.HIT
+ 0x6 INST_FETCH.MISS
+ 0x7 INST_FETCH.ALL
+ 0x9 DATA_READ.HIT
+ 0xa DATA_READ.MISS
+ 0xb DATA_READ.ALL
+ 0xd ALL.HIT
+ 0xe ALL.MISS
+ 0xf ALL.ALL
+
+# CPU_IA64_2 Table 11-94
+name:l3_writes type:exclusive default:0x7
+ 0x5 DATA_WRITE.HIT
+ 0x6 DATA_WRITE.MISS
+ 0x7 DATA_WRITE.ALL
+ 0x9 L2_WB.HIT
+ 0xa L2_WB.MISS
+ 0xb L2_WB.ALL
+ 0xd ALL.HIT
+ 0xe ALL.MISS
+ 0xf ALL.ALL
+
+# CPU_IA64_2 Table 11-95
+name:mem_read_current type:exclusive default:0x3
+ 0x1 IO
+ 0x3 ANY
+
+# CPU_IA64_2 Table 11-96
+name:rse_references_retired type:bitmask default:0x3
+ 0x1 LOAD
+ 0x2 STORE
+ 0x3 ALL
+
+# CPU_IA64_2 Table 11-97 bitmask
+name:syll_not_dispersed type:bitmask default:0xf
+ 0x1 EXPL
+ 0x2 IMPL
+ 0x4 FE
+ 0x8 MLI
+ 0xf ALL
+
+# CPU_IA64_2 Table 11-98
+name:syll_overcount type:exclusive default:0x3
+ 0x1 EXPL
+ 0x2 IMPL
+ 0x3 ALL
diff --git a/events/mips/1004K/events b/events/mips/1004K/events
new file mode 100644
index 0000000..698ca89
--- /dev/null
+++ b/events/mips/1004K/events
@@ -0,0 +1,173 @@
+#
+# MIPS 1004K
+#
+
+# The 1004K CPUs have two performance counters.
+#
+# Even/odd counters are distinguished by setting bit 10 in the event
+# mask. The kernel masks this bit out before writing the control
+# register.
+
+#
+# Events specific to both counters
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
+event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
+
+#
+# Events specific to counter 0
+#
+event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
+event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
+event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
+event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
+event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
+event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
+event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
+event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
+event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
+
+event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
+event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
+event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
+event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
+event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
+event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
+event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
+event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
+event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
+event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
+event:0x17 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : 23-0 Exceptions taken
+event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
+event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
+event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
+
+event:0x1c counters:0 um:zero minimum:500 name:POLICY_EVENTS : 28-0 Implementation specific policy manager events
+event:0x1d counters:0 um:zero minimum:500 name:ISPRAM_EVENTS : 29-0 Implementation specific ISPRAM events
+event:0x1e counters:0 um:zero minimum:500 name:COREEXTEND_EVENTS : 30-0 Implementation specific CorExtend events
+event:0x1f counters:0 um:zero minimum:500 name:YIELD_EVENTS : 31-0 Implementation specific yield events
+
+event:0x20 counters:0 um:zero minimum:500 name:ITC_LOADS : 32-0 ITC Loads
+event:0x21 counters:0 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 33-0 Uncached load instructions
+event:0x22 counters:0 um:zero minimum:500 name:FORK_INSNS : 34-0 Fork instructions completed
+event:0x23 counters:0 um:zero minimum:500 name:CP2_ARITH_INSNS : 35-0 CP2 arithmetic instructions completed
+event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
+
+event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
+event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
+event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
+event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
+event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
+event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instructions
+event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use stall cycles
+event:0x2e counters:0 um:zero minimum:500 name:INTERLOCK_STALLS : 46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions
+event:0x2f counters:0 um:zero minimum:500 name:RELAX_STALLS : 47-0 Low power stall cycles (operations) as requested by the policy manager
+
+event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
+event:0x31 counters:0 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
+
+#
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+# Some count events, others count stall cycles.
+#
+event:0x32 counters:0 um:zero minimum:500 name:FSB_LESS_25_FULL : 50-0 FSB < 25% full
+event:0x33 counters:0 um:zero minimum:500 name:FSB_OVER_50_FULL : 51-0 FSB > 50% full
+event:0x34 counters:0 um:zero minimum:500 name:LDQ_LESS_25_FULL : 52-0 LDQ < 25% full
+event:0x35 counters:0 um:zero minimum:500 name:LDQ_OVER_50_FULL : 53-0 LDQ > 50% full
+event:0x36 counters:0 um:zero minimum:500 name:WBB_LESS_25_FULL : 54-0 WBB < 25% full
+event:0x37 counters:0 um:zero minimum:500 name:WBB_OVER_50_FULL : 55-0 WBB > 50% full
+
+event:0x38 counters:0 um:zero minimum:500 name:INTERVENTION_HIT_COUNT : 56-0 External interventions that hit in the cache
+event:0x39 counters:0 um:zero minimum:500 name:INVALIDATE_INTERVENTION_COUNT : 57-0 External invalidate (i.e. leaving a cache line in the invalid state) interventions
+event:0x3a counters:0 um:zero minimum:500 name:EVICTION_COUNT : 58-0 Cache lines written back due to cache replacement or non-coherent cache operation
+event:0x3b counters:0 um:zero minimum:500 name:MESI_INVAL_COUNT : 59-0 MESI protocol transitions into invalid state
+event:0x3c counters:0 um:zero minimum:500 name:MESI_MODIFIED_COUNT : 60-0 MESI protocol transitions into modified state
+event:0x3d counters:0 um:zero minimum:500 name:SELF_INTERVENTION_LATENCY : 61-0 Latency from miss detection to self intervention
+event:0x3e counters:0 um:zero minimum:500 name:READ_RESPONSE_LATENCY : 62-0 Read latency from miss detection until critical dword of response is returned
+
+#
+# Events specific to counter 1
+#
+event:0x402 counters:1 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 2-1 Branch mispredictions
+event:0x403 counters:1 um:zero minimum:500 name:JR_31_MISPREDICTIONS : 3-1 JR $31 mispredictions
+event:0x404 counters:1 um:zero minimum:500 name:JR_31_NO_PREDICTIONS : 4-1 JR $31 not predicted (stack mismatch).
+event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
+event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
+event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
+event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
+event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
+event:0x40a counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : 10-1 Data cache lines written back to memory
+
+event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
+event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
+event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
+event:0x410 counters:1 um:zero minimum:500 name:MIPS16_INSNS : 16-1 MIPS16 instructions completed
+event:0x411 counters:1 um:zero minimum:500 name:INT_MUL_DIV_INSNS : 17-1 Integer multiply/divide instructions completed
+event:0x412 counters:1 um:zero minimum:500 name:REPLAYED_INSNS : 18-1 Replayed instructions
+event:0x413 counters:1 um:zero minimum:500 name:SC_INSNS_FAILED : 19-1 SC instructions completed, but store failed (because the link bit had been cleared)
+event:0x414 counters:1 um:zero minimum:500 name:CACHE_HIT_PREFETCH_INSNS : 20-1 PREFETCH instructions completed with cache hit
+event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
+event:0x416 counters:1 um:zero minimum:500 name:L2_CACHE_SINGLE_BIT_ERRORS : 22-1 Single bit errors corrected in L2
+event:0x417 counters:1 um:zero minimum:500 name:SINGLE_THREADED_CYCLES : 23-1 Cycles while one and only one TC is eligible for scheduling
+event:0x418 counters:1 um:zero minimum:500 name:REFETCHED_INSNS : 24-1 Replayed instructions sent back to IFU to be refetched
+event:0x419 counters:1 um:zero minimum:500 name:ALU_STALLS : 25-1 ALU stall cycles
+event:0x41a counters:1 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 26-1 ALU-DSP saturation instructions
+event:0x41b counters:1 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 27-1 MDU-DSP saturation instructions
+
+event:0x41c counters:1 um:zero minimum:500 name:CP2_EVENTS : 28-1 Implementation specific CP2 events
+event:0x41d counters:1 um:zero minimum:500 name:DSPRAM_EVENTS : 29-1 Implementation specific DSPRAM events
+
+event:0x41f counters:1 um:zero minimum:500 name:ITC_EVENT : 31-1 Implementation specific yield event
+
+event:0x421 counters:1 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 33-1 Uncached store instructions
+event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
+event:0x424 counters:1 um:zero minimum:500 name:INTERVENTION_MISS_STALLS : 36-1 Cache coherence intervention processing stall cycles due to an earlier miss
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
+event:0x426 counters:1 um:zero minimum:500 name:FSB_INDEX_CONFLICT_STALLS : 38-1 FSB (fill/store buffer) index conflict stall cycles
+event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
+event:0x428 counters:1 um:zero minimum:500 name:ITC_STALLS : 40-1 ITC stall cycles
+event:0x429 counters:1 um:zero minimum:500 name:FPU_STALLS : 41-1 FPU stall cycles
+event:0x42a counters:1 um:zero minimum:500 name:COREEXTEND_STALLS : 42-1 CorExtend stall cycles
+event:0x42b counters:1 um:zero minimum:500 name:DSPRAM_STALLS : 43-1 DSPRAM stall cycles
+
+event:0x42d counters:1 um:zero minimum:500 name:ALU_TO_AGEN_STALLS : 45-1 ALU to AGEN stall cycles
+event:0x42e counters:1 um:zero minimum:500 name:MISPREDICTION_STALLS : 46-1 Branch mispredict stall cycles
+
+event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
+event:0x431 counters:1 um:zero minimum:500 name:EJTAG_DATA_TRIGGERS : 49-1 EJTAG Data triggerpoints
+
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+# Some count events, others count stall cycles.
+#
+event:0x432 counters:1 um:zero minimum:500 name:FSB_25_50_FULL : 50-1 FSB 25-50% full
+event:0x433 counters:1 um:zero minimum:500 name:FSB_FULL_STALLS : 51-1 FSB full pipeline stall cycles
+event:0x434 counters:1 um:zero minimum:500 name:LDQ_25_50_FULL : 52-1 LDQ 25-50% full
+event:0x435 counters:1 um:zero minimum:500 name:LDQ_FULL_STALLS : 53-1 LDQ full pipeline stall cycles
+event:0x436 counters:1 um:zero minimum:500 name:WBB_25_50_FULL : 54-1 WBB 25-50% full
+event:0x437 counters:1 um:zero minimum:500 name:WBB_FULL_STALLS : 55-1 WBB full pipeline stall cycles
+
+event:0x438 counters:1 um:zero minimum:500 name:INTERVENTION_COUNT : 56-1 External interventions
+event:0x439 counters:1 um:zero minimum:500 name:INVALIDATE_INTERVENTION_HIT_COUNT : 57-1 External invalidate interventions that hit in the cache
+event:0x43a counters:1 um:zero minimum:500 name:WRITEBACK_COUNT : 58-1 Cache lines written back due to cache replacement or any cache operation (non-coherent, self, or external coherent)
+event:0x43b counters:1 um:zero minimum:500 name:MESI_EXCLUSIVE_COUNT : 59-1 MESI protocol transitions into exclusive state
+event:0x43c counters:1 um:zero minimum:500 name:MESI_SHARED_COUNT : 60-1 MESI protocol transitions into shared state
+event:0x43d counters:1 um:zero minimum:500 name:SELF_INTERVENTION_COUNT : 61-1 Self intervention requests on miss detection
+event:0x43e counters:1 um:zero minimum:500 name:READ_RESPONSE_COUNT : 62-1 Read requests on miss detection
diff --git a/events/mips/1004K/unit_masks b/events/mips/1004K/unit_masks
new file mode 100644
index 0000000..cbba0f9
--- /dev/null
+++ b/events/mips/1004K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 1004K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/20K/events b/events/mips/20K/events
new file mode 100644
index 0000000..25428e9
--- /dev/null
+++ b/events/mips/20K/events
@@ -0,0 +1,21 @@
+#
+# MIPS 20K
+#
+# The 20K supports only one performance counter.
+#
+event:0x0 counters:0 um:zero minimum:500 name:CYCLES : CPU cycles
+event:0x1 counters:0 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
+event:0x2 counters:0 um:zero minimum:500 name:FETCH_GROUPS : Fetch groups entering CPU execution pipes
+event:0x3 counters:0 um:zero minimum:500 name:FP_INSNS_COMPLETED : Instructions completed in FPU datapath (computational event:instructions only)
+event:0x4 counters:0 um:zero minimum:500 name:TLB_REFILLS_TAKEN : Taken TLB refill exceptions
+event:0x5 counters:0 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution
+event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution
+event:0x7 counters:0 um:zero minimum:500 name:JTLB_EXCEPTIONS : Taken Joint-TLB exceptions
+event:0x8 counters:0 um:zero minimum:500 name:REPLAY_DUE_TO_LOAD_DEPENDENT_SPEC_DISPATCH : Replays due to load-dependent speculative dispatch
+event:0x9 counters:0 um:zero minimum:500 name:INSN_REQ_FROM_IFU_TO_BIU : Instruction requests from the IFU to the BIU
+event:0xa counters:0 um:zero minimum:500 name:FPU_EXCEPTIONS_TAKEN : Taken FPU exceptions
+event:0xb counters:0 um:zero minimum:500 name:REPLAYS : Total number of LSU requested replays, Load-dependent speculative dispatch or FPU exception prediction replays.
+event:0xc counters:0 um:zero minimum:500 name:RPS_MISSPREDICTS : JR instructions that mispredicted using the Return Prediction Stack (RPS)
+event:0xd counters:0 um:zero minimum:500 name:JR_INSNS_COMPLETED : JR instruction that completed execution
+event:0xe counters:0 um:zero minimum:500 name:LSU_REPLAYS : LSU requested replays
+event:0xf counters:0 um:zero minimum:500 name:INSNS_COMPLETED : Instruction that completed execution (with or without exception)
diff --git a/events/mips/20K/unit_masks b/events/mips/20K/unit_masks
new file mode 100644
index 0000000..7571a6b
--- /dev/null
+++ b/events/mips/20K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 20Kc possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/24K/events b/events/mips/24K/events
new file mode 100644
index 0000000..58b0e17
--- /dev/null
+++ b/events/mips/24K/events
@@ -0,0 +1,144 @@
+#
+# MIPS 24K
+#
+
+# The 24K CPUs have two performance counters.
+#
+# Even/odd counters are distinguished by setting bit 10 in the event
+# mask. The kernel masks this bit out before writing the control
+# register.
+
+#
+# Events specific to both counters
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
+event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
+
+#
+# Events specific to counter 0
+#
+event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
+event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
+event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
+event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
+event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
+event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
+event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
+event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
+event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
+
+event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
+event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
+event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
+event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
+event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
+event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
+event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
+event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
+event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
+event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
+event:0x17 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : 23-0 Exceptions taken
+event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 24K family microarchitecture)
+event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
+event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
+
+event:0x1d counters:0 um:zero minimum:500 name:ISPRAM_EVENTS : 29-0 Implementation specific ISPRAM events
+event:0x1e counters:0 um:zero minimum:500 name:COREEXTEND_EVENTS : 30-0 Implementation specific CorExtend events
+
+event:0x21 counters:0 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 33-0 Uncached load instructions
+event:0x23 counters:0 um:zero minimum:500 name:CP2_ARITH_INSNS : 35-0 CP2 arithmetic instructions completed
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
+event:0x26 counters:0 um:zero minimum:500 name:SYNC_STALLS : 38-0 SYNC stall cycles
+event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
+event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
+event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
+event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
+event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
+event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instructions
+event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use stall cycles
+event:0x2e counters:0 um:zero minimum:500 name:INTERLOCK_STALLS : 46-0 Stall cycles due to return data from MFC0 and RDHWR instructions
+
+event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
+event:0x31 counters:0 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
+
+#
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+#
+event:0x32 counters:0 um:zero minimum:500 name:FSB_LESS_25_FULL : 50-0 FSB < 25% full
+event:0x33 counters:0 um:zero minimum:500 name:FSB_OVER_50_FULL : 51-0 FSB > 50% full
+event:0x34 counters:0 um:zero minimum:500 name:LDQ_LESS_25_FULL : 52-0 LDQ < 25% full
+event:0x35 counters:0 um:zero minimum:500 name:LDQ_OVER_50_FULL : 53-0 LDQ > 50% full
+event:0x36 counters:0 um:zero minimum:500 name:WBB_LESS_25_FULL : 54-0 WBB < 25% full
+event:0x37 counters:0 um:zero minimum:500 name:WBB_OVER_50_FULL : 55-0 WBB > 50% full
+
+#
+# Events specific to counter 1
+#
+event:0x402 counters:1 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 2-1 Branch mispredictions
+event:0x403 counters:1 um:zero minimum:500 name:JR_31_MISPREDICTIONS : 3-1 JR $31 mispredictions
+event:0x404 counters:1 um:zero minimum:500 name:JR_31_NO_PREDICTIONS : 4-1 JR $31 not predicted (stack mismatch).
+event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
+event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
+event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
+event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
+event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
+event:0x40a counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : 10-1 Data cache lines written back to memory
+event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
+event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
+event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
+event:0x410 counters:1 um:zero minimum:500 name:MIPS16_INSNS : 16-1 MIPS16 instructions completed
+event:0x411 counters:1 um:zero minimum:500 name:INT_MUL_DIV_INSNS : 17-1 Integer multiply/divide instructions completed
+event:0x412 counters:1 um:zero minimum:500 name:REPLAYED_INSNS : 18-1 Replayed instructions
+event:0x413 counters:1 um:zero minimum:500 name:SC_INSNS_FAILED : 19-1 SC instructions completed, but store failed (because the link bit had been cleared)
+event:0x414 counters:1 um:zero minimum:500 name:CACHE_HIT_PREFETCH_INSNS : 20-1 PREFETCH instructions completed with cache hit
+event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
+event:0x416 counters:1 um:zero minimum:500 name:L2_CACHE_SINGLE_BIT_ERRORS : 22-1 Single bit errors corrected in L2
+
+event:0x419 counters:1 um:zero minimum:500 name:ALU_STALLS : 25-1 ALU stall cycles
+event:0x41a counters:1 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 26-1 ALU-DSP saturation instructions
+event:0x41b counters:1 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 27-1 MDU-DSP saturation instructions
+
+event:0x41c counters:1 um:zero minimum:500 name:CP2_EVENTS : 28-1 Implementation specific CP2 events
+event:0x41d counters:1 um:zero minimum:500 name:DSPRAM_EVENTS : 29-1 Implementation specific DSPRAM events
+
+event:0x421 counters:1 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 33-1 Uncached store instructions
+event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
+event:0x426 counters:1 um:zero minimum:500 name:FSB_INDEX_CONFLICT_STALLS : 38-1 FSB (fill/store buffer) index conflict stall cycles
+event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
+event:0x429 counters:1 um:zero minimum:500 name:FPU_STALLS : 41-1 FPU stall cycles
+event:0x42a counters:1 um:zero minimum:500 name:COREEXTEND_STALLS : 42-1 CorExtend stall cycles
+event:0x42b counters:1 um:zero minimum:500 name:DSPRAM_STALLS : 43-1 DSPRAM stall cycles
+
+event:0x42d counters:1 um:zero minimum:500 name:ALU_TO_AGEN_STALLS : 45-1 ALU to AGEN stall cycles
+event:0x42e counters:1 um:zero minimum:500 name:MISPREDICTION_STALLS : 46-1 Branch mispredict stall cycles
+
+event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
+event:0x431 counters:1 um:zero minimum:500 name:EJTAG_DATA_TRIGGERS : 49-1 EJTAG Data triggerpoints
+
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+# Some count events, others count stall cycles.
+#
+event:0x432 counters:1 um:zero minimum:500 name:FSB_25_50_FULL : 50-1 FSB 25-50% full
+event:0x433 counters:1 um:zero minimum:500 name:FSB_FULL_STALLS : 51-1 FSB full pipeline stall cycles
+event:0x434 counters:1 um:zero minimum:500 name:LDQ_25_50_FULL : 52-1 LDQ 25-50% full
+event:0x435 counters:1 um:zero minimum:500 name:LDQ_FULL_STALLS : 53-1 LDQ full pipeline stall cycles
+event:0x436 counters:1 um:zero minimum:500 name:WBB_25_50_FULL : 54-1 WBB 25-50% full
+event:0x437 counters:1 um:zero minimum:500 name:WBB_FULL_STALLS : 55-1 WBB full pipeline stall cycles
diff --git a/events/mips/24K/unit_masks b/events/mips/24K/unit_masks
new file mode 100644
index 0000000..70d028a
--- /dev/null
+++ b/events/mips/24K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 24K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/25K/events b/events/mips/25K/events
new file mode 100644
index 0000000..4000678
--- /dev/null
+++ b/events/mips/25K/events
@@ -0,0 +1,81 @@
+#
+# MIPS 25Kf
+#
+# The 25Kf has two performance counters
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : CPU cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
+event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued
+event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued
+event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued
+event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued
+event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued
+event:0x7 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual-issued pairs
+event:0x8 counters:0,1 um:zero minimum:500 name:INSNS_COMPLETE : Instruction that completed execution (with or without exception)
+event:0x9 counters:0,1 um:zero minimum:500 name:FETCH_GROUPS_IN_PIPE : Fetch groups entering CPU execution pipes
+
+#
+# FPU:
+#
+event:0xa counters:0,1 um:zero minimum:500 name:INSN_FP_DATAPATH_COMPLETED : Instructions completed in FPU datapath (computational instructions only)
+event:0xb counters:0,1 um:zero minimum:500 name:FP_EXCEPTIONS_TAKEN : Taken FPU exceptions
+event:0xc counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_PREDICTED : Predicted FPU exceptions
+
+#
+# Branch/Jump Prediction:
+#
+event:0xd counters:0,1 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution
+event:0xe counters:0,1 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution
+event:0xf counters:0,1 um:zero minimum:500 name:JR_RPD_MISSPREDICTED : JR instructions that mispredicted using the Return Prediction Stack
+event:0x10 counters:0,1 um:zero minimum:500 name:JR_COMPLETED : JR instruction that completed execution
+
+#
+# Memory Management:
+#
+event:0x11 counters:0,1 um:zero minimum:500 name:UTLB_MISSES : U-TLB misses
+event:0x12 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_IFETCH : Raw count of Joint-TLB misses for instruction fetch
+event:0x13 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_LOADS_STORES : Raw count of Joint-TLB misses for loads/stores
+event:0x14 counters:0,1 um:zero minimum:500 name:JTLB_EXCEPTIONS : Refill, Invalid and Modified TLB exceptions
+
+#
+# Machine Check
+#
+event:0x15 counters:0,1 um:zero minimum:500 name:JTLB_IFETCH_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to instruction fetch
+event:0x16 counters:0,1 um:zero minimum:500 name:JTLB_DATA_ACCESS_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to data access
+event:0x17 counters:0,1 um:zero minimum:500 name:JTLB_REFILL_EXCEPTIONS : total Joint-TLB Instruction exceptions (refill)
+
+#
+# I-Cache Efficiency:
+#
+event:0x18 counters:0,1 um:zero minimum:500 name:INSNS_FETCHED_FROM_ICACHE : Total number of instructions fetched from the I-Cache
+event:0x19 counters:0,1 um:zero minimum:500 name:INSN_REQ_FROM_IFU_BIU : instruction requests from the IFU to the BIU
+event:0x1a counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : I-Cache miss
+
+#
+# D-Cache Efficiency:
+#
+event:0x1b counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : D-Cache miss
+event:0x1c counters:0,1 um:zero minimum:500 name:DCACHE_WRITEBACKS : D-Cache number of write-backs
+event:0x1d counters:0,1 um:zero minimum:500 name:CACHEABLE_DCACHE_REQUEST : number of cacheable requests to D-Cache
+
+#
+# Level 2 Cache Efficiency:
+#
+event:0x1e counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 Cache miss
+event:0x1f counters:0,1 um:zero minimum:500 name:L2_WBACKS : L2 Cache number of write-backs
+event:0x20 counters:0,1 um:zero minimum:500 name:CACHEABLE_L2_REQS : Number of cacheable requests to L2
+
+#
+# Replays:
+#
+event:0x21 counters:0,1 um:zero minimum:500 name:REPLAYS_LSU_LOAD_DEP_FPU : LSU requested replays, load-dependent speculative dispatch, FPU exception prediction
+event:0x22 counters:0,1 um:zero minimum:500 name:LSU_REQ_REPLAYS : LSU requested replays
+event:0x23 counters:0,1 um:zero minimum:500 name:REPLAYS_LOAD_DEP_DISPATCH : replays due to load-dependent speculative dispatch
+event:0x24 counters:0,1 um:zero minimum:500 name:REPLAYS_WBB_FULL : replays due to WBB full
+event:0x25 counters:0,1 um:zero minimum:500 name:FSB_FULL_REPLAYS : replays due to FSB full
+
+#
+# Misc:
+#
+event:0x26 counters:0,1 um:zero minimum:500 name:ICACHE_PSEUDO_HITS : I-Cache pseudo-hits
+event:0x27 counters:0,1 um:zero minimum:500 name:LOAD_STORE_ISSUED : Load/store instructions issued
diff --git a/events/mips/25K/unit_masks b/events/mips/25K/unit_masks
new file mode 100644
index 0000000..0854781
--- /dev/null
+++ b/events/mips/25K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 25Kf possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/34K/events b/events/mips/34K/events
new file mode 100644
index 0000000..d161556
--- /dev/null
+++ b/events/mips/34K/events
@@ -0,0 +1,158 @@
+#
+# MIPS 34K
+#
+
+# The 34K CPUs have two performance counters.
+#
+# Even/odd counters are distinguished by setting bit 10 in the event
+# mask. The kernel masks this bit out before writing the control
+# register.
+
+#
+# Events specific to both counters
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
+event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
+
+#
+# Events specific to counter 0
+#
+event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
+event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
+event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
+event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
+event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
+event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
+event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
+event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
+event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
+
+event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
+event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
+event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
+event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
+event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
+event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
+event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
+event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
+event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
+event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
+event:0x17 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : 23-0 Exceptions taken
+event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
+event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
+event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
+
+event:0x1c counters:0 um:zero minimum:500 name:POLICY_EVENTS : 28-0 Implementation specific policy manager events
+event:0x1d counters:0 um:zero minimum:500 name:ISPRAM_EVENTS : 29-0 Implementation specific ISPRAM events
+event:0x1e counters:0 um:zero minimum:500 name:COREEXTEND_EVENTS : 30-0 Implementation specific CorExtend events
+event:0x1f counters:0 um:zero minimum:500 name:YIELD_EVENTS : 31-0 Implementation specific yield events
+
+event:0x20 counters:0 um:zero minimum:500 name:ITC_LOADS : 32-0 ITC Loads
+event:0x21 counters:0 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 33-0 Uncached load instructions
+event:0x22 counters:0 um:zero minimum:500 name:FORK_INSNS : 34-0 Fork instructions completed
+event:0x23 counters:0 um:zero minimum:500 name:CP2_ARITH_INSNS : 35-0 CP2 arithmetic instructions completed
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
+
+event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
+event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
+event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
+event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
+event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
+event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instructions
+event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use stall cycles
+event:0x2e counters:0 um:zero minimum:500 name:INTERLOCK_STALLS : 46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions
+event:0x2f counters:0 um:zero minimum:500 name:RELAX_STALLS : 47-0 Low power stall cycles (operations) as requested by the policy manager
+
+event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
+event:0x31 counters:0 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
+
+#
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+#
+event:0x32 counters:0 um:zero minimum:500 name:FSB_LESS_25_FULL : 50-0 FSB < 25% full
+event:0x33 counters:0 um:zero minimum:500 name:FSB_OVER_50_FULL : 51-0 FSB > 50% full
+event:0x34 counters:0 um:zero minimum:500 name:LDQ_LESS_25_FULL : 52-0 LDQ < 25% full
+event:0x35 counters:0 um:zero minimum:500 name:LDQ_OVER_50_FULL : 53-0 LDQ > 50% full
+event:0x36 counters:0 um:zero minimum:500 name:WBB_LESS_25_FULL : 54-0 WBB < 25% full
+event:0x37 counters:0 um:zero minimum:500 name:WBB_OVER_50_FULL : 55-0 WBB > 50% full
+
+event:0x3e counters:0 um:zero minimum:500 name:READ_RESPONSE_LATENCY : 62-0 Read latency from miss detection until critical dword of response is returned
+
+#
+# Events specific to counter 1
+#
+event:0x402 counters:1 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 2-1 Branch mispredictions
+event:0x403 counters:1 um:zero minimum:500 name:JR_31_MISPREDICTIONS : 3-1 JR $31 mispredictions
+event:0x404 counters:1 um:zero minimum:500 name:JR_31_NO_PREDICTIONS : 4-1 JR $31 not predicted (stack mismatch).
+event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
+event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
+event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
+event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
+event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
+event:0x40a counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : 10-1 Data cache lines written back to memory
+
+event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
+event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
+event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
+event:0x410 counters:1 um:zero minimum:500 name:MIPS16_INSNS : 16-1 MIPS16 instructions completed
+event:0x411 counters:1 um:zero minimum:500 name:INT_MUL_DIV_INSNS : 17-1 Integer multiply/divide instructions completed
+event:0x412 counters:1 um:zero minimum:500 name:REPLAYED_INSNS : 18-1 Replayed instructions
+event:0x413 counters:1 um:zero minimum:500 name:SC_INSNS_FAILED : 19-1 SC instructions completed, but store failed (because the link bit had been cleared)
+event:0x414 counters:1 um:zero minimum:500 name:CACHE_HIT_PREFETCH_INSNS : 20-1 PREFETCH instructions completed with cache hit
+event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
+event:0x416 counters:1 um:zero minimum:500 name:L2_CACHE_SINGLE_BIT_ERRORS : 22-1 Single bit errors corrected in L2
+event:0x417 counters:1 um:zero minimum:500 name:SINGLE_THREADED_CYCLES : 23-1 Cycles while one and only one TC is eligible for scheduling
+event:0x418 counters:1 um:zero minimum:500 name:REFETCHED_INSNS : 24-1 Replayed instructions sent back to IFU to be refetched
+event:0x419 counters:1 um:zero minimum:500 name:ALU_STALLS : 25-1 ALU stall cycles
+event:0x41a counters:1 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 26-1 ALU-DSP saturation instructions
+event:0x41b counters:1 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 27-1 MDU-DSP saturation instructions
+
+event:0x41c counters:1 um:zero minimum:500 name:CP2_EVENTS : 28-1 Implementation specific CP2 events
+event:0x41d counters:1 um:zero minimum:500 name:DSPRAM_EVENTS : 29-1 Implementation specific DSPRAM events
+
+event:0x41f counters:1 um:zero minimum:500 name:ITC_EVENT : 31-1 Implementation specific yield event
+
+event:0x421 counters:1 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 33-1 Uncached store instructions
+event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
+
+event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
+event:0x428 counters:1 um:zero minimum:500 name:ITC_STALLS : 40-1 ITC stall cycles
+event:0x429 counters:1 um:zero minimum:500 name:FPU_STALLS : 41-1 FPU stall cycles
+event:0x42a counters:1 um:zero minimum:500 name:COREEXTEND_STALLS : 42-1 CorExtend stall cycles
+event:0x42b counters:1 um:zero minimum:500 name:DSPRAM_STALLS : 43-1 DSPRAM stall cycles
+
+event:0x42d counters:1 um:zero minimum:500 name:ALU_TO_AGEN_STALLS : 45-1 ALU to AGEN stall cycles
+event:0x42e counters:1 um:zero minimum:500 name:MISPREDICTION_STALLS : 46-1 Branch mispredict stall cycles
+
+event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
+event:0x431 counters:1 um:zero minimum:500 name:EJTAG_DATA_TRIGGERS : 49-1 EJTAG Data triggerpoints
+
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+# Some count events, others count stall cycles.
+#
+event:0x432 counters:1 um:zero minimum:500 name:FSB_25_50_FULL : 50-1 FSB 25-50% full
+event:0x433 counters:1 um:zero minimum:500 name:FSB_FULL_STALLS : 51-1 FSB full pipeline stall cycles
+event:0x434 counters:1 um:zero minimum:500 name:LDQ_25_50_FULL : 52-1 LDQ 25-50% full
+event:0x435 counters:1 um:zero minimum:500 name:LDQ_FULL_STALLS : 53-1 LDQ full pipeline stall cycles
+event:0x436 counters:1 um:zero minimum:500 name:WBB_25_50_FULL : 54-1 WBB 25-50% full
+event:0x437 counters:1 um:zero minimum:500 name:WBB_FULL_STALLS : 55-1 WBB full pipeline stall cycles
+
+event:0x43e counters:1 um:zero minimum:500 name:READ_RESPONSE_COUNT : 62-1 Read requests on miss detection
diff --git a/events/mips/34K/unit_masks b/events/mips/34K/unit_masks
new file mode 100644
index 0000000..6431af8
--- /dev/null
+++ b/events/mips/34K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 34K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/5K/events b/events/mips/5K/events
new file mode 100644
index 0000000..05874fd
--- /dev/null
+++ b/events/mips/5K/events
@@ -0,0 +1,36 @@
+#
+# MIPS 5K
+#
+# As standard the CPU supports 2 performance counters. Event 0, 2, 3 and 4
+# are available on both counters; the INSNS_EXECED is available on counter 0
+# as event 0 and on counter 1 as event 1; the remaining are counter-specific.
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
+event:0x2 counters:0,1 um:zero minimum:500 name:LOADS_EXECED : Load/pref(x)/sync/cache-ops executed
+event:0x3 counters:0,1 um:zero minimum:500 name:STORES_EXECED : Stores (including conditional stores) executed
+event:0x4 counters:0,1 um:zero minimum:500 name:COND_STORES_EXECED : Conditional stores executed
+
+#
+# Events specific to counter 0
+#
+event:0x1 counters:0 um:zero minimum:500 name:INSN_FETCHED : Instructions fetched
+event:0x5 counters:0 um:zero minimum:500 name:FAILED_COND_STORES : Failed conditional stores
+event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_EXECED : Branches executed
+event:0x7 counters:0 um:zero minimum:500 name:ITLB_MISSES : ITLB miss
+event:0x8 counters:0 um:zero minimum:500 name:DTLB_MISSES : DTLB miss
+event:0x9 counters:0 um:zero minimum:500 name:ICACHE_MISS : Instruction cache miss
+event:0xa counters:0 um:zero minimum:500 name:INSN_SCHEDULED : Instruction scheduled
+event:0xe counters:0 um:zero minimum:500 name:DUAL_ISSUED_INSNS : Dual issued instructions executed
+event:0xf counters:0 um:zero minimum:500 name:INSNS_EXECED : Instructions executed
+
+#
+# Events specific to counter 1
+#
+event:0x1 counters:1 um:zero minimum:500 name:INSNS_EXECED : Instructions executed
+event:0x5 counters:1 um:zero minimum:500 name:FP_INSNS_EXECED : Floating-point instructions executed
+event:0x6 counters:1 um:zero minimum:500 name:DCACHE_LINE_EVICTED : Data cache line evicted
+event:0x7 counters:1 um:zero minimum:500 name:TLB_MISS_EXCEPTIONS : TLB miss exceptions
+event:0x8 counters:1 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branch mispredicted
+event:0x9 counters:1 um:zero minimum:500 name:DCACHE_MISS : Data cache miss
+event:0xa counters:1 um:zero minimum:500 name:CONFLICT_STALL_M_STAGE : Instruction stall in M stage due to scheduling conflicts
+event:0xf counters:1 um:zero minimum:500 name:COP2_INSNS_EXECED : COP2 instructions executed
diff --git a/events/mips/5K/unit_masks b/events/mips/5K/unit_masks
new file mode 100644
index 0000000..a3f26e4
--- /dev/null
+++ b/events/mips/5K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 5K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/74K/events b/events/mips/74K/events
new file mode 100644
index 0000000..81700f8
--- /dev/null
+++ b/events/mips/74K/events
@@ -0,0 +1,159 @@
+#
+# MIPS 74K
+#
+
+# The 74K CPUs have four performance counters.
+#
+# Even/odd counters are distinguished by setting bit 10 in the event
+# mask. The kernel masks this bit out before writing the control
+# register.
+
+#
+# Events specific to all counters
+#
+event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
+event:0x1 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions graduated
+
+#
+# Events specific to counters 0 and 2
+#
+event:0x2 counters:0,2 um:zero minimum:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instructions
+event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
+event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
+
+event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
+event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
+event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
+event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer
+
+event:0xb counters:0,2 um:zero minimum:500 name:IFU_IDU_MISS_PRED_UPSTREAM_CYCLES : 11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch
+event:0xc counters:0,2 um:zero minimum:500 name:IFU_IDU_CLOGED_DOWNSTREAM_CYCLES : 12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS
+event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full
+event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full
+event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full
+event:0x10 counters:0,2 um:zero minimum:500 name:ALU_EMPTY_CYCLES : 16-0 DDQ0 (ALU out-of-order dispatch queue) empty cycles
+event:0x11 counters:0,2 um:zero minimum:500 name:ALU_OPERANDS_NOT_READY_CYCLES : 17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready
+event:0x12 counters:0,2 um:zero minimum:500 name:ALU_NO_ISSUES_CYCLES : 18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy
+event:0x13 counters:0,2 um:zero minimum:500 name:ALU_BUBBLE_CYCLES : 19-0 DDQ0 (ALU out-of-order dispatch queue) bubbles due to MFC1 data write
+event:0x14 counters:0,2 um:zero minimum:500 name:SINGLE_ISSUE_CYCLES : 20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles
+event:0x15 counters:0,2 um:zero minimum:500 name:OOO_ALU_ISSUE_CYCLES : 21-0 Out-of-order ALU issue cycles (issued instruction is not the oldest in the pool)
+event:0x16 counters:0,2 um:zero minimum:500 name:JALR_JALR_HB_INSNS : 22-0 Graduated JALR/JALR.HB instructions
+event:0x17 counters:0,2 um:zero minimum:500 name:DCACHE_LOAD_ACCESSES : 23-0 Counts all accesses to the data cache caused by load instructions
+event:0x18 counters:0,2 um:zero minimum:500 name:DCACHE_WRITEBACKS : 24-0 Data cache writebacks
+event:0x19 counters:0,2 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 25-0 Joint TLB data (non-instruction) accesses
+event:0x1a counters:0,2 um:zero minimum:500 name:LOAD_STORE_REPLAYS : 26-0 Load/store generated replays - load/store follows too closely a matching CACHEOP
+event:0x1b counters:0,2 um:zero minimum:500 name:LOAD_STORE_BLOCKED_CYCLES : 27-0 Load/store graduation blocked cycles due to CP1/2 store data not ready, SYNC/SYNCI/SC/CACHEOP at the head, or FSB/LDQ/WBB/ITU FIFO full
+event:0x1c counters:0,2 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 28-0 L2 Cache Writebacks
+event:0x1d counters:0,2 um:zero minimum:500 name:L2_CACHE_MISSES : 29-0 L2 Cache Misses
+event:0x1e counters:0,2 um:zero minimum:500 name:FSB_FULL_STALLS : 30-0 Pipe stall cycles due to FSB full
+event:0x1f counters:0,2 um:zero minimum:500 name:LDQ_FULL_STALLS : 31-0 Pipe stall cycles due to LDQ full
+event:0x20 counters:0,2 um:zero minimum:500 name:WBB_FULL_STALLS : 32-0 Pipe stall cycles due to WBB full
+
+event:0x23 counters:0,2 um:zero minimum:500 name:LOAD_MISS_CONSUMER_REPLAYS : 35-0 Replays following optimistic issue of instruction dependent on load which missed, counted only when the dependent instruction graduates
+event:0x24 counters:0,2 um:zero minimum:500 name:JR_NON_31_INSNS : 36-0 jr $xx (not $31) instructions graduated (at same cost as a mispredict)
+event:0x25 counters:0,2 um:zero minimum:500 name:BRANCH_INSNS : 37-0 Branch instructions graduated, excluding CP1/CP2 conditional branches
+event:0x26 counters:0,2 um:zero minimum:500 name:BRANCH_LIKELY_INSNS : 38-0 Branch likely instructions graduated including CP1 and CP2 branch likely instructions
+event:0x27 counters:0,2 um:zero minimum:500 name:COND_BRANCH_INSNS : 39-0 Conditional branches graduated
+event:0x28 counters:0,2 um:zero minimum:500 name:INTEGER_INSNS : 40-0 Integer instructions graduated including NOP, SSNOP, MOVCI, and EHB
+event:0x29 counters:0,2 um:zero minimum:500 name:LOAD_INSNS : 41-0 Loads graduated including CP1 ans CP2 loads
+event:0x2a counters:0,2 um:zero minimum:500 name:J_JAL_INSNS : 42-0 J/JAL graduated
+event:0x2b counters:0,2 um:zero minimum:500 name:NOP_INSNS : 43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB
+event:0x2c counters:0,2 um:zero minimum:500 name:DSP_INSNS : 44-0 DSP instructions graduated
+event:0x2d counters:0,2 um:zero minimum:500 name:DSP_BRANCH_INSNS : 45-0 DSP branch instructions graduated
+event:0x2e counters:0,2 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 46-0 Uncached loads graduated
+
+event:0x31 counters:0,2 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
+event:0x32 counters:0,2 um:zero minimum:500 name:CP1_BRANCH_MISPREDICTIONS : 50-0 CP1 branches mispredicted
+event:0x33 counters:0,2 um:zero minimum:500 name:SC_INSNS : 51-0 SC instructions graduated
+event:0x34 counters:0,2 um:zero minimum:500 name:PREFETCH_INSNS : 52-0 Prefetch instructions graduated
+event:0x35 counters:0,2 um:zero minimum:500 name:NO_INSN_CYCLES : 53-0 No instructions graduated cycles
+event:0x36 counters:0,2 um:zero minimum:500 name:ONE_INSN_CYCLES : 54-0 One instruction graduated cycles
+event:0x37 counters:0,2 um:zero minimum:500 name:GFIFO_BLOCKED_CYCLES : 55-0 GFIFO blocked cycles
+event:0x38 counters:0,2 um:zero minimum:500 name:MISPREDICTION_STALLS : 56-0 Cycles from the time of a pipe kill due to mispredict until the first new instruction graduates
+event:0x39 counters:0,2 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS_CYCLES : 57-0 Mispredicted branch instruction graduation cycles without the delay slot
+event:0x3a counters:0,2 um:zero minimum:500 name:EXCEPTIONS_TAKEN : 58-0 Exceptions taken
+event:0x3b counters:0,2 um:zero minimum:500 name:COREEXTEND_EVENTS : 59-0 Implementation specific CorExtend events
+
+event:0x3e counters:0,2 um:zero minimum:500 name:ISPRAM_EVENTS : 62-0 Implementation specific ISPRAM events
+event:0x3f counters:0,2 um:zero minimum:500 name:L2_CACHE_SINGLE_BIT_ERRORS : 63-0 Single bit errors corrected in L2
+event:0x40 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_0 : 64-0 Implementation specific system event 0
+event:0x41 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_2 : 65-0 Implementation specific system event 2
+event:0x42 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_4 : 66-0 Implementation specific system event 4
+event:0x43 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_6 : 67-0 Implementation specific system event 6
+event:0x44 counters:0,2 um:zero minimum:500 name:OCP_ALL_REQUESTS : 68-0 All OCP requests accepted
+event:0x45 counters:0,2 um:zero minimum:500 name:OCP_READ_REQUESTS : 69-0 OCP read requests accepted
+event:0x46 counters:0,2 um:zero minimum:500 name:OCP_WRITE_REQUESTS : 70-0 OCP write requests accepted
+
+event:0x4a counters:0,2 um:zero minimum:500 name:FSB_LESS_25_FULL : 74-0 FSB < 25% full
+event:0x4b counters:0,2 um:zero minimum:500 name:LDQ_LESS_25_FULL : 75-0 LDQ < 25% full
+event:0x4c counters:0,2 um:zero minimum:500 name:WBB_LESS_25_FULL : 76-0 WBB < 25% full
+
+
+#
+# Events specific to counters 1 and 3
+#
+
+event:0x402 counters:1,3 um:zero minimum:500 name:JR_31_MISPREDICTIONS : 2-1 JR $31 (return) instructions mispredicted
+event:0x403 counters:1,3 um:zero minimum:500 name:JR_31_NO_PREDICTIONS : 3-1 JR $31 (return) instructions not predicted
+event:0x404 counters:1,3 um:zero minimum:500 name:ITLB_MISSES : 4-1 Instruction micro-TLB misses
+event:0x405 counters:1,3 um:zero minimum:500 name:JTLB_INSN_MISSES : 5-1 Joint TLB instruction misses
+event:0x406 counters:1,3 um:zero minimum:500 name:ICACHE_MISSES : 6-1 Instruction cache misses, includes misses from fetch-ahead and speculation
+
+event:0x408 counters:1,3 um:zero minimum:500 name:PDTRACE_BACK_STALLS : 8-1 PDtrace back stalls
+event:0x409 counters:1,3 um:zero minimum:500 name:KILLED_FETCH_SLOTS : 9-1 Valid fetch slots killed due to taken branches/jumps or stalling instructions
+
+event:0x40b counters:1,3 um:zero minimum:500 name:IFU_IDU_NO_FETCH_CYCLES : 11-1 Cycles IFU-IDU gate open but no instructions fetched by IFU
+
+event:0x40d counters:1,3 um:zero minimum:500 name:DDQ1_FULL_DR_STALLS : 13-1 DR stage stall cycles due to DDQ1 (AGEN out-of-order dispatch queue) full
+event:0x40e counters:1,3 um:zero minimum:500 name:AGCB_FULL_DR_STALLS : 14-1 DR stage stall cycles due to AGCB (AGEN completion buffers) full
+event:0x40f counters:1,3 um:zero minimum:500 name:IODQ_FULL_DR_STALLS : 15-1 DR stage stall cycles due to IODQ (data comming back from IO) full
+event:0x410 counters:1,3 um:zero minimum:500 name:AGEN_EMPTY_CYCLES : 16-1 DDQ1 (AGEN out-of-order dispatch queue) empty cycles
+event:0x411 counters:1,3 um:zero minimum:500 name:AGEN_OPERANDS_NOT_READY_CYCLES : 17-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready
+event:0x412 counters:1,3 um:zero minimum:500 name:AGEN_NO_ISSUES_CYCLES : 18-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, non-issued stores blocking ready to issue loads, or non-issued CACHEOPs blocking ready to issue loads
+event:0x413 counters:1,3 um:zero minimum:500 name:AGEN_BUBBLE_CYCLES : 19-1 DDQ1 (AGEN out-of-order dispatch queue) bubbles due to MFC2 data write or cache access from FSB
+event:0x414 counters:1,3 um:zero minimum:500 name:DUAL_ISSUE_CYCLES : 20-1 Both DDQ0 (ALU out-of-order dispatch queue) and DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles
+event:0x415 counters:1,3 um:zero minimum:500 name:OOO_AGEN_ISSUE_CYCLES : 21-1 Out-of-order AGEN issue cycles (issued instruction is not the oldest in the pool)
+event:0x416 counters:1,3 um:zero minimum:500 name:DCACHE_LINE_REFILL_REQUESTS : 22-1 Data cache line loads (line refill requests)
+event:0x417 counters:1,3 um:zero minimum:500 name:DCACHE_ACCESSES : 23-1 Data cache accesses
+event:0x418 counters:1,3 um:zero minimum:500 name:DCACHE_MISSES : 24-1 Data cache misses
+event:0x419 counters:1,3 um:zero minimum:500 name:JTLB_DATA_MISSES : 25-1 Joint TLB data (non-instruction) misses
+event:0x41a counters:1,3 um:zero minimum:500 name:VA_TRANSALTION_CORNER_CASES : 26-1 Virtual memory address translation synonyms, homonyms, and aliases (loads/stores treated as miss in the cache)
+event:0x41b counters:1,3 um:zero minimum:500 name:LOAD_STORE_NO_FILL_REQUESTS : 27-1 Load/store graduations not resulting in a bus request because misses at integer pipe graduation turn into hit or merge with outstanding fill request
+event:0x41c counters:1,3 um:zero minimum:500 name:L2_CACHE_ACCESSES : 28-1 Accesses to the L2 cache
+event:0x41d counters:1,3 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
+event:0x41e counters:1,3 um:zero minimum:500 name:FSB_OVER_50_FULL : 30-1 FSB > 50% full
+event:0x41f counters:1,3 um:zero minimum:500 name:LDQ_OVER_50_FULL : 31-1 LDQ > 50% full
+event:0x420 counters:1,3 um:zero minimum:500 name:WBB_OVER_50_FULL : 32-1 WBB > 50% full
+
+event:0x423 counters:1,3 um:zero minimum:500 name:CP1_CP2_LOAD_INSNS : 35-1 CP1/CP2 load instructions graduated
+event:0x424 counters:1,3 um:zero minimum:500 name:MISPREDICTED_JR_31_INSNS : 36-1 jr $31 instructions graduated after mispredict
+event:0x425 counters:1,3 um:zero minimum:500 name:CP1_CP2_COND_BRANCH_INSNS : 37-1 CP1/CP2 conditional branch instructions graduated
+event:0x426 counters:1,3 um:zero minimum:500 name:MISPREDICTED_BRANCH_LIKELY_INSNS : 38-1 Mispredicted branch likely instructions graduated
+event:0x427 counters:1,3 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 39-1 Mispredicted branches graduated
+event:0x428 counters:1,3 um:zero minimum:500 name:FPU_INSNS : 40-1 FPU instructions graduated
+event:0x429 counters:1,3 um:zero minimum:500 name:STORE_INSNS : 41-1 Store instructions graduated including CP1 ans CP2 stores
+event:0x42a counters:1,3 um:zero minimum:500 name:MIPS16_INSNS : 42-1 MIPS16 instructions graduated
+event:0x42b counters:1,3 um:zero minimum:500 name:NT_MUL_DIV_INSNS : 43-1 Integer multiply/divide instructions graduated
+event:0x42c counters:1,3 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 44-1 ALU-DSP graduated, result was saturated
+event:0x42d counters:1,3 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 45-1 MDU-DSP graduated, result was saturated
+event:0x42e counters:1,3 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 46-1 Uncached stores graduated
+
+event:0x433 counters:1,3 um:zero minimum:500 name:FAILED_SC_INSNS : 51-1 SC instructions failed
+event:0x434 counters:1,3 um:zero minimum:500 name:CACHE_HIT_PREFETCH_INSNS : 52-1 PREFETCH instructions which did nothing, because they hit in the cache
+event:0x435 counters:1,3 um:zero minimum:500 name:LOAD_MISS_INSNS : 53-1 Cacheable load instructions that miss in the cache graduated
+event:0x436 counters:1,3 um:zero minimum:500 name:TWO_INSNS_CYCLES : 54-1 Two instructions graduated cycles
+event:0x437 counters:1,3 um:zero minimum:500 name:CP1_CP2_STORE_INSNS : 55-1 CP1/CP2 Store graduated
+event:0x43a counters:1,3 um:zero minimum:500 name:GRADUATION_REPLAYS : 58-1 Replays initiated from graduation
+event:0x43e counters:1,3 um:zero minimum:500 name:DSPRAM_EVENTS : 62-1 Implementation specific events from the DSPRAM block
+
+event:0x440 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_1 : 64-1 Implementation specific system event 1
+event:0x441 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_3 : 65-1 Implementation specific system event 3
+event:0x442 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_5 : 66-1 Implementation specific system event 5
+event:0x443 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_7 : 67-1 Implementation specific system event 7
+event:0x444 counters:0,2 um:zero minimum:500 name:OCP_ALL_CACHEABLE_REQUESTS : 68-1 All OCP cacheable requests accepted
+event:0x445 counters:0,2 um:zero minimum:500 name:OCP_READ_CACHEABLE_REQUESTS : 69-1 OCP cacheable read request accepted
+event:0x446 counters:0,2 um:zero minimum:500 name:OCP_WRITE_CACHEABLE_REQUESTS : 70-1 OCP cacheable write request accepted
+
+event:0x44a counters:0,2 um:zero minimum:500 name:FSB_25_50_FULL : 74-1 FSB 25-50% full
+event:0x44b counters:0,2 um:zero minimum:500 name:LDQ_25_50_FULL : 75-1 LDQ 25-50% full
+event:0x44c counters:0,2 um:zero minimum:500 name:WBB_25_50_FULL : 76-1 WBB 25-50% full
diff --git a/events/mips/74K/unit_masks b/events/mips/74K/unit_masks
new file mode 100644
index 0000000..d379dcf
--- /dev/null
+++ b/events/mips/74K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 74K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/loongson2/events b/events/mips/loongson2/events
new file mode 100644
index 0000000..68a472b
--- /dev/null
+++ b/events/mips/loongson2/events
@@ -0,0 +1,34 @@
+# loongson2 Events
+#
+event:0x00 counters:0 um:zero minimum:10000 name:CPU_CLK_UNHALTED : Cycles outside of haltstate
+event:0x01 counters:0 um:zero minimum:5000 name:BRANCH_INSTRUCTIONS : Branch instructions
+event:0x02 counters:0 um:zero minimum:400 name:JUMP_INSTRUCTIONS : JR instructions
+event:0x03 counters:0 um:zero minimum:500 name:JR31_INSTRUCTIONS : JR(rs=31) instructions
+event:0x04 counters:0 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:0x05 counters:0 um:zero minimum:500 name:ALU1_ISSUED : ALU1 operation issued
+event:0x06 counters:0 um:zero minimum:8000 name:MEM_ISSUED : Memory read/write issued
+event:0x07 counters:0 um:zero minimum:300 name:FALU1_ISSUED : Float ALU1 operation issued
+event:0x08 counters:0 um:zero minimum:200 name:BHT_BRANCH_INSTRUCTIONS : BHT prediction instructions
+event:0x09 counters:0 um:zero minimum:200 name:MEM_READ : Read from primary memory
+event:0x0a counters:0 um:zero minimum:300 name:FQUEUE_FULL : Fix queue full
+event:0x0b counters:0 um:zero minimum:300 name:ROQ_FULL : Reorder queue full
+event:0x0c counters:0 um:zero minimum:300 name:CP0_QUEUE_FULL : CP0 queue full
+event:0x0d counters:0 um:zero minimum:300 name:TLB_REFILL : TLB refill exception
+event:0x0e counters:0 um:zero minimum:5 name:EXCEPTION : Exceptions
+event:0x0f counters:0 um:zero minimum:300 name:INTERNAL_EXCEPTION : Internal exceptions
+event:0x10 counters:1 um:zero minimum:5000 name:INSTRUCTION_COMMITTED : Instruction committed
+event:0x11 counters:1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch mispredicted
+event:0x12 counters:1 um:zero minimum:200 name:JR_MISPREDICTED : JR mispredicted
+event:0x13 counters:1 um:zero minimum:200 name:JR31_MISPREDICTED : JR31 mispredicted
+event:0x14 counters:1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
+event:0x15 counters:1 um:zero minimum:500 name:ALU2_ISSUED : ALU2 operation issued
+event:0x16 counters:1 um:zero minimum:500 name:FALU2_ISSUED : FALU2 operation issued
+event:0x17 counters:1 um:zero minimum:500 name:UNCACHED_ACCESS : Uncached accesses
+event:0x18 counters:1 um:zero minimum:500 name:BHT_MISPREDICTED : Branch history table mispredicted
+event:0x19 counters:1 um:zero minimum:5000 name:MEM_WRITE : Write to memory
+event:0x1a counters:1 um:zero minimum:500 name:FTQ_FULL : Float queue full
+event:0x1b counters:1 um:zero minimum:500 name:BRANCH_QUEUE_FULL : Branch queue full
+event:0x1c counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
+event:0x1d counters:1 um:zero minimum:500 name:TOTAL_EXCEPTIONS : Total exceptions
+event:0x1e counters:1 um:zero minimum:500 name:LOAD_SPECULATION_MISSES : Load speculation misses
+event:0x1f counters:1 um:zero minimum:500 name:CP0Q_FORWARD_VALID : CP0 queue forward valid
diff --git a/events/mips/loongson2/unit_masks b/events/mips/loongson2/unit_masks
new file mode 100644
index 0000000..0d4ce5b
--- /dev/null
+++ b/events/mips/loongson2/unit_masks
@@ -0,0 +1,4 @@
+# loongson2 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/r10000/events b/events/mips/r10000/events
new file mode 100644
index 0000000..237cc06
--- /dev/null
+++ b/events/mips/r10000/events
@@ -0,0 +1,36 @@
+#
+# R10000 events
+#
+# The same event numbers mean different things on the two counters
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
+event:0x01 counters:0 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
+event:0x01 counters:1 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
+event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued
+event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated
+event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued
+event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated
+event:0x04 counters:0 um:zero minimum:500 name:STORE_COND_ISSUED : Store conditional issued
+event:0x04 counters:1 um:zero minimum:500 name:STORE_COND_GRADUATED : Store conditional graduated
+event:0x05 counters:0 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
+event:0x05 counters:1 um:zero minimum:500 name:FP_INSTRUCTON_GRADUATED : Floating-point instructions graduated
+event:0x06 counters:0 um:zero minimum:500 name:BRANCHES_RESOLVED : Branches resolved
+event:0x06 counters:1 um:zero minimum:500 name:QUADWORDS_WB_FROM_PRIMARY_DCACHE : Quadwords written back from primary data cache
+event:0x07 counters:0 um:zero minimum:500 name:QUADWORDS_WB_FROM_SCACHE : Quadwords written back from secondary cache
+event:0x07 counters:1 um:zero minimum:500 name:TLB_REFILL_EXCEPTIONS : TLB refill exceptions
+event:0x08 counters:0 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS_SCACHE : Correctable ECC errors on secondary cache data
+event:0x08 counters:1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted
+event:0x09 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
+event:0x09 counters:1 um:zero minimum:500 name:SCACHE_LOAD_STORE_CACHEOP_OPERATIONS : Secondary cache load / store and cache-ops operations
+event:0x0a counters:0 um:zero minimum:500 name:SCACHE_MISSES_INSTRUCTION : Secondary cache misses (instruction)
+event:0x0a counters:1 um:zero minimum:500 name:SCACHE_MISSES_DATA : Secondary cache misses (data)
+event:0x0b counters:0 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTED_INSN : Secondary cache way mispredicted (instruction)
+event:0x0b counters:1 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTED_DATA : Secondary cache way mispredicted (data)
+event:0x0c counters:0 um:zero minimum:500 name:EXTERNAL_INTERVENTION_RQ : External intervention requests
+event:0x0c counters:1 um:zero minimum:500 name:EXTERNAL_INTERVENTION_RQ_HITS_SCACHE : External intervention request is determined to have hit in secondary cache
+event:0x0d counters:0 um:zero minimum:500 name:EXTERNAL_INVALIDATE_RQ : External invalidate requests
+event:0x0d counters:1 um:zero minimum:500 name:EXTERNAL_INVALIDATE_RQ_HITS_SCACHE : External invalidate request is determined to have hit in secondary cache
+event:0x0e counters:0 um:zero minimum:500 name:FUNCTIONAL_UNIT_COMPLETION_CYCLES : Functional unit completion cycles
+event:0x0e counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_CLEANEXCLUSIVE_SCACHE_BLOCKS : Stores or prefetches with store hint to CleanExclusive secondary cache blocks
+event:0x0f counters:0 um:zero minimum:500 name:INSTRUCTION_GRADUATED : Instructions graduated
+event:0x0f counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_SHD_SCACHE_BLOCKS : Stores or prefetches with store hint to Shared secondary cache blocks
diff --git a/events/mips/r10000/unit_masks b/events/mips/r10000/unit_masks
new file mode 100644
index 0000000..fab7d83
--- /dev/null
+++ b/events/mips/r10000/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS R10000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/r12000/events b/events/mips/r12000/events
new file mode 100644
index 0000000..1fa6779
--- /dev/null
+++ b/events/mips/r12000/events
@@ -0,0 +1,35 @@
+#
+# R12000 events
+#
+event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
+event:0x1 counters:0,1,2,3 um:zero minimum:500 name:DECODED_INSTRUCTIONS : Decoded instructions
+event:0x2 counters:0,1,2,3 um:zero minimum:500 name:DECODED_LOADS : Decoded loads
+event:0x3 counters:0,1,2,3 um:zero minimum:500 name:DECODED_STORES : Decoded stores
+event:0x4 counters:0,1,2,3 um:zero minimum:500 name:MISS_TABLE_OCCUPANCY : Miss Handling Table Occupancy
+event:0x5 counters:0,1,2,3 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
+event:0x6 counters:0,1,2,3 um:zero minimum:500 name:RESOLVED_BRANCH_CONDITIONAL : Resolved conditional branches
+event:0x7 counters:0,1,2,3 um:zero minimum:500 name:QUADWORRDS_WRITEBACK_FROM_SC : Quadwords written back from secondary cache
+event:0x8 counters:0,1,2,3 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS : Correctable ECC errors on secondary cache data
+event:0x9 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:0xa counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_SECONDARY_CACHE_MISSES : Secondary cache misses (instruction)
+event:0xb counters:0,1,2,3 um:zero minimum:500 name:SECONDARY_CACHE_WAY_MISSPREDICTED : Secondary cache way mispredicted (instruction)
+event:0xc counters:0,1,2,3 um:zero minimum:500 name:INTERVENTION_REQUESTS : External intervention requests
+event:0xd counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_REQUESTS : External invalidate requests
+
+event:0xf counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
+event:0x10 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_INSTRUCTIONS_EXECUTED : Executed prefetch instructions
+event:0x11 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_MISSES_IN_DCACHE : Primary data cache misses by prefetch instructions
+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_LOADS : Graduated loads
+event:0x13 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_STORES : Graduated stores
+event:0x14 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_STORE_CONDITIONALS : Graduated store conditionals
+event:0x15 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_FP_INSTRUCTIONS : Graduated floating point instructions
+event:0x16 counters:0,1,2,3 um:zero minimum:500 name:QUADWORDS : Quadwords written back from primary data cache
+event:0x17 counters:0,1,2,3 um:zero minimum:500 name:TLB_MISSES : TLB misses
+event:0x18 counters:0,1,2,3 um:zero minimum:500 name:MISPREDICTED_BRANCHES : Mispredicted branches
+event:0x19 counters:0,1,2,3 um:zero minimum:500 name:DCACHE_MISSES : Primary data cache misses
+event:0x1a counters:0,1,2,3 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses (data)
+event:0x1b counters:0,1,2,3 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTION : Misprediction from scache way prediction table (data)
+event:0x1c counters:0,1,2,3 um:zero minimum:500 name:STATE_OF_SCACHE_INTERVENTION_HIT : State of external intervention hit in secondary cache
+event:0x1d counters:0,1,2,3 um:zero minimum:500 name:STATE_OF_EXTERNAL_INVALIDATION_HIT : State of external invalidation hits in secondary cache
+event:0x1e counters:0,1,2,3 um:zero minimum:500 name:STORE_PREFETCH_EXCLUSIVE_TO_CLEAN_SC_BLOCK : Store/prefetch exclusive to clean block in secondary cache
+event:0x1f counters:0,1,2,3 um:zero minimum:500 name:STORE_PREFETCH_EXCLUSIVE_SHARED_SC_BLOCK : Store/prefetch exclusive to shared block in secondary
diff --git a/events/mips/r12000/unit_masks b/events/mips/r12000/unit_masks
new file mode 100644
index 0000000..20c8250
--- /dev/null
+++ b/events/mips/r12000/unit_masks
@@ -0,0 +1,7 @@
+#
+# MIPS R12000 possible unit masks
+#
+# We don't support the R12000 conditional count feature yet.
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/rm7000/events b/events/mips/rm7000/events
new file mode 100644
index 0000000..bfcde7a
--- /dev/null
+++ b/events/mips/rm7000/events
@@ -0,0 +1,34 @@
+#
+# RM7000 events
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
+event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Total instructions issued
+event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
+event:0x03 counters:0,1 um:zero minimum:500 name:INTEGER_INSTRUCTIONS_ISSUED : Integer instructions issued
+event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
+event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
+event:0x06 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual issued pairs
+event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_PREFETCHES : Branch prefetches
+event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses
+event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
+event:0x0a counters:0,1 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses
+event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
+event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
+event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
+event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
+event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
+event:0x11 counters:0,1 um:zero minimum:500 name:BRANCHES_TAKEN : Branches taken
+event:0x12 counters:0,1 um:zero minimum:500 name:BRANCHES_ISSUED : Branches issued
+event:0x13 counters:0,1 um:zero minimum:500 name:SCACHE_WRITEBACKS : Secondary cache writebacks
+event:0x14 counters:0,1 um:zero minimum:500 name:PCACHE_WRITEBACKS : Primary cache writebacks
+event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
+event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_MISSES : Cache misses
+event:0x17 counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_STALL_CYCLES : FP possible exception cycles
+event:0x18 counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_DUE_MULTIPLIER_BUSY : Slip Cycles due to multiplier busy
+event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Coprocessor 0 slip cycles
+event:0x1a counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_PENDING_NON_BLKING_LOAD : Slip cycles due to pending non-blocking loads
+event:0x1c counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full stall cycles
+event:0x1d counters:0,1 um:zero minimum:500 name:CACHE_INSTRUCTION_STALL_CYCLES : Cache instruction stall cycles
+event:0x1e counters:0,1 um:zero minimum:500 name:MULTIPLIER_STALL_CYCLES : Multiplier stall cycles
+event:0x1f counters:0,1 um:zero minimum:500 name:STALL_CYCLES_PENDING_NON_BLKING_LOAD : Stall cycles due to pending non-blocking loads - stall start of exception
diff --git a/events/mips/rm7000/unit_masks b/events/mips/rm7000/unit_masks
new file mode 100644
index 0000000..cb11b7c
--- /dev/null
+++ b/events/mips/rm7000/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS RM7000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/rm9000/events b/events/mips/rm9000/events
new file mode 100644
index 0000000..71d8491
--- /dev/null
+++ b/events/mips/rm9000/events
@@ -0,0 +1,32 @@
+#
+# RM9000 events
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
+event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
+event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
+event:0x03 counters:0,1 um:zero minimum:500 name:INT_INSTRUCTIONS_ISSUED : Integer instructions issued
+event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
+event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
+event:0x06 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_DUAL_ISSUED : Dual-issued instruction pairs
+event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions
+event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
+event:0x0a counters:0,1 um:zero minimum:500 name:L2_CACHE_MISSES : L2 cache misses
+event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Icache misses
+event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Dcache misses
+event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
+event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
+event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
+event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
+event:0x11 counters:0,1 um:zero minimum:500 name:BRANCHES_TAKEN : Branches taken
+event:0x12 counters:0,1 um:zero minimum:500 name:BRANCHES_ISSUED : Branch instructions issued
+event:0x13 counters:0,1 um:zero minimum:500 name:L2_WRITEBACKS : L2 cache writebacks
+event:0x14 counters:0,1 um:zero minimum:500 name:DCACHE_WRITEBACKS : Dcache writebacks
+event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles
+event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_REMISSES : Cache remisses
+event:0x17 counters:0,1 um:zero minimum:500 name:FP_POSSIBLE_EXCEPTION_CYCLES : Floating-point possible exception cycles
+event:0x18 counters:0,1 um:zero minimum:500 name:MULTIPLIER_BUSY_SLIP_CYCLES : Slip cycles due to busy multiplier
+event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Co-processor 0 slip cycles
+event:0x1a counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_SLIP_CYCLES : Slip cycles due to pending non-blocking loads
+event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Stall cycles due to a full write buffer
+event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
+event:0x1e counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES : Stall cycles due to pending non-blocking loads - stall start of exception
diff --git a/events/mips/rm9000/unit_masks b/events/mips/rm9000/unit_masks
new file mode 100644
index 0000000..63ba9da
--- /dev/null
+++ b/events/mips/rm9000/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS RM9000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/sb1/events b/events/mips/sb1/events
new file mode 100644
index 0000000..efc28ce
--- /dev/null
+++ b/events/mips/sb1/events
@@ -0,0 +1,73 @@
+#
+# Sibyte SB1 events
+#
+
+event:0x10 counters:0,1,2,3 um:zero minimum:500 name:CYCLES :Elapsed cycles
+
+# Execution Counts and Instruction Slotting
+event:0x28 counters:1,2,3 um:zero minimum:500 name:ISSUE_L0 :Issue to L0
+event:0x29 counters:1,2,3 um:zero minimum:500 name:ISSUE_L1 :Issue to L0
+event:0x2a counters:1,2,3 um:zero minimum:500 name:ISSUE_E0 :Issue to E0
+event:0x2b counters:1,2,3 um:zero minimum:500 name:ISSUE_E1 :Issue to E1
+
+# Explaining Sub-Peak Performance: Pipeline Traps
+event:0x2f counters:1,2,3 um:zero minimum:500 name:BRANCH_MISSPREDICTS :Branch mispredicts
+event:0x1d counters:1,2,3 um:zero minimum:500 name:MBOX_REPLAY :MBOX replay
+event:0x1c counters:1,2,3 um:zero minimum:500 name:DCFIFO :DCFIFO
+event:0x1e counters:1,2,3 um:zero minimum:500 name:DATA_DEPENDENCY_REPLAY :Data dependency replay
+event:0x1b counters:1,2,3 um:zero minimum:500 name:DCACHE_FILL_REPLAY :Dcache fill replay
+event:0x1f counters:1,2,3 um:zero minimum:500 name:ANY_REPLAY :Any replay except mispredict
+
+
+# Explaining Sub-Peak Performance: static and dynamic stalls
+event:0x20 counters:1,2,3 um:zero minimum:500 name:MAX_ISSUE :Max issue
+event:0x21 counters:1,2,3 um:zero minimum:500 name:NO_VALID_INSN :No valid instr to issue
+event:0x22 counters:1,2,3 um:zero minimum:500 name:CONSUMER_WAITING_FOR_LOAD :load consumer waiting for dfill
+event:0x23 counters:1,2,3 um:zero minimum:500 name:NOT_DATA_READY :Not data ready
+event:0x24 counters:1,2,3 um:zero minimum:500 name:RESOURCE_CONSTRAINT :Resource (L0/1 E0/1) constraint
+event:0x25 counters:1,2,3 um:zero minimum:500 name:ISSUE_CONFLICT_DUE_IMISS :issue conflict due to imiss using LS0
+event:0x26 counters:1,2,3 um:zero minimum:500 name:ISSUE_CONFLICT_DUE_DFILL :issue conflict due to dfill using LS0/1
+
+# Grouping Co-issued Instructions
+event:0x27 counters:1,2,3 um:zero minimum:500 name:INSN_STAGE4 :One or more instructions survives stage 4
+
+# Branch information
+event:0x2c counters:1,2,3 um:zero minimum:500 name:BRANCH_STAGE4 :Branch survived stage 4
+event:0x2d counters:1,2,3 um:zero minimum:500 name:BRANCH_REALLY_TAKEN :Conditional branch was really taken
+event:0x2e counters:1,2,3 um:zero minimum:500 name:BRANCH_PREDICTED_TAKEN :Predicted taken conditional branch
+
+# Cache access
+event:0x1 counters:1,2,3 um:zero minimum:500 name:RQ_LENGTH :Read queue length
+event:0x2 counters:1,2,3 um:zero minimum:500 name:UNCACHED_RQ_LENGTH :Number of valid uncached entries in read queue
+event:0x3 counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
+
+event:0xa counters:1,2,3 um:zero minimum:500 name:DCACHE_FILLED_SHD_NONC_EXC :Dcache is filled (shared, nonc, exclusive)
+event:0xb counters:1,2,3 um:zero minimum:500 name:DCACHE_FILL_SHARED_LINE :Dcache is filled with shared line
+event:0xc counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
+event:0xf counters:1,2,3 um:zero minimum:500 name:WRITEBACK_RETURNS :Number of instruction returns
+event:0xd counters:1,2,3 um:zero minimum:500 name:VICTIM_WRITEBACK :A writeback occurs due to replacement
+event:0x7 counters:1,2,3 um:zero minimum:500 name:UPGRADE_SHARED_TO_EXCLUSIVE :A line is upgraded from shared to exclusive
+event:0x6 counters:1,2,3 um:zero minimum:500 name:LD_ST_HITS_PREFETCH_IN_QUEUE :Load/store hits prefetch in read queue
+event:0x5 counters:1,2,3 um:zero minimum:500 name:PREFETCH_HITS_CACHE_OR_READ_Q :Prefetch hits in cache or read queue
+event:0x4 counters:1,2,3 um:zero minimum:500 name:READ_HITS_READ_Q :Read hits in read queue
+
+# BIU
+
+event:0x11 counters:1,2,3 um:zero minimum:500 name:BIU_STALLS_ON_ZB_ADDR_BUS :BIU stalls on ZB addr bus
+event:0x12 counters:1,2,3 um:zero minimum:500 name:BIU_STALLS_ON_ZB_DATA_BUS :BIU stalls on ZB data bus
+event:0x13 counters:1,2,3 um:zero minimum:500 name:READ_RQ_SENT_TO_ABUS :Requests sent to ZB Abus
+event:0x14 counters:1,2,3 um:zero minimum:500 name:READ_RQ_NOPS_SENT_TO_ABUS :Read requests and NOPs sent to ZB Abus
+event:0x15 counters:1,2,3 um:zero minimum:500 name:READ_RQ_SENT_TO_ABUS :Read requests sent to ZB Abus
+event:0x16 counters:1,2,3 um:zero minimum:500 name:MBOX_RQ_WHEN_BIU_BUSY :MBOX requests to BIU when BIU busy
+
+# Multiprocessor
+event:0x1a counters:1,2,3 um:zero minimum:500 name:STORE_COND_FAILED :Failed store conditional
+event:0x16 counters:1,2,3 um:zero minimum:500 name:SNOOP_RQ_HITS :Snoop request hits anywhere
+event:0x17 counters:1,2,3 um:zero minimum:500 name:SNOOP_ADDR_Q_FULL :Snoop address queue is full
+event:0x18 counters:1,2,3 um:zero minimum:500 name:R_RESP_OTHER_CORE :Read response comes from the other core
+event:0x19 counters:1,2,3 um:zero minimum:500 name:R_RESP_OTHER_CORE_D_MOD :Read response comes from the other core with D_MOD set
+
+# Instruction Counts
+event:0x8 counters:1,2,3 um:zero minimum:500 name:LOAD_SURVIVED_STAGE4 :Load survived stage 4
+event:0x9 counters:1,2,3 um:zero minimum:500 name:STORE_SURVIVED_STAGE4 :Store survived stage 4
+event:0x0 counters:1,2,3 um:zero minimum:500 name:INSN_SURVIVED_STAGE7 :Instruction survived stage 7
diff --git a/events/mips/sb1/unit_masks b/events/mips/sb1/unit_masks
new file mode 100644
index 0000000..7fd41fb
--- /dev/null
+++ b/events/mips/sb1/unit_masks
@@ -0,0 +1,5 @@
+#
+# Sibyte SB1 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/vr5432/events b/events/mips/vr5432/events
new file mode 100644
index 0000000..31bd827
--- /dev/null
+++ b/events/mips/vr5432/events
@@ -0,0 +1,14 @@
+#
+# VR5432 events
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
+event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
+event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
+event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
+event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
+event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
+event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
+event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
+event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
+event:0xa counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted
diff --git a/events/mips/vr5432/unit_masks b/events/mips/vr5432/unit_masks
new file mode 100644
index 0000000..2239d12
--- /dev/null
+++ b/events/mips/vr5432/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS VR5432 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/vr5500/events b/events/mips/vr5500/events
new file mode 100644
index 0000000..c540176
--- /dev/null
+++ b/events/mips/vr5500/events
@@ -0,0 +1,16 @@
+#
+# VR5500, VR5532 and VR7701 events
+#
+# Very similar to what the VR5432 provides.
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed
+event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction
+event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction
+event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction
+event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction
+event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory
+event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill
+event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss
+event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache miss
+event:0xa counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch prediction miss
diff --git a/events/mips/vr5500/unit_masks b/events/mips/vr5500/unit_masks
new file mode 100644
index 0000000..ef69a7a
--- /dev/null
+++ b/events/mips/vr5500/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS VR5500 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc/7450/events b/events/ppc/7450/events
new file mode 100644
index 0000000..d27046f
--- /dev/null
+++ b/events/ppc/7450/events
@@ -0,0 +1,39 @@
+# 745x Events
+#
+event:0x1 counters:0,1,2,3 um:zero minimum:3000 name:CYCLES : Processor cycles
+event:0x2 counters:0,1,2,3 um:zero minimum:3000 name:COMPLETED_INSNS : Completed Instructions
+event:0x3 counters:0,1,2,3 um:zero minimum:3000 name:TBL_BIT_TRANSTNS : TBL Bit Transitions
+event:0x4 counters:0,1,2,3 um:zero minimum:3000 name:DISPATCHED_INSNS : Dispatched Instructions
+event:0x5 counters:0,1,2,3 um:zero minimum:3000 name:PROC_PERFMON_EXC : Process Performance Monitor Exception
+event:0x8 counters:0,1,3 um:zero minimum:3000 name:VPU_INSNS : VPU Instructions Completed
+event:0x9 counters:0,1,3 um:zero minimum:3000 name:VFPU_INSNS : VFPU Instructions Completed
+event:0xa counters:0,1,3 um:zero minimum:3000 name:VIU1_INSNS : VIU1 Instructions Completed
+event:0xb counters:0,1,3 um:zero minimum:3000 name:VIU2_INSNS : VIU2 Instructions Completed
+event:0xe counters:0,1 um:zero minimum:3000 name:VPU_CYCLES : Cycles a VPU Instruction
+event:0xf counters:0,1 um:zero minimum:3000 name:VFPU_CYCLES : Cycles a VFPU Instruction
+event:0x10 counters:0,1 um:zero minimum:3000 name:VIU1_CYCLES : Cycles a VIU1 Instruction
+event:0x11 counters:0,1 um:zero minimum:3000 name:VIU2_CYCLES : Cycles a VIU2 Instruction
+event:0x12 counters:2 um:zero minimum:3000 name:DTLB_MISSES : DTLB misses
+event:0x14 counters:0,1 um:zero minimum:3000 name:STORE_INSNS : Store Instructions
+event:0x15 counters:0,1 um:zero minimum:3000 name:L1_ICACHE_MISSES : L1 Instruction Cache Misses
+event:0x16 counters:0,1 um:zero minimum:3000 name:L1_DATA_SNOOPS : L1 Data Snoops
+event:0x17 counters:0,1 um:zero minimum:3000 name:UNRESOLVED_BRANCHES : Unresolved Branches
+event:0x1c counters:3 um:zero minimum:3000 name:MISPREDICTED_BRANCHES : Mispredicted branches
+event:0x1d counters:3 um:zero minimum:3000 name:FOLDED_BRANCHES : Folded branches
+event:0x1f counters:2 um:zero minimum:3000 name:BR_LN_STACK_MIS : Branch Link Stack Mispredicted
+event:0x27 counters:0 um:zero minimum:3000 name:ITLB_TABLE_CYCLES : ITLM Hardware Table Search Cycles
+event:0x29 counters:0 um:zero minimum:3000 name:L1_ICACHE_ACCESSES : L1 Instruction Cache Accesses
+event:0x2a counters:0 um:zero minimum:3000 name:INSN_BP_MATCHES : Instruction Breakpoint Matches
+event:0x32 counters:0 um:zero minimum:3000 name:L1_DSNOOP_HITS : L1 data snoop hits
+event:0x33 counters:0 um:zero minimum:3000 name:WRITETHRU_STORES : Write-through stores
+event:0x34 counters:0 um:zero minimum:3000 name:CACHEINH_STORES : Cache-inhibited stores
+event:0x35 counters:0 um:zero minimum:3000 name:L1_DLOAD_HIT : L1 data load hit
+event:0x36 counters:0 um:zero minimum:3000 name:L1_DTOUCH_HIT : L1 data touch hit
+event:0x37 counters:0 um:zero minimum:3000 name:L1_DSTORE_HIT : L1 data store hit
+event:0x38 counters:0 um:zero minimum:3000 name:L1_DATA_HITS : L1 data total hits
+event:0x40 counters:0 um:zero minimum:3000 name:ALTIVEC_LD_INSNS_COMPLETED : Altivec load instructions completed
+event:0x41 counters:0 um:zero minimum:3000 name:FP_STORE_INSNS_COMPLETED_LSU : Floating point store instructions completed in LSU
+event:0x4f counters:0 um:zero minimum:3000 name:FP_LOAD_INSNS_COMPLETED_LSU : Floating point load instructions completed in LSU
+event:0x50 counters:0 um:zero minimum:3000 name:FP_LDSINGLE_INSNS_COMPLETED_LSU : Floating point load single instructions completed in LSU
+event:0x5e counters:0 um:zero minimum:3000 name:FP_DENORMALIZED_RESULT : Floating point denormalized result
+
diff --git a/events/ppc/7450/unit_masks b/events/ppc/7450/unit_masks
new file mode 100644
index 0000000..33c15c2
--- /dev/null
+++ b/events/ppc/7450/unit_masks
@@ -0,0 +1,4 @@
+# 745x possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc/e300/events b/events/ppc/e300/events
new file mode 100644
index 0000000..c76923c
--- /dev/null
+++ b/events/ppc/e300/events
@@ -0,0 +1,40 @@
+# e300 Events
+#
+event:0x1 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK : Cycles
+event:0x2 counters:0,1,2,3 um:zero minimum:3000 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
+event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
+event:0x6 counters:0,1,2,3 um:zero minimum:500 name:PM_EVENT_TRANS : 0 to 1 translations on the pm_event input
+event:0x7 counters:0,1,2,3 um:zero minimum:500 name:PM_EVENT_CYCLES : processor bus cycle
+event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
+event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
+event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
+event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished
+event:0xd counters:0,1,2,3 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finished
+event:0xf counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch instructions mispredicted due to direction, target, or IAB prediction
+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
+event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued
+event:0x1f counters:0,1,2,3 um:zero minimum:500 name:CACHEINHIBITED_ACCESSES_TRANSLATED : Number of cache inhibited accesses translated
+event:0x3d counters:0,1,2,3 um:zero minimum:500 name:FETCHES : Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)
+event:0x3e counters:0,1,2,3 um:zero minimum:500 name:MMU_MISSES : Counts instruction TLB miss exceptions
+event:0x43 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_REQUESTS : Number of master transactions. (Number of master TSs.)
+event:0x44 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_I_REQUESTS : Number of master I-Side transactions. (Number of master I-Side TSs.)
+event:0x45 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_REQUESTS : Number of master D-Side transactions. (Number of master D-Side TSs.)
+event:0x47 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_RETRIES : Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.)
+event:0x4a counters:0,1,2,3 um:zero minimum:500 name:SNOOP_PUSHES : Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.)
+event:0x52 counters:0,1,2,3 um:zero minimum:500 name:PMC0_OVERFLOW : Counts the number of times PMC0[32] transitioned from 1 to 0.
+event:0x53 counters:0,1,2,3 um:zero minimum:500 name:PMC1_OVERFLOW : Counts the number of times PMC1[32] transitioned from 1 to 0.
+event:0x54 counters:0,1,2,3 um:zero minimum:500 name:PMC2_OVERFLOW : Counts the number of times PMC2[32] transitioned from 1 to 0.
+event:0x55 counters:0,1,2,3 um:zero minimum:500 name:PMC3_OVERFLOW : Counts the number of times PMC3[32] transitioned from 1 to 0.
+event:0x56 counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS : Number of interrupts taken
+event:0x57 counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_INTERRUPTS : Number of external input interrupts taken
+event:0x58 counters:0,1,2,3 um:zero minimum:500 name:CRITICAL_INTERRUPTS : Number of critical input interrupts taken
+event:0x59 counters:0,1,2,3 um:zero minimum:500 name:SC_TRAP_INTERRUPTS : Number of system call and trap interrupts
+event:0x5a counters:0,1,2,3 um:zero minimum:500 name:TRANS_TBL : Counts transitions of the TBL bit selected by PMGC0[TBSEL]
+event:0x60 counters:0,1,2,3 um:zero minimum:500 name:I_CACHE_HIT : Number if fetches that hit in i-cache
+event:0x61 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS_FOLDED : Number of instructions folded
+event:0x64 counters:0,1,2,3 um:zero minimum:500 name:STALLS_COM_BUFFER : Cycles issue stalled due to full completion buffer
+event:0x68 counters:0,1,2,3 um:zero minimum:500 name:STALLED_COMPLETION : Cycles that completion is stalled
+event:0x69 counters:0,1,2,3 um:zero minimum:500 name:STALLED_LOAD : Cycles that completion is stalled due to load
+event:0x6a counters:0,1,2,3 um:zero minimum:500 name:STALLED_FLOAT : Cycles that completion is stalled due to fp instruction
+event:0x6c counters:0,1,2,3 um:zero minimum:500 name:L_S_SPACE : Number of loads and stores to cacheable space in D cache
+event:0x6d counters:0,1,2,3 um:zero minimum:500 name:L_S_HIT : Number of loads and stores that hit in the D cache
diff --git a/events/ppc/e300/unit_masks b/events/ppc/e300/unit_masks
new file mode 100644
index 0000000..5e6a866
--- /dev/null
+++ b/events/ppc/e300/unit_masks
@@ -0,0 +1,4 @@
+# e300 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc/e500/events b/events/ppc/e500/events
new file mode 100644
index 0000000..e81f8b5
--- /dev/null
+++ b/events/ppc/e500/events
@@ -0,0 +1,83 @@
+# e500 Events
+#
+event:0x1 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK : Cycles
+event:0x2 counters:0,1,2,3 um:zero minimum:3000 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
+event:0x3 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops (counts 2 for load/store w/update)
+event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
+event:0x5 counters:0,1,2,3 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded
+event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
+event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
+event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
+event:0xb counters:0,1,2,3 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects
+event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished
+event:0xd counters:0,1,2,3 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finished
+event:0xe counters:0,1,2,3 um:zero minimum:500 name:BIFFED_BRANCHES_FINISHED : Biffed branches finished
+event:0xf counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch instructions mispredicted due to direction, target, or IAB prediction
+event:0x10 counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED_DIRECTION : Branches mispredicted due to direction prediction
+event:0x11 counters:0,1,2,3 um:zero minimum:500 name:BTB_HITS : Branches that hit in the BTB, or missed but are not taken
+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
+event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued
+event:0x14 counters:0,1,2,3 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued
+event:0x15 counters:0,1,2,3 um:zero minimum:500 name:SRS0_SCHEDULE_STALLED : Cycles SRS0 is not empty but 0 instructions scheduled
+event:0x16 counters:0,1,2,3 um:zero minimum:500 name:SRS1_SCHEDULE_STALLED : Cycles SRS1 is not empty but 0 instructions scheduled
+event:0x17 counters:0,1,2,3 um:zero minimum:500 name:VRS_SCHEDULE_STALLED : Cycles VRS is not empty but 0 instructions scheduled
+event:0x18 counters:0,1,2,3 um:zero minimum:500 name:LRS_SCHEDULE_STALLED : Cycles LRS is not empty but 0 instructions scheduled
+event:0x19 counters:0,1,2,3 um:zero minimum:500 name:BRS_SCHEDULE_STALLED : Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events
+event:0x1a counters:0,1,2,3 um:zero minimum:500 name:TOTAL_TRANSLATED : Total Ldst microops translated.
+event:0x1b counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED : Number of cacheable L* or EVL* microops translated. (This includes microops from load-multiple, load-update, and load-context instructions.)
+event:0x1c counters:0,1,2,3 um:zero minimum:500 name:STORES_TRANSLATED : Number of cacheable ST* or EVST* microops translated. (This includes microops from store-multiple, store-update, and save-context instructions.)
+event:0x1d counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED : Number of cacheable DCBT and DCBTST instructions translated (L1 only) (Does not count touches that are converted to nops i.e. exceptions, noncacheable, hid0[nopti] bit is set.)
+event:0x1e counters:0,1,2,3 um:zero minimum:500 name:CACHEOPS_TRANSLATED : Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi)
+event:0x1f counters:0,1,2,3 um:zero minimum:500 name:CACHEINHIBITED_ACCESSES_TRANSLATED : Number of cache inhibited accesses translated
+event:0x20 counters:0,1,2,3 um:zero minimum:500 name:GUARDED_LOADS_TRANSLATED : Number of guarded loads translated
+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:WRITETHROUGH_STORES_TRANSLATED : Number of write-through stores translated
+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES_TRANSLATED : Number of misaligned load or store accesses translated.
+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:TOTAL_ALLOCATED_DLFB : Total allocated to dLFB
+event:0x24 counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED_ALLOCATED_DLFB : Loads translated and allocated to dLFB (Applies to same class of instructions as loads translated.)
+event:0x25 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED_ALLOCATED_DLFB : Stores completed and allocated to dLFB (Applies to same class of instructions as stores translated.)
+event:0x26 counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED_ALLOCATED_DLFB : Touches translated and allocated to dLFB (Applies to same class of instructions as touches translated.)
+event:0x27 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED : Number of cacheable ST* or EVST* microops completed. (Applies to the same class of instructions as stores translated.)
+event:0x28 counters:0,1,2,3 um:zero minimum:500 name:DL1_LOCKS : Number of cache lines locked in the dL1. (Counts a lock even if an overlock condition is encountered.)
+event:0x29 counters:0,1,2,3 um:zero minimum:500 name:DL1_RELOADS : This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason.
+event:0x2a counters:0,1,2,3 um:zero minimum:500 name:DL1_CASTOUTS : dL1 castouts. Does not count castouts due to DCBF.
+event:0x2b counters:0,1,2,3 um:zero minimum:500 name:DETECTED_REPLAYS : Times detected replay condition - Load miss with dLFB full.
+event:0x2c counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_REPLAYS : Load miss with load queue full.
+event:0x2d counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_REPLAYS : Load guarded miss when the load is not yet at the bottom of the completion buffer.
+event:0x2e counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_REPLAYS : Translate a store when the StQ is full.
+event:0x2f counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_REPLAYS : Address collision.
+event:0x30 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_REPLAYS : DMMU_MISS_REPLAYS : DMMU miss.
+event:0x31 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_REPLAYS : DMMU_BUSY_REPLAYS : DMMU busy.
+event:0x32 counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS : Second part of misaligned access when first part missed in cache.
+event:0x33 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_DLFB_FULL_CYCLES : Cycles stalled on replay condition - Load miss with dLFB full.
+event:0x34 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Load miss with load queue full.
+event:0x35 counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_CYCLES : Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer.
+event:0x36 counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Translate a store when the StQ is full.
+event:0x37 counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_CYCLES : Cycles stalled on replay condition - Address collision.
+event:0x38 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_CYCLES : Cycles stalled on replay condition - DMMU miss.
+event:0x39 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_CYCLES : Cycles stalled on replay condition - DMMU busy.
+event:0x3a counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES : Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache.
+event:0x3b counters:0,1,2,3 um:zero minimum:500 name:IL1_LOCKS : Number of cache lines locked in the iL1. (Counts a lock even if an overlock condition is encountered.)
+event:0x3c counters:0,1,2,3 um:zero minimum:500 name:IL1_FETCH_RELOADS : This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch.
+event:0x3d counters:0,1,2,3 um:zero minimum:500 name:FETCHES : Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)
+event:0x3e counters:0,1,2,3 um:zero minimum:500 name:IMMU_TLB4K_RELOADS : iMMU TLB4K reloads
+event:0x3f counters:0,1,2,3 um:zero minimum:500 name:IMMU_VSP_RELOADS : iMMU VSP reloads
+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DMMU_TLB4K_RELOADS : dMMU TLB4K reloads
+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DMMU_VSP_RELOADS : dMMU VSP reloads
+event:0x42 counters:0,1,2,3 um:zero minimum:500 name:L2MMU_MISSES : Counts iTLB/dTLB error interrupt
+event:0x43 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_REQUESTS : Number of master transactions. (Number of master TSs.)
+event:0x44 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_I_REQUESTS : Number of master I-Side transactions. (Number of master I-Side TSs.)
+event:0x45 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_REQUESTS : Number of master D-Side transactions. (Number of master D-Side TSs.)
+event:0x46 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_CASTOUT_REQUESTS : Number of master D-Side non-program-demand castout transactions. This counts replacement pushes and snoop pushes. This does not count DCBF castouts. (Number of master D-side non-program-demand castout TSs.)
+event:0x47 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_RETRIES : Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.)
+event:0x48 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_REQUESTS : Number of externally generated snoop requests. (Counts snoop TSs.)
+event:0x49 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_HITS : Number of snoop hits on all D-side resources regardless of the cache state (modified, exclusive, or shared)
+event:0x4a counters:0,1,2,3 um:zero minimum:500 name:SNOOP_PUSHES : Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.)
+event:0x4b counters:0,1,2,3 um:zero minimum:500 name:SNOOP_RETRIES : Number of snoop requests retried. (Counts snoop ARTRYs.)
+event:0x52 counters:0,1,2,3 um:zero minimum:500 name:PMC0_OVERFLOW : Counts the number of times PMC0[32] transitioned from 1 to 0.
+event:0x53 counters:0,1,2,3 um:zero minimum:500 name:PMC1_OVERFLOW : Counts the number of times PMC1[32] transitioned from 1 to 0.
+event:0x54 counters:0,1,2,3 um:zero minimum:500 name:PMC2_OVERFLOW : Counts the number of times PMC2[32] transitioned from 1 to 0.
+event:0x55 counters:0,1,2,3 um:zero minimum:500 name:PMC3_OVERFLOW : Counts the number of times PMC3[32] transitioned from 1 to 0.
+event:0x56 counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS : Number of interrupts taken
+event:0x57 counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_INTERRUPTS : Number of external input interrupts taken
+event:0x58 counters:0,1,2,3 um:zero minimum:500 name:CRITICAL_INTERRUPTS : Number of critical input interrupts taken
+event:0x59 counters:0,1,2,3 um:zero minimum:500 name:SC_TRAP_INTERRUPTS : Number of system call and trap interrupts
diff --git a/events/ppc/e500/unit_masks b/events/ppc/e500/unit_masks
new file mode 100644
index 0000000..395c653
--- /dev/null
+++ b/events/ppc/e500/unit_masks
@@ -0,0 +1,4 @@
+# e500 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc/e500v2/events b/events/ppc/e500v2/events
new file mode 100644
index 0000000..851fd6a
--- /dev/null
+++ b/events/ppc/e500v2/events
@@ -0,0 +1,83 @@
+# e500 Events
+#
+event:0x1 counters:0,1,2,3 um:zero minimum:100 name:CPU_CLK : Cycles
+event:0x2 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_INSNS : Completed Instructions (0, 1, or 2 per cycle)
+event:0x3 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_OPS : Completed Micro-ops (counts 2 for load/store w/update)
+event:0x4 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCHES : Instruction fetches
+event:0x5 counters:0,1,2,3 um:zero minimum:500 name:DECODED_OPS : Micro-ops decoded
+event:0x8 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_BRANCHES : Branch Instructions completed
+event:0x9 counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_LOAD_OPS : Load micro-ops completed
+event:0xa counters:0,1,2,3 um:zero minimum:500 name:COMPLETED_STORE_OPS : Store micro-ops completed
+event:0xb counters:0,1,2,3 um:zero minimum:500 name:COMPLETION_REDIRECTS : Number of completion buffer redirects
+event:0xc counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_FINISHED : Branches finished
+event:0xd counters:0,1,2,3 um:zero minimum:500 name:TAKEN_BRANCHES_FINISHED : Taken branches finished
+event:0xe counters:0,1,2,3 um:zero minimum:500 name:BIFFED_BRANCHES_FINISHED : Biffed branches finished
+event:0xf counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch instructions mispredicted due to direction, target, or IAB prediction
+event:0x10 counters:0,1,2,3 um:zero minimum:500 name:BRANCHES_MISPREDICTED_DIRECTION : Branches mispredicted due to direction prediction
+event:0x11 counters:0,1,2,3 um:zero minimum:500 name:BTB_HITS : Branches that hit in the BTB, or missed but are not taken
+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:DECODE_STALLED : Cycles the instruction buffer was not empty, but 0 instructions decoded
+event:0x13 counters:0,1,2,3 um:zero minimum:500 name:ISSUE_STALLED : Cycles the issue buffer is not empty but 0 instructions issued
+event:0x14 counters:0,1,2,3 um:zero minimum:500 name:BRANCH_ISSUE_STALLED : Cycles the branch buffer is not empty but 0 instructions issued
+event:0x15 counters:0,1,2,3 um:zero minimum:500 name:SRS0_SCHEDULE_STALLED : Cycles SRS0 is not empty but 0 instructions scheduled
+event:0x16 counters:0,1,2,3 um:zero minimum:500 name:SRS1_SCHEDULE_STALLED : Cycles SRS1 is not empty but 0 instructions scheduled
+event:0x17 counters:0,1,2,3 um:zero minimum:500 name:VRS_SCHEDULE_STALLED : Cycles VRS is not empty but 0 instructions scheduled
+event:0x18 counters:0,1,2,3 um:zero minimum:500 name:LRS_SCHEDULE_STALLED : Cycles LRS is not empty but 0 instructions scheduled
+event:0x19 counters:0,1,2,3 um:zero minimum:500 name:BRS_SCHEDULE_STALLED : Cycles BRS is not empty but 0 instructions scheduled Load/Store, Data Cache, and dLFB Events
+event:0x1a counters:0,1,2,3 um:zero minimum:500 name:TOTAL_TRANSLATED : Total Ldst microops translated.
+event:0x1b counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED : Number of cacheable L* or EVL* microops translated. (This includes microops from load-multiple, load-update, and load-context instructions.)
+event:0x1c counters:0,1,2,3 um:zero minimum:500 name:STORES_TRANSLATED : Number of cacheable ST* or EVST* microops translated. (This includes microops from store-multiple, store-update, and save-context instructions.)
+event:0x1d counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED : Number of cacheable DCBT and DCBTST instructions translated (L1 only) (Does not count touches that are converted to nops i.e. exceptions, noncacheable, hid0[nopti] bit is set.)
+event:0x1e counters:0,1,2,3 um:zero minimum:500 name:CACHEOPS_TRANSLATED : Number of dcba, dcbf, dcbst, and dcbz instructions translated (e500 traps on dcbi)
+event:0x1f counters:0,1,2,3 um:zero minimum:500 name:CACHEINHIBITED_ACCESSES_TRANSLATED : Number of cache inhibited accesses translated
+event:0x20 counters:0,1,2,3 um:zero minimum:500 name:GUARDED_LOADS_TRANSLATED : Number of guarded loads translated
+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:WRITETHROUGH_STORES_TRANSLATED : Number of write-through stores translated
+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES_TRANSLATED : Number of misaligned load or store accesses translated.
+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:TOTAL_ALLOCATED_DLFB : Total allocated to dLFB
+event:0x24 counters:0,1,2,3 um:zero minimum:500 name:LOADS_TRANSLATED_ALLOCATED_DLFB : Loads translated and allocated to dLFB (Applies to same class of instructions as loads translated.)
+event:0x25 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED_ALLOCATED_DLFB : Stores completed and allocated to dLFB (Applies to same class of instructions as stores translated.)
+event:0x26 counters:0,1,2,3 um:zero minimum:500 name:TOUCHES_TRANSLATED_ALLOCATED_DLFB : Touches translated and allocated to dLFB (Applies to same class of instructions as touches translated.)
+event:0x27 counters:0,1,2,3 um:zero minimum:500 name:STORES_COMPLETED : Number of cacheable ST* or EVST* microops completed. (Applies to the same class of instructions as stores translated.)
+event:0x28 counters:0,1,2,3 um:zero minimum:500 name:DL1_LOCKS : Number of cache lines locked in the dL1. (Counts a lock even if an overlock condition is encountered.)
+event:0x29 counters:0,1,2,3 um:zero minimum:500 name:DL1_RELOADS : This is historically used to determine dcache miss rate (along with loads/stores completed). This counts dL1 reloads for any reason.
+event:0x2a counters:0,1,2,3 um:zero minimum:500 name:DL1_CASTOUTS : dL1 castouts. Does not count castouts due to DCBF.
+event:0x2b counters:0,1,2,3 um:zero minimum:500 name:DETECTED_REPLAYS : Times detected replay condition - Load miss with dLFB full.
+event:0x2c counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_REPLAYS : Load miss with load queue full.
+event:0x2d counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_REPLAYS : Load guarded miss when the load is not yet at the bottom of the completion buffer.
+event:0x2e counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_REPLAYS : Translate a store when the StQ is full.
+event:0x2f counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_REPLAYS : Address collision.
+event:0x30 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_REPLAYS : DMMU_MISS_REPLAYS : DMMU miss.
+event:0x31 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_REPLAYS : DMMU_BUSY_REPLAYS : DMMU busy.
+event:0x32 counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_REPLAYS : Second part of misaligned access when first part missed in cache.
+event:0x33 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_DLFB_FULL_CYCLES : Cycles stalled on replay condition - Load miss with dLFB full.
+event:0x34 counters:0,1,2,3 um:zero minimum:500 name:LOAD_MISS_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Load miss with load queue full.
+event:0x35 counters:0,1,2,3 um:zero minimum:500 name:LOAD_GUARDED_MISS_NOT_LAST_CYCLES : Cycles stalled on replay condition - Load guarded miss when the load is not yet at the bottom of the completion buffer.
+event:0x36 counters:0,1,2,3 um:zero minimum:500 name:STORE_TRANSLATED_QUEUE_FULL_CYCLES : Cycles stalled on replay condition - Translate a store when the StQ is full.
+event:0x37 counters:0,1,2,3 um:zero minimum:500 name:ADDRESS_COLLISION_CYCLES : Cycles stalled on replay condition - Address collision.
+event:0x38 counters:0,1,2,3 um:zero minimum:500 name:DMMU_MISS_CYCLES : Cycles stalled on replay condition - DMMU miss.
+event:0x39 counters:0,1,2,3 um:zero minimum:500 name:DMMU_BUSY_CYCLES : Cycles stalled on replay condition - DMMU busy.
+event:0x3a counters:0,1,2,3 um:zero minimum:500 name:SECOND_PART_MISALIGNED_AFTER_MISS_CYCLES : Cycles stalled on replay condition - Second part of misaligned access when first part missed in cache.
+event:0x3b counters:0,1,2,3 um:zero minimum:500 name:IL1_LOCKS : Number of cache lines locked in the iL1. (Counts a lock even if an overlock condition is encountered.)
+event:0x3c counters:0,1,2,3 um:zero minimum:500 name:IL1_FETCH_RELOADS : This is historically used to determine icache miss rate (along with instructions completed) Reloads due to demand fetch.
+event:0x3d counters:0,1,2,3 um:zero minimum:500 name:FETCHES : Counts the number of fetches that write at least one instruction to the instruction buffer. (With instruction fetched, can used to compute instructions-per-fetch)
+event:0x3e counters:0,1,2,3 um:zero minimum:500 name:IMMU_TLB4K_RELOADS : iMMU TLB4K reloads
+event:0x3f counters:0,1,2,3 um:zero minimum:500 name:IMMU_VSP_RELOADS : iMMU VSP reloads
+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DMMU_TLB4K_RELOADS : dMMU TLB4K reloads
+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DMMU_VSP_RELOADS : dMMU VSP reloads
+event:0x42 counters:0,1,2,3 um:zero minimum:500 name:L2MMU_MISSES : Counts iTLB/dTLB error interrupt
+event:0x43 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_REQUESTS : Number of master transactions. (Number of master TSs.)
+event:0x44 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_I_REQUESTS : Number of master I-Side transactions. (Number of master I-Side TSs.)
+event:0x45 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_REQUESTS : Number of master D-Side transactions. (Number of master D-Side TSs.)
+event:0x46 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_D_CASTOUT_REQUESTS : Number of master D-Side non-program-demand castout transactions. This counts replacement pushes and snoop pushes. This does not count DCBF castouts. (Number of master D-side non-program-demand castout TSs.)
+event:0x47 counters:0,1,2,3 um:zero minimum:500 name:BIU_MASTER_RETRIES : Number of transactions which were initiated by this processor which were retried on the BIU interface. (Number of master ARTRYs.)
+event:0x48 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_REQUESTS : Number of externally generated snoop requests. (Counts snoop TSs.)
+event:0x49 counters:0,1,2,3 um:zero minimum:500 name:SNOOP_HITS : Number of snoop hits on all D-side resources regardless of the cache state (modified, exclusive, or shared)
+event:0x4a counters:0,1,2,3 um:zero minimum:500 name:SNOOP_PUSHES : Number of snoop pushes from all D-side resources. (Counts snoop ARTRY/WOPs.)
+event:0x4b counters:0,1,2,3 um:zero minimum:500 name:SNOOP_RETRIES : Number of snoop requests retried. (Counts snoop ARTRYs.)
+event:0x52 counters:0,1,2,3 um:zero minimum:500 name:PMC0_OVERFLOW : Counts the number of times PMC0[32] transitioned from 1 to 0.
+event:0x53 counters:0,1,2,3 um:zero minimum:500 name:PMC1_OVERFLOW : Counts the number of times PMC1[32] transitioned from 1 to 0.
+event:0x54 counters:0,1,2,3 um:zero minimum:500 name:PMC2_OVERFLOW : Counts the number of times PMC2[32] transitioned from 1 to 0.
+event:0x55 counters:0,1,2,3 um:zero minimum:500 name:PMC3_OVERFLOW : Counts the number of times PMC3[32] transitioned from 1 to 0.
+event:0x56 counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS : Number of interrupts taken
+event:0x57 counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_INTERRUPTS : Number of external input interrupts taken
+event:0x58 counters:0,1,2,3 um:zero minimum:500 name:CRITICAL_INTERRUPTS : Number of critical input interrupts taken
+event:0x59 counters:0,1,2,3 um:zero minimum:500 name:SC_TRAP_INTERRUPTS : Number of system call and trap interrupts
diff --git a/events/ppc/e500v2/unit_masks b/events/ppc/e500v2/unit_masks
new file mode 100644
index 0000000..395c653
--- /dev/null
+++ b/events/ppc/e500v2/unit_masks
@@ -0,0 +1,4 @@
+# e500 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/970/event_mappings b/events/ppc64/970/event_mappings
new file mode 100644
index 0000000..73ce9d5
--- /dev/null
+++ b/events/ppc64/970/event_mappings
@@ -0,0 +1,494 @@
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X0400C51E mmcr1:0X000000000A46F18C mmcra:0X00002001
+
+#Group 1 pm_slice0, Time Slice 0
+event:0X010 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002001
+event:0X011 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002001
+event:0X012 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002001
+event:0X013 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002001
+event:0X014 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002001
+event:0X015 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002001
+event:0X016 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002001
+event:0X017 mmcr0:0X0000051E mmcr1:0X000000000A46F18C mmcra:0X00002001
+
+#Group 2 pm_eprof, Group for use with eprof
+event:0X020 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X021 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X022 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X023 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X024 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X025 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X026 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X027 mmcr0:0X00000F1E mmcr1:0X4003001005F09000 mmcra:0X00002001
+
+#Group 3 pm_basic, Basic performance indicators
+event:0X030 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X031 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X032 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X033 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X034 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X035 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X036 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002001
+event:0X037 mmcr0:0X0000091E mmcr1:0X4003001005F09000 mmcra:0X00002001
+
+#Group 4 pm_lsu, Information on the Load Store Unit
+event:0X040 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002001
+event:0X041 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002001
+event:0X042 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002001
+event:0X043 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002001
+event:0X044 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002001
+event:0X045 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002001
+event:0X046 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002001
+event:0X047 mmcr0:0X00000000 mmcr1:0X000F00007A400000 mmcra:0X00002001
+
+#Group 5 pm_fpu1, Floating Point events
+event:0X050 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002001
+event:0X051 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002001
+event:0X052 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002001
+event:0X053 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002001
+event:0X054 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002001
+event:0X055 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002001
+event:0X056 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002001
+event:0X057 mmcr0:0X00000000 mmcr1:0X00000000001E0480 mmcra:0X00002001
+
+#Group 6 pm_fpu2, Floating Point events
+event:0X060 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002001
+event:0X061 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002001
+event:0X062 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002001
+event:0X063 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002001
+event:0X064 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002001
+event:0X065 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002001
+event:0X066 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002001
+event:0X067 mmcr0:0X00000000 mmcr1:0X000020E87A400000 mmcra:0X00002001
+
+#Group 7 pm_isu_rename, ISU Rename Pool Events
+event:0X070 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002001
+event:0X071 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002001
+event:0X072 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002001
+event:0X073 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002001
+event:0X074 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002001
+event:0X075 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002001
+event:0X076 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002001
+event:0X077 mmcr0:0X00001228 mmcr1:0X400000218E6D84BC mmcra:0X00002001
+
+#Group 8 pm_isu_queues1, ISU Rename Pool Events
+event:0X080 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002001
+event:0X081 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002001
+event:0X082 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002001
+event:0X083 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002001
+event:0X084 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002001
+event:0X085 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002001
+event:0X086 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002001
+event:0X087 mmcr0:0X0000132E mmcr1:0X40000000851E994C mmcra:0X00002001
+
+#Group 9 pm_isu_flow, ISU Instruction Flow Events
+event:0X090 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002001
+event:0X091 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002001
+event:0X092 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002001
+event:0X093 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002001
+event:0X094 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002001
+event:0X095 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002001
+event:0X096 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002001
+event:0X097 mmcr0:0X0000181E mmcr1:0X400000B3D7B7C4BC mmcra:0X00002001
+
+#Group 10 pm_isu_work, ISU Indicators of Work Blockage
+event:0X0A0 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002001
+event:0X0A1 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002001
+event:0X0A2 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002001
+event:0X0A3 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002001
+event:0X0A4 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002001
+event:0X0A5 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002001
+event:0X0A6 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002001
+event:0X0A7 mmcr0:0X00000402 mmcr1:0X400000050FDE9D88 mmcra:0X00002001
+
+#Group 11 pm_fpu3, Floating Point events by unit
+event:0X0B0 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002001
+event:0X0B1 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002001
+event:0X0B2 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002001
+event:0X0B3 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002001
+event:0X0B4 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002001
+event:0X0B5 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002001
+event:0X0B6 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002001
+event:0X0B7 mmcr0:0X00001028 mmcr1:0X000000008D6354BC mmcra:0X00002001
+
+#Group 12 pm_fpu4, Floating Point events by unit
+event:0X0C0 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002001
+event:0X0C1 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002001
+event:0X0C2 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002001
+event:0X0C3 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002001
+event:0X0C4 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002001
+event:0X0C5 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002001
+event:0X0C6 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002001
+event:0X0C7 mmcr0:0X0000122C mmcr1:0X000000009DE774BC mmcra:0X00002001
+
+#Group 13 pm_fpu5, Floating Point events by unit
+event:0X0D0 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002001
+event:0X0D1 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002001
+event:0X0D2 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002001
+event:0X0D3 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002001
+event:0X0D4 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002001
+event:0X0D5 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002001
+event:0X0D6 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002001
+event:0X0D7 mmcr0:0X00001838 mmcr1:0X000000C0851E9958 mmcra:0X00002001
+
+#Group 14 pm_fpu7, Floating Point events by unit
+event:0X0E0 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002001
+event:0X0E1 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002001
+event:0X0E2 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002001
+event:0X0E3 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002001
+event:0X0E4 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002001
+event:0X0E5 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002001
+event:0X0E6 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002001
+event:0X0E7 mmcr0:0X0000193A mmcr1:0X000000C89DDE97E0 mmcra:0X00002001
+
+#Group 15 pm_lsu_flush, LSU Flush Events
+event:0X0F0 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002001
+event:0X0F1 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002001
+event:0X0F2 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002001
+event:0X0F3 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002001
+event:0X0F4 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002001
+event:0X0F5 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002001
+event:0X0F6 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002001
+event:0X0F7 mmcr0:0X0000122C mmcr1:0X000C00007BE774BC mmcra:0X00002001
+
+#Group 16 pm_lsu_load1, LSU Load Events
+event:0X100 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002001
+event:0X101 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002001
+event:0X102 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002001
+event:0X103 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002001
+event:0X104 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002001
+event:0X105 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002001
+event:0X106 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002001
+event:0X107 mmcr0:0X00001028 mmcr1:0X000F0000851E9958 mmcra:0X00002001
+
+#Group 17 pm_lsu_store1, LSU Store Events
+event:0X110 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002001
+event:0X111 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002001
+event:0X112 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002001
+event:0X113 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002001
+event:0X114 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002001
+event:0X115 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002001
+event:0X116 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002001
+event:0X117 mmcr0:0X0000112A mmcr1:0X000F00008D5E99DC mmcra:0X00002001
+
+#Group 18 pm_lsu_store2, LSU Store Events
+event:0X120 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002001
+event:0X121 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002001
+event:0X122 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002001
+event:0X123 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002001
+event:0X124 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002001
+event:0X125 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002001
+event:0X126 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002001
+event:0X127 mmcr0:0X00001838 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002001
+
+#Group 19 pm_lsu7, Information on the Load Store Unit
+event:0X130 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002001
+event:0X131 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002001
+event:0X132 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002001
+event:0X133 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002001
+event:0X134 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002001
+event:0X135 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002001
+event:0X136 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002001
+event:0X137 mmcr0:0X0000122C mmcr1:0X000830047BD2FE3C mmcra:0X00002001
+
+#Group 20 pm_misc, Misc Events for testing
+event:0X140 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002001
+event:0X141 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002001
+event:0X142 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002001
+event:0X143 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002001
+event:0X144 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002001
+event:0X145 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002001
+event:0X146 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002001
+event:0X147 mmcr0:0X00000404 mmcr1:0X0000000023C69194 mmcra:0X00002001
+
+#Group 21 pm_pe_bench1, PE Benchmarker group for FP analysis
+event:0X150 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002001
+event:0X151 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002001
+event:0X152 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002001
+event:0X153 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002001
+event:0X154 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002001
+event:0X155 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002001
+event:0X156 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002001
+event:0X157 mmcr0:0X00000000 mmcr1:0X10001002001E0480 mmcra:0X00002001
+
+#Group 22 pm_pe_bench4, PE Benchmarker group for L1 and TLB
+event:0X160 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X161 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X162 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X163 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X164 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X165 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X166 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X167 mmcr0:0X00001420 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+
+#Group 23 pm_hpmcount1, Hpmcount group for L1 and TLB behavior
+event:0X170 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X171 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X172 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X173 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X174 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X175 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X176 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+event:0X177 mmcr0:0X00001404 mmcr1:0X000B000004DE9000 mmcra:0X00002001
+
+#Group 24 pm_hpmcount2, Hpmcount group for computation
+event:0X180 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002001
+event:0X181 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002001
+event:0X182 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002001
+event:0X183 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002001
+event:0X184 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002001
+event:0X185 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002001
+event:0X186 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002001
+event:0X187 mmcr0:0X00000000 mmcr1:0X000020289DDE0480 mmcra:0X00002001
+
+#Group 25 pm_l1andbr, L1 misses and branch misspredict analysis
+event:0X190 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002001
+event:0X191 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002001
+event:0X192 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002001
+event:0X193 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002001
+event:0X194 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002001
+event:0X195 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002001
+event:0X196 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002001
+event:0X197 mmcr0:0X0000091E mmcr1:0X8003C01D0676FD6C mmcra:0X00002001
+
+#Group 26 pm_imix, Instruction mix: loads, stores and branches
+event:0X1A0 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002001
+event:0X1A1 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002001
+event:0X1A2 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002001
+event:0X1A3 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002001
+event:0X1A4 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002001
+event:0X1A5 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002001
+event:0X1A6 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002001
+event:0X1A7 mmcr0:0X0000091E mmcr1:0X8003C021065FB000 mmcra:0X00002001
+
+#Group 27 pm_branch, SLB and branch misspredict analysis
+event:0X1B0 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002001
+event:0X1B1 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002001
+event:0X1B2 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002001
+event:0X1B3 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002001
+event:0X1B4 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002001
+event:0X1B5 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002001
+event:0X1B6 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002001
+event:0X1B7 mmcr0:0X0000052A mmcr1:0X8008000BCEA2F4EC mmcra:0X00002001
+
+#Group 28 pm_data, data source and LMQ
+event:0X1C0 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002001
+event:0X1C1 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002001
+event:0X1C2 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002001
+event:0X1C3 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002001
+event:0X1C4 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002001
+event:0X1C5 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002001
+event:0X1C6 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002001
+event:0X1C7 mmcr0:0X00000712 mmcr1:0X0000300E3BD2FF74 mmcra:0X00002001
+
+#Group 29 pm_tlb, TLB and LRQ plus data prefetch
+event:0X1D0 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002001
+event:0X1D1 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002001
+event:0X1D2 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002001
+event:0X1D3 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002001
+event:0X1D4 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002001
+event:0X1D5 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002001
+event:0X1D6 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002001
+event:0X1D7 mmcr0:0X00001420 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002001
+
+#Group 30 pm_isource, inst source and tablewalk
+event:0X1E0 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002001
+event:0X1E1 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002001
+event:0X1E2 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002001
+event:0X1E3 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002001
+event:0X1E4 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002001
+event:0X1E5 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002001
+event:0X1E6 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002001
+event:0X1E7 mmcr0:0X0000060C mmcr1:0X800B00C0226EF1DC mmcra:0X00002001
+
+#Group 31 pm_sync, Sync and SRQ
+event:0X1F0 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002001
+event:0X1F1 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002001
+event:0X1F2 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002001
+event:0X1F3 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002001
+event:0X1F4 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002001
+event:0X1F5 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002001
+event:0X1F6 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002001
+event:0X1F7 mmcr0:0X00001D32 mmcr1:0X0003E0C107529780 mmcra:0X00002001
+
+#Group 32 pm_ierat, IERAT
+event:0X200 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002001
+event:0X201 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002001
+event:0X202 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002001
+event:0X203 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002001
+event:0X204 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002001
+event:0X205 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002001
+event:0X206 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002001
+event:0X207 mmcr0:0X00000D12 mmcr1:0X80000082C3D2F4BC mmcra:0X00002001
+
+#Group 33 pm_derat, DERAT
+event:0X210 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002001
+event:0X211 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002001
+event:0X212 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002001
+event:0X213 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002001
+event:0X214 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002001
+event:0X215 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002001
+event:0X216 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002001
+event:0X217 mmcr0:0X00000436 mmcr1:0X100B7052E274003C mmcra:0X00002001
+
+#Group 34 pm_mark1, Information on marked instructions
+event:0X220 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X221 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X222 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X223 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X224 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X225 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X226 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X227 mmcr0:0X00000006 mmcr1:0X00008080790852A4 mmcra:0X00002001
+
+#Group 35 pm_mark2, Marked Instructions Processing Flow
+event:0X230 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X231 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X232 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X233 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X234 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X235 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X236 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X237 mmcr0:0X0000020A mmcr1:0X0000000079484210 mmcra:0X00002001
+
+#Group 36 pm_mark3, Marked Stores Processing Flow
+event:0X240 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X241 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X242 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X243 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X244 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X245 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X246 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X247 mmcr0:0X0000031E mmcr1:0X00203004190A3F24 mmcra:0X00002001
+
+#Group 37 pm_lsu_mark1, Load Store Unit Marked Events
+event:0X250 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X251 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X252 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X253 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X254 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X255 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X256 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X257 mmcr0:0X00001B34 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+
+#Group 38 pm_lsu_mark2, Load Store Unit Marked Events
+event:0X260 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X261 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X262 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X263 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X264 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X265 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X266 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X267 mmcr0:0X00001838 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+
+#Group 39 pm_fxu1, Fixed Point events by unit
+event:0X270 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002001
+event:0X271 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002001
+event:0X272 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002001
+event:0X273 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002001
+event:0X274 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002001
+event:0X275 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002001
+event:0X276 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002001
+event:0X277 mmcr0:0X00000912 mmcr1:0X100010020084213C mmcra:0X00002001
+
+#Group 40 pm_fxu2, Fixed Point events by unit
+event:0X280 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002001
+event:0X281 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002001
+event:0X282 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002001
+event:0X283 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002001
+event:0X284 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002001
+event:0X285 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002001
+event:0X286 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002001
+event:0X287 mmcr0:0X0000091E mmcr1:0X4000000CA4042D78 mmcra:0X00002001
+
+#Group 41 pm_ifu, pm_ifu
+event:0X290 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002001
+event:0X291 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002001
+event:0X292 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002001
+event:0X293 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002001
+event:0X294 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002001
+event:0X295 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002001
+event:0X296 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002001
+event:0X297 mmcr0:0X00000D0C mmcr1:0X800000F06B7867A4 mmcra:0X00002001
+
+#Group 42 pm_cpi_stack1, CPI stack analysis
+event:0X2A0 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002001
+event:0X2A1 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002001
+event:0X2A2 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002001
+event:0X2A3 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002001
+event:0X2A4 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002001
+event:0X2A5 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002001
+event:0X2A6 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002001
+event:0X2A7 mmcr0:0X00001B3E mmcr1:0X4000C0C0ADD6963D mmcra:0X00002001
+
+#Group 43 pm_cpi_stack2, CPI stack analysis
+event:0X2B0 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002001
+event:0X2B1 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002001
+event:0X2B2 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002001
+event:0X2B3 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002001
+event:0X2B4 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002001
+event:0X2B5 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002001
+event:0X2B6 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002001
+event:0X2B7 mmcr0:0X00000B12 mmcr1:0X000B000003D60583 mmcra:0X00002001
+
+#Group 44 pm_cpi_stack3, CPI stack analysis
+event:0X2C0 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002001
+event:0X2C1 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002001
+event:0X2C2 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002001
+event:0X2C3 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002001
+event:0X2C4 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002001
+event:0X2C5 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002001
+event:0X2C6 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002001
+event:0X2C7 mmcr0:0X00000916 mmcr1:0X10001002001625BE mmcra:0X00002001
+
+#Group 45 pm_cpi_stack4, CPI stack analysis
+event:0X2D0 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002001
+event:0X2D1 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002001
+event:0X2D2 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002001
+event:0X2D3 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002001
+event:0X2D4 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002001
+event:0X2D5 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002001
+event:0X2D6 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002001
+event:0X2D7 mmcr0:0X00000000 mmcr1:0X00000000485805BD mmcra:0X00002001
+
+#Group 46 pm_cpi_stack5, CPI stack analysis
+event:0X2E0 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002001
+event:0X2E1 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002001
+event:0X2E2 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002001
+event:0X2E3 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002001
+event:0X2E4 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002001
+event:0X2E5 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002001
+event:0X2E6 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002001
+event:0X2E7 mmcr0:0X00000412 mmcr1:0X90010009B6D8F672 mmcra:0X00002001
+
+#Group 47 pm_data2, data source and LMQ
+event:0X2F0 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002001
+event:0X2F1 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002001
+event:0X2F2 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002001
+event:0X2F3 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002001
+event:0X2F4 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002001
+event:0X2F5 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002001
+event:0X2F6 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002001
+event:0X2F7 mmcr0:0X00000D12 mmcr1:0X0000300E6BD2FF74 mmcra:0X00002001
+
+#Group 48 pm_fetch_branch, Instruction fetch and branch events
+event:0X300 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002001
+event:0X301 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002001
+event:0X302 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002001
+event:0X303 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002001
+event:0X304 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002001
+event:0X305 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002001
+event:0X306 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002001
+event:0X307 mmcr0:0X0000060C mmcr1:0X800000CD6E5E9D6C mmcra:0X00002001
+
+#Group 49 pm_l1l2_miss, L1 and L2 miss events
+event:0X310 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002001
+event:0X311 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002001
+event:0X312 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002001
+event:0X313 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002001
+event:0X314 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002001
+event:0X315 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002001
+event:0X316 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002001
+event:0X317 mmcr0:0X00000712 mmcr1:0X000330023C86FB00 mmcra:0X00002001
diff --git a/events/ppc64/970/events b/events/ppc64/970/events
new file mode 100644
index 0000000..e1c6057
--- /dev/null
+++ b/events/ppc64/970/events
@@ -0,0 +1,505 @@
+#PPC64 PowerPC970 events
+#
+# Within each group the event names must be unique. Each event in a group is
+# assigned to a unique counter. The groups are from the groups defined in the
+# Performance Monitor Unit user guide for this processor.
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
+
+
+#Group 1 pm_slice0, Time Slice 0
+event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
+event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
+event:0X012 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP1 : (Group 1 pm_slice0) Completion stopped
+event:0X013 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_slice0) Instructions completed
+event:0X014 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP1 : (Group 1 pm_slice0) One or more PPC instruction completed
+event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
+event:0X016 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP1 : (Group 1 pm_slice0) Group completed
+event:0X017 counters:7 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP1 : (Group 1 pm_slice0) Group dispatch rejected
+
+#Group 2 pm_eprof, Group for use with eprof
+event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
+event:0X021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
+event:0X022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
+event:0X023 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP2 : (Group 2 pm_eprof) L1 D cache entries invalidated from L2
+event:0X024 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP2 : (Group 2 pm_eprof) Instructions dispatched
+event:0X025 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP2 : (Group 2 pm_eprof) Instructions completed
+event:0X026 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache store references
+event:0X027 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load references
+
+#Group 3 pm_basic, Basic performance indicators
+event:0X030 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed
+event:0X031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles
+event:0X032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
+event:0X033 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP3 : (Group 3 pm_basic) L1 D cache entries invalidated from L2
+event:0X034 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_basic) Instructions dispatched
+event:0X035 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed
+event:0X036 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache store references
+event:0X037 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache load references
+
+#Group 4 pm_lsu, Information on the Load Store Unit
+event:0X040 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP4 : (Group 4 pm_lsu) LRQ unaligned load flushes
+event:0X041 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP4 : (Group 4 pm_lsu) SRQ unaligned store flushes
+event:0X042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles
+event:0X043 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP4 : (Group 4 pm_lsu) Instructions completed
+event:0X044 counters:4 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP4 : (Group 4 pm_lsu) SRQ flushes
+event:0X045 counters:5 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP4 : (Group 4 pm_lsu) LRQ flushes
+event:0X046 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP4 : (Group 4 pm_lsu) L1 D cache store references
+event:0X047 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP4 : (Group 4 pm_lsu) L1 D cache load references
+
+#Group 5 pm_fpu1, Floating Point events
+event:0X050 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP5 : (Group 5 pm_fpu1) FPU executed FDIV instruction
+event:0X051 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP5 : (Group 5 pm_fpu1) FPU executed multiply-add instruction
+event:0X052 counters:2 um:zero minimum:1000 name:PM_FPU_FEST_GRP5 : (Group 5 pm_fpu1) FPU executed FEST instruction
+event:0X053 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP5 : (Group 5 pm_fpu1) FPU produced a result
+event:0X054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles
+event:0X055 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP5 : (Group 5 pm_fpu1) FPU executed FSQRT instruction
+event:0X056 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP5 : (Group 5 pm_fpu1) Instructions completed
+event:0X057 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP5 : (Group 5 pm_fpu1) FPU executing FMOV or FEST instructions
+
+#Group 6 pm_fpu2, Floating Point events
+event:0X060 counters:0 um:zero minimum:1000 name:PM_FPU_DENORM_GRP6 : (Group 6 pm_fpu2) FPU received denormalized data
+event:0X061 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP6 : (Group 6 pm_fpu2) FPU stalled in pipe3
+event:0X062 counters:2 um:zero minimum:10000 name:PM_CYC_GRP6 : (Group 6 pm_fpu2) Processor cycles
+event:0X063 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP6 : (Group 6 pm_fpu2) Instructions completed
+event:0X064 counters:4 um:zero minimum:1000 name:PM_FPU_ALL_GRP6 : (Group 6 pm_fpu2) FPU executed add, mult, sub, cmp or sel instruction
+event:0X065 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP6 : (Group 6 pm_fpu2) FPU executed store instruction
+event:0X066 counters:6 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP6 : (Group 6 pm_fpu2) FPU executed FRSP or FCONV instructions
+event:0X067 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP6 : (Group 6 pm_fpu2) LSU executed Floating Point load instruction
+
+#Group 7 pm_isu_rename, ISU Rename Pool Events
+event:0X070 counters:0 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles XER mapper full
+event:0X071 counters:1 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles CR logical operation mapper full
+event:0X072 counters:2 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles CR issue queue full
+event:0X073 counters:3 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles group dispatch blocked by scoreboard
+event:0X074 counters:4 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles LR/CTR mapper full
+event:0X075 counters:5 um:zero minimum:1000 name:PM_INST_DISP_GRP7 : (Group 7 pm_isu_rename) Instructions dispatched
+event:0X076 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP7 : (Group 7 pm_isu_rename) Instructions completed
+event:0X077 counters:7 um:zero minimum:10000 name:PM_CYC_GRP7 : (Group 7 pm_isu_rename) Processor cycles
+
+#Group 8 pm_isu_queues1, ISU Rename Pool Events
+event:0X080 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FPU0 issue queue full
+event:0X081 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FPU1 issue queue full
+event:0X082 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FXU0/LS0 queue full
+event:0X083 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FXU1/LS1 queue full
+event:0X084 counters:4 um:zero minimum:10000 name:PM_CYC_GRP8 : (Group 8 pm_isu_queues1) Processor cycles
+event:0X085 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP8 : (Group 8 pm_isu_queues1) Instructions completed
+event:0X086 counters:6 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles LRQ full
+event:0X087 counters:7 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles SRQ full
+
+#Group 9 pm_isu_flow, ISU Instruction Flow Events
+event:0X090 counters:0 um:zero minimum:1000 name:PM_INST_DISP_GRP9 : (Group 9 pm_isu_flow) Instructions dispatched
+event:0X091 counters:1 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_isu_flow) Processor cycles
+event:0X092 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP9 : (Group 9 pm_isu_flow) FXU0 produced a result
+event:0X093 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP9 : (Group 9 pm_isu_flow) FXU1 produced a result
+event:0X094 counters:4 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP9 : (Group 9 pm_isu_flow) Group dispatch valid
+event:0X095 counters:5 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP9 : (Group 9 pm_isu_flow) Group dispatch rejected
+event:0X096 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP9 : (Group 9 pm_isu_flow) Instructions completed
+event:0X097 counters:7 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_isu_flow) Processor cycles
+
+#Group 10 pm_isu_work, ISU Indicators of Work Blockage
+event:0X0A0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP10 : (Group 10 pm_isu_work) Cycles GCT empty
+event:0X0A1 counters:1 um:zero minimum:1000 name:PM_WORK_HELD_GRP10 : (Group 10 pm_isu_work) Work held
+event:0X0A2 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP10 : (Group 10 pm_isu_work) Completion stopped
+event:0X0A3 counters:3 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off and external interrupt pending
+event:0X0A4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP10 : (Group 10 pm_isu_work) Processor cycles
+event:0X0A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP10 : (Group 10 pm_isu_work) Instructions completed
+event:0X0A6 counters:6 um:zero minimum:1000 name:PM_EE_OFF_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off
+event:0X0A7 counters:7 um:zero minimum:1000 name:PM_EXT_INT_GRP10 : (Group 10 pm_isu_work) External interrupts
+
+#Group 11 pm_fpu3, Floating Point events by unit
+event:0X0B0 counters:0 um:zero minimum:1000 name:PM_FPU0_FDIV_GRP11 : (Group 11 pm_fpu3) FPU0 executed FDIV instruction
+event:0X0B1 counters:1 um:zero minimum:1000 name:PM_FPU1_FDIV_GRP11 : (Group 11 pm_fpu3) FPU1 executed FDIV instruction
+event:0X0B2 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP11 : (Group 11 pm_fpu3) FPU0 executed FRSP or FCONV instructions
+event:0X0B3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP11 : (Group 11 pm_fpu3) FPU1 executed FRSP or FCONV instructions
+event:0X0B4 counters:4 um:zero minimum:1000 name:PM_FPU0_FMA_GRP11 : (Group 11 pm_fpu3) FPU0 executed multiply-add instruction
+event:0X0B5 counters:5 um:zero minimum:1000 name:PM_FPU1_FMA_GRP11 : (Group 11 pm_fpu3) FPU1 executed multiply-add instruction
+event:0X0B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP11 : (Group 11 pm_fpu3) Instructions completed
+event:0X0B7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP11 : (Group 11 pm_fpu3) Processor cycles
+
+#Group 12 pm_fpu4, Floating Point events by unit
+event:0X0C0 counters:0 um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU0 executed FSQRT instruction
+event:0X0C1 counters:1 um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU1 executed FSQRT instruction
+event:0X0C2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP12 : (Group 12 pm_fpu4) FPU0 produced a result
+event:0X0C3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP12 : (Group 12 pm_fpu4) FPU1 produced a result
+event:0X0C4 counters:4 um:zero minimum:1000 name:PM_FPU0_ALL_GRP12 : (Group 12 pm_fpu4) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X0C5 counters:5 um:zero minimum:1000 name:PM_FPU1_ALL_GRP12 : (Group 12 pm_fpu4) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X0C6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP12 : (Group 12 pm_fpu4) Instructions completed
+event:0X0C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP12 : (Group 12 pm_fpu4) Processor cycles
+
+#Group 13 pm_fpu5, Floating Point events by unit
+event:0X0D0 counters:0 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP13 : (Group 13 pm_fpu5) FPU0 received denormalized data
+event:0X0D1 counters:1 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP13 : (Group 13 pm_fpu5) FPU1 received denormalized data
+event:0X0D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FMOV_FEST_GRP13 : (Group 13 pm_fpu5) FPU0 executed FMOV or FEST instructions
+event:0X0D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FMOV_FEST_GRP13 : (Group 13 pm_fpu5) FPU1 executing FMOV or FEST instructions
+event:0X0D4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP13 : (Group 13 pm_fpu5) Processor cycles
+event:0X0D5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP13 : (Group 13 pm_fpu5) Instructions completed
+event:0X0D6 counters:6 um:zero minimum:1000 name:PM_FPU0_FEST_GRP13 : (Group 13 pm_fpu5) FPU0 executed FEST instruction
+event:0X0D7 counters:7 um:zero minimum:1000 name:PM_FPU1_FEST_GRP13 : (Group 13 pm_fpu5) FPU1 executed FEST instruction
+
+#Group 14 pm_fpu7, Floating Point events by unit
+event:0X0E0 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP14 : (Group 14 pm_fpu7) FPU0 stalled in pipe3
+event:0X0E1 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP14 : (Group 14 pm_fpu7) FPU1 stalled in pipe3
+event:0X0E2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP14 : (Group 14 pm_fpu7) FPU0 produced a result
+event:0X0E3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP14 : (Group 14 pm_fpu7) FPU1 produced a result
+event:0X0E4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_fpu7) Processor cycles
+event:0X0E5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP14 : (Group 14 pm_fpu7) Instructions completed
+event:0X0E6 counters:6 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_fpu7) Processor cycles
+event:0X0E7 counters:7 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP14 : (Group 14 pm_fpu7) FPU0 executed FPSCR instruction
+
+#Group 15 pm_lsu_flush, LSU Flush Events
+event:0X0F0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP15 : (Group 15 pm_lsu_flush) LSU0 LRQ flushes
+event:0X0F1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP15 : (Group 15 pm_lsu_flush) LSU1 LRQ flushes
+event:0X0F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
+event:0X0F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
+event:0X0F4 counters:4 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_flush) LSU0 SRQ flushes
+event:0X0F5 counters:5 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_flush) LSU1 SRQ flushes
+event:0X0F6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP15 : (Group 15 pm_lsu_flush) Instructions completed
+event:0X0F7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
+
+#Group 16 pm_lsu_load1, LSU Load Events
+event:0X100 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP16 : (Group 16 pm_lsu_load1) LSU0 unaligned load flushes
+event:0X101 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP16 : (Group 16 pm_lsu_load1) LSU1 unaligned load flushes
+event:0X102 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load references
+event:0X103 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load references
+event:0X104 counters:4 um:zero minimum:10000 name:PM_CYC_GRP16 : (Group 16 pm_lsu_load1) Processor cycles
+event:0X105 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP16 : (Group 16 pm_lsu_load1) Instructions completed
+event:0X106 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load misses
+event:0X107 counters:7 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load misses
+
+#Group 17 pm_lsu_store1, LSU Store Events
+event:0X110 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP17 : (Group 17 pm_lsu_store1) LSU0 unaligned store flushes
+event:0X111 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP17 : (Group 17 pm_lsu_store1) LSU1 unaligned store flushes
+event:0X112 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP17 : (Group 17 pm_lsu_store1) LSU0 L1 D cache store references
+event:0X113 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP17 : (Group 17 pm_lsu_store1) LSU1 L1 D cache store references
+event:0X114 counters:4 um:zero minimum:10000 name:PM_CYC_GRP17 : (Group 17 pm_lsu_store1) Processor cycles
+event:0X115 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP17 : (Group 17 pm_lsu_store1) Instructions completed
+event:0X116 counters:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP17 : (Group 17 pm_lsu_store1) L1 D cache store misses
+event:0X117 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP17 : (Group 17 pm_lsu_store1) L1 D cache entries invalidated from L2
+
+#Group 18 pm_lsu_store2, LSU Store Events
+event:0X120 counters:0 um:zero minimum:1000 name:PM_LSU0_SRQ_STFWD_GRP18 : (Group 18 pm_lsu_store2) LSU0 SRQ store forwarded
+event:0X121 counters:1 um:zero minimum:1000 name:PM_LSU1_SRQ_STFWD_GRP18 : (Group 18 pm_lsu_store2) LSU1 SRQ store forwarded
+event:0X122 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP18 : (Group 18 pm_lsu_store2) LSU0 L1 D cache store references
+event:0X123 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP18 : (Group 18 pm_lsu_store2) LSU1 L1 D cache store references
+event:0X124 counters:4 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP18 : (Group 18 pm_lsu_store2) LSU0 busy
+event:0X125 counters:5 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_lsu_store2) Processor cycles
+event:0X126 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP18 : (Group 18 pm_lsu_store2) Instructions completed
+event:0X127 counters:7 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_lsu_store2) Processor cycles
+
+#Group 19 pm_lsu7, Information on the Load Store Unit
+event:0X130 counters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU0 DERAT misses
+event:0X131 counters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU1 DERAT misses
+event:0X132 counters:2 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
+event:0X133 counters:3 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
+event:0X134 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP19 : (Group 19 pm_lsu7) Instructions completed
+event:0X135 counters:5 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
+event:0X136 counters:6 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP19 : (Group 19 pm_lsu7) L1 reload data source valid
+event:0X137 counters:7 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
+
+#Group 20 pm_misc, Misc Events for testing
+event:0X140 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP20 : (Group 20 pm_misc) Cycles GCT empty
+event:0X141 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP20 : (Group 20 pm_misc) Cycles LMQ and SRQ empty
+event:0X142 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP20 : (Group 20 pm_misc) Hypervisor Cycles
+event:0X143 counters:3 um:zero minimum:10000 name:PM_CYC_GRP20 : (Group 20 pm_misc) Processor cycles
+event:0X144 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP20 : (Group 20 pm_misc) One or more PPC instruction completed
+event:0X145 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP20 : (Group 20 pm_misc) Instructions completed
+event:0X146 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP20 : (Group 20 pm_misc) Group completed
+event:0X147 counters:7 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP20 : (Group 20 pm_misc) Time Base bit transition
+
+#Group 21 pm_pe_bench1, PE Benchmarker group for FP analysis
+event:0X150 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP21 : (Group 21 pm_pe_bench1) FPU executed FDIV instruction
+event:0X151 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP21 : (Group 21 pm_pe_bench1) FPU executed multiply-add instruction
+event:0X152 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP21 : (Group 21 pm_pe_bench1) FXU produced a result
+event:0X153 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP21 : (Group 21 pm_pe_bench1) FPU produced a result
+event:0X154 counters:4 um:zero minimum:10000 name:PM_CYC_GRP21 : (Group 21 pm_pe_bench1) Processor cycles
+event:0X155 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP21 : (Group 21 pm_pe_bench1) FPU executed FSQRT instruction
+event:0X156 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP21 : (Group 21 pm_pe_bench1) Instructions completed
+event:0X157 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP21 : (Group 21 pm_pe_bench1) FPU executing FMOV or FEST instructions
+
+#Group 22 pm_pe_bench4, PE Benchmarker group for L1 and TLB
+event:0X160 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Data TLB misses
+event:0X161 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Instruction TLB misses
+event:0X162 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load misses
+event:0X163 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache store misses
+event:0X164 counters:4 um:zero minimum:10000 name:PM_CYC_GRP22 : (Group 22 pm_pe_bench4) Processor cycles
+event:0X165 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP22 : (Group 22 pm_pe_bench4) Instructions completed
+event:0X166 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache store references
+event:0X167 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load references
+
+#Group 23 pm_hpmcount1, Hpmcount group for L1 and TLB behavior
+event:0X170 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP23 : (Group 23 pm_hpmcount1) Data TLB misses
+event:0X171 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP23 : (Group 23 pm_hpmcount1) Cycles LMQ and SRQ empty
+event:0X172 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache load misses
+event:0X173 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache store misses
+event:0X174 counters:4 um:zero minimum:10000 name:PM_CYC_GRP23 : (Group 23 pm_hpmcount1) Processor cycles
+event:0X175 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP23 : (Group 23 pm_hpmcount1) Instructions completed
+event:0X176 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache store references
+event:0X177 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache load references
+
+#Group 24 pm_hpmcount2, Hpmcount group for computation
+event:0X180 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP24 : (Group 24 pm_hpmcount2) FPU executed FDIV instruction
+event:0X181 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP24 : (Group 24 pm_hpmcount2) FPU executed multiply-add instruction
+event:0X182 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP24 : (Group 24 pm_hpmcount2) FPU0 produced a result
+event:0X183 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP24 : (Group 24 pm_hpmcount2) FPU1 produced a result
+event:0X184 counters:4 um:zero minimum:10000 name:PM_CYC_GRP24 : (Group 24 pm_hpmcount2) Processor cycles
+event:0X185 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP24 : (Group 24 pm_hpmcount2) FPU executed store instruction
+event:0X186 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP24 : (Group 24 pm_hpmcount2) Instructions completed
+event:0X187 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP24 : (Group 24 pm_hpmcount2) LSU executed Floating Point load instruction
+
+#Group 25 pm_l1andbr, L1 misses and branch misspredict analysis
+event:0X190 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP25 : (Group 25 pm_l1andbr) Instructions completed
+event:0X191 counters:1 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_l1andbr) Processor cycles
+event:0X192 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP25 : (Group 25 pm_l1andbr) L1 D cache load misses
+event:0X193 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP25 : (Group 25 pm_l1andbr) Branches issued
+event:0X194 counters:4 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP25 : (Group 25 pm_l1andbr) LSU0 busy
+event:0X195 counters:5 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_l1andbr) Processor cycles
+event:0X196 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP25 : (Group 25 pm_l1andbr) Branch mispredictions due to CR bit setting
+event:0X197 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP25 : (Group 25 pm_l1andbr) Branch mispredictions due to target address
+
+#Group 26 pm_imix, Instruction mix: loads, stores and branches
+event:0X1A0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP26 : (Group 26 pm_imix) Instructions completed
+event:0X1A1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_imix) Processor cycles
+event:0X1A2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP26 : (Group 26 pm_imix) L1 D cache load misses
+event:0X1A3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP26 : (Group 26 pm_imix) Branches issued
+event:0X1A4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_imix) Processor cycles
+event:0X1A5 counters:5 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP26 : (Group 26 pm_imix) LSU0 busy
+event:0X1A6 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP26 : (Group 26 pm_imix) L1 D cache store references
+event:0X1A7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP26 : (Group 26 pm_imix) L1 D cache load references
+
+#Group 27 pm_branch, SLB and branch misspredict analysis
+event:0X1B0 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP27 : (Group 27 pm_branch) Run cycles
+event:0X1B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP27 : (Group 27 pm_branch) Data SLB misses
+event:0X1B2 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP27 : (Group 27 pm_branch) Branches issued
+event:0X1B3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP27 : (Group 27 pm_branch) Branch mispredictions due to CR bit setting
+event:0X1B4 counters:4 um:zero minimum:1000 name:PM_ISLB_MISS_GRP27 : (Group 27 pm_branch) Instruction SLB misses
+event:0X1B5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP27 : (Group 27 pm_branch) Processor cycles
+event:0X1B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP27 : (Group 27 pm_branch) Instructions completed
+event:0X1B7 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP27 : (Group 27 pm_branch) Branch mispredictions due to target address
+
+#Group 28 pm_data, data source and LMQ
+event:0X1C0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP28 : (Group 28 pm_data) Data loaded from L2
+event:0X1C1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
+event:0X1C2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP28 : (Group 28 pm_data) Data loaded from memory
+event:0X1C3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_data) Processor cycles
+event:0X1C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
+event:0X1C5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_data) Processor cycles
+event:0X1C6 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP28 : (Group 28 pm_data) LMQ slot 0 allocated
+event:0X1C7 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP28 : (Group 28 pm_data) LMQ slot 0 valid
+
+#Group 29 pm_tlb, TLB and LRQ plus data prefetch
+event:0X1D0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP29 : (Group 29 pm_tlb) Data TLB misses
+event:0X1D1 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP29 : (Group 29 pm_tlb) Instruction TLB misses
+event:0X1D2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP29 : (Group 29 pm_tlb) Instructions completed
+event:0X1D3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP29 : (Group 29 pm_tlb) Processor cycles
+event:0X1D4 counters:4 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP29 : (Group 29 pm_tlb) LRQ slot 0 allocated
+event:0X1D5 counters:5 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP29 : (Group 29 pm_tlb) LRQ slot 0 valid
+event:0X1D6 counters:6 um:zero minimum:1000 name:PM_L1_PREF_GRP29 : (Group 29 pm_tlb) L1 cache data prefetches
+event:0X1D7 counters:7 um:zero minimum:1000 name:PM_L2_PREF_GRP29 : (Group 29 pm_tlb) L2 cache prefetches
+
+#Group 30 pm_isource, inst source and tablewalk
+event:0X1E0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP30 : (Group 30 pm_isource) Instructions fetched from L2
+event:0X1E1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP30 : (Group 30 pm_isource) Instruction fetched from memory
+event:0X1E2 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP30 : (Group 30 pm_isource) Hypervisor Cycles
+event:0X1E3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP30 : (Group 30 pm_isource) Instructions completed
+event:0X1E4 counters:4 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP30 : (Group 30 pm_isource) Cycles doing data tablewalks
+event:0X1E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP30 : (Group 30 pm_isource) Processor cycles
+event:0X1E6 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP30 : (Group 30 pm_isource) Group completed
+event:0X1E7 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP30 : (Group 30 pm_isource) L1 D cache entries invalidated from L2
+
+#Group 31 pm_sync, Sync and SRQ
+event:0X1F0 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP31 : (Group 31 pm_sync) SRQ slot 0 allocated
+event:0X1F1 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP31 : (Group 31 pm_sync) SRQ slot 0 valid
+event:0X1F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP31 : (Group 31 pm_sync) L1 D cache load misses
+event:0X1F3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP31 : (Group 31 pm_sync) SRQ sync duration
+event:0X1F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_sync) Instructions completed
+event:0X1F5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_sync) Instructions completed
+event:0X1F6 counters:6 um:zero minimum:10000 name:PM_CYC_GRP31 : (Group 31 pm_sync) Processor cycles
+event:0X1F7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP31 : (Group 31 pm_sync) L1 D cache load references
+
+#Group 32 pm_ierat, IERAT
+event:0X200 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP32 : (Group 32 pm_ierat) Instruction fetched from L1
+event:0X201 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
+event:0X202 counters:2 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP32 : (Group 32 pm_ierat) Translation written to ierat
+event:0X203 counters:3 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
+event:0X204 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
+event:0X205 counters:5 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
+event:0X206 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
+event:0X207 counters:7 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
+
+#Group 33 pm_derat, DERAT
+event:0X210 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP33 : (Group 33 pm_derat) Cycles GCT empty
+event:0X211 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP33 : (Group 33 pm_derat) Group dispatch valid
+event:0X212 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP33 : (Group 33 pm_derat) L1 reload data source valid
+event:0X213 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP33 : (Group 33 pm_derat) Instructions completed
+event:0X214 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP33 : (Group 33 pm_derat) Instructions dispatched
+event:0X215 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP33 : (Group 33 pm_derat) DERAT misses
+event:0X216 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP33 : (Group 33 pm_derat) L1 D cache store references
+event:0X217 counters:7 um:zero minimum:10000 name:PM_CYC_GRP33 : (Group 33 pm_derat) Processor cycles
+
+#Group 34 pm_mark1, Information on marked instructions
+event:0X220 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP34 : (Group 34 pm_mark1) Marked L1 D cache load misses
+event:0X221 counters:1 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP34 : (Group 34 pm_mark1) Threshold timeout
+event:0X222 counters:2 um:zero minimum:10000 name:PM_CYC_GRP34 : (Group 34 pm_mark1) Processor cycles
+event:0X223 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP34 : (Group 34 pm_mark1) Marked group completed
+event:0X224 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP34 : (Group 34 pm_mark1) Group marked in IDU
+event:0X225 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP34 : (Group 34 pm_mark1) Marked group issued
+event:0X226 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP34 : (Group 34 pm_mark1) Marked instruction finished
+event:0X227 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP34 : (Group 34 pm_mark1) Instructions completed
+
+#Group 35 pm_mark2, Marked Instructions Processing Flow
+event:0X230 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP35 : (Group 35 pm_mark2) Marked group dispatched
+event:0X231 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction BRU processing finished
+event:0X232 counters:2 um:zero minimum:10000 name:PM_CYC_GRP35 : (Group 35 pm_mark2) Processor cycles
+event:0X233 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction CRU processing finished
+event:0X234 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP35 : (Group 35 pm_mark2) Group marked in IDU
+event:0X235 counters:5 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction FXU processing finished
+event:0X236 counters:6 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction FPU processing finished
+event:0X237 counters:7 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction LSU processing finished
+
+#Group 36 pm_mark3, Marked Stores Processing Flow
+event:0X240 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP36 : (Group 36 pm_mark3) Marked store instruction completed
+event:0X241 counters:1 um:zero minimum:10000 name:PM_CYC_GRP36 : (Group 36 pm_mark3) Processor cycles
+event:0X242 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP36 : (Group 36 pm_mark3) Marked store completed with intervention
+event:0X243 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP36 : (Group 36 pm_mark3) Marked group completed
+event:0X244 counters:4 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP36 : (Group 36 pm_mark3) Marked group completion timeout
+event:0X245 counters:5 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP36 : (Group 36 pm_mark3) Marked store sent to GPS
+event:0X246 counters:6 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP36 : (Group 36 pm_mark3) Marked instruction valid in SRQ
+event:0X247 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP36 : (Group 36 pm_mark3) Instructions completed
+
+#Group 37 pm_lsu_mark1, Load Store Unit Marked Events
+event:0X250 counters:0 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP37 : (Group 37 pm_lsu_mark1) Marked L1 D cache store misses
+event:0X251 counters:1 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP37 : (Group 37 pm_lsu_mark1) Marked IMR reloaded
+event:0X252 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_UST_GRP37 : (Group 37 pm_lsu_mark1) LSU0 marked unaligned store flushes
+event:0X253 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_UST_GRP37 : (Group 37 pm_lsu_mark1) LSU1 marked unaligned store flushes
+event:0X254 counters:4 um:zero minimum:10000 name:PM_CYC_GRP37 : (Group 37 pm_lsu_mark1) Processor cycles
+event:0X255 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP37 : (Group 37 pm_lsu_mark1) Instructions completed
+event:0X256 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_mark1) LSU0 marked unaligned load flushes
+event:0X257 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_mark1) LSU1 marked unaligned load flushes
+
+#Group 38 pm_lsu_mark2, Load Store Unit Marked Events
+event:0X260 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU0_GRP38 : (Group 38 pm_lsu_mark2) LSU0 L1 D cache load misses
+event:0X261 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU1_GRP38 : (Group 38 pm_lsu_mark2) LSU1 L1 D cache load misses
+event:0X262 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_LRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU0 marked LRQ flushes
+event:0X263 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_LRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU1 marked LRQ flushes
+event:0X264 counters:4 um:zero minimum:10000 name:PM_CYC_GRP38 : (Group 38 pm_lsu_mark2) Processor cycles
+event:0X265 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP38 : (Group 38 pm_lsu_mark2) Instructions completed
+event:0X266 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_SRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU0 marked SRQ flushes
+event:0X267 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_SRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU1 marked SRQ flushes
+
+#Group 39 pm_fxu1, Fixed Point events by unit
+event:0X270 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_fxu1) Instructions completed
+event:0X271 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_fxu1) Instructions completed
+event:0X272 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP39 : (Group 39 pm_fxu1) FXU produced a result
+event:0X273 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP39 : (Group 39 pm_fxu1) FXU1 busy FXU0 idle
+event:0X274 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP39 : (Group 39 pm_fxu1) FXU idle
+event:0X275 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP39 : (Group 39 pm_fxu1) FXU busy
+event:0X276 counters:6 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP39 : (Group 39 pm_fxu1) FXU0 busy FXU1 idle
+event:0X277 counters:7 um:zero minimum:10000 name:PM_CYC_GRP39 : (Group 39 pm_fxu1) Processor cycles
+
+#Group 40 pm_fxu2, Fixed Point events by unit
+event:0X280 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP40 : (Group 40 pm_fxu2) Instructions completed
+event:0X281 counters:1 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_fxu2) Processor cycles
+event:0X282 counters:2 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP40 : (Group 40 pm_fxu2) Cycles FXU1/LS1 queue full
+event:0X283 counters:3 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP40 : (Group 40 pm_fxu2) Cycles FXU0/LS0 queue full
+event:0X284 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP40 : (Group 40 pm_fxu2) FXU idle
+event:0X285 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP40 : (Group 40 pm_fxu2) FXU busy
+event:0X286 counters:6 um:zero minimum:1000 name:PM_FXU0_FIN_GRP40 : (Group 40 pm_fxu2) FXU0 produced a result
+event:0X287 counters:7 um:zero minimum:1000 name:PM_FXU1_FIN_GRP40 : (Group 40 pm_fxu2) FXU1 produced a result
+
+#Group 41 pm_ifu, pm_ifu
+event:0X290 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP41 : (Group 41 pm_ifu) Instruction fetched from L1
+event:0X291 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP41 : (Group 41 pm_ifu) Instruction fetched from memory
+event:0X292 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP41 : (Group 41 pm_ifu) Instructions fetched from prefetch
+event:0X293 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP41 : (Group 41 pm_ifu) No instructions fetched
+event:0X294 counters:4 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP41 : (Group 41 pm_ifu) Cycles at least 1 instruction fetched
+event:0X295 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP41 : (Group 41 pm_ifu) Instruction fetched from L2.5 modified
+event:0X296 counters:6 um:zero minimum:10000 name:PM_CYC_GRP41 : (Group 41 pm_ifu) Processor cycles
+event:0X297 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP41 : (Group 41 pm_ifu) Instructions completed
+
+#Group 42 pm_cpi_stack1, CPI stack analysis
+event:0X2A0 counters:0 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP42 : (Group 42 pm_cpi_stack1) LSU0 busy
+event:0X2A1 counters:1 um:zero minimum:1000 name:PM_LSU1_BUSY_GRP42 : (Group 42 pm_cpi_stack1) LSU1 busy
+event:0X2A2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP42 : (Group 42 pm_cpi_stack1) Flush initiated by LSU
+event:0X2A3 counters:3 um:zero minimum:1000 name:PM_FLUSH_LSU_BR_MPRED_GRP42 : (Group 42 pm_cpi_stack1) Flush caused by LSU or branch mispredict
+event:0X2A4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP42 : (Group 42 pm_cpi_stack1) Completion stall caused by LSU instruction
+event:0X2A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP42 : (Group 42 pm_cpi_stack1) Instructions completed
+event:0X2A6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP42 : (Group 42 pm_cpi_stack1) Completion stall caused by ERAT miss
+event:0X2A7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP42 : (Group 42 pm_cpi_stack1) Processor cycles
+
+#Group 43 pm_cpi_stack2, CPI stack analysis
+event:0X2B0 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_OTHER_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by other reason
+event:0X2B1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP43 : (Group 43 pm_cpi_stack2) Instructions completed
+event:0X2B2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP43 : (Group 43 pm_cpi_stack2) L1 D cache load misses
+event:0X2B3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP43 : (Group 43 pm_cpi_stack2) Processor cycles
+event:0X2B4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by D cache miss
+event:0X2B5 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP43 : (Group 43 pm_cpi_stack2) DERAT misses
+event:0X2B6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by reject
+event:0X2B7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP43 : (Group 43 pm_cpi_stack2) L1 D cache load references
+
+#Group 44 pm_cpi_stack3, CPI stack analysis
+event:0X2C0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP44 : (Group 44 pm_cpi_stack3) Instructions completed
+event:0X2C1 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_SRQ_FULL_GRP44 : (Group 44 pm_cpi_stack3) GCT empty caused by SRQ full
+event:0X2C2 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP44 : (Group 44 pm_cpi_stack3) FXU produced a result
+event:0X2C3 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP44 : (Group 44 pm_cpi_stack3) FPU produced a result
+event:0X2C4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP44 : (Group 44 pm_cpi_stack3) Completion stall caused by FXU instruction
+event:0X2C5 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP44 : (Group 44 pm_cpi_stack3) FXU busy
+event:0X2C6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP44 : (Group 44 pm_cpi_stack3) Completion stall caused by DIV instruction
+event:0X2C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP44 : (Group 44 pm_cpi_stack3) Processor cycles
+
+#Group 45 pm_cpi_stack4, CPI stack analysis
+event:0X2D0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FDIV instruction
+event:0X2D1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP45 : (Group 45 pm_cpi_stack4) FPU executed multiply-add instruction
+event:0X2D2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_cpi_stack4) Instructions completed
+event:0X2D3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_cpi_stack4) Instructions completed
+event:0X2D4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_FDIV_GRP45 : (Group 45 pm_cpi_stack4) Completion stall caused by FDIV or FQRT instruction
+event:0X2D5 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FSQRT instruction
+event:0X2D6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_FPU_GRP45 : (Group 45 pm_cpi_stack4) Completion stall caused by FPU instruction
+event:0X2D7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP45 : (Group 45 pm_cpi_stack4) Processor cycles
+
+#Group 46 pm_cpi_stack5, CPI stack analysis
+event:0X2E0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles GCT empty
+event:0X2E1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP46 : (Group 46 pm_cpi_stack5) Instructions completed
+event:0X2E2 counters:2 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP46 : (Group 46 pm_cpi_stack5) Flush caused by branch mispredict
+event:0X2E3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP46 : (Group 46 pm_cpi_stack5) Branch mispredictions due to target address
+event:0X2E4 counters:4 um:zero minimum:1000 name:PM_GCT_EMPTY_IC_MISS_GRP46 : (Group 46 pm_cpi_stack5) GCT empty due to I cache miss
+event:0X2E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP46 : (Group 46 pm_cpi_stack5) Processor cycles
+event:0X2E6 counters:6 um:zero minimum:1000 name:PM_GCT_EMPTY_BR_MPRED_GRP46 : (Group 46 pm_cpi_stack5) GCT empty due to branch mispredict
+event:0X2E7 counters:7 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles writing to instruction L1
+
+#Group 47 pm_data2, data source and LMQ
+event:0X2F0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 shared
+event:0X2F1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
+event:0X2F2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 modified
+event:0X2F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
+event:0X2F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
+event:0X2F5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
+event:0X2F6 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP47 : (Group 47 pm_data2) LMQ slot 0 allocated
+event:0X2F7 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP47 : (Group 47 pm_data2) LMQ slot 0 valid
+
+#Group 48 pm_fetch_branch, Instruction fetch and branch events
+event:0X300 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP48 : (Group 48 pm_fetch_branch) Instructions fetched from L2
+event:0X301 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP48 : (Group 48 pm_fetch_branch) Instruction fetched from memory
+event:0X302 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP48 : (Group 48 pm_fetch_branch) Instructions fetched from prefetch
+event:0X303 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP48 : (Group 48 pm_fetch_branch) Branches issued
+event:0X304 counters:4 um:zero minimum:10000 name:PM_CYC_GRP48 : (Group 48 pm_fetch_branch) Processor cycles
+event:0X305 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP48 : (Group 48 pm_fetch_branch) Instructions completed
+event:0X306 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP48 : (Group 48 pm_fetch_branch) Branch mispredictions due to CR bit setting
+event:0X307 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP48 : (Group 48 pm_fetch_branch) Branch mispredictions due to target address
+
+#Group 49 pm_l1l2_miss, L1 and L2 miss events
+event:0X310 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from L2
+event:0X311 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_l1l2_miss) Instructions completed
+event:0X312 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from memory
+event:0X313 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP49 : (Group 49 pm_l1l2_miss) LSU0 L1 D cache load misses
+event:0X314 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP49 : (Group 49 pm_l1l2_miss) One or more PPC instruction completed
+event:0X315 counters:5 um:zero minimum:10000 name:PM_CYC_GRP49 : (Group 49 pm_l1l2_miss) Processor cycles
+event:0X316 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP49 : (Group 49 pm_l1l2_miss) LSU1 L1 D cache load misses
+event:0X317 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP49 : (Group 49 pm_l1l2_miss) L1 D cache load references
diff --git a/events/ppc64/970/unit_masks b/events/ppc64/970/unit_masks
new file mode 100644
index 0000000..3aabdca
--- /dev/null
+++ b/events/ppc64/970/unit_masks
@@ -0,0 +1,4 @@
+# ppc64 970 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/970MP/event_mappings b/events/ppc64/970MP/event_mappings
new file mode 100644
index 0000000..b8d8113
--- /dev/null
+++ b/events/ppc64/970MP/event_mappings
@@ -0,0 +1,519 @@
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2007.
+# Contributed by Dave Nomura <dcnltc@us.ibm.com>.
+#
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X0400C51F mmcr1:0X000000000A46F18C mmcra:0X00002001
+
+#Group 1 pm_slice0, Time Slice 0
+event:0X0010 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0011 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0012 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0013 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0014 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0015 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0016 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+event:0X0017 mmcr0:0X0000051F mmcr1:0X000000000A46F18C mmcra:0X00002000
+
+#Group 2 pm_eprof, Group for use with eprof
+event:0X0020 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0021 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0022 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0023 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0024 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0025 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0026 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0027 mmcr0:0X00000F1F mmcr1:0X4003001005F09000 mmcra:0X00002000
+
+#Group 3 pm_basic, Basic performance indicators
+event:0X0030 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0031 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0032 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0033 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0034 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0035 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0036 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+event:0X0037 mmcr0:0X0000091F mmcr1:0X4003001005F09000 mmcra:0X00002000
+
+#Group 4 pm_lsu, Information on the Load Store Unit
+event:0X0040 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0041 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0042 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0043 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0044 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0045 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0046 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+event:0X0047 mmcr0:0X00000001 mmcr1:0X000F00007A400000 mmcra:0X00002000
+
+#Group 5 pm_fpu1, Floating Point events
+event:0X0050 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0051 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0052 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0053 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0054 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0055 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0056 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+event:0X0057 mmcr0:0X00000001 mmcr1:0X00000000001E0480 mmcra:0X00002000
+
+#Group 6 pm_fpu2, Floating Point events
+event:0X0060 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0061 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0062 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0063 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0064 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0065 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0066 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+event:0X0067 mmcr0:0X00000001 mmcr1:0X000020E87A400000 mmcra:0X00002000
+
+#Group 7 pm_isu_rename, ISU Rename Pool Events
+event:0X0070 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0071 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0072 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0073 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0074 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0075 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0076 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+event:0X0077 mmcr0:0X00001229 mmcr1:0X400000218E6D84BC mmcra:0X00002000
+
+#Group 8 pm_isu_queues1, ISU Rename Pool Events
+event:0X0080 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0081 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0082 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0083 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0084 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0085 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0086 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+event:0X0087 mmcr0:0X0000132F mmcr1:0X40000000851E994C mmcra:0X00002000
+
+#Group 9 pm_isu_flow, ISU Instruction Flow Events
+event:0X0090 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0091 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0092 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0093 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0094 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0095 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0096 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+event:0X0097 mmcr0:0X0000181F mmcr1:0X400000B3D7B7C4BC mmcra:0X00002000
+
+#Group 10 pm_isu_work, ISU Indicators of Work Blockage
+event:0X00A0 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A1 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A2 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A3 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A4 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A5 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A6 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+event:0X00A7 mmcr0:0X00000403 mmcr1:0X400000050FDE9D88 mmcra:0X00002000
+
+#Group 11 pm_fpu3, Floating Point events by unit
+event:0X00B0 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B1 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B2 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B3 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B4 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B5 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B6 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+event:0X00B7 mmcr0:0X00001029 mmcr1:0X000000008D6354BC mmcra:0X00002000
+
+#Group 12 pm_fpu4, Floating Point events by unit
+event:0X00C0 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C1 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C2 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C3 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C4 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C5 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C6 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+event:0X00C7 mmcr0:0X0000122D mmcr1:0X000000009DE774BC mmcra:0X00002000
+
+#Group 13 pm_fpu5, Floating Point events by unit
+event:0X00D0 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D1 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D2 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D3 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D4 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D5 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D6 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+event:0X00D7 mmcr0:0X00001839 mmcr1:0X000000C0851E9958 mmcra:0X00002000
+
+#Group 14 pm_fpu7, Floating Point events by unit
+event:0X00E0 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E1 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E2 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E3 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E4 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E5 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E6 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+event:0X00E7 mmcr0:0X0000193B mmcr1:0X000000C89DDE97E0 mmcra:0X00002000
+
+#Group 15 pm_lsu_flush, LSU Flush Events
+event:0X00F0 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F1 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F2 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F3 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F4 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F5 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F6 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+event:0X00F7 mmcr0:0X0000122D mmcr1:0X000C00007BE774BC mmcra:0X00002000
+
+#Group 16 pm_lsu_load1, LSU Load Events
+event:0X0100 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0101 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0102 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0103 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0104 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0105 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0106 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+event:0X0107 mmcr0:0X00001029 mmcr1:0X000F0000851E9958 mmcra:0X00002000
+
+#Group 17 pm_lsu_store1, LSU Store Events
+event:0X0110 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0111 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0112 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0113 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0114 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0115 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0116 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+event:0X0117 mmcr0:0X0000112B mmcr1:0X000F00008D5E99DC mmcra:0X00002000
+
+#Group 18 pm_lsu_store2, LSU Store Events
+event:0X0120 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0121 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0122 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0123 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0124 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0125 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0126 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+event:0X0127 mmcr0:0X00001839 mmcr1:0X0003C0D08D76F4BC mmcra:0X00002000
+
+#Group 19 pm_lsu7, Information on the Load Store Unit
+event:0X0130 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0131 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0132 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0133 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0134 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0135 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0136 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+event:0X0137 mmcr0:0X0000122D mmcr1:0X000830047BD2FE3C mmcra:0X00002000
+
+#Group 20 pm_misc, Misc Events for testing
+event:0X0140 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0141 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0142 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0143 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0144 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0145 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0146 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+event:0X0147 mmcr0:0X00000405 mmcr1:0X0000000023C69194 mmcra:0X00002000
+
+#Group 21 pm_pe_bench1, PE Benchmarker group for FP analysis
+event:0X0150 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0151 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0152 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0153 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0154 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0155 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0156 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+event:0X0157 mmcr0:0X00000001 mmcr1:0X10001002001E0480 mmcra:0X00002000
+
+#Group 22 pm_pe_bench4, PE Benchmarker group for L1 and TLB
+event:0X0160 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0161 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0162 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0163 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0164 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0165 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0166 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0167 mmcr0:0X00001421 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+
+#Group 23 pm_hpmcount1, Hpmcount group for L1 and TLB behavior
+event:0X0170 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0171 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0172 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0173 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0174 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0175 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0176 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+event:0X0177 mmcr0:0X00001405 mmcr1:0X000B000004DE9000 mmcra:0X00002000
+
+#Group 24 pm_hpmcount2, Hpmcount group for computation
+event:0X0180 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0181 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0182 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0183 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0184 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0185 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0186 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+event:0X0187 mmcr0:0X00000001 mmcr1:0X000020289DDE0480 mmcra:0X00002000
+
+#Group 25 pm_l1andbr, L1 misses and branch misspredict analysis
+event:0X0190 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0191 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0192 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0193 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0194 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0195 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0196 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+event:0X0197 mmcr0:0X0000091F mmcr1:0X8003C01D0676FD6C mmcra:0X00002000
+
+#Group 26 pm_imix, Instruction mix: loads, stores and branches
+event:0X01A0 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A1 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A2 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A3 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A4 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A5 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A6 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+event:0X01A7 mmcr0:0X0000091F mmcr1:0X8003C021065FB000 mmcra:0X00002000
+
+#Group 27 pm_branch, SLB and branch misspredict analysis
+event:0X01B0 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B1 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B2 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B3 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B4 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B5 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B6 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+event:0X01B7 mmcr0:0X0000052B mmcr1:0X8008000BCEA2F4EC mmcra:0X00002000
+
+#Group 28 pm_data, data source and LMQ
+event:0X01C0 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C1 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C2 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C3 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C4 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C5 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C6 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+event:0X01C7 mmcr0:0X0000070F mmcr1:0X0000300C4BD2FF74 mmcra:0X00002000
+
+#Group 29 pm_tlb, TLB and LRQ plus data prefetch
+event:0X01D0 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D1 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D2 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D3 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D4 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D5 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D6 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+event:0X01D7 mmcr0:0X00001421 mmcr1:0X0008E03C4BFDACEC mmcra:0X00002000
+
+#Group 30 pm_isource, inst source and tablewalk
+event:0X01E0 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E1 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E2 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E3 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E4 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E5 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E6 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+event:0X01E7 mmcr0:0X0000060D mmcr1:0X800B00C0226EF1DC mmcra:0X00002000
+
+#Group 31 pm_sync, Sync and SRQ
+event:0X01F0 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F1 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F2 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F3 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F4 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F5 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F6 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+event:0X01F7 mmcr0:0X00001D33 mmcr1:0X0003E0C107529780 mmcra:0X00002000
+
+#Group 32 pm_ierat, IERAT
+event:0X0200 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0201 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0202 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0203 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0204 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0205 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0206 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+event:0X0207 mmcr0:0X00000D13 mmcr1:0X80000082C3D2F4BC mmcra:0X00002000
+
+#Group 33 pm_derat, DERAT
+event:0X0210 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0211 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0212 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0213 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0214 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0215 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0216 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+event:0X0217 mmcr0:0X00000437 mmcr1:0X100B7052E274003C mmcra:0X00002000
+
+#Group 34 pm_mark1, Information on marked instructions
+event:0X0220 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0221 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0222 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0223 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0224 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0225 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0226 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+event:0X0227 mmcr0:0X00000007 mmcr1:0X00008080790852A4 mmcra:0X00002001
+
+#Group 35 pm_mark2, Marked Instructions Processing Flow
+event:0X0230 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0231 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0232 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0233 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0234 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0235 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0236 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+event:0X0237 mmcr0:0X0000020B mmcr1:0X0000000079484210 mmcra:0X00002001
+
+#Group 36 pm_mark3, Marked Stores Processing Flow
+event:0X0240 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0241 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0242 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0243 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0244 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0245 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0246 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+event:0X0247 mmcr0:0X0000031F mmcr1:0X00203004190A3F24 mmcra:0X00002001
+
+#Group 37 pm_lsu_mark1, Load Store Unit Marked Events
+event:0X0250 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0251 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0252 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0253 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0254 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0255 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0256 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+event:0X0257 mmcr0:0X00001B35 mmcr1:0X000280C08D5E9850 mmcra:0X00002001
+
+#Group 38 pm_lsu_mark2, Load Store Unit Marked Events
+event:0X0260 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0261 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0262 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0263 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0264 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0265 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0266 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+event:0X0267 mmcr0:0X00001839 mmcr1:0X000280C0959E99DC mmcra:0X00002001
+
+#Group 39 pm_fxu1, Fixed Point events by unit
+event:0X0270 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0271 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0272 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0273 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0274 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0275 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0276 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+event:0X0277 mmcr0:0X00000913 mmcr1:0X100010020084213C mmcra:0X00002000
+
+#Group 40 pm_fxu2, Fixed Point events by unit
+event:0X0280 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0281 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0282 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0283 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0284 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0285 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0286 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+event:0X0287 mmcr0:0X0000091F mmcr1:0X4000000CA4042D78 mmcra:0X00002000
+
+#Group 41 pm_ifu, pm_ifu
+event:0X0290 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0291 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0292 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0293 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0294 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0295 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0296 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+event:0X0297 mmcr0:0X00000D0D mmcr1:0X800000F06B7867A4 mmcra:0X00002000
+
+#Group 42 pm_cpi_stack1, CPI stack analysis
+event:0X02A0 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A1 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A2 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A3 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A4 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A5 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A6 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+event:0X02A7 mmcr0:0X00001B3F mmcr1:0X4000C0C0ADD6963D mmcra:0X00002000
+
+#Group 43 pm_cpi_stack2, CPI stack analysis
+event:0X02B0 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B1 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B2 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B3 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B4 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B5 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B6 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+event:0X02B7 mmcr0:0X00000B13 mmcr1:0X000B000003D60583 mmcra:0X00002000
+
+#Group 44 pm_cpi_stack3, CPI stack analysis
+event:0X02C0 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C1 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C2 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C3 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C4 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C5 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C6 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+event:0X02C7 mmcr0:0X00000917 mmcr1:0X10001002001625BE mmcra:0X00002000
+
+#Group 45 pm_cpi_stack4, CPI stack analysis
+event:0X02D0 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D1 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D2 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D3 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D4 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D5 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D6 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+event:0X02D7 mmcr0:0X00000001 mmcr1:0X00000000485805BD mmcra:0X00002000
+
+#Group 46 pm_cpi_stack5, CPI stack analysis
+event:0X02E0 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E1 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E2 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E3 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E4 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E5 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E6 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+event:0X02E7 mmcr0:0X00000413 mmcr1:0X90014009B6D8F672 mmcra:0X00002000
+
+#Group 47 pm_data2, data source and LMQ
+event:0X02F0 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F1 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F2 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F3 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F4 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F5 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F6 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+event:0X02F7 mmcr0:0X00000913 mmcr1:0X0000300C7BCE7F74 mmcra:0X00002000
+
+#Group 48 pm_fetch_branch, Instruction fetch and branch events
+event:0X0300 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0301 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0302 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0303 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0304 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0305 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0306 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+event:0X0307 mmcr0:0X0000060D mmcr1:0X800000CD6E5E9D6C mmcra:0X00002000
+
+#Group 49 pm_l1l2_miss, L1 and L2 miss events
+event:0X0310 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0311 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0312 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0313 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0314 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0315 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0316 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+event:0X0317 mmcr0:0X0000070F mmcr1:0X000330004C86FB00 mmcra:0X00002000
+
+#Group 50 pm_data_from, Data From L2 instructions
+event:0X0320 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0321 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0322 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0323 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0324 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0325 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0326 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+event:0X0327 mmcr0:0X0000070F mmcr1:0X000330004BCE7B00 mmcra:0X00002000
+
+#Group 51 pm_mark_data_from, Marked Data From L2 instructions
+event:0X0330 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0331 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0332 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0333 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0334 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0335 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0336 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
+event:0X0337 mmcr0:0X0000070F mmcr1:0X002030084BCE72F0 mmcra:0X00002001
diff --git a/events/ppc64/970MP/events b/events/ppc64/970MP/events
new file mode 100644
index 0000000..a02130f
--- /dev/null
+++ b/events/ppc64/970MP/events
@@ -0,0 +1,530 @@
+#PPC64 PowerPC970MP events
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2007.
+# Contributed by Dave Nomura <dcnltc@us.ibm.com>.
+#
+#
+# Within each group the event names must be unique. Each event in a group is
+# assigned to a unique counter. The groups are from the groups defined in the
+# Performance Monitor Unit user guide for this processor.
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
+
+
+#Group 1 pm_slice0, Time Slice 0
+event:0X0010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
+event:0X0011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
+event:0X0012 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP1 : (Group 1 pm_slice0) Completion stopped
+event:0X0013 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_slice0) Instructions completed
+event:0X0014 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP1 : (Group 1 pm_slice0) One or more PPC instruction completed
+event:0X0015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
+event:0X0016 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP1 : (Group 1 pm_slice0) Group completed
+event:0X0017 counters:7 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP1 : (Group 1 pm_slice0) Group dispatch rejected
+
+#Group 2 pm_eprof, Group for use with eprof
+event:0X0020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
+event:0X0021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
+event:0X0022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
+event:0X0023 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP2 : (Group 2 pm_eprof) L1 D cache entries invalidated from L2
+event:0X0024 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP2 : (Group 2 pm_eprof) Instructions dispatched
+event:0X0025 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP2 : (Group 2 pm_eprof) Instructions completed
+event:0X0026 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache store references
+event:0X0027 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load references
+
+#Group 3 pm_basic, Basic performance indicators
+event:0X0030 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed
+event:0X0031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles
+event:0X0032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
+event:0X0033 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP3 : (Group 3 pm_basic) L1 D cache entries invalidated from L2
+event:0X0034 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_basic) Instructions dispatched
+event:0X0035 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed
+event:0X0036 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache store references
+event:0X0037 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache load references
+
+#Group 4 pm_lsu, Information on the Load Store Unit
+event:0X0040 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP4 : (Group 4 pm_lsu) LRQ unaligned load flushes
+event:0X0041 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP4 : (Group 4 pm_lsu) SRQ unaligned store flushes
+event:0X0042 counters:2 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_lsu) Processor cycles
+event:0X0043 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP4 : (Group 4 pm_lsu) Instructions completed
+event:0X0044 counters:4 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP4 : (Group 4 pm_lsu) SRQ flushes
+event:0X0045 counters:5 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP4 : (Group 4 pm_lsu) LRQ flushes
+event:0X0046 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP4 : (Group 4 pm_lsu) L1 D cache store references
+event:0X0047 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP4 : (Group 4 pm_lsu) L1 D cache load references
+
+#Group 5 pm_fpu1, Floating Point events
+event:0X0050 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP5 : (Group 5 pm_fpu1) FPU executed FDIV instruction
+event:0X0051 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP5 : (Group 5 pm_fpu1) FPU executed multiply-add instruction
+event:0X0052 counters:2 um:zero minimum:1000 name:PM_FPU_FEST_GRP5 : (Group 5 pm_fpu1) FPU executed FEST instruction
+event:0X0053 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP5 : (Group 5 pm_fpu1) FPU produced a result
+event:0X0054 counters:4 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_fpu1) Processor cycles
+event:0X0055 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP5 : (Group 5 pm_fpu1) FPU executed FSQRT instruction
+event:0X0056 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP5 : (Group 5 pm_fpu1) Instructions completed
+event:0X0057 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP5 : (Group 5 pm_fpu1) FPU executing FMOV or FEST instructions
+
+#Group 6 pm_fpu2, Floating Point events
+event:0X0060 counters:0 um:zero minimum:1000 name:PM_FPU_DENORM_GRP6 : (Group 6 pm_fpu2) FPU received denormalized data
+event:0X0061 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP6 : (Group 6 pm_fpu2) FPU stalled in pipe3
+event:0X0062 counters:2 um:zero minimum:10000 name:PM_CYC_GRP6 : (Group 6 pm_fpu2) Processor cycles
+event:0X0063 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP6 : (Group 6 pm_fpu2) Instructions completed
+event:0X0064 counters:4 um:zero minimum:1000 name:PM_FPU_ALL_GRP6 : (Group 6 pm_fpu2) FPU executed add, mult, sub, cmp or sel instruction
+event:0X0065 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP6 : (Group 6 pm_fpu2) FPU executed store instruction
+event:0X0066 counters:6 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP6 : (Group 6 pm_fpu2) FPU executed FRSP or FCONV instructions
+event:0X0067 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP6 : (Group 6 pm_fpu2) LSU executed Floating Point load instruction
+
+#Group 7 pm_isu_rename, ISU Rename Pool Events
+event:0X0070 counters:0 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles XER mapper full
+event:0X0071 counters:1 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles CR logical operation mapper full
+event:0X0072 counters:2 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles CR issue queue full
+event:0X0073 counters:3 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles group dispatch blocked by scoreboard
+event:0X0074 counters:4 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP7 : (Group 7 pm_isu_rename) Cycles LR/CTR mapper full
+event:0X0075 counters:5 um:zero minimum:1000 name:PM_INST_DISP_GRP7 : (Group 7 pm_isu_rename) Instructions dispatched
+event:0X0076 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP7 : (Group 7 pm_isu_rename) Instructions completed
+event:0X0077 counters:7 um:zero minimum:10000 name:PM_CYC_GRP7 : (Group 7 pm_isu_rename) Processor cycles
+
+#Group 8 pm_isu_queues1, ISU Rename Pool Events
+event:0X0080 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FPU0 issue queue full
+event:0X0081 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FPU1 issue queue full
+event:0X0082 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FXU0/LS0 queue full
+event:0X0083 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles FXU1/LS1 queue full
+event:0X0084 counters:4 um:zero minimum:10000 name:PM_CYC_GRP8 : (Group 8 pm_isu_queues1) Processor cycles
+event:0X0085 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP8 : (Group 8 pm_isu_queues1) Instructions completed
+event:0X0086 counters:6 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles LRQ full
+event:0X0087 counters:7 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP8 : (Group 8 pm_isu_queues1) Cycles SRQ full
+
+#Group 9 pm_isu_flow, ISU Instruction Flow Events
+event:0X0090 counters:0 um:zero minimum:1000 name:PM_INST_DISP_GRP9 : (Group 9 pm_isu_flow) Instructions dispatched
+event:0X0091 counters:1 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_isu_flow) Processor cycles
+event:0X0092 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP9 : (Group 9 pm_isu_flow) FXU0 produced a result
+event:0X0093 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP9 : (Group 9 pm_isu_flow) FXU1 produced a result
+event:0X0094 counters:4 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP9 : (Group 9 pm_isu_flow) Group dispatch valid
+event:0X0095 counters:5 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP9 : (Group 9 pm_isu_flow) Group dispatch rejected
+event:0X0096 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP9 : (Group 9 pm_isu_flow) Instructions completed
+event:0X0097 counters:7 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_isu_flow) Processor cycles
+
+#Group 10 pm_isu_work, ISU Indicators of Work Blockage
+event:0X00A0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP10 : (Group 10 pm_isu_work) Cycles GCT empty
+event:0X00A1 counters:1 um:zero minimum:1000 name:PM_WORK_HELD_GRP10 : (Group 10 pm_isu_work) Work held
+event:0X00A2 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP10 : (Group 10 pm_isu_work) Completion stopped
+event:0X00A3 counters:3 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off and external interrupt pending
+event:0X00A4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP10 : (Group 10 pm_isu_work) Processor cycles
+event:0X00A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP10 : (Group 10 pm_isu_work) Instructions completed
+event:0X00A6 counters:6 um:zero minimum:1000 name:PM_EE_OFF_GRP10 : (Group 10 pm_isu_work) Cycles MSR(EE) bit off
+event:0X00A7 counters:7 um:zero minimum:1000 name:PM_EXT_INT_GRP10 : (Group 10 pm_isu_work) External interrupts
+
+#Group 11 pm_fpu3, Floating Point events by unit
+event:0X00B0 counters:0 um:zero minimum:1000 name:PM_FPU0_FDIV_GRP11 : (Group 11 pm_fpu3) FPU0 executed FDIV instruction
+event:0X00B1 counters:1 um:zero minimum:1000 name:PM_FPU1_FDIV_GRP11 : (Group 11 pm_fpu3) FPU1 executed FDIV instruction
+event:0X00B2 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP11 : (Group 11 pm_fpu3) FPU0 executed FRSP or FCONV instructions
+event:0X00B3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP11 : (Group 11 pm_fpu3) FPU1 executed FRSP or FCONV instructions
+event:0X00B4 counters:4 um:zero minimum:1000 name:PM_FPU0_FMA_GRP11 : (Group 11 pm_fpu3) FPU0 executed multiply-add instruction
+event:0X00B5 counters:5 um:zero minimum:1000 name:PM_FPU1_FMA_GRP11 : (Group 11 pm_fpu3) FPU1 executed multiply-add instruction
+event:0X00B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP11 : (Group 11 pm_fpu3) Instructions completed
+event:0X00B7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP11 : (Group 11 pm_fpu3) Processor cycles
+
+#Group 12 pm_fpu4, Floating Point events by unit
+event:0X00C0 counters:0 um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU0 executed FSQRT instruction
+event:0X00C1 counters:1 um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP12 : (Group 12 pm_fpu4) FPU1 executed FSQRT instruction
+event:0X00C2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP12 : (Group 12 pm_fpu4) FPU0 produced a result
+event:0X00C3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP12 : (Group 12 pm_fpu4) FPU1 produced a result
+event:0X00C4 counters:4 um:zero minimum:1000 name:PM_FPU0_ALL_GRP12 : (Group 12 pm_fpu4) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X00C5 counters:5 um:zero minimum:1000 name:PM_FPU1_ALL_GRP12 : (Group 12 pm_fpu4) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X00C6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP12 : (Group 12 pm_fpu4) Instructions completed
+event:0X00C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP12 : (Group 12 pm_fpu4) Processor cycles
+
+#Group 13 pm_fpu5, Floating Point events by unit
+event:0X00D0 counters:0 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP13 : (Group 13 pm_fpu5) FPU0 received denormalized data
+event:0X00D1 counters:1 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP13 : (Group 13 pm_fpu5) FPU1 received denormalized data
+event:0X00D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FMOV_FEST_GRP13 : (Group 13 pm_fpu5) FPU0 executed FMOV or FEST instructions
+event:0X00D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FMOV_FEST_GRP13 : (Group 13 pm_fpu5) FPU1 executing FMOV or FEST instructions
+event:0X00D4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP13 : (Group 13 pm_fpu5) Processor cycles
+event:0X00D5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP13 : (Group 13 pm_fpu5) Instructions completed
+event:0X00D6 counters:6 um:zero minimum:1000 name:PM_FPU0_FEST_GRP13 : (Group 13 pm_fpu5) FPU0 executed FEST instruction
+event:0X00D7 counters:7 um:zero minimum:1000 name:PM_FPU1_FEST_GRP13 : (Group 13 pm_fpu5) FPU1 executed FEST instruction
+
+#Group 14 pm_fpu7, Floating Point events by unit
+event:0X00E0 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP14 : (Group 14 pm_fpu7) FPU0 stalled in pipe3
+event:0X00E1 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP14 : (Group 14 pm_fpu7) FPU1 stalled in pipe3
+event:0X00E2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP14 : (Group 14 pm_fpu7) FPU0 produced a result
+event:0X00E3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP14 : (Group 14 pm_fpu7) FPU1 produced a result
+event:0X00E4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_fpu7) Processor cycles
+event:0X00E5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP14 : (Group 14 pm_fpu7) Instructions completed
+event:0X00E6 counters:6 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_fpu7) Processor cycles
+event:0X00E7 counters:7 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP14 : (Group 14 pm_fpu7) FPU0 executed FPSCR instruction
+
+#Group 15 pm_lsu_flush, LSU Flush Events
+event:0X00F0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP15 : (Group 15 pm_lsu_flush) LSU0 LRQ flushes
+event:0X00F1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP15 : (Group 15 pm_lsu_flush) LSU1 LRQ flushes
+event:0X00F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
+event:0X00F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
+event:0X00F4 counters:4 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_flush) LSU0 SRQ flushes
+event:0X00F5 counters:5 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_flush) LSU1 SRQ flushes
+event:0X00F6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP15 : (Group 15 pm_lsu_flush) Instructions completed
+event:0X00F7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_lsu_flush) Processor cycles
+
+#Group 16 pm_lsu_load1, LSU Load Events
+event:0X0100 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP16 : (Group 16 pm_lsu_load1) LSU0 unaligned load flushes
+event:0X0101 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP16 : (Group 16 pm_lsu_load1) LSU1 unaligned load flushes
+event:0X0102 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load references
+event:0X0103 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load references
+event:0X0104 counters:4 um:zero minimum:10000 name:PM_CYC_GRP16 : (Group 16 pm_lsu_load1) Processor cycles
+event:0X0105 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP16 : (Group 16 pm_lsu_load1) Instructions completed
+event:0X0106 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP16 : (Group 16 pm_lsu_load1) LSU0 L1 D cache load misses
+event:0X0107 counters:7 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP16 : (Group 16 pm_lsu_load1) LSU1 L1 D cache load misses
+
+#Group 17 pm_lsu_store1, LSU Store Events
+event:0X0110 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP17 : (Group 17 pm_lsu_store1) LSU0 unaligned store flushes
+event:0X0111 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP17 : (Group 17 pm_lsu_store1) LSU1 unaligned store flushes
+event:0X0112 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP17 : (Group 17 pm_lsu_store1) LSU0 L1 D cache store references
+event:0X0113 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP17 : (Group 17 pm_lsu_store1) LSU1 L1 D cache store references
+event:0X0114 counters:4 um:zero minimum:10000 name:PM_CYC_GRP17 : (Group 17 pm_lsu_store1) Processor cycles
+event:0X0115 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP17 : (Group 17 pm_lsu_store1) Instructions completed
+event:0X0116 counters:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP17 : (Group 17 pm_lsu_store1) L1 D cache store misses
+event:0X0117 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP17 : (Group 17 pm_lsu_store1) L1 D cache entries invalidated from L2
+
+#Group 18 pm_lsu_store2, LSU Store Events
+event:0X0120 counters:0 um:zero minimum:1000 name:PM_LSU0_SRQ_STFWD_GRP18 : (Group 18 pm_lsu_store2) LSU0 SRQ store forwarded
+event:0X0121 counters:1 um:zero minimum:1000 name:PM_LSU1_SRQ_STFWD_GRP18 : (Group 18 pm_lsu_store2) LSU1 SRQ store forwarded
+event:0X0122 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP18 : (Group 18 pm_lsu_store2) LSU0 L1 D cache store references
+event:0X0123 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP18 : (Group 18 pm_lsu_store2) LSU1 L1 D cache store references
+event:0X0124 counters:4 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP18 : (Group 18 pm_lsu_store2) LSU0 busy
+event:0X0125 counters:5 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_lsu_store2) Processor cycles
+event:0X0126 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP18 : (Group 18 pm_lsu_store2) Instructions completed
+event:0X0127 counters:7 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_lsu_store2) Processor cycles
+
+#Group 19 pm_lsu7, Information on the Load Store Unit
+event:0X0130 counters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU0 DERAT misses
+event:0X0131 counters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP19 : (Group 19 pm_lsu7) LSU1 DERAT misses
+event:0X0132 counters:2 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
+event:0X0133 counters:3 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
+event:0X0134 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP19 : (Group 19 pm_lsu7) Instructions completed
+event:0X0135 counters:5 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
+event:0X0136 counters:6 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP19 : (Group 19 pm_lsu7) L1 reload data source valid
+event:0X0137 counters:7 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_lsu7) Processor cycles
+
+#Group 20 pm_misc, Misc Events for testing
+event:0X0140 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP20 : (Group 20 pm_misc) Cycles GCT empty
+event:0X0141 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP20 : (Group 20 pm_misc) Cycles LMQ and SRQ empty
+event:0X0142 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP20 : (Group 20 pm_misc) Hypervisor Cycles
+event:0X0143 counters:3 um:zero minimum:10000 name:PM_CYC_GRP20 : (Group 20 pm_misc) Processor cycles
+event:0X0144 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP20 : (Group 20 pm_misc) One or more PPC instruction completed
+event:0X0145 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP20 : (Group 20 pm_misc) Instructions completed
+event:0X0146 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP20 : (Group 20 pm_misc) Group completed
+event:0X0147 counters:7 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP20 : (Group 20 pm_misc) Time Base bit transition
+
+#Group 21 pm_pe_bench1, PE Benchmarker group for FP analysis
+event:0X0150 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP21 : (Group 21 pm_pe_bench1) FPU executed FDIV instruction
+event:0X0151 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP21 : (Group 21 pm_pe_bench1) FPU executed multiply-add instruction
+event:0X0152 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP21 : (Group 21 pm_pe_bench1) FXU produced a result
+event:0X0153 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP21 : (Group 21 pm_pe_bench1) FPU produced a result
+event:0X0154 counters:4 um:zero minimum:10000 name:PM_CYC_GRP21 : (Group 21 pm_pe_bench1) Processor cycles
+event:0X0155 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP21 : (Group 21 pm_pe_bench1) FPU executed FSQRT instruction
+event:0X0156 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP21 : (Group 21 pm_pe_bench1) Instructions completed
+event:0X0157 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP21 : (Group 21 pm_pe_bench1) FPU executing FMOV or FEST instructions
+
+#Group 22 pm_pe_bench4, PE Benchmarker group for L1 and TLB
+event:0X0160 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Data TLB misses
+event:0X0161 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_pe_bench4) Instruction TLB misses
+event:0X0162 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load misses
+event:0X0163 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache store misses
+event:0X0164 counters:4 um:zero minimum:10000 name:PM_CYC_GRP22 : (Group 22 pm_pe_bench4) Processor cycles
+event:0X0165 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP22 : (Group 22 pm_pe_bench4) Instructions completed
+event:0X0166 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache store references
+event:0X0167 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP22 : (Group 22 pm_pe_bench4) L1 D cache load references
+
+#Group 23 pm_hpmcount1, Hpmcount group for L1 and TLB behavior
+event:0X0170 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP23 : (Group 23 pm_hpmcount1) Data TLB misses
+event:0X0171 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP23 : (Group 23 pm_hpmcount1) Cycles LMQ and SRQ empty
+event:0X0172 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache load misses
+event:0X0173 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache store misses
+event:0X0174 counters:4 um:zero minimum:10000 name:PM_CYC_GRP23 : (Group 23 pm_hpmcount1) Processor cycles
+event:0X0175 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP23 : (Group 23 pm_hpmcount1) Instructions completed
+event:0X0176 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache store references
+event:0X0177 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP23 : (Group 23 pm_hpmcount1) L1 D cache load references
+
+#Group 24 pm_hpmcount2, Hpmcount group for computation
+event:0X0180 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP24 : (Group 24 pm_hpmcount2) FPU executed FDIV instruction
+event:0X0181 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP24 : (Group 24 pm_hpmcount2) FPU executed multiply-add instruction
+event:0X0182 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP24 : (Group 24 pm_hpmcount2) FPU0 produced a result
+event:0X0183 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP24 : (Group 24 pm_hpmcount2) FPU1 produced a result
+event:0X0184 counters:4 um:zero minimum:10000 name:PM_CYC_GRP24 : (Group 24 pm_hpmcount2) Processor cycles
+event:0X0185 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP24 : (Group 24 pm_hpmcount2) FPU executed store instruction
+event:0X0186 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP24 : (Group 24 pm_hpmcount2) Instructions completed
+event:0X0187 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP24 : (Group 24 pm_hpmcount2) LSU executed Floating Point load instruction
+
+#Group 25 pm_l1andbr, L1 misses and branch misspredict analysis
+event:0X0190 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP25 : (Group 25 pm_l1andbr) Instructions completed
+event:0X0191 counters:1 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_l1andbr) Processor cycles
+event:0X0192 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP25 : (Group 25 pm_l1andbr) L1 D cache load misses
+event:0X0193 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP25 : (Group 25 pm_l1andbr) Branches issued
+event:0X0194 counters:4 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP25 : (Group 25 pm_l1andbr) LSU0 busy
+event:0X0195 counters:5 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_l1andbr) Processor cycles
+event:0X0196 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP25 : (Group 25 pm_l1andbr) Branch mispredictions due to CR bit setting
+event:0X0197 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP25 : (Group 25 pm_l1andbr) Branch mispredictions due to target address
+
+#Group 26 pm_imix, Instruction mix: loads, stores and branches
+event:0X01A0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP26 : (Group 26 pm_imix) Instructions completed
+event:0X01A1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_imix) Processor cycles
+event:0X01A2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP26 : (Group 26 pm_imix) L1 D cache load misses
+event:0X01A3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP26 : (Group 26 pm_imix) Branches issued
+event:0X01A4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_imix) Processor cycles
+event:0X01A5 counters:5 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP26 : (Group 26 pm_imix) LSU0 busy
+event:0X01A6 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP26 : (Group 26 pm_imix) L1 D cache store references
+event:0X01A7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP26 : (Group 26 pm_imix) L1 D cache load references
+
+#Group 27 pm_branch, SLB and branch misspredict analysis
+event:0X01B0 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP27 : (Group 27 pm_branch) Run cycles
+event:0X01B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP27 : (Group 27 pm_branch) Data SLB misses
+event:0X01B2 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP27 : (Group 27 pm_branch) Branches issued
+event:0X01B3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP27 : (Group 27 pm_branch) Branch mispredictions due to CR bit setting
+event:0X01B4 counters:4 um:zero minimum:1000 name:PM_ISLB_MISS_GRP27 : (Group 27 pm_branch) Instruction SLB misses
+event:0X01B5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP27 : (Group 27 pm_branch) Processor cycles
+event:0X01B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP27 : (Group 27 pm_branch) Instructions completed
+event:0X01B7 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP27 : (Group 27 pm_branch) Branch mispredictions due to target address
+
+#Group 28 pm_data, data source and LMQ
+event:0X01C0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP28 : (Group 28 pm_data) Data loaded from L2
+event:0X01C1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP28 : (Group 28 pm_data) Data loaded from memory
+event:0X01C2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
+event:0X01C3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_data) Processor cycles
+event:0X01C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_data) Instructions completed
+event:0X01C5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_data) Processor cycles
+event:0X01C6 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP28 : (Group 28 pm_data) LMQ slot 0 allocated
+event:0X01C7 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP28 : (Group 28 pm_data) LMQ slot 0 valid
+
+#Group 29 pm_tlb, TLB and LRQ plus data prefetch
+event:0X01D0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP29 : (Group 29 pm_tlb) Data TLB misses
+event:0X01D1 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP29 : (Group 29 pm_tlb) Instruction TLB misses
+event:0X01D2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP29 : (Group 29 pm_tlb) Instructions completed
+event:0X01D3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP29 : (Group 29 pm_tlb) Processor cycles
+event:0X01D4 counters:4 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP29 : (Group 29 pm_tlb) LRQ slot 0 allocated
+event:0X01D5 counters:5 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP29 : (Group 29 pm_tlb) LRQ slot 0 valid
+event:0X01D6 counters:6 um:zero minimum:1000 name:PM_L1_PREF_GRP29 : (Group 29 pm_tlb) L1 cache data prefetches
+event:0X01D7 counters:7 um:zero minimum:1000 name:PM_L2_PREF_GRP29 : (Group 29 pm_tlb) L2 cache prefetches
+
+#Group 30 pm_isource, inst source and tablewalk
+event:0X01E0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP30 : (Group 30 pm_isource) Instructions fetched from L2
+event:0X01E1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP30 : (Group 30 pm_isource) Instruction fetched from memory
+event:0X01E2 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP30 : (Group 30 pm_isource) Hypervisor Cycles
+event:0X01E3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP30 : (Group 30 pm_isource) Instructions completed
+event:0X01E4 counters:4 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP30 : (Group 30 pm_isource) Cycles doing data tablewalks
+event:0X01E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP30 : (Group 30 pm_isource) Processor cycles
+event:0X01E6 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP30 : (Group 30 pm_isource) Group completed
+event:0X01E7 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP30 : (Group 30 pm_isource) L1 D cache entries invalidated from L2
+
+#Group 31 pm_sync, Sync and SRQ
+event:0X01F0 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP31 : (Group 31 pm_sync) SRQ slot 0 allocated
+event:0X01F1 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP31 : (Group 31 pm_sync) SRQ slot 0 valid
+event:0X01F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP31 : (Group 31 pm_sync) L1 D cache load misses
+event:0X01F3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP31 : (Group 31 pm_sync) SRQ sync duration
+event:0X01F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_sync) Instructions completed
+event:0X01F5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_sync) Instructions completed
+event:0X01F6 counters:6 um:zero minimum:10000 name:PM_CYC_GRP31 : (Group 31 pm_sync) Processor cycles
+event:0X01F7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP31 : (Group 31 pm_sync) L1 D cache load references
+
+#Group 32 pm_ierat, IERAT
+event:0X0200 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP32 : (Group 32 pm_ierat) Instruction fetched from L1
+event:0X0201 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
+event:0X0202 counters:2 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP32 : (Group 32 pm_ierat) Translation written to ierat
+event:0X0203 counters:3 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
+event:0X0204 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
+event:0X0205 counters:5 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
+event:0X0206 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_ierat) Instructions completed
+event:0X0207 counters:7 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_ierat) Processor cycles
+
+#Group 33 pm_derat, DERAT
+event:0X0210 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP33 : (Group 33 pm_derat) Cycles GCT empty
+event:0X0211 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP33 : (Group 33 pm_derat) Group dispatch valid
+event:0X0212 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP33 : (Group 33 pm_derat) L1 reload data source valid
+event:0X0213 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP33 : (Group 33 pm_derat) Instructions completed
+event:0X0214 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP33 : (Group 33 pm_derat) Instructions dispatched
+event:0X0215 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP33 : (Group 33 pm_derat) DERAT misses
+event:0X0216 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP33 : (Group 33 pm_derat) L1 D cache store references
+event:0X0217 counters:7 um:zero minimum:10000 name:PM_CYC_GRP33 : (Group 33 pm_derat) Processor cycles
+
+#Group 34 pm_mark1, Information on marked instructions
+event:0X0220 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP34 : (Group 34 pm_mark1) Marked L1 D cache load misses
+event:0X0221 counters:1 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP34 : (Group 34 pm_mark1) Threshold timeout
+event:0X0222 counters:2 um:zero minimum:10000 name:PM_CYC_GRP34 : (Group 34 pm_mark1) Processor cycles
+event:0X0223 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP34 : (Group 34 pm_mark1) Marked group completed
+event:0X0224 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP34 : (Group 34 pm_mark1) Group marked in IDU
+event:0X0225 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP34 : (Group 34 pm_mark1) Marked group issued
+event:0X0226 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP34 : (Group 34 pm_mark1) Marked instruction finished
+event:0X0227 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP34 : (Group 34 pm_mark1) Instructions completed
+
+#Group 35 pm_mark2, Marked Instructions Processing Flow
+event:0X0230 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP35 : (Group 35 pm_mark2) Marked group dispatched
+event:0X0231 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction BRU processing finished
+event:0X0232 counters:2 um:zero minimum:10000 name:PM_CYC_GRP35 : (Group 35 pm_mark2) Processor cycles
+event:0X0233 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction CRU processing finished
+event:0X0234 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP35 : (Group 35 pm_mark2) Group marked in IDU
+event:0X0235 counters:5 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction FXU processing finished
+event:0X0236 counters:6 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction FPU processing finished
+event:0X0237 counters:7 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP35 : (Group 35 pm_mark2) Marked instruction LSU processing finished
+
+#Group 36 pm_mark3, Marked Stores Processing Flow
+event:0X0240 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP36 : (Group 36 pm_mark3) Marked store instruction completed
+event:0X0241 counters:1 um:zero minimum:10000 name:PM_CYC_GRP36 : (Group 36 pm_mark3) Processor cycles
+event:0X0242 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP36 : (Group 36 pm_mark3) Marked store completed with intervention
+event:0X0243 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP36 : (Group 36 pm_mark3) Marked group completed
+event:0X0244 counters:4 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP36 : (Group 36 pm_mark3) Marked group completion timeout
+event:0X0245 counters:5 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP36 : (Group 36 pm_mark3) Marked store sent to GPS
+event:0X0246 counters:6 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP36 : (Group 36 pm_mark3) Marked instruction valid in SRQ
+event:0X0247 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP36 : (Group 36 pm_mark3) Instructions completed
+
+#Group 37 pm_lsu_mark1, Load Store Unit Marked Events
+event:0X0250 counters:0 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP37 : (Group 37 pm_lsu_mark1) Marked L1 D cache store misses
+event:0X0251 counters:1 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP37 : (Group 37 pm_lsu_mark1) Marked IMR reloaded
+event:0X0252 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_UST_GRP37 : (Group 37 pm_lsu_mark1) LSU0 marked unaligned store flushes
+event:0X0253 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_UST_GRP37 : (Group 37 pm_lsu_mark1) LSU1 marked unaligned store flushes
+event:0X0254 counters:4 um:zero minimum:10000 name:PM_CYC_GRP37 : (Group 37 pm_lsu_mark1) Processor cycles
+event:0X0255 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP37 : (Group 37 pm_lsu_mark1) Instructions completed
+event:0X0256 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_mark1) LSU0 marked unaligned load flushes
+event:0X0257 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_mark1) LSU1 marked unaligned load flushes
+
+#Group 38 pm_lsu_mark2, Load Store Unit Marked Events
+event:0X0260 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU0_GRP38 : (Group 38 pm_lsu_mark2) LSU0 L1 D cache load misses
+event:0X0261 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU1_GRP38 : (Group 38 pm_lsu_mark2) LSU1 L1 D cache load misses
+event:0X0262 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_LRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU0 marked LRQ flushes
+event:0X0263 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_LRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU1 marked LRQ flushes
+event:0X0264 counters:4 um:zero minimum:10000 name:PM_CYC_GRP38 : (Group 38 pm_lsu_mark2) Processor cycles
+event:0X0265 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP38 : (Group 38 pm_lsu_mark2) Instructions completed
+event:0X0266 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_SRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU0 marked SRQ flushes
+event:0X0267 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_SRQ_GRP38 : (Group 38 pm_lsu_mark2) LSU1 marked SRQ flushes
+
+#Group 39 pm_fxu1, Fixed Point events by unit
+event:0X0270 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_fxu1) Instructions completed
+event:0X0271 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_fxu1) Instructions completed
+event:0X0272 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP39 : (Group 39 pm_fxu1) FXU produced a result
+event:0X0273 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP39 : (Group 39 pm_fxu1) FXU1 busy FXU0 idle
+event:0X0274 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP39 : (Group 39 pm_fxu1) FXU idle
+event:0X0275 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP39 : (Group 39 pm_fxu1) FXU busy
+event:0X0276 counters:6 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP39 : (Group 39 pm_fxu1) FXU0 busy FXU1 idle
+event:0X0277 counters:7 um:zero minimum:10000 name:PM_CYC_GRP39 : (Group 39 pm_fxu1) Processor cycles
+
+#Group 40 pm_fxu2, Fixed Point events by unit
+event:0X0280 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP40 : (Group 40 pm_fxu2) Instructions completed
+event:0X0281 counters:1 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_fxu2) Processor cycles
+event:0X0282 counters:2 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP40 : (Group 40 pm_fxu2) Cycles FXU1/LS1 queue full
+event:0X0283 counters:3 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP40 : (Group 40 pm_fxu2) Cycles FXU0/LS0 queue full
+event:0X0284 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP40 : (Group 40 pm_fxu2) FXU idle
+event:0X0285 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP40 : (Group 40 pm_fxu2) FXU busy
+event:0X0286 counters:6 um:zero minimum:1000 name:PM_FXU0_FIN_GRP40 : (Group 40 pm_fxu2) FXU0 produced a result
+event:0X0287 counters:7 um:zero minimum:1000 name:PM_FXU1_FIN_GRP40 : (Group 40 pm_fxu2) FXU1 produced a result
+
+#Group 41 pm_ifu, pm_ifu
+event:0X0290 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP41 : (Group 41 pm_ifu) Instruction fetched from L1
+event:0X0291 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP41 : (Group 41 pm_ifu) Instruction fetched from memory
+event:0X0292 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP41 : (Group 41 pm_ifu) Instructions fetched from prefetch
+event:0X0293 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP41 : (Group 41 pm_ifu) No instructions fetched
+event:0X0294 counters:4 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP41 : (Group 41 pm_ifu) Cycles at least 1 instruction fetched
+event:0X0295 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP41 : (Group 41 pm_ifu) Instruction fetched from L2.5 modified
+event:0X0296 counters:6 um:zero minimum:10000 name:PM_CYC_GRP41 : (Group 41 pm_ifu) Processor cycles
+event:0X0297 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP41 : (Group 41 pm_ifu) Instructions completed
+
+#Group 42 pm_cpi_stack1, CPI stack analysis
+event:0X02A0 counters:0 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP42 : (Group 42 pm_cpi_stack1) LSU0 busy
+event:0X02A1 counters:1 um:zero minimum:1000 name:PM_LSU1_BUSY_GRP42 : (Group 42 pm_cpi_stack1) LSU1 busy
+event:0X02A2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP42 : (Group 42 pm_cpi_stack1) Flush initiated by LSU
+event:0X02A3 counters:3 um:zero minimum:1000 name:PM_FLUSH_LSU_BR_MPRED_GRP42 : (Group 42 pm_cpi_stack1) Flush caused by LSU or branch mispredict
+event:0X02A4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP42 : (Group 42 pm_cpi_stack1) Completion stall caused by LSU instruction
+event:0X02A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP42 : (Group 42 pm_cpi_stack1) Instructions completed
+event:0X02A6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP42 : (Group 42 pm_cpi_stack1) Completion stall caused by ERAT miss
+event:0X02A7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP42 : (Group 42 pm_cpi_stack1) Processor cycles
+
+#Group 43 pm_cpi_stack2, CPI stack analysis
+event:0X02B0 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_OTHER_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by other reason
+event:0X02B1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP43 : (Group 43 pm_cpi_stack2) Instructions completed
+event:0X02B2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP43 : (Group 43 pm_cpi_stack2) L1 D cache load misses
+event:0X02B3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP43 : (Group 43 pm_cpi_stack2) Processor cycles
+event:0X02B4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by D cache miss
+event:0X02B5 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP43 : (Group 43 pm_cpi_stack2) DERAT misses
+event:0X02B6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP43 : (Group 43 pm_cpi_stack2) Completion stall caused by reject
+event:0X02B7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP43 : (Group 43 pm_cpi_stack2) L1 D cache load references
+
+#Group 44 pm_cpi_stack3, CPI stack analysis
+event:0X02C0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP44 : (Group 44 pm_cpi_stack3) Instructions completed
+event:0X02C1 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_SRQ_FULL_GRP44 : (Group 44 pm_cpi_stack3) GCT empty caused by SRQ full
+event:0X02C2 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP44 : (Group 44 pm_cpi_stack3) FXU produced a result
+event:0X02C3 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP44 : (Group 44 pm_cpi_stack3) FPU produced a result
+event:0X02C4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP44 : (Group 44 pm_cpi_stack3) Completion stall caused by FXU instruction
+event:0X02C5 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP44 : (Group 44 pm_cpi_stack3) FXU busy
+event:0X02C6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP44 : (Group 44 pm_cpi_stack3) Completion stall caused by DIV instruction
+event:0X02C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP44 : (Group 44 pm_cpi_stack3) Processor cycles
+
+#Group 45 pm_cpi_stack4, CPI stack analysis
+event:0X02D0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FDIV instruction
+event:0X02D1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP45 : (Group 45 pm_cpi_stack4) FPU executed multiply-add instruction
+event:0X02D2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_cpi_stack4) Instructions completed
+event:0X02D3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP45 : (Group 45 pm_cpi_stack4) IOPS instructions completed
+event:0X02D4 counters:4 um:zero minimum:1000 name:PM_CMPLU_STALL_FDIV_GRP45 : (Group 45 pm_cpi_stack4) Completion stall caused by FDIV or FQRT instruction
+event:0X02D5 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP45 : (Group 45 pm_cpi_stack4) FPU executed FSQRT instruction
+event:0X02D6 counters:6 um:zero minimum:1000 name:PM_CMPLU_STALL_FPU_GRP45 : (Group 45 pm_cpi_stack4) Completion stall caused by FPU instruction
+event:0X02D7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP45 : (Group 45 pm_cpi_stack4) Processor cycles
+
+#Group 46 pm_cpi_stack5, CPI stack analysis
+event:0X02E0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles GCT empty
+event:0X02E1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP46 : (Group 46 pm_cpi_stack5) Instructions completed
+event:0X02E2 counters:2 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP46 : (Group 46 pm_cpi_stack5) Flush caused by branch mispredict
+event:0X02E3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP46 : (Group 46 pm_cpi_stack5) Branch mispredictions due to target address
+event:0X02E4 counters:4 um:zero minimum:1000 name:PM_GCT_EMPTY_IC_MISS_GRP46 : (Group 46 pm_cpi_stack5) GCT empty due to I cache miss
+event:0X02E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP46 : (Group 46 pm_cpi_stack5) Processor cycles
+event:0X02E6 counters:6 um:zero minimum:1000 name:PM_GCT_EMPTY_BR_MPRED_GRP46 : (Group 46 pm_cpi_stack5) GCT empty due to branch mispredict
+event:0X02E7 counters:7 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP46 : (Group 46 pm_cpi_stack5) Cycles writing to instruction L1
+
+#Group 47 pm_data2, data source and LMQ
+event:0X02F0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
+event:0X02F1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_data2) Instructions completed
+event:0X02F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
+event:0X02F3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP47 : (Group 47 pm_data2) Processor cycles
+event:0X02F4 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 shared
+event:0X02F5 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP47 : (Group 47 pm_data2) Data loaded from L2.5 modified
+event:0X02F6 counters:6 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP47 : (Group 47 pm_data2) LMQ slot 0 allocated
+event:0X02F7 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP47 : (Group 47 pm_data2) LMQ slot 0 valid
+
+#Group 48 pm_fetch_branch, Instruction fetch and branch events
+event:0X0300 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP48 : (Group 48 pm_fetch_branch) Instructions fetched from L2
+event:0X0301 counters:1 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP48 : (Group 48 pm_fetch_branch) Instruction fetched from memory
+event:0X0302 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP48 : (Group 48 pm_fetch_branch) Instructions fetched from prefetch
+event:0X0303 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP48 : (Group 48 pm_fetch_branch) Branches issued
+event:0X0304 counters:4 um:zero minimum:10000 name:PM_CYC_GRP48 : (Group 48 pm_fetch_branch) Processor cycles
+event:0X0305 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP48 : (Group 48 pm_fetch_branch) Instructions completed
+event:0X0306 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP48 : (Group 48 pm_fetch_branch) Branch mispredictions due to CR bit setting
+event:0X0307 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP48 : (Group 48 pm_fetch_branch) Branch mispredictions due to target address
+
+#Group 49 pm_l1l2_miss, L1 and L2 miss events
+event:0X0310 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from L2
+event:0X0311 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP49 : (Group 49 pm_l1l2_miss) Data loaded from memory
+event:0X0312 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_l1l2_miss) Instructions completed
+event:0X0313 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP49 : (Group 49 pm_l1l2_miss) LSU0 L1 D cache load misses
+event:0X0314 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP49 : (Group 49 pm_l1l2_miss) One or more PPC instruction completed
+event:0X0315 counters:5 um:zero minimum:10000 name:PM_CYC_GRP49 : (Group 49 pm_l1l2_miss) Processor cycles
+event:0X0316 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP49 : (Group 49 pm_l1l2_miss) LSU1 L1 D cache load misses
+event:0X0317 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP49 : (Group 49 pm_l1l2_miss) L1 D cache load references
+
+#Group 50 pm_data_from, Data From L2 instructions
+event:0X0320 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP50 : (Group 50 pm_data_from) Data loaded from L2
+event:0X0321 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP50 : (Group 50 pm_data_from) Data loaded from memory
+event:0X0322 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP50 : (Group 50 pm_data_from) Instructions completed
+event:0X0323 counters:3 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_data_from) Processor cycles
+event:0X0324 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP50 : (Group 50 pm_data_from) Data loaded from L2.5 shared
+event:0X0325 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP50 : (Group 50 pm_data_from) Data loaded from L2.5 modified
+event:0X0326 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP50 : (Group 50 pm_data_from) LSU1 L1 D cache load misses
+event:0X0327 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP50 : (Group 50 pm_data_from) L1 D cache load references
+
+#Group 51 pm_mark_data_from, Marked Data From L2 instructions
+event:0X0330 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP51 : (Group 51 pm_mark_data_from) Marked data loaded from L2
+event:0X0331 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_MEM_GRP51 : (Group 51 pm_mark_data_from) Marked data loaded from memory
+event:0X0332 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP51 : (Group 51 pm_mark_data_from) Instructions completed
+event:0X0333 counters:3 um:zero minimum:10000 name:PM_CYC_GRP51 : (Group 51 pm_mark_data_from) Processor cycles
+event:0X0334 counters:4 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP51 : (Group 51 pm_mark_data_from) Marked data loaded from L2.5 shared
+event:0X0335 counters:5 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP51 : (Group 51 pm_mark_data_from) Marked data loaded from L2.5 modified
+event:0X0336 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP51 : (Group 51 pm_mark_data_from) Marked instruction finished
+event:0X0337 counters:7 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP51 : (Group 51 pm_mark_data_from) Marked L1 reload data source valid
diff --git a/events/ppc64/970MP/unit_masks b/events/ppc64/970MP/unit_masks
new file mode 100644
index 0000000..012fe54
--- /dev/null
+++ b/events/ppc64/970MP/unit_masks
@@ -0,0 +1,9 @@
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2006.
+# Contributed by Dave Nomura <dcnltc@us.ibm.com>.
+#
+# ppc64 970 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/cell-be/events b/events/ppc64/cell-be/events
new file mode 100644
index 0000000..3bcb393
--- /dev/null
+++ b/events/ppc64/cell-be/events
@@ -0,0 +1,517 @@
+#ppc64 Cell Broadband Engine events
+#
+# Copyright OProfile authors
+#
+#(C) COPYRIGHT International Business Machines Corp. 2006
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>
+#
+#
+# As many as 4 signals may be specified when they are from the same group.
+# In some instances, signals from other groups in the same island or one
+# other island may also be specified.
+#
+# Each signal is assigned to a unique counter. There are 4 32-bit hardware
+# counters. The signals are defined in the Cell Broadband Engine
+# Performance manual.
+#
+# Each event is given a unique event number. The event number is used by the
+# Oprofile code to resolve event names for the postprocessing. This is done
+# to preserve compatibility with the rest of the Oprofile code. The event
+# number format group_num followed by the counter number for the event within
+# the group.
+
+# Signal Default
+event:0x1 counters:0,1,2,3 um:zero minimum:100000 name:CYCLES : Processor Cycles
+event:0x2 counters:0,1,2,3 um:zero minimum:60000 name:SPU_CYCLES : SPU Processor Cycles
+
+
+# Cell BE Island 2 - PowerPC Processing Unit (PPU)
+
+# CBE Signal Group 21 - PPU Instruction Unit - Group 1 (NClk)
+event:0x834 counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:Branch_Commit : Branch instruction committed.
+event:0x835 counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:Branch_Flush : Branch instruction that caused a misprediction flush is committed. Branch misprediction includes: (1) misprediction of taken or not-taken on conditional branch, (2) misprediction of branch target address on bclr[1] and bcctr[1].
+event:0x836 counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:Ibuf_Empty : Instruction buffer empty.
+event:0x837 counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:IERAT_Miss : Instruction effective-address-to-real-address translation (I-ERAT) miss.
+event:0x838 counters:0,1,2,3 um:PPU_01_cycles_or_edges minimum:10000 name:IL1_Miss_Cycles : L1 Instruction cache miss cycles. Counts the cycles from the miss event until the returned instruction is dispatched or cancelled due to branch misprediction, completion restart, or exceptions (see Note 1).
+event:0x83a counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:Dispatch_Blocked : Valid instruction available for dispatch, but dispatch is blocked.
+event:0x83d counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:Instr_Flushed : Instruction in pipeline stage EX7 causes a flush.
+event:0x83f counters:0,1,2,3 um:PPU_01_edges minimum:10000 name:PPC_Commit : Two PowerPC instructions committed. For microcode sequences, only the last microcode operation is counted. Committed instructions are counted two at a time. If only one instruction has committed for a given cycle, this event will not be raised until another instruction has been committed in a future cycle.
+
+
+# CBE Signal Group 22 - PPU Execution Unit (NClk)
+event:0x89a counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:DERAT_Miss : Data effective-address-to-real-address translation (D-ERAT) miss. Not speculative.
+event:0x89b counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:Store_Request : Store request counted at the L2 interface. Counts microcoded PPE sequences more than once (see Note 1 for exceptions). (Thread 0 and 1)
+event:0x89c counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:Load_Valid : Load valid at a particular pipe stage. Speculative, since flushed operations are counted as well. Counts microcoded PPE sequences more than once. Misaligned flushes might be counted the first time as well. Load operations include all loads that read data from the cache, dcbt and dcbtst. Does not include load Vector/SIMD multimedia extension pattern instructions.
+event:0x89d counters:0,1,2,3 um:PPU_01_cycles minimum:10000 name:DL1_Miss : L1 D-cache load miss. Pulsed when there is a miss request that has a tag miss but not an ERAT miss. Speculative, since flushed operations are counted as well.
+
+
+# Cell BE Island 3 - PowerPC Storage Subsystem (PPSS)
+
+# CBE Signal Group 31 - PPSS Bus Interface Unit (NClk/2)
+event:0xc1c counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:rcv_mmio_rd_ev : Load from MFC memory-mapped I/O (MMIO) space.
+event:0xc1d counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:rcv_mmio_wr_ev : Stores to MFC MMIO space.
+event:0xc22 counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:even_token_req_ev : Request token for even memory bank numbers 0-14.
+event:0xc2b counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:rcv_data_ev : Receive 8-beat data from the Element Interconnect Bus (EIB).
+event:0xc2c counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:send_data_ev : Send 8-beat data to the EIB.
+event:0xc2d counters:0,1,2,3 um:PPU_2_edges minimum:10000 name:send_cmd_ev : Send a command to the EIB; includes retried commands.
+event:0xc2e counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:dgnt_dly_cy : Cycles between data request and data grant.
+event:0xc33 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:nc_wr_not_emp_cy : The five-entry Non-Cacheable Unit (NCU) Store Command queue not empty.
+
+
+# CBE Signal Group 32 - PPSS L2 Cache Controller - Group 1 (NClk/2)
+event:0xc80 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:cache_hit : Cache hit for core interface unit (CIU) loads and stores.
+event:0xc81 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:cache_miss : Cache miss for CIU loads and stores.
+event:0xc84 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:load_miss : CIU load miss.
+event:0xc85 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:store_miss : CIU store to Invalid state (miss).
+event:0xc87 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:larx_miss_th1 : Load word and reserve indexed (lwarx/ldarx) for Thread 0 hits Invalid cache state
+event:0xc8e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:stcx_miss_th1 : Store word conditional indexed (stwcx/stdcx) for Thread 0 hits Invalid cache state when reservation is set.
+event:0xc99 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:all_snp_busy : All four snoop state machines busy.
+
+# CBE Signal Group 33 - PPSS L2 Cache Controller - Group 2 (NClk/2)
+event:0xce8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:dclaim_srt : Data line claim (dclaim) that received good combined response; includes store/stcx/dcbz to Shared (S), Shared Last (SL),or Tagged (T) cache state; does not include dcbz to Invalid (I) cache state (see Note 1).
+event:0xcef counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:dclaim_to_rwitm : Dclaim converted into rwitm; may still not get to the bus if stcx is aborted (see Note 2).
+event:0xcf0 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:store_mxe : Store to modified (M), modified unsolicited (MU), or exclusive (E) cache state.
+event:0xcf1 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:stq_full : 8-entry store queue (STQ) full.
+event:0xcf2 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:store_rc_ack : Store dispatched to RC machine is acknowledged.
+event:0xcf3 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:gather_store : Gatherable store (type = 00000) received from CIU.
+event:0xcf6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_push : Snoop push.
+event:0xcf7 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:intv_snode_er : Send intervention from (SL | E) cache state to a destination within the same CBE chip.
+event:0xcf8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:intv_snode_mx : Send intervention from (M | MU) cache state to a destination within the same CBE chip.
+event:0xcfd counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_retry : Respond with Retry to a snooped request due to one of the following conflicts: read-and-claim state machine (RC) full address, castout (CO) congruence class, snoop (SNP) machine full address, all snoop machines busy, directory lockout, or parity error.
+event:0xcfe counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_busy_retry : Respond with Retry to a snooped request because all snoop machines are busy.
+event:0xcff counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_mx_to_est : Snooped response causes a cache state transition from (M | MU) to (E | S | T).
+event:0xd00 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_e_to_s : Snooped response causes a cache state transition from E to S.
+event:0xd01 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_esrt_to_i : Snooped response causes a cache state transition from (E | SL | S | T) to Invalid (I).
+event:0xd02 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:snp_mx_to_i : Snooped response causes a cache state transition from (M | MU) to I.
+
+# CBE Signal Group 34 - PPSS L2 Cache Controller - Group 3 (NClk/2)
+event:0xd54 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:larx_miss : Load and reserve indexed (lwarx/ldarx) for Thread 1 hits Invalid cache state.
+event:0xd5b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:stcx_miss_th2 : Store conditional indexed (stwcx/stdcx) for Thread 1 hits Invalid cache state.
+
+# CBE Signal Group 35 - PPSS Non-Cacheable Unit (NClk/2)
+event:0xdac counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_any : Non-cacheable store request received from CIU; includes all synchronization operations such as sync and eieio.
+event:0xdad counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_sync : sync received from CIU.
+event:0xdb0 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_store : Non-cacheable store request received from CIU; includes only stores.
+event:0xdb2 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_eieio : eieio received from CIU.
+event:0xdb3 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_req_tlbie : tlbie received from CIU.
+event:0xdb4 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_bot_sync : sync at the bottom of the store queue, while waiting on st_done signal from the Bus Interface Unit (BIU) and sync_done signal from L2.
+event:0xdb5 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_bot_lsync : lwsync at the bottom of the store queue, while waiting for a sync_done signal from the L2.
+event:0xdb6 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_bot_eieio : eieio at the bottom of the store queue, while waiting for a st_done signal from the BIU and a sync_done signal from the L2.
+event:0xdb7 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_bot_tlbieg : tlbie at the bottom of the store queue, while waiting for a st_done signal from the BIU.
+event:0xdb8 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:st_combined : Non-cacheable store combined with the previous non-cacheable store with a contiguous address.
+event:0xdb9 counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:ld_cancel : Load request canceled by CIU due to late detection of load-hit-store condition (128B boundary).
+event:0xdba counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:ld_hit_st : NCU detects a load hitting a previous store to an overlapping address (32B boundary).
+event:0xdbb counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stb_full : All four store-gather buffers full.
+event:0xdbc counters:0,1,2,3 um:PPU_0_edges minimum:10000 name:ld_req : Non-cacheable load request received from CIU; includes instruction and data fetches.
+event:0xdbd counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_not_empty : The four-deep store queue not empty.
+event:0xdbe counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stq_full : The four-deep store queue full.
+event:0xdbf counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:stb_not_empty : At least one store gather buffer not empty.
+
+# Cell BE Island 4 - Synergistic Processor Unit (SPU)
+#
+# OPROFILE FOR CELL ONLY SUPPORTS PROFILING ON ONE SPU EVENT AT A TIME
+#
+# CBE Signal Group 41 - SPU (NClk)
+event:0x1004 counters:0 um:SPU_02_cycles minimum:10000 name:dual_instrctn_commit : Dual instruction committed.
+event:0x1005 counters:0 um:SPU_02_cycles minimum:10000 name:sngl_instrctn_commit : Single instruction committed.
+event:0x1006 counters:0 um:SPU_02_cycles minimum:10000 name:ppln0_instrctn_commit : Pipeline 0 instruction committed.
+event:0x1007 counters:0 um:SPU_02_cycles minimum:10000 name:ppln1_instrctn_commit : Pipeline 1 instruction committed.
+event:0x1008 counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:instrctn_ftch_stll : Instruction fetch stall.
+event:0x1009 counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:lcl_strg_bsy : Local storage busy.
+event:0x100A counters:0 um:SPU_02_cycles minimum:10000 name:dma_cnflct_ld_st : DMA may conflict with load or store.
+event:0x100B counters:0 um:SPU_02_cycles minimum:10000 name:str_to_lcl_strg : Store instruction to local storage issued.
+event:0x100C counters:0 um:SPU_02_cycles minimum:10000 name:ld_frm_lcl_strg : Load intruction from local storage issued.
+event:0x100D counters:0 um:SPU_02_cycles minimum:10000 name:fpu_exctn : Floating-Point Unit (FPU) exception.
+event:0x100E counters:0 um:SPU_02_cycles minimum:10000 name:brnch_instrctn_commit : Branch instruction committed.
+event:0x100F counters:0 um:SPU_02_cycles minimum:10000 name:change_of_flow : Non-sequential change of the SPU program counter, which can be caused by branch, asynchronous interrupt, stalled wait on channel, error correction code (ECC) error, and so forth.
+event:0x1010 counters:0 um:SPU_02_cycles minimum:10000 name:brnch_not_tkn : Branch not taken.
+event:0x1011 counters:0 um:SPU_02_cycles minimum:10000 name:brnch_mss_prdctn : Branch miss prediction; not exact. Certain other code sequences can cause additional pulses on this signal (see Note 2).
+event:0x1012 counters:0 um:SPU_02_cycles minimum:10000 name:brnch_hnt_mss_prdctn : Branch hint miss prediction; not exact. Certain other code sequences can cause additional pulses on this signal (see Note 2).
+event:0x1013 counters:0 um:SPU_02_cycles minimum:10000 name:instrctn_seqnc_err : Instruction sequence error.
+event:0x1015 counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl_wrt : Stalled waiting on any blocking channel write (see Note 3).
+event:0x1016 counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl0 : Stalled waiting on External Event Status (Channel 0) (see Note 3).
+event:0x1017 counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl3 : Stalled waiting on Signal Notification 1 (Channel 3) (see Note 3).
+event:0x1018 counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl4 : Stalled waiting on Signal Notification 2 (Channel 4) (see Note 3).
+event:0x1019 counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl21 : Stalled waiting on DMA Command Opcode or ClassID Register (Channel 21) (see Note 3).
+event:0x101A counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl24 : Stalled waiting on Tag Group Status (Channel 24) (see Note 3).
+event:0x101B counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl25 : Stalled waiting on List Stall-and-Notify Tag Status (Channel 25) (see Note 3).
+event:0x101C counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl28 : Stalled waiting on PPU Mailbox (Channel 28) (see Note 3).
+event:0x1022 counters:0 um:SPU_02_cycles_or_edges minimum:10000 name:stlld_wait_on_chnl29 : Stalled waiting on SPU Mailbox (Channel 29) (see Note 3).
+
+
+# CBE Signal Group 42 - SPU Trigger (NClk)
+event:0x10A1 counters:0 um:SPU_Trigger_cycles_or_edges minimum:10000 name:stld_wait_chnl_op : Stalled waiting on channel operation (See Note 2).
+
+# CBE Signal Group 43 - SPU Event (NClk)
+event:0x1107 counters:0 um:SPU_Event_cycles_or_edges minimum:10000 name:instrctn_ftch_stll : Instruction fetch stall.
+
+# Cell BE Island 6 - Element Interconnect Bus (EIB)
+
+# CBE Signal Group 61 - EIB Address Concentrator 0 (NClk/2)
+event:0x17d4 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(0) : Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 1)
+event:0x17d5 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(1) : Number of dclaim commands (including atomic) AC1 to AC0. (Group 1)
+event:0x17d6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(2) : Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 1)
+event:0x17d7 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(3) : Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 1)
+event:0x17d8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(4) : Number of tlbie commands from AC1 to AC0. (Group 1)
+event:0x17df counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_CAM_PERF(1) : Previous adjacent address match (PAAM) Content Addressable Memory (CAM) hit. (Group 1)
+event:0x17e0 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_CAM_PERF(2) : PAAM CAM miss. (Group 1)
+event:0x17e2 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_CAM_CMD_REFLECTED : Command reflected. (Group 1)
+event:0x17e4 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(0) : Number of read and rwitm commands (including atomic) AC1 to AC0. (Group 2)
+event:0x17e5 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(1) : Number of dclaim commands (including atomic) AC1 to AC0. (Group 2)
+event:0x17e6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(2) : Number of wwk, wwc, and wwf commands from AC1 to AC0. (Group 2)
+event:0x17e7 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(3) : Number of sync, tlbsync, and eieio commands from AC1 to AC0. (Group 2)
+event:0x17e8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_ICMD_PERF(4) : Number of tlbie commands from AC1 to AC0. (Group 2)
+event:0x17ef counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_CAM_PERF(1) : PAAM CAM hit. (Group 2)
+event:0x17f0 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_CAM_PERF(2) : PAAM CAM miss. (Group 2)
+event:0x17f2 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC0_W_CAM_CMD_REFLECTED : Command reflected. (Group 2)
+
+# CBE Signal Group 62 - EIB Address Concentrator 1 (NClk/2)
+event:0x1839 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(1) : Local command from SPE 6.
+event:0x183a counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(2) : Local command from SPE 4.
+event:0x183b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(3) : Local command from SPE 2.
+event:0x183c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(4) : Local command from SPE 0.
+event:0x183d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(5) : Local command from PPE.
+event:0x183e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(6) : Local command from SPE 1.
+event:0x183f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(7) : Local command from SPE 3.
+event:0x1840 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(8) : Local command from SPE 5.
+event:0x1841 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(9) : Local command from SPE 7.
+event:0x1844 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(12) : AC1-to-AC0 global command from SPE 6.
+event:0x1845 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(13) : AC1-to-AC0 global command from SPE 4.
+event:0x1846 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(14) : AC1-to-AC0 global command from SPE 2.
+event:0x1847 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(15) : AC1-to-AC0 global command from SPE 0.
+event:0x1848 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(16) : AC1-to-AC0 global command from PPE.
+event:0x1849 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(17) : AC1-to-AC0 global command from SPE 1.
+event:0x184a counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(18) : AC1-to-AC0 global command from SPE 3.
+event:0x184b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(19) : AC1-to-AC0 global command from SPE 5.
+event:0x184c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(20) : AC1-to-AC0 global command from SPE 7.
+event:0x184f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(23) : AC1 sends a global command to AC0.
+event:0x1850 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(24) : AC0 reflects a global command back to AC1.
+event:0x1851 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WAC1_WAC1_TRCMUX_W_TRCGRP_ACPERF(25) : AC1 reflects a command back to the bus masters.
+
+# CBE Signal Group 63 - EIB Data Ring Arbitrator - Group 1 (NClk/2)
+event:0x189c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(0) : Grant on data ring 0.
+event:0x189d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(1) : Grant on data ring 1.
+event:0x189e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(2) : Grant on data ring 2.
+event:0x189f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(3) : Grant on data ring 3.
+event:0x18a0 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPE(4) : Data ring 0 is in use.
+event:0x18a1 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPE(5) : Data ring 1 is in use.
+event:0x18a2 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPE(6) : Data ring 2 is in use.
+event:0x18a3 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPE(7) : Data ring 3 is in use.
+event:0x18a4 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPE(8) : All data rings are idle.
+event:0x18a5 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPE(9) : One data ring is busy.
+event:0x18a6 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPE(10) : Two or three data rings are busy.
+event:0x18a7 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPE(11) : All data rings are busy.
+event:0x18a8 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(12) : BIC data request pending.
+event:0x18a9 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(13) : SPE 6 data request pending.
+event:0x18aa counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(14) : SPE 4 data request pending.
+event:0x18ab counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(15) : SPE 2 data request pending.
+event:0x18ac counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(16) : SPE 0 data request pending.
+event:0x18ad counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(17) : MIC data request pending.
+event:0x18ae counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(18) : PPE data request pending.
+event:0x18af counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(19) : SPE 1 data request pending.
+event:0x18b0 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(20) : SPE 3 data request pending.
+event:0x18b1 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(21) : SPE 5 data request pending.
+event:0x18b2 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(22) : SPE 7 data request pending.
+event:0x18b3 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPE(23) : IOC data request pending.
+event:0x18b4 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(24) : BIC is data destination.
+event:0x18b5 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(25) : SPE 6 is data destination.
+event:0x18b6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(26) : SPE 4 is data destination.
+event:0x18b7 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(27) : SPE 2 is data destination.
+event:0x18b8 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(28) : SPE 0 is data destination.
+event:0x18b9 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(29) : MIC is data destination.
+event:0x18ba counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(30) : PPE is data destination.
+event:0x18bb counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPE(31) : SPE 1 is data destination.
+
+# CBE Signal Group 64 - EIB Data Ring Arbitrator - Group 2 (NClk/2)
+event:0x1900 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(0) : BIC data request pending.
+event:0x1901 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(1) : SPE 6 data request pending.
+event:0x1902 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(2) : SPE 4 data request pending.
+event:0x1903 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(3) : SPE 2 data request pending.
+event:0x1904 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(4) : SPE 0 data request pending.
+event:0x1905 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(5) : MIC data request pending.
+event:0x1906 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(6) : PPE data request pending.
+event:0x1907 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(7) : SPE 1 data request pending.
+event:0x1908 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(8) : SPE 3 data request pending.
+event:0x1909 counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(9) : SPE 5 data request pending.
+event:0x190a counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(10) : SPE 7 data request pending.
+event:0x190b counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:WDA_DTRC_TRCGRPF(11) : IOC data request pending.
+event:0x190c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(12) : BIC is data destination.
+event:0x190d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(13) : SPE 6 is data destination.
+event:0x190e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(14) : SPE 4 is data destination.
+event:0x190f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(15) : SPE 2 is data destination.
+event:0x1910 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(16) : SPE 0 is data destination.
+event:0x1911 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(17) : MIC is data destination.
+event:0x1912 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(18) : PPE is data destination.
+event:0x1913 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(19) : SPE 1 is data destination.
+event:0x1914 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(20) : SPE 3 is data destination.
+event:0x1915 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(21) : SPE 5 is data destination.
+event:0x1916 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(22) : SPE 7 is data destination.
+event:0x1917 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(23) : IOC is data destination.
+event:0x1918 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(24) : Grant on data ring 0.
+event:0x1919 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(25) : Grant on data ring 1.
+event:0x191a counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(26) : Grant on data ring 2.
+event:0x191b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:WDA_DTRC_TRCGRPF(27) : Grant on data ring 3.
+event:0x191c counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPF(28) : All data rings are idle.
+event:0x191d counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPF(29) : One data ring is busy.
+event:0x191e counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPF(30) : Two or three data rings are busy.
+event:0x191f counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:WDA_DTRC_TRCGRPF(31) : All four data rings are busy.
+
+# CBE Signal Group 651 - EIB Token Manager - Group A0/B0 (NClk/2)
+event:0xfe4c counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_unused : Even XIO token unused by RAG 0.
+event:0xfe4d counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_unused : Odd XIO token unused by RAG 0.
+event:0xfe4e counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_unused : Even bank token unused by RAG 0.
+event:0xfe4f counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_unused : Odd bank token unused by RAG 0.
+event:0xfe54 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc0 : Token granted for SPE 0.
+event:0xfe55 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc1 : Token granted for SPE 1.
+event:0xfe56 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc2 : Token granted for SPE 2.
+event:0xfe57 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc3 : Token granted for SPE 3.
+event:0xfe58 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc4 : Token granted for SPE 4.
+event:0xfe59 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc5 : Token granted for SPE 5.
+event:0xfe5a counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc6 : Token granted for SPE 6.
+event:0xfe5b counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:token_granted_spc7 : Token granted for SPE 7.
+
+
+# CBE Signal Group 652 - EIB Token Manager - Group A1/B1 (NClk/2)
+event:0xfeb0 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_wasted : Even XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.
+event:0xfeb1 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_wasted : Odd XIO token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.
+event:0xfeb2 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_wasted : Even bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.
+event:0xfeb3 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_wasted : Odd bank token wasted by RAG 0; valid only when Unused Enable (UE) = 1 in TKM_CR register.
+event:0xfebc counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_xio_e_wasted : Even XIO token wasted by RAG U.
+event:0xfebd counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_xio_o_wasted : Odd XIO token wasted by RAG U.
+event:0xfebe counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_e_wasted : Even bank token wasted by RAG U.
+event:0xfebf counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_o_wasted : Odd bank token wasted by RAG U.
+
+# CBE Signal Group 653 - EIB Token Manager - Group A2/B2 (NClk/2)
+event:0xff14 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_shared_to_rag1 : Even XIO token from RAG 0 shared with RAG 1
+event:0xff15 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_shared_to_rag2 : Even XIO token from RAG 0 shared with RAG 2
+event:0xff16 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_e_shared_to_rag3 : Even XIO token from RAG 0 shared with RAG 3
+event:0xff17 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_shared_to_rag1 : Odd XIO token from RAG 0 shared with RAG 1
+event:0xff18 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_shared_to_rag2 : Odd XIO token from RAG 0 shared with RAG 2
+event:0xff19 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_xio_o_shared_to_rag3 : Odd XIO token from RAG 0 shared with RAG 3
+event:0xff1a counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_shared_to_rag1 : Even bank token from RAG 0 shared with RAG 1
+event:0xff1b counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_shared_to_rag2 : Even bank token from RAG 0 shared with RAG 2
+event:0xff1c counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_e_shared_to_rag3 : Even bank token from RAG 0 shared with RAG 3
+event:0xff1d counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_shared_to_rag1 : Odd bank token from RAG 0 shared with RAG 1
+event:0xff1e counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_shared_to_rag2 : Odd bank token from RAG 0 shared with RAG 2
+event:0xff1f counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag0_bank_o_shared_to_rag3 : Odd bank token from RAG 0 shared with RAG 3
+
+
+# CBE Signal Group 654 - EIB Token Manager - Group A0/B0 (NClk/2)
+# Repeat of the 65400, 65401, 65402, 65403, 65416, 65417, 65418, 65419 events
+
+
+# CBE Signal Group 655 - EIB Token Manager - Group A1/B1 (NClk/2)
+#repeat of the 65200 events
+
+
+# CBE Signal Group 656 - EIB Token Manager - Group A2/B2 (NClk/2)
+event:0x1004f counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_o_shared_to_rag0 : Odd bank token from RAG U shared with RAG 0
+event:0x10050 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_e_shared_to_rag0 : Even XIO token from RAG 1 shared with RAG 0
+event:0x10051 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_e_shared_to_rag2 : Even XIO token from RAG 1 shared with RAG 2
+event:0x10052 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_e_shared_to_rag3 : Even XIO token from RAG 1 shared with RAG 3
+event:0x10053 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_o_shared_to_rag0 : Odd XIO token from RAG 1 shared with RAG 0
+event:0x10054 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_o_shared_to_rag2 : Odd XIO token from RAG 1 shared with RAG 2
+event:0x10055 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_xio_o_shared_to_rag3 : Odd XIO token from RAG 1 shared with RAG 3
+event:0x10056 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_e_shared_to_rag0 : Even bank token from RAG 1 shared with RAG 0
+event:0x10057 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_e_shared_to_rag2 : Even bank token from RAG 1 shared with RAG 2
+event:0x10058 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_e_shared_to_rag3 : Even bank token from RAG 1 shared with RAG 3
+event:0x10059 counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_o_shared_to_rag0 : Odd bank token from RAG 1 shared with RAG 0
+event:0x1005a counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_o_shared_to_rag2 : Odd bank token from RAG 1 shared with RAG 2
+event:0x1005b counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:rag1_bank_o_shared_to_rag3 : Odd bank token from RAG 1 shared with RAG 3
+event:0x1005c counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_xio_e_shared_to_rag1 : Even XIO token from RAG U shared with RAG 1
+event:0x1005d counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_xio_o_shared_to_rag1 : Odd XIO token from RAG U shared with RAG 1
+event:0x1005e counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_e_shared_to_rag1 : Even bank token from RAG U shared with RAG 1
+event:0x1005f counters:0,1,2,3 um:PPU_0_cycles minimum:10000 name:ragu_bank_o_shared_to_rag1 : Odd bank token from RAG U shared with RAG 1
+
+# CBE Signal Group 657 - EIB Token Manager - Group C0/D0 (NClk/2)
+event:0x100e4 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_unused : Even XIO token unused by RAG 2
+event:0x100e5 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_unused : Odd XIO token unused by RAG 2
+event:0x100e6 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_unused : Even bank token unused by RAG 2
+event:0x100e7 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_unused : Odd bank token unused by RAG 2
+event:0x100e8 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif0_in_unused : IOIF0 In token unused by RAG 0
+event:0x100e9 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif0_out_unused : IOIF0 Out token unused by RAG 0
+event:0x100ea counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif1_in_unused : IOIF1 In token unused by RAG 0
+event:0x100eb counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif1_out_unused : IOIF1 Out token unused by RAG 0
+
+
+# CBE Signal Group 658 - EIB Token Manager - Group C1/D1 (NClk/2)
+event:0x10148 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_wasted : Even XIO token wasted by RAG 2
+event:0x10149 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_wasted : Odd XIO token wasted by RAG 2
+event:0x1014a counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_wasted : Even bank token wasted by RAG 2
+event:0x1014b counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_wasted : Odd bank token wasted by RAG 2
+
+
+# CBE Signal Group 659 - EIB Token Manager - Group C2/D2 (NClk/2)
+event:0x101ac counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_shared_to_rag0 : Even XIO token from RAG 2 shared with RAG 0
+event:0x101ad counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_shared_to_rag1 : Even XIO token from RAG 2 shared with RAG 1
+event:0x101ae counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_e_shared_to_rag3 : Even XIO token from RAG 2 shared with RAG 3
+event:0x101af counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_shared_to_rag0 : Odd XIO token from RAG 2 shared with RAG 0
+event:0x101b0 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_shared_to_rag1 : Odd XIO token from RAG 2 shared with RAG 1
+event:0x101b1 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_xio_o_shared_to_rag3 : Odd XIO token from RAG 2 shared with RAG 3
+event:0x101b2 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_shared_to_rag0 : Even bank token from RAG 2 shared with RAG 0
+event:0x101b3 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_shared_to_rag1 : Even bank token from RAG 2 shared with RAG 1
+event:0x101b4 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_e_shared_to_rag3 : Even bank token from RAG 2 shared with RAG 3
+event:0x101b5 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_shared_to_rag0 : Odd bank token from RAG 2 shared with RAG 0
+event:0x101b6 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_shared_to_rag1 : Odd bank token from RAG 2 shared with RAG 1
+event:0x101b7 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag2_bank_o_shared_to_rag3 : Odd bank token from RAG 2 shared with RAG 3
+
+
+# CBE Signal Group 6510 - EIB Token Manager - Group C3 (NClk/2)
+event:0x9ef38 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif0_in_wasted : IOIF0 In token wasted by RAG 0
+event:0x9ef39 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif0_out_wasted : IOIF0 Out token wasted by RAG 0
+event:0x9ef3a counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif1_in_wasted : IOIF1 In token wasted by RAG 0
+event:0x9ef3b counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag0_ioif1_out_wasted : IOIF1 Out token wasted by RAG 0
+
+
+# CBE Signal Group 6511 - EIB Token Manager - Group C0/D0 (NClk/2)
+# repeat of the events 65764 - 65771
+
+# CBE Signal Group 6512 - EIB Token Manager - Group C1/D1 (NClk/2)
+event:0x9f010 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_e_wasted : Even XIO token wasted by RAG 3
+event:0x9f011 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_o_wasted : Odd XIO token wasted by RAG 3
+event:0x9f012 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_e_wasted : Even bank token wasted by RAG 3
+event:0x9f013 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_o_wasted : Odd bank token wasted by RAG 3
+
+# CBE Signal Group 6513 - EIB Token Manager - Group C2/D2 (NClk/2)
+event:0x9f074 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_e_shared_to_rag0 : Even XIO token from RAG 3 shared with RAG 0
+event:0x9f075 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_e_shared_to_rag1 : Even XIO token from RAG 3 shared with RAG 1
+event:0x9f076 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_e_shared_to_rag2 : Even XIO token from RAG 3 shared with RAG 2
+event:0x9f077 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_o_shared_to_rag0 : Odd XIO token from RAG 3 shared with RAG 0
+event:0x9f078 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_o_shared_to_rag1 : Odd XIO token from RAG 3 shared with RAG 1
+event:0x9f079 counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_xio_o_shared_to_rag2 : Odd XIO token from RAG 3 shared with RAG 2
+event:0x9f07a counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_e_shared_to_rag0 : Even bank token from RAG 3 shared with RAG 0
+event:0x9f07b counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_e_shared_to_rag1 : Even bank token from RAG 3 shared with RAG 1
+event:0x9f07c counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_e_shared_to_rag2 : Even bank token from RAG 3 shared with RAG 2
+event:0x9f07d counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_o_shared_to_rag0 : Odd bank token from RAG 3 shared with RAG 0
+event:0x9f07e counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_o_shared_to_rag1 : Odd bank token from RAG 3 shared with RAG 1
+event:0x9f07f counters:0,1,2,3 um:PPU_2_cycles minimum:10000 name:rag3_bank_o_shared_to_rag2 : Odd bank token from RAG 3 shared with RAG 2
+
+
+# Cell BE Island 7 - Memory Interface Controller (MIC)
+
+# CBE Signal Group 71 - MIC Group 1 (NClk/2)
+event:0x1bc5 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM1(1) : XIO1 - Read command queue is empty.
+event:0x1bc6 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM1(2) : XIO1 - Write command queue is empty.
+event:0x1bc8 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM1(4) : XIO1 - Read command queue is full.
+event:0x1bc9 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM1(5) : XIO1 - MIC responds with a Retry for a read command because the read command queue is full.
+event:0x1bca counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM1(6) : XIO1 - Write command queue is full.
+event:0x1bcb counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM1(7) : XIO1 - MIC responds with a Retry for a write command because the write command queue is full.
+event:0x1bde counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1_YMM_CCS_PERFORM(2) : XIO1 - Read command dispatched; includes high-priority and fast-path reads (see Note 1).
+event:0x1bdf counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1_YMM_CCS_PERFORM(3) : XIO1 - Write command dispatched (see Note 1).
+event:0x1be0 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1_YMM_CCS_PERFORM(4) : XIO1 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1).
+event:0x1be1 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1_YMM_CCS_PERFORM(5) : XIO1 - Refresh dispatched (see Note 1).
+event:0x1be3 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1_YMM_CCS_PERFORM(7) : XIO1 - Byte-masking write command (data size >= 16 bytes) dispatched (see Note 1).
+event:0x1be5 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1_YMM_CRW_PERFORM(1) : XIO1 - Write command dispatched after a read command was previously dispatched (see Note 1).
+event:0x1be6 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL1_YMM_CRW_PERFORM(2) : XIO1 - Read command dispatched after a write command was previously dispatched (see Note 1).
+
+
+# CBE Signal Group 72 - MIC Group 2 (NClk/2)
+event:0x1c29 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM2(1) : XIO0 - Read command queue is empty.
+event:0x1c2a counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM2(2) : XIO0 - Write command queue is empty.
+event:0x1c2c counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM2(4) : XIO0 - Read command queue is full.
+event:0x1c2d counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM2(5) : XIO0 - MIC responds with a Retry for a read command because the read command queue is full.
+event:0x1c2e counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM2(6) : XIO0 - Write command queue is full.
+event:0x1c2f counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_COMMON_YMB_CSR_PERFORM2(7) : XIO0 - MIC responds with a Retry for a write command because the write command queue is full.
+event:0x1c42 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CCS_PERFORM(2) : XIO0 - Read command dispatched; includes high-priority and fast-path reads (see Note 1).
+event:0x1c43 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CCS_PERFORM(3) : XIO0 - Write command dispatched (see Note 1).
+event:0x1c44 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CCS_PERFORM(4) : XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1).
+event:0x1c45 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CCS_PERFORM(5) : XIO0 - Refresh dispatched (see Note 1).
+event:0x1c49 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CRW_PERFORM(1) : XIO0 - Write command dispatched after a read command was previously dispatched (see Note 1).
+event:0x1c4a counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CRW_PERFORM(2) : XIO0 - Read command dispatched after a write command was previously dispatched (see Note 1).
+
+# CBE Signal Group 73 - MIC Group 3 (NClk/2)
+event:0x1ca7 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CCS_PERFORM(3) : XIO0 - Write command dispatched (see Note 1).
+event:0x1ca8 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CCS_PERFORM(4) : XIO0 - Read-Modify-Write command (data size < 16 bytes) dispatched (see Note 1).
+event:0x1ca9 counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CCS_PERFORM(5) : XIO0 - Refresh dispatched (see Note 1).
+event:0x1cab counters:0,1,2,3 um:PPU_0123_cycles minimum:10000 name:YM_CTL0_YMM_CCS_PERFORM(7) : XIO0 - Byte-masking write command (data size >= 16 bytes) dispatched (see Note 1).
+
+
+# Cell BE Island 8 - Broadband Engine Interface (BEI)
+
+# CBE Signal Group 81 - BIF Controller - IOIF0 Word 0 (NClk/2)
+event:0x1fb0 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:B2F_Type_A_Data : Type A data physical layer group (PLG). Does not include header-only or credit-only data PLGs. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data.
+event:0x1fb1 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:B2F_Type_B_Data : Type B data PLG. In IOIF mode, counts I/O device read data; in BIF mode, counts all outbound data.
+event:0x1fb2 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:IOC_Type_A_Data : Type A data PLG. Does not include header-only or credit-only PLGs. In IOIF mode, counts CBE store data to I/O device. Does not apply in BIF mode.
+event:0x1fb3 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:IOC_Type_B_Data : Type B data PLG. In IOIF mode, counts CBE store data to an I/O device. Does not apply in BIF mode.
+event:0x1fb4 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Data_PLG : Data PLG. Does not include header-only or credit-only PLGs.
+event:0x1fb5 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_PLG : Command PLG (no credit-only PLG). In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/ reflected command or snoop/combined responses.
+event:0x1fb6 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_A_Transfer : Type A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs).
+event:0x1fb7 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_B_Transfer : Type B data transfer.
+event:0x1fb8 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Cmd_Credit_Only_PLG : Command-credit-only command PLG in either IOIF or BIF mode.
+event:0x1fb9 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Data_Credit_Only_PLG : Data-credit-only data PLG sent in either IOIF or BIF mode.
+event:0x1fba counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Non-Null_Envelopes : Non-null envelope sent (does not include long envelopes).
+event:0x1fbc counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:null_env_sent : Null envelope sent (see Note 1).
+event:0x1fbd counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:no_valid_data : No valid data sent this cycle (see Note 1).
+event:0x1fbe counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:norm_env_sent : Normal envelope sent (see Note 1).
+event:0x1fbf counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:lnog_env_sent : Long envelope sent (see Note 1).
+event:0x1fc0 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:per_mon_null_sent : A Null PLG inserted in an outgoing envelope.
+event:0x1fc1 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:per_mon_array_full : Outbound envelope array is full.
+
+# CBE Signal Group 82 - BIF Controller - IOIF1 Word 0 (NClk/2)
+event:0x201b counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_B_Transfer : Type B data transfer.
+
+
+# CBE Signal Group 83 - BIF Controller - IOIF0 Word 2 (NClk/2)
+event:0x206d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:null_env_rcvd : Null envelope received (see Note 1).
+event:0x207a counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_PLG : Command PLG, but not credit-only PLG. In IOIF mode, counts I/O command or reply PLGs. In BIF mode, counts command/reflected command or snoop/combined responses.
+event:0x207b counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_Credit_Only_PLG : Command-credit-only command PLG.
+event:0x2080 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:norm_env_rcvd_good : Normal envelope received is good (see Note 1).
+event:0x2081 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:long_env_rcvd_good : Long envelope received is good (see Note 1).
+event:0x2082 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:cmd_credit_only_PLG : Data-credit-only data PLG in either IOIF or BIF mode; will count a maximum of one per envelope (see Note 1).
+event:0x2083 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:non-null_envelope : Non-null envelope; does not include long envelopes; includes retried envelopes (see Note 1).
+event:0x2084 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:data_grnt_rcvd : Data grant received.
+event:0x2088 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Data_PLG : Data PLG. Does not include header-only or credit-only PLGs.
+event:0x2089 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_A_transfer : Type A data transfer regardless of length. Can also be used to count Type A data header PLGs, but not credit-only PLGs.
+event:0x208a counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_B_transfer : Type B data transfer.
+
+# CBE Signal Group 84 - BIF Controller - IOIF1 Word 2 (NClk/2)
+event:0x20d1 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:null_env_rcvd : Null envelope received (see Note 1).
+event:0x20de counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_PLG : Command PLG (no credit-only PLG). Counts I/O command or reply PLGs.
+event:0x20df counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Command_Credit_Only_PLG : Command-credit-only command PLG.
+event:0x20e4 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:norm_env_rcvd_good : Normal envelope received is good (see Note 1).
+event:0x20e5 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:long_env_rcvd_good : Long envelope received is good (see Note 1).
+event:0x20e6 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:cmd_credit_only_PLG : Data-credit-only data PLG received; will count a maximum of one per envelope (see Note 1).
+event:0x20e7 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:non-null_envelope : Non-Null envelope received; does not include long envelopes; includes retried envelopes (see Note 1).
+event:0x20e8 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:data_grnt_rcvd : Data grant received.
+event:0x20ec counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Data_PLG : Data PLG received. Does not include header-only or credit-only PLGs.
+event:0x20ed counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_A_transfer : Type I A data transfer regardless of length. Can also be used to count Type A data header PLGs (but not credit-only PLGs).
+event:0x20ee counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:Type_B_transfer : Type B data transfer received.
+
+# CBE Signal Group 85 - I/O Controller Word 0 - Group 1 (NClk/2)
+event:0x213c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:mmio_rd_to_ioif1 : Received MMIO read targeted to IOIF1.
+event:0x213d counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:mmio_wrt_to_ioif1 : Received MMIO write targeted to IOIF1.
+event:0x213e counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:mmio_rd_to_ioif0 : Received MMIO read targeted to IOIF0.
+event:0x213f counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:mmio_wrt_to_ioif0 : Received MMIO write targeted to IOIF0.
+event:0x2140 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:cmd_to_slice0 : Sent command to IOIF0.
+event:0x2141 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:cmd_to_slice1 : Sent command to IOIF1.
+
+# CBE Signal Group 86 - I/O Controller Word 2 - Group 2 (NClk/2)
+event:0x219d counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:re_dep_dm3 : IOIF0 Dependency Matrix 3 is occupied by a dependent command (see Note 1).
+event:0x219e counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:re_dep_dm4 : IOIF0 Dependency Matrix 4 is occupied by a dependent command (see Note 1).
+event:0x219f counters:0,1,2,3 um:PPU_02_cycles_or_edges minimum:10000 name:re_dep_dm5 : IOIF0 Dependency Matrix 5 is occupied by a dependent command (see Note 1).
+event:0x21a2 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:slice0_ld_rqst : Received read request from IOIF0.
+event:0x21a3 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:slice0_str_rqst : Received write request from IOIF0.
+event:0x21a6 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:intrpt_from_realizer : Received interrupt from the IOIF0.
+
+# CBE Signal Group 87 - I/O Controller - Group 3 (NClk/2)
+event:0x220c counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn_even : IOIF0 request for token for even memory banks 0-14 (see Note 1).
+event:0x220d counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn_odd : IOIF0 request for token for odd memory banks 1-15 (see Note 1).
+event:0x220e counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn1_3_5_7 : IOIF0 request for token type 1, 3, 5, or 7 (see Note 1).
+event:0x220f counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn9_11_13_15 : IOIF0 request for token type 9, 11, 13, or 15 (see Note 1).
+event:0x2214 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn16 : IOIF0 request for token type 16 (see Note 1).
+event:0x2215 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn17 : IOIF0 request for token type 17 (see Note 1).
+event:0x2216 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn18 : IOIF0 request for token type 18 (see Note 1).
+event:0x2217 counters:0,1,2,3 um:PPU_02_cycles minimum:10000 name:slice0_rqst_tkn19 : IOIF0 request for token type 19 (see Note 1).
+
+
+# CBE Signal Group 88 - I/O Controller Word 0 - Group 4 (NClk/2)
+event:0x2260 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:io_pt_hit : I/O page table cache hit for commands from IOIF.
+event:0x2261 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:io_pt_miss : I/O page table cache miss for commands from IOIF.
+event:0x2263 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:io_seg_tbl_hit : I/O segment table cache hit.
+event:0x2264 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:io_seg_tbl_miss : I/O segment table cache miss.
+event:0x2278 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:intrrpt_frm_spu : Interrupt received from any SPU (reflected cmd when IIC has sent ACK response).
+event:0x2279 counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:iic_intrrpt_to_pu_thrd0 : Internal interrupt controller (IIC) generated interrupt to PPU thread 0.
+event:0x227a counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:iic_intrrpt_to_pu_thrd1 : IIC generated interrupt to PPU thread 1.
+event:0x227b counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:pu_intrrpt_to_pu_thrd0 : Received external interrupt (using MMIO) from PPU to PPU thread 0.
+event:0x227c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:pu_intrrpt_to_pu_thrd1 : Received external interrupt (using MMIO) from PPU to PPU thread 1.
+event:0x227c counters:0,1,2,3 um:PPU_02_edges minimum:10000 name:pu_intrrpt_to_pu_thrd1 : Received external interrupt (using MMIO) from PPU to PPU thread 1.
diff --git a/events/ppc64/cell-be/unit_masks b/events/ppc64/cell-be/unit_masks
new file mode 100644
index 0000000..64a4959
--- /dev/null
+++ b/events/ppc64/cell-be/unit_masks
@@ -0,0 +1,137 @@
+# Cell Broadband Engine possible unit masks
+#
+# Copyright OProfile authors
+#
+#(C) COPYRIGHT International Business Machines Corp. 2006
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>
+#
+#
+name:zero type:mandatory default:0x0
+ 0x000 Count cycles [mandatory]
+name:PPU_0_cycles type:bitmask default:0x013
+ 0x001 Count cycles [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x010 PPU Bus Word 0 [mandatory]
+name:PPU_0_edges type:bitmask default:0x012
+ 0x000 Count edges [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x010 PPU Bus Word 0 [mandatory]
+name:PPU_2_cycles type:bitmask default:0x043
+ 0x001 Count cycles [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x040 PPU Bus Word 2 [mandatory]
+name:PPU_2_edges type:bitmask default:0x042
+ 0x000 Count edges [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x040 PPU Bus Word 2 [mandatory]
+name:PPU_01_cycles type:bitmask default:0x023
+ 0x001 Count cycles [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x010 PPU Bus Word 0 [optional ]
+ 0x020 PPU Bus Word 1 [default ]
+name:PPU_01_edges type:bitmask default:0x022
+ 0x000 Count edges [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x010 PPU Bus Word 0 [optional ]
+ 0x020 PPU Bus Word 1 [default ]
+name:PPU_01_cycles_or_edges type:bitmask default:0x023
+ 0x000 Count edges [optional ]
+ 0x001 Count cycles [default ]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x010 PPU Bus Word 0 [optional ]
+ 0x020 PPU Bus Word 1 [default ]
+name:PPU_02_cycles type:bitmask default:0x013
+ 0x001 Count cycles [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x010 PPU Bus Word 0 [default ]
+ 0x040 PPU Bus Word 2 [optional ]
+name:PPU_02_edges type:bitmask default:0x012
+ 0x000 Count edges [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x010 PPU Bus Word 0 [default ]
+ 0x040 PPU Bus Word 2 [optional ]
+name:PPU_02_cycles_or_edges type:bitmask default:0x013
+ 0x000 Count edges [optional ]
+ 0x001 Count cycles [default ]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x010 PPU Bus Word 0 [default ]
+ 0x040 PPU Bus Word 2 [optional ]
+name:PPU_0123_cycles type:bitmask default:0x033
+ 0x001 Count cycles [mandatory]
+ 0x000 Negative polarity [optional ]
+ 0x002 Positive polarity [default ]
+ 0x030 PPU Bus Word 0/1 [default ]
+ 0x0c0 PPU Bus Word 2/3 [optional ]
+name:SPU_02_cycles type:bitmask default:0x0113
+ 0x0001 Count cycles [mandatory]
+ 0x0000 Negative polarity [optional ]
+ 0x0002 Positive polarity [default ]
+ 0x0110 SPU Bus Word 0 [default ]
+ 0x0140 SPU Bus Word 2 [optional ]
+ 0x0000 SPU 0 [default ]
+ 0x1000 SPU 1 [optional ]
+ 0x2000 SPU 2 [optional ]
+ 0x3000 SPU 3 [optional ]
+ 0x4000 SPU 4 [optional ]
+ 0x5000 SPU 5 [optional ]
+ 0x6000 SPU 6 [optional ]
+ 0x7000 SPU 7 [optional ]
+name:SPU_02_cycles_or_edges type:bitmask default:0x0113
+ 0x0000 Count edges [optional ]
+ 0x0001 Count cycles [default ]
+ 0x0000 Negative polarity [optional ]
+ 0x0002 Positive polarity [default ]
+ 0x0110 SPU Bus Word 0 [default ]
+ 0x0140 SPU Bus Word 2 [optional ]
+ 0x0000 SPU 0 [default ]
+ 0x1000 SPU 1 [optional ]
+ 0x2000 SPU 2 [optional ]
+ 0x3000 SPU 3 [optional ]
+ 0x4000 SPU 4 [optional ]
+ 0x5000 SPU 5 [optional ]
+ 0x6000 SPU 6 [optional ]
+ 0x7000 SPU 7 [optional ]
+name:SPU_Trigger_cycles_or_edges type:bitmask default:0x0107
+ 0x0000 Count edges [optional ]
+ 0x0001 Count cycles [default ]
+ 0x0000 Negative polarity [optional ]
+ 0x0002 Positive polarity [default ]
+ 0x0104 SPU Trigger 0 [default ]
+ 0x0114 SPU Trigger 1 [optional ]
+ 0x0124 SPU Trigger 2 [optional ]
+ 0x0134 SPU Trigger 3 [optional ]
+ 0x0000 SPU 0 [default ]
+ 0x1000 SPU 1 [optional ]
+ 0x2000 SPU 2 [optional ]
+ 0x3000 SPU 3 [optional ]
+ 0x4000 SPU 4 [optional ]
+ 0x5000 SPU 5 [optional ]
+ 0x6000 SPU 6 [optional ]
+ 0x7000 SPU 7 [optional ]
+name:SPU_Event_cycles_or_edges type:bitmask default:0x0147
+ 0x0000 Count edges [optional ]
+ 0x0001 Count cycles [default ]
+ 0x0000 Negative polarity [optional ]
+ 0x0002 Positive polarity [default ]
+ 0x0144 SPU Event 0 [default ]
+ 0x0154 SPU Event 1 [optional ]
+ 0x0164 SPU Event 2 [optional ]
+ 0x0174 SPU Event 3 [optional ]
+ 0x0000 SPU 0 [default ]
+ 0x1000 SPU 1 [optional ]
+ 0x2000 SPU 2 [optional ]
+ 0x3000 SPU 3 [optional ]
+ 0x4000 SPU 4 [optional ]
+ 0x5000 SPU 5 [optional ]
+ 0x6000 SPU 6 [optional ]
+ 0x7000 SPU 7 [optional ]
diff --git a/events/ppc64/ibm-compat-v1/event_mappings b/events/ppc64/ibm-compat-v1/event_mappings
new file mode 100644
index 0000000..5805604
--- /dev/null
+++ b/events/ppc64/ibm-compat-v1/event_mappings
@@ -0,0 +1,82 @@
+#PPC64 pmu-compat event mappings, version 1
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2009.
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>.
+#
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+
+#Group 1 pm_compat_utilization1, Basic CPU utilization
+event:0X0010 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+event:0X0011 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+event:0X0012 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+event:0X0013 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+
+#Group 2 pm_compat_utilization2, CPI and utilization data
+event:0X0020 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+event:0X0021 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+event:0X0022 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+event:0X0023 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+
+#Group 3 pm_compat_dsource, Data Access sources
+event:0X0030 mmcr0:0X00000000 mmcr1:0X00000000FEFEFEFA mmcra:0X00000000
+event:0X0031 mmcr0:0X00000000 mmcr1:0X00000000FEFEFEFA mmcra:0X00000000
+event:0X0032 mmcr0:0X00000000 mmcr1:0X00000000FEFEFEFA mmcra:0X00000000
+event:0X0033 mmcr0:0X00000000 mmcr1:0X00000000FEFEFEFA mmcra:0X00000000
+
+#Group 4 pm_compat_l1_dcache_load_store_miss, L1 D-Cache load/store miss
+event:0X0040 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+event:0X0041 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+event:0X0042 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+event:0X0043 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+
+#Group 5 pm_compat_l1_cache_load, L1 Cache loads
+event:0X0050 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+event:0X0051 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+event:0X0052 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+event:0X0053 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+
+#Group 6 pm_compat_instruction_directory, Instruction Directory
+event:0X0060 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+event:0X0061 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+event:0X0062 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+event:0X0063 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+
+#Group 7 pm_compat_data_directory, Data Directory
+event:0X0070 mmcr0:0X00000000 mmcr1:0X00000000FCF6FCFA mmcra:0X00000000
+event:0X0071 mmcr0:0X00000000 mmcr1:0X00000000FCF6FCFA mmcra:0X00000000
+event:0X0072 mmcr0:0X00000000 mmcr1:0X00000000FCF6FCFA mmcra:0X00000000
+event:0X0073 mmcr0:0X00000000 mmcr1:0X00000000FCF6FCFA mmcra:0X00000000
+
+#Group 8 pm_compat_cpi_1plus_ppc, Misc CPI and utilization data
+event:0X0080 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+event:0X0081 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+event:0X0082 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+event:0X0083 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+
+#Group 9 pm_compat_misc_events1, Misc Events
+event:0X0090 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+event:0X0091 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+event:0X0092 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+event:0X0093 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+
+#Group 10 pm_compat_misc_events2, Misc Events
+event:0X00A0 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+event:0X00A1 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+event:0X00A2 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+event:0X00A3 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+
+#Group 11 pm_compat_misc_events3, Misc Events
+event:0X00B0 mmcr0:0X00000000 mmcr1:0X00000000F8F2F8F6 mmcra:0X00000000
+event:0X00B1 mmcr0:0X00000000 mmcr1:0X00000000F8F2F8F6 mmcra:0X00000000
+event:0X00B2 mmcr0:0X00000000 mmcr1:0X00000000F8F2F8F6 mmcra:0X00000000
+event:0X00B3 mmcr0:0X00000000 mmcr1:0X00000000F8F2F8F6 mmcra:0X00000000
+
+#Group 12 pm_compat_suspend, Suspend Events
+event:0X00C0 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+event:0X00C1 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+event:0X00C2 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+event:0X00C3 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
diff --git a/events/ppc64/ibm-compat-v1/events b/events/ppc64/ibm-compat-v1/events
new file mode 100644
index 0000000..9d5e9c6
--- /dev/null
+++ b/events/ppc64/ibm-compat-v1/events
@@ -0,0 +1,91 @@
+#PPC64 pmu-compat events, version 1
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2009.
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>.
+#
+#
+# Within each group, the event names must be unique. Each event in a group is
+# assigned to a unique counter.
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:2 um:zero minimum:10000 name:CYCLES : Processor Cycles
+
+
+#Group 1 pm_compat_utilization1, Basic CPU utilization
+event:0X0010 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP1 : (Group 1 pm_compat_utilization1) At least one thread in run cycles
+event:0X0011 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_compat_utilization1) Run cycles
+event:0X0012 counters:2 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_compat_utilization1) Processor cycles
+event:0X0013 counters:3 um:zero minimum:1000 name:PM_RUN_PURR_GRP1 : (Group 1 pm_compat_utilization1) Run PURR Even
+
+#Group 2 pm_compat_utilization2, CPI and utilization data
+event:0X0020 counters:0 um:zero minimum:1000 name:PM_FPU_FLOP_GRP2 : (Group 2 pm_compat_utilization2) FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
+event:0X0021 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_compat_utilization2) Run cycles
+event:0X0022 counters:2 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_compat_utilization2) Processor cycles
+event:0X0023 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP2 : (Group 2 pm_compat_utilization2) Run instructions completed
+
+#Group 3 pm_compat_dsource, Data Access sources
+event:0X0030 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L1-5_GRP3 : (Group 3 pm_compat_dsource) Data loaded from L1.5
+event:0X0031 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP3 : (Group 3 pm_compat_dsource) Data loaded missed L2
+event:0X0032 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP3 : (Group 3 pm_compat_dsource) Data loaded from private L3 miss
+event:0X0033 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP3 : (Group 3 pm_compat_dsource) Run instructions completed
+
+#Group 4 pm_compat_l1_dcache_load_store_miss, L1 D-Cache load/store miss
+event:0X0040 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) Instruction completed
+event:0X0041 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) Store instructions finished
+event:0X0042 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) L1 D cache store misses
+event:0X0043 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP4 : (Group 4 pm_compat_l1_dcache_load_store_miss) L1 D cache load misses
+
+#Group 5 pm_compat_l1_cache_load, L1 Cache loads
+event:0X0050 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP5 : (Group 5 pm_compat_l1_cache_load) Instruction completed
+event:0X0051 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP5 : (Group 5 pm_compat_l1_cache_load) Data loaded missed L2
+event:0X0052 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP5 : (Group 5 pm_compat_l1_cache_load) L1 reload data source valid
+event:0X0053 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP5 : (Group 5 pm_compat_l1_cache_load) L1 D cache load misses
+
+#Group 6 pm_compat_instruction_directory, Instruction Directory
+event:0X0060 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP6 : (Group 6 pm_compat_instruction_directory) IERAT miss coun
+event:0X0061 counters:1 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP6 : (Group 6 pm_compat_instruction_directory) L1 I cache miss coun
+event:0X0062 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP6 : (Group 6 pm_compat_instruction_directory) Instruction completed
+event:0X0063 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP6 : (Group 6 pm_compat_instruction_directory) Instruction TLB misses
+
+#Group 7 pm_compat_data_directory, Data Directory
+event:0X0070 counters:0 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_CYC_GRP7 : (Group 7 pm_compat_data_directory) DERAT miss latency
+event:0X0071 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP7 : (Group 7 pm_compat_data_directory) DERAT misses
+event:0X0072 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP7 : (Group 7 pm_compat_data_directory) Data TLB misses
+event:0X0073 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP7 : (Group 7 pm_compat_data_directory) Run instructions completed
+
+#Group 8 pm_compat_cpi_1plus_ppc, Misc CPI and utilization data
+event:0X0080 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP8 : (Group 8 pm_compat_cpi_1plus_ppc) One or more PPC instruction completed
+event:0X0081 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP8 : (Group 8 pm_compat_cpi_1plus_ppc) Run cycles
+event:0X0082 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP8 : (Group 8 pm_compat_cpi_1plus_ppc) Instructions dispatched
+event:0X0083 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP8 : (Group 8 pm_compat_cpi_1plus_ppc) Cycles at least one instruction dispatched
+
+#Group 9 pm_compat_misc_events1, Misc Events
+event:0X0090 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP9 : (Group 9 pm_compat_misc_events1) Instruction completed
+event:0X0091 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP9 : (Group 9 pm_compat_misc_events1) External interrupts
+event:0X0092 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP9 : (Group 9 pm_compat_misc_events1) Time Base bit transition
+event:0X0093 counters:3 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_compat_misc_events1) Processor cycles
+
+#Group 10 pm_compat_misc_events2, Misc Events
+event:0X00A0 counters:0 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP10 : (Group 10 pm_compat_misc_events2) IMC matched instructions completed
+event:0X00A1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP10 : (Group 10 pm_compat_misc_events2) Instructions dispatched
+event:0X00A2 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP10 : (Group 10 pm_compat_misc_events2) Concurrent run instructions
+event:0X00A3 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP10 : (Group 10 pm_compat_misc_events2) Flushes
+
+#Group 11 pm_compat_misc_events3, Misc Events
+event:0X00B0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP11 : (Group 11 pm_compat_misc_events3) Cycles GCT empty
+event:0X00B1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP11 : (Group 11 pm_compat_misc_events3) Instructions dispatched
+event:0X00B2 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP11 : (Group 11 pm_compat_misc_events3) Time Base bit transition
+event:0X00B3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP11 : (Group 11 pm_compat_misc_events3) Branches incorrectly predicted
+
+#Group 12 pm_compat_suspend, Suspend Events
+event:0X00C0 counters:0 um:zero minimum:1000 name:PM_SUSPENDED_GRP12 : (Group 12 pm_compat_suspend) Suspended
+event:0X00C1 counters:1 um:zero minimum:1000 name:PM_SUSPENDED_GRP12 : (Group 12 pm_compat_suspend) Suspended
+event:0X00C2 counters:2 um:zero minimum:1000 name:PM_SUSPENDED_GRP12 : (Group 12 pm_compat_suspend) Suspended
+event:0X00C3 counters:3 um:zero minimum:1000 name:PM_SUSPENDED_GRP12 : (Group 12 pm_compat_suspend) Suspended
diff --git a/events/ppc64/ibm-compat-v1/unit_masks b/events/ppc64/ibm-compat-v1/unit_masks
new file mode 100644
index 0000000..170c53b
--- /dev/null
+++ b/events/ppc64/ibm-compat-v1/unit_masks
@@ -0,0 +1,9 @@
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2009.
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>.
+#
+# ppc64 compat mode version 1 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/pa6t/event_mappings b/events/ppc64/pa6t/event_mappings
new file mode 100644
index 0000000..0bbddcb
--- /dev/null
+++ b/events/ppc64/pa6t/event_mappings
@@ -0,0 +1,48 @@
+# pa6t does not have an mmcra. mmcr0 has all the enables and config
+# bits. mmcr1 contains the event selectors for the four programmable
+# events
+
+# Group Default
+event:0x1 mmcr0:0x000000000005b81b mmcr1:0x0000000000949f00 mmcra:0x0
+event:0x3 mmcr0:0x000000000005b81b mmcr1:0x0000000000949f00 mmcra:0x0
+event:0x4 mmcr0:0x000000000005b81b mmcr1:0x0000000000949f00 mmcra:0x0
+
+# Group 1, Load/Store
+event:0x10 mmcr0:0x000000000007f83f mmcr1:0x00000000a8c0cab1 mmcra:0x0
+event:0x11 mmcr0:0x000000000007f83f mmcr1:0x00000000a8c0cab1 mmcra:0x0
+event:0x12 mmcr0:0x000000000007f83f mmcr1:0x00000000a8c0cab1 mmcra:0x0
+event:0x13 mmcr0:0x000000000007f83f mmcr1:0x00000000a8c0cab1 mmcra:0x0
+event:0x14 mmcr0:0x000000000007f83f mmcr1:0x00000000a8c0cab1 mmcra:0x0
+event:0x15 mmcr0:0x000000000007f83f mmcr1:0x00000000a8c0cab1 mmcra:0x0
+
+# Group 2, Frontend
+event:0x20 mmcr0:0x000000000007f83f mmcr1:0x0000000002058401 mmcra:0x0
+event:0x21 mmcr0:0x000000000007f83f mmcr1:0x0000000002058401 mmcra:0x0
+event:0x22 mmcr0:0x000000000007f83f mmcr1:0x0000000002058401 mmcra:0x0
+event:0x23 mmcr0:0x000000000007f83f mmcr1:0x0000000002058401 mmcra:0x0
+event:0x24 mmcr0:0x000000000007f83f mmcr1:0x0000000002058401 mmcra:0x0
+event:0x25 mmcr0:0x000000000007f83f mmcr1:0x0000000002058401 mmcra:0x0
+
+# Group 3, Branches
+event:0x30 mmcr0:0x000000000007f83f mmcr1:0x000000008d8b8988 mmcra:0x0
+event:0x31 mmcr0:0x000000000007f83f mmcr1:0x000000008d8b8988 mmcra:0x0
+event:0x32 mmcr0:0x000000000007f83f mmcr1:0x000000008d8b8988 mmcra:0x0
+event:0x33 mmcr0:0x000000000007f83f mmcr1:0x000000008d8b8988 mmcra:0x0
+event:0x34 mmcr0:0x000000000007f83f mmcr1:0x000000008d8b8988 mmcra:0x0
+event:0x35 mmcr0:0x000000000007f83f mmcr1:0x000000008d8b8988 mmcra:0x0
+
+# Group 4, Translation
+event:0x40 mmcr0:0x000000000007f83f mmcr1:0x0000000086baa7a8 mmcra:0x0
+event:0x41 mmcr0:0x000000000007f83f mmcr1:0x0000000086baa7a8 mmcra:0x0
+event:0x42 mmcr0:0x000000000007f83f mmcr1:0x0000000086baa7a8 mmcra:0x0
+event:0x43 mmcr0:0x000000000007f83f mmcr1:0x0000000086baa7a8 mmcra:0x0
+event:0x44 mmcr0:0x000000000007f83f mmcr1:0x0000000086baa7a8 mmcra:0x0
+event:0x45 mmcr0:0x000000000007f83f mmcr1:0x0000000086baa7a8 mmcra:0x0
+
+# Group 5, Memory
+event:0x50 mmcr0:0x000000000007f83f mmcr1:0x00000000c030cab1 mmcra:0x0
+event:0x51 mmcr0:0x000000000007f83f mmcr1:0x00000000c030cab1 mmcra:0x0
+event:0x52 mmcr0:0x000000000007f83f mmcr1:0x00000000c030cab1 mmcra:0x0
+event:0x53 mmcr0:0x000000000007f83f mmcr1:0x00000000c030cab1 mmcra:0x0
+event:0x54 mmcr0:0x000000000007f83f mmcr1:0x00000000c030cab1 mmcra:0x0
+event:0x55 mmcr0:0x000000000007f83f mmcr1:0x00000000c030cab1 mmcra:0x0
diff --git a/events/ppc64/pa6t/events b/events/ppc64/pa6t/events
new file mode 100644
index 0000000..5e2bc2f
--- /dev/null
+++ b/events/ppc64/pa6t/events
@@ -0,0 +1,52 @@
+# ppc64 pa6t events
+#
+# Unlike the IBM ppc64 chips, any of pa6t's events can be programmed into any
+# of the counters (pmc2-5). The notion of groups on pa6t is thus
+# artificial. That said, we can still define useful aggregations to guide the
+# user in his choice of group for a profiling session.
+
+# Group Default
+event:0x1 counters:0 um:zero minimum:10000 name:CYCLES : Processor Cycles
+event:0x3 counters:3 um:zero minimum:10000 name:ISS_CYCLES : Processor Cycles with instructions issued
+event:0x4 counters:4 um:zero minimum:10000 name:RET_UOP : Retired Micro-operatioins
+
+# Group 1, Load/Store
+event:0x10 counters:0 um:zero minimum:10000 name:GRP1_CYCLES : Processor Cycles
+event:0x11 counters:1 um:zero minimum:10000 name:GRP1_INST_RETIRED : Instructions retired
+event:0x12 counters:2 um:zero minimum:1000 name:GRP1_DCACHE_RD_MISS__NS : Dcache read misses NS
+event:0x13 counters:3 um:zero minimum:500 name:GRP1_MRB_LD_MISS_L2__NS : Load misses filling from memory
+event:0x14 counters:4 um:zero minimum:500 name:GRP1_MRB_ST_MISS_ALLOC__NS : Store misses in L1D and allocates an MRB entry
+event:0x15 counters:5 um:zero minimum:500 name:GRP1_TLB_MISS_D__NS : TLB misses NS (D- only)
+
+# Group 2, Frontend
+event:0x20 counters:0 um:zero minimum:10000 name:GRP2_CYCLES : Processor Cycles
+event:0x21 counters:1 um:zero minimum:10000 name:GRP2_INST_RETIRED : Instructions retired
+event:0x22 counters:2 um:zero minimum:2000 name:GRP2_FETCH_REQ : Demand fetch requests made to the Icache
+event:0x23 counters:3 um:zero minimum:500 name:GRP2_ICACHE_MISS_DEM__NS : Demand fetch requests missing in the Icache
+event:0x24 counters:4 um:zero minimum:500 name:GRP2_ICACHE_MISS_ALL : Demand and spec fetch requests missing in the Icache
+event:0x25 counters:5 um:zero minimum:2000 name:GRP2_ICACHE_ACC : Icache accesses
+
+# Group 3, Branches
+event:0x30 counters:0 um:zero minimum:10000 name:GRP3_CYCLES : Processor Cycles
+event:0x31 counters:1 um:zero minimum:10000 name:GRP3_INST_RETIRED : Instructions retired
+event:0x32 counters:2 um:zero minimum:500 name:GRP3_NXT_LINE_MISPRED__NS : Next fetch address mispredict
+event:0x33 counters:3 um:zero minimum:500 name:GRP3_DIRN_MISPRED__NS : Branch direction mispredict
+event:0x34 counters:4 um:zero minimum:500 name:GRP3_TGT_ADDR_MISPRED__NS : Branch target address mispredict
+event:0x35 counters:5 um:zero minimum:2000 name:GRP3_BRA_TAKEN__NS : Taken branches
+
+# Group 4, Translation
+event:0x40 counters:0 um:zero minimum:10000 name:GRP4_CYCLES : Processor Cycles
+event:0x41 counters:1 um:zero minimum:10000 name:GRP4_INST_RETIRED : Instructions retired
+event:0x42 counters:2 um:zero minimum:500 name:GRP4_TLB_MISS_D__NS : TLB Misses (D-)
+event:0x43 counters:3 um:zero minimum:500 name:GRP4_TLB_MISS_I__NS : TLB MIsses (I-)
+event:0x44 counters:4 um:zero minimum:500 name:GRP4_DERAT_MISS__NS : DERAT Misses
+event:0x45 counters:5 um:zero minimum:500 name:GRP4_IERAT_MISS__NS : IERAT Misses
+
+# Group 5, Memory
+event:0x50 counters:0 um:zero minimum:10000 name:GRP5_CYCLES : Processor Cycles
+event:0x51 counters:1 um:zero minimum:10000 name:GRP5_INST_RETIRED : Instructions retired
+event:0x52 counters:2 um:zero minimum:500 name:GRP5_DCACHE_RD_MISS__NS : Dcache read misses NS
+event:0x53 counters:3 um:zero minimum:500 name:GRP5_MRB_LD_MISS_L2__NS : Load misses filling from memory
+event:0x54 counters:4 um:zero minimum:500 name:GRP5_DCACHE_VIC : Dcache line evicted (snoops not included)
+event:0x55 counters:5 um:zero minimum:500 name:GRP5_MRB_ST_MISS_ALLOC__NS : Store misses in L1D and allocates an MRB entry
+
diff --git a/events/ppc64/pa6t/unit_masks b/events/ppc64/pa6t/unit_masks
new file mode 100644
index 0000000..ccc3ddd
--- /dev/null
+++ b/events/ppc64/pa6t/unit_masks
@@ -0,0 +1,4 @@
+# ppc64 pa6t possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/power4/event_mappings b/events/ppc64/power4/event_mappings
new file mode 100644
index 0000000..90caa05
--- /dev/null
+++ b/events/ppc64/power4/event_mappings
@@ -0,0 +1,634 @@
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+
+#Group 1 pm_slice0, Time Slice 0
+event:0X010 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+event:0X011 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+event:0X012 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+event:0X013 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+event:0X014 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+event:0X015 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+event:0X016 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+event:0X017 mmcr0:0X00000D0E mmcr1:0X000000004A5675AC mmcra:0X00022001
+
+#Group 2 pm_eprof, Group for use with eprof
+event:0X020 mmcr0:0X0000070E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X021 mmcr0:0X0000070E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X022 mmcr0:0X0000070E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X023 mmcr0:0X0000070E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X024 mmcr0:0X0000070E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X025 mmcr0:0X0000070E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X026 mmcr0:0X0000070E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X027 mmcr0:0X0000070E mmcr1:0X1003400045F29420 mmcra:0X00002001
+
+#Group 3 pm_basic, Basic performance indicators
+event:0X030 mmcr0:0X0000090E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X031 mmcr0:0X0000090E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X032 mmcr0:0X0000090E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X033 mmcr0:0X0000090E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X034 mmcr0:0X0000090E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X035 mmcr0:0X0000090E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X036 mmcr0:0X0000090E mmcr1:0X1003400045F29420 mmcra:0X00002001
+event:0X037 mmcr0:0X0000090E mmcr1:0X1003400045F29420 mmcra:0X00002001
+
+#Group 4 pm_ifu, IFU events
+event:0X040 mmcr0:0X00000938 mmcr1:0X80000000C6767D6C mmcra:0X00022001
+event:0X041 mmcr0:0X00000938 mmcr1:0X80000000C6767D6C mmcra:0X00022001
+event:0X042 mmcr0:0X00000938 mmcr1:0X80000000C6767D6C mmcra:0X00022001
+event:0X043 mmcr0:0X00000938 mmcr1:0X80000000C6767D6C mmcra:0X00022001
+event:0X044 mmcr0:0X00000938 mmcr1:0X80000000C6767D6C mmcra:0X00022001
+event:0X045 mmcr0:0X00000938 mmcr1:0X80000000C6767D6C mmcra:0X00022001
+event:0X046 mmcr0:0X00000938 mmcr1:0X80000000C6767D6C mmcra:0X00022001
+event:0X047 mmcr0:0X00000938 mmcr1:0X80000000C6767D6C mmcra:0X00022001
+
+#Group 5 pm_isu, ISU Queue full events
+event:0X050 mmcr0:0X0000112A mmcr1:0X50041000EA5103A0 mmcra:0X00002001
+event:0X051 mmcr0:0X0000112A mmcr1:0X50041000EA5103A0 mmcra:0X00002001
+event:0X052 mmcr0:0X0000112A mmcr1:0X50041000EA5103A0 mmcra:0X00002001
+event:0X053 mmcr0:0X0000112A mmcr1:0X50041000EA5103A0 mmcra:0X00002001
+event:0X054 mmcr0:0X0000112A mmcr1:0X50041000EA5103A0 mmcra:0X00002001
+event:0X055 mmcr0:0X0000112A mmcr1:0X50041000EA5103A0 mmcra:0X00002001
+event:0X056 mmcr0:0X0000112A mmcr1:0X50041000EA5103A0 mmcra:0X00002001
+event:0X057 mmcr0:0X0000112A mmcr1:0X50041000EA5103A0 mmcra:0X00002001
+
+#Group 6 pm_lsource, Information on data source
+event:0X060 mmcr0:0X00000E1C mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X061 mmcr0:0X00000E1C mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X062 mmcr0:0X00000E1C mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X063 mmcr0:0X00000E1C mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X064 mmcr0:0X00000E1C mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X065 mmcr0:0X00000E1C mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X066 mmcr0:0X00000E1C mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X067 mmcr0:0X00000E1C mmcr1:0X0010C000739CE738 mmcra:0X00002001
+
+#Group 7 pm_isource, Instruction Source information
+event:0X070 mmcr0:0X00000F1E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X071 mmcr0:0X00000F1E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X072 mmcr0:0X00000F1E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X073 mmcr0:0X00000F1E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X074 mmcr0:0X00000F1E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X075 mmcr0:0X00000F1E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X076 mmcr0:0X00000F1E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X077 mmcr0:0X00000F1E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+
+#Group 8 pm_lsu, Information on the Load Store Unit
+event:0X080 mmcr0:0X00000810 mmcr1:0X000F00003A508420 mmcra:0X00002001
+event:0X081 mmcr0:0X00000810 mmcr1:0X000F00003A508420 mmcra:0X00002001
+event:0X082 mmcr0:0X00000810 mmcr1:0X000F00003A508420 mmcra:0X00002001
+event:0X083 mmcr0:0X00000810 mmcr1:0X000F00003A508420 mmcra:0X00002001
+event:0X084 mmcr0:0X00000810 mmcr1:0X000F00003A508420 mmcra:0X00002001
+event:0X085 mmcr0:0X00000810 mmcr1:0X000F00003A508420 mmcra:0X00002001
+event:0X086 mmcr0:0X00000810 mmcr1:0X000F00003A508420 mmcra:0X00002001
+event:0X087 mmcr0:0X00000810 mmcr1:0X000F00003A508420 mmcra:0X00002001
+
+#Group 9 pm_xlate1, Translation Events
+event:0X090 mmcr0:0X00001028 mmcr1:0X81082000F67E849C mmcra:0X00022001
+event:0X091 mmcr0:0X00001028 mmcr1:0X81082000F67E849C mmcra:0X00022001
+event:0X092 mmcr0:0X00001028 mmcr1:0X81082000F67E849C mmcra:0X00022001
+event:0X093 mmcr0:0X00001028 mmcr1:0X81082000F67E849C mmcra:0X00022001
+event:0X094 mmcr0:0X00001028 mmcr1:0X81082000F67E849C mmcra:0X00022001
+event:0X095 mmcr0:0X00001028 mmcr1:0X81082000F67E849C mmcra:0X00022001
+event:0X096 mmcr0:0X00001028 mmcr1:0X81082000F67E849C mmcra:0X00022001
+event:0X097 mmcr0:0X00001028 mmcr1:0X81082000F67E849C mmcra:0X00022001
+
+#Group 10 pm_xlate2, Translation Events
+event:0X0A0 mmcr0:0X0000112A mmcr1:0X81082000D77E849C mmcra:0X00022001
+event:0X0A1 mmcr0:0X0000112A mmcr1:0X81082000D77E849C mmcra:0X00022001
+event:0X0A2 mmcr0:0X0000112A mmcr1:0X81082000D77E849C mmcra:0X00022001
+event:0X0A3 mmcr0:0X0000112A mmcr1:0X81082000D77E849C mmcra:0X00022001
+event:0X0A4 mmcr0:0X0000112A mmcr1:0X81082000D77E849C mmcra:0X00022001
+event:0X0A5 mmcr0:0X0000112A mmcr1:0X81082000D77E849C mmcra:0X00022001
+event:0X0A6 mmcr0:0X0000112A mmcr1:0X81082000D77E849C mmcra:0X00022001
+event:0X0A7 mmcr0:0X0000112A mmcr1:0X81082000D77E849C mmcra:0X00022001
+
+#Group 11 pm_gps1, L3 Events
+event:0X0B0 mmcr0:0X00001022 mmcr1:0X00000C00B5E5349C mmcra:0X00022001
+event:0X0B1 mmcr0:0X00001022 mmcr1:0X00000C00B5E5349C mmcra:0X00022001
+event:0X0B2 mmcr0:0X00001022 mmcr1:0X00000C00B5E5349C mmcra:0X00022001
+event:0X0B3 mmcr0:0X00001022 mmcr1:0X00000C00B5E5349C mmcra:0X00022001
+event:0X0B4 mmcr0:0X00001022 mmcr1:0X00000C00B5E5349C mmcra:0X00022001
+event:0X0B5 mmcr0:0X00001022 mmcr1:0X00000C00B5E5349C mmcra:0X00022001
+event:0X0B6 mmcr0:0X00001022 mmcr1:0X00000C00B5E5349C mmcra:0X00022001
+event:0X0B7 mmcr0:0X00001022 mmcr1:0X00000C00B5E5349C mmcra:0X00022001
+
+#Group 12 pm_l2a, L2 SliceA events
+event:0X0C0 mmcr0:0X0000162A mmcr1:0X00000C008469749C mmcra:0X00022001
+event:0X0C1 mmcr0:0X0000162A mmcr1:0X00000C008469749C mmcra:0X00022001
+event:0X0C2 mmcr0:0X0000162A mmcr1:0X00000C008469749C mmcra:0X00022001
+event:0X0C3 mmcr0:0X0000162A mmcr1:0X00000C008469749C mmcra:0X00022001
+event:0X0C4 mmcr0:0X0000162A mmcr1:0X00000C008469749C mmcra:0X00022001
+event:0X0C5 mmcr0:0X0000162A mmcr1:0X00000C008469749C mmcra:0X00022001
+event:0X0C6 mmcr0:0X0000162A mmcr1:0X00000C008469749C mmcra:0X00022001
+event:0X0C7 mmcr0:0X0000162A mmcr1:0X00000C008469749C mmcra:0X00022001
+
+#Group 13 pm_l2b, L2 SliceB events
+event:0X0D0 mmcr0:0X00001A32 mmcr1:0X0000060094F1B49C mmcra:0X00022001
+event:0X0D1 mmcr0:0X00001A32 mmcr1:0X0000060094F1B49C mmcra:0X00022001
+event:0X0D2 mmcr0:0X00001A32 mmcr1:0X0000060094F1B49C mmcra:0X00022001
+event:0X0D3 mmcr0:0X00001A32 mmcr1:0X0000060094F1B49C mmcra:0X00022001
+event:0X0D4 mmcr0:0X00001A32 mmcr1:0X0000060094F1B49C mmcra:0X00022001
+event:0X0D5 mmcr0:0X00001A32 mmcr1:0X0000060094F1B49C mmcra:0X00022001
+event:0X0D6 mmcr0:0X00001A32 mmcr1:0X0000060094F1B49C mmcra:0X00022001
+event:0X0D7 mmcr0:0X00001A32 mmcr1:0X0000060094F1B49C mmcra:0X00022001
+
+#Group 14 pm_l2c, L2 SliceC events
+event:0X0E0 mmcr0:0X00001E3A mmcr1:0X00000600A579F49C mmcra:0X00022001
+event:0X0E1 mmcr0:0X00001E3A mmcr1:0X00000600A579F49C mmcra:0X00022001
+event:0X0E2 mmcr0:0X00001E3A mmcr1:0X00000600A579F49C mmcra:0X00022001
+event:0X0E3 mmcr0:0X00001E3A mmcr1:0X00000600A579F49C mmcra:0X00022001
+event:0X0E4 mmcr0:0X00001E3A mmcr1:0X00000600A579F49C mmcra:0X00022001
+event:0X0E5 mmcr0:0X00001E3A mmcr1:0X00000600A579F49C mmcra:0X00022001
+event:0X0E6 mmcr0:0X00001E3A mmcr1:0X00000600A579F49C mmcra:0X00022001
+event:0X0E7 mmcr0:0X00001E3A mmcr1:0X00000600A579F49C mmcra:0X00022001
+
+#Group 15 pm_fpu1, Floating Point events
+event:0X0F0 mmcr0:0X00000810 mmcr1:0X00000000420E84A0 mmcra:0X00002001
+event:0X0F1 mmcr0:0X00000810 mmcr1:0X00000000420E84A0 mmcra:0X00002001
+event:0X0F2 mmcr0:0X00000810 mmcr1:0X00000000420E84A0 mmcra:0X00002001
+event:0X0F3 mmcr0:0X00000810 mmcr1:0X00000000420E84A0 mmcra:0X00002001
+event:0X0F4 mmcr0:0X00000810 mmcr1:0X00000000420E84A0 mmcra:0X00002001
+event:0X0F5 mmcr0:0X00000810 mmcr1:0X00000000420E84A0 mmcra:0X00002001
+event:0X0F6 mmcr0:0X00000810 mmcr1:0X00000000420E84A0 mmcra:0X00002001
+event:0X0F7 mmcr0:0X00000810 mmcr1:0X00000000420E84A0 mmcra:0X00002001
+
+#Group 16 pm_fpu2, Floating Point events
+event:0X100 mmcr0:0X00000810 mmcr1:0X010020E83A508420 mmcra:0X00002001
+event:0X101 mmcr0:0X00000810 mmcr1:0X010020E83A508420 mmcra:0X00002001
+event:0X102 mmcr0:0X00000810 mmcr1:0X010020E83A508420 mmcra:0X00002001
+event:0X103 mmcr0:0X00000810 mmcr1:0X010020E83A508420 mmcra:0X00002001
+event:0X104 mmcr0:0X00000810 mmcr1:0X010020E83A508420 mmcra:0X00002001
+event:0X105 mmcr0:0X00000810 mmcr1:0X010020E83A508420 mmcra:0X00002001
+event:0X106 mmcr0:0X00000810 mmcr1:0X010020E83A508420 mmcra:0X00002001
+event:0X107 mmcr0:0X00000810 mmcr1:0X010020E83A508420 mmcra:0X00002001
+
+#Group 17 pm_idu1, Instruction Decode Unit events
+event:0X110 mmcr0:0X0000090E mmcr1:0X040100008456794C mmcra:0X00022001
+event:0X111 mmcr0:0X0000090E mmcr1:0X040100008456794C mmcra:0X00022001
+event:0X112 mmcr0:0X0000090E mmcr1:0X040100008456794C mmcra:0X00022001
+event:0X113 mmcr0:0X0000090E mmcr1:0X040100008456794C mmcra:0X00022001
+event:0X114 mmcr0:0X0000090E mmcr1:0X040100008456794C mmcra:0X00022001
+event:0X115 mmcr0:0X0000090E mmcr1:0X040100008456794C mmcra:0X00022001
+event:0X116 mmcr0:0X0000090E mmcr1:0X040100008456794C mmcra:0X00022001
+event:0X117 mmcr0:0X0000090E mmcr1:0X040100008456794C mmcra:0X00022001
+
+#Group 18 pm_idu2, Instruction Decode Unit events
+event:0X120 mmcr0:0X0000090E mmcr1:0X04010000A5527B5C mmcra:0X00022001
+event:0X121 mmcr0:0X0000090E mmcr1:0X04010000A5527B5C mmcra:0X00022001
+event:0X122 mmcr0:0X0000090E mmcr1:0X04010000A5527B5C mmcra:0X00022001
+event:0X123 mmcr0:0X0000090E mmcr1:0X04010000A5527B5C mmcra:0X00022001
+event:0X124 mmcr0:0X0000090E mmcr1:0X04010000A5527B5C mmcra:0X00022001
+event:0X125 mmcr0:0X0000090E mmcr1:0X04010000A5527B5C mmcra:0X00022001
+event:0X126 mmcr0:0X0000090E mmcr1:0X04010000A5527B5C mmcra:0X00022001
+event:0X127 mmcr0:0X0000090E mmcr1:0X04010000A5527B5C mmcra:0X00022001
+
+#Group 19 pm_isu_rename, ISU Rename Pool Events
+event:0X130 mmcr0:0X00001228 mmcr1:0X100550008E6D949C mmcra:0X00022001
+event:0X131 mmcr0:0X00001228 mmcr1:0X100550008E6D949C mmcra:0X00022001
+event:0X132 mmcr0:0X00001228 mmcr1:0X100550008E6D949C mmcra:0X00022001
+event:0X133 mmcr0:0X00001228 mmcr1:0X100550008E6D949C mmcra:0X00022001
+event:0X134 mmcr0:0X00001228 mmcr1:0X100550008E6D949C mmcra:0X00022001
+event:0X135 mmcr0:0X00001228 mmcr1:0X100550008E6D949C mmcra:0X00022001
+event:0X136 mmcr0:0X00001228 mmcr1:0X100550008E6D949C mmcra:0X00022001
+event:0X137 mmcr0:0X00001228 mmcr1:0X100550008E6D949C mmcra:0X00022001
+
+#Group 20 pm_isu_queues1, ISU Queue Full Events
+event:0X140 mmcr0:0X0000132E mmcr1:0X10050000850E994C mmcra:0X00022001
+event:0X141 mmcr0:0X0000132E mmcr1:0X10050000850E994C mmcra:0X00022001
+event:0X142 mmcr0:0X0000132E mmcr1:0X10050000850E994C mmcra:0X00022001
+event:0X143 mmcr0:0X0000132E mmcr1:0X10050000850E994C mmcra:0X00022001
+event:0X144 mmcr0:0X0000132E mmcr1:0X10050000850E994C mmcra:0X00022001
+event:0X145 mmcr0:0X0000132E mmcr1:0X10050000850E994C mmcra:0X00022001
+event:0X146 mmcr0:0X0000132E mmcr1:0X10050000850E994C mmcra:0X00022001
+event:0X147 mmcr0:0X0000132E mmcr1:0X10050000850E994C mmcra:0X00022001
+
+#Group 21 pm_isu_flow, ISU Instruction Flow Events
+event:0X150 mmcr0:0X0000190E mmcr1:0X10005000D7B7C49C mmcra:0X00022001
+event:0X151 mmcr0:0X0000190E mmcr1:0X10005000D7B7C49C mmcra:0X00022001
+event:0X152 mmcr0:0X0000190E mmcr1:0X10005000D7B7C49C mmcra:0X00022001
+event:0X153 mmcr0:0X0000190E mmcr1:0X10005000D7B7C49C mmcra:0X00022001
+event:0X154 mmcr0:0X0000190E mmcr1:0X10005000D7B7C49C mmcra:0X00022001
+event:0X155 mmcr0:0X0000190E mmcr1:0X10005000D7B7C49C mmcra:0X00022001
+event:0X156 mmcr0:0X0000190E mmcr1:0X10005000D7B7C49C mmcra:0X00022001
+event:0X157 mmcr0:0X0000190E mmcr1:0X10005000D7B7C49C mmcra:0X00022001
+
+#Group 22 pm_isu_work, ISU Indicators of Work Blockage
+event:0X160 mmcr0:0X00000C12 mmcr1:0X100010004FCE9DA8 mmcra:0X00002001
+event:0X161 mmcr0:0X00000C12 mmcr1:0X100010004FCE9DA8 mmcra:0X00002001
+event:0X162 mmcr0:0X00000C12 mmcr1:0X100010004FCE9DA8 mmcra:0X00002001
+event:0X163 mmcr0:0X00000C12 mmcr1:0X100010004FCE9DA8 mmcra:0X00002001
+event:0X164 mmcr0:0X00000C12 mmcr1:0X100010004FCE9DA8 mmcra:0X00002001
+event:0X165 mmcr0:0X00000C12 mmcr1:0X100010004FCE9DA8 mmcra:0X00002001
+event:0X166 mmcr0:0X00000C12 mmcr1:0X100010004FCE9DA8 mmcra:0X00002001
+event:0X167 mmcr0:0X00000C12 mmcr1:0X100010004FCE9DA8 mmcra:0X00002001
+
+#Group 23 pm_serialize, LSU Serializing Events
+event:0X170 mmcr0:0X00001332 mmcr1:0X0118B000E9D69DFC mmcra:0X00022001
+event:0X171 mmcr0:0X00001332 mmcr1:0X0118B000E9D69DFC mmcra:0X00022001
+event:0X172 mmcr0:0X00001332 mmcr1:0X0118B000E9D69DFC mmcra:0X00022001
+event:0X173 mmcr0:0X00001332 mmcr1:0X0118B000E9D69DFC mmcra:0X00022001
+event:0X174 mmcr0:0X00001332 mmcr1:0X0118B000E9D69DFC mmcra:0X00022001
+event:0X175 mmcr0:0X00001332 mmcr1:0X0118B000E9D69DFC mmcra:0X00022001
+event:0X176 mmcr0:0X00001332 mmcr1:0X0118B000E9D69DFC mmcra:0X00022001
+event:0X177 mmcr0:0X00001332 mmcr1:0X0118B000E9D69DFC mmcra:0X00022001
+
+#Group 24 pm_lsubusy, LSU Busy Events
+event:0X180 mmcr0:0X0000193A mmcr1:0X0000F000DFF5E49C mmcra:0X00022001
+event:0X181 mmcr0:0X0000193A mmcr1:0X0000F000DFF5E49C mmcra:0X00022001
+event:0X182 mmcr0:0X0000193A mmcr1:0X0000F000DFF5E49C mmcra:0X00022001
+event:0X183 mmcr0:0X0000193A mmcr1:0X0000F000DFF5E49C mmcra:0X00022001
+event:0X184 mmcr0:0X0000193A mmcr1:0X0000F000DFF5E49C mmcra:0X00022001
+event:0X185 mmcr0:0X0000193A mmcr1:0X0000F000DFF5E49C mmcra:0X00022001
+event:0X186 mmcr0:0X0000193A mmcr1:0X0000F000DFF5E49C mmcra:0X00022001
+event:0X187 mmcr0:0X0000193A mmcr1:0X0000F000DFF5E49C mmcra:0X00022001
+
+#Group 25 pm_lsource2, Information on data source
+event:0X190 mmcr0:0X00000938 mmcr1:0X0010C0003B9CE738 mmcra:0X00002001
+event:0X191 mmcr0:0X00000938 mmcr1:0X0010C0003B9CE738 mmcra:0X00002001
+event:0X192 mmcr0:0X00000938 mmcr1:0X0010C0003B9CE738 mmcra:0X00002001
+event:0X193 mmcr0:0X00000938 mmcr1:0X0010C0003B9CE738 mmcra:0X00002001
+event:0X194 mmcr0:0X00000938 mmcr1:0X0010C0003B9CE738 mmcra:0X00002001
+event:0X195 mmcr0:0X00000938 mmcr1:0X0010C0003B9CE738 mmcra:0X00002001
+event:0X196 mmcr0:0X00000938 mmcr1:0X0010C0003B9CE738 mmcra:0X00002001
+event:0X197 mmcr0:0X00000938 mmcr1:0X0010C0003B9CE738 mmcra:0X00002001
+
+#Group 26 pm_lsource3, Information on data source
+event:0X1A0 mmcr0:0X00000E1C mmcr1:0X0010C00073B87724 mmcra:0X00022001
+event:0X1A1 mmcr0:0X00000E1C mmcr1:0X0010C00073B87724 mmcra:0X00022001
+event:0X1A2 mmcr0:0X00000E1C mmcr1:0X0010C00073B87724 mmcra:0X00022001
+event:0X1A3 mmcr0:0X00000E1C mmcr1:0X0010C00073B87724 mmcra:0X00022001
+event:0X1A4 mmcr0:0X00000E1C mmcr1:0X0010C00073B87724 mmcra:0X00022001
+event:0X1A5 mmcr0:0X00000E1C mmcr1:0X0010C00073B87724 mmcra:0X00022001
+event:0X1A6 mmcr0:0X00000E1C mmcr1:0X0010C00073B87724 mmcra:0X00022001
+event:0X1A7 mmcr0:0X00000E1C mmcr1:0X0010C00073B87724 mmcra:0X00022001
+
+#Group 27 pm_isource2, Instruction Source information
+event:0X1B0 mmcr0:0X0000090E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X1B1 mmcr0:0X0000090E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X1B2 mmcr0:0X0000090E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X1B3 mmcr0:0X0000090E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X1B4 mmcr0:0X0000090E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X1B5 mmcr0:0X0000090E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X1B6 mmcr0:0X0000090E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+event:0X1B7 mmcr0:0X0000090E mmcr1:0X800000007BDEF7BC mmcra:0X00022001
+
+#Group 28 pm_isource3, Instruction Source information
+event:0X1C0 mmcr0:0X00000F1E mmcr1:0X800000007BDEF3A4 mmcra:0X00022001
+event:0X1C1 mmcr0:0X00000F1E mmcr1:0X800000007BDEF3A4 mmcra:0X00022001
+event:0X1C2 mmcr0:0X00000F1E mmcr1:0X800000007BDEF3A4 mmcra:0X00022001
+event:0X1C3 mmcr0:0X00000F1E mmcr1:0X800000007BDEF3A4 mmcra:0X00022001
+event:0X1C4 mmcr0:0X00000F1E mmcr1:0X800000007BDEF3A4 mmcra:0X00022001
+event:0X1C5 mmcr0:0X00000F1E mmcr1:0X800000007BDEF3A4 mmcra:0X00022001
+event:0X1C6 mmcr0:0X00000F1E mmcr1:0X800000007BDEF3A4 mmcra:0X00022001
+event:0X1C7 mmcr0:0X00000F1E mmcr1:0X800000007BDEF3A4 mmcra:0X00022001
+
+#Group 29 pm_fpu3, Floating Point events by unit
+event:0X1D0 mmcr0:0X00001028 mmcr1:0X000000008D63549C mmcra:0X00022001
+event:0X1D1 mmcr0:0X00001028 mmcr1:0X000000008D63549C mmcra:0X00022001
+event:0X1D2 mmcr0:0X00001028 mmcr1:0X000000008D63549C mmcra:0X00022001
+event:0X1D3 mmcr0:0X00001028 mmcr1:0X000000008D63549C mmcra:0X00022001
+event:0X1D4 mmcr0:0X00001028 mmcr1:0X000000008D63549C mmcra:0X00022001
+event:0X1D5 mmcr0:0X00001028 mmcr1:0X000000008D63549C mmcra:0X00022001
+event:0X1D6 mmcr0:0X00001028 mmcr1:0X000000008D63549C mmcra:0X00022001
+event:0X1D7 mmcr0:0X00001028 mmcr1:0X000000008D63549C mmcra:0X00022001
+
+#Group 30 pm_fpu4, Floating Point events by unit
+event:0X1E0 mmcr0:0X0000122C mmcr1:0X000000009DE7749C mmcra:0X00022001
+event:0X1E1 mmcr0:0X0000122C mmcr1:0X000000009DE7749C mmcra:0X00022001
+event:0X1E2 mmcr0:0X0000122C mmcr1:0X000000009DE7749C mmcra:0X00022001
+event:0X1E3 mmcr0:0X0000122C mmcr1:0X000000009DE7749C mmcra:0X00022001
+event:0X1E4 mmcr0:0X0000122C mmcr1:0X000000009DE7749C mmcra:0X00022001
+event:0X1E5 mmcr0:0X0000122C mmcr1:0X000000009DE7749C mmcra:0X00022001
+event:0X1E6 mmcr0:0X0000122C mmcr1:0X000000009DE7749C mmcra:0X00022001
+event:0X1E7 mmcr0:0X0000122C mmcr1:0X000000009DE7749C mmcra:0X00022001
+
+#Group 31 pm_fpu5, Floating Point events by unit
+event:0X1F0 mmcr0:0X00001838 mmcr1:0X00000000850E9958 mmcra:0X00002001
+event:0X1F1 mmcr0:0X00001838 mmcr1:0X00000000850E9958 mmcra:0X00002001
+event:0X1F2 mmcr0:0X00001838 mmcr1:0X00000000850E9958 mmcra:0X00002001
+event:0X1F3 mmcr0:0X00001838 mmcr1:0X00000000850E9958 mmcra:0X00002001
+event:0X1F4 mmcr0:0X00001838 mmcr1:0X00000000850E9958 mmcra:0X00002001
+event:0X1F5 mmcr0:0X00001838 mmcr1:0X00000000850E9958 mmcra:0X00002001
+event:0X1F6 mmcr0:0X00001838 mmcr1:0X00000000850E9958 mmcra:0X00002001
+event:0X1F7 mmcr0:0X00001838 mmcr1:0X00000000850E9958 mmcra:0X00002001
+
+#Group 32 pm_fpu6, Floating Point events by unit
+event:0X200 mmcr0:0X00001B3E mmcr1:0X01002000C735E3A4 mmcra:0X00022001
+event:0X201 mmcr0:0X00001B3E mmcr1:0X01002000C735E3A4 mmcra:0X00022001
+event:0X202 mmcr0:0X00001B3E mmcr1:0X01002000C735E3A4 mmcra:0X00022001
+event:0X203 mmcr0:0X00001B3E mmcr1:0X01002000C735E3A4 mmcra:0X00022001
+event:0X204 mmcr0:0X00001B3E mmcr1:0X01002000C735E3A4 mmcra:0X00022001
+event:0X205 mmcr0:0X00001B3E mmcr1:0X01002000C735E3A4 mmcra:0X00022001
+event:0X206 mmcr0:0X00001B3E mmcr1:0X01002000C735E3A4 mmcra:0X00022001
+event:0X207 mmcr0:0X00001B3E mmcr1:0X01002000C735E3A4 mmcra:0X00022001
+
+#Group 33 pm_fpu7, Floating Point events by unit
+event:0X210 mmcr0:0X0000193A mmcr1:0X000000009DCE93E0 mmcra:0X00002001
+event:0X211 mmcr0:0X0000193A mmcr1:0X000000009DCE93E0 mmcra:0X00002001
+event:0X212 mmcr0:0X0000193A mmcr1:0X000000009DCE93E0 mmcra:0X00002001
+event:0X213 mmcr0:0X0000193A mmcr1:0X000000009DCE93E0 mmcra:0X00002001
+event:0X214 mmcr0:0X0000193A mmcr1:0X000000009DCE93E0 mmcra:0X00002001
+event:0X215 mmcr0:0X0000193A mmcr1:0X000000009DCE93E0 mmcra:0X00002001
+event:0X216 mmcr0:0X0000193A mmcr1:0X000000009DCE93E0 mmcra:0X00002001
+event:0X217 mmcr0:0X0000193A mmcr1:0X000000009DCE93E0 mmcra:0X00002001
+
+#Group 34 pm_fxu, Fix Point Unit events
+event:0X220 mmcr0:0X0000090E mmcr1:0X400000024294A520 mmcra:0X00002001
+event:0X221 mmcr0:0X0000090E mmcr1:0X400000024294A520 mmcra:0X00002001
+event:0X222 mmcr0:0X0000090E mmcr1:0X400000024294A520 mmcra:0X00002001
+event:0X223 mmcr0:0X0000090E mmcr1:0X400000024294A520 mmcra:0X00002001
+event:0X224 mmcr0:0X0000090E mmcr1:0X400000024294A520 mmcra:0X00002001
+event:0X225 mmcr0:0X0000090E mmcr1:0X400000024294A520 mmcra:0X00002001
+event:0X226 mmcr0:0X0000090E mmcr1:0X400000024294A520 mmcra:0X00002001
+event:0X227 mmcr0:0X0000090E mmcr1:0X400000024294A520 mmcra:0X00002001
+
+#Group 35 pm_lsu_lmq, LSU Load Miss Queue Events
+event:0X230 mmcr0:0X00001E3E mmcr1:0X0100A000EE4E9D78 mmcra:0X00002001
+event:0X231 mmcr0:0X00001E3E mmcr1:0X0100A000EE4E9D78 mmcra:0X00002001
+event:0X232 mmcr0:0X00001E3E mmcr1:0X0100A000EE4E9D78 mmcra:0X00002001
+event:0X233 mmcr0:0X00001E3E mmcr1:0X0100A000EE4E9D78 mmcra:0X00002001
+event:0X234 mmcr0:0X00001E3E mmcr1:0X0100A000EE4E9D78 mmcra:0X00002001
+event:0X235 mmcr0:0X00001E3E mmcr1:0X0100A000EE4E9D78 mmcra:0X00002001
+event:0X236 mmcr0:0X00001E3E mmcr1:0X0100A000EE4E9D78 mmcra:0X00002001
+event:0X237 mmcr0:0X00001E3E mmcr1:0X0100A000EE4E9D78 mmcra:0X00002001
+
+#Group 36 pm_lsu_flush, LSU Flush Events
+event:0X240 mmcr0:0X0000122C mmcr1:0X000C000039E7749C mmcra:0X00022001
+event:0X241 mmcr0:0X0000122C mmcr1:0X000C000039E7749C mmcra:0X00022001
+event:0X242 mmcr0:0X0000122C mmcr1:0X000C000039E7749C mmcra:0X00022001
+event:0X243 mmcr0:0X0000122C mmcr1:0X000C000039E7749C mmcra:0X00022001
+event:0X244 mmcr0:0X0000122C mmcr1:0X000C000039E7749C mmcra:0X00022001
+event:0X245 mmcr0:0X0000122C mmcr1:0X000C000039E7749C mmcra:0X00022001
+event:0X246 mmcr0:0X0000122C mmcr1:0X000C000039E7749C mmcra:0X00022001
+event:0X247 mmcr0:0X0000122C mmcr1:0X000C000039E7749C mmcra:0X00022001
+
+#Group 37 pm_lsu_load1, LSU Load Events
+event:0X250 mmcr0:0X00001028 mmcr1:0X000F0000850E9958 mmcra:0X00002001
+event:0X251 mmcr0:0X00001028 mmcr1:0X000F0000850E9958 mmcra:0X00002001
+event:0X252 mmcr0:0X00001028 mmcr1:0X000F0000850E9958 mmcra:0X00002001
+event:0X253 mmcr0:0X00001028 mmcr1:0X000F0000850E9958 mmcra:0X00002001
+event:0X254 mmcr0:0X00001028 mmcr1:0X000F0000850E9958 mmcra:0X00002001
+event:0X255 mmcr0:0X00001028 mmcr1:0X000F0000850E9958 mmcra:0X00002001
+event:0X256 mmcr0:0X00001028 mmcr1:0X000F0000850E9958 mmcra:0X00002001
+event:0X257 mmcr0:0X00001028 mmcr1:0X000F0000850E9958 mmcra:0X00002001
+
+#Group 38 pm_lsu_store1, LSU Store Events
+event:0X260 mmcr0:0X0000112A mmcr1:0X000F00008D4E99DC mmcra:0X00022001
+event:0X261 mmcr0:0X0000112A mmcr1:0X000F00008D4E99DC mmcra:0X00022001
+event:0X262 mmcr0:0X0000112A mmcr1:0X000F00008D4E99DC mmcra:0X00022001
+event:0X263 mmcr0:0X0000112A mmcr1:0X000F00008D4E99DC mmcra:0X00022001
+event:0X264 mmcr0:0X0000112A mmcr1:0X000F00008D4E99DC mmcra:0X00022001
+event:0X265 mmcr0:0X0000112A mmcr1:0X000F00008D4E99DC mmcra:0X00022001
+event:0X266 mmcr0:0X0000112A mmcr1:0X000F00008D4E99DC mmcra:0X00022001
+event:0X267 mmcr0:0X0000112A mmcr1:0X000F00008D4E99DC mmcra:0X00022001
+
+#Group 39 pm_lsu_store2, LSU Store Events
+event:0X270 mmcr0:0X00001838 mmcr1:0X0003C0008D76749C mmcra:0X00022001
+event:0X271 mmcr0:0X00001838 mmcr1:0X0003C0008D76749C mmcra:0X00022001
+event:0X272 mmcr0:0X00001838 mmcr1:0X0003C0008D76749C mmcra:0X00022001
+event:0X273 mmcr0:0X00001838 mmcr1:0X0003C0008D76749C mmcra:0X00022001
+event:0X274 mmcr0:0X00001838 mmcr1:0X0003C0008D76749C mmcra:0X00022001
+event:0X275 mmcr0:0X00001838 mmcr1:0X0003C0008D76749C mmcra:0X00022001
+event:0X276 mmcr0:0X00001838 mmcr1:0X0003C0008D76749C mmcra:0X00022001
+event:0X277 mmcr0:0X00001838 mmcr1:0X0003C0008D76749C mmcra:0X00022001
+
+#Group 40 pm_lsu7, Information on the Load Store Unit
+event:0X280 mmcr0:0X0000122C mmcr1:0X0118C00039F8749C mmcra:0X00022001
+event:0X281 mmcr0:0X0000122C mmcr1:0X0118C00039F8749C mmcra:0X00022001
+event:0X282 mmcr0:0X0000122C mmcr1:0X0118C00039F8749C mmcra:0X00022001
+event:0X283 mmcr0:0X0000122C mmcr1:0X0118C00039F8749C mmcra:0X00022001
+event:0X284 mmcr0:0X0000122C mmcr1:0X0118C00039F8749C mmcra:0X00022001
+event:0X285 mmcr0:0X0000122C mmcr1:0X0118C00039F8749C mmcra:0X00022001
+event:0X286 mmcr0:0X0000122C mmcr1:0X0118C00039F8749C mmcra:0X00022001
+event:0X287 mmcr0:0X0000122C mmcr1:0X0118C00039F8749C mmcra:0X00022001
+
+#Group 41 pm_dpfetch, Data Prefetch Events
+event:0X290 mmcr0:0X0000173E mmcr1:0X0108F000E74E93F8 mmcra:0X00002001
+event:0X291 mmcr0:0X0000173E mmcr1:0X0108F000E74E93F8 mmcra:0X00002001
+event:0X292 mmcr0:0X0000173E mmcr1:0X0108F000E74E93F8 mmcra:0X00002001
+event:0X293 mmcr0:0X0000173E mmcr1:0X0108F000E74E93F8 mmcra:0X00002001
+event:0X294 mmcr0:0X0000173E mmcr1:0X0108F000E74E93F8 mmcra:0X00002001
+event:0X295 mmcr0:0X0000173E mmcr1:0X0108F000E74E93F8 mmcra:0X00002001
+event:0X296 mmcr0:0X0000173E mmcr1:0X0108F000E74E93F8 mmcra:0X00002001
+event:0X297 mmcr0:0X0000173E mmcr1:0X0108F000E74E93F8 mmcra:0X00002001
+
+#Group 42 pm_misc, Misc Events for testing
+event:0X2A0 mmcr0:0X00000C14 mmcr1:0X0000000061D695B4 mmcra:0X00022001
+event:0X2A1 mmcr0:0X00000C14 mmcr1:0X0000000061D695B4 mmcra:0X00022001
+event:0X2A2 mmcr0:0X00000C14 mmcr1:0X0000000061D695B4 mmcra:0X00022001
+event:0X2A3 mmcr0:0X00000C14 mmcr1:0X0000000061D695B4 mmcra:0X00022001
+event:0X2A4 mmcr0:0X00000C14 mmcr1:0X0000000061D695B4 mmcra:0X00022001
+event:0X2A5 mmcr0:0X00000C14 mmcr1:0X0000000061D695B4 mmcra:0X00022001
+event:0X2A6 mmcr0:0X00000C14 mmcr1:0X0000000061D695B4 mmcra:0X00022001
+event:0X2A7 mmcr0:0X00000C14 mmcr1:0X0000000061D695B4 mmcra:0X00022001
+
+#Group 43 pm_mark1, Information on marked instructions
+event:0X2B0 mmcr0:0X00000816 mmcr1:0X010080803B18D6A4 mmcra:0X00722001
+event:0X2B1 mmcr0:0X00000816 mmcr1:0X010080803B18D6A4 mmcra:0X00722001
+event:0X2B2 mmcr0:0X00000816 mmcr1:0X010080803B18D6A4 mmcra:0X00722001
+event:0X2B3 mmcr0:0X00000816 mmcr1:0X010080803B18D6A4 mmcra:0X00722001
+event:0X2B4 mmcr0:0X00000816 mmcr1:0X010080803B18D6A4 mmcra:0X00722001
+event:0X2B5 mmcr0:0X00000816 mmcr1:0X010080803B18D6A4 mmcra:0X00722001
+event:0X2B6 mmcr0:0X00000816 mmcr1:0X010080803B18D6A4 mmcra:0X00722001
+event:0X2B7 mmcr0:0X00000816 mmcr1:0X010080803B18D6A4 mmcra:0X00722001
+
+#Group 44 pm_mark2, Marked Instructions Processing Flow
+event:0X2C0 mmcr0:0X00000A1A mmcr1:0X000000003B58C630 mmcra:0X00002001
+event:0X2C1 mmcr0:0X00000A1A mmcr1:0X000000003B58C630 mmcra:0X00002001
+event:0X2C2 mmcr0:0X00000A1A mmcr1:0X000000003B58C630 mmcra:0X00002001
+event:0X2C3 mmcr0:0X00000A1A mmcr1:0X000000003B58C630 mmcra:0X00002001
+event:0X2C4 mmcr0:0X00000A1A mmcr1:0X000000003B58C630 mmcra:0X00002001
+event:0X2C5 mmcr0:0X00000A1A mmcr1:0X000000003B58C630 mmcra:0X00002001
+event:0X2C6 mmcr0:0X00000A1A mmcr1:0X000000003B58C630 mmcra:0X00002001
+event:0X2C7 mmcr0:0X00000A1A mmcr1:0X000000003B58C630 mmcra:0X00002001
+
+#Group 45 pm_mark3, Marked Stores Processing Flow
+event:0X2D0 mmcr0:0X00000B0E mmcr1:0X010020005B1ABDA4 mmcra:0X00022001
+event:0X2D1 mmcr0:0X00000B0E mmcr1:0X010020005B1ABDA4 mmcra:0X00022001
+event:0X2D2 mmcr0:0X00000B0E mmcr1:0X010020005B1ABDA4 mmcra:0X00022001
+event:0X2D3 mmcr0:0X00000B0E mmcr1:0X010020005B1ABDA4 mmcra:0X00022001
+event:0X2D4 mmcr0:0X00000B0E mmcr1:0X010020005B1ABDA4 mmcra:0X00022001
+event:0X2D5 mmcr0:0X00000B0E mmcr1:0X010020005B1ABDA4 mmcra:0X00022001
+event:0X2D6 mmcr0:0X00000B0E mmcr1:0X010020005B1ABDA4 mmcra:0X00022001
+event:0X2D7 mmcr0:0X00000B0E mmcr1:0X010020005B1ABDA4 mmcra:0X00022001
+
+#Group 46 pm_mark4, Marked Loads Processing FLow
+event:0X2E0 mmcr0:0X0000080E mmcr1:0X01028080421AD4A0 mmcra:0X00002001
+event:0X2E1 mmcr0:0X0000080E mmcr1:0X01028080421AD4A0 mmcra:0X00002001
+event:0X2E2 mmcr0:0X0000080E mmcr1:0X01028080421AD4A0 mmcra:0X00002001
+event:0X2E3 mmcr0:0X0000080E mmcr1:0X01028080421AD4A0 mmcra:0X00002001
+event:0X2E4 mmcr0:0X0000080E mmcr1:0X01028080421AD4A0 mmcra:0X00002001
+event:0X2E5 mmcr0:0X0000080E mmcr1:0X01028080421AD4A0 mmcra:0X00002001
+event:0X2E6 mmcr0:0X0000080E mmcr1:0X01028080421AD4A0 mmcra:0X00002001
+event:0X2E7 mmcr0:0X0000080E mmcr1:0X01028080421AD4A0 mmcra:0X00002001
+
+#Group 47 pm_mark_lsource, Information on marked data source
+event:0X2F0 mmcr0:0X00000E1C mmcr1:0X00103000739CE738 mmcra:0X00002001
+event:0X2F1 mmcr0:0X00000E1C mmcr1:0X00103000739CE738 mmcra:0X00002001
+event:0X2F2 mmcr0:0X00000E1C mmcr1:0X00103000739CE738 mmcra:0X00002001
+event:0X2F3 mmcr0:0X00000E1C mmcr1:0X00103000739CE738 mmcra:0X00002001
+event:0X2F4 mmcr0:0X00000E1C mmcr1:0X00103000739CE738 mmcra:0X00002001
+event:0X2F5 mmcr0:0X00000E1C mmcr1:0X00103000739CE738 mmcra:0X00002001
+event:0X2F6 mmcr0:0X00000E1C mmcr1:0X00103000739CE738 mmcra:0X00002001
+event:0X2F7 mmcr0:0X00000E1C mmcr1:0X00103000739CE738 mmcra:0X00002001
+
+#Group 48 pm_mark_lsource2, Information on marked data source
+event:0X300 mmcr0:0X0000090E mmcr1:0X00103000E39CE738 mmcra:0X00002001
+event:0X301 mmcr0:0X0000090E mmcr1:0X00103000E39CE738 mmcra:0X00002001
+event:0X302 mmcr0:0X0000090E mmcr1:0X00103000E39CE738 mmcra:0X00002001
+event:0X303 mmcr0:0X0000090E mmcr1:0X00103000E39CE738 mmcra:0X00002001
+event:0X304 mmcr0:0X0000090E mmcr1:0X00103000E39CE738 mmcra:0X00002001
+event:0X305 mmcr0:0X0000090E mmcr1:0X00103000E39CE738 mmcra:0X00002001
+event:0X306 mmcr0:0X0000090E mmcr1:0X00103000E39CE738 mmcra:0X00002001
+event:0X307 mmcr0:0X0000090E mmcr1:0X00103000E39CE738 mmcra:0X00002001
+
+#Group 49 pm_mark_lsource3, Information on marked data source
+event:0X310 mmcr0:0X00000E1C mmcr1:0X00103000738E9770 mmcra:0X00002001
+event:0X311 mmcr0:0X00000E1C mmcr1:0X00103000738E9770 mmcra:0X00002001
+event:0X312 mmcr0:0X00000E1C mmcr1:0X00103000738E9770 mmcra:0X00002001
+event:0X313 mmcr0:0X00000E1C mmcr1:0X00103000738E9770 mmcra:0X00002001
+event:0X314 mmcr0:0X00000E1C mmcr1:0X00103000738E9770 mmcra:0X00002001
+event:0X315 mmcr0:0X00000E1C mmcr1:0X00103000738E9770 mmcra:0X00002001
+event:0X316 mmcr0:0X00000E1C mmcr1:0X00103000738E9770 mmcra:0X00002001
+event:0X317 mmcr0:0X00000E1C mmcr1:0X00103000738E9770 mmcra:0X00002001
+
+#Group 50 pm_lsu_mark1, Load Store Unit Marked Events
+event:0X320 mmcr0:0X00001B34 mmcr1:0X01028000850E98D4 mmcra:0X00022001
+event:0X321 mmcr0:0X00001B34 mmcr1:0X01028000850E98D4 mmcra:0X00022001
+event:0X322 mmcr0:0X00001B34 mmcr1:0X01028000850E98D4 mmcra:0X00022001
+event:0X323 mmcr0:0X00001B34 mmcr1:0X01028000850E98D4 mmcra:0X00022001
+event:0X324 mmcr0:0X00001B34 mmcr1:0X01028000850E98D4 mmcra:0X00022001
+event:0X325 mmcr0:0X00001B34 mmcr1:0X01028000850E98D4 mmcra:0X00022001
+event:0X326 mmcr0:0X00001B34 mmcr1:0X01028000850E98D4 mmcra:0X00022001
+event:0X327 mmcr0:0X00001B34 mmcr1:0X01028000850E98D4 mmcra:0X00022001
+
+#Group 51 pm_lsu_mark2, Load Store Unit Marked Events
+event:0X330 mmcr0:0X00001838 mmcr1:0X01028000958E99DC mmcra:0X00022001
+event:0X331 mmcr0:0X00001838 mmcr1:0X01028000958E99DC mmcra:0X00022001
+event:0X332 mmcr0:0X00001838 mmcr1:0X01028000958E99DC mmcra:0X00022001
+event:0X333 mmcr0:0X00001838 mmcr1:0X01028000958E99DC mmcra:0X00022001
+event:0X334 mmcr0:0X00001838 mmcr1:0X01028000958E99DC mmcra:0X00022001
+event:0X335 mmcr0:0X00001838 mmcr1:0X01028000958E99DC mmcra:0X00022001
+event:0X336 mmcr0:0X00001838 mmcr1:0X01028000958E99DC mmcra:0X00022001
+event:0X337 mmcr0:0X00001838 mmcr1:0X01028000958E99DC mmcra:0X00022001
+
+#Group 52 pm_lsu_mark3, Load Store Unit Marked Events
+event:0X340 mmcr0:0X00001D0E mmcr1:0X0100B000CE8ED6A4 mmcra:0X00022001
+event:0X341 mmcr0:0X00001D0E mmcr1:0X0100B000CE8ED6A4 mmcra:0X00022001
+event:0X342 mmcr0:0X00001D0E mmcr1:0X0100B000CE8ED6A4 mmcra:0X00022001
+event:0X343 mmcr0:0X00001D0E mmcr1:0X0100B000CE8ED6A4 mmcra:0X00022001
+event:0X344 mmcr0:0X00001D0E mmcr1:0X0100B000CE8ED6A4 mmcra:0X00022001
+event:0X345 mmcr0:0X00001D0E mmcr1:0X0100B000CE8ED6A4 mmcra:0X00022001
+event:0X346 mmcr0:0X00001D0E mmcr1:0X0100B000CE8ED6A4 mmcra:0X00022001
+event:0X347 mmcr0:0X00001D0E mmcr1:0X0100B000CE8ED6A4 mmcra:0X00022001
+
+#Group 53 pm_threshold, Group for pipeline threshold studies
+event:0X350 mmcr0:0X00001E16 mmcr1:0X0100A000CA4ED5F4 mmcra:0X00722001
+event:0X351 mmcr0:0X00001E16 mmcr1:0X0100A000CA4ED5F4 mmcra:0X00722001
+event:0X352 mmcr0:0X00001E16 mmcr1:0X0100A000CA4ED5F4 mmcra:0X00722001
+event:0X353 mmcr0:0X00001E16 mmcr1:0X0100A000CA4ED5F4 mmcra:0X00722001
+event:0X354 mmcr0:0X00001E16 mmcr1:0X0100A000CA4ED5F4 mmcra:0X00722001
+event:0X355 mmcr0:0X00001E16 mmcr1:0X0100A000CA4ED5F4 mmcra:0X00722001
+event:0X356 mmcr0:0X00001E16 mmcr1:0X0100A000CA4ED5F4 mmcra:0X00722001
+event:0X357 mmcr0:0X00001E16 mmcr1:0X0100A000CA4ED5F4 mmcra:0X00722001
+
+#Group 54 pm_pe_bench1, PE Benchmarker group for FP analysis
+event:0X360 mmcr0:0X00000810 mmcr1:0X10001002420E84A0 mmcra:0X00002001
+event:0X361 mmcr0:0X00000810 mmcr1:0X10001002420E84A0 mmcra:0X00002001
+event:0X362 mmcr0:0X00000810 mmcr1:0X10001002420E84A0 mmcra:0X00002001
+event:0X363 mmcr0:0X00000810 mmcr1:0X10001002420E84A0 mmcra:0X00002001
+event:0X364 mmcr0:0X00000810 mmcr1:0X10001002420E84A0 mmcra:0X00002001
+event:0X365 mmcr0:0X00000810 mmcr1:0X10001002420E84A0 mmcra:0X00002001
+event:0X366 mmcr0:0X00000810 mmcr1:0X10001002420E84A0 mmcra:0X00002001
+event:0X367 mmcr0:0X00000810 mmcr1:0X10001002420E84A0 mmcra:0X00002001
+
+#Group 55 pm_pe_bench2, PE Benchmarker group for FP stalls analysis
+event:0X370 mmcr0:0X00000710 mmcr1:0X110420689A508BA0 mmcra:0X00002001
+event:0X371 mmcr0:0X00000710 mmcr1:0X110420689A508BA0 mmcra:0X00002001
+event:0X372 mmcr0:0X00000710 mmcr1:0X110420689A508BA0 mmcra:0X00002001
+event:0X373 mmcr0:0X00000710 mmcr1:0X110420689A508BA0 mmcra:0X00002001
+event:0X374 mmcr0:0X00000710 mmcr1:0X110420689A508BA0 mmcra:0X00002001
+event:0X375 mmcr0:0X00000710 mmcr1:0X110420689A508BA0 mmcra:0X00002001
+event:0X376 mmcr0:0X00000710 mmcr1:0X110420689A508BA0 mmcra:0X00002001
+event:0X377 mmcr0:0X00000710 mmcr1:0X110420689A508BA0 mmcra:0X00002001
+
+#Group 56 pm_pe_bench3, PE Benchmarker group for branch analysis
+event:0X380 mmcr0:0X00000938 mmcr1:0X90040000C66A7D6C mmcra:0X00022001
+event:0X381 mmcr0:0X00000938 mmcr1:0X90040000C66A7D6C mmcra:0X00022001
+event:0X382 mmcr0:0X00000938 mmcr1:0X90040000C66A7D6C mmcra:0X00022001
+event:0X383 mmcr0:0X00000938 mmcr1:0X90040000C66A7D6C mmcra:0X00022001
+event:0X384 mmcr0:0X00000938 mmcr1:0X90040000C66A7D6C mmcra:0X00022001
+event:0X385 mmcr0:0X00000938 mmcr1:0X90040000C66A7D6C mmcra:0X00022001
+event:0X386 mmcr0:0X00000938 mmcr1:0X90040000C66A7D6C mmcra:0X00022001
+event:0X387 mmcr0:0X00000938 mmcr1:0X90040000C66A7D6C mmcra:0X00022001
+
+#Group 57 pm_pe_bench4, PE Benchmarker group for L1 and TLB analysis
+event:0X390 mmcr0:0X00001420 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X391 mmcr0:0X00001420 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X392 mmcr0:0X00001420 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X393 mmcr0:0X00001420 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X394 mmcr0:0X00001420 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X395 mmcr0:0X00001420 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X396 mmcr0:0X00001420 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X397 mmcr0:0X00001420 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+
+#Group 58 pm_pe_bench5, PE Benchmarker group for L2 analysis
+event:0X3A0 mmcr0:0X0000090E mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X3A1 mmcr0:0X0000090E mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X3A2 mmcr0:0X0000090E mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X3A3 mmcr0:0X0000090E mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X3A4 mmcr0:0X0000090E mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X3A5 mmcr0:0X0000090E mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X3A6 mmcr0:0X0000090E mmcr1:0X0010C000739CE738 mmcra:0X00002001
+event:0X3A7 mmcr0:0X0000090E mmcr1:0X0010C000739CE738 mmcra:0X00002001
+
+#Group 59 pm_pe_bench6, PE Benchmarker group for L3 analysis
+event:0X3B0 mmcr0:0X00000E1C mmcr1:0X0010C000739C74B8 mmcra:0X00002001
+event:0X3B1 mmcr0:0X00000E1C mmcr1:0X0010C000739C74B8 mmcra:0X00002001
+event:0X3B2 mmcr0:0X00000E1C mmcr1:0X0010C000739C74B8 mmcra:0X00002001
+event:0X3B3 mmcr0:0X00000E1C mmcr1:0X0010C000739C74B8 mmcra:0X00002001
+event:0X3B4 mmcr0:0X00000E1C mmcr1:0X0010C000739C74B8 mmcra:0X00002001
+event:0X3B5 mmcr0:0X00000E1C mmcr1:0X0010C000739C74B8 mmcra:0X00002001
+event:0X3B6 mmcr0:0X00000E1C mmcr1:0X0010C000739C74B8 mmcra:0X00002001
+event:0X3B7 mmcr0:0X00000E1C mmcr1:0X0010C000739C74B8 mmcra:0X00002001
+
+#Group 60 pm_hpmcount1, Hpmcount group for L1 and TLB behavior analysis
+event:0X3C0 mmcr0:0X00001414 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X3C1 mmcr0:0X00001414 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X3C2 mmcr0:0X00001414 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X3C3 mmcr0:0X00001414 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X3C4 mmcr0:0X00001414 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X3C5 mmcr0:0X00001414 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X3C6 mmcr0:0X00001414 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+event:0X3C7 mmcr0:0X00001414 mmcr1:0X010B000044CE9420 mmcra:0X00002001
+
+#Group 61 pm_hpmcount2, Hpmcount group for computation intensity analysis
+event:0X3D0 mmcr0:0X00000810 mmcr1:0X010020289DCE84A0 mmcra:0X00002001
+event:0X3D1 mmcr0:0X00000810 mmcr1:0X010020289DCE84A0 mmcra:0X00002001
+event:0X3D2 mmcr0:0X00000810 mmcr1:0X010020289DCE84A0 mmcra:0X00002001
+event:0X3D3 mmcr0:0X00000810 mmcr1:0X010020289DCE84A0 mmcra:0X00002001
+event:0X3D4 mmcr0:0X00000810 mmcr1:0X010020289DCE84A0 mmcra:0X00002001
+event:0X3D5 mmcr0:0X00000810 mmcr1:0X010020289DCE84A0 mmcra:0X00002001
+event:0X3D6 mmcr0:0X00000810 mmcr1:0X010020289DCE84A0 mmcra:0X00002001
+event:0X3D7 mmcr0:0X00000810 mmcr1:0X010020289DCE84A0 mmcra:0X00002001
+
+#Group 62 pm_l1andbr, L1 misses and branch misspredict analysis
+event:0X3E0 mmcr0:0X0000090E mmcr1:0X8003C00046367CE8 mmcra:0X00002001
+event:0X3E1 mmcr0:0X0000090E mmcr1:0X8003C00046367CE8 mmcra:0X00002001
+event:0X3E2 mmcr0:0X0000090E mmcr1:0X8003C00046367CE8 mmcra:0X00002001
+event:0X3E3 mmcr0:0X0000090E mmcr1:0X8003C00046367CE8 mmcra:0X00002001
+event:0X3E4 mmcr0:0X0000090E mmcr1:0X8003C00046367CE8 mmcra:0X00002001
+event:0X3E5 mmcr0:0X0000090E mmcr1:0X8003C00046367CE8 mmcra:0X00002001
+event:0X3E6 mmcr0:0X0000090E mmcr1:0X8003C00046367CE8 mmcra:0X00002001
+event:0X3E7 mmcr0:0X0000090E mmcr1:0X8003C00046367CE8 mmcra:0X00002001
+
+#Group 63 pm_imix, Instruction mix: loads, stores and branches
+event:0X3F0 mmcr0:0X0000090E mmcr1:0X8003C000460FB420 mmcra:0X00002001
+event:0X3F1 mmcr0:0X0000090E mmcr1:0X8003C000460FB420 mmcra:0X00002001
+event:0X3F2 mmcr0:0X0000090E mmcr1:0X8003C000460FB420 mmcra:0X00002001
+event:0X3F3 mmcr0:0X0000090E mmcr1:0X8003C000460FB420 mmcra:0X00002001
+event:0X3F4 mmcr0:0X0000090E mmcr1:0X8003C000460FB420 mmcra:0X00002001
+event:0X3F5 mmcr0:0X0000090E mmcr1:0X8003C000460FB420 mmcra:0X00002001
+event:0X3F6 mmcr0:0X0000090E mmcr1:0X8003C000460FB420 mmcra:0X00002001
+event:0X3F7 mmcr0:0X0000090E mmcr1:0X8003C000460FB420 mmcra:0X00002001
diff --git a/events/ppc64/power4/events b/events/ppc64/power4/events
new file mode 100644
index 0000000..7c553d3
--- /dev/null
+++ b/events/ppc64/power4/events
@@ -0,0 +1,645 @@
+#PPC64 POWER4 events
+#
+# Within each group the event names must be unique. Each event in a group is
+# assigned to a unique counter. The groups are from the groups defined in the
+# Performance Monitor Unit user guide for this processor.
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
+
+
+#Group 1 pm_slice0, Time Slice 0
+event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_slice0) Run cycles
+event:0X011 counters:1 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
+event:0X012 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP1 : (Group 1 pm_slice0) Completion stopped
+event:0X013 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_slice0) Instructions completed
+event:0X014 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP1 : (Group 1 pm_slice0) One or more PPC instruction completed
+event:0X015 counters:5 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_slice0) Processor cycles
+event:0X016 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP1 : (Group 1 pm_slice0) Group completed
+event:0X017 counters:7 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP1 : (Group 1 pm_slice0) Group dispatch rejected
+
+#Group 2 pm_eprof, Group for use with eprof
+event:0X020 counters:0 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
+event:0X021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_eprof) Processor cycles
+event:0X022 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load misses
+event:0X023 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP2 : (Group 2 pm_eprof) L1 D cache entries invalidated from L2
+event:0X024 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP2 : (Group 2 pm_eprof) Instructions dispatched
+event:0X025 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP2 : (Group 2 pm_eprof) Instructions completed
+event:0X026 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache store references
+event:0X027 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP2 : (Group 2 pm_eprof) L1 D cache load references
+
+#Group 3 pm_basic, Basic performance indicators
+event:0X030 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed
+event:0X031 counters:1 um:zero minimum:10000 name:PM_CYC_GRP3 : (Group 3 pm_basic) Processor cycles
+event:0X032 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP3 : (Group 3 pm_basic) L1 D cache load misses
+event:0X033 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP3 : (Group 3 pm_basic) L1 D cache entries invalidated from L2
+event:0X034 counters:4 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_basic) Instructions dispatched
+event:0X035 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_basic) Instructions completed
+event:0X036 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache store references
+event:0X037 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP3 : (Group 3 pm_basic) L1 D cache load references
+
+#Group 4 pm_ifu, IFU events
+event:0X040 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP4 : (Group 4 pm_ifu) Instructions completed
+event:0X041 counters:1 um:zero minimum:1000 name:PM_BIQ_IDU_FULL_CYC_GRP4 : (Group 4 pm_ifu) Cycles BIQ or IDU full
+event:0X042 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP4 : (Group 4 pm_ifu) Branches issued
+event:0X043 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP4 : (Group 4 pm_ifu) Branch mispredictions due CR bit setting
+event:0X044 counters:4 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP4 : (Group 4 pm_ifu) Cycles at least 1 instruction fetched
+event:0X045 counters:5 um:zero minimum:10000 name:PM_CYC_GRP4 : (Group 4 pm_ifu) Processor cycles
+event:0X046 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP4 : (Group 4 pm_ifu) Branch mispredictions due to target address
+event:0X047 counters:7 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP4 : (Group 4 pm_ifu) Cycles writing to instruction L1
+
+#Group 5 pm_isu, ISU Queue full events
+event:0X050 counters:0 um:zero minimum:1000 name:PM_FPR_MAP_FULL_CYC_GRP5 : (Group 5 pm_isu) Cycles FPR mapper full
+event:0X051 counters:1 um:zero minimum:1000 name:PM_BRQ_FULL_CYC_GRP5 : (Group 5 pm_isu) Cycles branch queue full
+event:0X052 counters:2 um:zero minimum:1000 name:PM_GPR_MAP_FULL_CYC_GRP5 : (Group 5 pm_isu) Cycles GPR mapper full
+event:0X053 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP5 : (Group 5 pm_isu) Instructions completed
+event:0X054 counters:4 um:zero minimum:1000 name:PM_FPU_FULL_CYC_GRP5 : (Group 5 pm_isu) Cycles FPU issue queue full
+event:0X055 counters:5 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP5 : (Group 5 pm_isu) Cycles GCT full
+event:0X056 counters:6 um:zero minimum:10000 name:PM_CYC_GRP5 : (Group 5 pm_isu) Processor cycles
+event:0X057 counters:7 um:zero minimum:1000 name:PM_FXLS_FULL_CYC_GRP5 : (Group 5 pm_isu) Cycles FXLS queue is full
+
+#Group 6 pm_lsource, Information on data source
+event:0X060 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP6 : (Group 6 pm_lsource) Data loaded from L3
+event:0X061 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP6 : (Group 6 pm_lsource) Data loaded from memory
+event:0X062 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L35_GRP6 : (Group 6 pm_lsource) Data loaded from L3.5
+event:0X063 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP6 : (Group 6 pm_lsource) Data loaded from L2
+event:0X064 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP6 : (Group 6 pm_lsource) Data loaded from L2.5 shared
+event:0X065 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GRP6 : (Group 6 pm_lsource) Data loaded from L2.75 shared
+event:0X066 counters:6 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP6 : (Group 6 pm_lsource) Data loaded from L2.75 modified
+event:0X067 counters:7 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP6 : (Group 6 pm_lsource) Data loaded from L2.5 modified
+
+#Group 7 pm_isource, Instruction Source information
+event:0X070 counters:0 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP7 : (Group 7 pm_isource) Instruction fetched from memory
+event:0X071 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_L275_GRP7 : (Group 7 pm_isource) Instruction fetched from L2.5/L2.75
+event:0X072 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP7 : (Group 7 pm_isource) Instructions fetched from L2
+event:0X073 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L35_GRP7 : (Group 7 pm_isource) Instructions fetched from L3.5
+event:0X074 counters:4 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP7 : (Group 7 pm_isource) Instruction fetched from L3
+event:0X075 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP7 : (Group 7 pm_isource) Instruction fetched from L1
+event:0X076 counters:6 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP7 : (Group 7 pm_isource) Instructions fetched from prefetch
+event:0X077 counters:7 um:zero minimum:1000 name:PM_0INST_FETCH_GRP7 : (Group 7 pm_isource) No instructions fetched
+
+#Group 8 pm_lsu, Information on the Load Store Unit
+event:0X080 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP8 : (Group 8 pm_lsu) LRQ unaligned load flushes
+event:0X081 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP8 : (Group 8 pm_lsu) SRQ unaligned store flushes
+event:0X082 counters:2 um:zero minimum:10000 name:PM_CYC_GRP8 : (Group 8 pm_lsu) Processor cycles
+event:0X083 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP8 : (Group 8 pm_lsu) Instructions completed
+event:0X084 counters:4 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP8 : (Group 8 pm_lsu) SRQ flushes
+event:0X085 counters:5 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP8 : (Group 8 pm_lsu) LRQ flushes
+event:0X086 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP8 : (Group 8 pm_lsu) L1 D cache store references
+event:0X087 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP8 : (Group 8 pm_lsu) L1 D cache load references
+
+#Group 9 pm_xlate1, Translation Events
+event:0X090 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP9 : (Group 9 pm_xlate1) Instruction TLB misses
+event:0X091 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP9 : (Group 9 pm_xlate1) Data TLB misses
+event:0X092 counters:2 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP9 : (Group 9 pm_xlate1) Cycles doing data tablewalks
+event:0X093 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP9 : (Group 9 pm_xlate1) LMQ slot 0 valid
+event:0X094 counters:4 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP9 : (Group 9 pm_xlate1) Translation written to ierat
+event:0X095 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP9 : (Group 9 pm_xlate1) DERAT misses
+event:0X096 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP9 : (Group 9 pm_xlate1) Instructions completed
+event:0X097 counters:7 um:zero minimum:10000 name:PM_CYC_GRP9 : (Group 9 pm_xlate1) Processor cycles
+
+#Group 10 pm_xlate2, Translation Events
+event:0X0A0 counters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP10 : (Group 10 pm_xlate2) Instruction SLB misses
+event:0X0A1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP10 : (Group 10 pm_xlate2) Data SLB misses
+event:0X0A2 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP10 : (Group 10 pm_xlate2) SRQ sync duration
+event:0X0A3 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP10 : (Group 10 pm_xlate2) LMQ slot 0 allocated
+event:0X0A4 counters:4 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP10 : (Group 10 pm_xlate2) Translation written to ierat
+event:0X0A5 counters:5 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP10 : (Group 10 pm_xlate2) DERAT misses
+event:0X0A6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP10 : (Group 10 pm_xlate2) Instructions completed
+event:0X0A7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP10 : (Group 10 pm_xlate2) Processor cycles
+
+#Group 11 pm_gps1, L3 Events
+event:0X0B0 counters:0 um:zero minimum:1000 name:PM_L3B0_DIR_REF_GRP11 : (Group 11 pm_gps1) L3 bank 0 directory references
+event:0X0B1 counters:1 um:zero minimum:1000 name:PM_L3B0_DIR_MIS_GRP11 : (Group 11 pm_gps1) L3 bank 0 directory misses
+event:0X0B2 counters:2 um:zero minimum:1000 name:PM_FAB_CMD_ISSUED_GRP11 : (Group 11 pm_gps1) Fabric command issued
+event:0X0B3 counters:3 um:zero minimum:1000 name:PM_FAB_CMD_RETRIED_GRP11 : (Group 11 pm_gps1) Fabric command retried
+event:0X0B4 counters:4 um:zero minimum:1000 name:PM_L3B1_DIR_REF_GRP11 : (Group 11 pm_gps1) L3 bank 1 directory references
+event:0X0B5 counters:5 um:zero minimum:1000 name:PM_L3B1_DIR_MIS_GRP11 : (Group 11 pm_gps1) L3 bank 1 directory misses
+event:0X0B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP11 : (Group 11 pm_gps1) Instructions completed
+event:0X0B7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP11 : (Group 11 pm_gps1) Processor cycles
+
+#Group 12 pm_l2a, L2 SliceA events
+event:0X0C0 counters:0 um:zero minimum:1000 name:PM_L2SA_MOD_TAG_GRP12 : (Group 12 pm_l2a) L2 slice A transition from modified to tagged
+event:0X0C1 counters:1 um:zero minimum:1000 name:PM_L2SA_SHR_INV_GRP12 : (Group 12 pm_l2a) L2 slice A transition from shared to invalid
+event:0X0C2 counters:2 um:zero minimum:1000 name:PM_L2SA_ST_REQ_GRP12 : (Group 12 pm_l2a) L2 slice A store requests
+event:0X0C3 counters:3 um:zero minimum:1000 name:PM_L2SA_ST_HIT_GRP12 : (Group 12 pm_l2a) L2 slice A store hits
+event:0X0C4 counters:4 um:zero minimum:1000 name:PM_L2SA_SHR_MOD_GRP12 : (Group 12 pm_l2a) L2 slice A transition from shared to modified
+event:0X0C5 counters:5 um:zero minimum:1000 name:PM_L2SA_MOD_INV_GRP12 : (Group 12 pm_l2a) L2 slice A transition from modified to invalid
+event:0X0C6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP12 : (Group 12 pm_l2a) Instructions completed
+event:0X0C7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP12 : (Group 12 pm_l2a) Processor cycles
+
+#Group 13 pm_l2b, L2 SliceB events
+event:0X0D0 counters:0 um:zero minimum:1000 name:PM_L2SB_MOD_TAG_GRP13 : (Group 13 pm_l2b) L2 slice B transition from modified to tagged
+event:0X0D1 counters:1 um:zero minimum:1000 name:PM_L2SB_SHR_INV_GRP13 : (Group 13 pm_l2b) L2 slice B transition from shared to invalid
+event:0X0D2 counters:2 um:zero minimum:1000 name:PM_L2SB_ST_REQ_GRP13 : (Group 13 pm_l2b) L2 slice B store requests
+event:0X0D3 counters:3 um:zero minimum:1000 name:PM_L2SB_ST_HIT_GRP13 : (Group 13 pm_l2b) L2 slice B store hits
+event:0X0D4 counters:4 um:zero minimum:1000 name:PM_L2SB_SHR_MOD_GRP13 : (Group 13 pm_l2b) L2 slice B transition from shared to modified
+event:0X0D5 counters:5 um:zero minimum:1000 name:PM_L2SB_MOD_INV_GRP13 : (Group 13 pm_l2b) L2 slice B transition from modified to invalid
+event:0X0D6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP13 : (Group 13 pm_l2b) Instructions completed
+event:0X0D7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP13 : (Group 13 pm_l2b) Processor cycles
+
+#Group 14 pm_l2c, L2 SliceC events
+event:0X0E0 counters:0 um:zero minimum:1000 name:PM_L2SC_MOD_TAG_GRP14 : (Group 14 pm_l2c) L2 slice C transition from modified to tagged
+event:0X0E1 counters:1 um:zero minimum:1000 name:PM_L2SC_SHR_INV_GRP14 : (Group 14 pm_l2c) L2 slice C transition from shared to invalid
+event:0X0E2 counters:2 um:zero minimum:1000 name:PM_L2SC_ST_REQ_GRP14 : (Group 14 pm_l2c) L2 slice C store requests
+event:0X0E3 counters:3 um:zero minimum:1000 name:PM_L2SC_ST_HIT_GRP14 : (Group 14 pm_l2c) L2 slice C store hits
+event:0X0E4 counters:4 um:zero minimum:1000 name:PM_L2SC_SHR_MOD_GRP14 : (Group 14 pm_l2c) L2 slice C transition from shared to modified
+event:0X0E5 counters:5 um:zero minimum:1000 name:PM_L2SC_MOD_INV_GRP14 : (Group 14 pm_l2c) L2 slice C transition from modified to invalid
+event:0X0E6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP14 : (Group 14 pm_l2c) Instructions completed
+event:0X0E7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_l2c) Processor cycles
+
+#Group 15 pm_fpu1, Floating Point events
+event:0X0F0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP15 : (Group 15 pm_fpu1) FPU executed FDIV instruction
+event:0X0F1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP15 : (Group 15 pm_fpu1) FPU executed multiply-add instruction
+event:0X0F2 counters:2 um:zero minimum:1000 name:PM_FPU_FEST_GRP15 : (Group 15 pm_fpu1) FPU executed FEST instruction
+event:0X0F3 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP15 : (Group 15 pm_fpu1) FPU produced a result
+event:0X0F4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP15 : (Group 15 pm_fpu1) Processor cycles
+event:0X0F5 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP15 : (Group 15 pm_fpu1) FPU executed FSQRT instruction
+event:0X0F6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP15 : (Group 15 pm_fpu1) Instructions completed
+event:0X0F7 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP15 : (Group 15 pm_fpu1) FPU executing FMOV or FEST instructions
+
+#Group 16 pm_fpu2, Floating Point events
+event:0X100 counters:0 um:zero minimum:1000 name:PM_FPU_DENORM_GRP16 : (Group 16 pm_fpu2) FPU received denormalized data
+event:0X101 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP16 : (Group 16 pm_fpu2) FPU stalled in pipe3
+event:0X102 counters:2 um:zero minimum:10000 name:PM_CYC_GRP16 : (Group 16 pm_fpu2) Processor cycles
+event:0X103 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP16 : (Group 16 pm_fpu2) Instructions completed
+event:0X104 counters:4 um:zero minimum:1000 name:PM_FPU_ALL_GRP16 : (Group 16 pm_fpu2) FPU executed add, mult, sub, cmp or sel instruction
+event:0X105 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP16 : (Group 16 pm_fpu2) FPU executed store instruction
+event:0X106 counters:6 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP16 : (Group 16 pm_fpu2) FPU executed FRSP or FCONV instructions
+event:0X107 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP16 : (Group 16 pm_fpu2) LSU executed Floating Point load instruction
+
+#Group 17 pm_idu1, Instruction Decode Unit events
+event:0X110 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP17 : (Group 17 pm_idu1) Instructions completed
+event:0X111 counters:1 um:zero minimum:10000 name:PM_CYC_GRP17 : (Group 17 pm_idu1) Processor cycles
+event:0X112 counters:2 um:zero minimum:1000 name:PM_1INST_CLB_CYC_GRP17 : (Group 17 pm_idu1) Cycles 1 instruction in CLB
+event:0X113 counters:3 um:zero minimum:1000 name:PM_2INST_CLB_CYC_GRP17 : (Group 17 pm_idu1) Cycles 2 instructions in CLB
+event:0X114 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP17 : (Group 17 pm_idu1) One or more PPC instruction completed
+event:0X115 counters:5 um:zero minimum:10000 name:PM_CYC_GRP17 : (Group 17 pm_idu1) Processor cycles
+event:0X116 counters:6 um:zero minimum:1000 name:PM_3INST_CLB_CYC_GRP17 : (Group 17 pm_idu1) Cycles 3 instructions in CLB
+event:0X117 counters:7 um:zero minimum:1000 name:PM_4INST_CLB_CYC_GRP17 : (Group 17 pm_idu1) Cycles 4 instructions in CLB
+
+#Group 18 pm_idu2, Instruction Decode Unit events
+event:0X120 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP18 : (Group 18 pm_idu2) Instructions completed
+event:0X121 counters:1 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_idu2) Processor cycles
+event:0X122 counters:2 um:zero minimum:1000 name:PM_5INST_CLB_CYC_GRP18 : (Group 18 pm_idu2) Cycles 5 instructions in CLB
+event:0X123 counters:3 um:zero minimum:1000 name:PM_6INST_CLB_CYC_GRP18 : (Group 18 pm_idu2) Cycles 6 instructions in CLB
+event:0X124 counters:4 um:zero minimum:1000 name:PM_GRP_DISP_SUCCESS_GRP18 : (Group 18 pm_idu2) Group dispatch success
+event:0X125 counters:5 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_idu2) Processor cycles
+event:0X126 counters:6 um:zero minimum:1000 name:PM_7INST_CLB_CYC_GRP18 : (Group 18 pm_idu2) Cycles 7 instructions in CLB
+event:0X127 counters:7 um:zero minimum:1000 name:PM_8INST_CLB_CYC_GRP18 : (Group 18 pm_idu2) Cycles 8 instructions in CLB
+
+#Group 19 pm_isu_rename, ISU Rename Pool Events
+event:0X130 counters:0 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP19 : (Group 19 pm_isu_rename) Cycles XER mapper full
+event:0X131 counters:1 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP19 : (Group 19 pm_isu_rename) Cycles CR logical operation mapper full
+event:0X132 counters:2 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP19 : (Group 19 pm_isu_rename) Cycles CR issue queue full
+event:0X133 counters:3 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP19 : (Group 19 pm_isu_rename) Cycles group dispatch blocked by scoreboard
+event:0X134 counters:4 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP19 : (Group 19 pm_isu_rename) Cycles LR/CTR mapper full
+event:0X135 counters:5 um:zero minimum:1000 name:PM_INST_DISP_GRP19 : (Group 19 pm_isu_rename) Instructions dispatched
+event:0X136 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP19 : (Group 19 pm_isu_rename) Instructions completed
+event:0X137 counters:7 um:zero minimum:10000 name:PM_CYC_GRP19 : (Group 19 pm_isu_rename) Processor cycles
+
+#Group 20 pm_isu_queues1, ISU Queue Full Events
+event:0X140 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP20 : (Group 20 pm_isu_queues1) Cycles FPU0 issue queue full
+event:0X141 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP20 : (Group 20 pm_isu_queues1) Cycles FPU1 issue queue full
+event:0X142 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP20 : (Group 20 pm_isu_queues1) Cycles FXU0/LS0 queue full
+event:0X143 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP20 : (Group 20 pm_isu_queues1) Cycles FXU1/LS1 queue full
+event:0X144 counters:4 um:zero minimum:10000 name:PM_CYC_GRP20 : (Group 20 pm_isu_queues1) Processor cycles
+event:0X145 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP20 : (Group 20 pm_isu_queues1) Instructions completed
+event:0X146 counters:6 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP20 : (Group 20 pm_isu_queues1) Cycles LRQ full
+event:0X147 counters:7 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP20 : (Group 20 pm_isu_queues1) Cycles SRQ full
+
+#Group 21 pm_isu_flow, ISU Instruction Flow Events
+event:0X150 counters:0 um:zero minimum:1000 name:PM_INST_DISP_GRP21 : (Group 21 pm_isu_flow) Instructions dispatched
+event:0X151 counters:1 um:zero minimum:10000 name:PM_CYC_GRP21 : (Group 21 pm_isu_flow) Processor cycles
+event:0X152 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP21 : (Group 21 pm_isu_flow) FXU0 produced a result
+event:0X153 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP21 : (Group 21 pm_isu_flow) FXU1 produced a result
+event:0X154 counters:4 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP21 : (Group 21 pm_isu_flow) Group dispatch valid
+event:0X155 counters:5 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP21 : (Group 21 pm_isu_flow) Group dispatch rejected
+event:0X156 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP21 : (Group 21 pm_isu_flow) Instructions completed
+event:0X157 counters:7 um:zero minimum:10000 name:PM_CYC_GRP21 : (Group 21 pm_isu_flow) Processor cycles
+
+#Group 22 pm_isu_work, ISU Indicators of Work Blockage
+event:0X160 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP22 : (Group 22 pm_isu_work) Cycles GCT empty
+event:0X161 counters:1 um:zero minimum:1000 name:PM_WORK_HELD_GRP22 : (Group 22 pm_isu_work) Work held
+event:0X162 counters:2 um:zero minimum:1000 name:PM_STOP_COMPLETION_GRP22 : (Group 22 pm_isu_work) Completion stopped
+event:0X163 counters:3 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP22 : (Group 22 pm_isu_work) Cycles MSR(EE) bit off and external interrupt pending
+event:0X164 counters:4 um:zero minimum:10000 name:PM_CYC_GRP22 : (Group 22 pm_isu_work) Processor cycles
+event:0X165 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP22 : (Group 22 pm_isu_work) Instructions completed
+event:0X166 counters:6 um:zero minimum:1000 name:PM_EE_OFF_GRP22 : (Group 22 pm_isu_work) Cycles MSR(EE) bit off
+event:0X167 counters:7 um:zero minimum:1000 name:PM_EXT_INT_GRP22 : (Group 22 pm_isu_work) External interrupts
+
+#Group 23 pm_serialize, LSU Serializing Events
+event:0X170 counters:0 um:zero minimum:1000 name:PM_SNOOP_TLBIE_GRP23 : (Group 23 pm_serialize) Snoop TLBIE
+event:0X171 counters:1 um:zero minimum:1000 name:PM_STCX_FAIL_GRP23 : (Group 23 pm_serialize) STCX failed
+event:0X172 counters:2 um:zero minimum:1000 name:PM_STCX_PASS_GRP23 : (Group 23 pm_serialize) Stcx passes
+event:0X173 counters:3 um:zero minimum:10000 name:PM_CYC_GRP23 : (Group 23 pm_serialize) Processor cycles
+event:0X174 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP23 : (Group 23 pm_serialize) One or more PPC instruction completed
+event:0X175 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP23 : (Group 23 pm_serialize) Instructions completed
+event:0X176 counters:6 um:zero minimum:1000 name:PM_LARX_LSU0_GRP23 : (Group 23 pm_serialize) Larx executed on LSU0
+event:0X177 counters:7 um:zero minimum:1000 name:PM_LARX_LSU1_GRP23 : (Group 23 pm_serialize) Larx executed on LSU1
+
+#Group 24 pm_lsubusy, LSU Busy Events
+event:0X180 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP24 : (Group 24 pm_lsubusy) SRQ slot 0 valid
+event:0X181 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP24 : (Group 24 pm_lsubusy) SRQ slot 0 allocated
+event:0X182 counters:2 um:zero minimum:1000 name:PM_LSU0_BUSY_GRP24 : (Group 24 pm_lsubusy) LSU0 busy
+event:0X183 counters:3 um:zero minimum:1000 name:PM_LSU1_BUSY_GRP24 : (Group 24 pm_lsubusy) LSU1 busy
+event:0X184 counters:4 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP24 : (Group 24 pm_lsubusy) LRQ slot 0 valid
+event:0X185 counters:5 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP24 : (Group 24 pm_lsubusy) LRQ slot 0 allocated
+event:0X186 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP24 : (Group 24 pm_lsubusy) Instructions completed
+event:0X187 counters:7 um:zero minimum:10000 name:PM_CYC_GRP24 : (Group 24 pm_lsubusy) Processor cycles
+
+#Group 25 pm_lsource2, Information on data source
+event:0X190 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP25 : (Group 25 pm_lsource2) Instructions completed
+event:0X191 counters:1 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP25 : (Group 25 pm_lsource2) L1 reload data source valid
+event:0X192 counters:2 um:zero minimum:10000 name:PM_CYC_GRP25 : (Group 25 pm_lsource2) Processor cycles
+event:0X193 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP25 : (Group 25 pm_lsource2) Data loaded from L2
+event:0X194 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP25 : (Group 25 pm_lsource2) Data loaded from L2.5 shared
+event:0X195 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GRP25 : (Group 25 pm_lsource2) Data loaded from L2.75 shared
+event:0X196 counters:6 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP25 : (Group 25 pm_lsource2) Data loaded from L2.75 modified
+event:0X197 counters:7 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP25 : (Group 25 pm_lsource2) Data loaded from L2.5 modified
+
+#Group 26 pm_lsource3, Information on data source
+event:0X1A0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP26 : (Group 26 pm_lsource3) Data loaded from L3
+event:0X1A1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP26 : (Group 26 pm_lsource3) Data loaded from memory
+event:0X1A2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L35_GRP26 : (Group 26 pm_lsource3) Data loaded from L3.5
+event:0X1A3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP26 : (Group 26 pm_lsource3) Data loaded from L2
+event:0X1A4 counters:4 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP26 : (Group 26 pm_lsource3) L1 reload data source valid
+event:0X1A5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP26 : (Group 26 pm_lsource3) Processor cycles
+event:0X1A6 counters:6 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP26 : (Group 26 pm_lsource3) Data loaded from L2.75 modified
+event:0X1A7 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP26 : (Group 26 pm_lsource3) Instructions completed
+
+#Group 27 pm_isource2, Instruction Source information
+event:0X1B0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP27 : (Group 27 pm_isource2) Instructions completed
+event:0X1B1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP27 : (Group 27 pm_isource2) Processor cycles
+event:0X1B2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP27 : (Group 27 pm_isource2) Instructions fetched from L2
+event:0X1B3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L35_GRP27 : (Group 27 pm_isource2) Instructions fetched from L3.5
+event:0X1B4 counters:4 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP27 : (Group 27 pm_isource2) Instruction fetched from L3
+event:0X1B5 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP27 : (Group 27 pm_isource2) Instruction fetched from L1
+event:0X1B6 counters:6 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP27 : (Group 27 pm_isource2) Instructions fetched from prefetch
+event:0X1B7 counters:7 um:zero minimum:1000 name:PM_0INST_FETCH_GRP27 : (Group 27 pm_isource2) No instructions fetched
+
+#Group 28 pm_isource3, Instruction Source information
+event:0X1C0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_MEM_GRP28 : (Group 28 pm_isource3) Instruction fetched from memory
+event:0X1C1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_L275_GRP28 : (Group 28 pm_isource3) Instruction fetched from L2.5/L2.75
+event:0X1C2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP28 : (Group 28 pm_isource3) Instructions fetched from L2
+event:0X1C3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L35_GRP28 : (Group 28 pm_isource3) Instructions fetched from L3.5
+event:0X1C4 counters:4 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP28 : (Group 28 pm_isource3) Instruction fetched from L3
+event:0X1C5 counters:5 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP28 : (Group 28 pm_isource3) Instruction fetched from L1
+event:0X1C6 counters:6 um:zero minimum:10000 name:PM_CYC_GRP28 : (Group 28 pm_isource3) Processor cycles
+event:0X1C7 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_isource3) Instructions completed
+
+#Group 29 pm_fpu3, Floating Point events by unit
+event:0X1D0 counters:0 um:zero minimum:1000 name:PM_FPU0_FDIV_GRP29 : (Group 29 pm_fpu3) FPU0 executed FDIV instruction
+event:0X1D1 counters:1 um:zero minimum:1000 name:PM_FPU1_FDIV_GRP29 : (Group 29 pm_fpu3) FPU1 executed FDIV instruction
+event:0X1D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP29 : (Group 29 pm_fpu3) FPU0 executed FRSP or FCONV instructions
+event:0X1D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP29 : (Group 29 pm_fpu3) FPU1 executed FRSP or FCONV instructions
+event:0X1D4 counters:4 um:zero minimum:1000 name:PM_FPU0_FMA_GRP29 : (Group 29 pm_fpu3) FPU0 executed multiply-add instruction
+event:0X1D5 counters:5 um:zero minimum:1000 name:PM_FPU1_FMA_GRP29 : (Group 29 pm_fpu3) FPU1 executed multiply-add instruction
+event:0X1D6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP29 : (Group 29 pm_fpu3) Instructions completed
+event:0X1D7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP29 : (Group 29 pm_fpu3) Processor cycles
+
+#Group 30 pm_fpu4, Floating Point events by unit
+event:0X1E0 counters:0 um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP30 : (Group 30 pm_fpu4) FPU0 executed FSQRT instruction
+event:0X1E1 counters:1 um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP30 : (Group 30 pm_fpu4) FPU1 executed FSQRT instruction
+event:0X1E2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP30 : (Group 30 pm_fpu4) FPU0 produced a result
+event:0X1E3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP30 : (Group 30 pm_fpu4) FPU1 produced a result
+event:0X1E4 counters:4 um:zero minimum:1000 name:PM_FPU0_ALL_GRP30 : (Group 30 pm_fpu4) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X1E5 counters:5 um:zero minimum:1000 name:PM_FPU1_ALL_GRP30 : (Group 30 pm_fpu4) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X1E6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP30 : (Group 30 pm_fpu4) Instructions completed
+event:0X1E7 counters:7 um:zero minimum:10000 name:PM_CYC_GRP30 : (Group 30 pm_fpu4) Processor cycles
+
+#Group 31 pm_fpu5, Floating Point events by unit
+event:0X1F0 counters:0 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP31 : (Group 31 pm_fpu5) FPU0 received denormalized data
+event:0X1F1 counters:1 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP31 : (Group 31 pm_fpu5) FPU1 received denormalized data
+event:0X1F2 counters:2 um:zero minimum:1000 name:PM_FPU0_FMOV_FEST_GRP31 : (Group 31 pm_fpu5) FPU0 executed FMOV or FEST instructions
+event:0X1F3 counters:3 um:zero minimum:1000 name:PM_FPU1_FMOV_FEST_GRP31 : (Group 31 pm_fpu5) FPU1 executing FMOV or FEST instructions
+event:0X1F4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP31 : (Group 31 pm_fpu5) Processor cycles
+event:0X1F5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_fpu5) Instructions completed
+event:0X1F6 counters:6 um:zero minimum:1000 name:PM_FPU0_FEST_GRP31 : (Group 31 pm_fpu5) FPU0 executed FEST instruction
+event:0X1F7 counters:7 um:zero minimum:1000 name:PM_FPU1_FEST_GRP31 : (Group 31 pm_fpu5) FPU1 executed FEST instruction
+
+#Group 32 pm_fpu6, Floating Point events by unit
+event:0X200 counters:0 um:zero minimum:1000 name:PM_FPU0_SINGLE_GRP32 : (Group 32 pm_fpu6) FPU0 executed single precision instruction
+event:0X201 counters:1 um:zero minimum:1000 name:PM_FPU1_SINGLE_GRP32 : (Group 32 pm_fpu6) FPU1 executed single precision instruction
+event:0X202 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP32 : (Group 32 pm_fpu6) LSU0 executed Floating Point load instruction
+event:0X203 counters:3 um:zero minimum:1000 name:PM_LSU1_LDF_GRP32 : (Group 32 pm_fpu6) LSU1 executed Floating Point load instruction
+event:0X204 counters:4 um:zero minimum:1000 name:PM_FPU0_STF_GRP32 : (Group 32 pm_fpu6) FPU0 executed store instruction
+event:0X205 counters:5 um:zero minimum:1000 name:PM_FPU1_STF_GRP32 : (Group 32 pm_fpu6) FPU1 executed store instruction
+event:0X206 counters:6 um:zero minimum:10000 name:PM_CYC_GRP32 : (Group 32 pm_fpu6) Processor cycles
+event:0X207 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_fpu6) Instructions completed
+
+#Group 33 pm_fpu7, Floating Point events by unit
+event:0X210 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP33 : (Group 33 pm_fpu7) FPU0 stalled in pipe3
+event:0X211 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP33 : (Group 33 pm_fpu7) FPU1 stalled in pipe3
+event:0X212 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP33 : (Group 33 pm_fpu7) FPU0 produced a result
+event:0X213 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP33 : (Group 33 pm_fpu7) FPU1 produced a result
+event:0X214 counters:4 um:zero minimum:10000 name:PM_CYC_GRP33 : (Group 33 pm_fpu7) Processor cycles
+event:0X215 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP33 : (Group 33 pm_fpu7) Instructions completed
+event:0X216 counters:6 um:zero minimum:10000 name:PM_CYC_GRP33 : (Group 33 pm_fpu7) Processor cycles
+event:0X217 counters:7 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP33 : (Group 33 pm_fpu7) FPU0 executed FPSCR instruction
+
+#Group 34 pm_fxu, Fix Point Unit events
+event:0X220 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP34 : (Group 34 pm_fxu) Instructions completed
+event:0X221 counters:1 um:zero minimum:10000 name:PM_CYC_GRP34 : (Group 34 pm_fxu) Processor cycles
+event:0X222 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP34 : (Group 34 pm_fxu) FXU produced a result
+event:0X223 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP34 : (Group 34 pm_fxu) FXU1 busy FXU0 idle
+event:0X224 counters:4 um:zero minimum:1000 name:PM_FXU_IDLE_GRP34 : (Group 34 pm_fxu) FXU idle
+event:0X225 counters:5 um:zero minimum:1000 name:PM_FXU_BUSY_GRP34 : (Group 34 pm_fxu) FXU busy
+event:0X226 counters:6 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP34 : (Group 34 pm_fxu) FXU0 busy FXU1 idle
+event:0X227 counters:7 um:zero minimum:1000 name:PM_FXLS_FULL_CYC_GRP34 : (Group 34 pm_fxu) Cycles FXLS queue is full
+
+#Group 35 pm_lsu_lmq, LSU Load Miss Queue Events
+event:0X230 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_LHR_MERGE_GRP35 : (Group 35 pm_lsu_lmq) LMQ LHR merges
+event:0X231 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP35 : (Group 35 pm_lsu_lmq) Cycles LMQ full
+event:0X232 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP35 : (Group 35 pm_lsu_lmq) LMQ slot 0 allocated
+event:0X233 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP35 : (Group 35 pm_lsu_lmq) LMQ slot 0 valid
+event:0X234 counters:4 um:zero minimum:10000 name:PM_CYC_GRP35 : (Group 35 pm_lsu_lmq) Processor cycles
+event:0X235 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP35 : (Group 35 pm_lsu_lmq) Instructions completed
+event:0X236 counters:6 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP35 : (Group 35 pm_lsu_lmq) SRQ sync duration
+event:0X237 counters:7 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP35 : (Group 35 pm_lsu_lmq) Cycles doing data tablewalks
+
+#Group 36 pm_lsu_flush, LSU Flush Events
+event:0X240 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP36 : (Group 36 pm_lsu_flush) LSU0 LRQ flushes
+event:0X241 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP36 : (Group 36 pm_lsu_flush) LSU1 LRQ flushes
+event:0X242 counters:2 um:zero minimum:10000 name:PM_CYC_GRP36 : (Group 36 pm_lsu_flush) Processor cycles
+event:0X243 counters:3 um:zero minimum:10000 name:PM_CYC_GRP36 : (Group 36 pm_lsu_flush) Processor cycles
+event:0X244 counters:4 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP36 : (Group 36 pm_lsu_flush) LSU0 SRQ flushes
+event:0X245 counters:5 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP36 : (Group 36 pm_lsu_flush) LSU1 SRQ flushes
+event:0X246 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP36 : (Group 36 pm_lsu_flush) Instructions completed
+event:0X247 counters:7 um:zero minimum:10000 name:PM_CYC_GRP36 : (Group 36 pm_lsu_flush) Processor cycles
+
+#Group 37 pm_lsu_load1, LSU Load Events
+event:0X250 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_load1) LSU0 unaligned load flushes
+event:0X251 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP37 : (Group 37 pm_lsu_load1) LSU1 unaligned load flushes
+event:0X252 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_GRP37 : (Group 37 pm_lsu_load1) LSU0 L1 D cache load references
+event:0X253 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_GRP37 : (Group 37 pm_lsu_load1) LSU1 L1 D cache load references
+event:0X254 counters:4 um:zero minimum:10000 name:PM_CYC_GRP37 : (Group 37 pm_lsu_load1) Processor cycles
+event:0X255 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP37 : (Group 37 pm_lsu_load1) Instructions completed
+event:0X256 counters:6 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP37 : (Group 37 pm_lsu_load1) LSU0 L1 D cache load misses
+event:0X257 counters:7 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP37 : (Group 37 pm_lsu_load1) LSU1 L1 D cache load misses
+
+#Group 38 pm_lsu_store1, LSU Store Events
+event:0X260 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP38 : (Group 38 pm_lsu_store1) LSU0 unaligned store flushes
+event:0X261 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP38 : (Group 38 pm_lsu_store1) LSU1 unaligned store flushes
+event:0X262 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP38 : (Group 38 pm_lsu_store1) LSU0 L1 D cache store references
+event:0X263 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP38 : (Group 38 pm_lsu_store1) LSU1 L1 D cache store references
+event:0X264 counters:4 um:zero minimum:10000 name:PM_CYC_GRP38 : (Group 38 pm_lsu_store1) Processor cycles
+event:0X265 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP38 : (Group 38 pm_lsu_store1) Instructions completed
+event:0X266 counters:6 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP38 : (Group 38 pm_lsu_store1) L1 D cache store misses
+event:0X267 counters:7 um:zero minimum:1000 name:PM_DC_INV_L2_GRP38 : (Group 38 pm_lsu_store1) L1 D cache entries invalidated from L2
+
+#Group 39 pm_lsu_store2, LSU Store Events
+event:0X270 counters:0 um:zero minimum:1000 name:PM_LSU0_SRQ_STFWD_GRP39 : (Group 39 pm_lsu_store2) LSU0 SRQ store forwarded
+event:0X271 counters:1 um:zero minimum:1000 name:PM_LSU1_SRQ_STFWD_GRP39 : (Group 39 pm_lsu_store2) LSU1 SRQ store forwarded
+event:0X272 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP39 : (Group 39 pm_lsu_store2) LSU0 L1 D cache store references
+event:0X273 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP39 : (Group 39 pm_lsu_store2) LSU1 L1 D cache store references
+event:0X274 counters:4 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP39 : (Group 39 pm_lsu_store2) L1 D cache store misses
+event:0X275 counters:5 um:zero minimum:10000 name:PM_CYC_GRP39 : (Group 39 pm_lsu_store2) Processor cycles
+event:0X276 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_lsu_store2) Instructions completed
+event:0X277 counters:7 um:zero minimum:10000 name:PM_CYC_GRP39 : (Group 39 pm_lsu_store2) Processor cycles
+
+#Group 40 pm_lsu7, Information on the Load Store Unit
+event:0X280 counters:0 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP40 : (Group 40 pm_lsu7) LSU0 DERAT misses
+event:0X281 counters:1 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP40 : (Group 40 pm_lsu7) LSU1 DERAT misses
+event:0X282 counters:2 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_lsu7) Processor cycles
+event:0X283 counters:3 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_lsu7) Processor cycles
+event:0X284 counters:4 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP40 : (Group 40 pm_lsu7) L1 reload data source valid
+event:0X285 counters:5 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_lsu7) Processor cycles
+event:0X286 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP40 : (Group 40 pm_lsu7) Instructions completed
+event:0X287 counters:7 um:zero minimum:10000 name:PM_CYC_GRP40 : (Group 40 pm_lsu7) Processor cycles
+
+#Group 41 pm_dpfetch, Data Prefetch Events
+event:0X290 counters:0 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_GRP41 : (Group 41 pm_dpfetch) D cache new prefetch stream allocated
+event:0X291 counters:1 um:zero minimum:1000 name:PM_DC_PREF_L2_CLONE_L3_GRP41 : (Group 41 pm_dpfetch) L2 prefetch cloned with L3
+event:0X292 counters:2 um:zero minimum:1000 name:PM_L2_PREF_GRP41 : (Group 41 pm_dpfetch) L2 cache prefetches
+event:0X293 counters:3 um:zero minimum:1000 name:PM_L1_PREF_GRP41 : (Group 41 pm_dpfetch) L1 cache data prefetches
+event:0X294 counters:4 um:zero minimum:10000 name:PM_CYC_GRP41 : (Group 41 pm_dpfetch) Processor cycles
+event:0X295 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP41 : (Group 41 pm_dpfetch) Instructions completed
+event:0X296 counters:6 um:zero minimum:10000 name:PM_CYC_GRP41 : (Group 41 pm_dpfetch) Processor cycles
+event:0X297 counters:7 um:zero minimum:1000 name:PM_DC_PREF_OUT_STREAMS_GRP41 : (Group 41 pm_dpfetch) Out of prefetch streams
+
+#Group 42 pm_misc, Misc Events for testing
+event:0X2A0 counters:0 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP42 : (Group 42 pm_misc) Cycles GCT empty
+event:0X2A1 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP42 : (Group 42 pm_misc) Cycles LMQ and SRQ empty
+event:0X2A2 counters:2 um:zero minimum:1000 name:PM_HV_CYC_GRP42 : (Group 42 pm_misc) Hypervisor Cycles
+event:0X2A3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP42 : (Group 42 pm_misc) Processor cycles
+event:0X2A4 counters:4 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP42 : (Group 42 pm_misc) One or more PPC instruction completed
+event:0X2A5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP42 : (Group 42 pm_misc) Instructions completed
+event:0X2A6 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP42 : (Group 42 pm_misc) Group completed
+event:0X2A7 counters:7 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP42 : (Group 42 pm_misc) Time Base bit transition
+
+#Group 43 pm_mark1, Information on marked instructions
+event:0X2B0 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP43 : (Group 43 pm_mark1) Marked L1 D cache load misses
+event:0X2B1 counters:1 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP43 : (Group 43 pm_mark1) Threshold timeout
+event:0X2B2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP43 : (Group 43 pm_mark1) Processor cycles
+event:0X2B3 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP43 : (Group 43 pm_mark1) Marked group completed
+event:0X2B4 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP43 : (Group 43 pm_mark1) Group marked in IDU
+event:0X2B5 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP43 : (Group 43 pm_mark1) Marked group issued
+event:0X2B6 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP43 : (Group 43 pm_mark1) Marked instruction finished
+event:0X2B7 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP43 : (Group 43 pm_mark1) Instructions completed
+
+#Group 44 pm_mark2, Marked Instructions Processing Flow
+event:0X2C0 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP44 : (Group 44 pm_mark2) Marked group dispatched
+event:0X2C1 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction BRU processing finished
+event:0X2C2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP44 : (Group 44 pm_mark2) Processor cycles
+event:0X2C3 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction CRU processing finished
+event:0X2C4 counters:4 um:zero minimum:1000 name:PM_GRP_MRK_GRP44 : (Group 44 pm_mark2) Group marked in IDU
+event:0X2C5 counters:5 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction FXU processing finished
+event:0X2C6 counters:6 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction FPU processing finished
+event:0X2C7 counters:7 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP44 : (Group 44 pm_mark2) Marked instruction LSU processing finished
+
+#Group 45 pm_mark3, Marked Stores Processing Flow
+event:0X2D0 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP45 : (Group 45 pm_mark3) Marked store instruction completed
+event:0X2D1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP45 : (Group 45 pm_mark3) Processor cycles
+event:0X2D2 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP45 : (Group 45 pm_mark3) Marked store completed with intervention
+event:0X2D3 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP45 : (Group 45 pm_mark3) Marked group completed
+event:0X2D4 counters:4 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP45 : (Group 45 pm_mark3) Marked group completion timeout
+event:0X2D5 counters:5 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP45 : (Group 45 pm_mark3) Marked store sent to GPS
+event:0X2D6 counters:6 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP45 : (Group 45 pm_mark3) Marked instruction valid in SRQ
+event:0X2D7 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_mark3) Instructions completed
+
+#Group 46 pm_mark4, Marked Loads Processing FLow
+event:0X2E0 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP46 : (Group 46 pm_mark4) Marked L1 D cache load misses
+event:0X2E1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP46 : (Group 46 pm_mark4) Processor cycles
+event:0X2E2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP46 : (Group 46 pm_mark4) Marked LRQ flushes
+event:0X2E3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_GRP46 : (Group 46 pm_mark4) Marked SRQ flushes
+event:0X2E4 counters:4 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP46 : (Group 46 pm_mark4) Marked group completion timeout
+event:0X2E5 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP46 : (Group 46 pm_mark4) Marked group issued
+event:0X2E6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP46 : (Group 46 pm_mark4) Instructions completed
+event:0X2E7 counters:7 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_ULD_GRP46 : (Group 46 pm_mark4) Marked unaligned load flushes
+
+#Group 47 pm_mark_lsource, Information on marked data source
+event:0X2F0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L3
+event:0X2F1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_MEM_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from memory
+event:0X2F2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L3.5
+event:0X2F3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2
+event:0X2F4 counters:4 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2.5 shared
+event:0X2F5 counters:5 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2.75 shared
+event:0X2F6 counters:6 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2.75 modified
+event:0X2F7 counters:7 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP47 : (Group 47 pm_mark_lsource) Marked data loaded from L2.5 modified
+
+#Group 48 pm_mark_lsource2, Information on marked data source
+event:0X300 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP48 : (Group 48 pm_mark_lsource2) Instructions completed
+event:0X301 counters:1 um:zero minimum:10000 name:PM_CYC_GRP48 : (Group 48 pm_mark_lsource2) Processor cycles
+event:0X302 counters:2 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP48 : (Group 48 pm_mark_lsource2) Marked L1 reload data source valid
+event:0X303 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2
+event:0X304 counters:4 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2.5 shared
+event:0X305 counters:5 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2.75 shared
+event:0X306 counters:6 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2.75 modified
+event:0X307 counters:7 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP48 : (Group 48 pm_mark_lsource2) Marked data loaded from L2.5 modified
+
+#Group 49 pm_mark_lsource3, Information on marked data source
+event:0X310 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from L3
+event:0X311 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_MEM_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from memory
+event:0X312 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from L3.5
+event:0X313 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from L2
+event:0X314 counters:4 um:zero minimum:10000 name:PM_CYC_GRP49 : (Group 49 pm_mark_lsource3) Processor cycles
+event:0X315 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_mark_lsource3) Instructions completed
+event:0X316 counters:6 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP49 : (Group 49 pm_mark_lsource3) Marked data loaded from L2.75 modified
+event:0X317 counters:7 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP49 : (Group 49 pm_mark_lsource3) Marked L1 reload data source valid
+
+#Group 50 pm_lsu_mark1, Load Store Unit Marked Events
+event:0X320 counters:0 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP50 : (Group 50 pm_lsu_mark1) Marked L1 D cache store misses
+event:0X321 counters:1 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP50 : (Group 50 pm_lsu_mark1) Marked IMR reloaded
+event:0X322 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_ULD_GRP50 : (Group 50 pm_lsu_mark1) LSU0 marked unaligned load flushes
+event:0X323 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_ULD_GRP50 : (Group 50 pm_lsu_mark1) LSU1 marked unaligned load flushes
+event:0X324 counters:4 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_lsu_mark1) Processor cycles
+event:0X325 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP50 : (Group 50 pm_lsu_mark1) Instructions completed
+event:0X326 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_UST_GRP50 : (Group 50 pm_lsu_mark1) LSU0 marked unaligned store flushes
+event:0X327 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_UST_GRP50 : (Group 50 pm_lsu_mark1) LSU1 marked unaligned store flushes
+
+#Group 51 pm_lsu_mark2, Load Store Unit Marked Events
+event:0X330 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU0_GRP51 : (Group 51 pm_lsu_mark2) LSU0 L1 D cache load misses
+event:0X331 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU1_GRP51 : (Group 51 pm_lsu_mark2) LSU1 L1 D cache load misses
+event:0X332 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_LRQ_GRP51 : (Group 51 pm_lsu_mark2) LSU0 marked LRQ flushes
+event:0X333 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_LRQ_GRP51 : (Group 51 pm_lsu_mark2) LSU1 marked LRQ flushes
+event:0X334 counters:4 um:zero minimum:10000 name:PM_CYC_GRP51 : (Group 51 pm_lsu_mark2) Processor cycles
+event:0X335 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP51 : (Group 51 pm_lsu_mark2) Instructions completed
+event:0X336 counters:6 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_SRQ_GRP51 : (Group 51 pm_lsu_mark2) LSU0 marked SRQ flushes
+event:0X337 counters:7 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_SRQ_GRP51 : (Group 51 pm_lsu_mark2) LSU1 marked SRQ flushes
+
+#Group 52 pm_lsu_mark3, Load Store Unit Marked Events
+event:0X340 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP52 : (Group 52 pm_lsu_mark3) Marked STCX failed
+event:0X341 counters:1 um:zero minimum:10000 name:PM_CYC_GRP52 : (Group 52 pm_lsu_mark3) Processor cycles
+event:0X342 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_INST_FIN_GRP52 : (Group 52 pm_lsu_mark3) LSU0 finished a marked instruction
+event:0X343 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_INST_FIN_GRP52 : (Group 52 pm_lsu_mark3) LSU1 finished a marked instruction
+event:0X344 counters:4 um:zero minimum:10000 name:PM_CYC_GRP52 : (Group 52 pm_lsu_mark3) Processor cycles
+event:0X345 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP52 : (Group 52 pm_lsu_mark3) Marked group issued
+event:0X346 counters:6 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP52 : (Group 52 pm_lsu_mark3) Marked instruction finished
+event:0X347 counters:7 um:zero minimum:10000 name:PM_INST_CMPL_GRP52 : (Group 52 pm_lsu_mark3) Instructions completed
+
+#Group 53 pm_threshold, Group for pipeline threshold studies
+event:0X350 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_LHR_MERGE_GRP53 : (Group 53 pm_threshold) LMQ LHR merges
+event:0X351 counters:1 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP53 : (Group 53 pm_threshold) Threshold timeout
+event:0X352 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP53 : (Group 53 pm_threshold) LMQ slot 0 valid
+event:0X353 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP53 : (Group 53 pm_threshold) Instructions completed
+event:0X354 counters:4 um:zero minimum:10000 name:PM_CYC_GRP53 : (Group 53 pm_threshold) Processor cycles
+event:0X355 counters:5 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP53 : (Group 53 pm_threshold) Marked group issued
+event:0X356 counters:6 um:zero minimum:1000 name:PM_GRP_CMPL_GRP53 : (Group 53 pm_threshold) Group completed
+event:0X357 counters:7 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP53 : (Group 53 pm_threshold) LMQ slot 0 allocated
+
+#Group 54 pm_pe_bench1, PE Benchmarker group for FP analysis
+event:0X360 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP54 : (Group 54 pm_pe_bench1) FPU executed FDIV instruction
+event:0X361 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP54 : (Group 54 pm_pe_bench1) FPU executed multiply-add instruction
+event:0X362 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP54 : (Group 54 pm_pe_bench1) FXU produced a result
+event:0X363 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP54 : (Group 54 pm_pe_bench1) FPU produced a result
+event:0X364 counters:4 um:zero minimum:10000 name:PM_CYC_GRP54 : (Group 54 pm_pe_bench1) Processor cycles
+event:0X365 counters:5 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP54 : (Group 54 pm_pe_bench1) FPU executed FSQRT instruction
+event:0X366 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP54 : (Group 54 pm_pe_bench1) Instructions completed
+event:0X367 counters:7 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP54 : (Group 54 pm_pe_bench1) FPU executing FMOV or FEST instructions
+
+#Group 55 pm_pe_bench2, PE Benchmarker group for FP stalls analysis
+event:0X370 counters:0 um:zero minimum:10000 name:PM_CYC_GRP55 : (Group 55 pm_pe_bench2) Processor cycles
+event:0X371 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP55 : (Group 55 pm_pe_bench2) FPU stalled in pipe3
+event:0X372 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP55 : (Group 55 pm_pe_bench2) FPU0 produced a result
+event:0X373 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP55 : (Group 55 pm_pe_bench2) Instructions completed
+event:0X374 counters:4 um:zero minimum:1000 name:PM_FPU_FULL_CYC_GRP55 : (Group 55 pm_pe_bench2) Cycles FPU issue queue full
+event:0X375 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP55 : (Group 55 pm_pe_bench2) FPU executed store instruction
+event:0X376 counters:6 um:zero minimum:1000 name:PM_FPU1_FIN_GRP55 : (Group 55 pm_pe_bench2) FPU1 produced a result
+event:0X377 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP55 : (Group 55 pm_pe_bench2) LSU executed Floating Point load instruction
+
+#Group 56 pm_pe_bench3, PE Benchmarker group for branch analysis
+event:0X380 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP56 : (Group 56 pm_pe_bench3) Instructions completed
+event:0X381 counters:1 um:zero minimum:1000 name:PM_BIQ_IDU_FULL_CYC_GRP56 : (Group 56 pm_pe_bench3) Cycles BIQ or IDU full
+event:0X382 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP56 : (Group 56 pm_pe_bench3) Branches issued
+event:0X383 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP56 : (Group 56 pm_pe_bench3) Branch mispredictions due CR bit setting
+event:0X384 counters:4 um:zero minimum:1000 name:PM_BRQ_FULL_CYC_GRP56 : (Group 56 pm_pe_bench3) Cycles branch queue full
+event:0X385 counters:5 um:zero minimum:10000 name:PM_CYC_GRP56 : (Group 56 pm_pe_bench3) Processor cycles
+event:0X386 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP56 : (Group 56 pm_pe_bench3) Branch mispredictions due to target address
+event:0X387 counters:7 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP56 : (Group 56 pm_pe_bench3) Cycles writing to instruction L1
+
+#Group 57 pm_pe_bench4, PE Benchmarker group for L1 and TLB analysis
+event:0X390 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP57 : (Group 57 pm_pe_bench4) Data TLB misses
+event:0X391 counters:1 um:zero minimum:1000 name:PM_ITLB_MISS_GRP57 : (Group 57 pm_pe_bench4) Instruction TLB misses
+event:0X392 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP57 : (Group 57 pm_pe_bench4) L1 D cache load misses
+event:0X393 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP57 : (Group 57 pm_pe_bench4) L1 D cache store misses
+event:0X394 counters:4 um:zero minimum:10000 name:PM_CYC_GRP57 : (Group 57 pm_pe_bench4) Processor cycles
+event:0X395 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP57 : (Group 57 pm_pe_bench4) Instructions completed
+event:0X396 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP57 : (Group 57 pm_pe_bench4) L1 D cache store references
+event:0X397 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP57 : (Group 57 pm_pe_bench4) L1 D cache load references
+
+#Group 58 pm_pe_bench5, PE Benchmarker group for L2 analysis
+event:0X3A0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP58 : (Group 58 pm_pe_bench5) Instructions completed
+event:0X3A1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP58 : (Group 58 pm_pe_bench5) Processor cycles
+event:0X3A2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L35_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L3.5
+event:0X3A3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2
+event:0X3A4 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2.5 shared
+event:0X3A5 counters:5 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2.75 shared
+event:0X3A6 counters:6 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2.75 modified
+event:0X3A7 counters:7 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP58 : (Group 58 pm_pe_bench5) Data loaded from L2.5 modified
+
+#Group 59 pm_pe_bench6, PE Benchmarker group for L3 analysis
+event:0X3B0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L3
+event:0X3B1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_MEM_GRP59 : (Group 59 pm_pe_bench6) Data loaded from memory
+event:0X3B2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L35_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L3.5
+event:0X3B3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L2
+event:0X3B4 counters:4 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L2.5 shared
+event:0X3B5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP59 : (Group 59 pm_pe_bench6) Processor cycles
+event:0X3B6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP59 : (Group 59 pm_pe_bench6) Instructions completed
+event:0X3B7 counters:7 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP59 : (Group 59 pm_pe_bench6) Data loaded from L2.5 modified
+
+#Group 60 pm_hpmcount1, Hpmcount group for L1 and TLB behavior analysis
+event:0X3C0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_GRP60 : (Group 60 pm_hpmcount1) Data TLB misses
+event:0X3C1 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP60 : (Group 60 pm_hpmcount1) Cycles LMQ and SRQ empty
+event:0X3C2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP60 : (Group 60 pm_hpmcount1) L1 D cache load misses
+event:0X3C3 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP60 : (Group 60 pm_hpmcount1) L1 D cache store misses
+event:0X3C4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP60 : (Group 60 pm_hpmcount1) Processor cycles
+event:0X3C5 counters:5 um:zero minimum:10000 name:PM_INST_CMPL_GRP60 : (Group 60 pm_hpmcount1) Instructions completed
+event:0X3C6 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP60 : (Group 60 pm_hpmcount1) L1 D cache store references
+event:0X3C7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP60 : (Group 60 pm_hpmcount1) L1 D cache load references
+
+#Group 61 pm_hpmcount2, Hpmcount group for computation intensity analysis
+event:0X3D0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP61 : (Group 61 pm_hpmcount2) FPU executed FDIV instruction
+event:0X3D1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP61 : (Group 61 pm_hpmcount2) FPU executed multiply-add instruction
+event:0X3D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP61 : (Group 61 pm_hpmcount2) FPU0 produced a result
+event:0X3D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP61 : (Group 61 pm_hpmcount2) FPU1 produced a result
+event:0X3D4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP61 : (Group 61 pm_hpmcount2) Processor cycles
+event:0X3D5 counters:5 um:zero minimum:1000 name:PM_FPU_STF_GRP61 : (Group 61 pm_hpmcount2) FPU executed store instruction
+event:0X3D6 counters:6 um:zero minimum:10000 name:PM_INST_CMPL_GRP61 : (Group 61 pm_hpmcount2) Instructions completed
+event:0X3D7 counters:7 um:zero minimum:1000 name:PM_LSU_LDF_GRP61 : (Group 61 pm_hpmcount2) LSU executed Floating Point load instruction
+
+#Group 62 pm_l1andbr, L1 misses and branch misspredict analysis
+event:0X3E0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP62 : (Group 62 pm_l1andbr) Instructions completed
+event:0X3E1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP62 : (Group 62 pm_l1andbr) Processor cycles
+event:0X3E2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP62 : (Group 62 pm_l1andbr) L1 D cache load misses
+event:0X3E3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP62 : (Group 62 pm_l1andbr) Branches issued
+event:0X3E4 counters:4 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP62 : (Group 62 pm_l1andbr) L1 D cache store misses
+event:0X3E5 counters:5 um:zero minimum:10000 name:PM_CYC_GRP62 : (Group 62 pm_l1andbr) Processor cycles
+event:0X3E6 counters:6 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP62 : (Group 62 pm_l1andbr) Branch mispredictions due CR bit setting
+event:0X3E7 counters:7 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP62 : (Group 62 pm_l1andbr) Branch mispredictions due to target address
+
+#Group 63 pm_imix, Instruction mix: loads, stores and branches
+event:0X3F0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP63 : (Group 63 pm_imix) Instructions completed
+event:0X3F1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP63 : (Group 63 pm_imix) Processor cycles
+event:0X3F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP63 : (Group 63 pm_imix) L1 D cache load misses
+event:0X3F3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP63 : (Group 63 pm_imix) Branches issued
+event:0X3F4 counters:4 um:zero minimum:10000 name:PM_CYC_GRP63 : (Group 63 pm_imix) Processor cycles
+event:0X3F5 counters:5 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP63 : (Group 63 pm_imix) L1 D cache store misses
+event:0X3F6 counters:6 um:zero minimum:1000 name:PM_ST_REF_L1_GRP63 : (Group 63 pm_imix) L1 D cache store references
+event:0X3F7 counters:7 um:zero minimum:1000 name:PM_LD_REF_L1_GRP63 : (Group 63 pm_imix) L1 D cache load references
diff --git a/events/ppc64/power4/unit_masks b/events/ppc64/power4/unit_masks
new file mode 100644
index 0000000..7643f05
--- /dev/null
+++ b/events/ppc64/power4/unit_masks
@@ -0,0 +1,5 @@
+# ppc64 POWER4 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+
diff --git a/events/ppc64/power5++/event_mappings b/events/ppc64/power5++/event_mappings
new file mode 100644
index 0000000..57ed17b
--- /dev/null
+++ b/events/ppc64/power5++/event_mappings
@@ -0,0 +1,1140 @@
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2007.
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>.
+#
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+
+#Group 0 with random sampling
+event:0X002 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X0010 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+event:0X0011 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+event:0X0012 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+event:0X0013 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+
+#Group 2 pm_completion, Completion and cycle counts
+event:0X0020 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X0021 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X0022 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X0023 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+
+#Group 3 pm_group_dispatch, Group dispatch events
+event:0X0030 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X0031 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X0032 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X0033 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+
+#Group 4 pm_clb1, CLB fullness
+event:0X0040 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X0041 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X0042 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X0043 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+
+#Group 5 pm_clb2, CLB fullness
+event:0X0050 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X0051 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X0052 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X0053 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+
+#Group 6 pm_gct_empty, GCT empty reasons
+event:0X0060 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X0061 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X0062 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X0063 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+
+#Group 7 pm_gct_usage, GCT Usage
+event:0X0070 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X0071 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X0072 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X0073 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+
+#Group 8 pm_lsu1, LSU LRQ and LMQ events
+event:0X0080 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+event:0X0081 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+event:0X0082 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+event:0X0083 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+
+#Group 9 pm_lsu2, LSU SRQ events
+event:0X0090 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+event:0X0091 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+event:0X0092 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+event:0X0093 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+
+#Group 10 pm_lsu3, LSU SRQ and LMQ events
+event:0X00A0 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+event:0X00A1 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+event:0X00A2 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+event:0X00A3 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+
+#Group 11 pm_lsu4, LSU SRQ and LMQ events
+event:0X00B0 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+event:0X00B1 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+event:0X00B2 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+event:0X00B3 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+
+#Group 12 pm_prefetch1, Prefetch stream allocation
+event:0X00C0 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+event:0X00C1 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+event:0X00C2 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+event:0X00C3 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+
+#Group 13 pm_prefetch2, Prefetch events
+event:0X00D0 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X00D1 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X00D2 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X00D3 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+
+#Group 14 pm_prefetch3, L2 prefetch and misc events
+event:0X00E0 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+event:0X00E1 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+event:0X00E2 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+event:0X00E3 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+
+#Group 15 pm_prefetch4, Misc prefetch and reject events
+event:0X00F0 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+event:0X00F1 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+event:0X00F2 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+event:0X00F3 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+
+#Group 16 pm_lsu_reject1, LSU reject events
+event:0X0100 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+event:0X0101 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+event:0X0102 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+event:0X0103 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+
+#Group 17 pm_lsu_reject2, LSU rejects due to reload CDF or tag update collision
+event:0X0110 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+event:0X0111 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+event:0X0112 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+event:0X0113 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+
+#Group 18 pm_lsu_reject3, LSU rejects due to ERAT, held instuctions
+event:0X0120 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+event:0X0121 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+event:0X0122 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+event:0X0123 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+
+#Group 19 pm_lsu_reject4, LSU0/1 reject LMQ full
+event:0X0130 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+event:0X0131 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+event:0X0132 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+event:0X0133 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+
+#Group 20 pm_lsu_reject5, LSU misc reject and flush events
+event:0X0140 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+event:0X0141 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+event:0X0142 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+event:0X0143 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+
+#Group 21 pm_flush1, Misc flush events
+event:0X0150 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X0151 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X0152 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X0153 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+
+#Group 22 pm_flush2, Flushes due to scoreboard and sync
+event:0X0160 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X0161 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X0162 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X0163 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+
+#Group 23 pm_lsu_flush_srq_lrq, LSU flush by SRQ and LRQ events
+event:0X0170 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X0171 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X0172 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X0173 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+
+#Group 24 pm_lsu_flush_lrq, LSU0/1 flush due to LRQ
+event:0X0180 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X0181 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X0182 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X0183 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+
+#Group 25 pm_lsu_flush_srq, LSU0/1 flush due to SRQ
+event:0X0190 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X0191 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X0192 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X0193 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+
+#Group 26 pm_lsu_flush_unaligned, LSU flush due to unaligned data
+event:0X01A0 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X01A1 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X01A2 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X01A3 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+
+#Group 27 pm_lsu_flush_uld, LSU0/1 flush due to unaligned load
+event:0X01B0 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X01B1 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X01B2 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X01B3 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+
+#Group 28 pm_lsu_flush_ust, LSU0/1 flush due to unaligned store
+event:0X01C0 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X01C1 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X01C2 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X01C3 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+
+#Group 29 pm_lsu_flush_full, LSU flush due to LRQ/SRQ full
+event:0X01D0 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X01D1 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X01D2 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X01D3 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+
+#Group 30 pm_lsu_stall1, LSU Stalls
+event:0X01E0 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X01E1 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X01E2 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X01E3 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+
+#Group 31 pm_lsu_stall2, LSU Stalls
+event:0X01F0 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X01F1 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X01F2 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X01F3 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+
+#Group 32 pm_fxu_stall, FXU Stalls
+event:0X0200 mmcr0:0X00000000 mmcr1:0X40000008CA320232 mmcra:0X00000001
+event:0X0201 mmcr0:0X00000000 mmcr1:0X40000008CA320232 mmcra:0X00000001
+event:0X0202 mmcr0:0X00000000 mmcr1:0X40000008CA320232 mmcra:0X00000001
+event:0X0203 mmcr0:0X00000000 mmcr1:0X40000008CA320232 mmcra:0X00000001
+
+#Group 33 pm_fpu_stall, FPU Stalls
+event:0X0210 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X0211 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X0212 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X0213 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+
+#Group 34 pm_queue_full, BRQ LRQ LMQ queue full
+event:0X0220 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X0221 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X0222 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X0223 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+
+#Group 35 pm_issueq_full, FPU FX full
+event:0X0230 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X0231 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X0232 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X0233 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+
+#Group 36 pm_mapper_full1, CR CTR GPR mapper full
+event:0X0240 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X0241 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X0242 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X0243 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+
+#Group 37 pm_mapper_full2, FPR XER mapper full
+event:0X0250 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X0251 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X0252 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X0253 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+
+#Group 38 pm_misc_load, Non-cachable loads and stcx events
+event:0X0260 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X0261 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X0262 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X0263 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+
+#Group 39 pm_ic_demand, ICache demand from BR redirect
+event:0X0270 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+event:0X0271 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+event:0X0272 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+event:0X0273 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+
+#Group 40 pm_ic_pref, ICache prefetch
+event:0X0280 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+event:0X0281 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+event:0X0282 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+event:0X0283 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+
+#Group 41 pm_ic_miss, ICache misses
+event:0X0290 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X0291 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X0292 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X0293 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+
+#Group 42 pm_branch_miss, Branch mispredict, TLB and SLB misses
+event:0X02A0 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X02A1 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X02A2 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X02A3 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+
+#Group 43 pm_branch1, Branch operations
+event:0X02B0 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+event:0X02B1 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+event:0X02B2 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+event:0X02B3 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+
+#Group 44 pm_branch2, Branch operations
+event:0X02C0 mmcr0:0X00000000 mmcr1:0X4000000C22CC8C02 mmcra:0X00000001
+event:0X02C1 mmcr0:0X00000000 mmcr1:0X4000000C22CC8C02 mmcra:0X00000001
+event:0X02C2 mmcr0:0X00000000 mmcr1:0X4000000C22CC8C02 mmcra:0X00000001
+event:0X02C3 mmcr0:0X00000000 mmcr1:0X4000000C22CC8C02 mmcra:0X00000001
+
+#Group 45 pm_L1_tlbmiss, L1 load and TLB misses
+event:0X02D0 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X02D1 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X02D2 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X02D3 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+
+#Group 46 pm_L1_DERAT_miss, L1 store and DERAT misses
+event:0X02E0 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+event:0X02E1 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+event:0X02E2 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+event:0X02E3 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+
+#Group 47 pm_L1_slbmiss, L1 load and SLB misses
+event:0X02F0 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X02F1 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X02F2 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X02F3 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+
+#Group 48 pm_dtlbref, Data TLB references
+event:0X0300 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+event:0X0301 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+event:0X0302 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+event:0X0303 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+
+#Group 49 pm_dtlbmiss, Data TLB misses
+event:0X0310 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+event:0X0311 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+event:0X0312 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+event:0X0313 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+
+#Group 50 pm_dtlb, Data TLB references and misses
+event:0X0320 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+event:0X0321 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+event:0X0322 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+event:0X0323 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+
+#Group 51 pm_L1_refmiss, L1 load references and misses and store references and misses
+event:0X0330 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+event:0X0331 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+event:0X0332 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+event:0X0333 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+
+#Group 52 pm_dsource1, L3 cache and memory data access
+event:0X0340 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+event:0X0341 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+event:0X0342 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+event:0X0343 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+
+#Group 53 pm_dsource2, L3 cache and memory data access
+event:0X0350 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+event:0X0351 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+event:0X0352 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+event:0X0353 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+
+#Group 54 pm_dsource_L2, L2 cache data access
+event:0X0360 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+event:0X0361 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+event:0X0362 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+event:0X0363 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+
+#Group 55 pm_dsource_L3, L3 cache data access
+event:0X0370 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+event:0X0371 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+event:0X0372 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+event:0X0373 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+
+#Group 56 pm_isource1, Instruction source information
+event:0X0380 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+event:0X0381 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+event:0X0382 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+event:0X0383 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+
+#Group 57 pm_isource2, Instruction source information
+event:0X0390 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+event:0X0391 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+event:0X0392 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+event:0X0393 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+
+#Group 58 pm_isource_L2, L2 instruction source information
+event:0X03A0 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+event:0X03A1 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+event:0X03A2 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+event:0X03A3 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+
+#Group 59 pm_isource_L3, L3 instruction source information
+event:0X03B0 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+event:0X03B1 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+event:0X03B2 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+event:0X03B3 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+
+#Group 60 pm_pteg_source1, PTEG source information
+event:0X03C0 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+event:0X03C1 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+event:0X03C2 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+event:0X03C3 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+
+#Group 61 pm_pteg_source2, PTEG source information
+event:0X03D0 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+event:0X03D1 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+event:0X03D2 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+event:0X03D3 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+
+#Group 62 pm_pteg_source3, PTEG source information
+event:0X03E0 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+event:0X03E1 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+event:0X03E2 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+event:0X03E3 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+
+#Group 63 pm_pteg_source4, L3 PTEG and group disptach events
+event:0X03F0 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+event:0X03F1 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+event:0X03F2 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+event:0X03F3 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+
+#Group 64 pm_L2SA_ld, L2 slice A load events
+event:0X0400 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X0401 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X0402 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X0403 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+
+#Group 65 pm_L2SA_st, L2 slice A store events
+event:0X0410 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X0411 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X0412 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X0413 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+
+#Group 66 pm_L2SA_st2, L2 slice A store events
+event:0X0420 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X0421 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X0422 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X0423 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+
+#Group 67 pm_L2SB_ld, L2 slice B load events
+event:0X0430 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X0431 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X0432 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X0433 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+
+#Group 68 pm_L2SB_st, L2 slice B store events
+event:0X0440 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+event:0X0441 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+event:0X0442 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+event:0X0443 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+
+#Group 69 pm_L2SB_st2, L2 slice B store events
+event:0X0450 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X0451 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X0452 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X0453 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+
+#Group 70 pm_L2SC_ld, L2 slice C load events
+event:0X0460 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X0461 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X0462 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X0463 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+
+#Group 71 pm_L2SC_st, L2 slice C store events
+event:0X0470 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+event:0X0471 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+event:0X0472 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+event:0X0473 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+
+#Group 72 pm_L2SC_st2, L2 slice C store events
+event:0X0480 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X0481 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X0482 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X0483 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+
+#Group 73 pm_L3SA_trans, L3 slice A state transistions
+event:0X0490 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X0491 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X0492 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X0493 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+
+#Group 74 pm_L3SB_trans, L3 slice B state transistions
+event:0X04A0 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X04A1 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X04A2 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X04A3 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+
+#Group 75 pm_L3SC_trans, L3 slice C state transistions
+event:0X04B0 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X04B1 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X04B2 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X04B3 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+
+#Group 76 pm_L2SA_trans, L2 slice A state transistions
+event:0X04C0 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X04C1 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X04C2 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X04C3 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+
+#Group 77 pm_L2SB_trans, L2 slice B state transistions
+event:0X04D0 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X04D1 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X04D2 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X04D3 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+
+#Group 78 pm_L2SC_trans, L2 slice C state transistions
+event:0X04E0 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X04E1 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X04E2 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X04E3 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+
+#Group 79 pm_L3SAB_retry, L3 slice A/B snoop retry and all CI/CO busy
+event:0X04F0 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X04F1 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X04F2 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X04F3 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+
+#Group 80 pm_L3SAB_hit, L3 slice A/B hit and reference
+event:0X0500 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X0501 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X0502 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X0503 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+
+#Group 81 pm_L3SC_retry_hit, L3 slice C hit & snoop retry
+event:0X0510 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X0511 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X0512 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X0513 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+
+#Group 82 pm_fpu1, Floating Point events
+event:0X0520 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X0521 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X0522 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X0523 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+
+#Group 83 pm_fpu2, Floating Point events
+event:0X0530 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X0531 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X0532 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X0533 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+
+#Group 84 pm_fpu3, Floating point events
+event:0X0540 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X0541 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X0542 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X0543 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+
+#Group 85 pm_fpu4, Floating point events
+event:0X0550 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X0551 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X0552 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X0553 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+
+#Group 86 pm_fpu5, Floating point events by unit
+event:0X0560 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X0561 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X0562 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X0563 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+
+#Group 87 pm_fpu6, Floating point events by unit
+event:0X0570 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X0571 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X0572 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X0573 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+
+#Group 88 pm_fpu7, Floating point events by unit
+event:0X0580 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X0581 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X0582 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X0583 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+
+#Group 89 pm_fpu8, Floating point events by unit
+event:0X0590 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X0591 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X0592 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X0593 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+
+#Group 90 pm_fpu9, Floating point events by unit
+event:0X05A0 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X05A1 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X05A2 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X05A3 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+
+#Group 91 pm_fpu10, Floating point events by unit
+event:0X05B0 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X05B1 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X05B2 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X05B3 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+
+#Group 92 pm_fpu11, Floating point events by unit
+event:0X05C0 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X05C1 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X05C2 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X05C3 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+
+#Group 93 pm_fpu12, Floating point events by unit
+event:0X05D0 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X05D1 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X05D2 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X05D3 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+
+#Group 94 pm_fxu1, Fixed Point events
+event:0X05E0 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X05E1 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X05E2 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X05E3 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+
+#Group 95 pm_fxu2, Fixed Point events
+event:0X05F0 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X05F1 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X05F2 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X05F3 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+
+#Group 96 pm_fxu3, Fixed Point events
+event:0X0600 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X0601 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X0602 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X0603 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+
+#Group 97 pm_smt_priorities1, Thread priority events
+event:0X0610 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X0611 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X0612 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X0613 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+
+#Group 98 pm_smt_priorities2, Thread priority events
+event:0X0620 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X0621 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X0622 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X0623 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+
+#Group 99 pm_smt_priorities3, Thread priority events
+event:0X0630 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X0631 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X0632 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X0633 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+
+#Group 100 pm_smt_priorities4, Thread priority events
+event:0X0640 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X0641 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X0642 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X0643 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+
+#Group 101 pm_smt_both, Thread common events
+event:0X0650 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X0651 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X0652 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X0653 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+
+#Group 102 pm_smt_selection, Thread selection
+event:0X0660 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X0661 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X0662 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X0663 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+
+#Group 103 pm_smt_selectover1, Thread selection overide
+event:0X0670 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X0671 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X0672 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X0673 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+
+#Group 104 pm_smt_selectover2, Thread selection overide
+event:0X0680 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X0681 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X0682 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X0683 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+
+#Group 105 pm_fabric1, Fabric events
+event:0X0690 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X0691 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X0692 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X0693 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+
+#Group 106 pm_fabric2, Fabric data movement
+event:0X06A0 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X06A1 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X06A2 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X06A3 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+
+#Group 107 pm_fabric3, Fabric data movement
+event:0X06B0 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X06B1 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X06B2 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X06B3 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+
+#Group 108 pm_fabric4, Fabric data movement
+event:0X06C0 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X06C1 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X06C2 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X06C3 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+
+#Group 109 pm_snoop1, Snoop retry
+event:0X06D0 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X06D1 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X06D2 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X06D3 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+
+#Group 110 pm_snoop2, Snoop read retry
+event:0X06E0 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X06E1 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X06E2 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X06E3 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+
+#Group 111 pm_snoop3, Snoop write retry
+event:0X06F0 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X06F1 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X06F2 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X06F3 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+
+#Group 112 pm_snoop4, Snoop partial write retry
+event:0X0700 mmcr0:0X00000000 mmcr1:0X30540E048CCC8CAC mmcra:0X00000000
+event:0X0701 mmcr0:0X00000000 mmcr1:0X30540E048CCC8CAC mmcra:0X00000000
+event:0X0702 mmcr0:0X00000000 mmcr1:0X30540E048CCC8CAC mmcra:0X00000000
+event:0X0703 mmcr0:0X00000000 mmcr1:0X30540E048CCC8CAC mmcra:0X00000000
+
+#Group 113 pm_mem_rq, Memory read queue dispatch
+event:0X0710 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X0711 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X0712 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X0713 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+
+#Group 114 pm_mem_read, Memory read complete and cancel
+event:0X0720 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X0721 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X0722 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X0723 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+
+#Group 115 pm_mem_wq, Memory write queue dispatch
+event:0X0730 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X0731 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X0732 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X0733 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+
+#Group 116 pm_mem_pwq, Memory partial write queue
+event:0X0740 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X0741 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X0742 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X0743 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+
+#Group 117 pm_threshold, Thresholding
+event:0X0750 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X0751 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X0752 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X0753 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+
+#Group 118 pm_mrk_grp1, Marked group events
+event:0X0760 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X0761 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X0762 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X0763 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+
+#Group 119 pm_mrk_grp2, Marked group events
+event:0X0770 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+event:0X0771 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+event:0X0772 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+event:0X0773 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+
+#Group 120 pm_mrk_dsource1, Marked data from
+event:0X0780 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+event:0X0781 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+event:0X0782 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+event:0X0783 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+
+#Group 121 pm_mrk_dsource2, Marked data from
+event:0X0790 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+event:0X0791 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+event:0X0792 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+event:0X0793 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+
+#Group 122 pm_mrk_dsource3, Marked data from
+event:0X07A0 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+event:0X07A1 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+event:0X07A2 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+event:0X07A3 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+
+#Group 123 pm_mrk_dsource4, Marked data from
+event:0X07B0 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+event:0X07B1 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+event:0X07B2 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+event:0X07B3 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+
+#Group 124 pm_mrk_dsource5, Marked data from
+event:0X07C0 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+event:0X07C1 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+event:0X07C2 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+event:0X07C3 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+
+#Group 125 pm_mrk_dsource6, Marked data from
+event:0X07D0 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+event:0X07D1 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+event:0X07D2 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+event:0X07D3 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+
+#Group 126 pm_mrk_dsource7, Marked data from
+event:0X07E0 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+event:0X07E1 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+event:0X07E2 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+event:0X07E3 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+
+#Group 127 pm_mrk_dtlbref, Marked data TLB references
+event:0X07F0 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+event:0X07F1 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+event:0X07F2 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+event:0X07F3 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+
+#Group 128 pm_mrk_dtlbmiss, Marked data TLB misses
+event:0X0800 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+event:0X0801 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+event:0X0802 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+event:0X0803 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+
+#Group 129 pm_mrk_dtlb_dslb, Marked data TLB references and misses and marked data SLB misses
+event:0X0810 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+event:0X0811 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+event:0X0812 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+event:0X0813 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+
+#Group 130 pm_mrk_lbref, Marked TLB and SLB references
+event:0X0820 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+event:0X0821 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+event:0X0822 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+event:0X0823 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+
+#Group 131 pm_mrk_lsmiss, Marked load and store miss
+event:0X0830 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X0831 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X0832 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X0833 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+
+#Group 132 pm_mrk_ulsflush, Mark unaligned load and store flushes
+event:0X0840 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X0841 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X0842 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X0843 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+
+#Group 133 pm_mrk_misc, Misc marked instructions
+event:0X0850 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X0851 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X0852 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X0853 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+
+#Group 134 pm_lsref_L1, Load/Store operations and L1 activity
+event:0X0860 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+event:0X0861 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+event:0X0862 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+event:0X0863 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+
+#Group 135 pm_lsref_L2L3, Load/Store operations and L2, L3 activity
+event:0X0870 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+event:0X0871 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+event:0X0872 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+event:0X0873 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+
+#Group 136 pm_lsref_tlbmiss, Load/Store operations and TLB misses
+event:0X0880 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X0881 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X0882 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X0883 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+
+#Group 137 pm_Dmiss, Data cache misses
+event:0X0890 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+event:0X0891 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+event:0X0892 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+event:0X0893 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+
+#Group 138 pm_prefetchX, Prefetch events
+event:0X08A0 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X08A1 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X08A2 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X08A3 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+
+#Group 139 pm_branchX, Branch operations
+event:0X08B0 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+event:0X08B1 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+event:0X08B2 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+event:0X08B3 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+
+#Group 140 pm_fpuX1, Floating point events by unit
+event:0X08C0 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X08C1 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X08C2 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X08C3 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+
+#Group 141 pm_fpuX2, Floating point events by unit
+event:0X08D0 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X08D1 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X08D2 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X08D3 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+
+#Group 142 pm_fpuX3, Floating point events by unit
+event:0X08E0 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X08E1 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X08E2 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X08E3 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+
+#Group 143 pm_fpuX4, Floating point and L1 events
+event:0X08F0 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X08F1 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X08F2 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X08F3 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+
+#Group 144 pm_fpuX5, Floating point events
+event:0X0900 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X0901 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X0902 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X0903 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+
+#Group 145 pm_fpuX6, Floating point events
+event:0X0910 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X0911 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X0912 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X0913 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+
+#Group 146 pm_fpuX7, Floating point events
+event:0X0920 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+event:0X0921 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+event:0X0922 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+event:0X0923 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+
+#Group 147 pm_hpmcount8, HPM group for set 9
+event:0X0930 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+event:0X0931 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+event:0X0932 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+event:0X0933 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+
+#Group 148 pm_hpmcount2, HPM group for set 2
+event:0X0940 mmcr0:0X00000000 mmcr1:0X0430000412201220 mmcra:0X00000000
+event:0X0941 mmcr0:0X00000000 mmcr1:0X0430000412201220 mmcra:0X00000000
+event:0X0942 mmcr0:0X00000000 mmcr1:0X0430000412201220 mmcra:0X00000000
+event:0X0943 mmcr0:0X00000000 mmcr1:0X0430000412201220 mmcra:0X00000000
+
+#Group 149 pm_hpmcount3, HPM group for set 3
+event:0X0950 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+event:0X0951 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+event:0X0952 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+event:0X0953 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+
+#Group 150 pm_hpmcount4, HPM group for set 7
+event:0X0960 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X0961 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X0962 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X0963 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+
+#Group 151 pm_flop, Floating point operations
+event:0X0970 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+event:0X0971 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+event:0X0972 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+event:0X0973 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+
+#Group 152 pm_eprof1, Group for use with eprof
+event:0X0980 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X0981 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X0982 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X0983 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+
+#Group 153 pm_eprof2, Group for use with eprof
+event:0X0990 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+event:0X0991 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+event:0X0992 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+event:0X0993 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+
+#Group 154 pm_flip, Group for flips
+event:0X09A0 mmcr0:0X00000000 mmcr1:0X000000021E105010 mmcra:0X00000000
+event:0X09A1 mmcr0:0X00000000 mmcr1:0X000000021E105010 mmcra:0X00000000
+event:0X09A2 mmcr0:0X00000000 mmcr1:0X000000021E105010 mmcra:0X00000000
+event:0X09A3 mmcr0:0X00000000 mmcr1:0X000000021E105010 mmcra:0X00000000
+
+#Group 155 pm_hpmcount5, HPM group for set 5
+event:0X09B0 mmcr0:0X00000000 mmcr1:0X00B000001E881020 mmcra:0X00000000
+event:0X09B1 mmcr0:0X00000000 mmcr1:0X00B000001E881020 mmcra:0X00000000
+event:0X09B2 mmcr0:0X00000000 mmcr1:0X00B000001E881020 mmcra:0X00000000
+event:0X09B3 mmcr0:0X00000000 mmcr1:0X00B000001E881020 mmcra:0X00000000
+
+#Group 156 pm_hpmcount6, HPM group for set 6
+event:0X09C0 mmcr0:0X00000000 mmcr1:0X003000001E122086 mmcra:0X00000000
+event:0X09C1 mmcr0:0X00000000 mmcr1:0X003000001E122086 mmcra:0X00000000
+event:0X09C2 mmcr0:0X00000000 mmcr1:0X003000001E122086 mmcra:0X00000000
+event:0X09C3 mmcr0:0X00000000 mmcr1:0X003000001E122086 mmcra:0X00000000
+
+#Group 157 pm_hpmcount7, HPM group for set 8
+event:0X09D0 mmcr0:0X00000000 mmcr1:0X00030005120E1E0E mmcra:0X00000000
+event:0X09D1 mmcr0:0X00000000 mmcr1:0X00030005120E1E0E mmcra:0X00000000
+event:0X09D2 mmcr0:0X00000000 mmcr1:0X00030005120E1E0E mmcra:0X00000000
+event:0X09D3 mmcr0:0X00000000 mmcr1:0X00030005120E1E0E mmcra:0X00000000
+
+#Group 158 pm_ep_threshold, Thresholding
+event:0X09E0 mmcr0:0X00000000 mmcr1:0X0000000004121628 mmcra:0X00000001
+event:0X09E1 mmcr0:0X00000000 mmcr1:0X0000000004121628 mmcra:0X00000001
+event:0X09E2 mmcr0:0X00000000 mmcr1:0X0000000004121628 mmcra:0X00000001
+event:0X09E3 mmcr0:0X00000000 mmcr1:0X0000000004121628 mmcra:0X00000001
+
+#Group 159 pm_ep_mrk_grp1, Marked group events
+event:0X09F0 mmcr0:0X00000000 mmcr1:0X0000000004120A26 mmcra:0X00000001
+event:0X09F1 mmcr0:0X00000000 mmcr1:0X0000000004120A26 mmcra:0X00000001
+event:0X09F2 mmcr0:0X00000000 mmcr1:0X0000000004120A26 mmcra:0X00000001
+event:0X09F3 mmcr0:0X00000000 mmcr1:0X0000000004120A26 mmcra:0X00000001
+
+#Group 160 pm_ep_mrk_grp2, Marked group events
+event:0X0A00 mmcr0:0X00000000 mmcr1:0X410300032A12C822 mmcra:0X00000001
+event:0X0A01 mmcr0:0X00000000 mmcr1:0X410300032A12C822 mmcra:0X00000001
+event:0X0A02 mmcr0:0X00000000 mmcr1:0X410300032A12C822 mmcra:0X00000001
+event:0X0A03 mmcr0:0X00000000 mmcr1:0X410300032A12C822 mmcra:0X00000001
+
+#Group 161 pm_ep_mrk_dsource1, Marked data from
+event:0X0A10 mmcr0:0X00000000 mmcr1:0X010B000B0E124444 mmcra:0X00000001
+event:0X0A11 mmcr0:0X00000000 mmcr1:0X010B000B0E124444 mmcra:0X00000001
+event:0X0A12 mmcr0:0X00000000 mmcr1:0X010B000B0E124444 mmcra:0X00000001
+event:0X0A13 mmcr0:0X00000000 mmcr1:0X010B000B0E124444 mmcra:0X00000001
+
+#Group 162 pm_ep_mrk_dsource2, Marked data from
+event:0X0A20 mmcr0:0X00000000 mmcr1:0X010B00082E12E410 mmcra:0X00000001
+event:0X0A21 mmcr0:0X00000000 mmcr1:0X010B00082E12E410 mmcra:0X00000001
+event:0X0A22 mmcr0:0X00000000 mmcr1:0X010B00082E12E410 mmcra:0X00000001
+event:0X0A23 mmcr0:0X00000000 mmcr1:0X010B00082E12E410 mmcra:0X00000001
+
+#Group 163 pm_ep_mrk_dsource3, Marked data from
+event:0X0A30 mmcr0:0X00000000 mmcr1:0X010B000712484C4C mmcra:0X00000001
+event:0X0A31 mmcr0:0X00000000 mmcr1:0X010B000712484C4C mmcra:0X00000001
+event:0X0A32 mmcr0:0X00000000 mmcr1:0X010B000712484C4C mmcra:0X00000001
+event:0X0A33 mmcr0:0X00000000 mmcr1:0X010B000712484C4C mmcra:0X00000001
+
+#Group 164 pm_ep_mrk_dsource4, Marked data from
+event:0X0A40 mmcr0:0X00000000 mmcr1:0X010B000712462E42 mmcra:0X00000001
+event:0X0A41 mmcr0:0X00000000 mmcr1:0X010B000712462E42 mmcra:0X00000001
+event:0X0A42 mmcr0:0X00000000 mmcr1:0X010B000712462E42 mmcra:0X00000001
+event:0X0A43 mmcr0:0X00000000 mmcr1:0X010B000712462E42 mmcra:0X00000001
+
+#Group 165 pm_ep_mrk_dsource5, Marked data from
+event:0X0A50 mmcr0:0X00000000 mmcr1:0X010B000B3C124040 mmcra:0X00000001
+event:0X0A51 mmcr0:0X00000000 mmcr1:0X010B000B3C124040 mmcra:0X00000001
+event:0X0A52 mmcr0:0X00000000 mmcr1:0X010B000B3C124040 mmcra:0X00000001
+event:0X0A53 mmcr0:0X00000000 mmcr1:0X010B000B3C124040 mmcra:0X00000001
+
+#Group 166 pm_ep_mrk_dsource6, Marked data from
+event:0X0A60 mmcr0:0X00000000 mmcr1:0X010B000512460246 mmcra:0X00000001
+event:0X0A61 mmcr0:0X00000000 mmcr1:0X010B000512460246 mmcra:0X00000001
+event:0X0A62 mmcr0:0X00000000 mmcr1:0X010B000512460246 mmcra:0X00000001
+event:0X0A63 mmcr0:0X00000000 mmcr1:0X010B000512460246 mmcra:0X00000001
+
+#Group 167 pm_ep_mrk_dsource7, Marked data from
+event:0X0A70 mmcr0:0X00000000 mmcr1:0X010B0007124E3C4E mmcra:0X00000001
+event:0X0A71 mmcr0:0X00000000 mmcr1:0X010B0007124E3C4E mmcra:0X00000001
+event:0X0A72 mmcr0:0X00000000 mmcr1:0X010B0007124E3C4E mmcra:0X00000001
+event:0X0A73 mmcr0:0X00000000 mmcr1:0X010B0007124E3C4E mmcra:0X00000001
+
+#Group 168 pm_ep_mrk_lbmiss, Marked TLB and SLB misses
+event:0X0A80 mmcr0:0X00000000 mmcr1:0X020C0007121A1A1A mmcra:0X00000001
+event:0X0A81 mmcr0:0X00000000 mmcr1:0X020C0007121A1A1A mmcra:0X00000001
+event:0X0A82 mmcr0:0X00000000 mmcr1:0X020C0007121A1A1A mmcra:0X00000001
+event:0X0A83 mmcr0:0X00000000 mmcr1:0X020C0007121A1A1A mmcra:0X00000001
+
+#Group 169 pm_ep_mrk_dtlbref, Marked data TLB references
+event:0X0A90 mmcr0:0X00000000 mmcr1:0X020C0007120C0C0C mmcra:0X00000001
+event:0X0A91 mmcr0:0X00000000 mmcr1:0X020C0007120C0C0C mmcra:0X00000001
+event:0X0A92 mmcr0:0X00000000 mmcr1:0X020C0007120C0C0C mmcra:0X00000001
+event:0X0A93 mmcr0:0X00000000 mmcr1:0X020C0007120C0C0C mmcra:0X00000001
+
+#Group 170 pm_ep_mrk_dtlbmiss, Marked data TLB misses
+event:0X0AA0 mmcr0:0X00000000 mmcr1:0X020C0007121A1A1A mmcra:0X00000001
+event:0X0AA1 mmcr0:0X00000000 mmcr1:0X020C0007121A1A1A mmcra:0X00000001
+event:0X0AA2 mmcr0:0X00000000 mmcr1:0X020C0007121A1A1A mmcra:0X00000001
+event:0X0AA3 mmcr0:0X00000000 mmcr1:0X020C0007121A1A1A mmcra:0X00000001
+
+#Group 171 pm_ep_mrk_lbref, Marked TLB and SLB references
+event:0X0AB0 mmcr0:0X00000000 mmcr1:0X063C000A0C120C8E mmcra:0X00000001
+event:0X0AB1 mmcr0:0X00000000 mmcr1:0X063C000A0C120C8E mmcra:0X00000001
+event:0X0AB2 mmcr0:0X00000000 mmcr1:0X063C000A0C120C8E mmcra:0X00000001
+event:0X0AB3 mmcr0:0X00000000 mmcr1:0X063C000A0C120C8E mmcra:0X00000001
+
+#Group 172 pm_ep_mrk_lsmiss, Marked load and store miss
+event:0X0AC0 mmcr0:0X00000000 mmcr1:0X000800081012060A mmcra:0X00000001
+event:0X0AC1 mmcr0:0X00000000 mmcr1:0X000800081012060A mmcra:0X00000001
+event:0X0AC2 mmcr0:0X00000000 mmcr1:0X000800081012060A mmcra:0X00000001
+event:0X0AC3 mmcr0:0X00000000 mmcr1:0X000800081012060A mmcra:0X00000001
+
+#Group 173 pm_ep_mrk_ulsflush, Mark unaligned load and store flushes
+event:0X0AD0 mmcr0:0X00000000 mmcr1:0X0020000006122020 mmcra:0X00000001
+event:0X0AD1 mmcr0:0X00000000 mmcr1:0X0020000006122020 mmcra:0X00000001
+event:0X0AD2 mmcr0:0X00000000 mmcr1:0X0020000006122020 mmcra:0X00000001
+event:0X0AD3 mmcr0:0X00000000 mmcr1:0X0020000006122020 mmcra:0X00000001
+
+#Group 174 pm_ep_mrk_misc1, Misc marked instructions
+event:0X0AE0 mmcr0:0X00000000 mmcr1:0X0000000012062816 mmcra:0X00000001
+event:0X0AE1 mmcr0:0X00000000 mmcr1:0X0000000012062816 mmcra:0X00000001
+event:0X0AE2 mmcr0:0X00000000 mmcr1:0X0000000012062816 mmcra:0X00000001
+event:0X0AE3 mmcr0:0X00000000 mmcr1:0X0000000012062816 mmcra:0X00000001
+
+#Group 175 pm_ep_mrk_misc2, Misc marked instructions
+event:0X0AF0 mmcr0:0X00000000 mmcr1:0X010B000612445EE4 mmcra:0X00000001
+event:0X0AF1 mmcr0:0X00000000 mmcr1:0X010B000612445EE4 mmcra:0X00000001
+event:0X0AF2 mmcr0:0X00000000 mmcr1:0X010B000612445EE4 mmcra:0X00000001
+event:0X0AF3 mmcr0:0X00000000 mmcr1:0X010B000612445EE4 mmcra:0X00000001
+
+#Group 176 pm_ep_mrk_misc3, Misc marked instructions
+event:0X0B00 mmcr0:0X00000000 mmcr1:0X053B0005124C8C0E mmcra:0X00000001
+event:0X0B01 mmcr0:0X00000000 mmcr1:0X053B0005124C8C0E mmcra:0X00000001
+event:0X0B02 mmcr0:0X00000000 mmcr1:0X053B0005124C8C0E mmcra:0X00000001
+event:0X0B03 mmcr0:0X00000000 mmcr1:0X053B0005124C8C0E mmcra:0X00000001
+
+#Group 177 pm_ep_mrk_misc4, Misc marked instructions
+event:0X0B10 mmcr0:0X00000000 mmcr1:0X030F00091A12E82E mmcra:0X00000001
+event:0X0B11 mmcr0:0X00000000 mmcr1:0X030F00091A12E82E mmcra:0X00000001
+event:0X0B12 mmcr0:0X00000000 mmcr1:0X030F00091A12E82E mmcra:0X00000001
+event:0X0B13 mmcr0:0X00000000 mmcr1:0X030F00091A12E82E mmcra:0X00000001
+
+#Group 178 pm_ep_mrk_misc5, Misc marked instructions
+event:0X0B20 mmcr0:0X00000000 mmcr1:0X022C00080C120286 mmcra:0X00000001
+event:0X0B21 mmcr0:0X00000000 mmcr1:0X022C00080C120286 mmcra:0X00000001
+event:0X0B22 mmcr0:0X00000000 mmcr1:0X022C00080C120286 mmcra:0X00000001
+event:0X0B23 mmcr0:0X00000000 mmcr1:0X022C00080C120286 mmcra:0X00000001
+
+#Group 179 pm_ep_mrk_misc6, Misc marked instructions
+event:0X0B30 mmcr0:0X00000000 mmcr1:0X022C00081A12888A mmcra:0X00000001
+event:0X0B31 mmcr0:0X00000000 mmcr1:0X022C00081A12888A mmcra:0X00000001
+event:0X0B32 mmcr0:0X00000000 mmcr1:0X022C00081A12888A mmcra:0X00000001
+event:0X0B33 mmcr0:0X00000000 mmcr1:0X022C00081A12888A mmcra:0X00000001
+
+#Group 180 pm_ep_mrk_misc7, Misc marked instructions
+event:0X0B40 mmcr0:0X00000000 mmcr1:0X012B000412408280 mmcra:0X00000001
+event:0X0B41 mmcr0:0X00000000 mmcr1:0X012B000412408280 mmcra:0X00000001
+event:0X0B42 mmcr0:0X00000000 mmcr1:0X012B000412408280 mmcra:0X00000001
+event:0X0B43 mmcr0:0X00000000 mmcr1:0X012B000412408280 mmcra:0X00000001
+
+#Group 181 pm_ep_mrk_misc8, Misc marked instructions
+event:0X0B50 mmcr0:0X00000000 mmcr1:0X00200000120A8486 mmcra:0X00000001
+event:0X0B51 mmcr0:0X00000000 mmcr1:0X00200000120A8486 mmcra:0X00000001
+event:0X0B52 mmcr0:0X00000000 mmcr1:0X00200000120A8486 mmcra:0X00000001
+event:0X0B53 mmcr0:0X00000000 mmcr1:0X00200000120A8486 mmcra:0X00000001
+
+#Group 182 pm_ep_mrk_misc9, Misc marked instructions
+event:0X0B60 mmcr0:0X00000000 mmcr1:0X0028000012AC8EEC mmcra:0X00000001
+event:0X0B61 mmcr0:0X00000000 mmcr1:0X0028000012AC8EEC mmcra:0X00000001
+event:0X0B62 mmcr0:0X00000000 mmcr1:0X0028000012AC8EEC mmcra:0X00000001
+event:0X0B63 mmcr0:0X00000000 mmcr1:0X0028000012AC8EEC mmcra:0X00000001
+
+#Group 183 pm_ep_mrk_misc10, Misc marked instructions
+event:0X0B70 mmcr0:0X00000000 mmcr1:0X0008000412C0E8E6 mmcra:0X00000001
+event:0X0B71 mmcr0:0X00000000 mmcr1:0X0008000412C0E8E6 mmcra:0X00000001
+event:0X0B72 mmcr0:0X00000000 mmcr1:0X0008000412C0E8E6 mmcra:0X00000001
+event:0X0B73 mmcr0:0X00000000 mmcr1:0X0008000412C0E8E6 mmcra:0X00000001
+
+#Group 184 pm_ep_mrk_misc11, Misc marked instructions
+event:0X0B80 mmcr0:0X00000000 mmcr1:0X01030003120A443C mmcra:0X00000001
+event:0X0B81 mmcr0:0X00000000 mmcr1:0X01030003120A443C mmcra:0X00000001
+event:0X0B82 mmcr0:0X00000000 mmcr1:0X01030003120A443C mmcra:0X00000001
+event:0X0B83 mmcr0:0X00000000 mmcr1:0X01030003120A443C mmcra:0X00000001
+
+#Group 185 pm_ep_mrk_misc12, Misc marked instructions
+event:0X0B90 mmcr0:0X00000000 mmcr1:0X0020000012501010 mmcra:0X00000001
+event:0X0B91 mmcr0:0X00000000 mmcr1:0X0020000012501010 mmcra:0X00000001
+event:0X0B92 mmcr0:0X00000000 mmcr1:0X0020000012501010 mmcra:0X00000001
+event:0X0B93 mmcr0:0X00000000 mmcr1:0X0020000012501010 mmcra:0X00000001
+
+#Group 186 pm_ep_mrk_misc13, Misc marked instructions
+event:0X0BA0 mmcr0:0X00000000 mmcr1:0X0103000B0E1236CC mmcra:0X00000001
+event:0X0BA1 mmcr0:0X00000000 mmcr1:0X0103000B0E1236CC mmcra:0X00000001
+event:0X0BA2 mmcr0:0X00000000 mmcr1:0X0103000B0E1236CC mmcra:0X00000001
+event:0X0BA3 mmcr0:0X00000000 mmcr1:0X0103000B0E1236CC mmcra:0X00000001
+
+#Group 187 pm_ep_mrk_misc14, Misc marked instructions
+event:0X0BB0 mmcr0:0X00000000 mmcr1:0X0000000012282828 mmcra:0X00000001
+event:0X0BB1 mmcr0:0X00000000 mmcr1:0X0000000012282828 mmcra:0X00000001
+event:0X0BB2 mmcr0:0X00000000 mmcr1:0X0000000012282828 mmcra:0X00000001
+event:0X0BB3 mmcr0:0X00000000 mmcr1:0X0000000012282828 mmcra:0X00000001
+
+#Group 188 pm_ep_mrk_misc15, Misc marked instructions
+event:0X0BC0 mmcr0:0X00000000 mmcr1:0X4000000412220A26 mmcra:0X00000001
+event:0X0BC1 mmcr0:0X00000000 mmcr1:0X4000000412220A26 mmcra:0X00000001
+event:0X0BC2 mmcr0:0X00000000 mmcr1:0X4000000412220A26 mmcra:0X00000001
+event:0X0BC3 mmcr0:0X00000000 mmcr1:0X4000000412220A26 mmcra:0X00000001
diff --git a/events/ppc64/power5++/events b/events/ppc64/power5++/events
new file mode 100644
index 0000000..e4d055b
--- /dev/null
+++ b/events/ppc64/power5++/events
@@ -0,0 +1,1151 @@
+#PPC64 POWER5++ events
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2007.
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>.
+#
+#
+# Within each group the event names must be unique. Each event in a group is
+# assigned to a unique counter. The groups are from the groups defined in the
+# Performance Monitor Unit user guide for this processor.
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:1 um:zero minimum:10000 name:CYCLES : Processor Cycles
+
+#Group 0 with random sampling
+event:0X002 counters:2 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
+
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X0010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
+event:0X0011 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Instructions completed
+event:0X0012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
+event:0X0013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
+
+#Group 2 pm_completion, Completion and cycle counts
+event:0X0020 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP2 : (Group 2 pm_completion) One or more PPC instruction completed
+event:0X0021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empty
+event:0X0022 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP2 : (Group 2 pm_completion) Group completed
+event:0X0023 counters:3 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_completion) Processor cycles
+
+#Group 3 pm_group_dispatch, Group dispatch events
+event:0X0030 counters:0 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP3 : (Group 3 pm_group_dispatch) Group dispatch valid
+event:0X0031 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP3 : (Group 3 pm_group_dispatch) Group dispatch rejected
+event:0X0032 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP3 : (Group 3 pm_group_dispatch) Cycles group dispatch blocked by scoreboard
+event:0X0033 counters:3 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_group_dispatch) Instructions dispatched
+
+#Group 4 pm_clb1, CLB fullness
+event:0X0040 counters:0 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles no instructions in CLB
+event:0X0041 counters:1 um:zero minimum:1000 name:PM_2INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles 2 instructions in CLB
+event:0X0042 counters:2 um:zero minimum:1000 name:PM_CLB_EMPTY_CYC_GRP4 : (Group 4 pm_clb1) Cycles CLB empty
+event:0X0043 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_CYC_GRP4 : (Group 4 pm_clb1) Marked load latency from L3.5 modified
+
+#Group 5 pm_clb2, CLB fullness
+event:0X0050 counters:0 um:zero minimum:1000 name:PM_5INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 5 instructions in CLB
+event:0X0051 counters:1 um:zero minimum:1000 name:PM_6INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 6 instructions in CLB
+event:0X0052 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP5 : (Group 5 pm_clb2) Marked instruction valid in SRQ
+event:0X0053 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP5 : (Group 5 pm_clb2) Internal operations completed
+
+#Group 6 pm_gct_empty, GCT empty reasons
+event:0X0060 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP6 : (Group 6 pm_gct_empty) Cycles no GCT slot allocated
+event:0X0061 counters:1 um:zero minimum:1000 name:PM_GCT_NOSLOT_IC_MISS_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by I cache miss
+event:0X0062 counters:2 um:zero minimum:1000 name:PM_GCT_NOSLOT_SRQ_FULL_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by SRQ full
+event:0X0063 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by branch mispredict
+
+#Group 7 pm_gct_usage, GCT Usage
+event:0X0070 counters:0 um:zero minimum:1000 name:PM_GCT_USAGE_00to59_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT less than 60% full
+event:0X0071 counters:1 um:zero minimum:1000 name:PM_GCT_USAGE_60to79_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT 60-79% full
+event:0X0072 counters:2 um:zero minimum:1000 name:PM_GCT_USAGE_80to99_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT 80-99% full
+event:0X0073 counters:3 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT full
+
+#Group 8 pm_lsu1, LSU LRQ and LMQ events
+event:0X0080 counters:0 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP8 : (Group 8 pm_lsu1) LRQ slot 0 allocated
+event:0X0081 counters:1 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP8 : (Group 8 pm_lsu1) LRQ slot 0 valid
+event:0X0082 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP8 : (Group 8 pm_lsu1) LMQ slot 0 allocated
+event:0X0083 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP8 : (Group 8 pm_lsu1) LMQ slot 0 valid
+
+#Group 9 pm_lsu2, LSU SRQ events
+event:0X0090 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP9 : (Group 9 pm_lsu2) SRQ slot 0 allocated
+event:0X0091 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP9 : (Group 9 pm_lsu2) SRQ slot 0 valid
+event:0X0092 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP9 : (Group 9 pm_lsu2) SRQ sync duration
+event:0X0093 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP9 : (Group 9 pm_lsu2) Cycles SRQ full
+
+#Group 10 pm_lsu3, LSU SRQ and LMQ events
+event:0X00A0 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_LHR_MERGE_GRP10 : (Group 10 pm_lsu3) LMQ LHR merges
+event:0X00A1 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_STFWD_GRP10 : (Group 10 pm_lsu3) SRQ store forwarded
+event:0X00A2 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP10 : (Group 10 pm_lsu3) Cycles LMQ and SRQ empty
+event:0X00A3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP10 : (Group 10 pm_lsu3) Cycles SRQ empty
+
+#Group 11 pm_lsu4, LSU SRQ and LMQ events
+event:0X00B0 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP11 : (Group 11 pm_lsu4) Cycles LMQ full
+event:0X00B1 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP11 : (Group 11 pm_lsu4) Cycles SRQ full
+event:0X00B2 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP11 : (Group 11 pm_lsu4) Cycles LMQ and SRQ empty
+event:0X00B3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP11 : (Group 11 pm_lsu4) Cycles SRQ empty
+
+#Group 12 pm_prefetch1, Prefetch stream allocation
+event:0X00C0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP12 : (Group 12 pm_prefetch1) Instruction fetched missed L2
+event:0X00C1 counters:1 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP12 : (Group 12 pm_prefetch1) Cycles at least 1 instruction fetched
+event:0X00C2 counters:2 um:zero minimum:1000 name:PM_DC_PREF_OUT_OF_STREAMS_GRP12 : (Group 12 pm_prefetch1) D cache out of prefetch streams
+event:0X00C3 counters:3 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_GRP12 : (Group 12 pm_prefetch1) D cache new prefetch stream allocated
+
+#Group 13 pm_prefetch2, Prefetch events
+event:0X00D0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP13 : (Group 13 pm_prefetch2) Internal operations completed
+event:0X00D1 counters:1 um:zero minimum:1000 name:PM_CLB_FULL_CYC_GRP13 : (Group 13 pm_prefetch2) Cycles CLB full
+event:0X00D2 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP13 : (Group 13 pm_prefetch2) L1 cache data prefetches
+event:0X00D3 counters:3 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP13 : (Group 13 pm_prefetch2) Instruction prefetched installed in prefetch buffer
+
+#Group 14 pm_prefetch3, L2 prefetch and misc events
+event:0X00E0 counters:0 um:zero minimum:1000 name:PM_1INST_CLB_CYC_GRP14 : (Group 14 pm_prefetch3) Cycles 1 instruction in CLB
+event:0X00E1 counters:1 um:zero minimum:1000 name:PM_LSU_BUSY_REJECT_GRP14 : (Group 14 pm_prefetch3) LSU busy due to reject
+event:0X00E2 counters:2 um:zero minimum:1000 name:PM_L2_PREF_GRP14 : (Group 14 pm_prefetch3) L2 cache prefetches
+event:0X00E3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP14 : (Group 14 pm_prefetch3) Internal operations completed
+
+#Group 15 pm_prefetch4, Misc prefetch and reject events
+event:0X00F0 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_SRQ_GRP15 : (Group 15 pm_prefetch4) LSU0 SRQ lhs rejects
+event:0X00F1 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_SRQ_GRP15 : (Group 15 pm_prefetch4) LSU1 SRQ lhs rejects
+event:0X00F2 counters:2 um:zero minimum:1000 name:PM_DC_PREF_DST_GRP15 : (Group 15 pm_prefetch4) DST (Data Stream Touch) stream start
+event:0X00F3 counters:3 um:zero minimum:1000 name:PM_L2_PREF_GRP15 : (Group 15 pm_prefetch4) L2 cache prefetches
+
+#Group 16 pm_lsu_reject1, LSU reject events
+event:0X0100 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_ERAT_MISS_GRP16 : (Group 16 pm_lsu_reject1) LSU reject due to ERAT miss
+event:0X0101 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_LMQ_FULL_GRP16 : (Group 16 pm_lsu_reject1) LSU reject due to LMQ full or missed data coming
+event:0X0102 counters:2 um:zero minimum:1000 name:PM_FLUSH_IMBAL_GRP16 : (Group 16 pm_lsu_reject1) Flush caused by thread GCT imbalance
+event:0X0103 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_GRP16 : (Group 16 pm_lsu_reject1) Marked SRQ lhs flushes
+
+#Group 17 pm_lsu_reject2, LSU rejects due to reload CDF or tag update collision
+event:0X0110 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_RELOAD_CDF_GRP17 : (Group 17 pm_lsu_reject2) LSU0 reject due to reload CDF or tag update collision
+event:0X0111 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_RELOAD_CDF_GRP17 : (Group 17 pm_lsu_reject2) LSU1 reject due to reload CDF or tag update collision
+event:0X0112 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP17 : (Group 17 pm_lsu_reject2) Internal operations completed
+event:0X0113 counters:3 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP17 : (Group 17 pm_lsu_reject2) Cycles writing to instruction L1
+
+#Group 18 pm_lsu_reject3, LSU rejects due to ERAT, held instuctions
+event:0X0120 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_ERAT_MISS_GRP18 : (Group 18 pm_lsu_reject3) LSU0 reject due to ERAT miss
+event:0X0121 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_ERAT_MISS_GRP18 : (Group 18 pm_lsu_reject3) LSU1 reject due to ERAT miss
+event:0X0122 counters:2 um:zero minimum:1000 name:PM_LWSYNC_HELD_GRP18 : (Group 18 pm_lsu_reject3) LWSYNC held at dispatch
+event:0X0123 counters:3 um:zero minimum:1000 name:PM_TLBIE_HELD_GRP18 : (Group 18 pm_lsu_reject3) TLBIE held at dispatch
+
+#Group 19 pm_lsu_reject4, LSU0/1 reject LMQ full
+event:0X0130 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_LMQ_FULL_GRP19 : (Group 19 pm_lsu_reject4) LSU0 reject due to LMQ full or missed data coming
+event:0X0131 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_LMQ_FULL_GRP19 : (Group 19 pm_lsu_reject4) LSU1 reject due to LMQ full or missed data coming
+event:0X0132 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP19 : (Group 19 pm_lsu_reject4) Internal operations completed
+event:0X0133 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP19 : (Group 19 pm_lsu_reject4) Branches issued
+
+#Group 20 pm_lsu_reject5, LSU misc reject and flush events
+event:0X0140 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_SRQ_GRP20 : (Group 20 pm_lsu_reject5) LSU SRQ lhs rejects
+event:0X0141 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_RELOAD_CDF_GRP20 : (Group 20 pm_lsu_reject5) LSU reject due to reload CDF or tag update collision
+event:0X0142 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP20 : (Group 20 pm_lsu_reject5) Flush initiated by LSU
+event:0X0143 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP20 : (Group 20 pm_lsu_reject5) Flushes
+
+#Group 21 pm_flush1, Misc flush events
+event:0X0150 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP21 : (Group 21 pm_flush1) Internal operations completed
+event:0X0151 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP21 : (Group 21 pm_flush1) SRQ unaligned store flushes
+event:0X0152 counters:2 um:zero minimum:1000 name:PM_FLUSH_IMBAL_GRP21 : (Group 21 pm_flush1) Flush caused by thread GCT imbalance
+event:0X0153 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP21 : (Group 21 pm_flush1) L1 D cache entries invalidated from L2
+
+#Group 22 pm_flush2, Flushes due to scoreboard and sync
+event:0X0160 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_flush2) Instruction TLB misses
+event:0X0161 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP22 : (Group 22 pm_flush2) Internal operations completed
+event:0X0162 counters:2 um:zero minimum:1000 name:PM_FLUSH_SB_GRP22 : (Group 22 pm_flush2) Flush caused by scoreboard operation
+event:0X0163 counters:3 um:zero minimum:1000 name:PM_FLUSH_SYNC_GRP22 : (Group 22 pm_flush2) Flush caused by sync
+
+#Group 23 pm_lsu_flush_srq_lrq, LSU flush by SRQ and LRQ events
+event:0X0170 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) SRQ flushes
+event:0X0171 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) LRQ flushes
+event:0X0172 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) Internal operations completed
+event:0X0173 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) Flush initiated by LSU
+
+#Group 24 pm_lsu_flush_lrq, LSU0/1 flush due to LRQ
+event:0X0180 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP24 : (Group 24 pm_lsu_flush_lrq) LSU0 LRQ flushes
+event:0X0181 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP24 : (Group 24 pm_lsu_flush_lrq) LSU1 LRQ flushes
+event:0X0182 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP24 : (Group 24 pm_lsu_flush_lrq) Flush initiated by LSU
+event:0X0183 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP24 : (Group 24 pm_lsu_flush_lrq) Internal operations completed
+
+#Group 25 pm_lsu_flush_srq, LSU0/1 flush due to SRQ
+event:0X0190 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP25 : (Group 25 pm_lsu_flush_srq) LSU0 SRQ lhs flushes
+event:0X0191 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP25 : (Group 25 pm_lsu_flush_srq) LSU1 SRQ lhs flushes
+event:0X0192 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP25 : (Group 25 pm_lsu_flush_srq) Internal operations completed
+event:0X0193 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP25 : (Group 25 pm_lsu_flush_srq) Flush initiated by LSU
+
+#Group 26 pm_lsu_flush_unaligned, LSU flush due to unaligned data
+event:0X01A0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP26 : (Group 26 pm_lsu_flush_unaligned) LRQ unaligned load flushes
+event:0X01A1 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP26 : (Group 26 pm_lsu_flush_unaligned) SRQ unaligned store flushes
+event:0X01A2 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP26 : (Group 26 pm_lsu_flush_unaligned) Branches issued
+event:0X01A3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP26 : (Group 26 pm_lsu_flush_unaligned) Internal operations completed
+
+#Group 27 pm_lsu_flush_uld, LSU0/1 flush due to unaligned load
+event:0X01B0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP27 : (Group 27 pm_lsu_flush_uld) LSU0 unaligned load flushes
+event:0X01B1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP27 : (Group 27 pm_lsu_flush_uld) LSU1 unaligned load flushes
+event:0X01B2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP27 : (Group 27 pm_lsu_flush_uld) Flush initiated by LSU
+event:0X01B3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP27 : (Group 27 pm_lsu_flush_uld) Internal operations completed
+
+#Group 28 pm_lsu_flush_ust, LSU0/1 flush due to unaligned store
+event:0X01C0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP28 : (Group 28 pm_lsu_flush_ust) LSU0 unaligned store flushes
+event:0X01C1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP28 : (Group 28 pm_lsu_flush_ust) LSU1 unaligned store flushes
+event:0X01C2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP28 : (Group 28 pm_lsu_flush_ust) Internal operations completed
+event:0X01C3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP28 : (Group 28 pm_lsu_flush_ust) Flush initiated by LSU
+
+#Group 29 pm_lsu_flush_full, LSU flush due to LRQ/SRQ full
+event:0X01D0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_FULL_GRP29 : (Group 29 pm_lsu_flush_full) Flush caused by LRQ full
+event:0X01D1 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP29 : (Group 29 pm_lsu_flush_full) Internal operations completed
+event:0X01D2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP29 : (Group 29 pm_lsu_flush_full) Marked LRQ flushes
+event:0X01D3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_FULL_GRP29 : (Group 29 pm_lsu_flush_full) Flush caused by SRQ full
+
+#Group 30 pm_lsu_stall1, LSU Stalls
+event:0X01E0 counters:0 um:zero minimum:1000 name:PM_GRP_MRK_GRP30 : (Group 30 pm_lsu_stall1) Group marked in IDU
+event:0X01E1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP30 : (Group 30 pm_lsu_stall1) Completion stall caused by LSU instruction
+event:0X01E2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP30 : (Group 30 pm_lsu_stall1) Internal operations completed
+event:0X01E3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP30 : (Group 30 pm_lsu_stall1) Completion stall caused by reject
+
+#Group 31 pm_lsu_stall2, LSU Stalls
+event:0X01F0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP31 : (Group 31 pm_lsu_stall2) Internal operations completed
+event:0X01F1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP31 : (Group 31 pm_lsu_stall2) Completion stall caused by D cache miss
+event:0X01F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP31 : (Group 31 pm_lsu_stall2) Processor cycles
+event:0X01F3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP31 : (Group 31 pm_lsu_stall2) Completion stall caused by ERAT miss
+
+#Group 32 pm_fxu_stall, FXU Stalls
+event:0X0200 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_BR_REDIR_NONSPEC_GRP32 : (Group 32 pm_fxu_stall) Group experienced non-speculative I cache miss or branch redirect
+event:0X0201 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP32 : (Group 32 pm_fxu_stall) Completion stall caused by FXU instruction
+event:0X0202 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP32 : (Group 32 pm_fxu_stall) Internal operations completed
+event:0X0203 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP32 : (Group 32 pm_fxu_stall) Completion stall caused by DIV instruction
+
+#Group 33 pm_fpu_stall, FPU Stalls
+event:0X0210 counters:0 um:zero minimum:1000 name:PM_FPU_FULL_CYC_GRP33 : (Group 33 pm_fpu_stall) Cycles FPU issue queue full
+event:0X0211 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FDIV_GRP33 : (Group 33 pm_fpu_stall) Completion stall caused by FDIV or FQRT instruction
+event:0X0212 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP33 : (Group 33 pm_fpu_stall) Internal operations completed
+event:0X0213 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_FPU_GRP33 : (Group 33 pm_fpu_stall) Completion stall caused by FPU instruction
+
+#Group 34 pm_queue_full, BRQ LRQ LMQ queue full
+event:0X0220 counters:0 um:zero minimum:1000 name:PM_LARX_LSU0_GRP34 : (Group 34 pm_queue_full) Larx executed on LSU0
+event:0X0221 counters:1 um:zero minimum:1000 name:PM_BRQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles branch queue full
+event:0X0222 counters:2 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles LRQ full
+event:0X0223 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles LMQ full
+
+#Group 35 pm_issueq_full, FPU FX full
+event:0X0230 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FPU0 issue queue full
+event:0X0231 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FPU1 issue queue full
+event:0X0232 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FXU0/LS0 queue full
+event:0X0233 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FXU1/LS1 queue full
+
+#Group 36 pm_mapper_full1, CR CTR GPR mapper full
+event:0X0240 counters:0 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles CR logical operation mapper full
+event:0X0241 counters:1 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles LR/CTR mapper full
+event:0X0242 counters:2 um:zero minimum:1000 name:PM_GPR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles GPR mapper full
+event:0X0243 counters:3 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles CR issue queue full
+
+#Group 37 pm_mapper_full2, FPR XER mapper full
+event:0X0250 counters:0 um:zero minimum:1000 name:PM_FPR_MAP_FULL_CYC_GRP37 : (Group 37 pm_mapper_full2) Cycles FPR mapper full
+event:0X0251 counters:1 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP37 : (Group 37 pm_mapper_full2) Cycles XER mapper full
+event:0X0252 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2MISS_GRP37 : (Group 37 pm_mapper_full2) Marked data loaded missed L2
+event:0X0253 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP37 : (Group 37 pm_mapper_full2) Internal operations completed
+
+#Group 38 pm_misc_load, Non-cachable loads and stcx events
+event:0X0260 counters:0 um:zero minimum:1000 name:PM_STCX_FAIL_GRP38 : (Group 38 pm_misc_load) STCX failed
+event:0X0261 counters:1 um:zero minimum:1000 name:PM_STCX_PASS_GRP38 : (Group 38 pm_misc_load) Stcx passes
+event:0X0262 counters:2 um:zero minimum:1000 name:PM_LSU0_NCLD_GRP38 : (Group 38 pm_misc_load) LSU0 non-cacheable loads
+event:0X0263 counters:3 um:zero minimum:1000 name:PM_LSU1_NCLD_GRP38 : (Group 38 pm_misc_load) LSU1 non-cacheable loads
+
+#Group 39 pm_ic_demand, ICache demand from BR redirect
+event:0X0270 counters:0 um:zero minimum:1000 name:PM_LSU0_BUSY_REJECT_GRP39 : (Group 39 pm_ic_demand) LSU0 busy due to reject
+event:0X0271 counters:1 um:zero minimum:1000 name:PM_LSU1_BUSY_REJECT_GRP39 : (Group 39 pm_ic_demand) LSU1 busy due to reject
+event:0X0272 counters:2 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BHT_REDIRECT_GRP39 : (Group 39 pm_ic_demand) L2 I cache demand request due to BHT redirect
+event:0X0273 counters:3 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_REDIRECT_GRP39 : (Group 39 pm_ic_demand) L2 I cache demand request due to branch redirect
+
+#Group 40 pm_ic_pref, ICache prefetch
+event:0X0280 counters:0 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP40 : (Group 40 pm_ic_pref) Translation written to ierat
+event:0X0281 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP40 : (Group 40 pm_ic_pref) Instruction prefetch requests
+event:0X0282 counters:2 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP40 : (Group 40 pm_ic_pref) Instruction prefetched installed in prefetch buffer
+event:0X0283 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP40 : (Group 40 pm_ic_pref) No instructions fetched
+
+#Group 41 pm_ic_miss, ICache misses
+event:0X0290 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_NONSPEC_GRP41 : (Group 41 pm_ic_miss) Group experienced non-speculative I cache miss
+event:0X0291 counters:1 um:zero minimum:1000 name:PM_GRP_IC_MISS_GRP41 : (Group 41 pm_ic_miss) Group experienced I cache miss
+event:0X0292 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP41 : (Group 41 pm_ic_miss) L1 reload data source valid
+event:0X0293 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP41 : (Group 41 pm_ic_miss) Internal operations completed
+
+#Group 42 pm_branch_miss, Branch mispredict, TLB and SLB misses
+event:0X02A0 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP42 : (Group 42 pm_branch_miss) TLB misses
+event:0X02A1 counters:1 um:zero minimum:1000 name:PM_SLB_MISS_GRP42 : (Group 42 pm_branch_miss) SLB misses
+event:0X02A2 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP42 : (Group 42 pm_branch_miss) Branch mispredictions due to CR bit setting
+event:0X02A3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP42 : (Group 42 pm_branch_miss) Branch mispredictions due to target address
+
+#Group 43 pm_branch1, Branch operations
+event:0X02B0 counters:0 um:zero minimum:1000 name:PM_BR_UNCOND_GRP43 : (Group 43 pm_branch1) Unconditional branch
+event:0X02B1 counters:1 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, target prediction
+event:0X02B2 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, CR prediction
+event:0X02B3 counters:3 um:zero minimum:1000 name:PM_BR_PRED_CR_TA_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, CR and target prediction
+
+#Group 44 pm_branch2, Branch operations
+event:0X02C0 counters:0 um:zero minimum:1000 name:PM_GRP_BR_REDIR_NONSPEC_GRP44 : (Group 44 pm_branch2) Group experienced non-speculative branch redirect
+event:0X02C1 counters:1 um:zero minimum:1000 name:PM_GRP_BR_REDIR_GRP44 : (Group 44 pm_branch2) Group experienced branch redirect
+event:0X02C2 counters:2 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP44 : (Group 44 pm_branch2) Flush caused by branch mispredict
+event:0X02C3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP44 : (Group 44 pm_branch2) Internal operations completed
+
+#Group 45 pm_L1_tlbmiss, L1 load and TLB misses
+event:0X02D0 counters:0 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP45 : (Group 45 pm_L1_tlbmiss) Cycles doing data tablewalks
+event:0X02D1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP45 : (Group 45 pm_L1_tlbmiss) Data TLB misses
+event:0X02D2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP45 : (Group 45 pm_L1_tlbmiss) L1 D cache load misses
+event:0X02D3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP45 : (Group 45 pm_L1_tlbmiss) L1 D cache load references
+
+#Group 46 pm_L1_DERAT_miss, L1 store and DERAT misses
+event:0X02E0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP46 : (Group 46 pm_L1_DERAT_miss) Data loaded from L2
+event:0X02E1 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP46 : (Group 46 pm_L1_DERAT_miss) DERAT misses
+event:0X02E2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP46 : (Group 46 pm_L1_DERAT_miss) L1 D cache store references
+event:0X02E3 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP46 : (Group 46 pm_L1_DERAT_miss) L1 D cache store misses
+
+#Group 47 pm_L1_slbmiss, L1 load and SLB misses
+event:0X02F0 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_GRP47 : (Group 47 pm_L1_slbmiss) Data SLB misses
+event:0X02F1 counters:1 um:zero minimum:1000 name:PM_ISLB_MISS_GRP47 : (Group 47 pm_L1_slbmiss) Instruction SLB misses
+event:0X02F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP47 : (Group 47 pm_L1_slbmiss) LSU0 L1 D cache load misses
+event:0X02F3 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP47 : (Group 47 pm_L1_slbmiss) LSU1 L1 D cache load misses
+
+#Group 48 pm_dtlbref, Data TLB references
+event:0X0300 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_4K_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 4K page
+event:0X0301 counters:1 um:zero minimum:1000 name:PM_DTLB_REF_64K_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 64K page
+event:0X0302 counters:2 um:zero minimum:1000 name:PM_DTLB_REF_16M_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 16M page
+event:0X0303 counters:3 um:zero minimum:1000 name:PM_DTLB_REF_16G_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 16G page
+
+#Group 49 pm_dtlbmiss, Data TLB misses
+event:0X0310 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_4K_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 4K page
+event:0X0311 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_64K_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 64K page
+event:0X0312 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_16M_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 16M page
+event:0X0313 counters:3 um:zero minimum:1000 name:PM_DTLB_MISS_16G_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 16G page
+
+#Group 50 pm_dtlb, Data TLB references and misses
+event:0X0320 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_GRP50 : (Group 50 pm_dtlb) Data TLB references
+event:0X0321 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP50 : (Group 50 pm_dtlb) Data TLB misses
+event:0X0322 counters:2 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_dtlb) Processor cycles
+event:0X0323 counters:3 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_dtlb) Processor cycles
+
+#Group 51 pm_L1_refmiss, L1 load references and misses and store references and misses
+event:0X0330 counters:0 um:zero minimum:1000 name:PM_LD_REF_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache load references
+event:0X0331 counters:1 um:zero minimum:1000 name:PM_ST_REF_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache store references
+event:0X0332 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache load misses
+event:0X0333 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache store misses
+
+#Group 52 pm_dsource1, L3 cache and memory data access
+event:0X0340 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP52 : (Group 52 pm_dsource1) Data loaded from L3
+event:0X0341 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP52 : (Group 52 pm_dsource1) Data loaded from local memory
+event:0X0342 counters:2 um:zero minimum:1000 name:PM_FLUSH_GRP52 : (Group 52 pm_dsource1) Flushes
+event:0X0343 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP52 : (Group 52 pm_dsource1) Internal operations completed
+
+#Group 53 pm_dsource2, L3 cache and memory data access
+event:0X0350 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP53 : (Group 53 pm_dsource2) Data loaded from L3
+event:0X0351 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP53 : (Group 53 pm_dsource2) Data loaded from local memory
+event:0X0352 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP53 : (Group 53 pm_dsource2) Data loaded missed L2
+event:0X0353 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP53 : (Group 53 pm_dsource2) Data loaded from remote memory
+
+#Group 54 pm_dsource_L2, L2 cache data access
+event:0X0360 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.5 shared
+event:0X0361 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.5 modified
+event:0X0362 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.75 shared
+event:0X0363 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.75 modified
+
+#Group 55 pm_dsource_L3, L3 cache data access
+event:0X0370 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.5 shared
+event:0X0371 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.5 modified
+event:0X0372 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L375_SHR_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.75 shared
+event:0X0373 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L375_MOD_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.75 modified
+
+#Group 56 pm_isource1, Instruction source information
+event:0X0380 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP56 : (Group 56 pm_isource1) Instruction fetched from L3
+event:0X0381 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP56 : (Group 56 pm_isource1) Instruction fetched from L1
+event:0X0382 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP56 : (Group 56 pm_isource1) Instruction fetched from prefetch
+event:0X0383 counters:3 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP56 : (Group 56 pm_isource1) Instruction fetched from remote memory
+
+#Group 57 pm_isource2, Instruction source information
+event:0X0390 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP57 : (Group 57 pm_isource2) Instruction fetched from L2
+event:0X0391 counters:1 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP57 : (Group 57 pm_isource2) Instruction fetched from local memory
+event:0X0392 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP57 : (Group 57 pm_isource2) Internal operations completed
+event:0X0393 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP57 : (Group 57 pm_isource2) No instructions fetched
+
+#Group 58 pm_isource_L2, L2 instruction source information
+event:0X03A0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L25_SHR_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.5 shared
+event:0X03A1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.5 modified
+event:0X03A2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L275_SHR_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.75 shared
+event:0X03A3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L275_MOD_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.75 modified
+
+#Group 59 pm_isource_L3, L3 instruction source information
+event:0X03B0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L35_SHR_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.5 shared
+event:0X03B1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L35_MOD_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.5 modified
+event:0X03B2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L375_SHR_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.75 shared
+event:0X03B3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L375_MOD_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.75 modified
+
+#Group 60 pm_pteg_source1, PTEG source information
+event:0X03C0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L25_SHR_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.5 shared
+event:0X03C1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L25_MOD_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.5 modified
+event:0X03C2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L275_SHR_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.75 shared
+event:0X03C3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L275_MOD_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.75 modified
+
+#Group 61 pm_pteg_source2, PTEG source information
+event:0X03D0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L35_SHR_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.5 shared
+event:0X03D1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L35_MOD_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.5 modified
+event:0X03D2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L375_SHR_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.75 shared
+event:0X03D3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L375_MOD_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.75 modified
+
+#Group 62 pm_pteg_source3, PTEG source information
+event:0X03E0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from L2
+event:0X03E1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from local memory
+event:0X03E2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from L2 miss
+event:0X03E3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from remote memory
+
+#Group 63 pm_pteg_source4, L3 PTEG and group disptach events
+event:0X03F0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP63 : (Group 63 pm_pteg_source4) PTEG loaded from L3
+event:0X03F1 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_GRP63 : (Group 63 pm_pteg_source4) Group dispatches
+event:0X03F2 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_SUCCESS_GRP63 : (Group 63 pm_pteg_source4) Group dispatch success
+event:0X03F3 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP63 : (Group 63 pm_pteg_source4) L1 D cache entries invalidated from L2
+
+#Group 64 pm_L2SA_ld, L2 slice A load events
+event:0X0400 counters:0 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_GRP64 : (Group 64 pm_L2SA_ld) L2 slice A RC load dispatch attempt
+event:0X0401 counters:1 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_RC_FULL_GRP64 : (Group 64 pm_L2SA_ld) L2 slice A RC load dispatch attempt failed due to all RC full
+event:0X0402 counters:2 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_ADDR_GRP64 : (Group 64 pm_L2SA_ld) L2 slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X0403 counters:3 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_OTHER_GRP64 : (Group 64 pm_L2SA_ld) L2 slice A RC load dispatch attempt failed due to other reasons
+
+#Group 65 pm_L2SA_st, L2 slice A store events
+event:0X0410 counters:0 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_GRP65 : (Group 65 pm_L2SA_st) L2 slice A RC store dispatch attempt
+event:0X0411 counters:1 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_RC_FULL_GRP65 : (Group 65 pm_L2SA_st) L2 slice A RC store dispatch attempt failed due to all RC full
+event:0X0412 counters:2 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_ADDR_GRP65 : (Group 65 pm_L2SA_st) L2 slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X0413 counters:3 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_OTHER_GRP65 : (Group 65 pm_L2SA_st) L2 slice A RC store dispatch attempt failed due to other reasons
+
+#Group 66 pm_L2SA_st2, L2 slice A store events
+event:0X0420 counters:0 um:zero minimum:1000 name:PM_L2SA_RC_DISP_FAIL_CO_BUSY_GRP66 : (Group 66 pm_L2SA_st2) L2 slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X0421 counters:1 um:zero minimum:1000 name:PM_L2SA_ST_REQ_GRP66 : (Group 66 pm_L2SA_st2) L2 slice A store requests
+event:0X0422 counters:2 um:zero minimum:1000 name:PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL_GRP66 : (Group 66 pm_L2SA_st2) L2 slice A RC dispatch attempt failed due to all CO busy
+event:0X0423 counters:3 um:zero minimum:1000 name:PM_L2SA_ST_HIT_GRP66 : (Group 66 pm_L2SA_st2) L2 slice A store hits
+
+#Group 67 pm_L2SB_ld, L2 slice B load events
+event:0X0430 counters:0 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_GRP67 : (Group 67 pm_L2SB_ld) L2 slice B RC load dispatch attempt
+event:0X0431 counters:1 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_RC_FULL_GRP67 : (Group 67 pm_L2SB_ld) L2 slice B RC load dispatch attempt failed due to all RC full
+event:0X0432 counters:2 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_ADDR_GRP67 : (Group 67 pm_L2SB_ld) L2 slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X0433 counters:3 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_OTHER_GRP67 : (Group 67 pm_L2SB_ld) L2 slice B RC load dispatch attempt failed due to other reasons
+
+#Group 68 pm_L2SB_st, L2 slice B store events
+event:0X0440 counters:0 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_GRP68 : (Group 68 pm_L2SB_st) L2 slice B RC store dispatch attempt
+event:0X0441 counters:1 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_RC_FULL_GRP68 : (Group 68 pm_L2SB_st) L2 slice B RC store dispatch attempt failed due to all RC full
+event:0X0442 counters:2 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_ADDR_GRP68 : (Group 68 pm_L2SB_st) L2 slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X0443 counters:3 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_OTHER_GRP68 : (Group 68 pm_L2SB_st) L2 slice B RC store dispatch attempt failed due to other reasons
+
+#Group 69 pm_L2SB_st2, L2 slice B store events
+event:0X0450 counters:0 um:zero minimum:1000 name:PM_L2SB_RC_DISP_FAIL_CO_BUSY_GRP69 : (Group 69 pm_L2SB_st2) L2 slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X0451 counters:1 um:zero minimum:1000 name:PM_L2SB_ST_REQ_GRP69 : (Group 69 pm_L2SB_st2) L2 slice B store requests
+event:0X0452 counters:2 um:zero minimum:1000 name:PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL_GRP69 : (Group 69 pm_L2SB_st2) L2 slice B RC dispatch attempt failed due to all CO busy
+event:0X0453 counters:3 um:zero minimum:1000 name:PM_L2SB_ST_HIT_GRP69 : (Group 69 pm_L2SB_st2) L2 slice B store hits
+
+#Group 70 pm_L2SC_ld, L2 slice C load events
+event:0X0460 counters:0 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_GRP70 : (Group 70 pm_L2SC_ld) L2 slice C RC load dispatch attempt
+event:0X0461 counters:1 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_RC_FULL_GRP70 : (Group 70 pm_L2SC_ld) L2 slice C RC load dispatch attempt failed due to all RC full
+event:0X0462 counters:2 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_ADDR_GRP70 : (Group 70 pm_L2SC_ld) L2 slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X0463 counters:3 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_OTHER_GRP70 : (Group 70 pm_L2SC_ld) L2 slice C RC load dispatch attempt failed due to other reasons
+
+#Group 71 pm_L2SC_st, L2 slice C store events
+event:0X0470 counters:0 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_GRP71 : (Group 71 pm_L2SC_st) L2 slice C RC store dispatch attempt
+event:0X0471 counters:1 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_RC_FULL_GRP71 : (Group 71 pm_L2SC_st) L2 slice C RC store dispatch attempt failed due to all RC full
+event:0X0472 counters:2 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_ADDR_GRP71 : (Group 71 pm_L2SC_st) L2 slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X0473 counters:3 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_OTHER_GRP71 : (Group 71 pm_L2SC_st) L2 slice C RC store dispatch attempt failed due to other reasons
+
+#Group 72 pm_L2SC_st2, L2 slice C store events
+event:0X0480 counters:0 um:zero minimum:1000 name:PM_L2SC_RC_DISP_FAIL_CO_BUSY_GRP72 : (Group 72 pm_L2SC_st2) L2 slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X0481 counters:1 um:zero minimum:1000 name:PM_L2SC_ST_REQ_GRP72 : (Group 72 pm_L2SC_st2) L2 slice C store requests
+event:0X0482 counters:2 um:zero minimum:1000 name:PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL_GRP72 : (Group 72 pm_L2SC_st2) L2 slice C RC dispatch attempt failed due to all CO busy
+event:0X0483 counters:3 um:zero minimum:1000 name:PM_L2SC_ST_HIT_GRP72 : (Group 72 pm_L2SC_st2) L2 slice C store hits
+
+#Group 73 pm_L3SA_trans, L3 slice A state transistions
+event:0X0490 counters:0 um:zero minimum:1000 name:PM_L3SA_MOD_TAG_GRP73 : (Group 73 pm_L3SA_trans) L3 slice A transition from modified to TAG
+event:0X0491 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP73 : (Group 73 pm_L3SA_trans) Internal operations completed
+event:0X0492 counters:2 um:zero minimum:1000 name:PM_L3SA_MOD_INV_GRP73 : (Group 73 pm_L3SA_trans) L3 slice A transition from modified to invalid
+event:0X0493 counters:3 um:zero minimum:1000 name:PM_L3SA_SHR_INV_GRP73 : (Group 73 pm_L3SA_trans) L3 slice A transition from shared to invalid
+
+#Group 74 pm_L3SB_trans, L3 slice B state transistions
+event:0X04A0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP74 : (Group 74 pm_L3SB_trans) Internal operations completed
+event:0X04A1 counters:1 um:zero minimum:1000 name:PM_L3SB_MOD_TAG_GRP74 : (Group 74 pm_L3SB_trans) L3 slice B transition from modified to TAG
+event:0X04A2 counters:2 um:zero minimum:1000 name:PM_L3SB_MOD_INV_GRP74 : (Group 74 pm_L3SB_trans) L3 slice B transition from modified to invalid
+event:0X04A3 counters:3 um:zero minimum:1000 name:PM_L3SB_SHR_INV_GRP74 : (Group 74 pm_L3SB_trans) L3 slice B transition from shared to invalid
+
+#Group 75 pm_L3SC_trans, L3 slice C state transistions
+event:0X04B0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP75 : (Group 75 pm_L3SC_trans) Internal operations completed
+event:0X04B1 counters:1 um:zero minimum:1000 name:PM_L3SC_MOD_TAG_GRP75 : (Group 75 pm_L3SC_trans) L3 slice C transition from modified to TAG
+event:0X04B2 counters:2 um:zero minimum:1000 name:PM_L3SC_MOD_INV_GRP75 : (Group 75 pm_L3SC_trans) L3 slice C transition from modified to invalid
+event:0X04B3 counters:3 um:zero minimum:1000 name:PM_L3SC_SHR_INV_GRP75 : (Group 75 pm_L3SC_trans) L3 slice C transition from shared to invalid
+
+#Group 76 pm_L2SA_trans, L2 slice A state transistions
+event:0X04C0 counters:0 um:zero minimum:1000 name:PM_L2SA_MOD_TAG_GRP76 : (Group 76 pm_L2SA_trans) L2 slice A transition from modified to tagged
+event:0X04C1 counters:1 um:zero minimum:1000 name:PM_L2SA_SHR_MOD_GRP76 : (Group 76 pm_L2SA_trans) L2 slice A transition from shared to modified
+event:0X04C2 counters:2 um:zero minimum:1000 name:PM_L2SA_MOD_INV_GRP76 : (Group 76 pm_L2SA_trans) L2 slice A transition from modified to invalid
+event:0X04C3 counters:3 um:zero minimum:1000 name:PM_L2SA_SHR_INV_GRP76 : (Group 76 pm_L2SA_trans) L2 slice A transition from shared to invalid
+
+#Group 77 pm_L2SB_trans, L2 slice B state transistions
+event:0X04D0 counters:0 um:zero minimum:1000 name:PM_L2SB_MOD_TAG_GRP77 : (Group 77 pm_L2SB_trans) L2 slice B transition from modified to tagged
+event:0X04D1 counters:1 um:zero minimum:1000 name:PM_L2SB_SHR_MOD_GRP77 : (Group 77 pm_L2SB_trans) L2 slice B transition from shared to modified
+event:0X04D2 counters:2 um:zero minimum:1000 name:PM_L2SB_MOD_INV_GRP77 : (Group 77 pm_L2SB_trans) L2 slice B transition from modified to invalid
+event:0X04D3 counters:3 um:zero minimum:1000 name:PM_L2SB_SHR_INV_GRP77 : (Group 77 pm_L2SB_trans) L2 slice B transition from shared to invalid
+
+#Group 78 pm_L2SC_trans, L2 slice C state transistions
+event:0X04E0 counters:0 um:zero minimum:1000 name:PM_L2SC_MOD_TAG_GRP78 : (Group 78 pm_L2SC_trans) L2 slice C transition from modified to tagged
+event:0X04E1 counters:1 um:zero minimum:1000 name:PM_L2SC_SHR_MOD_GRP78 : (Group 78 pm_L2SC_trans) L2 slice C transition from shared to modified
+event:0X04E2 counters:2 um:zero minimum:1000 name:PM_L2SC_MOD_INV_GRP78 : (Group 78 pm_L2SC_trans) L2 slice C transition from modified to invalid
+event:0X04E3 counters:3 um:zero minimum:1000 name:PM_L2SC_SHR_INV_GRP78 : (Group 78 pm_L2SC_trans) L2 slice C transition from shared to invalid
+
+#Group 79 pm_L3SAB_retry, L3 slice A/B snoop retry and all CI/CO busy
+event:0X04F0 counters:0 um:zero minimum:1000 name:PM_L3SA_ALL_BUSY_GRP79 : (Group 79 pm_L3SAB_retry) L3 slice A active for every cycle all CI/CO machines busy
+event:0X04F1 counters:1 um:zero minimum:1000 name:PM_L3SB_ALL_BUSY_GRP79 : (Group 79 pm_L3SAB_retry) L3 slice B active for every cycle all CI/CO machines busy
+event:0X04F2 counters:2 um:zero minimum:1000 name:PM_L3SA_SNOOP_RETRY_GRP79 : (Group 79 pm_L3SAB_retry) L3 slice A snoop retries
+event:0X04F3 counters:3 um:zero minimum:1000 name:PM_L3SB_SNOOP_RETRY_GRP79 : (Group 79 pm_L3SAB_retry) L3 slice B snoop retries
+
+#Group 80 pm_L3SAB_hit, L3 slice A/B hit and reference
+event:0X0500 counters:0 um:zero minimum:1000 name:PM_L3SA_REF_GRP80 : (Group 80 pm_L3SAB_hit) L3 slice A references
+event:0X0501 counters:1 um:zero minimum:1000 name:PM_L3SB_REF_GRP80 : (Group 80 pm_L3SAB_hit) L3 slice B references
+event:0X0502 counters:2 um:zero minimum:1000 name:PM_L3SA_HIT_GRP80 : (Group 80 pm_L3SAB_hit) L3 slice A hits
+event:0X0503 counters:3 um:zero minimum:1000 name:PM_L3SB_HIT_GRP80 : (Group 80 pm_L3SAB_hit) L3 slice B hits
+
+#Group 81 pm_L3SC_retry_hit, L3 slice C hit & snoop retry
+event:0X0510 counters:0 um:zero minimum:1000 name:PM_L3SC_ALL_BUSY_GRP81 : (Group 81 pm_L3SC_retry_hit) L3 slice C active for every cycle all CI/CO machines busy
+event:0X0511 counters:1 um:zero minimum:1000 name:PM_L3SC_REF_GRP81 : (Group 81 pm_L3SC_retry_hit) L3 slice C references
+event:0X0512 counters:2 um:zero minimum:1000 name:PM_L3SC_SNOOP_RETRY_GRP81 : (Group 81 pm_L3SC_retry_hit) L3 slice C snoop retries
+event:0X0513 counters:3 um:zero minimum:1000 name:PM_L3SC_HIT_GRP81 : (Group 81 pm_L3SC_retry_hit) L3 slice C hits
+
+#Group 82 pm_fpu1, Floating Point events
+event:0X0520 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP82 : (Group 82 pm_fpu1) FPU executed FDIV instruction
+event:0X0521 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP82 : (Group 82 pm_fpu1) FPU executed multiply-add instruction
+event:0X0522 counters:2 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP82 : (Group 82 pm_fpu1) FPU executed FMOV or FEST instructions
+event:0X0523 counters:3 um:zero minimum:1000 name:PM_FPU_FEST_GRP82 : (Group 82 pm_fpu1) FPU executed FEST instruction
+
+#Group 83 pm_fpu2, Floating Point events
+event:0X0530 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP83 : (Group 83 pm_fpu2) FPU executed one flop instruction
+event:0X0531 counters:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP83 : (Group 83 pm_fpu2) FPU executed FSQRT instruction
+event:0X0532 counters:2 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP83 : (Group 83 pm_fpu2) FPU executed FRSP or FCONV instructions
+event:0X0533 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP83 : (Group 83 pm_fpu2) FPU produced a result
+
+#Group 84 pm_fpu3, Floating point events
+event:0X0540 counters:0 um:zero minimum:1000 name:PM_FPU_DENORM_GRP84 : (Group 84 pm_fpu3) FPU received denormalized data
+event:0X0541 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP84 : (Group 84 pm_fpu3) FPU stalled in pipe3
+event:0X0542 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP84 : (Group 84 pm_fpu3) FPU0 produced a result
+event:0X0543 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP84 : (Group 84 pm_fpu3) FPU1 produced a result
+
+#Group 85 pm_fpu4, Floating point events
+event:0X0550 counters:0 um:zero minimum:1000 name:PM_FPU_SINGLE_GRP85 : (Group 85 pm_fpu4) FPU executed single precision instruction
+event:0X0551 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP85 : (Group 85 pm_fpu4) FPU executed store instruction
+event:0X0552 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP85 : (Group 85 pm_fpu4) Internal operations completed
+event:0X0553 counters:3 um:zero minimum:1000 name:PM_LSU_LDF_GRP85 : (Group 85 pm_fpu4) LSU executed Floating Point load instruction
+
+#Group 86 pm_fpu5, Floating point events by unit
+event:0X0560 counters:0 um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU0 executed FSQRT instruction
+event:0X0561 counters:1 um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU1 executed FSQRT instruction
+event:0X0562 counters:2 um:zero minimum:1000 name:PM_FPU0_FEST_GRP86 : (Group 86 pm_fpu5) FPU0 executed FEST instruction
+event:0X0563 counters:3 um:zero minimum:1000 name:PM_FPU1_FEST_GRP86 : (Group 86 pm_fpu5) FPU1 executed FEST instruction
+
+#Group 87 pm_fpu6, Floating point events by unit
+event:0X0570 counters:0 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP87 : (Group 87 pm_fpu6) FPU0 received denormalized data
+event:0X0571 counters:1 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP87 : (Group 87 pm_fpu6) FPU1 received denormalized data
+event:0X0572 counters:2 um:zero minimum:1000 name:PM_FPU0_FMOV_FEST_GRP87 : (Group 87 pm_fpu6) FPU0 executed FMOV or FEST instructions
+event:0X0573 counters:3 um:zero minimum:1000 name:PM_FPU1_FMOV_FEST_GRP87 : (Group 87 pm_fpu6) FPU1 executed FMOV or FEST instructions
+
+#Group 88 pm_fpu7, Floating point events by unit
+event:0X0580 counters:0 um:zero minimum:1000 name:PM_FPU0_FDIV_GRP88 : (Group 88 pm_fpu7) FPU0 executed FDIV instruction
+event:0X0581 counters:1 um:zero minimum:1000 name:PM_FPU1_FDIV_GRP88 : (Group 88 pm_fpu7) FPU1 executed FDIV instruction
+event:0X0582 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP88 : (Group 88 pm_fpu7) FPU0 executed FRSP or FCONV instructions
+event:0X0583 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP88 : (Group 88 pm_fpu7) FPU1 executed FRSP or FCONV instructions
+
+#Group 89 pm_fpu8, Floating point events by unit
+event:0X0590 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP89 : (Group 89 pm_fpu8) FPU0 stalled in pipe3
+event:0X0591 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP89 : (Group 89 pm_fpu8) FPU1 stalled in pipe3
+event:0X0592 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP89 : (Group 89 pm_fpu8) Internal operations completed
+event:0X0593 counters:3 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP89 : (Group 89 pm_fpu8) FPU0 executed FPSCR instruction
+
+#Group 90 pm_fpu9, Floating point events by unit
+event:0X05A0 counters:0 um:zero minimum:1000 name:PM_FPU0_SINGLE_GRP90 : (Group 90 pm_fpu9) FPU0 executed single precision instruction
+event:0X05A1 counters:1 um:zero minimum:1000 name:PM_FPU1_SINGLE_GRP90 : (Group 90 pm_fpu9) FPU1 executed single precision instruction
+event:0X05A2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP90 : (Group 90 pm_fpu9) LSU0 executed Floating Point load instruction
+event:0X05A3 counters:3 um:zero minimum:1000 name:PM_LSU1_LDF_GRP90 : (Group 90 pm_fpu9) LSU1 executed Floating Point load instruction
+
+#Group 91 pm_fpu10, Floating point events by unit
+event:0X05B0 counters:0 um:zero minimum:1000 name:PM_FPU0_FMA_GRP91 : (Group 91 pm_fpu10) FPU0 executed multiply-add instruction
+event:0X05B1 counters:1 um:zero minimum:1000 name:PM_FPU1_FMA_GRP91 : (Group 91 pm_fpu10) FPU1 executed multiply-add instruction
+event:0X05B2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP91 : (Group 91 pm_fpu10) Internal operations completed
+event:0X05B3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP91 : (Group 91 pm_fpu10) FPU1 executed FRSP or FCONV instructions
+
+#Group 92 pm_fpu11, Floating point events by unit
+event:0X05C0 counters:0 um:zero minimum:1000 name:PM_FPU0_1FLOP_GRP92 : (Group 92 pm_fpu11) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X05C1 counters:1 um:zero minimum:1000 name:PM_FPU1_1FLOP_GRP92 : (Group 92 pm_fpu11) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X05C2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP92 : (Group 92 pm_fpu11) FPU0 produced a result
+event:0X05C3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP92 : (Group 92 pm_fpu11) Internal operations completed
+
+#Group 93 pm_fpu12, Floating point events by unit
+event:0X05D0 counters:0 um:zero minimum:1000 name:PM_FPU0_STF_GRP93 : (Group 93 pm_fpu12) FPU0 executed store instruction
+event:0X05D1 counters:1 um:zero minimum:1000 name:PM_FPU1_STF_GRP93 : (Group 93 pm_fpu12) FPU1 executed store instruction
+event:0X05D2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP93 : (Group 93 pm_fpu12) LSU0 executed Floating Point load instruction
+event:0X05D3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP93 : (Group 93 pm_fpu12) Internal operations completed
+
+#Group 94 pm_fxu1, Fixed Point events
+event:0X05E0 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP94 : (Group 94 pm_fxu1) FXU idle
+event:0X05E1 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP94 : (Group 94 pm_fxu1) FXU busy
+event:0X05E2 counters:2 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP94 : (Group 94 pm_fxu1) FXU0 busy FXU1 idle
+event:0X05E3 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP94 : (Group 94 pm_fxu1) FXU1 busy FXU0 idle
+
+#Group 95 pm_fxu2, Fixed Point events
+event:0X05F0 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP95 : (Group 95 pm_fxu2) Marked group dispatched
+event:0X05F1 counters:1 um:zero minimum:1000 name:PM_MRK_GRP_BR_REDIR_GRP95 : (Group 95 pm_fxu2) Group experienced marked branch redirect
+event:0X05F2 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP95 : (Group 95 pm_fxu2) FXU produced a result
+event:0X05F3 counters:3 um:zero minimum:1000 name:PM_FXLS_FULL_CYC_GRP95 : (Group 95 pm_fxu2) Cycles FXLS queue is full
+
+#Group 96 pm_fxu3, Fixed Point events
+event:0X0600 counters:0 um:zero minimum:1000 name:PM_3INST_CLB_CYC_GRP96 : (Group 96 pm_fxu3) Cycles 3 instructions in CLB
+event:0X0601 counters:1 um:zero minimum:1000 name:PM_4INST_CLB_CYC_GRP96 : (Group 96 pm_fxu3) Cycles 4 instructions in CLB
+event:0X0602 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP96 : (Group 96 pm_fxu3) FXU0 produced a result
+event:0X0603 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP96 : (Group 96 pm_fxu3) FXU1 produced a result
+
+#Group 97 pm_smt_priorities1, Thread priority events
+event:0X0610 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_4_CYC_GRP97 : (Group 97 pm_smt_priorities1) Cycles thread running at priority level 4
+event:0X0611 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_7_CYC_GRP97 : (Group 97 pm_smt_priorities1) Cycles thread running at priority level 7
+event:0X0612 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_0_CYC_GRP97 : (Group 97 pm_smt_priorities1) Cycles no thread priority difference
+event:0X0613 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_1or2_CYC_GRP97 : (Group 97 pm_smt_priorities1) Cycles thread priority difference is 1 or 2
+
+#Group 98 pm_smt_priorities2, Thread priority events
+event:0X0620 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_3_CYC_GRP98 : (Group 98 pm_smt_priorities2) Cycles thread running at priority level 3
+event:0X0621 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_6_CYC_GRP98 : (Group 98 pm_smt_priorities2) Cycles thread running at priority level 6
+event:0X0622 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_3or4_CYC_GRP98 : (Group 98 pm_smt_priorities2) Cycles thread priority difference is 3 or 4
+event:0X0623 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_5or6_CYC_GRP98 : (Group 98 pm_smt_priorities2) Cycles thread priority difference is 5 or 6
+
+#Group 99 pm_smt_priorities3, Thread priority events
+event:0X0630 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_2_CYC_GRP99 : (Group 99 pm_smt_priorities3) Cycles thread running at priority level 2
+event:0X0631 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_5_CYC_GRP99 : (Group 99 pm_smt_priorities3) Cycles thread running at priority level 5
+event:0X0632 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP99 : (Group 99 pm_smt_priorities3) Cycles thread priority difference is -1 or -2
+event:0X0633 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP99 : (Group 99 pm_smt_priorities3) Cycles thread priority difference is -3 or -4
+
+#Group 100 pm_smt_priorities4, Thread priority events
+event:0X0640 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_1_CYC_GRP100 : (Group 100 pm_smt_priorities4) Cycles thread running at priority level 1
+event:0X0641 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP100 : (Group 100 pm_smt_priorities4) Hypervisor Cycles
+event:0X0642 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP100 : (Group 100 pm_smt_priorities4) Cycles thread priority difference is -5 or -6
+event:0X0643 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP100 : (Group 100 pm_smt_priorities4) Internal operations completed
+
+#Group 101 pm_smt_both, Thread common events
+event:0X0650 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP101 : (Group 101 pm_smt_both) One of the threads in run cycles
+event:0X0651 counters:1 um:zero minimum:1000 name:PM_THRD_GRP_CMPL_BOTH_CYC_GRP101 : (Group 101 pm_smt_both) Cycles group completed by both threads
+event:0X0652 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP101 : (Group 101 pm_smt_both) Internal operations completed
+event:0X0653 counters:3 um:zero minimum:1000 name:PM_THRD_L2MISS_BOTH_CYC_GRP101 : (Group 101 pm_smt_both) Cycles both threads in L2 misses
+
+#Group 102 pm_smt_selection, Thread selection
+event:0X0660 counters:0 um:zero minimum:1000 name:PM_SNOOP_TLBIE_GRP102 : (Group 102 pm_smt_selection) Snoop TLBIE
+event:0X0661 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP102 : (Group 102 pm_smt_selection) Internal operations completed
+event:0X0662 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_T0_GRP102 : (Group 102 pm_smt_selection) Decode selected thread 0
+event:0X0663 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_T1_GRP102 : (Group 102 pm_smt_selection) Decode selected thread 1
+
+#Group 103 pm_smt_selectover1, Thread selection overide
+event:0X0670 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP103 : (Group 103 pm_smt_selectover1) Internal operations completed
+event:0X0671 counters:1 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP103 : (Group 103 pm_smt_selectover1) Cycles no instructions in CLB
+event:0X0672 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_OVER_CLB_EMPTY_GRP103 : (Group 103 pm_smt_selectover1) Thread selection overrides caused by CLB empty
+event:0X0673 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_OVER_GCT_IMBAL_GRP103 : (Group 103 pm_smt_selectover1) Thread selection overrides caused by GCT imbalance
+
+#Group 104 pm_smt_selectover2, Thread selection overide
+event:0X0680 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP104 : (Group 104 pm_smt_selectover2) Internal operations completed
+event:0X0681 counters:1 um:zero minimum:10000 name:PM_CYC_GRP104 : (Group 104 pm_smt_selectover2) Processor cycles
+event:0X0682 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_OVER_ISU_HOLD_GRP104 : (Group 104 pm_smt_selectover2) Thread selection overrides caused by ISU holds
+event:0X0683 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_OVER_L2MISS_GRP104 : (Group 104 pm_smt_selectover2) Thread selection overrides caused by L2 misses
+
+#Group 105 pm_fabric1, Fabric events
+event:0X0690 counters:0 um:zero minimum:1000 name:PM_FAB_CMD_ISSUED_GRP105 : (Group 105 pm_fabric1) Fabric command issued
+event:0X0691 counters:1 um:zero minimum:1000 name:PM_FAB_DCLAIM_ISSUED_GRP105 : (Group 105 pm_fabric1) dclaim issued
+event:0X0692 counters:2 um:zero minimum:1000 name:PM_FAB_CMD_RETRIED_GRP105 : (Group 105 pm_fabric1) Fabric command retried
+event:0X0693 counters:3 um:zero minimum:1000 name:PM_FAB_DCLAIM_RETRIED_GRP105 : (Group 105 pm_fabric1) dclaim retried
+
+#Group 106 pm_fabric2, Fabric data movement
+event:0X06A0 counters:0 um:zero minimum:1000 name:PM_FAB_P1toM1_SIDECAR_EMPTY_GRP106 : (Group 106 pm_fabric2) P1 to M1 sidecar empty
+event:0X06A1 counters:1 um:zero minimum:1000 name:PM_FAB_HOLDtoVN_EMPTY_GRP106 : (Group 106 pm_fabric2) Hold buffer to VN empty
+event:0X06A2 counters:2 um:zero minimum:1000 name:PM_FAB_P1toVNorNN_SIDECAR_EMPTY_GRP106 : (Group 106 pm_fabric2) P1 to VN/NN sidecar empty
+event:0X06A3 counters:3 um:zero minimum:1000 name:PM_FAB_VBYPASS_EMPTY_GRP106 : (Group 106 pm_fabric2) Vertical bypass buffer empty
+
+#Group 107 pm_fabric3, Fabric data movement
+event:0X06B0 counters:0 um:zero minimum:1000 name:PM_FAB_PNtoNN_DIRECT_GRP107 : (Group 107 pm_fabric3) PN to NN beat went straight to its destination
+event:0X06B1 counters:1 um:zero minimum:1000 name:PM_FAB_PNtoVN_DIRECT_GRP107 : (Group 107 pm_fabric3) PN to VN beat went straight to its destination
+event:0X06B2 counters:2 um:zero minimum:1000 name:PM_FAB_PNtoNN_SIDECAR_GRP107 : (Group 107 pm_fabric3) PN to NN beat went to sidecar first
+event:0X06B3 counters:3 um:zero minimum:1000 name:PM_FAB_PNtoVN_SIDECAR_GRP107 : (Group 107 pm_fabric3) PN to VN beat went to sidecar first
+
+#Group 108 pm_fabric4, Fabric data movement
+event:0X06C0 counters:0 um:zero minimum:1000 name:PM_FAB_M1toP1_SIDECAR_EMPTY_GRP108 : (Group 108 pm_fabric4) M1 to P1 sidecar empty
+event:0X06C1 counters:1 um:zero minimum:1000 name:PM_FAB_HOLDtoNN_EMPTY_GRP108 : (Group 108 pm_fabric4) Hold buffer to NN empty
+event:0X06C2 counters:2 um:zero minimum:1000 name:PM_EE_OFF_GRP108 : (Group 108 pm_fabric4) Cycles MSR(EE) bit off
+event:0X06C3 counters:3 um:zero minimum:1000 name:PM_FAB_M1toVNorNN_SIDECAR_EMPTY_GRP108 : (Group 108 pm_fabric4) M1 to VN/NN sidecar empty
+
+#Group 109 pm_snoop1, Snoop retry
+event:0X06D0 counters:0 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_QFULL_GRP109 : (Group 109 pm_snoop1) Snoop read retry due to read queue full
+event:0X06D1 counters:1 um:zero minimum:1000 name:PM_SNOOP_DCLAIM_RETRY_QFULL_GRP109 : (Group 109 pm_snoop1) Snoop dclaim/flush retry due to write/dclaim queues full
+event:0X06D2 counters:2 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_QFULL_GRP109 : (Group 109 pm_snoop1) Snoop read retry due to read queue full
+event:0X06D3 counters:3 um:zero minimum:1000 name:PM_SNOOP_PARTIAL_RTRY_QFULL_GRP109 : (Group 109 pm_snoop1) Snoop partial write retry due to partial-write queues full
+
+#Group 110 pm_snoop2, Snoop read retry
+event:0X06E0 counters:0 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_RQ_GRP110 : (Group 110 pm_snoop2) Snoop read retry due to collision with active read queue
+event:0X06E1 counters:1 um:zero minimum:1000 name:PM_SNOOP_RETRY_1AHEAD_GRP110 : (Group 110 pm_snoop2) Snoop retry due to one ahead collision
+event:0X06E2 counters:2 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_WQ_GRP110 : (Group 110 pm_snoop2) Snoop read retry due to collision with active write queue
+event:0X06E3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP110 : (Group 110 pm_snoop2) Internal operations completed
+
+#Group 111 pm_snoop3, Snoop write retry
+event:0X06F0 counters:0 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_RQ_GRP111 : (Group 111 pm_snoop3) Snoop write/dclaim retry due to collision with active read queue
+event:0X06F1 counters:1 um:zero minimum:1000 name:PM_MEM_HI_PRIO_WR_CMPL_GRP111 : (Group 111 pm_snoop3) High priority write completed
+event:0X06F2 counters:2 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_WQ_GRP111 : (Group 111 pm_snoop3) Snoop write/dclaim retry due to collision with active write queue
+event:0X06F3 counters:3 um:zero minimum:1000 name:PM_MEM_LO_PRIO_WR_CMPL_GRP111 : (Group 111 pm_snoop3) Low priority write completed
+
+#Group 112 pm_snoop4, Snoop partial write retry
+event:0X0700 counters:0 um:zero minimum:1000 name:PM_SNOOP_PW_RETRY_RQ_GRP112 : (Group 112 pm_snoop4) Snoop partial-write retry due to collision with active read queue
+event:0X0701 counters:1 um:zero minimum:1000 name:PM_MEM_RQ_DISP_Q16to19_GRP112 : (Group 112 pm_snoop4) Memory read queue dispatched to queues 16-19
+event:0X0702 counters:2 um:zero minimum:1000 name:PM_SNOOP_PW_RETRY_WQ_PWQ_GRP112 : (Group 112 pm_snoop4) Snoop partial-write retry due to collision with active write or partial-write queue
+event:0X0703 counters:3 um:zero minimum:1000 name:PM_SNOOP_PW_RETRY_RQ_GRP112 : (Group 112 pm_snoop4) Snoop partial-write retry due to collision with active read queue
+
+#Group 113 pm_mem_rq, Memory read queue dispatch
+event:0X0710 counters:0 um:zero minimum:1000 name:PM_MEM_RQ_DISP_GRP113 : (Group 113 pm_mem_rq) Memory read queue dispatched
+event:0X0711 counters:1 um:zero minimum:1000 name:PM_MEM_SPEC_RD_CANCEL_GRP113 : (Group 113 pm_mem_rq) Speculative memory read cancelled
+event:0X0712 counters:2 um:zero minimum:1000 name:PM_MEM_NONSPEC_RD_CANCEL_GRP113 : (Group 113 pm_mem_rq) Non speculative memory read cancelled
+event:0X0713 counters:3 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP113 : (Group 113 pm_mem_rq) Cycles MSR(EE) bit off and external interrupt pending
+
+#Group 114 pm_mem_read, Memory read complete and cancel
+event:0X0720 counters:0 um:zero minimum:1000 name:PM_MEM_RQ_DISP_Q0to3_GRP114 : (Group 114 pm_mem_read) Memory read queue dispatched to queues 0-3
+event:0X0721 counters:1 um:zero minimum:1000 name:PM_MEM_RQ_DISP_Q8to11_GRP114 : (Group 114 pm_mem_read) Memory read queue dispatched to queues 8-11
+event:0X0722 counters:2 um:zero minimum:1000 name:PM_MEM_RQ_DISP_Q4to7_GRP114 : (Group 114 pm_mem_read) Memory read queue dispatched to queues 4-7
+event:0X0723 counters:3 um:zero minimum:1000 name:PM_EXT_INT_GRP114 : (Group 114 pm_mem_read) External interrupts
+
+#Group 115 pm_mem_wq, Memory write queue dispatch
+event:0X0730 counters:0 um:zero minimum:1000 name:PM_MEM_WQ_DISP_WRITE_GRP115 : (Group 115 pm_mem_wq) Memory write queue dispatched due to write
+event:0X0731 counters:1 um:zero minimum:1000 name:PM_MEM_WQ_DISP_Q0to7_GRP115 : (Group 115 pm_mem_wq) Memory write queue dispatched to queues 0-7
+event:0X0732 counters:2 um:zero minimum:1000 name:PM_MEM_WQ_DISP_DCLAIM_GRP115 : (Group 115 pm_mem_wq) Memory write queue dispatched due to dclaim/flush
+event:0X0733 counters:3 um:zero minimum:1000 name:PM_MEM_WQ_DISP_Q8to15_GRP115 : (Group 115 pm_mem_wq) Memory write queue dispatched to queues 8-15
+
+#Group 116 pm_mem_pwq, Memory partial write queue
+event:0X0740 counters:0 um:zero minimum:1000 name:PM_MEM_PWQ_DISP_GRP116 : (Group 116 pm_mem_pwq) Memory partial-write queue dispatched
+event:0X0741 counters:1 um:zero minimum:1000 name:PM_MEM_PW_CMPL_GRP116 : (Group 116 pm_mem_pwq) Memory partial-write completed
+event:0X0742 counters:2 um:zero minimum:1000 name:PM_MEM_PW_GATH_GRP116 : (Group 116 pm_mem_pwq) Memory partial-write gathered
+event:0X0743 counters:3 um:zero minimum:1000 name:PM_MEM_PWQ_DISP_Q2or3_GRP116 : (Group 116 pm_mem_pwq) Memory partial-write queue dispatched to Write Queue 2 or 3
+
+#Group 117 pm_threshold, Thresholding
+event:0X0750 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP117 : (Group 117 pm_threshold) Marked group dispatched
+event:0X0751 counters:1 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP117 : (Group 117 pm_threshold) Marked IMR reloaded
+event:0X0752 counters:2 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP117 : (Group 117 pm_threshold) Threshold timeout
+event:0X0753 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP117 : (Group 117 pm_threshold) Marked instruction LSU processing finished
+
+#Group 118 pm_mrk_grp1, Marked group events
+event:0X0760 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP118 : (Group 118 pm_mrk_grp1) Marked group dispatched
+event:0X0761 counters:1 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP118 : (Group 118 pm_mrk_grp1) Marked L1 D cache store misses
+event:0X0762 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP118 : (Group 118 pm_mrk_grp1) Marked instruction finished
+event:0X0763 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP118 : (Group 118 pm_mrk_grp1) Marked group completed
+
+#Group 119 pm_mrk_grp2, Marked group events
+event:0X0770 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP119 : (Group 119 pm_mrk_grp2) Marked group issued
+event:0X0771 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP119 : (Group 119 pm_mrk_grp2) Marked instruction BRU processing finished
+event:0X0772 counters:2 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP119 : (Group 119 pm_mrk_grp2) Marked L1 reload data source valid
+event:0X0773 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_IC_MISS_GRP119 : (Group 119 pm_mrk_grp2) Group experienced marked I cache miss
+
+#Group 120 pm_mrk_dsource1, Marked data from
+event:0X0780 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP120 : (Group 120 pm_mrk_dsource1) Marked data loaded from L2
+event:0X0781 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_CYC_GRP120 : (Group 120 pm_mrk_dsource1) Marked load latency from L2
+event:0X0782 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP120 : (Group 120 pm_mrk_dsource1) Marked data loaded from L2.5 modified
+event:0X0783 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_CYC_GRP120 : (Group 120 pm_mrk_dsource1) Marked load latency from L2.5 modified
+
+#Group 121 pm_mrk_dsource2, Marked data from
+event:0X0790 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP121 : (Group 121 pm_mrk_dsource2) Marked data loaded from L2.5 shared
+event:0X0791 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_CYC_GRP121 : (Group 121 pm_mrk_dsource2) Marked load latency from L2.5 shared
+event:0X0792 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP121 : (Group 121 pm_mrk_dsource2) Internal operations completed
+event:0X0793 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP121 : (Group 121 pm_mrk_dsource2) FPU produced a result
+
+#Group 122 pm_mrk_dsource3, Marked data from
+event:0X07A0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP122 : (Group 122 pm_mrk_dsource3) Marked data loaded from L3
+event:0X07A1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_CYC_GRP122 : (Group 122 pm_mrk_dsource3) Marked load latency from L3
+event:0X07A2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_GRP122 : (Group 122 pm_mrk_dsource3) Marked data loaded from L3.5 modified
+event:0X07A3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_CYC_GRP122 : (Group 122 pm_mrk_dsource3) Marked load latency from L3.5 modified
+
+#Group 123 pm_mrk_dsource4, Marked data from
+event:0X07B0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_GRP123 : (Group 123 pm_mrk_dsource4) Marked data loaded from remote memory
+event:0X07B1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_CYC_GRP123 : (Group 123 pm_mrk_dsource4) Marked load latency from L2.75 shared
+event:0X07B2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_GRP123 : (Group 123 pm_mrk_dsource4) Marked data loaded from L2.75 shared
+event:0X07B3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_CYC_GRP123 : (Group 123 pm_mrk_dsource4) Marked load latency from remote memory
+
+#Group 124 pm_mrk_dsource5, Marked data from
+event:0X07C0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_GRP124 : (Group 124 pm_mrk_dsource5) Marked data loaded from L3.5 shared
+event:0X07C1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_CYC_GRP124 : (Group 124 pm_mrk_dsource5) Marked load latency from L3.5 shared
+event:0X07C2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_GRP124 : (Group 124 pm_mrk_dsource5) Marked data loaded from local memory
+event:0X07C3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_CYC_GRP124 : (Group 124 pm_mrk_dsource5) Marked load latency from local memory
+
+#Group 125 pm_mrk_dsource6, Marked data from
+event:0X07D0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP125 : (Group 125 pm_mrk_dsource6) Marked data loaded from L2.75 modified
+event:0X07D1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_CYC_GRP125 : (Group 125 pm_mrk_dsource6) Marked load latency from L2.75 shared
+event:0X07D2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP125 : (Group 125 pm_mrk_dsource6) Internal operations completed
+event:0X07D3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_CYC_GRP125 : (Group 125 pm_mrk_dsource6) Marked load latency from L2.75 modified
+
+#Group 126 pm_mrk_dsource7, Marked data from
+event:0X07E0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_MOD_GRP126 : (Group 126 pm_mrk_dsource7) Marked data loaded from L3.75 modified
+event:0X07E1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_SHR_CYC_GRP126 : (Group 126 pm_mrk_dsource7) Marked load latency from L3.75 shared
+event:0X07E2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_SHR_GRP126 : (Group 126 pm_mrk_dsource7) Marked data loaded from L3.75 shared
+event:0X07E3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_MOD_CYC_GRP126 : (Group 126 pm_mrk_dsource7) Marked load latency from L3.75 modified
+
+#Group 127 pm_mrk_dtlbref, Marked data TLB references
+event:0X07F0 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_4K_GRP127 : (Group 127 pm_mrk_dtlbref) Marked Data TLB reference for 4K page
+event:0X07F1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_REF_64K_GRP127 : (Group 127 pm_mrk_dtlbref) Marked Data TLB reference for 64K page
+event:0X07F2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16M_GRP127 : (Group 127 pm_mrk_dtlbref) Marked Data TLB reference for 16M page
+event:0X07F3 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16G_GRP127 : (Group 127 pm_mrk_dtlbref) Marked Data TLB reference for 16G page
+
+#Group 128 pm_mrk_dtlbmiss, Marked data TLB misses
+event:0X0800 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP128 : (Group 128 pm_mrk_dtlbmiss) Marked Data TLB misses for 4K page
+event:0X0801 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_64K_GRP128 : (Group 128 pm_mrk_dtlbmiss) Marked Data TLB misses for 64K page
+event:0X0802 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16M_GRP128 : (Group 128 pm_mrk_dtlbmiss) Marked Data TLB misses for 16M page
+event:0X0803 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16G_GRP128 : (Group 128 pm_mrk_dtlbmiss) Marked Data TLB misses for 16G page
+
+#Group 129 pm_mrk_dtlb_dslb, Marked data TLB references and misses and marked data SLB misses
+event:0X0810 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Marked Data TLB reference
+event:0X0811 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Marked Data TLB misses
+event:0X0812 counters:2 um:zero minimum:1000 name:PM_MRK_DSLB_MISS_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Marked Data SLB misses
+event:0X0813 counters:3 um:zero minimum:10000 name:PM_CYC_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Processor cycles
+
+#Group 130 pm_mrk_lbref, Marked TLB and SLB references
+event:0X0820 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_4K_GRP130 : (Group 130 pm_mrk_lbref) Marked Data TLB reference for 4K page
+event:0X0821 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP130 : (Group 130 pm_mrk_lbref) Internal operations completed
+event:0X0822 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16M_GRP130 : (Group 130 pm_mrk_lbref) Marked Data TLB reference for 16M page
+event:0X0823 counters:3 um:zero minimum:1000 name:PM_MRK_DSLB_MISS_GRP130 : (Group 130 pm_mrk_lbref) Marked Data SLB misses
+
+#Group 131 pm_mrk_lsmiss, Marked load and store miss
+event:0X0830 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP131 : (Group 131 pm_mrk_lsmiss) Marked L1 D cache load misses
+event:0X0831 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP131 : (Group 131 pm_mrk_lsmiss) Internal operations completed
+event:0X0832 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP131 : (Group 131 pm_mrk_lsmiss) Marked store completed with intervention
+event:0X0833 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP131 : (Group 131 pm_mrk_lsmiss) Marked instruction CRU processing finished
+
+#Group 132 pm_mrk_ulsflush, Mark unaligned load and store flushes
+event:0X0840 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP132 : (Group 132 pm_mrk_ulsflush) Marked store instruction completed
+event:0X0841 counters:1 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP132 : (Group 132 pm_mrk_ulsflush) Marked L1 D cache store misses
+event:0X0842 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_UST_GRP132 : (Group 132 pm_mrk_ulsflush) Marked unaligned store flushes
+event:0X0843 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_ULD_GRP132 : (Group 132 pm_mrk_ulsflush) Marked unaligned load flushes
+
+#Group 133 pm_mrk_misc, Misc marked instructions
+event:0X0850 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP133 : (Group 133 pm_mrk_misc) Marked STCX failed
+event:0X0851 counters:1 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP133 : (Group 133 pm_mrk_misc) Marked store sent to GPS
+event:0X0852 counters:2 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP133 : (Group 133 pm_mrk_misc) Marked instruction FPU processing finished
+event:0X0853 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP133 : (Group 133 pm_mrk_misc) Marked group completion timeout
+
+#Group 134 pm_lsref_L1, Load/Store operations and L1 activity
+event:0X0860 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP134 : (Group 134 pm_lsref_L1) Data loaded from L2
+event:0X0861 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP134 : (Group 134 pm_lsref_L1) Instruction fetched from L1
+event:0X0862 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP134 : (Group 134 pm_lsref_L1) L1 D cache store references
+event:0X0863 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP134 : (Group 134 pm_lsref_L1) L1 D cache load references
+
+#Group 135 pm_lsref_L2L3, Load/Store operations and L2, L3 activity
+event:0X0870 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP135 : (Group 135 pm_lsref_L2L3) Data loaded from L3
+event:0X0871 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP135 : (Group 135 pm_lsref_L2L3) Data loaded from local memory
+event:0X0872 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP135 : (Group 135 pm_lsref_L2L3) L1 D cache store references
+event:0X0873 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP135 : (Group 135 pm_lsref_L2L3) L1 D cache load references
+
+#Group 136 pm_lsref_tlbmiss, Load/Store operations and TLB misses
+event:0X0880 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP136 : (Group 136 pm_lsref_tlbmiss) Instruction TLB misses
+event:0X0881 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP136 : (Group 136 pm_lsref_tlbmiss) Data TLB misses
+event:0X0882 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP136 : (Group 136 pm_lsref_tlbmiss) L1 D cache store references
+event:0X0883 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP136 : (Group 136 pm_lsref_tlbmiss) L1 D cache load references
+
+#Group 137 pm_Dmiss, Data cache misses
+event:0X0890 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP137 : (Group 137 pm_Dmiss) Data loaded from L3
+event:0X0891 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP137 : (Group 137 pm_Dmiss) Data loaded from local memory
+event:0X0892 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP137 : (Group 137 pm_Dmiss) L1 D cache load misses
+event:0X0893 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP137 : (Group 137 pm_Dmiss) L1 D cache store misses
+
+#Group 138 pm_prefetchX, Prefetch events
+event:0X08A0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP138 : (Group 138 pm_prefetchX) Processor cycles
+event:0X08A1 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP138 : (Group 138 pm_prefetchX) Instruction prefetch requests
+event:0X08A2 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP138 : (Group 138 pm_prefetchX) L1 cache data prefetches
+event:0X08A3 counters:3 um:zero minimum:1000 name:PM_L2_PREF_GRP138 : (Group 138 pm_prefetchX) L2 cache prefetches
+
+#Group 139 pm_branchX, Branch operations
+event:0X08B0 counters:0 um:zero minimum:1000 name:PM_BR_UNCOND_GRP139 : (Group 139 pm_branchX) Unconditional branch
+event:0X08B1 counters:1 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP139 : (Group 139 pm_branchX) A conditional branch was predicted, target prediction
+event:0X08B2 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP139 : (Group 139 pm_branchX) A conditional branch was predicted, CR prediction
+event:0X08B3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP139 : (Group 139 pm_branchX) Branches issued
+
+#Group 140 pm_fpuX1, Floating point events by unit
+event:0X08C0 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP140 : (Group 140 pm_fpuX1) FPU0 stalled in pipe3
+event:0X08C1 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP140 : (Group 140 pm_fpuX1) FPU1 stalled in pipe3
+event:0X08C2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP140 : (Group 140 pm_fpuX1) FPU0 produced a result
+event:0X08C3 counters:3 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP140 : (Group 140 pm_fpuX1) FPU0 executed FPSCR instruction
+
+#Group 141 pm_fpuX2, Floating point events by unit
+event:0X08D0 counters:0 um:zero minimum:1000 name:PM_FPU0_FMA_GRP141 : (Group 141 pm_fpuX2) FPU0 executed multiply-add instruction
+event:0X08D1 counters:1 um:zero minimum:1000 name:PM_FPU1_FMA_GRP141 : (Group 141 pm_fpuX2) FPU1 executed multiply-add instruction
+event:0X08D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP141 : (Group 141 pm_fpuX2) FPU0 executed FRSP or FCONV instructions
+event:0X08D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP141 : (Group 141 pm_fpuX2) FPU1 executed FRSP or FCONV instructions
+
+#Group 142 pm_fpuX3, Floating point events by unit
+event:0X08E0 counters:0 um:zero minimum:1000 name:PM_FPU0_1FLOP_GRP142 : (Group 142 pm_fpuX3) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X08E1 counters:1 um:zero minimum:1000 name:PM_FPU1_1FLOP_GRP142 : (Group 142 pm_fpuX3) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X08E2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP142 : (Group 142 pm_fpuX3) FPU0 produced a result
+event:0X08E3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP142 : (Group 142 pm_fpuX3) FPU1 produced a result
+
+#Group 143 pm_fpuX4, Floating point and L1 events
+event:0X08F0 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP143 : (Group 143 pm_fpuX4) FPU executed one flop instruction
+event:0X08F1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP143 : (Group 143 pm_fpuX4) FPU executed multiply-add instruction
+event:0X08F2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP143 : (Group 143 pm_fpuX4) L1 D cache store references
+event:0X08F3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP143 : (Group 143 pm_fpuX4) L1 D cache load references
+
+#Group 144 pm_fpuX5, Floating point events
+event:0X0900 counters:0 um:zero minimum:1000 name:PM_FPU_SINGLE_GRP144 : (Group 144 pm_fpuX5) FPU executed single precision instruction
+event:0X0901 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP144 : (Group 144 pm_fpuX5) FPU executed store instruction
+event:0X0902 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP144 : (Group 144 pm_fpuX5) FPU0 produced a result
+event:0X0903 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP144 : (Group 144 pm_fpuX5) FPU1 produced a result
+
+#Group 145 pm_fpuX6, Floating point events
+event:0X0910 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP145 : (Group 145 pm_fpuX6) FPU executed FDIV instruction
+event:0X0911 counters:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP145 : (Group 145 pm_fpuX6) FPU executed FSQRT instruction
+event:0X0912 counters:2 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP145 : (Group 145 pm_fpuX6) FPU executed FRSP or FCONV instructions
+event:0X0913 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP145 : (Group 145 pm_fpuX6) FPU produced a result
+
+#Group 146 pm_fpuX7, Floating point events
+event:0X0920 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP146 : (Group 146 pm_fpuX7) FPU executed one flop instruction
+event:0X0921 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP146 : (Group 146 pm_fpuX7) FPU executed multiply-add instruction
+event:0X0922 counters:2 um:zero minimum:1000 name:PM_FPU_STF_GRP146 : (Group 146 pm_fpuX7) FPU executed store instruction
+event:0X0923 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP146 : (Group 146 pm_fpuX7) FPU produced a result
+
+#Group 147 pm_hpmcount8, HPM group for set 9
+event:0X0930 counters:0 um:zero minimum:10000 name:PM_CYC_GRP147 : (Group 147 pm_hpmcount8) Processor cycles
+event:0X0931 counters:1 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP147 : (Group 147 pm_hpmcount8) Marked instruction FXU processing finished
+event:0X0932 counters:2 um:zero minimum:10000 name:PM_CYC_GRP147 : (Group 147 pm_hpmcount8) Processor cycles
+event:0X0933 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP147 : (Group 147 pm_hpmcount8) FPU produced a result
+
+#Group 148 pm_hpmcount2, HPM group for set 2
+event:0X0940 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP148 : (Group 148 pm_hpmcount2) Instructions completed
+event:0X0941 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP148 : (Group 148 pm_hpmcount2) FPU executed store instruction
+event:0X0942 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP148 : (Group 148 pm_hpmcount2) Instructions dispatched
+event:0X0943 counters:3 um:zero minimum:1000 name:PM_LSU_LDF_GRP148 : (Group 148 pm_hpmcount2) LSU executed Floating Point load instruction
+
+#Group 149 pm_hpmcount3, HPM group for set 3
+event:0X0950 counters:0 um:zero minimum:10000 name:PM_CYC_GRP149 : (Group 149 pm_hpmcount3) Processor cycles
+event:0X0951 counters:1 um:zero minimum:1000 name:PM_INST_DISP_ATTEMPT_GRP149 : (Group 149 pm_hpmcount3) Instructions dispatch attempted
+event:0X0952 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP149 : (Group 149 pm_hpmcount3) L1 D cache load misses
+event:0X0953 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP149 : (Group 149 pm_hpmcount3) L1 D cache store misses
+
+#Group 150 pm_hpmcount4, HPM group for set 7
+event:0X0960 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP150 : (Group 150 pm_hpmcount4) TLB misses
+event:0X0961 counters:1 um:zero minimum:10000 name:PM_CYC_GRP150 : (Group 150 pm_hpmcount4) Processor cycles
+event:0X0962 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP150 : (Group 150 pm_hpmcount4) L1 D cache store references
+event:0X0963 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP150 : (Group 150 pm_hpmcount4) L1 D cache load references
+
+#Group 151 pm_flop, Floating point operations
+event:0X0970 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP151 : (Group 151 pm_flop) FPU executed FDIV instruction
+event:0X0971 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP151 : (Group 151 pm_flop) FPU executed multiply-add instruction
+event:0X0972 counters:2 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP151 : (Group 151 pm_flop) FPU executed FSQRT instruction
+event:0X0973 counters:3 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP151 : (Group 151 pm_flop) FPU executed one flop instruction
+
+#Group 152 pm_eprof1, Group for use with eprof
+event:0X0980 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP152 : (Group 152 pm_eprof1) Instructions completed
+event:0X0981 counters:1 um:zero minimum:10000 name:PM_CYC_GRP152 : (Group 152 pm_eprof1) Processor cycles
+event:0X0982 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP152 : (Group 152 pm_eprof1) L1 D cache load misses
+event:0X0983 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP152 : (Group 152 pm_eprof1) L1 D cache entries invalidated from L2
+
+#Group 153 pm_eprof2, Group for use with eprof
+event:0X0990 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP153 : (Group 153 pm_eprof2) Instructions completed
+event:0X0991 counters:1 um:zero minimum:1000 name:PM_ST_REF_L1_GRP153 : (Group 153 pm_eprof2) L1 D cache store references
+event:0X0992 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP153 : (Group 153 pm_eprof2) Instructions dispatched
+event:0X0993 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP153 : (Group 153 pm_eprof2) L1 D cache load references
+
+#Group 154 pm_flip, Group for flips
+event:0X09A0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP154 : (Group 154 pm_flip) Processor cycles
+event:0X09A1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP154 : (Group 154 pm_flip) FPU executed multiply-add instruction
+event:0X09A2 counters:2 um:zero minimum:1000 name:PM_FPU_STF_GRP154 : (Group 154 pm_flip) FPU executed store instruction
+event:0X09A3 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP154 : (Group 154 pm_flip) FPU produced a result
+
+#Group 155 pm_hpmcount5, HPM group for set 5
+event:0X09B0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP155 : (Group 155 pm_hpmcount5) Processor cycles
+event:0X09B1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP155 : (Group 155 pm_hpmcount5) Data TLB misses
+event:0X09B2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP155 : (Group 155 pm_hpmcount5) L1 D cache load misses
+event:0X09B3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP155 : (Group 155 pm_hpmcount5) L1 D cache load references
+
+#Group 156 pm_hpmcount6, HPM group for set 6
+event:0X09C0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP156 : (Group 156 pm_hpmcount6) Processor cycles
+event:0X09C1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP156 : (Group 156 pm_hpmcount6) Instructions completed
+event:0X09C2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP156 : (Group 156 pm_hpmcount6) L1 D cache store references
+event:0X09C3 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP156 : (Group 156 pm_hpmcount6) L1 D cache store misses
+
+#Group 157 pm_hpmcount7, HPM group for set 8
+event:0X09D0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP157 : (Group 157 pm_hpmcount7) Instructions completed
+event:0X09D1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP157 : (Group 157 pm_hpmcount7) Data loaded from local memory
+event:0X09D2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP157 : (Group 157 pm_hpmcount7) Processor cycles
+event:0X09D3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP157 : (Group 157 pm_hpmcount7) Data loaded from remote memory
+
+#Group 158 pm_ep_threshold, Thresholding
+event:0X09E0 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP158 : (Group 158 pm_ep_threshold) Marked group dispatched
+event:0X09E1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP158 : (Group 158 pm_ep_threshold) Instructions completed
+event:0X09E2 counters:2 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP158 : (Group 158 pm_ep_threshold) Threshold timeout
+event:0X09E3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP158 : (Group 158 pm_ep_threshold) Marked instruction LSU processing finished
+
+#Group 159 pm_ep_mrk_grp1, Marked group events
+event:0X09F0 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP159 : (Group 159 pm_ep_mrk_grp1) Marked group dispatched
+event:0X09F1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP159 : (Group 159 pm_ep_mrk_grp1) Instructions completed
+event:0X09F2 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP159 : (Group 159 pm_ep_mrk_grp1) Marked instruction finished
+event:0X09F3 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP159 : (Group 159 pm_ep_mrk_grp1) Marked group completed
+
+#Group 160 pm_ep_mrk_grp2, Marked group events
+event:0X0A00 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP160 : (Group 160 pm_ep_mrk_grp2) Marked group issued
+event:0X0A01 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP160 : (Group 160 pm_ep_mrk_grp2) Instructions completed
+event:0X0A02 counters:2 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP160 : (Group 160 pm_ep_mrk_grp2) Marked L1 reload data source valid
+event:0X0A03 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_IC_MISS_GRP160 : (Group 160 pm_ep_mrk_grp2) Group experienced marked I cache miss
+
+#Group 161 pm_ep_mrk_dsource1, Marked data from
+event:0X0A10 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP161 : (Group 161 pm_ep_mrk_dsource1) Marked data loaded from L2
+event:0X0A11 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP161 : (Group 161 pm_ep_mrk_dsource1) Instructions completed
+event:0X0A12 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP161 : (Group 161 pm_ep_mrk_dsource1) Marked data loaded from L2.5 modified
+event:0X0A13 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_CYC_GRP161 : (Group 161 pm_ep_mrk_dsource1) Marked load latency from L2.5 modified
+
+#Group 162 pm_ep_mrk_dsource2, Marked data from
+event:0X0A20 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP162 : (Group 162 pm_ep_mrk_dsource2) Marked data loaded from L2.5 shared
+event:0X0A21 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP162 : (Group 162 pm_ep_mrk_dsource2) Instructions completed
+event:0X0A22 counters:2 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP162 : (Group 162 pm_ep_mrk_dsource2) Marked IMR reloaded
+event:0X0A23 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP162 : (Group 162 pm_ep_mrk_dsource2) FPU produced a result
+
+#Group 163 pm_ep_mrk_dsource3, Marked data from
+event:0X0A30 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP163 : (Group 163 pm_ep_mrk_dsource3) Instructions completed
+event:0X0A31 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_CYC_GRP163 : (Group 163 pm_ep_mrk_dsource3) Marked load latency from L3
+event:0X0A32 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_GRP163 : (Group 163 pm_ep_mrk_dsource3) Marked data loaded from L3.5 modified
+event:0X0A33 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_CYC_GRP163 : (Group 163 pm_ep_mrk_dsource3) Marked load latency from L3.5 modified
+
+#Group 164 pm_ep_mrk_dsource4, Marked data from
+event:0X0A40 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP164 : (Group 164 pm_ep_mrk_dsource4) Instructions completed
+event:0X0A41 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_CYC_GRP164 : (Group 164 pm_ep_mrk_dsource4) Marked load latency from L2.75 shared
+event:0X0A42 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_GRP164 : (Group 164 pm_ep_mrk_dsource4) Marked data loaded from L2.75 shared
+event:0X0A43 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_CYC_GRP164 : (Group 164 pm_ep_mrk_dsource4) Marked load latency from remote memory
+
+#Group 165 pm_ep_mrk_dsource5, Marked data from
+event:0X0A50 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_GRP165 : (Group 165 pm_ep_mrk_dsource5) Marked data loaded from L3.5 shared
+event:0X0A51 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP165 : (Group 165 pm_ep_mrk_dsource5) Instructions completed
+event:0X0A52 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_GRP165 : (Group 165 pm_ep_mrk_dsource5) Marked data loaded from local memory
+event:0X0A53 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_CYC_GRP165 : (Group 165 pm_ep_mrk_dsource5) Marked load latency from local memory
+
+#Group 166 pm_ep_mrk_dsource6, Marked data from
+event:0X0A60 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP166 : (Group 166 pm_ep_mrk_dsource6) Instructions completed
+event:0X0A61 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_CYC_GRP166 : (Group 166 pm_ep_mrk_dsource6) Marked load latency from L2.75 shared
+event:0X0A62 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP166 : (Group 166 pm_ep_mrk_dsource6) Internal operations completed
+event:0X0A63 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_CYC_GRP166 : (Group 166 pm_ep_mrk_dsource6) Marked load latency from L2.75 modified
+
+#Group 167 pm_ep_mrk_dsource7, Marked data from
+event:0X0A70 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP167 : (Group 167 pm_ep_mrk_dsource7) Instructions completed
+event:0X0A71 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_SHR_CYC_GRP167 : (Group 167 pm_ep_mrk_dsource7) Marked load latency from L3.75 shared
+event:0X0A72 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_SHR_GRP167 : (Group 167 pm_ep_mrk_dsource7) Marked data loaded from L3.75 shared
+event:0X0A73 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_MOD_CYC_GRP167 : (Group 167 pm_ep_mrk_dsource7) Marked load latency from L3.75 modified
+
+#Group 168 pm_ep_mrk_lbmiss, Marked TLB and SLB misses
+event:0X0A80 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP168 : (Group 168 pm_ep_mrk_lbmiss) Instructions completed
+event:0X0A81 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_64K_GRP168 : (Group 168 pm_ep_mrk_lbmiss) Marked Data TLB misses for 64K page
+event:0X0A82 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16M_GRP168 : (Group 168 pm_ep_mrk_lbmiss) Marked Data TLB misses for 16M page
+event:0X0A83 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16G_GRP168 : (Group 168 pm_ep_mrk_lbmiss) Marked Data TLB misses for 16G page
+
+#Group 169 pm_ep_mrk_dtlbref, Marked data TLB references
+event:0X0A90 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP169 : (Group 169 pm_ep_mrk_dtlbref) Instructions completed
+event:0X0A91 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_REF_64K_GRP169 : (Group 169 pm_ep_mrk_dtlbref) Marked Data TLB reference for 64K page
+event:0X0A92 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16M_GRP169 : (Group 169 pm_ep_mrk_dtlbref) Marked Data TLB reference for 16M page
+event:0X0A93 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16G_GRP169 : (Group 169 pm_ep_mrk_dtlbref) Marked Data TLB reference for 16G page
+
+#Group 170 pm_ep_mrk_dtlbmiss, Marked data TLB misses
+event:0X0AA0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP170 : (Group 170 pm_ep_mrk_dtlbmiss) Instructions completed
+event:0X0AA1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_64K_GRP170 : (Group 170 pm_ep_mrk_dtlbmiss) Marked Data TLB misses for 64K page
+event:0X0AA2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16M_GRP170 : (Group 170 pm_ep_mrk_dtlbmiss) Marked Data TLB misses for 16M page
+event:0X0AA3 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16G_GRP170 : (Group 170 pm_ep_mrk_dtlbmiss) Marked Data TLB misses for 16G page
+
+#Group 171 pm_ep_mrk_lbref, Marked TLB and SLB references
+event:0X0AB0 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_4K_GRP171 : (Group 171 pm_ep_mrk_lbref) Marked Data TLB reference for 4K page
+event:0X0AB1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP171 : (Group 171 pm_ep_mrk_lbref) Instructions completed
+event:0X0AB2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16M_GRP171 : (Group 171 pm_ep_mrk_lbref) Marked Data TLB reference for 16M page
+event:0X0AB3 counters:3 um:zero minimum:1000 name:PM_MRK_DSLB_MISS_GRP171 : (Group 171 pm_ep_mrk_lbref) Marked Data SLB misses
+
+#Group 172 pm_ep_mrk_lsmiss, Marked load and store miss
+event:0X0AC0 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP172 : (Group 172 pm_ep_mrk_lsmiss) Marked L1 D cache load misses
+event:0X0AC1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP172 : (Group 172 pm_ep_mrk_lsmiss) Instructions completed
+event:0X0AC2 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP172 : (Group 172 pm_ep_mrk_lsmiss) Marked store completed with intervention
+event:0X0AC3 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP172 : (Group 172 pm_ep_mrk_lsmiss) Marked instruction CRU processing finished
+
+#Group 173 pm_ep_mrk_ulsflush, Mark unaligned load and store flushes
+event:0X0AD0 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP173 : (Group 173 pm_ep_mrk_ulsflush) Marked store instruction completed
+event:0X0AD1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP173 : (Group 173 pm_ep_mrk_ulsflush) Instructions completed
+event:0X0AD2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_UST_GRP173 : (Group 173 pm_ep_mrk_ulsflush) Marked unaligned store flushes
+event:0X0AD3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_ULD_GRP173 : (Group 173 pm_ep_mrk_ulsflush) Marked unaligned load flushes
+
+#Group 174 pm_ep_mrk_misc1, Misc marked instructions
+event:0X0AE0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP174 : (Group 174 pm_ep_mrk_misc1) Instructions completed
+event:0X0AE1 counters:1 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP174 : (Group 174 pm_ep_mrk_misc1) Marked store sent to GPS
+event:0X0AE2 counters:2 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP174 : (Group 174 pm_ep_mrk_misc1) Marked instruction FPU processing finished
+event:0X0AE3 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP174 : (Group 174 pm_ep_mrk_misc1) Marked group completion timeout
+
+#Group 175 pm_ep_mrk_misc2, Misc marked instructions
+event:0X0AF0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP175 : (Group 175 pm_ep_mrk_misc2) Instructions completed
+event:0X0AF1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_CYC_GRP175 : (Group 175 pm_ep_mrk_misc2) Marked load latency from L2.5 shared
+event:0X0AF2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP175 : (Group 175 pm_ep_mrk_misc2) Marked data loaded from L3
+event:0X0AF3 counters:3 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP175 : (Group 175 pm_ep_mrk_misc2) Marked IMR reloaded
+
+#Group 176 pm_ep_mrk_misc3, Misc marked instructions
+event:0X0B00 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP176 : (Group 176 pm_ep_mrk_misc3) Instructions completed
+event:0X0B01 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_CYC_GRP176 : (Group 176 pm_ep_mrk_misc3) Marked load latency from L3.5 shared
+event:0X0B02 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_GRP176 : (Group 176 pm_ep_mrk_misc3) Marked Data TLB misses
+event:0X0B03 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_GRP176 : (Group 176 pm_ep_mrk_misc3) Marked data loaded from remote memory
+
+#Group 177 pm_ep_mrk_misc4, Misc marked instructions
+event:0X0B10 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP177 : (Group 177 pm_ep_mrk_misc4) Marked Data TLB misses for 4K page
+event:0X0B11 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP177 : (Group 177 pm_ep_mrk_misc4) Instructions completed
+event:0X0B12 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_GRP177 : (Group 177 pm_ep_mrk_misc4) Marked Data TLB reference
+event:0X0B13 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP177 : (Group 177 pm_ep_mrk_misc4) Marked data loaded from L2.75 modified
+
+#Group 178 pm_ep_mrk_misc5, Misc marked instructions
+event:0X0B20 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_4K_GRP178 : (Group 178 pm_ep_mrk_misc5) Marked Data TLB reference for 4K page
+event:0X0B21 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP178 : (Group 178 pm_ep_mrk_misc5) Instructions completed
+event:0X0B22 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP178 : (Group 178 pm_ep_mrk_misc5) Internal operations completed
+event:0X0B23 counters:3 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_SRQ_GRP178 : (Group 178 pm_ep_mrk_misc5) LSU0 marked SRQ lhs flushes
+
+#Group 179 pm_ep_mrk_misc6, Misc marked instructions
+event:0X0B30 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP179 : (Group 179 pm_ep_mrk_misc6) Marked Data TLB misses for 4K page
+event:0X0B31 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP179 : (Group 179 pm_ep_mrk_misc6) Instructions completed
+event:0X0B32 counters:2 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_ULD_GRP179 : (Group 179 pm_ep_mrk_misc6) LSU1 marked unaligned load flushes
+event:0X0B33 counters:3 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_UST_GRP179 : (Group 179 pm_ep_mrk_misc6) LSU1 marked unaligned store flushes
+
+#Group 180 pm_ep_mrk_misc7, Misc marked instructions
+event:0X0B40 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP180 : (Group 180 pm_ep_mrk_misc7) Instructions completed
+event:0X0B41 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_CYC_GRP180 : (Group 180 pm_ep_mrk_misc7) Marked load latency from L2
+event:0X0B42 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_ULD_GRP180 : (Group 180 pm_ep_mrk_misc7) LSU0 marked unaligned load flushes
+event:0X0B43 counters:3 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_UST_GRP180 : (Group 180 pm_ep_mrk_misc7) LSU0 marked unaligned store flushes
+
+#Group 181 pm_ep_mrk_misc8, Misc marked instructions
+event:0X0B50 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP181 : (Group 181 pm_ep_mrk_misc8) Instructions completed
+event:0X0B51 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP181 : (Group 181 pm_ep_mrk_misc8) Marked instruction BRU processing finished
+event:0X0B52 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_LRQ_GRP181 : (Group 181 pm_ep_mrk_misc8) LSU0 marked LRQ flushes
+event:0X0B53 counters:3 um:zero minimum:1000 name:PM_MRK_LSU0_FLUSH_SRQ_GRP181 : (Group 181 pm_ep_mrk_misc8) LSU0 marked SRQ lhs flushes
+
+#Group 182 pm_ep_mrk_misc9, Misc marked instructions
+event:0X0B60 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP182 : (Group 182 pm_ep_mrk_misc9) Instructions completed
+event:0X0B61 counters:1 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_LRQ_GRP182 : (Group 182 pm_ep_mrk_misc9) LSU1 marked LRQ flushes
+event:0X0B62 counters:2 um:zero minimum:1000 name:PM_MRK_LSU1_FLUSH_SRQ_GRP182 : (Group 182 pm_ep_mrk_misc9) LSU1 marked SRQ lhs flushes
+event:0X0B63 counters:3 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP182 : (Group 182 pm_ep_mrk_misc9) Marked STCX failed
+
+#Group 183 pm_ep_mrk_misc10, Misc marked instructions
+event:0X0B70 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP183 : (Group 183 pm_ep_mrk_misc10) Instructions completed
+event:0X0B71 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU0_GRP183 : (Group 183 pm_ep_mrk_misc10) LSU0 marked L1 D cache load misses
+event:0X0B72 counters:2 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_LSU1_GRP183 : (Group 183 pm_ep_mrk_misc10) LSU1 marked L1 D cache load misses
+event:0X0B73 counters:3 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP183 : (Group 183 pm_ep_mrk_misc10) Marked L1 D cache store misses
+
+#Group 184 pm_ep_mrk_misc11, Misc marked instructions
+event:0X0B80 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP184 : (Group 184 pm_ep_mrk_misc11) Instructions completed
+event:0X0B81 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP184 : (Group 184 pm_ep_mrk_misc11) Marked instruction BRU processing finished
+event:0X0B82 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP184 : (Group 184 pm_ep_mrk_misc11) Marked data loaded from L2.5 modified
+event:0X0B83 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_MOD_GRP184 : (Group 184 pm_ep_mrk_misc11) Marked data loaded from L3.75 modified
+
+#Group 185 pm_ep_mrk_misc12, Misc marked instructions
+event:0X0B90 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP185 : (Group 185 pm_ep_mrk_misc12) Instructions completed
+event:0X0B91 counters:1 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_UST_GRP185 : (Group 185 pm_ep_mrk_misc12) Marked unaligned store flushes
+event:0X0B92 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP185 : (Group 185 pm_ep_mrk_misc12) Marked LRQ flushes
+event:0X0B93 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_GRP185 : (Group 185 pm_ep_mrk_misc12) Marked SRQ lhs flushes
+
+#Group 186 pm_ep_mrk_misc13, Misc marked instructions
+event:0X0BA0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP186 : (Group 186 pm_ep_mrk_misc13) Marked data loaded from L2
+event:0X0BA1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP186 : (Group 186 pm_ep_mrk_misc13) Instructions completed
+event:0X0BA2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2MISS_GRP186 : (Group 186 pm_ep_mrk_misc13) Marked data loaded missed L2
+event:0X0BA3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP186 : (Group 186 pm_ep_mrk_misc13) Marked instruction valid in SRQ
+
+#Group 187 pm_ep_mrk_misc14, Misc marked instructions
+event:0X0BB0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP187 : (Group 187 pm_ep_mrk_misc14) Instructions completed
+event:0X0BB1 counters:1 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP187 : (Group 187 pm_ep_mrk_misc14) Marked instruction FXU processing finished
+event:0X0BB2 counters:2 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP187 : (Group 187 pm_ep_mrk_misc14) Marked instruction FPU processing finished
+event:0X0BB3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP187 : (Group 187 pm_ep_mrk_misc14) Marked instruction LSU processing finished
+
+#Group 188 pm_ep_mrk_misc15, Misc marked instructions
+event:0X0BC0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP188 : (Group 188 pm_ep_mrk_misc15) Instructions completed
+event:0X0BC1 counters:1 um:zero minimum:1000 name:PM_MRK_GRP_BR_REDIR_GRP188 : (Group 188 pm_ep_mrk_misc15) Group experienced marked branch redirect
+event:0X0BC2 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP188 : (Group 188 pm_ep_mrk_misc15) Marked instruction finished
+event:0X0BC3 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP188 : (Group 188 pm_ep_mrk_misc15) Marked group completed
diff --git a/events/ppc64/power5++/unit_masks b/events/ppc64/power5++/unit_masks
new file mode 100644
index 0000000..2d57319
--- /dev/null
+++ b/events/ppc64/power5++/unit_masks
@@ -0,0 +1,4 @@
+# ppc64 Power5++ possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/power5+/event_mappings b/events/ppc64/power5+/event_mappings
new file mode 100644
index 0000000..735d2d1
--- /dev/null
+++ b/events/ppc64/power5+/event_mappings
@@ -0,0 +1,1232 @@
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+
+#Group 0 with random sampling
+event:0X002 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X010 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+event:0X011 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+event:0X012 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+event:0X013 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+event:0X014 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+event:0X015 mmcr0:0X00000000 mmcr1:0X000000000A12121E mmcra:0X00000000
+
+#Group 2 pm_completion, Completion and cycle counts
+event:0X020 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X021 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X022 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X023 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X024 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X025 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+
+#Group 3 pm_group_dispatch, Group dispatch events
+event:0X030 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X031 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X032 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X033 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X034 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X035 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+
+#Group 4 pm_clb1, CLB fullness
+event:0X040 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X041 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X042 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X043 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X044 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X045 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+
+#Group 5 pm_clb2, CLB fullness
+event:0X050 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X051 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X052 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X053 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X054 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X055 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+
+#Group 6 pm_gct_empty, GCT empty reasons
+event:0X060 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X061 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X062 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X063 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X064 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X065 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+
+#Group 7 pm_gct_usage, GCT Usage
+event:0X070 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X071 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X072 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X073 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X074 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X075 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+
+#Group 8 pm_lsu1, LSU LRQ and LMQ events
+event:0X080 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+event:0X081 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+event:0X082 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+event:0X083 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+event:0X084 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+event:0X085 mmcr0:0X00000000 mmcr1:0X020F000FCECCCCCA mmcra:0X00000000
+
+#Group 9 pm_lsu2, LSU SRQ events
+event:0X090 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+event:0X091 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+event:0X092 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+event:0X093 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+event:0X094 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+event:0X095 mmcr0:0X00000000 mmcr1:0X400E000ECECCCA86 mmcra:0X00000000
+
+#Group 10 pm_lsu3, LSU SRQ and LMQ events
+event:0X0A0 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+event:0X0A1 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+event:0X0A2 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+event:0X0A3 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+event:0X0A4 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+event:0X0A5 mmcr0:0X00000000 mmcr1:0X030F0004EA102A2A mmcra:0X00000000
+
+#Group 11 pm_lsu4, LSU SRQ and LMQ events
+event:0X0B0 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+event:0X0B1 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+event:0X0B2 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+event:0X0B3 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+event:0X0B4 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+event:0X0B5 mmcr0:0X00000000 mmcr1:0X40030000EEA62A2A mmcra:0X00000000
+
+#Group 12 pm_prefetch1, Prefetch stream allocation
+event:0X0C0 mmcr0:0X00000000 mmcr1:0X8432000D3AC884CE mmcra:0X00000000
+event:0X0C1 mmcr0:0X00000000 mmcr1:0X8432000D3AC884CE mmcra:0X00000000
+event:0X0C2 mmcr0:0X00000000 mmcr1:0X8432000D3AC884CE mmcra:0X00000000
+event:0X0C3 mmcr0:0X00000000 mmcr1:0X8432000D3AC884CE mmcra:0X00000000
+event:0X0C4 mmcr0:0X00000000 mmcr1:0X8432000D3AC884CE mmcra:0X00000000
+event:0X0C5 mmcr0:0X00000000 mmcr1:0X8432000D3AC884CE mmcra:0X00000000
+
+#Group 13 pm_prefetch2, Prefetch events
+event:0X0D0 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0D1 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0D2 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0D3 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0D4 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0D5 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+
+#Group 14 pm_prefetch3, L2 prefetch and misc events
+event:0X0E0 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+event:0X0E1 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+event:0X0E2 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+event:0X0E3 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+event:0X0E4 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+event:0X0E5 mmcr0:0X00000000 mmcr1:0X047C000482108602 mmcra:0X00000001
+
+#Group 15 pm_prefetch4, Misc prefetch and reject events
+event:0X0F0 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+event:0X0F1 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+event:0X0F2 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+event:0X0F3 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+event:0X0F4 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+event:0X0F5 mmcr0:0X00000000 mmcr1:0X0CF200028088CC86 mmcra:0X00000000
+
+#Group 16 pm_lsu_reject1, LSU reject events
+event:0X100 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+event:0X101 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+event:0X102 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+event:0X103 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+event:0X104 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+event:0X105 mmcr0:0X00000000 mmcr1:0XC8E000022010C610 mmcra:0X00000001
+
+#Group 17 pm_lsu_reject2, LSU rejects due to reload CDF or tag update collision
+event:0X110 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+event:0X111 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+event:0X112 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+event:0X113 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+event:0X114 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+event:0X115 mmcr0:0X00000000 mmcr1:0X88C00001848C02CE mmcra:0X00000001
+
+#Group 18 pm_lsu_reject3, LSU rejects due to ERAT, held instuctions
+event:0X120 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+event:0X121 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+event:0X122 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+event:0X123 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+event:0X124 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+event:0X125 mmcr0:0X00000000 mmcr1:0X48C00003868EC0C8 mmcra:0X00000000
+
+#Group 19 pm_lsu_reject4, LSU0/1 reject LMQ full
+event:0X130 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+event:0X131 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+event:0X132 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+event:0X133 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+event:0X134 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+event:0X135 mmcr0:0X00000000 mmcr1:0X88C00001828A02C8 mmcra:0X00000001
+
+#Group 20 pm_lsu_reject5, LSU misc reject and flush events
+event:0X140 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+event:0X141 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+event:0X142 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+event:0X143 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+event:0X144 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+event:0X145 mmcr0:0X00000000 mmcr1:0X48C0000010208A8E mmcra:0X00000000
+
+#Group 21 pm_flush1, Misc flush events
+event:0X150 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X151 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X152 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X153 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X154 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X155 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+
+#Group 22 pm_flush2, Flushes due to scoreboard and sync
+event:0X160 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X161 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X162 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X163 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X164 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X165 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+
+#Group 23 pm_lsu_flush_srq_lrq, LSU flush by SRQ and LRQ events
+event:0X170 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X171 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X172 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X173 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X174 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X175 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+
+#Group 24 pm_lsu_flush_lrq, LSU0/1 flush due to LRQ
+event:0X180 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X181 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X182 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X183 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X184 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X185 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+
+#Group 25 pm_lsu_flush_srq, LSU0/1 flush due to SRQ
+event:0X190 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X191 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X192 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X193 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X194 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X195 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+
+#Group 26 pm_lsu_flush_unaligned, LSU flush due to unaligned data
+event:0X1A0 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X1A1 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X1A2 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X1A3 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X1A4 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X1A5 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+
+#Group 27 pm_lsu_flush_uld, LSU0/1 flush due to unaligned load
+event:0X1B0 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1B1 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1B2 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1B3 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1B4 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1B5 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+
+#Group 28 pm_lsu_flush_ust, LSU0/1 flush due to unaligned store
+event:0X1C0 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1C1 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1C2 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1C3 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1C4 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1C5 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+
+#Group 29 pm_lsu_flush_full, LSU flush due to LRQ/SRQ full
+event:0X1D0 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1D1 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1D2 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1D3 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1D4 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1D5 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+
+#Group 30 pm_lsu_stall1, LSU Stalls
+event:0X1E0 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1E1 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1E2 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1E3 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1E4 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1E5 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+
+#Group 31 pm_lsu_stall2, LSU Stalls
+event:0X1F0 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1F1 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1F2 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1F3 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1F4 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1F5 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+
+#Group 32 pm_fxu_stall, FXU Stalls
+event:0X200 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X201 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X202 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X203 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X204 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X205 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+
+#Group 33 pm_fpu_stall, FPU Stalls
+event:0X210 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X211 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X212 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X213 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X214 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X215 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+
+#Group 34 pm_queue_full, BRQ LRQ LMQ queue full
+event:0X220 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X221 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X222 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X223 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X224 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X225 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+
+#Group 35 pm_issueq_full, FPU FX full
+event:0X230 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X231 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X232 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X233 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X234 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X235 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+
+#Group 36 pm_mapper_full1, CR CTR GPR mapper full
+event:0X240 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X241 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X242 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X243 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X244 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X245 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+
+#Group 37 pm_mapper_full2, FPR XER mapper full
+event:0X250 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X251 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X252 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X253 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X254 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X255 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+
+#Group 38 pm_misc_load, Non-cachable loads and stcx events
+event:0X260 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X261 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X262 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X263 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X264 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X265 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+
+#Group 39 pm_ic_demand, ICache demand from BR redirect
+event:0X270 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+event:0X271 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+event:0X272 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+event:0X273 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+event:0X274 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+event:0X275 mmcr0:0X00000000 mmcr1:0X800C000FC2CAC0C2 mmcra:0X00000000
+
+#Group 40 pm_ic_pref, ICache prefetch
+event:0X280 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+event:0X281 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+event:0X282 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+event:0X283 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+event:0X284 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+event:0X285 mmcr0:0X00000000 mmcr1:0X8000000DCECC8E1A mmcra:0X00000000
+
+#Group 41 pm_ic_miss, ICache misses
+event:0X290 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X291 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X292 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X293 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X294 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X295 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+
+#Group 42 pm_branch_miss, Branch mispredict, TLB and SLB misses
+event:0X2A0 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X2A1 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X2A2 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X2A3 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X2A4 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X2A5 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+
+#Group 43 pm_branch1, Branch operations
+event:0X2B0 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+event:0X2B1 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+event:0X2B2 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+event:0X2B3 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+event:0X2B4 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+event:0X2B5 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0E0E mmcra:0X00000000
+
+#Group 44 pm_branch2, Branch operations
+event:0X2C0 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2C1 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2C2 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2C3 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2C4 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2C5 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+
+#Group 45 pm_L1_tlbmiss, L1 load and TLB misses
+event:0X2D0 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2D1 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2D2 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2D3 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2D4 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2D5 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+
+#Group 46 pm_L1_DERAT_miss, L1 store and DERAT misses
+event:0X2E0 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+event:0X2E1 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+event:0X2E2 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+event:0X2E3 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+event:0X2E4 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+event:0X2E5 mmcr0:0X00000000 mmcr1:0X00B300080E202086 mmcra:0X00000000
+
+#Group 47 pm_L1_slbmiss, L1 load and SLB misses
+event:0X2F0 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2F1 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2F2 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2F3 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2F4 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2F5 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+
+#Group 48 pm_dtlbref, Data TLB references
+event:0X300 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+event:0X301 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+event:0X302 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+event:0X303 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+event:0X304 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+event:0X305 mmcr0:0X00000000 mmcr1:0X000C000F0C0C0C0C mmcra:0X00000000
+
+#Group 49 pm_dtlbmiss, Data TLB misses
+event:0X310 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+event:0X311 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+event:0X312 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+event:0X313 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+event:0X314 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+event:0X315 mmcr0:0X00000000 mmcr1:0X000C000F1A1A1A1A mmcra:0X00000000
+
+#Group 50 pm_dtlb, Data TLB references and misses
+event:0X320 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+event:0X321 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+event:0X322 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+event:0X323 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+event:0X324 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+event:0X325 mmcr0:0X00000000 mmcr1:0X008C0008C8881E1E mmcra:0X00000000
+
+#Group 51 pm_L1_refmiss, L1 load references and misses and store references and misses
+event:0X330 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+event:0X331 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+event:0X332 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+event:0X333 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+event:0X334 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+event:0X335 mmcr0:0X00000000 mmcr1:0X0030000050501086 mmcra:0X00000000
+
+#Group 52 pm_dsource1, L3 cache and memory data access
+event:0X340 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+event:0X341 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+event:0X342 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+event:0X343 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+event:0X344 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+event:0X345 mmcr0:0X00000000 mmcr1:0X4003000C1C0E8E02 mmcra:0X00000001
+
+#Group 53 pm_dsource2, L3 cache and memory data access
+event:0X350 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+event:0X351 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+event:0X352 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+event:0X353 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+event:0X354 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+event:0X355 mmcr0:0X00000000 mmcr1:0X0003000F1C0E360E mmcra:0X00000000
+
+#Group 54 pm_dsource_L2, L2 cache data access
+event:0X360 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+event:0X361 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+event:0X362 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+event:0X363 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+event:0X364 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+event:0X365 mmcr0:0X00000000 mmcr1:0X0003000F2E2E2E2E mmcra:0X00000000
+
+#Group 55 pm_dsource_L3, L3 cache data access
+event:0X370 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+event:0X371 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+event:0X372 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+event:0X373 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+event:0X374 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+event:0X375 mmcr0:0X00000000 mmcr1:0X0003000F3C3C3C3C mmcra:0X00000000
+
+#Group 56 pm_isource1, Instruction source information
+event:0X380 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+event:0X381 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+event:0X382 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+event:0X383 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+event:0X384 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+event:0X385 mmcr0:0X00000000 mmcr1:0X8000000F1A1A1A0C mmcra:0X00000000
+
+#Group 57 pm_isource2, Instruction source information
+event:0X390 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+event:0X391 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+event:0X392 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+event:0X393 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+event:0X394 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+event:0X395 mmcr0:0X00000000 mmcr1:0X8000000D0C0C021A mmcra:0X00000001
+
+#Group 58 pm_isource_L2, L2 instruction source information
+event:0X3A0 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+event:0X3A1 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+event:0X3A2 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+event:0X3A3 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+event:0X3A4 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+event:0X3A5 mmcr0:0X00000000 mmcr1:0X8000000F2C2C2C2C mmcra:0X00000000
+
+#Group 59 pm_isource_L3, L3 instruction source information
+event:0X3B0 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+event:0X3B1 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+event:0X3B2 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+event:0X3B3 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+event:0X3B4 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+event:0X3B5 mmcr0:0X00000000 mmcr1:0X8000000F3A3A3A3A mmcra:0X00000000
+
+#Group 60 pm_pteg_source1, PTEG source information
+event:0X3C0 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+event:0X3C1 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+event:0X3C2 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+event:0X3C3 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+event:0X3C4 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+event:0X3C5 mmcr0:0X00000000 mmcr1:0X0002000F2E2E2E2E mmcra:0X00000000
+
+#Group 61 pm_pteg_source2, PTEG source information
+event:0X3D0 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+event:0X3D1 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+event:0X3D2 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+event:0X3D3 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+event:0X3D4 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+event:0X3D5 mmcr0:0X00000000 mmcr1:0X0002000F3C3C3C3C mmcra:0X00000000
+
+#Group 62 pm_pteg_source3, PTEG source information
+event:0X3E0 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+event:0X3E1 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+event:0X3E2 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+event:0X3E3 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+event:0X3E4 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+event:0X3E5 mmcr0:0X00000000 mmcr1:0X0002000F0E0E360E mmcra:0X00000000
+
+#Group 63 pm_pteg_source4, L3 PTEG and group disptach events
+event:0X3F0 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+event:0X3F1 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+event:0X3F2 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+event:0X3F3 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+event:0X3F4 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+event:0X3F5 mmcr0:0X00000000 mmcr1:0X003200081C04048E mmcra:0X00000000
+
+#Group 64 pm_L2SA_ld, L2 slice A load events
+event:0X400 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X401 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X402 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X403 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X404 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X405 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+
+#Group 65 pm_L2SA_st, L2 slice A store events
+event:0X410 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X411 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X412 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X413 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X414 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X415 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+
+#Group 66 pm_L2SA_st2, L2 slice A store events
+event:0X420 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X421 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X422 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X423 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X424 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X425 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+
+#Group 67 pm_L2SB_ld, L2 slice B load events
+event:0X430 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X431 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X432 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X433 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X434 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X435 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+
+#Group 68 pm_L2SB_st, L2 slice B store events
+event:0X440 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+event:0X441 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+event:0X442 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+event:0X443 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+event:0X444 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+event:0X445 mmcr0:0X00000000 mmcr1:0X3055800582C482C2 mmcra:0X00000000
+
+#Group 69 pm_L2SB_st2, L2 slice B store events
+event:0X450 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X451 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X452 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X453 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X454 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X455 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+
+#Group 70 pm_L2SB_ld, L2 slice C load events
+event:0X460 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X461 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X462 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X463 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X464 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X465 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+
+#Group 71 pm_L2SB_st, L2 slice C store events
+event:0X470 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+event:0X471 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+event:0X472 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+event:0X473 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+event:0X474 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+event:0X475 mmcr0:0X00000000 mmcr1:0X3055800584C284C4 mmcra:0X00000000
+
+#Group 72 pm_L2SB_st2, L2 slice C store events
+event:0X480 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X481 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X482 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X483 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X484 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X485 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+
+#Group 73 pm_L3SA_trans, L3 slice A state transistions
+event:0X490 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X491 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X492 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X493 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X494 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X495 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+
+#Group 74 pm_L3SB_trans, L3 slice B state transistions
+event:0X4A0 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X4A1 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X4A2 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X4A3 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X4A4 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X4A5 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+
+#Group 75 pm_L3SC_trans, L3 slice C state transistions
+event:0X4B0 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X4B1 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X4B2 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X4B3 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X4B4 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X4B5 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+
+#Group 76 pm_L2SA_trans, L2 slice A state transistions
+event:0X4C0 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X4C1 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X4C2 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X4C3 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X4C4 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X4C5 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+
+#Group 77 pm_L2SB_trans, L2 slice B state transistions
+event:0X4D0 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4D1 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4D2 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4D3 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4D4 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4D5 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+
+#Group 78 pm_L2SC_trans, L2 slice C state transistions
+event:0X4E0 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4E1 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4E2 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4E3 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4E4 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4E5 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+
+#Group 79 pm_L3SAB_retry, L3 slice A/B snoop retry and all CI/CO busy
+event:0X4F0 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4F1 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4F2 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4F3 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4F4 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4F5 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+
+#Group 80 pm_L3SAB_hit, L3 slice A/B hit and reference
+event:0X500 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X501 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X502 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X503 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X504 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X505 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+
+#Group 81 pm_L3SC_retry_hit, L3 slice C hit & snoop retry
+event:0X510 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X511 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X512 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X513 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X514 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X515 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+
+#Group 82 pm_fpu1, Floating Point events
+event:0X520 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X521 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X522 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X523 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X524 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X525 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+
+#Group 83 pm_fpu2, Floating Point events
+event:0X530 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X531 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X532 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X533 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X534 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X535 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+
+#Group 84 pm_fpu3, Floating point events
+event:0X540 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X541 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X542 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X543 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X544 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X545 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+
+#Group 85 pm_fpu4, Floating point events
+event:0X550 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X551 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X552 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X553 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X554 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X555 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+
+#Group 86 pm_fpu5, Floating point events by unit
+event:0X560 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X561 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X562 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X563 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X564 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X565 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+
+#Group 87 pm_fpu6, Floating point events by unit
+event:0X570 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X571 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X572 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X573 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X574 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X575 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+
+#Group 88 pm_fpu7, Floating point events by unit
+event:0X580 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X581 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X582 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X583 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X584 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X585 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+
+#Group 89 pm_fpu8, Floating point events by unit
+event:0X590 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X591 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X592 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X593 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X594 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X595 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+
+#Group 90 pm_fpu9, Floating point events by unit
+event:0X5A0 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X5A1 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X5A2 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X5A3 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X5A4 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X5A5 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+
+#Group 91 pm_fpu10, Floating point events by unit
+event:0X5B0 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X5B1 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X5B2 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X5B3 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X5B4 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X5B5 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+
+#Group 92 pm_fpu11, Floating point events by unit
+event:0X5C0 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X5C1 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X5C2 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X5C3 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X5C4 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X5C5 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+
+#Group 93 pm_fpu12, Floating point events by unit
+event:0X5D0 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5D1 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5D2 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5D3 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5D4 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5D5 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+
+#Group 94 pm_fxu1, Fixed Point events
+event:0X5E0 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5E1 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5E2 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5E3 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5E4 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5E5 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+
+#Group 95 pm_fxu2, Fixed Point events
+event:0X5F0 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5F1 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5F2 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5F3 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5F4 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5F5 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+
+#Group 96 pm_fxu3, Fixed Point events
+event:0X600 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X601 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X602 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X603 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X604 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X605 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+
+#Group 97 pm_smt_priorities1, Thread priority events
+event:0X610 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X611 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X612 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X613 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X614 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X615 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+
+#Group 98 pm_smt_priorities2, Thread priority events
+event:0X620 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X621 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X622 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X623 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X624 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X625 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+
+#Group 99 pm_smt_priorities3, Thread priority events
+event:0X630 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X631 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X632 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X633 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X634 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X635 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+
+#Group 100 pm_smt_priorities4, Thread priority events
+event:0X640 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X641 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X642 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X643 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X644 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X645 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+
+#Group 101 pm_smt_both, Thread common events
+event:0X650 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X651 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X652 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X653 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X654 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X655 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+
+#Group 102 pm_smt_selection, Thread selection
+event:0X660 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X661 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X662 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X663 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X664 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X665 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+
+#Group 103 pm_smt_selectover1, Thread selection overide
+event:0X670 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X671 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X672 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X673 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X674 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X675 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+
+#Group 104 pm_smt_selectover2, Thread selection overide
+event:0X680 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X681 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X682 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X683 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X684 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X685 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+
+#Group 105 pm_fabric1, Fabric events
+event:0X690 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X691 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X692 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X693 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X694 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X695 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+
+#Group 106 pm_fabric2, Fabric data movement
+event:0X6A0 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X6A1 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X6A2 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X6A3 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X6A4 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X6A5 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+
+#Group 107 pm_fabric3, Fabric data movement
+event:0X6B0 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X6B1 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X6B2 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X6B3 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X6B4 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X6B5 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+
+#Group 108 pm_fabric4, Fabric data movement
+event:0X6C0 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X6C1 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X6C2 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X6C3 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X6C4 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X6C5 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+
+#Group 109 pm_snoop1, Snoop retry
+event:0X6D0 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6D1 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6D2 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6D3 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6D4 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6D5 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+
+#Group 110 pm_snoop2, Snoop read retry
+event:0X6E0 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6E1 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6E2 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6E3 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6E4 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6E5 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+
+#Group 111 pm_snoop3, Snoop write retry
+event:0X6F0 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6F1 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6F2 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6F3 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6F4 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6F5 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+
+#Group 112 pm_snoop4, Snoop partial write retry
+event:0X700 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X701 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X702 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X703 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X704 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X705 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+
+#Group 113 pm_mem_rq, Memory read queue dispatch
+event:0X710 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X711 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X712 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X713 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X714 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X715 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+
+#Group 114 pm_mem_read, Memory read complete and cancel
+event:0X720 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X721 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X722 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X723 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X724 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X725 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+
+#Group 115 pm_mem_wq, Memory write queue dispatch
+event:0X730 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X731 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X732 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X733 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X734 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X735 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+
+#Group 116 pm_mem_pwq, Memory partial write queue
+event:0X740 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X741 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X742 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X743 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X744 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X745 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+
+#Group 117 pm_threshold, Thresholding
+event:0X750 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X751 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X752 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X753 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X754 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X755 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+
+#Group 118 pm_mrk_grp1, Marked group events
+event:0X760 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X761 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X762 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X763 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X764 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X765 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+
+#Group 119 pm_mrk_grp2, Marked group events
+event:0X770 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+event:0X771 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+event:0X772 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+event:0X773 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+event:0X774 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+event:0X775 mmcr0:0X00000000 mmcr1:0X410300032A0AC822 mmcra:0X00000001
+
+#Group 120 pm_mrk_dsource1, Marked data from
+event:0X780 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+event:0X781 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+event:0X782 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+event:0X783 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+event:0X784 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+event:0X785 mmcr0:0X00000000 mmcr1:0X010B000F0E404444 mmcra:0X00000001
+
+#Group 121 pm_mrk_dsource2, Marked data from
+event:0X790 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+event:0X791 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+event:0X792 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+event:0X793 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+event:0X794 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+event:0X795 mmcr0:0X00000000 mmcr1:0X010B000C2E440210 mmcra:0X00000001
+
+#Group 122 pm_mrk_dsource3, Marked data from
+event:0X7A0 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+event:0X7A1 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+event:0X7A2 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+event:0X7A3 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+event:0X7A4 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+event:0X7A5 mmcr0:0X00000000 mmcr1:0X010B000F1C484C4C mmcra:0X00000001
+
+#Group 123 pm_mrk_dsource4, Marked data from
+event:0X7B0 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+event:0X7B1 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+event:0X7B2 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+event:0X7B3 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+event:0X7B4 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+event:0X7B5 mmcr0:0X00000000 mmcr1:0X010B000F42462E42 mmcra:0X00000001
+
+#Group 124 pm_mrk_dsource5, Marked data from
+event:0X7C0 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+event:0X7C1 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+event:0X7C2 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+event:0X7C3 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+event:0X7C4 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+event:0X7C5 mmcr0:0X00000000 mmcr1:0X010B000F3C4C4040 mmcra:0X00000001
+
+#Group 125 pm_mrk_dsource6, Marked data from
+event:0X7D0 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+event:0X7D1 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+event:0X7D2 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+event:0X7D3 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+event:0X7D4 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+event:0X7D5 mmcr0:0X00000000 mmcr1:0X010B000D46460246 mmcra:0X00000001
+
+#Group 126 pm_mrk_dsource7, Marked data from
+event:0X7E0 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+event:0X7E1 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+event:0X7E2 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+event:0X7E3 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+event:0X7E4 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+event:0X7E5 mmcr0:0X00000000 mmcr1:0X010B000F4E4E3C4E mmcra:0X00000001
+
+#Group 127 pm_mrk_dtlbref, Marked data TLB references
+event:0X7F0 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+event:0X7F1 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+event:0X7F2 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+event:0X7F3 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+event:0X7F4 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+event:0X7F5 mmcr0:0X00000000 mmcr1:0X020C000F0C0C0C0C mmcra:0X00000001
+
+#Group 128 pm_mrk_dtlbmiss, Marked data TLB misses
+event:0X800 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+event:0X801 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+event:0X802 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+event:0X803 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+event:0X804 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+event:0X805 mmcr0:0X00000000 mmcr1:0X020C000F1A1A1A1A mmcra:0X00000001
+
+#Group 129 pm_mrk_dtlb_dslb, Marked data TLB references and misses and marked data SLB misses
+event:0X810 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+event:0X811 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+event:0X812 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+event:0X813 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+event:0X814 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+event:0X815 mmcr0:0X00000000 mmcr1:0X063C0008C8AC8E1E mmcra:0X00000001
+
+#Group 130 pm_mrk_lbref, Marked TLB and SLB references
+event:0X820 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+event:0X821 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+event:0X822 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+event:0X823 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+event:0X824 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+event:0X825 mmcr0:0X00000000 mmcr1:0X063C000A0C020C8E mmcra:0X00000001
+
+#Group 131 pm_mrk_lsmiss, Marked load and store miss
+event:0X830 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X831 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X832 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X833 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X834 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X835 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+
+#Group 132 pm_mrk_ulsflush, Mark unaligned load and store flushes
+event:0X840 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X841 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X842 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X843 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X844 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X845 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+
+#Group 133 pm_mrk_misc, Misc marked instructions
+event:0X850 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X851 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X852 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X853 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X854 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X855 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+
+#Group 134 pm_lsref_L1, Load/Store operations and L1 activity
+event:0X860 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+event:0X861 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+event:0X862 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+event:0X863 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+event:0X864 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+event:0X865 mmcr0:0X00000000 mmcr1:0X8033000C0E1A2020 mmcra:0X00000000
+
+#Group 135 pm_lsref_L2L3, Load/Store operations and L2,L3 activity
+event:0X870 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+event:0X871 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+event:0X872 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+event:0X873 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+event:0X874 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+event:0X875 mmcr0:0X00000000 mmcr1:0X0033000C1C0E2020 mmcra:0X00000000
+
+#Group 136 pm_lsref_tlbmiss, Load/Store operations and TLB misses
+event:0X880 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X881 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X882 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X883 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X884 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X885 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+
+#Group 137 pm_Dmiss, Data cache misses
+event:0X890 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+event:0X891 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+event:0X892 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+event:0X893 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+event:0X894 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+event:0X895 mmcr0:0X00000000 mmcr1:0X0033000C1C0E1086 mmcra:0X00000000
+
+#Group 138 pm_prefetchX, Prefetch events
+event:0X8A0 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X8A1 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X8A2 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X8A3 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X8A4 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X8A5 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+
+#Group 139 pm_branchX, Branch operations
+event:0X8B0 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+event:0X8B1 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+event:0X8B2 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+event:0X8B3 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+event:0X8B4 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+event:0X8B5 mmcr0:0X00000000 mmcr1:0X8000000F0E0E0EC8 mmcra:0X00000000
+
+#Group 140 pm_fpuX1, Floating point events by unit
+event:0X8C0 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X8C1 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X8C2 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X8C3 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X8C4 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X8C5 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+
+#Group 141 pm_fpuX2, Floating point events by unit
+event:0X8D0 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X8D1 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X8D2 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X8D3 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X8D4 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X8D5 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+
+#Group 142 pm_fpuX3, Floating point events by unit
+event:0X8E0 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X8E1 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X8E2 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X8E3 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X8E4 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X8E5 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+
+#Group 143 pm_fpuX4, Floating point and L1 events
+event:0X8F0 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8F1 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8F2 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8F3 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8F4 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8F5 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+
+#Group 144 pm_fpuX5, Floating point events
+event:0X900 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X901 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X902 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X903 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X904 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X905 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+
+#Group 145 pm_fpuX6, Floating point events
+event:0X910 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X911 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X912 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X913 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X914 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X915 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+
+#Group 146 pm_fpuX7, Floating point events
+event:0X920 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+event:0X921 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+event:0X922 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+event:0X923 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+event:0X924 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+event:0X925 mmcr0:0X00000000 mmcr1:0X0000000220105010 mmcra:0X00000000
+
+#Group 147 pm_hpmcount1, HPM group for set 1
+event:0X930 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+event:0X931 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+event:0X932 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+event:0X933 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+event:0X934 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+event:0X935 mmcr0:0X00000000 mmcr1:0X000000001E281E10 mmcra:0X00000000
+
+#Group 148 pm_hpmcount2, HPM group for set 2
+event:0X940 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X941 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X942 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X943 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X944 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X945 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+
+#Group 149 pm_hpmcount3, HPM group for set 3
+event:0X950 mmcr0:0X00000000 mmcr1:0X403000041EC01086 mmcra:0X00000000
+event:0X951 mmcr0:0X00000000 mmcr1:0X403000041EC01086 mmcra:0X00000000
+event:0X952 mmcr0:0X00000000 mmcr1:0X403000041EC01086 mmcra:0X00000000
+event:0X953 mmcr0:0X00000000 mmcr1:0X403000041EC01086 mmcra:0X00000000
+event:0X954 mmcr0:0X00000000 mmcr1:0X403000041EC01086 mmcra:0X00000000
+event:0X955 mmcr0:0X00000000 mmcr1:0X403000041EC01086 mmcra:0X00000000
+
+#Group 150 pm_hpmcount4, HPM group for set 7
+event:0X960 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X961 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X962 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X963 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X964 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X965 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+
+#Group 151 pm_flop, Floating point operations
+event:0X970 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+event:0X971 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+event:0X972 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+event:0X973 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+event:0X974 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+event:0X975 mmcr0:0X00000000 mmcr1:0X0000000010105050 mmcra:0X00000000
+
+#Group 152 pm_eprof1, Group for use with eprof
+event:0X980 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X981 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X982 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X983 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X984 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X985 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+
+#Group 153 pm_eprof2, Group for use with eprof
+event:0X990 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+event:0X991 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+event:0X992 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+event:0X993 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+event:0X994 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
+event:0X995 mmcr0:0X00000000 mmcr1:0X0030000012501220 mmcra:0X00000000
diff --git a/events/ppc64/power5+/events b/events/ppc64/power5+/events
new file mode 100644
index 0000000..0624c39
--- /dev/null
+++ b/events/ppc64/power5+/events
@@ -0,0 +1,1242 @@
+#PPC64 Power5+ events
+#
+# Within each group the event names must be unique. Each event in a group is
+# assigned to a unique counter. The groups are from the groups defined in the
+# Performance Monitor Unit user guide for this processor.
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles using continuous sampling
+
+#Group 0 with random sampling
+event:0X002 counters:2 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
+
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
+event:0X011 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Instructions completed
+event:0X012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
+event:0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
+event:0X014 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP1 : (Group 1 pm_utilization) Run instructions completed
+event:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
+
+#Group 2 pm_completion, Completion and cycle counts
+event:0X020 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP2 : (Group 2 pm_completion) One or more PPC instruction completed
+event:0X021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empty
+event:0X022 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP2 : (Group 2 pm_completion) Group completed
+event:0X023 counters:3 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_completion) Processor cycles
+event:0X024 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP2 : (Group 2 pm_completion) Run instructions completed
+event:0X025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_completion) Run cycles
+
+#Group 3 pm_group_dispatch, Group dispatch events
+event:0X030 counters:0 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP3 : (Group 3 pm_group_dispatch) Group dispatch valid
+event:0X031 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP3 : (Group 3 pm_group_dispatch) Group dispatch rejected
+event:0X032 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP3 : (Group 3 pm_group_dispatch) Cycles group dispatch blocked by scoreboard
+event:0X033 counters:3 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_group_dispatch) Instructions dispatched
+event:0X034 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP3 : (Group 3 pm_group_dispatch) Run instructions completed
+event:0X035 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP3 : (Group 3 pm_group_dispatch) Run cycles
+
+#Group 4 pm_clb1, CLB fullness
+event:0X040 counters:0 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles no instructions in CLB
+event:0X041 counters:1 um:zero minimum:1000 name:PM_2INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles 2 instructions in CLB
+event:0X042 counters:2 um:zero minimum:1000 name:PM_CLB_EMPTY_CYC_GRP4 : (Group 4 pm_clb1) Cycles CLB empty
+event:0X043 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_CYC_GRP4 : (Group 4 pm_clb1) Marked load latency from L3.5 modified
+event:0X044 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP4 : (Group 4 pm_clb1) Run instructions completed
+event:0X045 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP4 : (Group 4 pm_clb1) Run cycles
+
+#Group 5 pm_clb2, CLB fullness
+event:0X050 counters:0 um:zero minimum:1000 name:PM_5INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 5 instructions in CLB
+event:0X051 counters:1 um:zero minimum:1000 name:PM_6INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 6 instructions in CLB
+event:0X052 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP5 : (Group 5 pm_clb2) Marked instruction valid in SRQ
+event:0X053 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP5 : (Group 5 pm_clb2) IOPS instructions completed
+event:0X054 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP5 : (Group 5 pm_clb2) Run instructions completed
+event:0X055 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP5 : (Group 5 pm_clb2) Run cycles
+
+#Group 6 pm_gct_empty, GCT empty reasons
+event:0X060 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP6 : (Group 6 pm_gct_empty) Cycles no GCT slot allocated
+event:0X061 counters:1 um:zero minimum:1000 name:PM_GCT_NOSLOT_IC_MISS_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by I cache miss
+event:0X062 counters:2 um:zero minimum:1000 name:PM_GCT_NOSLOT_SRQ_FULL_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by SRQ full
+event:0X063 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by branch mispredict
+event:0X064 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP6 : (Group 6 pm_gct_empty) Run instructions completed
+event:0X065 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP6 : (Group 6 pm_gct_empty) Run cycles
+
+#Group 7 pm_gct_usage, GCT Usage
+event:0X070 counters:0 um:zero minimum:1000 name:PM_GCT_USAGE_00to59_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT less than 60% full
+event:0X071 counters:1 um:zero minimum:1000 name:PM_GCT_USAGE_60to79_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT 60-79% full
+event:0X072 counters:2 um:zero minimum:1000 name:PM_GCT_USAGE_80to99_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT 80-99% full
+event:0X073 counters:3 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT full
+event:0X074 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP7 : (Group 7 pm_gct_usage) Run instructions completed
+event:0X075 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP7 : (Group 7 pm_gct_usage) Run cycles
+
+#Group 8 pm_lsu1, LSU LRQ and LMQ events
+event:0X080 counters:0 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP8 : (Group 8 pm_lsu1) LRQ slot 0 allocated
+event:0X081 counters:1 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP8 : (Group 8 pm_lsu1) LRQ slot 0 valid
+event:0X082 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP8 : (Group 8 pm_lsu1) LMQ slot 0 allocated
+event:0X083 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP8 : (Group 8 pm_lsu1) LMQ slot 0 valid
+event:0X084 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP8 : (Group 8 pm_lsu1) Run instructions completed
+event:0X085 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP8 : (Group 8 pm_lsu1) Run cycles
+
+#Group 9 pm_lsu2, LSU SRQ events
+event:0X090 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP9 : (Group 9 pm_lsu2) SRQ slot 0 allocated
+event:0X091 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP9 : (Group 9 pm_lsu2) SRQ slot 0 valid
+event:0X092 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP9 : (Group 9 pm_lsu2) SRQ sync duration
+event:0X093 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP9 : (Group 9 pm_lsu2) Cycles SRQ full
+event:0X094 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP9 : (Group 9 pm_lsu2) Run instructions completed
+event:0X095 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP9 : (Group 9 pm_lsu2) Run cycles
+
+#Group 10 pm_lsu3, LSU SRQ and LMQ events
+event:0X0A0 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_LHR_MERGE_GRP10 : (Group 10 pm_lsu3) LMQ LHR merges
+event:0X0A1 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_STFWD_GRP10 : (Group 10 pm_lsu3) SRQ store forwarded
+event:0X0A2 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP10 : (Group 10 pm_lsu3) Cycles LMQ and SRQ empty
+event:0X0A3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP10 : (Group 10 pm_lsu3) Cycles SRQ empty
+event:0X0A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP10 : (Group 10 pm_lsu3) Run instructions completed
+event:0X0A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP10 : (Group 10 pm_lsu3) Run cycles
+
+#Group 11 pm_lsu4, LSU SRQ and LMQ events
+event:0X0B0 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP11 : (Group 11 pm_lsu4) Cycles LMQ full
+event:0X0B1 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP11 : (Group 11 pm_lsu4) Cycles SRQ full
+event:0X0B2 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP11 : (Group 11 pm_lsu4) Cycles LMQ and SRQ empty
+event:0X0B3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP11 : (Group 11 pm_lsu4) Cycles SRQ empty
+event:0X0B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP11 : (Group 11 pm_lsu4) Run instructions completed
+event:0X0B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP11 : (Group 11 pm_lsu4) Run cycles
+
+#Group 12 pm_prefetch1, Prefetch stream allocation
+event:0X0C0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP12 : (Group 12 pm_prefetch1) Instructions fetched missed L2
+event:0X0C1 counters:1 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP12 : (Group 12 pm_prefetch1) Cycles at least 1 instruction fetched
+event:0X0C2 counters:2 um:zero minimum:1000 name:PM_DC_OUT_OF_STREAMS_GRP12 : (Group 12 pm_prefetch1) LSU Data prefetch out of streams
+event:0X0C3 counters:3 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_GRP12 : (Group 12 pm_prefetch1) D cache new prefetch stream allocated
+event:0X0C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP12 : (Group 12 pm_prefetch1) Run instructions completed
+event:0X0C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP12 : (Group 12 pm_prefetch1) Run cycles
+
+#Group 13 pm_prefetch2, Prefetch events
+event:0X0D0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP13 : (Group 13 pm_prefetch2) IOPS instructions completed
+event:0X0D1 counters:1 um:zero minimum:1000 name:PM_CLB_FULL_CYC_GRP13 : (Group 13 pm_prefetch2) Cycles CLB full
+event:0X0D2 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP13 : (Group 13 pm_prefetch2) L1 cache data prefetches
+event:0X0D3 counters:3 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP13 : (Group 13 pm_prefetch2) Instruction prefetched installed in prefetch
+event:0X0D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP13 : (Group 13 pm_prefetch2) Run instructions completed
+event:0X0D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP13 : (Group 13 pm_prefetch2) Run cycles
+
+#Group 14 pm_prefetch3, L2 prefetch and misc events
+event:0X0E0 counters:0 um:zero minimum:1000 name:PM_1INST_CLB_CYC_GRP14 : (Group 14 pm_prefetch3) Cycles 1 instruction in CLB
+event:0X0E1 counters:1 um:zero minimum:1000 name:PM_LSU_BUSY_REJECT_GRP14 : (Group 14 pm_prefetch3) LSU busy due to reject
+event:0X0E2 counters:2 um:zero minimum:1000 name:PM_L2_PREF_GRP14 : (Group 14 pm_prefetch3) L2 cache prefetches
+event:0X0E3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP14 : (Group 14 pm_prefetch3) IOPS instructions completed
+event:0X0E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP14 : (Group 14 pm_prefetch3) Run instructions completed
+event:0X0E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP14 : (Group 14 pm_prefetch3) Run cycles
+
+#Group 15 pm_prefetch4, Misc prefetch and reject events
+event:0X0F0 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_SRQ_LHS_GRP15 : (Group 15 pm_prefetch4) LSU0 SRQ rejects
+event:0X0F1 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_SRQ_LHS_GRP15 : (Group 15 pm_prefetch4) LSU1 SRQ rejects
+event:0X0F2 counters:2 um:zero minimum:1000 name:PM_DC_PREF_DST_GRP15 : (Group 15 pm_prefetch4) DST (Data Stream Touch) stream start
+event:0X0F3 counters:3 um:zero minimum:1000 name:PM_L2_PREF_GRP15 : (Group 15 pm_prefetch4) L2 cache prefetches
+event:0X0F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP15 : (Group 15 pm_prefetch4) Run instructions completed
+event:0X0F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP15 : (Group 15 pm_prefetch4) Run cycles
+
+#Group 16 pm_lsu_reject1, LSU reject events
+event:0X100 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_ERAT_MISS_GRP16 : (Group 16 pm_lsu_reject1) LSU reject due to ERAT miss
+event:0X101 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_LMQ_FULL_GRP16 : (Group 16 pm_lsu_reject1) LSU reject due to LMQ full or missed data coming
+event:0X102 counters:2 um:zero minimum:1000 name:PM_FLUSH_IMBAL_GRP16 : (Group 16 pm_lsu_reject1) Flush caused by thread GCT imbalance
+event:0X103 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_GRP16 : (Group 16 pm_lsu_reject1) Marked SRQ flushes
+event:0X104 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP16 : (Group 16 pm_lsu_reject1) Run instructions completed
+event:0X105 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP16 : (Group 16 pm_lsu_reject1) Run cycles
+
+#Group 17 pm_lsu_reject2, LSU rejects due to reload CDF or tag update collision
+event:0X110 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_RELOAD_CDF_GRP17 : (Group 17 pm_lsu_reject2) LSU0 reject due to reload CDF or tag update collision
+event:0X111 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_RELOAD_CDF_GRP17 : (Group 17 pm_lsu_reject2) LSU1 reject due to reload CDF or tag update collision
+event:0X112 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP17 : (Group 17 pm_lsu_reject2) IOPS instructions completed
+event:0X113 counters:3 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP17 : (Group 17 pm_lsu_reject2) Cycles writing to instruction L1
+event:0X114 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP17 : (Group 17 pm_lsu_reject2) Run instructions completed
+event:0X115 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP17 : (Group 17 pm_lsu_reject2) Run cycles
+
+#Group 18 pm_lsu_reject3, LSU rejects due to ERAT, held instuctions
+event:0X120 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_ERAT_MISS_GRP18 : (Group 18 pm_lsu_reject3) LSU0 reject due to ERAT miss
+event:0X121 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_ERAT_MISS_GRP18 : (Group 18 pm_lsu_reject3) LSU1 reject due to ERAT miss
+event:0X122 counters:2 um:zero minimum:1000 name:PM_LWSYNC_HELD_GRP18 : (Group 18 pm_lsu_reject3) LWSYNC held at dispatch
+event:0X123 counters:3 um:zero minimum:1000 name:PM_TLBIE_HELD_GRP18 : (Group 18 pm_lsu_reject3) TLBIE held at dispatch
+event:0X124 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP18 : (Group 18 pm_lsu_reject3) Run instructions completed
+event:0X125 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP18 : (Group 18 pm_lsu_reject3) Run cycles
+
+#Group 19 pm_lsu_reject4, LSU0/1 reject LMQ full
+event:0X130 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_LMQ_FULL_GRP19 : (Group 19 pm_lsu_reject4) LSU0 reject due to LMQ full or missed data coming
+event:0X131 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_LMQ_FULL_GRP19 : (Group 19 pm_lsu_reject4) LSU1 reject due to LMQ full or missed data coming
+event:0X132 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP19 : (Group 19 pm_lsu_reject4) IOPS instructions completed
+event:0X133 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP19 : (Group 19 pm_lsu_reject4) Branches issued
+event:0X134 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP19 : (Group 19 pm_lsu_reject4) Run instructions completed
+event:0X135 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP19 : (Group 19 pm_lsu_reject4) Run cycles
+
+#Group 20 pm_lsu_reject5, LSU misc reject and flush events
+event:0X140 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_SRQ_LHS_GRP20 : (Group 20 pm_lsu_reject5) LSU SRQ rejects
+event:0X141 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_RELOAD_CDF_GRP20 : (Group 20 pm_lsu_reject5) LSU reject due to reload CDF or tag update collision
+event:0X142 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP20 : (Group 20 pm_lsu_reject5) Flush initiated by LSU
+event:0X143 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP20 : (Group 20 pm_lsu_reject5) Flushes
+event:0X144 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP20 : (Group 20 pm_lsu_reject5) Run instructions completed
+event:0X145 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP20 : (Group 20 pm_lsu_reject5) Run cycles
+
+#Group 21 pm_flush1, Misc flush events
+event:0X150 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP21 : (Group 21 pm_flush1) IOPS instructions completed
+event:0X151 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP21 : (Group 21 pm_flush1) SRQ unaligned store flushes
+event:0X152 counters:2 um:zero minimum:1000 name:PM_FLUSH_IMBAL_GRP21 : (Group 21 pm_flush1) Flush caused by thread GCT imbalance
+event:0X153 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP21 : (Group 21 pm_flush1) L1 D cache entries invalidated from L2
+event:0X154 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP21 : (Group 21 pm_flush1) Run instructions completed
+event:0X155 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP21 : (Group 21 pm_flush1) Run cycles
+
+#Group 22 pm_flush2, Flushes due to scoreboard and sync
+event:0X160 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP22 : (Group 22 pm_flush2) Instruction TLB misses
+event:0X161 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP22 : (Group 22 pm_flush2) IOPS instructions completed
+event:0X162 counters:2 um:zero minimum:1000 name:PM_FLUSH_SB_GRP22 : (Group 22 pm_flush2) Flush caused by scoreboard operation
+event:0X163 counters:3 um:zero minimum:1000 name:PM_FLUSH_SYNC_GRP22 : (Group 22 pm_flush2) Flush caused by sync
+event:0X164 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP22 : (Group 22 pm_flush2) Run instructions completed
+event:0X165 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP22 : (Group 22 pm_flush2) Run cycles
+
+#Group 23 pm_lsu_flush_srq_lrq, LSU flush by SRQ and LRQ events
+event:0X170 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) SRQ flushes
+event:0X171 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) LRQ flushes
+event:0X172 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) IOPS instructions completed
+event:0X173 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) Flush initiated by LSU
+event:0X174 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) Run instructions completed
+event:0X175 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP23 : (Group 23 pm_lsu_flush_srq_lrq) Run cycles
+
+#Group 24 pm_lsu_flush_lrq, LSU0/1 flush due to LRQ
+event:0X180 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP24 : (Group 24 pm_lsu_flush_lrq) LSU0 LRQ flushes
+event:0X181 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP24 : (Group 24 pm_lsu_flush_lrq) LSU1 LRQ flushes
+event:0X182 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP24 : (Group 24 pm_lsu_flush_lrq) Flush initiated by LSU
+event:0X183 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP24 : (Group 24 pm_lsu_flush_lrq) IOPS instructions completed
+event:0X184 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP24 : (Group 24 pm_lsu_flush_lrq) Run instructions completed
+event:0X185 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP24 : (Group 24 pm_lsu_flush_lrq) Run cycles
+
+#Group 25 pm_lsu_flush_srq, LSU0/1 flush due to SRQ
+event:0X190 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP25 : (Group 25 pm_lsu_flush_srq) LSU0 SRQ flushes
+event:0X191 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP25 : (Group 25 pm_lsu_flush_srq) LSU1 SRQ flushes
+event:0X192 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP25 : (Group 25 pm_lsu_flush_srq) IOPS instructions completed
+event:0X193 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP25 : (Group 25 pm_lsu_flush_srq) Flush initiated by LSU
+event:0X194 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP25 : (Group 25 pm_lsu_flush_srq) Run instructions completed
+event:0X195 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP25 : (Group 25 pm_lsu_flush_srq) Run cycles
+
+#Group 26 pm_lsu_flush_unaligned, LSU flush due to unaligned data
+event:0X1A0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP26 : (Group 26 pm_lsu_flush_unaligned) LRQ unaligned load flushes
+event:0X1A1 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP26 : (Group 26 pm_lsu_flush_unaligned) SRQ unaligned store flushes
+event:0X1A2 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP26 : (Group 26 pm_lsu_flush_unaligned) Branches issued
+event:0X1A3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP26 : (Group 26 pm_lsu_flush_unaligned) IOPS instructions completed
+event:0X1A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP26 : (Group 26 pm_lsu_flush_unaligned) Run instructions completed
+event:0X1A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP26 : (Group 26 pm_lsu_flush_unaligned) Run cycles
+
+#Group 27 pm_lsu_flush_uld, LSU0/1 flush due to unaligned load
+event:0X1B0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP27 : (Group 27 pm_lsu_flush_uld) LSU0 unaligned load flushes
+event:0X1B1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP27 : (Group 27 pm_lsu_flush_uld) LSU1 unaligned load flushes
+event:0X1B2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP27 : (Group 27 pm_lsu_flush_uld) Flush initiated by LSU
+event:0X1B3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP27 : (Group 27 pm_lsu_flush_uld) IOPS instructions completed
+event:0X1B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP27 : (Group 27 pm_lsu_flush_uld) Run instructions completed
+event:0X1B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP27 : (Group 27 pm_lsu_flush_uld) Run cycles
+
+#Group 28 pm_lsu_flush_ust, LSU0/1 flush due to unaligned store
+event:0X1C0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP28 : (Group 28 pm_lsu_flush_ust) LSU0 unaligned store flushes
+event:0X1C1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP28 : (Group 28 pm_lsu_flush_ust) LSU1 unaligned store flushes
+event:0X1C2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP28 : (Group 28 pm_lsu_flush_ust) IOPS instructions completed
+event:0X1C3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP28 : (Group 28 pm_lsu_flush_ust) Flush initiated by LSU
+event:0X1C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP28 : (Group 28 pm_lsu_flush_ust) Run instructions completed
+event:0X1C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP28 : (Group 28 pm_lsu_flush_ust) Run cycles
+
+#Group 29 pm_lsu_flush_full, LSU flush due to LRQ/SRQ full
+event:0X1D0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_FULL_GRP29 : (Group 29 pm_lsu_flush_full) Flush caused by LRQ full
+event:0X1D1 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP29 : (Group 29 pm_lsu_flush_full) IOPS instructions completed
+event:0X1D2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP29 : (Group 29 pm_lsu_flush_full) Marked LRQ flushes
+event:0X1D3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_FULL_GRP29 : (Group 29 pm_lsu_flush_full) Flush caused by SRQ full
+event:0X1D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP29 : (Group 29 pm_lsu_flush_full) Run instructions completed
+event:0X1D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP29 : (Group 29 pm_lsu_flush_full) Run cycles
+
+#Group 30 pm_lsu_stall1, LSU Stalls
+event:0X1E0 counters:0 um:zero minimum:1000 name:PM_GRP_MRK_GRP30 : (Group 30 pm_lsu_stall1) Group marked in IDU
+event:0X1E1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP30 : (Group 30 pm_lsu_stall1) Completion stall caused by LSU instruction
+event:0X1E2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP30 : (Group 30 pm_lsu_stall1) IOPS instructions completed
+event:0X1E3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP30 : (Group 30 pm_lsu_stall1) Completion stall caused by reject
+event:0X1E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP30 : (Group 30 pm_lsu_stall1) Run instructions completed
+event:0X1E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP30 : (Group 30 pm_lsu_stall1) Run cycles
+
+#Group 31 pm_lsu_stall2, LSU Stalls
+event:0X1F0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP31 : (Group 31 pm_lsu_stall2) IOPS instructions completed
+event:0X1F1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP31 : (Group 31 pm_lsu_stall2) Completion stall caused by D cache miss
+event:0X1F2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP31 : (Group 31 pm_lsu_stall2) Processor cycles
+event:0X1F3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP31 : (Group 31 pm_lsu_stall2) Completion stall caused by ERAT miss
+event:0X1F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP31 : (Group 31 pm_lsu_stall2) Run instructions completed
+event:0X1F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP31 : (Group 31 pm_lsu_stall2) Run cycles
+
+#Group 32 pm_fxu_stall, FXU Stalls
+event:0X200 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_BR_REDIR_NONSPEC_GRP32 : (Group 32 pm_fxu_stall) Group experienced non-speculative I cache miss or branch redirect
+event:0X201 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP32 : (Group 32 pm_fxu_stall) Completion stall caused by FXU instruction
+event:0X202 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP32 : (Group 32 pm_fxu_stall) IOPS instructions completed
+event:0X203 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP32 : (Group 32 pm_fxu_stall) Completion stall caused by DIV instruction
+event:0X204 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP32 : (Group 32 pm_fxu_stall) Run instructions completed
+event:0X205 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP32 : (Group 32 pm_fxu_stall) Run cycles
+
+#Group 33 pm_fpu_stall, FPU Stalls
+event:0X210 counters:0 um:zero minimum:1000 name:PM_FPU_FULL_CYC_GRP33 : (Group 33 pm_fpu_stall) Cycles FPU issue queue full
+event:0X211 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FDIV_GRP33 : (Group 33 pm_fpu_stall) Completion stall caused by FDIV or FQRT instruction
+event:0X212 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP33 : (Group 33 pm_fpu_stall) IOPS instructions completed
+event:0X213 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_FPU_GRP33 : (Group 33 pm_fpu_stall) Completion stall caused by FPU instruction
+event:0X214 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP33 : (Group 33 pm_fpu_stall) Run instructions completed
+event:0X215 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP33 : (Group 33 pm_fpu_stall) Run cycles
+
+#Group 34 pm_queue_full, BRQ LRQ LMQ queue full
+event:0X220 counters:0 um:zero minimum:1000 name:PM_LARX_LSU0_GRP34 : (Group 34 pm_queue_full) Larx executed on LSU0
+event:0X221 counters:1 um:zero minimum:1000 name:PM_BRQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles branch queue full
+event:0X222 counters:2 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles LRQ full
+event:0X223 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP34 : (Group 34 pm_queue_full) Cycles LMQ full
+event:0X224 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP34 : (Group 34 pm_queue_full) Run instructions completed
+event:0X225 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP34 : (Group 34 pm_queue_full) Run cycles
+
+#Group 35 pm_issueq_full, FPU FX full
+event:0X230 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FPU0 issue queue full
+event:0X231 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FPU1 issue queue full
+event:0X232 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FXU0/LS0 queue full
+event:0X233 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP35 : (Group 35 pm_issueq_full) Cycles FXU1/LS1 queue full
+event:0X234 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP35 : (Group 35 pm_issueq_full) Run instructions completed
+event:0X235 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP35 : (Group 35 pm_issueq_full) Run cycles
+
+#Group 36 pm_mapper_full1, CR CTR GPR mapper full
+event:0X240 counters:0 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles CR logical operation mapper full
+event:0X241 counters:1 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles LR/CTR mapper full
+event:0X242 counters:2 um:zero minimum:1000 name:PM_GPR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles GPR mapper full
+event:0X243 counters:3 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP36 : (Group 36 pm_mapper_full1) Cycles CR issue queue full
+event:0X244 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP36 : (Group 36 pm_mapper_full1) Run instructions completed
+event:0X245 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP36 : (Group 36 pm_mapper_full1) Run cycles
+
+#Group 37 pm_mapper_full2, FPR XER mapper full
+event:0X250 counters:0 um:zero minimum:1000 name:PM_FPR_MAP_FULL_CYC_GRP37 : (Group 37 pm_mapper_full2) Cycles FPR mapper full
+event:0X251 counters:1 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP37 : (Group 37 pm_mapper_full2) Cycles XER mapper full
+event:0X252 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2MISS_GRP37 : (Group 37 pm_mapper_full2) Marked data loaded missed L2
+event:0X253 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP37 : (Group 37 pm_mapper_full2) IOPS instructions completed
+event:0X254 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP37 : (Group 37 pm_mapper_full2) Run instructions completed
+event:0X255 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP37 : (Group 37 pm_mapper_full2) Run cycles
+
+#Group 38 pm_misc_load, Non-cachable loads and stcx events
+event:0X260 counters:0 um:zero minimum:1000 name:PM_STCX_FAIL_GRP38 : (Group 38 pm_misc_load) STCX failed
+event:0X261 counters:1 um:zero minimum:1000 name:PM_STCX_PASS_GRP38 : (Group 38 pm_misc_load) Stcx passes
+event:0X262 counters:2 um:zero minimum:1000 name:PM_LSU0_NCLD_GRP38 : (Group 38 pm_misc_load) LSU0 non-cacheable loads
+event:0X263 counters:3 um:zero minimum:1000 name:PM_LSU1_NCLD_GRP38 : (Group 38 pm_misc_load) LSU1 non-cacheable loads
+event:0X264 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP38 : (Group 38 pm_misc_load) Run instructions completed
+event:0X265 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP38 : (Group 38 pm_misc_load) Run cycles
+
+#Group 39 pm_ic_demand, ICache demand from BR redirect
+event:0X270 counters:0 um:zero minimum:1000 name:PM_LSU0_BUSY_REJECT_GRP39 : (Group 39 pm_ic_demand) LSU0 busy due to reject
+event:0X271 counters:1 um:zero minimum:1000 name:PM_LSU1_BUSY_REJECT_GRP39 : (Group 39 pm_ic_demand) LSU1 busy due to reject
+event:0X272 counters:2 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BHT_REDIRECT_GRP39 : (Group 39 pm_ic_demand) L2 I cache demand request due to BHT redirect
+event:0X273 counters:3 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_REDIRECT_GRP39 : (Group 39 pm_ic_demand) L2 I cache demand request due to branch redirect
+event:0X274 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP39 : (Group 39 pm_ic_demand) Run instructions completed
+event:0X275 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP39 : (Group 39 pm_ic_demand) Run cycles
+
+#Group 40 pm_ic_pref, ICache prefetch
+event:0X280 counters:0 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP40 : (Group 40 pm_ic_pref) Translation written to ierat
+event:0X281 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP40 : (Group 40 pm_ic_pref) Instruction prefetch requests
+event:0X282 counters:2 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP40 : (Group 40 pm_ic_pref) Instruction prefetched installed in prefetch
+event:0X283 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP40 : (Group 40 pm_ic_pref) No instructions fetched
+event:0X284 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP40 : (Group 40 pm_ic_pref) Run instructions completed
+event:0X285 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP40 : (Group 40 pm_ic_pref) Run cycles
+
+#Group 41 pm_ic_miss, ICache misses
+event:0X290 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_NONSPEC_GRP41 : (Group 41 pm_ic_miss) Group experienced non-speculative I cache miss
+event:0X291 counters:1 um:zero minimum:1000 name:PM_GRP_IC_MISS_GRP41 : (Group 41 pm_ic_miss) Group experienced I cache miss
+event:0X292 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP41 : (Group 41 pm_ic_miss) L1 reload data source valid
+event:0X293 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP41 : (Group 41 pm_ic_miss) IOPS instructions completed
+event:0X294 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP41 : (Group 41 pm_ic_miss) Run instructions completed
+event:0X295 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP41 : (Group 41 pm_ic_miss) Run cycles
+
+#Group 42 pm_branch_miss, Branch mispredict, TLB and SLB misses
+event:0X2A0 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP42 : (Group 42 pm_branch_miss) TLB misses
+event:0X2A1 counters:1 um:zero minimum:1000 name:PM_SLB_MISS_GRP42 : (Group 42 pm_branch_miss) SLB misses
+event:0X2A2 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP42 : (Group 42 pm_branch_miss) Branch mispredictions due to CR bit setting
+event:0X2A3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP42 : (Group 42 pm_branch_miss) Branch mispredictions due to target address
+event:0X2A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP42 : (Group 42 pm_branch_miss) Run instructions completed
+event:0X2A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP42 : (Group 42 pm_branch_miss) Run cycles
+
+#Group 43 pm_branch1, Branch operations
+event:0X2B0 counters:0 um:zero minimum:1000 name:PM_BR_UNCOND_GRP43 : (Group 43 pm_branch1) Unconditional branch
+event:0X2B1 counters:1 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, target prediction
+event:0X2B2 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, CR prediction
+event:0X2B3 counters:3 um:zero minimum:1000 name:PM_BR_PRED_CR_TA_GRP43 : (Group 43 pm_branch1) A conditional branch was predicted, CR and target prediction
+event:0X2B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP43 : (Group 43 pm_branch1) Run instructions completed
+event:0X2B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP43 : (Group 43 pm_branch1) Run cycles
+
+#Group 44 pm_branch2, Branch operations
+event:0X2C0 counters:0 um:zero minimum:1000 name:PM_GRP_BR_REDIR_NONSPEC_GRP44 : (Group 44 pm_branch2) Group experienced non-speculative branch redirect
+event:0X2C1 counters:1 um:zero minimum:1000 name:PM_GRP_BR_REDIR_GRP44 : (Group 44 pm_branch2) Group experienced branch redirect
+event:0X2C2 counters:2 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP44 : (Group 44 pm_branch2) Flush caused by branch mispredict
+event:0X2C3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP44 : (Group 44 pm_branch2) IOPS instructions completed
+event:0X2C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP44 : (Group 44 pm_branch2) Run instructions completed
+event:0X2C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP44 : (Group 44 pm_branch2) Run cycles
+
+#Group 45 pm_L1_tlbmiss, L1 load and TLB misses
+event:0X2D0 counters:0 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP45 : (Group 45 pm_L1_tlbmiss) Cycles doing data tablewalks
+event:0X2D1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP45 : (Group 45 pm_L1_tlbmiss) Data TLB misses
+event:0X2D2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP45 : (Group 45 pm_L1_tlbmiss) L1 D cache load misses
+event:0X2D3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP45 : (Group 45 pm_L1_tlbmiss) L1 D cache load references
+event:0X2D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP45 : (Group 45 pm_L1_tlbmiss) Run instructions completed
+event:0X2D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP45 : (Group 45 pm_L1_tlbmiss) Run cycles
+
+#Group 46 pm_L1_DERAT_miss, L1 store and DERAT misses
+event:0X2E0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP46 : (Group 46 pm_L1_DERAT_miss) Data loaded from L2
+event:0X2E1 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP46 : (Group 46 pm_L1_DERAT_miss) DERAT misses
+event:0X2E2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP46 : (Group 46 pm_L1_DERAT_miss) L1 D cache store references
+event:0X2E3 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP46 : (Group 46 pm_L1_DERAT_miss) L1 D cache store misses
+event:0X2E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP46 : (Group 46 pm_L1_DERAT_miss) Run instructions completed
+event:0X2E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP46 : (Group 46 pm_L1_DERAT_miss) Run cycles
+
+#Group 47 pm_L1_slbmiss, L1 load and SLB misses
+event:0X2F0 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_GRP47 : (Group 47 pm_L1_slbmiss) Data SLB misses
+event:0X2F1 counters:1 um:zero minimum:1000 name:PM_ISLB_MISS_GRP47 : (Group 47 pm_L1_slbmiss) Instruction SLB misses
+event:0X2F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP47 : (Group 47 pm_L1_slbmiss) LSU0 L1 D cache load misses
+event:0X2F3 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP47 : (Group 47 pm_L1_slbmiss) LSU1 L1 D cache load misses
+event:0X2F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP47 : (Group 47 pm_L1_slbmiss) Run instructions completed
+event:0X2F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP47 : (Group 47 pm_L1_slbmiss) Run cycles
+
+#Group 48 pm_dtlbref, Data TLB references
+event:0X300 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_4K_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 4K page
+event:0X301 counters:1 um:zero minimum:1000 name:PM_DTLB_REF_64K_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 64K page
+event:0X302 counters:2 um:zero minimum:1000 name:PM_DTLB_REF_16M_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 16M page
+event:0X303 counters:3 um:zero minimum:1000 name:PM_DTLB_REF_16G_GRP48 : (Group 48 pm_dtlbref) Data TLB reference for 16G page
+event:0X304 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP48 : (Group 48 pm_dtlbref) Run instructions completed
+event:0X305 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP48 : (Group 48 pm_dtlbref) Run cycles
+
+#Group 49 pm_dtlbmiss, Data TLB misses
+event:0X310 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_4K_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 4K page
+event:0X311 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_64K_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 64K page
+event:0X312 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_16M_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 16M page
+event:0X313 counters:3 um:zero minimum:1000 name:PM_DTLB_MISS_16G_GRP49 : (Group 49 pm_dtlbmiss) Data TLB miss for 16G page
+event:0X314 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP49 : (Group 49 pm_dtlbmiss) Run instructions completed
+event:0X315 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP49 : (Group 49 pm_dtlbmiss) Run cycles
+
+#Group 50 pm_dtlb, Data TLB references and misses
+event:0X320 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_GRP50 : (Group 50 pm_dtlb) Data TLB references
+event:0X321 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP50 : (Group 50 pm_dtlb) Data TLB misses
+event:0X322 counters:2 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_dtlb) Processor cycles
+event:0X323 counters:3 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_dtlb) Processor cycles
+event:0X324 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP50 : (Group 50 pm_dtlb) Run instructions completed
+event:0X325 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP50 : (Group 50 pm_dtlb) Run cycles
+
+#Group 51 pm_L1_refmiss, L1 load references and misses and store references and misses
+event:0X330 counters:0 um:zero minimum:1000 name:PM_LD_REF_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache load references
+event:0X331 counters:1 um:zero minimum:1000 name:PM_ST_REF_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache store references
+event:0X332 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache load misses
+event:0X333 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP51 : (Group 51 pm_L1_refmiss) L1 D cache store misses
+event:0X334 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP51 : (Group 51 pm_L1_refmiss) Run instructions completed
+event:0X335 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP51 : (Group 51 pm_L1_refmiss) Run cycles
+
+#Group 52 pm_dsource1, L3 cache and memory data access
+event:0X340 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP52 : (Group 52 pm_dsource1) Data loaded from L3
+event:0X341 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP52 : (Group 52 pm_dsource1) Data loaded from local memory
+event:0X342 counters:2 um:zero minimum:1000 name:PM_FLUSH_GRP52 : (Group 52 pm_dsource1) Flushes
+event:0X343 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP52 : (Group 52 pm_dsource1) IOPS instructions completed
+event:0X344 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP52 : (Group 52 pm_dsource1) Run instructions completed
+event:0X345 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP52 : (Group 52 pm_dsource1) Run cycles
+
+#Group 53 pm_dsource2, L3 cache and memory data access
+event:0X350 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP53 : (Group 53 pm_dsource2) Data loaded from L3
+event:0X351 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP53 : (Group 53 pm_dsource2) Data loaded from local memory
+event:0X352 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP53 : (Group 53 pm_dsource2) Data loaded missed L2
+event:0X353 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP53 : (Group 53 pm_dsource2) Data loaded from remote memory
+event:0X354 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP53 : (Group 53 pm_dsource2) Run instructions completed
+event:0X355 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP53 : (Group 53 pm_dsource2) Run cycles
+
+#Group 54 pm_dsource_L2, L2 cache data access
+event:0X360 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.5 shared
+event:0X361 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.5 modified
+event:0X362 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.75 shared
+event:0X363 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP54 : (Group 54 pm_dsource_L2) Data loaded from L2.75 modified
+event:0X364 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP54 : (Group 54 pm_dsource_L2) Run instructions completed
+event:0X365 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP54 : (Group 54 pm_dsource_L2) Run cycles
+
+#Group 55 pm_dsource_L3, L3 cache data access
+event:0X370 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.5 shared
+event:0X371 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.5 modified
+event:0X372 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L375_SHR_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.75 shared
+event:0X373 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L375_MOD_GRP55 : (Group 55 pm_dsource_L3) Data loaded from L3.75 modified
+event:0X374 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP55 : (Group 55 pm_dsource_L3) Run instructions completed
+event:0X375 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP55 : (Group 55 pm_dsource_L3) Run cycles
+
+#Group 56 pm_isource1, Instruction source information
+event:0X380 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP56 : (Group 56 pm_isource1) Instruction fetched from L3
+event:0X381 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP56 : (Group 56 pm_isource1) Instruction fetched from L1
+event:0X382 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP56 : (Group 56 pm_isource1) Instructions fetched from prefetch
+event:0X383 counters:3 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP56 : (Group 56 pm_isource1) Instruction fetched from remote memory
+event:0X384 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP56 : (Group 56 pm_isource1) Run instructions completed
+event:0X385 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP56 : (Group 56 pm_isource1) Run cycles
+
+#Group 57 pm_isource2, Instruction source information
+event:0X390 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP57 : (Group 57 pm_isource2) Instructions fetched from L2
+event:0X391 counters:1 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP57 : (Group 57 pm_isource2) Instruction fetched from local memory
+event:0X392 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP57 : (Group 57 pm_isource2) IOPS instructions completed
+event:0X393 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP57 : (Group 57 pm_isource2) No instructions fetched
+event:0X394 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP57 : (Group 57 pm_isource2) Run instructions completed
+event:0X395 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP57 : (Group 57 pm_isource2) Run cycles
+
+#Group 58 pm_isource_L2, L2 instruction source information
+event:0X3A0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L25_SHR_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.5 shared
+event:0X3A1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.5 modified
+event:0X3A2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L275_SHR_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.75 shared
+event:0X3A3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L275_MOD_GRP58 : (Group 58 pm_isource_L2) Instruction fetched from L2.75 modified
+event:0X3A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP58 : (Group 58 pm_isource_L2) Run instructions completed
+event:0X3A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP58 : (Group 58 pm_isource_L2) Run cycles
+
+#Group 59 pm_isource_L3, L3 instruction source information
+event:0X3B0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP59 : (Group 59 pm_isource_L3) Instructions fetched missed L2
+event:0X3B1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L35_MOD_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.5 modified
+event:0X3B2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L375_SHR_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.75 shared
+event:0X3B3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L375_MOD_GRP59 : (Group 59 pm_isource_L3) Instruction fetched from L3.75 modified
+event:0X3B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP59 : (Group 59 pm_isource_L3) Run instructions completed
+event:0X3B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP59 : (Group 59 pm_isource_L3) Run cycles
+
+#Group 60 pm_pteg_source1, PTEG source information
+event:0X3C0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L25_SHR_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.5 shared
+event:0X3C1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L25_MOD_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.5 modified
+event:0X3C2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L275_SHR_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.75 shared
+event:0X3C3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L275_MOD_GRP60 : (Group 60 pm_pteg_source1) PTEG loaded from L2.75 modified
+event:0X3C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP60 : (Group 60 pm_pteg_source1) Run instructions completed
+event:0X3C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP60 : (Group 60 pm_pteg_source1) Run cycles
+
+#Group 61 pm_pteg_source2, PTEG source information
+event:0X3D0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L35_SHR_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.5 shared
+event:0X3D1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L35_MOD_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.5 modified
+event:0X3D2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L375_SHR_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.75 shared
+event:0X3D3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L375_MOD_GRP61 : (Group 61 pm_pteg_source2) PTEG loaded from L3.75 modified
+event:0X3D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP61 : (Group 61 pm_pteg_source2) Run instructions completed
+event:0X3D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP61 : (Group 61 pm_pteg_source2) Run cycles
+
+#Group 62 pm_pteg_source3, PTEG source information
+event:0X3E0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from L2
+event:0X3E1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from local memory
+event:0X3E2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from L2 miss
+event:0X3E3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP62 : (Group 62 pm_pteg_source3) PTEG loaded from remote memory
+event:0X3E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP62 : (Group 62 pm_pteg_source3) Run instructions completed
+event:0X3E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP62 : (Group 62 pm_pteg_source3) Run cycles
+
+#Group 63 pm_pteg_source4, L3 PTEG and group disptach events
+event:0X3F0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP63 : (Group 63 pm_pteg_source4) PTEG loaded from L3
+event:0X3F1 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_GRP63 : (Group 63 pm_pteg_source4) Group dispatches
+event:0X3F2 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_SUCCESS_GRP63 : (Group 63 pm_pteg_source4) Group dispatch success
+event:0X3F3 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP63 : (Group 63 pm_pteg_source4) L1 D cache entries invalidated from L2
+event:0X3F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP63 : (Group 63 pm_pteg_source4) Run instructions completed
+event:0X3F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP63 : (Group 63 pm_pteg_source4) Run cycles
+
+#Group 64 pm_L2SA_ld, L2 slice A load events
+event:0X400 counters:0 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_GRP64 : (Group 64 pm_L2SA_ld) L2 Slice A RC load dispatch attempt
+event:0X401 counters:1 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_RC_FULL_GRP64 : (Group 64 pm_L2SA_ld) L2 Slice A RC load dispatch attempt failed due to all RC full
+event:0X402 counters:2 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_ADDR_GRP64 : (Group 64 pm_L2SA_ld) L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X403 counters:3 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_OTHER_GRP64 : (Group 64 pm_L2SA_ld) L2 Slice A RC load dispatch attempt failed due to other reasons
+event:0X404 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP64 : (Group 64 pm_L2SA_ld) Run instructions completed
+event:0X405 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP64 : (Group 64 pm_L2SA_ld) Run cycles
+
+#Group 65 pm_L2SA_st, L2 slice A store events
+event:0X410 counters:0 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_GRP65 : (Group 65 pm_L2SA_st) L2 Slice A RC store dispatch attempt
+event:0X411 counters:1 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_RC_FULL_GRP65 : (Group 65 pm_L2SA_st) L2 Slice A RC store dispatch attempt failed due to all RC full
+event:0X412 counters:2 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_ADDR_GRP65 : (Group 65 pm_L2SA_st) L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X413 counters:3 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_OTHER_GRP65 : (Group 65 pm_L2SA_st) L2 Slice A RC store dispatch attempt failed due to other reasons
+event:0X414 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP65 : (Group 65 pm_L2SA_st) Run instructions completed
+event:0X415 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP65 : (Group 65 pm_L2SA_st) Run cycles
+
+#Group 66 pm_L2SA_st2, L2 slice A store events
+event:0X420 counters:0 um:zero minimum:1000 name:PM_L2SA_RC_DISP_FAIL_CO_BUSY_GRP66 : (Group 66 pm_L2SA_st2) L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X421 counters:1 um:zero minimum:1000 name:PM_L2SA_ST_REQ_GRP66 : (Group 66 pm_L2SA_st2) L2 slice A store requests
+event:0X422 counters:2 um:zero minimum:1000 name:PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL_GRP66 : (Group 66 pm_L2SA_st2) L2 Slice A RC dispatch attempt failed due to all CO busy
+event:0X423 counters:3 um:zero minimum:1000 name:PM_L2SA_ST_HIT_GRP66 : (Group 66 pm_L2SA_st2) L2 slice A store hits
+event:0X424 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP66 : (Group 66 pm_L2SA_st2) Run instructions completed
+event:0X425 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP66 : (Group 66 pm_L2SA_st2) Run cycles
+
+#Group 67 pm_L2SB_ld, L2 slice B load events
+event:0X430 counters:0 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_GRP67 : (Group 67 pm_L2SB_ld) L2 Slice B RC load dispatch attempt
+event:0X431 counters:1 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_RC_FULL_GRP67 : (Group 67 pm_L2SB_ld) L2 Slice B RC load dispatch attempt failed due to all RC full
+event:0X432 counters:2 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_ADDR_GRP67 : (Group 67 pm_L2SB_ld) L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X433 counters:3 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_OTHER_GRP67 : (Group 67 pm_L2SB_ld) L2 Slice B RC load dispatch attempt failed due to other reasons
+event:0X434 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP67 : (Group 67 pm_L2SB_ld) Run instructions completed
+event:0X435 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP67 : (Group 67 pm_L2SB_ld) Run cycles
+
+#Group 68 pm_L2SB_st, L2 slice B store events
+event:0X440 counters:0 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_GRP68 : (Group 68 pm_L2SB_st) L2 Slice B RC store dispatch attempt
+event:0X441 counters:1 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_RC_FULL_GRP68 : (Group 68 pm_L2SB_st) L2 Slice B RC store dispatch attempt failed due to all RC full
+event:0X442 counters:2 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_ADDR_GRP68 : (Group 68 pm_L2SB_st) L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X443 counters:3 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_OTHER_GRP68 : (Group 68 pm_L2SB_st) L2 Slice B RC store dispatch attempt failed due to other reasons
+event:0X444 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP68 : (Group 68 pm_L2SB_st) Run instructions completed
+event:0X445 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP68 : (Group 68 pm_L2SB_st) Run cycles
+
+#Group 69 pm_L2SB_st2, L2 slice B store events
+event:0X450 counters:0 um:zero minimum:1000 name:PM_L2SB_RC_DISP_FAIL_CO_BUSY_GRP69 : (Group 69 pm_L2SB_st2) L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X451 counters:1 um:zero minimum:1000 name:PM_L2SB_ST_REQ_GRP69 : (Group 69 pm_L2SB_st2) L2 slice B store requests
+event:0X452 counters:2 um:zero minimum:1000 name:PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL_GRP69 : (Group 69 pm_L2SB_st2) L2 Slice B RC dispatch attempt failed due to all CO busy
+event:0X453 counters:3 um:zero minimum:1000 name:PM_L2SB_ST_HIT_GRP69 : (Group 69 pm_L2SB_st2) L2 slice B store hits
+event:0X454 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP69 : (Group 69 pm_L2SB_st2) Run instructions completed
+event:0X455 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP69 : (Group 69 pm_L2SB_st2) Run cycles
+
+#Group 70 pm_L2SB_ld, L2 slice C load events
+event:0X460 counters:0 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_GRP70 : (Group 70 pm_L2SB_ld) L2 Slice C RC load dispatch attempt
+event:0X461 counters:1 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_RC_FULL_GRP70 : (Group 70 pm_L2SB_ld) L2 Slice C RC load dispatch attempt failed due to all RC full
+event:0X462 counters:2 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_ADDR_GRP70 : (Group 70 pm_L2SB_ld) L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X463 counters:3 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_OTHER_GRP70 : (Group 70 pm_L2SB_ld) L2 Slice C RC load dispatch attempt failed due to other reasons
+event:0X464 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP70 : (Group 70 pm_L2SB_ld) Run instructions completed
+event:0X465 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP70 : (Group 70 pm_L2SB_ld) Run cycles
+
+#Group 71 pm_L2SB_st, L2 slice C store events
+event:0X470 counters:0 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_GRP71 : (Group 71 pm_L2SB_st) L2 Slice C RC store dispatch attempt
+event:0X471 counters:1 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_RC_FULL_GRP71 : (Group 71 pm_L2SB_st) L2 Slice C RC store dispatch attempt failed due to all RC full
+event:0X472 counters:2 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_ADDR_GRP71 : (Group 71 pm_L2SB_st) L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X473 counters:3 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_OTHER_GRP71 : (Group 71 pm_L2SB_st) L2 Slice C RC store dispatch attempt failed due to other reasons
+event:0X474 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP71 : (Group 71 pm_L2SB_st) Run instructions completed
+event:0X475 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP71 : (Group 71 pm_L2SB_st) Run cycles
+
+#Group 72 pm_L2SB_st2, L2 slice C store events
+event:0X480 counters:0 um:zero minimum:1000 name:PM_L2SC_RC_DISP_FAIL_CO_BUSY_GRP72 : (Group 72 pm_L2SB_st2) L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X481 counters:1 um:zero minimum:1000 name:PM_L2SC_ST_REQ_GRP72 : (Group 72 pm_L2SB_st2) L2 slice C store requests
+event:0X482 counters:2 um:zero minimum:1000 name:PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL_GRP72 : (Group 72 pm_L2SB_st2) L2 Slice C RC dispatch attempt failed due to all CO busy
+event:0X483 counters:3 um:zero minimum:1000 name:PM_L2SC_ST_HIT_GRP72 : (Group 72 pm_L2SB_st2) L2 slice C store hits
+event:0X484 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP72 : (Group 72 pm_L2SB_st2) Run instructions completed
+event:0X485 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP72 : (Group 72 pm_L2SB_st2) Run cycles
+
+#Group 73 pm_L3SA_trans, L3 slice A state transistions
+event:0X490 counters:0 um:zero minimum:1000 name:PM_L3SA_MOD_TAG_GRP73 : (Group 73 pm_L3SA_trans) L3 slice A transition from modified to TAG
+event:0X491 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP73 : (Group 73 pm_L3SA_trans) IOPS instructions completed
+event:0X492 counters:2 um:zero minimum:1000 name:PM_L3SA_MOD_INV_GRP73 : (Group 73 pm_L3SA_trans) L3 slice A transition from modified to invalid
+event:0X493 counters:3 um:zero minimum:1000 name:PM_L3SA_SHR_INV_GRP73 : (Group 73 pm_L3SA_trans) L3 slice A transition from shared to invalid
+event:0X494 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP73 : (Group 73 pm_L3SA_trans) Run instructions completed
+event:0X495 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP73 : (Group 73 pm_L3SA_trans) Run cycles
+
+#Group 74 pm_L3SB_trans, L3 slice B state transistions
+event:0X4A0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP74 : (Group 74 pm_L3SB_trans) IOPS instructions completed
+event:0X4A1 counters:1 um:zero minimum:1000 name:PM_L3SB_MOD_TAG_GRP74 : (Group 74 pm_L3SB_trans) L3 slice B transition from modified to TAG
+event:0X4A2 counters:2 um:zero minimum:1000 name:PM_L3SB_MOD_INV_GRP74 : (Group 74 pm_L3SB_trans) L3 slice B transition from modified to invalid
+event:0X4A3 counters:3 um:zero minimum:1000 name:PM_L3SB_SHR_INV_GRP74 : (Group 74 pm_L3SB_trans) L3 slice B transition from shared to invalid
+event:0X4A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP74 : (Group 74 pm_L3SB_trans) Run instructions completed
+event:0X4A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP74 : (Group 74 pm_L3SB_trans) Run cycles
+
+#Group 75 pm_L3SC_trans, L3 slice C state transistions
+event:0X4B0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP75 : (Group 75 pm_L3SC_trans) IOPS instructions completed
+event:0X4B1 counters:1 um:zero minimum:1000 name:PM_L3SC_MOD_TAG_GRP75 : (Group 75 pm_L3SC_trans) L3 slice C transition from modified to TAG
+event:0X4B2 counters:2 um:zero minimum:1000 name:PM_L3SC_MOD_INV_GRP75 : (Group 75 pm_L3SC_trans) L3 slice C transition from modified to invalid
+event:0X4B3 counters:3 um:zero minimum:1000 name:PM_L3SC_SHR_INV_GRP75 : (Group 75 pm_L3SC_trans) L3 slice C transition from shared to invalid
+event:0X4B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP75 : (Group 75 pm_L3SC_trans) Run instructions completed
+event:0X4B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP75 : (Group 75 pm_L3SC_trans) Run cycles
+
+#Group 76 pm_L2SA_trans, L2 slice A state transistions
+event:0X4C0 counters:0 um:zero minimum:1000 name:PM_L2SA_MOD_TAG_GRP76 : (Group 76 pm_L2SA_trans) L2 slice A transition from modified to tagged
+event:0X4C1 counters:1 um:zero minimum:1000 name:PM_L2SA_SHR_MOD_GRP76 : (Group 76 pm_L2SA_trans) L2 slice A transition from shared to modified
+event:0X4C2 counters:2 um:zero minimum:1000 name:PM_L2SA_MOD_INV_GRP76 : (Group 76 pm_L2SA_trans) L2 slice A transition from modified to invalid
+event:0X4C3 counters:3 um:zero minimum:1000 name:PM_L2SA_SHR_INV_GRP76 : (Group 76 pm_L2SA_trans) L2 slice A transition from shared to invalid
+event:0X4C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP76 : (Group 76 pm_L2SA_trans) Run instructions completed
+event:0X4C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP76 : (Group 76 pm_L2SA_trans) Run cycles
+
+#Group 77 pm_L2SB_trans, L2 slice B state transistions
+event:0X4D0 counters:0 um:zero minimum:1000 name:PM_L2SB_MOD_TAG_GRP77 : (Group 77 pm_L2SB_trans) L2 slice B transition from modified to tagged
+event:0X4D1 counters:1 um:zero minimum:1000 name:PM_L2SB_SHR_MOD_GRP77 : (Group 77 pm_L2SB_trans) L2 slice B transition from shared to modified
+event:0X4D2 counters:2 um:zero minimum:1000 name:PM_L2SB_MOD_INV_GRP77 : (Group 77 pm_L2SB_trans) L2 slice B transition from modified to invalid
+event:0X4D3 counters:3 um:zero minimum:1000 name:PM_L2SB_SHR_INV_GRP77 : (Group 77 pm_L2SB_trans) L2 slice B transition from shared to invalid
+event:0X4D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP77 : (Group 77 pm_L2SB_trans) Run instructions completed
+event:0X4D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP77 : (Group 77 pm_L2SB_trans) Run cycles
+
+#Group 78 pm_L2SC_trans, L2 slice C state transistions
+event:0X4E0 counters:0 um:zero minimum:1000 name:PM_L2SC_MOD_TAG_GRP78 : (Group 78 pm_L2SC_trans) L2 slice C transition from modified to tagged
+event:0X4E1 counters:1 um:zero minimum:1000 name:PM_L2SC_SHR_MOD_GRP78 : (Group 78 pm_L2SC_trans) L2 slice C transition from shared to modified
+event:0X4E2 counters:2 um:zero minimum:1000 name:PM_L2SC_MOD_INV_GRP78 : (Group 78 pm_L2SC_trans) L2 slice C transition from modified to invalid
+event:0X4E3 counters:3 um:zero minimum:1000 name:PM_L2SC_SHR_INV_GRP78 : (Group 78 pm_L2SC_trans) L2 slice C transition from shared to invalid
+event:0X4E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP78 : (Group 78 pm_L2SC_trans) Run instructions completed
+event:0X4E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP78 : (Group 78 pm_L2SC_trans) Run cycles
+
+#Group 79 pm_L3SAB_retry, L3 slice A/B snoop retry and all CI/CO busy
+event:0X4F0 counters:0 um:zero minimum:1000 name:PM_L3SA_ALL_BUSY_GRP79 : (Group 79 pm_L3SAB_retry) L3 slice A active for every cycle all CI/CO machines busy
+event:0X4F1 counters:1 um:zero minimum:1000 name:PM_L3SB_ALL_BUSY_GRP79 : (Group 79 pm_L3SAB_retry) L3 slice B active for every cycle all CI/CO machines busy
+event:0X4F2 counters:2 um:zero minimum:1000 name:PM_L3SA_SNOOP_RETRY_GRP79 : (Group 79 pm_L3SAB_retry) L3 slice A snoop retries
+event:0X4F3 counters:3 um:zero minimum:1000 name:PM_L3SB_SNOOP_RETRY_GRP79 : (Group 79 pm_L3SAB_retry) L3 slice B snoop retries
+event:0X4F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP79 : (Group 79 pm_L3SAB_retry) Run instructions completed
+event:0X4F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP79 : (Group 79 pm_L3SAB_retry) Run cycles
+
+#Group 80 pm_L3SAB_hit, L3 slice A/B hit and reference
+event:0X500 counters:0 um:zero minimum:1000 name:PM_L3SA_REF_GRP80 : (Group 80 pm_L3SAB_hit) L3 slice A references
+event:0X501 counters:1 um:zero minimum:1000 name:PM_L3SB_REF_GRP80 : (Group 80 pm_L3SAB_hit) L3 slice B references
+event:0X502 counters:2 um:zero minimum:1000 name:PM_L3SA_HIT_GRP80 : (Group 80 pm_L3SAB_hit) L3 slice A hits
+event:0X503 counters:3 um:zero minimum:1000 name:PM_L3SB_HIT_GRP80 : (Group 80 pm_L3SAB_hit) L3 slice B hits
+event:0X504 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP80 : (Group 80 pm_L3SAB_hit) Run instructions completed
+event:0X505 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP80 : (Group 80 pm_L3SAB_hit) Run cycles
+
+#Group 81 pm_L3SC_retry_hit, L3 slice C hit & snoop retry
+event:0X510 counters:0 um:zero minimum:1000 name:PM_L3SC_ALL_BUSY_GRP81 : (Group 81 pm_L3SC_retry_hit) L3 slice C active for every cycle all CI/CO machines busy
+event:0X511 counters:1 um:zero minimum:1000 name:PM_L3SC_REF_GRP81 : (Group 81 pm_L3SC_retry_hit) L3 slice C references
+event:0X512 counters:2 um:zero minimum:1000 name:PM_L3SC_SNOOP_RETRY_GRP81 : (Group 81 pm_L3SC_retry_hit) L3 slice C snoop retries
+event:0X513 counters:3 um:zero minimum:1000 name:PM_L3SC_HIT_GRP81 : (Group 81 pm_L3SC_retry_hit) L3 Slice C hits
+event:0X514 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP81 : (Group 81 pm_L3SC_retry_hit) Run instructions completed
+event:0X515 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP81 : (Group 81 pm_L3SC_retry_hit) Run cycles
+
+#Group 82 pm_fpu1, Floating Point events
+event:0X520 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP82 : (Group 82 pm_fpu1) FPU executed FDIV instruction
+event:0X521 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP82 : (Group 82 pm_fpu1) FPU executed multiply-add instruction
+event:0X522 counters:2 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP82 : (Group 82 pm_fpu1) FPU executing FMOV or FEST instructions
+event:0X523 counters:3 um:zero minimum:1000 name:PM_FPU_FEST_GRP82 : (Group 82 pm_fpu1) FPU executed FEST instruction
+event:0X524 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP82 : (Group 82 pm_fpu1) Run instructions completed
+event:0X525 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP82 : (Group 82 pm_fpu1) Run cycles
+
+#Group 83 pm_fpu2, Floating Point events
+event:0X530 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP83 : (Group 83 pm_fpu2) FPU executed one flop instruction
+event:0X531 counters:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP83 : (Group 83 pm_fpu2) FPU executed FSQRT instruction
+event:0X532 counters:2 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP83 : (Group 83 pm_fpu2) FPU executed FRSP or FCONV instructions
+event:0X533 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP83 : (Group 83 pm_fpu2) FPU produced a result
+event:0X534 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP83 : (Group 83 pm_fpu2) Run instructions completed
+event:0X535 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP83 : (Group 83 pm_fpu2) Run cycles
+
+#Group 84 pm_fpu3, Floating point events
+event:0X540 counters:0 um:zero minimum:1000 name:PM_FPU_DENORM_GRP84 : (Group 84 pm_fpu3) FPU received denormalized data
+event:0X541 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP84 : (Group 84 pm_fpu3) FPU stalled in pipe3
+event:0X542 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP84 : (Group 84 pm_fpu3) FPU0 produced a result
+event:0X543 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP84 : (Group 84 pm_fpu3) FPU1 produced a result
+event:0X544 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP84 : (Group 84 pm_fpu3) Run instructions completed
+event:0X545 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP84 : (Group 84 pm_fpu3) Run cycles
+
+#Group 85 pm_fpu4, Floating point events
+event:0X550 counters:0 um:zero minimum:1000 name:PM_FPU_SINGLE_GRP85 : (Group 85 pm_fpu4) FPU executed single precision instruction
+event:0X551 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP85 : (Group 85 pm_fpu4) FPU executed store instruction
+event:0X552 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP85 : (Group 85 pm_fpu4) IOPS instructions completed
+event:0X553 counters:3 um:zero minimum:1000 name:PM_LSU_LDF_GRP85 : (Group 85 pm_fpu4) LSU executed Floating Point load instruction
+event:0X554 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP85 : (Group 85 pm_fpu4) Run instructions completed
+event:0X555 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP85 : (Group 85 pm_fpu4) Run cycles
+
+#Group 86 pm_fpu5, Floating point events by unit
+event:0X560 counters:0 um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU0 executed FSQRT instruction
+event:0X561 counters:1 um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP86 : (Group 86 pm_fpu5) FPU1 executed FSQRT instruction
+event:0X562 counters:2 um:zero minimum:1000 name:PM_FPU0_FEST_GRP86 : (Group 86 pm_fpu5) FPU0 executed FEST instruction
+event:0X563 counters:3 um:zero minimum:1000 name:PM_FPU1_FEST_GRP86 : (Group 86 pm_fpu5) FPU1 executed FEST instruction
+event:0X564 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP86 : (Group 86 pm_fpu5) Run instructions completed
+event:0X565 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP86 : (Group 86 pm_fpu5) Run cycles
+
+#Group 87 pm_fpu6, Floating point events by unit
+event:0X570 counters:0 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP87 : (Group 87 pm_fpu6) FPU0 received denormalized data
+event:0X571 counters:1 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP87 : (Group 87 pm_fpu6) FPU1 received denormalized data
+event:0X572 counters:2 um:zero minimum:1000 name:PM_FPU0_FMOV_FEST_GRP87 : (Group 87 pm_fpu6) FPU0 executed FMOV or FEST instructions
+event:0X573 counters:3 um:zero minimum:1000 name:PM_FPU1_FMOV_FEST_GRP87 : (Group 87 pm_fpu6) FPU1 executing FMOV or FEST instructions
+event:0X574 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP87 : (Group 87 pm_fpu6) Run instructions completed
+event:0X575 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP87 : (Group 87 pm_fpu6) Run cycles
+
+#Group 88 pm_fpu7, Floating point events by unit
+event:0X580 counters:0 um:zero minimum:1000 name:PM_FPU0_FDIV_GRP88 : (Group 88 pm_fpu7) FPU0 executed FDIV instruction
+event:0X581 counters:1 um:zero minimum:1000 name:PM_FPU1_FDIV_GRP88 : (Group 88 pm_fpu7) FPU1 executed FDIV instruction
+event:0X582 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP88 : (Group 88 pm_fpu7) FPU0 executed FRSP or FCONV instructions
+event:0X583 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP88 : (Group 88 pm_fpu7) FPU1 executed FRSP or FCONV instructions
+event:0X584 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP88 : (Group 88 pm_fpu7) Run instructions completed
+event:0X585 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP88 : (Group 88 pm_fpu7) Run cycles
+
+#Group 89 pm_fpu8, Floating point events by unit
+event:0X590 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP89 : (Group 89 pm_fpu8) FPU0 stalled in pipe3
+event:0X591 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP89 : (Group 89 pm_fpu8) FPU1 stalled in pipe3
+event:0X592 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP89 : (Group 89 pm_fpu8) IOPS instructions completed
+event:0X593 counters:3 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP89 : (Group 89 pm_fpu8) FPU0 executed FPSCR instruction
+event:0X594 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP89 : (Group 89 pm_fpu8) Run instructions completed
+event:0X595 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP89 : (Group 89 pm_fpu8) Run cycles
+
+#Group 90 pm_fpu9, Floating point events by unit
+event:0X5A0 counters:0 um:zero minimum:1000 name:PM_FPU0_SINGLE_GRP90 : (Group 90 pm_fpu9) FPU0 executed single precision instruction
+event:0X5A1 counters:1 um:zero minimum:1000 name:PM_FPU1_SINGLE_GRP90 : (Group 90 pm_fpu9) FPU1 executed single precision instruction
+event:0X5A2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP90 : (Group 90 pm_fpu9) LSU0 executed Floating Point load instruction
+event:0X5A3 counters:3 um:zero minimum:1000 name:PM_LSU1_LDF_GRP90 : (Group 90 pm_fpu9) LSU1 executed Floating Point load instruction
+event:0X5A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP90 : (Group 90 pm_fpu9) Run instructions completed
+event:0X5A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP90 : (Group 90 pm_fpu9) Run cycles
+
+#Group 91 pm_fpu10, Floating point events by unit
+event:0X5B0 counters:0 um:zero minimum:1000 name:PM_FPU0_FMA_GRP91 : (Group 91 pm_fpu10) FPU0 executed multiply-add instruction
+event:0X5B1 counters:1 um:zero minimum:1000 name:PM_FPU1_FMA_GRP91 : (Group 91 pm_fpu10) FPU1 executed multiply-add instruction
+event:0X5B2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP91 : (Group 91 pm_fpu10) IOPS instructions completed
+event:0X5B3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP91 : (Group 91 pm_fpu10) FPU1 executed FRSP or FCONV instructions
+event:0X5B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP91 : (Group 91 pm_fpu10) Run instructions completed
+event:0X5B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP91 : (Group 91 pm_fpu10) Run cycles
+
+#Group 92 pm_fpu11, Floating point events by unit
+event:0X5C0 counters:0 um:zero minimum:1000 name:PM_FPU0_1FLOP_GRP92 : (Group 92 pm_fpu11) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X5C1 counters:1 um:zero minimum:1000 name:PM_FPU1_1FLOP_GRP92 : (Group 92 pm_fpu11) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X5C2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP92 : (Group 92 pm_fpu11) FPU0 produced a result
+event:0X5C3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP92 : (Group 92 pm_fpu11) IOPS instructions completed
+event:0X5C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP92 : (Group 92 pm_fpu11) Run instructions completed
+event:0X5C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP92 : (Group 92 pm_fpu11) Run cycles
+
+#Group 93 pm_fpu12, Floating point events by unit
+event:0X5D0 counters:0 um:zero minimum:1000 name:PM_FPU0_STF_GRP93 : (Group 93 pm_fpu12) FPU0 executed store instruction
+event:0X5D1 counters:1 um:zero minimum:1000 name:PM_FPU1_STF_GRP93 : (Group 93 pm_fpu12) FPU1 executed store instruction
+event:0X5D2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP93 : (Group 93 pm_fpu12) LSU0 executed Floating Point load instruction
+event:0X5D3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP93 : (Group 93 pm_fpu12) IOPS instructions completed
+event:0X5D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP93 : (Group 93 pm_fpu12) Run instructions completed
+event:0X5D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP93 : (Group 93 pm_fpu12) Run cycles
+
+#Group 94 pm_fxu1, Fixed Point events
+event:0X5E0 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP94 : (Group 94 pm_fxu1) FXU idle
+event:0X5E1 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP94 : (Group 94 pm_fxu1) FXU busy
+event:0X5E2 counters:2 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP94 : (Group 94 pm_fxu1) FXU0 busy FXU1 idle
+event:0X5E3 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP94 : (Group 94 pm_fxu1) FXU1 busy FXU0 idle
+event:0X5E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP94 : (Group 94 pm_fxu1) Run instructions completed
+event:0X5E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP94 : (Group 94 pm_fxu1) Run cycles
+
+#Group 95 pm_fxu2, Fixed Point events
+event:0X5F0 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP95 : (Group 95 pm_fxu2) Marked group dispatched
+event:0X5F1 counters:1 um:zero minimum:1000 name:PM_MRK_GRP_BR_REDIR_GRP95 : (Group 95 pm_fxu2) Group experienced marked branch redirect
+event:0X5F2 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP95 : (Group 95 pm_fxu2) FXU produced a result
+event:0X5F3 counters:3 um:zero minimum:1000 name:PM_FXLS_FULL_CYC_GRP95 : (Group 95 pm_fxu2) Cycles FXLS queue is full
+event:0X5F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP95 : (Group 95 pm_fxu2) Run instructions completed
+event:0X5F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP95 : (Group 95 pm_fxu2) Run cycles
+
+#Group 96 pm_fxu3, Fixed Point events
+event:0X600 counters:0 um:zero minimum:1000 name:PM_3INST_CLB_CYC_GRP96 : (Group 96 pm_fxu3) Cycles 3 instructions in CLB
+event:0X601 counters:1 um:zero minimum:1000 name:PM_4INST_CLB_CYC_GRP96 : (Group 96 pm_fxu3) Cycles 4 instructions in CLB
+event:0X602 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP96 : (Group 96 pm_fxu3) FXU0 produced a result
+event:0X603 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP96 : (Group 96 pm_fxu3) FXU1 produced a result
+event:0X604 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP96 : (Group 96 pm_fxu3) Run instructions completed
+event:0X605 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP96 : (Group 96 pm_fxu3) Run cycles
+
+#Group 97 pm_smt_priorities1, Thread priority events
+event:0X610 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_4_CYC_GRP97 : (Group 97 pm_smt_priorities1) Cycles thread running at priority level 4
+event:0X611 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_7_CYC_GRP97 : (Group 97 pm_smt_priorities1) Cycles thread running at priority level 7
+event:0X612 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_0_CYC_GRP97 : (Group 97 pm_smt_priorities1) Cycles no thread priority difference
+event:0X613 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_1or2_CYC_GRP97 : (Group 97 pm_smt_priorities1) Cycles thread priority difference is 1 or 2
+event:0X614 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP97 : (Group 97 pm_smt_priorities1) Run instructions completed
+event:0X615 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP97 : (Group 97 pm_smt_priorities1) Run cycles
+
+#Group 98 pm_smt_priorities2, Thread priority events
+event:0X620 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_3_CYC_GRP98 : (Group 98 pm_smt_priorities2) Cycles thread running at priority level 3
+event:0X621 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_6_CYC_GRP98 : (Group 98 pm_smt_priorities2) Cycles thread running at priority level 6
+event:0X622 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_3or4_CYC_GRP98 : (Group 98 pm_smt_priorities2) Cycles thread priority difference is 3 or 4
+event:0X623 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_5or6_CYC_GRP98 : (Group 98 pm_smt_priorities2) Cycles thread priority difference is 5 or 6
+event:0X624 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP98 : (Group 98 pm_smt_priorities2) Run instructions completed
+event:0X625 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP98 : (Group 98 pm_smt_priorities2) Run cycles
+
+#Group 99 pm_smt_priorities3, Thread priority events
+event:0X630 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_2_CYC_GRP99 : (Group 99 pm_smt_priorities3) Cycles thread running at priority level 2
+event:0X631 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_5_CYC_GRP99 : (Group 99 pm_smt_priorities3) Cycles thread running at priority level 5
+event:0X632 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP99 : (Group 99 pm_smt_priorities3) Cycles thread priority difference is -1 or -2
+event:0X633 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP99 : (Group 99 pm_smt_priorities3) Cycles thread priority difference is -3 or -4
+event:0X634 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP99 : (Group 99 pm_smt_priorities3) Run instructions completed
+event:0X635 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP99 : (Group 99 pm_smt_priorities3) Run cycles
+
+#Group 100 pm_smt_priorities4, Thread priority events
+event:0X640 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_1_CYC_GRP100 : (Group 100 pm_smt_priorities4) Cycles thread running at priority level 1
+event:0X641 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP100 : (Group 100 pm_smt_priorities4) Hypervisor Cycles
+event:0X642 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP100 : (Group 100 pm_smt_priorities4) Cycles thread priority difference is -5 or -6
+event:0X643 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP100 : (Group 100 pm_smt_priorities4) IOPS instructions completed
+event:0X644 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP100 : (Group 100 pm_smt_priorities4) Run instructions completed
+event:0X645 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP100 : (Group 100 pm_smt_priorities4) Run cycles
+
+#Group 101 pm_smt_both, Thread common events
+event:0X650 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP101 : (Group 101 pm_smt_both) One of the threads in run cycles
+event:0X651 counters:1 um:zero minimum:1000 name:PM_THRD_GRP_CMPL_BOTH_CYC_GRP101 : (Group 101 pm_smt_both) Cycles group completed by both threads
+event:0X652 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP101 : (Group 101 pm_smt_both) IOPS instructions completed
+event:0X653 counters:3 um:zero minimum:1000 name:PM_THRD_L2MISS_BOTH_CYC_GRP101 : (Group 101 pm_smt_both) Cycles both threads in L2 misses
+event:0X654 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP101 : (Group 101 pm_smt_both) Run instructions completed
+event:0X655 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP101 : (Group 101 pm_smt_both) Run cycles
+
+#Group 102 pm_smt_selection, Thread selection
+event:0X660 counters:0 um:zero minimum:1000 name:PM_SNOOP_TLBIE_GRP102 : (Group 102 pm_smt_selection) Snoop TLBIE
+event:0X661 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP102 : (Group 102 pm_smt_selection) IOPS instructions completed
+event:0X662 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_T0_GRP102 : (Group 102 pm_smt_selection) Decode selected thread 0
+event:0X663 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_T1_GRP102 : (Group 102 pm_smt_selection) Decode selected thread 1
+event:0X664 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP102 : (Group 102 pm_smt_selection) Run instructions completed
+event:0X665 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP102 : (Group 102 pm_smt_selection) Run cycles
+
+#Group 103 pm_smt_selectover1, Thread selection overide
+event:0X670 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP103 : (Group 103 pm_smt_selectover1) IOPS instructions completed
+event:0X671 counters:1 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP103 : (Group 103 pm_smt_selectover1) Cycles no instructions in CLB
+event:0X672 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_OVER_CLB_EMPTY_GRP103 : (Group 103 pm_smt_selectover1) Thread selection overides caused by CLB empty
+event:0X673 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_OVER_GCT_IMBAL_GRP103 : (Group 103 pm_smt_selectover1) Thread selection overides caused by GCT imbalance
+event:0X674 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP103 : (Group 103 pm_smt_selectover1) Run instructions completed
+event:0X675 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP103 : (Group 103 pm_smt_selectover1) Run cycles
+
+#Group 104 pm_smt_selectover2, Thread selection overide
+event:0X680 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP104 : (Group 104 pm_smt_selectover2) IOPS instructions completed
+event:0X681 counters:1 um:zero minimum:10000 name:PM_CYC_GRP104 : (Group 104 pm_smt_selectover2) Processor cycles
+event:0X682 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_OVER_ISU_HOLD_GRP104 : (Group 104 pm_smt_selectover2) Thread selection overides caused by ISU holds
+event:0X683 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_OVER_L2MISS_GRP104 : (Group 104 pm_smt_selectover2) Thread selection overides caused by L2 misses
+event:0X684 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP104 : (Group 104 pm_smt_selectover2) Run instructions completed
+event:0X685 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP104 : (Group 104 pm_smt_selectover2) Run cycles
+
+#Group 105 pm_fabric1, Fabric events
+event:0X690 counters:0 um:zero minimum:1000 name:PM_FAB_CMD_ISSUED_GRP105 : (Group 105 pm_fabric1) Fabric command issued
+event:0X691 counters:1 um:zero minimum:1000 name:PM_FAB_DCLAIM_ISSUED_GRP105 : (Group 105 pm_fabric1) dclaim issued
+event:0X692 counters:2 um:zero minimum:1000 name:PM_FAB_CMD_RETRIED_GRP105 : (Group 105 pm_fabric1) Fabric command retried
+event:0X693 counters:3 um:zero minimum:1000 name:PM_FAB_DCLAIM_RETRIED_GRP105 : (Group 105 pm_fabric1) dclaim retried
+event:0X694 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP105 : (Group 105 pm_fabric1) Run instructions completed
+event:0X695 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP105 : (Group 105 pm_fabric1) Run cycles
+
+#Group 106 pm_fabric2, Fabric data movement
+event:0X6A0 counters:0 um:zero minimum:1000 name:PM_FAB_P1toM1_SIDECAR_EMPTY_GRP106 : (Group 106 pm_fabric2) P1 to M1 sidecar empty
+event:0X6A1 counters:1 um:zero minimum:1000 name:PM_FAB_HOLDtoVN_EMPTY_GRP106 : (Group 106 pm_fabric2) Hold buffer to VN empty
+event:0X6A2 counters:2 um:zero minimum:1000 name:PM_FAB_P1toVNorNN_SIDECAR_EMPTY_GRP106 : (Group 106 pm_fabric2) P1 to VN/NN sidecar empty
+event:0X6A3 counters:3 um:zero minimum:1000 name:PM_FAB_VBYPASS_EMPTY_GRP106 : (Group 106 pm_fabric2) Vertical bypass buffer empty
+event:0X6A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP106 : (Group 106 pm_fabric2) Run instructions completed
+event:0X6A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP106 : (Group 106 pm_fabric2) Run cycles
+
+#Group 107 pm_fabric3, Fabric data movement
+event:0X6B0 counters:0 um:zero minimum:1000 name:PM_FAB_PNtoNN_DIRECT_GRP107 : (Group 107 pm_fabric3) PN to NN beat went straight to its destination
+event:0X6B1 counters:1 um:zero minimum:1000 name:PM_FAB_PNtoVN_DIRECT_GRP107 : (Group 107 pm_fabric3) PN to VN beat went straight to its destination
+event:0X6B2 counters:2 um:zero minimum:1000 name:PM_FAB_PNtoNN_SIDECAR_GRP107 : (Group 107 pm_fabric3) PN to NN beat went to sidecar first
+event:0X6B3 counters:3 um:zero minimum:1000 name:PM_FAB_PNtoVN_SIDECAR_GRP107 : (Group 107 pm_fabric3) PN to VN beat went to sidecar first
+event:0X6B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP107 : (Group 107 pm_fabric3) Run instructions completed
+event:0X6B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP107 : (Group 107 pm_fabric3) Run cycles
+
+#Group 108 pm_fabric4, Fabric data movement
+event:0X6C0 counters:0 um:zero minimum:1000 name:PM_FAB_M1toP1_SIDECAR_EMPTY_GRP108 : (Group 108 pm_fabric4) M1 to P1 sidecar empty
+event:0X6C1 counters:1 um:zero minimum:1000 name:PM_FAB_HOLDtoNN_EMPTY_GRP108 : (Group 108 pm_fabric4) Hold buffer to NN empty
+event:0X6C2 counters:2 um:zero minimum:1000 name:PM_EE_OFF_GRP108 : (Group 108 pm_fabric4) Cycles MSR(EE) bit off
+event:0X6C3 counters:3 um:zero minimum:1000 name:PM_FAB_M1toVNorNN_SIDECAR_EMPTY_GRP108 : (Group 108 pm_fabric4) M1 to VN/NN sidecar empty
+event:0X6C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP108 : (Group 108 pm_fabric4) Run instructions completed
+event:0X6C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP108 : (Group 108 pm_fabric4) Run cycles
+
+#Group 109 pm_snoop1, Snoop retry
+event:0X6D0 counters:0 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_QFULL_GRP109 : (Group 109 pm_snoop1) Snoop read retry due to read queue full
+event:0X6D1 counters:1 um:zero minimum:1000 name:PM_SNOOP_DCLAIM_RETRY_QFULL_GRP109 : (Group 109 pm_snoop1) Snoop dclaim/flush retry due to write/dclaim queues full
+event:0X6D2 counters:2 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_QFULL_GRP109 : (Group 109 pm_snoop1) Snoop read retry due to read queue full
+event:0X6D3 counters:3 um:zero minimum:1000 name:PM_SNOOP_PARTIAL_RTRY_QFULL_GRP109 : (Group 109 pm_snoop1) Snoop partial write retry due to partial-write queues full
+event:0X6D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP109 : (Group 109 pm_snoop1) Run instructions completed
+event:0X6D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP109 : (Group 109 pm_snoop1) Run cycles
+
+#Group 110 pm_snoop2, Snoop read retry
+event:0X6E0 counters:0 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_RQ_GRP110 : (Group 110 pm_snoop2) Snoop read retry due to collision with active read queue
+event:0X6E1 counters:1 um:zero minimum:1000 name:PM_SNOOP_RETRY_1AHEAD_GRP110 : (Group 110 pm_snoop2) Snoop retry due to one ahead collision
+event:0X6E2 counters:2 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_WQ_GRP110 : (Group 110 pm_snoop2) Snoop read retry due to collision with active write queue
+event:0X6E3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP110 : (Group 110 pm_snoop2) IOPS instructions completed
+event:0X6E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP110 : (Group 110 pm_snoop2) Run instructions completed
+event:0X6E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP110 : (Group 110 pm_snoop2) Run cycles
+
+#Group 111 pm_snoop3, Snoop write retry
+event:0X6F0 counters:0 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_RQ_GRP111 : (Group 111 pm_snoop3) Snoop write/dclaim retry due to collision with active read queue
+event:0X6F1 counters:1 um:zero minimum:1000 name:PM_MEM_HI_PRIO_WR_CMPL_GRP111 : (Group 111 pm_snoop3) High priority write completed
+event:0X6F2 counters:2 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_WQ_GRP111 : (Group 111 pm_snoop3) Snoop write/dclaim retry due to collision with active write queue
+event:0X6F3 counters:3 um:zero minimum:1000 name:PM_MEM_LO_PRIO_WR_CMPL_GRP111 : (Group 111 pm_snoop3) Low priority write completed
+event:0X6F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP111 : (Group 111 pm_snoop3) Run instructions completed
+event:0X6F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP111 : (Group 111 pm_snoop3) Run cycles
+
+#Group 112 pm_snoop4, Snoop partial write retry
+event:0X700 counters:0 um:zero minimum:1000 name:PM_SNOOP_PW_RETRY_RQ_GRP112 : (Group 112 pm_snoop4) Snoop partial-write retry due to collision with active read queue
+event:0X701 counters:1 um:zero minimum:1000 name:PM_MEM_HI_PRIO_PW_CMPL_GRP112 : (Group 112 pm_snoop4) High priority partial-write completed
+event:0X702 counters:2 um:zero minimum:1000 name:PM_SNOOP_PW_RETRY_WQ_PWQ_GRP112 : (Group 112 pm_snoop4) Snoop partial-write retry due to collision with active write or partial-write queue
+event:0X703 counters:3 um:zero minimum:1000 name:PM_MEM_LO_PRIO_PW_CMPL_GRP112 : (Group 112 pm_snoop4) Low priority partial-write completed
+event:0X704 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP112 : (Group 112 pm_snoop4) Run instructions completed
+event:0X705 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP112 : (Group 112 pm_snoop4) Run cycles
+
+#Group 113 pm_mem_rq, Memory read queue dispatch
+event:0X710 counters:0 um:zero minimum:1000 name:PM_MEM_RQ_DISP_GRP113 : (Group 113 pm_mem_rq) Memory read queue dispatched
+event:0X711 counters:1 um:zero minimum:1000 name:PM_MEM_RQ_DISP_BUSY8to15_GRP113 : (Group 113 pm_mem_rq) Memory read queue dispatched with 8-15 queues busy
+event:0X712 counters:2 um:zero minimum:1000 name:PM_MEM_RQ_DISP_BUSY1to7_GRP113 : (Group 113 pm_mem_rq) Memory read queue dispatched with 1-7 queues busy
+event:0X713 counters:3 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP113 : (Group 113 pm_mem_rq) Cycles MSR(EE) bit off and external interrupt pending
+event:0X714 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP113 : (Group 113 pm_mem_rq) Run instructions completed
+event:0X715 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP113 : (Group 113 pm_mem_rq) Run cycles
+
+#Group 114 pm_mem_read, Memory read complete and cancel
+event:0X720 counters:0 um:zero minimum:1000 name:PM_MEM_READ_CMPL_GRP114 : (Group 114 pm_mem_read) Memory read completed or canceled
+event:0X721 counters:1 um:zero minimum:1000 name:PM_MEM_FAST_PATH_RD_CMPL_GRP114 : (Group 114 pm_mem_read) Fast path memory read completed
+event:0X722 counters:2 um:zero minimum:1000 name:PM_MEM_SPEC_RD_CANCEL_GRP114 : (Group 114 pm_mem_read) Speculative memory read canceled
+event:0X723 counters:3 um:zero minimum:1000 name:PM_EXT_INT_GRP114 : (Group 114 pm_mem_read) External interrupts
+event:0X724 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP114 : (Group 114 pm_mem_read) Run instructions completed
+event:0X725 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP114 : (Group 114 pm_mem_read) Run cycles
+
+#Group 115 pm_mem_wq, Memory write queue dispatch
+event:0X730 counters:0 um:zero minimum:1000 name:PM_MEM_WQ_DISP_WRITE_GRP115 : (Group 115 pm_mem_wq) Memory write queue dispatched due to write
+event:0X731 counters:1 um:zero minimum:1000 name:PM_MEM_WQ_DISP_BUSY1to7_GRP115 : (Group 115 pm_mem_wq) Memory write queue dispatched with 1-7 queues busy
+event:0X732 counters:2 um:zero minimum:1000 name:PM_MEM_WQ_DISP_DCLAIM_GRP115 : (Group 115 pm_mem_wq) Memory write queue dispatched due to dclaim/flush
+event:0X733 counters:3 um:zero minimum:1000 name:PM_MEM_WQ_DISP_BUSY8to15_GRP115 : (Group 115 pm_mem_wq) Memory write queue dispatched with 8-15 queues busy
+event:0X734 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP115 : (Group 115 pm_mem_wq) Run instructions completed
+event:0X735 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP115 : (Group 115 pm_mem_wq) Run cycles
+
+#Group 116 pm_mem_pwq, Memory partial write queue
+event:0X740 counters:0 um:zero minimum:1000 name:PM_MEM_PWQ_DISP_GRP116 : (Group 116 pm_mem_pwq) Memory partial-write queue dispatched
+event:0X741 counters:1 um:zero minimum:1000 name:PM_MEM_PWQ_DISP_BUSY2or3_GRP116 : (Group 116 pm_mem_pwq) Memory partial-write queue dispatched with 2-3 queues busy
+event:0X742 counters:2 um:zero minimum:1000 name:PM_MEM_PW_GATH_GRP116 : (Group 116 pm_mem_pwq) Memory partial-write gathered
+event:0X743 counters:3 um:zero minimum:1000 name:PM_MEM_PW_CMPL_GRP116 : (Group 116 pm_mem_pwq) Memory partial-write completed
+event:0X744 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP116 : (Group 116 pm_mem_pwq) Run instructions completed
+event:0X745 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP116 : (Group 116 pm_mem_pwq) Run cycles
+
+#Group 117 pm_threshold, Thresholding
+event:0X750 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP117 : (Group 117 pm_threshold) Marked group dispatched
+event:0X751 counters:1 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP117 : (Group 117 pm_threshold) Marked IMR reloaded
+event:0X752 counters:2 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP117 : (Group 117 pm_threshold) Threshold timeout
+event:0X753 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP117 : (Group 117 pm_threshold) Marked instruction LSU processing finished
+event:0X754 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP117 : (Group 117 pm_threshold) Run instructions completed
+event:0X755 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP117 : (Group 117 pm_threshold) Run cycles
+
+#Group 118 pm_mrk_grp1, Marked group events
+event:0X760 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP118 : (Group 118 pm_mrk_grp1) Marked group dispatched
+event:0X761 counters:1 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP118 : (Group 118 pm_mrk_grp1) Marked L1 D cache store misses
+event:0X762 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP118 : (Group 118 pm_mrk_grp1) Marked instruction finished
+event:0X763 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP118 : (Group 118 pm_mrk_grp1) Marked group completed
+event:0X764 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP118 : (Group 118 pm_mrk_grp1) Run instructions completed
+event:0X765 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP118 : (Group 118 pm_mrk_grp1) Run cycles
+
+#Group 119 pm_mrk_grp2, Marked group events
+event:0X770 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP119 : (Group 119 pm_mrk_grp2) Marked group issued
+event:0X771 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP119 : (Group 119 pm_mrk_grp2) Marked instruction BRU processing finished
+event:0X772 counters:2 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP119 : (Group 119 pm_mrk_grp2) Marked L1 reload data source valid
+event:0X773 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_IC_MISS_GRP119 : (Group 119 pm_mrk_grp2) Group experienced marked I cache miss
+event:0X774 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP119 : (Group 119 pm_mrk_grp2) Run instructions completed
+event:0X775 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP119 : (Group 119 pm_mrk_grp2) Run cycles
+
+#Group 120 pm_mrk_dsource1, Marked data from
+event:0X780 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP120 : (Group 120 pm_mrk_dsource1) Marked data loaded from L2
+event:0X781 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_CYC_GRP120 : (Group 120 pm_mrk_dsource1) Marked load latency from L2
+event:0X782 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP120 : (Group 120 pm_mrk_dsource1) Marked data loaded from L2.5 modified
+event:0X783 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_CYC_GRP120 : (Group 120 pm_mrk_dsource1) Marked load latency from L2.5 modified
+event:0X784 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP120 : (Group 120 pm_mrk_dsource1) Run instructions completed
+event:0X785 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP120 : (Group 120 pm_mrk_dsource1) Run cycles
+
+#Group 121 pm_mrk_dsource2, Marked data from
+event:0X790 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP121 : (Group 121 pm_mrk_dsource2) Marked data loaded from L2.5 shared
+event:0X791 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_CYC_GRP121 : (Group 121 pm_mrk_dsource2) Marked load latency from L2.5 shared
+event:0X792 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP121 : (Group 121 pm_mrk_dsource2) IOPS instructions completed
+event:0X793 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP121 : (Group 121 pm_mrk_dsource2) FPU produced a result
+event:0X794 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP121 : (Group 121 pm_mrk_dsource2) Run instructions completed
+event:0X795 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP121 : (Group 121 pm_mrk_dsource2) Run cycles
+
+#Group 122 pm_mrk_dsource3, Marked data from
+event:0X7A0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP122 : (Group 122 pm_mrk_dsource3) Marked data loaded from L3
+event:0X7A1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_CYC_GRP122 : (Group 122 pm_mrk_dsource3) Marked load latency from L3
+event:0X7A2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_GRP122 : (Group 122 pm_mrk_dsource3) Marked data loaded from L3.5 modified
+event:0X7A3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_CYC_GRP122 : (Group 122 pm_mrk_dsource3) Marked load latency from L3.5 modified
+event:0X7A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP122 : (Group 122 pm_mrk_dsource3) Run instructions completed
+event:0X7A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP122 : (Group 122 pm_mrk_dsource3) Run cycles
+
+#Group 123 pm_mrk_dsource4, Marked data from
+event:0X7B0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_GRP123 : (Group 123 pm_mrk_dsource4) Marked data loaded from remote memory
+event:0X7B1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_CYC_GRP123 : (Group 123 pm_mrk_dsource4) Marked load latency from L2.75 shared
+event:0X7B2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_GRP123 : (Group 123 pm_mrk_dsource4) Marked data loaded from L2.75 shared
+event:0X7B3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_CYC_GRP123 : (Group 123 pm_mrk_dsource4) Marked load latency from remote memory
+event:0X7B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP123 : (Group 123 pm_mrk_dsource4) Run instructions completed
+event:0X7B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP123 : (Group 123 pm_mrk_dsource4) Run cycles
+
+#Group 124 pm_mrk_dsource5, Marked data from
+event:0X7C0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_GRP124 : (Group 124 pm_mrk_dsource5) Marked data loaded from L3.5 shared
+event:0X7C1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_CYC_GRP124 : (Group 124 pm_mrk_dsource5) Marked load latency from L3.5 shared
+event:0X7C2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_GRP124 : (Group 124 pm_mrk_dsource5) Marked data loaded from local memory
+event:0X7C3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_CYC_GRP124 : (Group 124 pm_mrk_dsource5) Marked load latency from local memory
+event:0X7C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP124 : (Group 124 pm_mrk_dsource5) Run instructions completed
+event:0X7C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP124 : (Group 124 pm_mrk_dsource5) Run cycles
+
+#Group 125 pm_mrk_dsource6, Marked data from
+event:0X7D0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP125 : (Group 125 pm_mrk_dsource6) Marked data loaded from L2.75 modified
+event:0X7D1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_CYC_GRP125 : (Group 125 pm_mrk_dsource6) Marked load latency from L2.75 shared
+event:0X7D2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP125 : (Group 125 pm_mrk_dsource6) IOPS instructions completed
+event:0X7D3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_CYC_GRP125 : (Group 125 pm_mrk_dsource6) Marked load latency from L2.75 modified
+event:0X7D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP125 : (Group 125 pm_mrk_dsource6) Run instructions completed
+event:0X7D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP125 : (Group 125 pm_mrk_dsource6) Run cycles
+
+#Group 126 pm_mrk_dsource7, Marked data from
+event:0X7E0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_MOD_GRP126 : (Group 126 pm_mrk_dsource7) Marked data loaded from L3.75 modified
+event:0X7E1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_SHR_CYC_GRP126 : (Group 126 pm_mrk_dsource7) Marked load latency from L3.75 shared
+event:0X7E2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_SHR_GRP126 : (Group 126 pm_mrk_dsource7) Marked data loaded from L3.75 shared
+event:0X7E3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_MOD_CYC_GRP126 : (Group 126 pm_mrk_dsource7) Marked load latency from L3.75 modified
+event:0X7E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP126 : (Group 126 pm_mrk_dsource7) Run instructions completed
+event:0X7E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP126 : (Group 126 pm_mrk_dsource7) Run cycles
+
+#Group 127 pm_mrk_dtlbref, Marked data TLB references
+event:0X7F0 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_4K_GRP127 : (Group 127 pm_mrk_dtlbref) Marked Data TLB reference for 4K page
+event:0X7F1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_REF_64K_GRP127 : (Group 127 pm_mrk_dtlbref) Marked Data TLB reference for 64K page
+event:0X7F2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16M_GRP127 : (Group 127 pm_mrk_dtlbref) Marked Data TLB reference for 16M page
+event:0X7F3 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16G_GRP127 : (Group 127 pm_mrk_dtlbref) Marked Data TLB reference for 16G page
+event:0X7F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP127 : (Group 127 pm_mrk_dtlbref) Run instructions completed
+event:0X7F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP127 : (Group 127 pm_mrk_dtlbref) Run cycles
+
+#Group 128 pm_mrk_dtlbmiss, Marked data TLB misses
+event:0X800 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP128 : (Group 128 pm_mrk_dtlbmiss) Marked Data TLB misses for 4K page
+event:0X801 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_64K_GRP128 : (Group 128 pm_mrk_dtlbmiss) Marked Data TLB misses for 64K page
+event:0X802 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16M_GRP128 : (Group 128 pm_mrk_dtlbmiss) Marked Data TLB misses for 16M page
+event:0X803 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16G_GRP128 : (Group 128 pm_mrk_dtlbmiss) Marked Data TLB misses for 16G page
+event:0X804 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP128 : (Group 128 pm_mrk_dtlbmiss) Run instructions completed
+event:0X805 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP128 : (Group 128 pm_mrk_dtlbmiss) Run cycles
+
+#Group 129 pm_mrk_dtlb_dslb, Marked data TLB references and misses and marked data SLB misses
+event:0X810 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Marked Data TLB reference
+event:0X811 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Marked Data TLB misses
+event:0X812 counters:2 um:zero minimum:1000 name:PM_MRK_DSLB_MISS_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Marked Data SLB misses
+event:0X813 counters:3 um:zero minimum:10000 name:PM_CYC_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Processor cycles
+event:0X814 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Run instructions completed
+event:0X815 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP129 : (Group 129 pm_mrk_dtlb_dslb) Run cycles
+
+#Group 130 pm_mrk_lbref, Marked TLB and SLB references
+event:0X820 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_4K_GRP130 : (Group 130 pm_mrk_lbref) Marked Data TLB reference for 4K page
+event:0X821 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP130 : (Group 130 pm_mrk_lbref) IOPS instructions completed
+event:0X822 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16M_GRP130 : (Group 130 pm_mrk_lbref) Marked Data TLB reference for 16M page
+event:0X823 counters:3 um:zero minimum:1000 name:PM_MRK_DSLB_MISS_GRP130 : (Group 130 pm_mrk_lbref) Marked Data SLB misses
+event:0X824 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP130 : (Group 130 pm_mrk_lbref) Run instructions completed
+event:0X825 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP130 : (Group 130 pm_mrk_lbref) Run cycles
+
+#Group 131 pm_mrk_lsmiss, Marked load and store miss
+event:0X830 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP131 : (Group 131 pm_mrk_lsmiss) Marked L1 D cache load misses
+event:0X831 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP131 : (Group 131 pm_mrk_lsmiss) IOPS instructions completed
+event:0X832 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP131 : (Group 131 pm_mrk_lsmiss) Marked store completed with intervention
+event:0X833 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP131 : (Group 131 pm_mrk_lsmiss) Marked instruction CRU processing finished
+event:0X834 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP131 : (Group 131 pm_mrk_lsmiss) Run instructions completed
+event:0X835 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP131 : (Group 131 pm_mrk_lsmiss) Run cycles
+
+#Group 132 pm_mrk_ulsflush, Mark unaligned load and store flushes
+event:0X840 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP132 : (Group 132 pm_mrk_ulsflush) Marked store instruction completed
+event:0X841 counters:1 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP132 : (Group 132 pm_mrk_ulsflush) Marked L1 D cache store misses
+event:0X842 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_UST_GRP132 : (Group 132 pm_mrk_ulsflush) Marked unaligned store flushes
+event:0X843 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_ULD_GRP132 : (Group 132 pm_mrk_ulsflush) Marked unaligned load flushes
+event:0X844 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP132 : (Group 132 pm_mrk_ulsflush) Run instructions completed
+event:0X845 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP132 : (Group 132 pm_mrk_ulsflush) Run cycles
+
+#Group 133 pm_mrk_misc, Misc marked instructions
+event:0X850 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP133 : (Group 133 pm_mrk_misc) Marked STCX failed
+event:0X851 counters:1 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP133 : (Group 133 pm_mrk_misc) Marked store sent to GPS
+event:0X852 counters:2 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP133 : (Group 133 pm_mrk_misc) Marked instruction FPU processing finished
+event:0X853 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP133 : (Group 133 pm_mrk_misc) Marked group completion timeout
+event:0X854 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP133 : (Group 133 pm_mrk_misc) Run instructions completed
+event:0X855 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP133 : (Group 133 pm_mrk_misc) Run cycles
+
+#Group 134 pm_lsref_L1, Load/Store operations and L1 activity
+event:0X860 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP134 : (Group 134 pm_lsref_L1) Data loaded from L2
+event:0X861 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP134 : (Group 134 pm_lsref_L1) Instruction fetched from L1
+event:0X862 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP134 : (Group 134 pm_lsref_L1) L1 D cache store references
+event:0X863 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP134 : (Group 134 pm_lsref_L1) L1 D cache load references
+event:0X864 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP134 : (Group 134 pm_lsref_L1) Run instructions completed
+event:0X865 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP134 : (Group 134 pm_lsref_L1) Run cycles
+
+#Group 135 pm_lsref_L2L3, Load/Store operations and L2,L3 activity
+event:0X870 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP135 : (Group 135 pm_lsref_L2L3) Data loaded from L3
+event:0X871 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP135 : (Group 135 pm_lsref_L2L3) Data loaded from local memory
+event:0X872 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP135 : (Group 135 pm_lsref_L2L3) L1 D cache store references
+event:0X873 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP135 : (Group 135 pm_lsref_L2L3) L1 D cache load references
+event:0X874 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP135 : (Group 135 pm_lsref_L2L3) Run instructions completed
+event:0X875 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP135 : (Group 135 pm_lsref_L2L3) Run cycles
+
+#Group 136 pm_lsref_tlbmiss, Load/Store operations and TLB misses
+event:0X880 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP136 : (Group 136 pm_lsref_tlbmiss) Instruction TLB misses
+event:0X881 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP136 : (Group 136 pm_lsref_tlbmiss) Data TLB misses
+event:0X882 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP136 : (Group 136 pm_lsref_tlbmiss) L1 D cache store references
+event:0X883 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP136 : (Group 136 pm_lsref_tlbmiss) L1 D cache load references
+event:0X884 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP136 : (Group 136 pm_lsref_tlbmiss) Run instructions completed
+event:0X885 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP136 : (Group 136 pm_lsref_tlbmiss) Run cycles
+
+#Group 137 pm_Dmiss, Data cache misses
+event:0X890 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP137 : (Group 137 pm_Dmiss) Data loaded from L3
+event:0X891 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP137 : (Group 137 pm_Dmiss) Data loaded from local memory
+event:0X892 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP137 : (Group 137 pm_Dmiss) L1 D cache load misses
+event:0X893 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP137 : (Group 137 pm_Dmiss) L1 D cache store misses
+event:0X894 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP137 : (Group 137 pm_Dmiss) Run instructions completed
+event:0X895 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP137 : (Group 137 pm_Dmiss) Run cycles
+
+#Group 138 pm_prefetchX, Prefetch events
+event:0X8A0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP138 : (Group 138 pm_prefetchX) Processor cycles
+event:0X8A1 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP138 : (Group 138 pm_prefetchX) Instruction prefetch requests
+event:0X8A2 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP138 : (Group 138 pm_prefetchX) L1 cache data prefetches
+event:0X8A3 counters:3 um:zero minimum:1000 name:PM_L2_PREF_GRP138 : (Group 138 pm_prefetchX) L2 cache prefetches
+event:0X8A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP138 : (Group 138 pm_prefetchX) Run instructions completed
+event:0X8A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP138 : (Group 138 pm_prefetchX) Run cycles
+
+#Group 139 pm_branchX, Branch operations
+event:0X8B0 counters:0 um:zero minimum:1000 name:PM_BR_UNCOND_GRP139 : (Group 139 pm_branchX) Unconditional branch
+event:0X8B1 counters:1 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP139 : (Group 139 pm_branchX) A conditional branch was predicted, target prediction
+event:0X8B2 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP139 : (Group 139 pm_branchX) A conditional branch was predicted, CR prediction
+event:0X8B3 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP139 : (Group 139 pm_branchX) Branches issued
+event:0X8B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP139 : (Group 139 pm_branchX) Run instructions completed
+event:0X8B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP139 : (Group 139 pm_branchX) Run cycles
+
+#Group 140 pm_fpuX1, Floating point events by unit
+event:0X8C0 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP140 : (Group 140 pm_fpuX1) FPU0 stalled in pipe3
+event:0X8C1 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP140 : (Group 140 pm_fpuX1) FPU1 stalled in pipe3
+event:0X8C2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP140 : (Group 140 pm_fpuX1) FPU0 produced a result
+event:0X8C3 counters:3 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP140 : (Group 140 pm_fpuX1) FPU0 executed FPSCR instruction
+event:0X8C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP140 : (Group 140 pm_fpuX1) Run instructions completed
+event:0X8C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP140 : (Group 140 pm_fpuX1) Run cycles
+
+#Group 141 pm_fpuX2, Floating point events by unit
+event:0X8D0 counters:0 um:zero minimum:1000 name:PM_FPU0_FMA_GRP141 : (Group 141 pm_fpuX2) FPU0 executed multiply-add instruction
+event:0X8D1 counters:1 um:zero minimum:1000 name:PM_FPU1_FMA_GRP141 : (Group 141 pm_fpuX2) FPU1 executed multiply-add instruction
+event:0X8D2 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP141 : (Group 141 pm_fpuX2) FPU0 executed FRSP or FCONV instructions
+event:0X8D3 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP141 : (Group 141 pm_fpuX2) FPU1 executed FRSP or FCONV instructions
+event:0X8D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP141 : (Group 141 pm_fpuX2) Run instructions completed
+event:0X8D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP141 : (Group 141 pm_fpuX2) Run cycles
+
+#Group 142 pm_fpuX3, Floating point events by unit
+event:0X8E0 counters:0 um:zero minimum:1000 name:PM_FPU0_1FLOP_GRP142 : (Group 142 pm_fpuX3) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X8E1 counters:1 um:zero minimum:1000 name:PM_FPU1_1FLOP_GRP142 : (Group 142 pm_fpuX3) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X8E2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP142 : (Group 142 pm_fpuX3) FPU0 produced a result
+event:0X8E3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP142 : (Group 142 pm_fpuX3) FPU1 produced a result
+event:0X8E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP142 : (Group 142 pm_fpuX3) Run instructions completed
+event:0X8E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP142 : (Group 142 pm_fpuX3) Run cycles
+
+#Group 143 pm_fpuX4, Floating point and L1 events
+event:0X8F0 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP143 : (Group 143 pm_fpuX4) FPU executed one flop instruction
+event:0X8F1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP143 : (Group 143 pm_fpuX4) FPU executed multiply-add instruction
+event:0X8F2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP143 : (Group 143 pm_fpuX4) L1 D cache store references
+event:0X8F3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP143 : (Group 143 pm_fpuX4) L1 D cache load references
+event:0X8F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP143 : (Group 143 pm_fpuX4) Run instructions completed
+event:0X8F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP143 : (Group 143 pm_fpuX4) Run cycles
+
+#Group 144 pm_fpuX5, Floating point events
+event:0X900 counters:0 um:zero minimum:1000 name:PM_FPU_SINGLE_GRP144 : (Group 144 pm_fpuX5) FPU executed single precision instruction
+event:0X901 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP144 : (Group 144 pm_fpuX5) FPU executed store instruction
+event:0X902 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP144 : (Group 144 pm_fpuX5) FPU0 produced a result
+event:0X903 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP144 : (Group 144 pm_fpuX5) FPU1 produced a result
+event:0X904 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP144 : (Group 144 pm_fpuX5) Run instructions completed
+event:0X905 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP144 : (Group 144 pm_fpuX5) Run cycles
+
+#Group 145 pm_fpuX6, Floating point events
+event:0X910 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP145 : (Group 145 pm_fpuX6) FPU executed FDIV instruction
+event:0X911 counters:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP145 : (Group 145 pm_fpuX6) FPU executed FSQRT instruction
+event:0X912 counters:2 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP145 : (Group 145 pm_fpuX6) FPU executed FRSP or FCONV instructions
+event:0X913 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP145 : (Group 145 pm_fpuX6) FPU produced a result
+event:0X914 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP145 : (Group 145 pm_fpuX6) Run instructions completed
+event:0X915 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP145 : (Group 145 pm_fpuX6) Run cycles
+
+#Group 146 pm_fpuX7, Floating point events
+event:0X920 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP146 : (Group 146 pm_fpuX7) FPU executed one flop instruction
+event:0X921 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP146 : (Group 146 pm_fpuX7) FPU executed multiply-add instruction
+event:0X922 counters:2 um:zero minimum:1000 name:PM_FPU_STF_GRP146 : (Group 146 pm_fpuX7) FPU executed store instruction
+event:0X923 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP146 : (Group 146 pm_fpuX7) FPU produced a result
+event:0X924 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP146 : (Group 146 pm_fpuX7) Run instructions completed
+event:0X925 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP146 : (Group 146 pm_fpuX7) Run cycles
+
+#Group 147 pm_hpmcount1, HPM group for set 1
+event:0X930 counters:0 um:zero minimum:10000 name:PM_CYC_GRP147 : (Group 147 pm_hpmcount1) Processor cycles
+event:0X931 counters:1 um:zero minimum:1000 name:PM_FXU_FIN_GRP147 : (Group 147 pm_hpmcount1) FXU produced a result
+event:0X932 counters:2 um:zero minimum:10000 name:PM_CYC_GRP147 : (Group 147 pm_hpmcount1) Processor cycles
+event:0X933 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP147 : (Group 147 pm_hpmcount1) FPU produced a result
+event:0X934 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP147 : (Group 147 pm_hpmcount1) Run instructions completed
+event:0X935 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP147 : (Group 147 pm_hpmcount1) Run cycles
+
+#Group 148 pm_hpmcount2, HPM group for set 2
+event:0X940 counters:0 um:zero minimum:10000 name:PM_CYC_GRP148 : (Group 148 pm_hpmcount2) Processor cycles
+event:0X941 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP148 : (Group 148 pm_hpmcount2) FPU executed store instruction
+event:0X942 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP148 : (Group 148 pm_hpmcount2) Instructions dispatched
+event:0X943 counters:3 um:zero minimum:1000 name:PM_LSU_LDF_GRP148 : (Group 148 pm_hpmcount2) LSU executed Floating Point load instruction
+event:0X944 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP148 : (Group 148 pm_hpmcount2) Run instructions completed
+event:0X945 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP148 : (Group 148 pm_hpmcount2) Run cycles
+
+#Group 149 pm_hpmcount3, HPM group for set 3
+event:0X950 counters:0 um:zero minimum:10000 name:PM_CYC_GRP149 : (Group 149 pm_hpmcount3) Processor cycles
+event:0X951 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP149 : (Group 149 pm_hpmcount3) Instructions dispatched
+event:0X952 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP149 : (Group 149 pm_hpmcount3) L1 D cache load misses
+event:0X953 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP149 : (Group 149 pm_hpmcount3) L1 D cache store misses
+event:0X954 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP149 : (Group 149 pm_hpmcount3) Run instructions completed
+event:0X955 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP149 : (Group 149 pm_hpmcount3) Run cycles
+
+#Group 150 pm_hpmcount4, HPM group for set 7
+event:0X960 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP150 : (Group 150 pm_hpmcount4) TLB misses
+event:0X961 counters:1 um:zero minimum:10000 name:PM_CYC_GRP150 : (Group 150 pm_hpmcount4) Processor cycles
+event:0X962 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP150 : (Group 150 pm_hpmcount4) L1 D cache store references
+event:0X963 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP150 : (Group 150 pm_hpmcount4) L1 D cache load references
+event:0X964 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP150 : (Group 150 pm_hpmcount4) Run instructions completed
+event:0X965 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP150 : (Group 150 pm_hpmcount4) Run cycles
+
+#Group 151 pm_flop, Floating point operations
+event:0X970 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP151 : (Group 151 pm_flop) FPU executed FDIV instruction
+event:0X971 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP151 : (Group 151 pm_flop) FPU executed multiply-add instruction
+event:0X972 counters:2 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP151 : (Group 151 pm_flop) FPU executed FSQRT instruction
+event:0X973 counters:3 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP151 : (Group 151 pm_flop) FPU executed one flop instruction
+event:0X974 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP151 : (Group 151 pm_flop) Run instructions completed
+event:0X975 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP151 : (Group 151 pm_flop) Run cycles
+
+#Group 152 pm_eprof1, Group for use with eprof
+event:0X980 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP152 : (Group 152 pm_eprof1) Instructions completed
+event:0X981 counters:1 um:zero minimum:10000 name:PM_CYC_GRP152 : (Group 152 pm_eprof1) Processor cycles
+event:0X982 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP152 : (Group 152 pm_eprof1) L1 D cache load misses
+event:0X983 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP152 : (Group 152 pm_eprof1) L1 D cache entries invalidated from L2
+event:0X984 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP152 : (Group 152 pm_eprof1) Run instructions completed
+event:0X985 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP152 : (Group 152 pm_eprof1) Run cycles
+
+#Group 153 pm_eprof2, Group for use with eprof
+event:0X990 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP153 : (Group 153 pm_eprof2) Instructions completed
+event:0X991 counters:1 um:zero minimum:1000 name:PM_ST_REF_L1_GRP153 : (Group 153 pm_eprof2) L1 D cache store references
+event:0X992 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP153 : (Group 153 pm_eprof2) Instructions dispatched
+event:0X993 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP153 : (Group 153 pm_eprof2) L1 D cache load references
+event:0X994 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP153 : (Group 153 pm_eprof2) Run instructions completed
+event:0X995 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP153 : (Group 153 pm_eprof2) Run cycles
diff --git a/events/ppc64/power5+/unit_masks b/events/ppc64/power5+/unit_masks
new file mode 100644
index 0000000..77921ae
--- /dev/null
+++ b/events/ppc64/power5+/unit_masks
@@ -0,0 +1,4 @@
+# ppc64 Power5+ possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/power5/event_mappings b/events/ppc64/power5/event_mappings
new file mode 100644
index 0000000..dd3c779
--- /dev/null
+++ b/events/ppc64/power5/event_mappings
@@ -0,0 +1,1192 @@
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+
+#Group 0 with random sampling
+event:0X002 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X010 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X011 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X012 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X013 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X014 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X015 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+
+#Group 2 pm_completion, Completion and cycle counts
+event:0X020 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X021 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X022 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X023 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X024 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+event:0X025 mmcr0:0X00000000 mmcr1:0X000000002608261E mmcra:0X00000000
+
+#Group 3 pm_group_dispatch, Group dispatch events
+event:0X030 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X031 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X032 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X033 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X034 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+event:0X035 mmcr0:0X00000000 mmcr1:0X4000000EC6C8C212 mmcra:0X00000000
+
+#Group 4 pm_clb1, CLB fullness
+event:0X040 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X041 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X042 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X043 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X044 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+event:0X045 mmcr0:0X00000000 mmcr1:0X015B000180848C4C mmcra:0X00000001
+
+#Group 5 pm_clb2, CLB fullness
+event:0X050 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X051 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X052 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X053 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X054 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+event:0X055 mmcr0:0X00000000 mmcr1:0X014300028A8CCC02 mmcra:0X00000001
+
+#Group 6 pm_gct_empty, GCT empty reasons
+event:0X060 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X061 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X062 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X063 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X064 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+event:0X065 mmcr0:0X00000000 mmcr1:0X4000000008380838 mmcra:0X00000000
+
+#Group 7 pm_gct_usage, GCT Usage
+event:0X070 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X071 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X072 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X073 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X074 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+event:0X075 mmcr0:0X00000000 mmcr1:0X000000003E3E3E3E mmcra:0X00000000
+
+#Group 8 pm_lsu1, LSU LRQ and LMQ events
+event:0X080 mmcr0:0X00000000 mmcr1:0X000F000FCCC4CCCA mmcra:0X00000000
+event:0X081 mmcr0:0X00000000 mmcr1:0X000F000FCCC4CCCA mmcra:0X00000000
+event:0X082 mmcr0:0X00000000 mmcr1:0X000F000FCCC4CCCA mmcra:0X00000000
+event:0X083 mmcr0:0X00000000 mmcr1:0X000F000FCCC4CCCA mmcra:0X00000000
+event:0X084 mmcr0:0X00000000 mmcr1:0X000F000FCCC4CCCA mmcra:0X00000000
+event:0X085 mmcr0:0X00000000 mmcr1:0X000F000FCCC4CCCA mmcra:0X00000000
+
+#Group 9 pm_lsu2, LSU SRQ events
+event:0X090 mmcr0:0X00000000 mmcr1:0X400E000ECAC2CA86 mmcra:0X00000000
+event:0X091 mmcr0:0X00000000 mmcr1:0X400E000ECAC2CA86 mmcra:0X00000000
+event:0X092 mmcr0:0X00000000 mmcr1:0X400E000ECAC2CA86 mmcra:0X00000000
+event:0X093 mmcr0:0X00000000 mmcr1:0X400E000ECAC2CA86 mmcra:0X00000000
+event:0X094 mmcr0:0X00000000 mmcr1:0X400E000ECAC2CA86 mmcra:0X00000000
+event:0X095 mmcr0:0X00000000 mmcr1:0X400E000ECAC2CA86 mmcra:0X00000000
+
+#Group 10 pm_lsu3, LSU SRQ and LMQ events
+event:0X0A0 mmcr0:0X00000000 mmcr1:0X010F000A102ACA2A mmcra:0X00000000
+event:0X0A1 mmcr0:0X00000000 mmcr1:0X010F000A102ACA2A mmcra:0X00000000
+event:0X0A2 mmcr0:0X00000000 mmcr1:0X010F000A102ACA2A mmcra:0X00000000
+event:0X0A3 mmcr0:0X00000000 mmcr1:0X010F000A102ACA2A mmcra:0X00000000
+event:0X0A4 mmcr0:0X00000000 mmcr1:0X010F000A102ACA2A mmcra:0X00000000
+event:0X0A5 mmcr0:0X00000000 mmcr1:0X010F000A102ACA2A mmcra:0X00000000
+
+#Group 11 pm_prefetch1, Prefetch stream allocation
+event:0X0B0 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+event:0X0B1 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+event:0X0B2 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+event:0X0B3 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+event:0X0B4 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+event:0X0B5 mmcr0:0X00000000 mmcr1:0X8432000D36C884CE mmcra:0X00000000
+
+#Group 12 pm_prefetch2, Prefetch events
+event:0X0C0 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0C1 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0C2 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0C3 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0C4 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+event:0X0C5 mmcr0:0X00000000 mmcr1:0X8103000602CACE8E mmcra:0X00000001
+
+#Group 13 pm_prefetch3, L2 prefetch and misc events
+event:0X0D0 mmcr0:0X00000000 mmcr1:0X047C000820828602 mmcra:0X00000001
+event:0X0D1 mmcr0:0X00000000 mmcr1:0X047C000820828602 mmcra:0X00000001
+event:0X0D2 mmcr0:0X00000000 mmcr1:0X047C000820828602 mmcra:0X00000001
+event:0X0D3 mmcr0:0X00000000 mmcr1:0X047C000820828602 mmcra:0X00000001
+event:0X0D4 mmcr0:0X00000000 mmcr1:0X047C000820828602 mmcra:0X00000001
+event:0X0D5 mmcr0:0X00000000 mmcr1:0X047C000820828602 mmcra:0X00000001
+
+#Group 14 pm_prefetch4, Misc prefetch and reject events
+event:0X0E0 mmcr0:0X00000000 mmcr1:0X063E000EC0C8CC86 mmcra:0X00000000
+event:0X0E1 mmcr0:0X00000000 mmcr1:0X063E000EC0C8CC86 mmcra:0X00000000
+event:0X0E2 mmcr0:0X00000000 mmcr1:0X063E000EC0C8CC86 mmcra:0X00000000
+event:0X0E3 mmcr0:0X00000000 mmcr1:0X063E000EC0C8CC86 mmcra:0X00000000
+event:0X0E4 mmcr0:0X00000000 mmcr1:0X063E000EC0C8CC86 mmcra:0X00000000
+event:0X0E5 mmcr0:0X00000000 mmcr1:0X063E000EC0C8CC86 mmcra:0X00000000
+
+#Group 15 pm_lsu_reject1, LSU reject events
+event:0X0F0 mmcr0:0X00000000 mmcr1:0XC22C000E2010C610 mmcra:0X00000001
+event:0X0F1 mmcr0:0X00000000 mmcr1:0XC22C000E2010C610 mmcra:0X00000001
+event:0X0F2 mmcr0:0X00000000 mmcr1:0XC22C000E2010C610 mmcra:0X00000001
+event:0X0F3 mmcr0:0X00000000 mmcr1:0XC22C000E2010C610 mmcra:0X00000001
+event:0X0F4 mmcr0:0X00000000 mmcr1:0XC22C000E2010C610 mmcra:0X00000001
+event:0X0F5 mmcr0:0X00000000 mmcr1:0XC22C000E2010C610 mmcra:0X00000001
+
+#Group 16 pm_lsu_reject2, LSU rejects due to reload CDF or tag update collision
+event:0X100 mmcr0:0X00000000 mmcr1:0X820C000DC4CC02CE mmcra:0X00000001
+event:0X101 mmcr0:0X00000000 mmcr1:0X820C000DC4CC02CE mmcra:0X00000001
+event:0X102 mmcr0:0X00000000 mmcr1:0X820C000DC4CC02CE mmcra:0X00000001
+event:0X103 mmcr0:0X00000000 mmcr1:0X820C000DC4CC02CE mmcra:0X00000001
+event:0X104 mmcr0:0X00000000 mmcr1:0X820C000DC4CC02CE mmcra:0X00000001
+event:0X105 mmcr0:0X00000000 mmcr1:0X820C000DC4CC02CE mmcra:0X00000001
+
+#Group 17 pm_lsu_reject3, LSU rejects due to ERAT, held instuctions
+event:0X110 mmcr0:0X00000000 mmcr1:0X420C000FC6CEC0C8 mmcra:0X00000000
+event:0X111 mmcr0:0X00000000 mmcr1:0X420C000FC6CEC0C8 mmcra:0X00000000
+event:0X112 mmcr0:0X00000000 mmcr1:0X420C000FC6CEC0C8 mmcra:0X00000000
+event:0X113 mmcr0:0X00000000 mmcr1:0X420C000FC6CEC0C8 mmcra:0X00000000
+event:0X114 mmcr0:0X00000000 mmcr1:0X420C000FC6CEC0C8 mmcra:0X00000000
+event:0X115 mmcr0:0X00000000 mmcr1:0X420C000FC6CEC0C8 mmcra:0X00000000
+
+#Group 18 pm_lsu_reject4, LSU0/1 reject LMQ full
+event:0X120 mmcr0:0X00000000 mmcr1:0X820C000DC2CA02C8 mmcra:0X00000001
+event:0X121 mmcr0:0X00000000 mmcr1:0X820C000DC2CA02C8 mmcra:0X00000001
+event:0X122 mmcr0:0X00000000 mmcr1:0X820C000DC2CA02C8 mmcra:0X00000001
+event:0X123 mmcr0:0X00000000 mmcr1:0X820C000DC2CA02C8 mmcra:0X00000001
+event:0X124 mmcr0:0X00000000 mmcr1:0X820C000DC2CA02C8 mmcra:0X00000001
+event:0X125 mmcr0:0X00000000 mmcr1:0X820C000DC2CA02C8 mmcra:0X00000001
+
+#Group 19 pm_lsu_reject5, LSU misc reject and flush events
+event:0X130 mmcr0:0X00000000 mmcr1:0X420C000C10208A8E mmcra:0X00000000
+event:0X131 mmcr0:0X00000000 mmcr1:0X420C000C10208A8E mmcra:0X00000000
+event:0X132 mmcr0:0X00000000 mmcr1:0X420C000C10208A8E mmcra:0X00000000
+event:0X133 mmcr0:0X00000000 mmcr1:0X420C000C10208A8E mmcra:0X00000000
+event:0X134 mmcr0:0X00000000 mmcr1:0X420C000C10208A8E mmcra:0X00000000
+event:0X135 mmcr0:0X00000000 mmcr1:0X420C000C10208A8E mmcra:0X00000000
+
+#Group 20 pm_flush1, Misc flush events
+event:0X140 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X141 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X142 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X143 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X144 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+event:0X145 mmcr0:0X00000000 mmcr1:0XC0F000020210C68E mmcra:0X00000001
+
+#Group 21 pm_flush2, Flushes due to scoreboard and sync
+event:0X150 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X151 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X152 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X153 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X154 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+event:0X155 mmcr0:0X00000000 mmcr1:0XC08000038002C4C2 mmcra:0X00000001
+
+#Group 22 pm_lsu_flush_srq_lrq, LSU flush by SRQ and LRQ events
+event:0X160 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X161 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X162 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X163 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X164 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+event:0X165 mmcr0:0X00000000 mmcr1:0X40C000002020028A mmcra:0X00000001
+
+#Group 23 pm_lsu_flush_lrq, LSU0/1 flush due to LRQ
+event:0X170 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X171 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X172 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X173 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X174 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+event:0X175 mmcr0:0X00000000 mmcr1:0X40C00000848C8A02 mmcra:0X00000001
+
+#Group 24 pm_lsu_flush_srq, LSU0/1 flush due to SRQ
+event:0X180 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X181 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X182 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X183 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X184 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+event:0X185 mmcr0:0X00000000 mmcr1:0X40C00000868E028A mmcra:0X00000001
+
+#Group 25 pm_lsu_flush_unaligned, LSU flush due to unaligned data
+event:0X190 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X191 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X192 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X193 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X194 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+event:0X195 mmcr0:0X00000000 mmcr1:0X80C000021010C802 mmcra:0X00000001
+
+#Group 26 pm_lsu_flush_uld, LSU0/1 flush due to unaligned load
+event:0X1A0 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1A1 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1A2 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1A3 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1A4 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+event:0X1A5 mmcr0:0X00000000 mmcr1:0X40C0000080888A02 mmcra:0X00000001
+
+#Group 27 pm_lsu_flush_ust, LSU0/1 flush due to unaligned store
+event:0X1B0 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1B1 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1B2 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1B3 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1B4 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+event:0X1B5 mmcr0:0X00000000 mmcr1:0X40C00000828A028A mmcra:0X00000001
+
+#Group 28 pm_lsu_flush_full, LSU flush due to LRQ/SRQ full
+event:0X1C0 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1C1 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1C2 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1C3 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1C4 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+event:0X1C5 mmcr0:0X00000000 mmcr1:0XC0200009CE0210C0 mmcra:0X00000001
+
+#Group 29 pm_lsu_stall1, LSU Stalls
+event:0X1D0 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1D1 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1D2 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1D3 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1D4 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+event:0X1D5 mmcr0:0X00000000 mmcr1:0X4000000028300234 mmcra:0X00000001
+
+#Group 30 pm_lsu_stall2, LSU Stalls
+event:0X1E0 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1E1 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1E2 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1E3 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1E4 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+event:0X1E5 mmcr0:0X00000000 mmcr1:0X4000000002341E36 mmcra:0X00000001
+
+#Group 31 pm_fxu_stall, FXU Stalls
+event:0X1F0 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X1F1 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X1F2 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X1F3 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X1F4 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+event:0X1F5 mmcr0:0X00000000 mmcr1:0X4000000822320232 mmcra:0X00000001
+
+#Group 32 pm_fpu_stall, FPU Stalls
+event:0X200 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X201 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X202 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X203 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X204 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+event:0X205 mmcr0:0X00000000 mmcr1:0X4000000020360230 mmcra:0X00000001
+
+#Group 33 pm_queue_full, BRQ LRQ LMQ queue full
+event:0X210 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X211 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X212 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X213 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X214 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+event:0X215 mmcr0:0X00000000 mmcr1:0X400B0009CE8A84CE mmcra:0X00000000
+
+#Group 34 pm_issueq_full, FPU FX full
+event:0X220 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X221 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X222 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X223 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X224 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+event:0X225 mmcr0:0X00000000 mmcr1:0X40000000868E8088 mmcra:0X00000000
+
+#Group 35 pm_mapper_full1, CR CTR GPR mapper full
+event:0X230 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X231 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X232 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X233 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X234 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+event:0X235 mmcr0:0X00000000 mmcr1:0X40000002888CCA82 mmcra:0X00000000
+
+#Group 36 pm_mapper_full2, FPR XER mapper full
+event:0X240 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X241 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X242 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X243 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X244 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+event:0X245 mmcr0:0X00000000 mmcr1:0X4103000282843602 mmcra:0X00000001
+
+#Group 37 pm_misc_load, Non-cachable loads and stcx events
+event:0X250 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X251 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X252 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X253 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X254 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+event:0X255 mmcr0:0X00000000 mmcr1:0X0438000CC2CA828A mmcra:0X00000001
+
+#Group 38 pm_ic_demand, ICache demand from BR redirect
+event:0X260 mmcr0:0X00000000 mmcr1:0X800C000FC6CEC0C2 mmcra:0X00000000
+event:0X261 mmcr0:0X00000000 mmcr1:0X800C000FC6CEC0C2 mmcra:0X00000000
+event:0X262 mmcr0:0X00000000 mmcr1:0X800C000FC6CEC0C2 mmcra:0X00000000
+event:0X263 mmcr0:0X00000000 mmcr1:0X800C000FC6CEC0C2 mmcra:0X00000000
+event:0X264 mmcr0:0X00000000 mmcr1:0X800C000FC6CEC0C2 mmcra:0X00000000
+event:0X265 mmcr0:0X00000000 mmcr1:0X800C000FC6CEC0C2 mmcra:0X00000000
+
+#Group 39 pm_ic_pref, ICache prefetch
+event:0X270 mmcr0:0X00000000 mmcr1:0X8000000CCECC8E1A mmcra:0X00000000
+event:0X271 mmcr0:0X00000000 mmcr1:0X8000000CCECC8E1A mmcra:0X00000000
+event:0X272 mmcr0:0X00000000 mmcr1:0X8000000CCECC8E1A mmcra:0X00000000
+event:0X273 mmcr0:0X00000000 mmcr1:0X8000000CCECC8E1A mmcra:0X00000000
+event:0X274 mmcr0:0X00000000 mmcr1:0X8000000CCECC8E1A mmcra:0X00000000
+event:0X275 mmcr0:0X00000000 mmcr1:0X8000000CCECC8E1A mmcra:0X00000000
+
+#Group 40 pm_ic_miss, ICache misses
+event:0X280 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X281 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X282 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X283 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X284 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+event:0X285 mmcr0:0X00000000 mmcr1:0X4003000E32CEC802 mmcra:0X00000001
+
+#Group 41 pm_branch_miss, Branch mispredict, TLB and SLB misses
+event:0X290 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X291 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X292 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X293 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X294 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+event:0X295 mmcr0:0X00000000 mmcr1:0X808000031010CACC mmcra:0X00000000
+
+#Group 42 pm_branch1, Branch operations
+event:0X2A0 mmcr0:0X00000000 mmcr1:0X800000030E0E0E0E mmcra:0X00000000
+event:0X2A1 mmcr0:0X00000000 mmcr1:0X800000030E0E0E0E mmcra:0X00000000
+event:0X2A2 mmcr0:0X00000000 mmcr1:0X800000030E0E0E0E mmcra:0X00000000
+event:0X2A3 mmcr0:0X00000000 mmcr1:0X800000030E0E0E0E mmcra:0X00000000
+event:0X2A4 mmcr0:0X00000000 mmcr1:0X800000030E0E0E0E mmcra:0X00000000
+event:0X2A5 mmcr0:0X00000000 mmcr1:0X800000030E0E0E0E mmcra:0X00000000
+
+#Group 43 pm_branch2, Branch operations
+event:0X2B0 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2B1 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2B2 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2B3 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2B4 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+event:0X2B5 mmcr0:0X00000000 mmcr1:0X4000000CCACC8C02 mmcra:0X00000001
+
+#Group 44 pm_L1_tlbmiss, L1 load and TLB misses
+event:0X2C0 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2C1 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2C2 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2C3 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2C4 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+event:0X2C5 mmcr0:0X00000000 mmcr1:0X00B000008E881020 mmcra:0X00000000
+
+#Group 45 pm_L1_DERAT_miss, L1 store and DERAT misses
+event:0X2D0 mmcr0:0X00000000 mmcr1:0X00B300000E202086 mmcra:0X00000000
+event:0X2D1 mmcr0:0X00000000 mmcr1:0X00B300000E202086 mmcra:0X00000000
+event:0X2D2 mmcr0:0X00000000 mmcr1:0X00B300000E202086 mmcra:0X00000000
+event:0X2D3 mmcr0:0X00000000 mmcr1:0X00B300000E202086 mmcra:0X00000000
+event:0X2D4 mmcr0:0X00000000 mmcr1:0X00B300000E202086 mmcra:0X00000000
+event:0X2D5 mmcr0:0X00000000 mmcr1:0X00B300000E202086 mmcra:0X00000000
+
+#Group 46 pm_L1_slbmiss, L1 load and SLB misses
+event:0X2E0 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2E1 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2E2 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2E3 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2E4 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+event:0X2E5 mmcr0:0X00000000 mmcr1:0X00B000008A82848C mmcra:0X00000000
+
+#Group 47 pm_L1_dtlbmiss_4K, L1 load references and 4K Data TLB references and misses
+event:0X2F0 mmcr0:0X00000000 mmcr1:0X08F0000084808088 mmcra:0X00000000
+event:0X2F1 mmcr0:0X00000000 mmcr1:0X08F0000084808088 mmcra:0X00000000
+event:0X2F2 mmcr0:0X00000000 mmcr1:0X08F0000084808088 mmcra:0X00000000
+event:0X2F3 mmcr0:0X00000000 mmcr1:0X08F0000084808088 mmcra:0X00000000
+event:0X2F4 mmcr0:0X00000000 mmcr1:0X08F0000084808088 mmcra:0X00000000
+event:0X2F5 mmcr0:0X00000000 mmcr1:0X08F0000084808088 mmcra:0X00000000
+
+#Group 48 pm_L1_dtlbmiss_16M, L1 store references and 16M Data TLB references and misses
+event:0X300 mmcr0:0X00000000 mmcr1:0X08F000008C88828A mmcra:0X00000000
+event:0X301 mmcr0:0X00000000 mmcr1:0X08F000008C88828A mmcra:0X00000000
+event:0X302 mmcr0:0X00000000 mmcr1:0X08F000008C88828A mmcra:0X00000000
+event:0X303 mmcr0:0X00000000 mmcr1:0X08F000008C88828A mmcra:0X00000000
+event:0X304 mmcr0:0X00000000 mmcr1:0X08F000008C88828A mmcra:0X00000000
+event:0X305 mmcr0:0X00000000 mmcr1:0X08F000008C88828A mmcra:0X00000000
+
+#Group 49 pm_dsource1, L3 cache and memory data access
+event:0X310 mmcr0:0X00000000 mmcr1:0X400300001C0E8E02 mmcra:0X00000001
+event:0X311 mmcr0:0X00000000 mmcr1:0X400300001C0E8E02 mmcra:0X00000001
+event:0X312 mmcr0:0X00000000 mmcr1:0X400300001C0E8E02 mmcra:0X00000001
+event:0X313 mmcr0:0X00000000 mmcr1:0X400300001C0E8E02 mmcra:0X00000001
+event:0X314 mmcr0:0X00000000 mmcr1:0X400300001C0E8E02 mmcra:0X00000001
+event:0X315 mmcr0:0X00000000 mmcr1:0X400300001C0E8E02 mmcra:0X00000001
+
+#Group 50 pm_dsource2, L3 cache and memory data access
+event:0X320 mmcr0:0X00000000 mmcr1:0X000300031C0E360E mmcra:0X00000000
+event:0X321 mmcr0:0X00000000 mmcr1:0X000300031C0E360E mmcra:0X00000000
+event:0X322 mmcr0:0X00000000 mmcr1:0X000300031C0E360E mmcra:0X00000000
+event:0X323 mmcr0:0X00000000 mmcr1:0X000300031C0E360E mmcra:0X00000000
+event:0X324 mmcr0:0X00000000 mmcr1:0X000300031C0E360E mmcra:0X00000000
+event:0X325 mmcr0:0X00000000 mmcr1:0X000300031C0E360E mmcra:0X00000000
+
+#Group 51 pm_dsource_L2, L2 cache data access
+event:0X330 mmcr0:0X00000000 mmcr1:0X000300032E2E2E2E mmcra:0X00000000
+event:0X331 mmcr0:0X00000000 mmcr1:0X000300032E2E2E2E mmcra:0X00000000
+event:0X332 mmcr0:0X00000000 mmcr1:0X000300032E2E2E2E mmcra:0X00000000
+event:0X333 mmcr0:0X00000000 mmcr1:0X000300032E2E2E2E mmcra:0X00000000
+event:0X334 mmcr0:0X00000000 mmcr1:0X000300032E2E2E2E mmcra:0X00000000
+event:0X335 mmcr0:0X00000000 mmcr1:0X000300032E2E2E2E mmcra:0X00000000
+
+#Group 52 pm_dsource_L3, L3 cache data access
+event:0X340 mmcr0:0X00000000 mmcr1:0X000300033C3C3C3C mmcra:0X00000000
+event:0X341 mmcr0:0X00000000 mmcr1:0X000300033C3C3C3C mmcra:0X00000000
+event:0X342 mmcr0:0X00000000 mmcr1:0X000300033C3C3C3C mmcra:0X00000000
+event:0X343 mmcr0:0X00000000 mmcr1:0X000300033C3C3C3C mmcra:0X00000000
+event:0X344 mmcr0:0X00000000 mmcr1:0X000300033C3C3C3C mmcra:0X00000000
+event:0X345 mmcr0:0X00000000 mmcr1:0X000300033C3C3C3C mmcra:0X00000000
+
+#Group 53 pm_isource1, Instruction source information
+event:0X350 mmcr0:0X00000000 mmcr1:0X8000000C1A1A1A0C mmcra:0X00000000
+event:0X351 mmcr0:0X00000000 mmcr1:0X8000000C1A1A1A0C mmcra:0X00000000
+event:0X352 mmcr0:0X00000000 mmcr1:0X8000000C1A1A1A0C mmcra:0X00000000
+event:0X353 mmcr0:0X00000000 mmcr1:0X8000000C1A1A1A0C mmcra:0X00000000
+event:0X354 mmcr0:0X00000000 mmcr1:0X8000000C1A1A1A0C mmcra:0X00000000
+event:0X355 mmcr0:0X00000000 mmcr1:0X8000000C1A1A1A0C mmcra:0X00000000
+
+#Group 54 pm_isource2, Instruction source information
+event:0X360 mmcr0:0X00000000 mmcr1:0X8000000C0C0C021A mmcra:0X00000001
+event:0X361 mmcr0:0X00000000 mmcr1:0X8000000C0C0C021A mmcra:0X00000001
+event:0X362 mmcr0:0X00000000 mmcr1:0X8000000C0C0C021A mmcra:0X00000001
+event:0X363 mmcr0:0X00000000 mmcr1:0X8000000C0C0C021A mmcra:0X00000001
+event:0X364 mmcr0:0X00000000 mmcr1:0X8000000C0C0C021A mmcra:0X00000001
+event:0X365 mmcr0:0X00000000 mmcr1:0X8000000C0C0C021A mmcra:0X00000001
+
+#Group 55 pm_isource_L2, L2 instruction source information
+event:0X370 mmcr0:0X00000000 mmcr1:0X8000000C2C2C2C2C mmcra:0X00000000
+event:0X371 mmcr0:0X00000000 mmcr1:0X8000000C2C2C2C2C mmcra:0X00000000
+event:0X372 mmcr0:0X00000000 mmcr1:0X8000000C2C2C2C2C mmcra:0X00000000
+event:0X373 mmcr0:0X00000000 mmcr1:0X8000000C2C2C2C2C mmcra:0X00000000
+event:0X374 mmcr0:0X00000000 mmcr1:0X8000000C2C2C2C2C mmcra:0X00000000
+event:0X375 mmcr0:0X00000000 mmcr1:0X8000000C2C2C2C2C mmcra:0X00000000
+
+#Group 56 pm_isource_L3, L3 instruction source information
+event:0X380 mmcr0:0X00000000 mmcr1:0X8000000C3A3A3A3A mmcra:0X00000000
+event:0X381 mmcr0:0X00000000 mmcr1:0X8000000C3A3A3A3A mmcra:0X00000000
+event:0X382 mmcr0:0X00000000 mmcr1:0X8000000C3A3A3A3A mmcra:0X00000000
+event:0X383 mmcr0:0X00000000 mmcr1:0X8000000C3A3A3A3A mmcra:0X00000000
+event:0X384 mmcr0:0X00000000 mmcr1:0X8000000C3A3A3A3A mmcra:0X00000000
+event:0X385 mmcr0:0X00000000 mmcr1:0X8000000C3A3A3A3A mmcra:0X00000000
+
+#Group 57 pm_pteg_source1, PTEG source information
+event:0X390 mmcr0:0X00000000 mmcr1:0X000200032E2E2E2E mmcra:0X00000000
+event:0X391 mmcr0:0X00000000 mmcr1:0X000200032E2E2E2E mmcra:0X00000000
+event:0X392 mmcr0:0X00000000 mmcr1:0X000200032E2E2E2E mmcra:0X00000000
+event:0X393 mmcr0:0X00000000 mmcr1:0X000200032E2E2E2E mmcra:0X00000000
+event:0X394 mmcr0:0X00000000 mmcr1:0X000200032E2E2E2E mmcra:0X00000000
+event:0X395 mmcr0:0X00000000 mmcr1:0X000200032E2E2E2E mmcra:0X00000000
+
+#Group 58 pm_pteg_source2, PTEG source information
+event:0X3A0 mmcr0:0X00000000 mmcr1:0X000200033C3C3C3C mmcra:0X00000000
+event:0X3A1 mmcr0:0X00000000 mmcr1:0X000200033C3C3C3C mmcra:0X00000000
+event:0X3A2 mmcr0:0X00000000 mmcr1:0X000200033C3C3C3C mmcra:0X00000000
+event:0X3A3 mmcr0:0X00000000 mmcr1:0X000200033C3C3C3C mmcra:0X00000000
+event:0X3A4 mmcr0:0X00000000 mmcr1:0X000200033C3C3C3C mmcra:0X00000000
+event:0X3A5 mmcr0:0X00000000 mmcr1:0X000200033C3C3C3C mmcra:0X00000000
+
+#Group 59 pm_pteg_source3, PTEG source information
+event:0X3B0 mmcr0:0X00000000 mmcr1:0X000200030E0E360E mmcra:0X00000000
+event:0X3B1 mmcr0:0X00000000 mmcr1:0X000200030E0E360E mmcra:0X00000000
+event:0X3B2 mmcr0:0X00000000 mmcr1:0X000200030E0E360E mmcra:0X00000000
+event:0X3B3 mmcr0:0X00000000 mmcr1:0X000200030E0E360E mmcra:0X00000000
+event:0X3B4 mmcr0:0X00000000 mmcr1:0X000200030E0E360E mmcra:0X00000000
+event:0X3B5 mmcr0:0X00000000 mmcr1:0X000200030E0E360E mmcra:0X00000000
+
+#Group 60 pm_pteg_source4, L3 PTEG and group disptach events
+event:0X3C0 mmcr0:0X00000000 mmcr1:0X003200001C04048E mmcra:0X00000000
+event:0X3C1 mmcr0:0X00000000 mmcr1:0X003200001C04048E mmcra:0X00000000
+event:0X3C2 mmcr0:0X00000000 mmcr1:0X003200001C04048E mmcra:0X00000000
+event:0X3C3 mmcr0:0X00000000 mmcr1:0X003200001C04048E mmcra:0X00000000
+event:0X3C4 mmcr0:0X00000000 mmcr1:0X003200001C04048E mmcra:0X00000000
+event:0X3C5 mmcr0:0X00000000 mmcr1:0X003200001C04048E mmcra:0X00000000
+
+#Group 61 pm_L2SA_ld, L2 slice A load events
+event:0X3D0 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X3D1 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X3D2 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X3D3 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X3D4 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+event:0X3D5 mmcr0:0X00000000 mmcr1:0X3055400580C080C0 mmcra:0X00000000
+
+#Group 62 pm_L2SA_st, L2 slice A store events
+event:0X3E0 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X3E1 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X3E2 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X3E3 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X3E4 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+event:0X3E5 mmcr0:0X00000000 mmcr1:0X3055800580C080C0 mmcra:0X00000000
+
+#Group 63 pm_L2SA_st2, L2 slice A store events
+event:0X3F0 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X3F1 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X3F2 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X3F3 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X3F4 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+event:0X3F5 mmcr0:0X00000000 mmcr1:0X3055C00580C080C0 mmcra:0X00000000
+
+#Group 64 pm_L2SB_ld, L2 slice B load events
+event:0X400 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X401 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X402 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X403 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X404 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+event:0X405 mmcr0:0X00000000 mmcr1:0X3055400582C282C2 mmcra:0X00000000
+
+#Group 65 pm_L2SB_st, L2 slice B store events
+event:0X410 mmcr0:0X00000000 mmcr1:0X3055800582C282C2 mmcra:0X00000000
+event:0X411 mmcr0:0X00000000 mmcr1:0X3055800582C282C2 mmcra:0X00000000
+event:0X412 mmcr0:0X00000000 mmcr1:0X3055800582C282C2 mmcra:0X00000000
+event:0X413 mmcr0:0X00000000 mmcr1:0X3055800582C282C2 mmcra:0X00000000
+event:0X414 mmcr0:0X00000000 mmcr1:0X3055800582C282C2 mmcra:0X00000000
+event:0X415 mmcr0:0X00000000 mmcr1:0X3055800582C282C2 mmcra:0X00000000
+
+#Group 66 pm_L2SB_st2, L2 slice B store events
+event:0X420 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X421 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X422 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X423 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X424 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+event:0X425 mmcr0:0X00000000 mmcr1:0X3055C00582C282C2 mmcra:0X00000000
+
+#Group 67 pm_L2SB_ld, L2 slice C load events
+event:0X430 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X431 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X432 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X433 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X434 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+event:0X435 mmcr0:0X00000000 mmcr1:0X3055400584C484C4 mmcra:0X00000000
+
+#Group 68 pm_L2SB_st, L2 slice C store events
+event:0X440 mmcr0:0X00000000 mmcr1:0X3055800584C484C4 mmcra:0X00000000
+event:0X441 mmcr0:0X00000000 mmcr1:0X3055800584C484C4 mmcra:0X00000000
+event:0X442 mmcr0:0X00000000 mmcr1:0X3055800584C484C4 mmcra:0X00000000
+event:0X443 mmcr0:0X00000000 mmcr1:0X3055800584C484C4 mmcra:0X00000000
+event:0X444 mmcr0:0X00000000 mmcr1:0X3055800584C484C4 mmcra:0X00000000
+event:0X445 mmcr0:0X00000000 mmcr1:0X3055800584C484C4 mmcra:0X00000000
+
+#Group 69 pm_L2SB_st2, L2 slice C store events
+event:0X450 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X451 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X452 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X453 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X454 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+event:0X455 mmcr0:0X00000000 mmcr1:0X3055C00584C484C4 mmcra:0X00000000
+
+#Group 70 pm_L3SA_trans, L3 slice A state transistions
+event:0X460 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X461 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X462 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X463 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X464 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+event:0X465 mmcr0:0X00000000 mmcr1:0X3015000AC602C686 mmcra:0X00000001
+
+#Group 71 pm_L3SB_trans, L3 slice B state transistions
+event:0X470 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X471 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X472 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X473 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X474 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+event:0X475 mmcr0:0X00000000 mmcr1:0X3015000602C8C888 mmcra:0X00000001
+
+#Group 72 pm_L3SC_trans, L3 slice C state transistions
+event:0X480 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X481 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X482 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X483 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X484 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+event:0X485 mmcr0:0X00000000 mmcr1:0X3015000602CACA8A mmcra:0X00000001
+
+#Group 73 pm_L2SA_trans, L2 slice A state transistions
+event:0X490 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X491 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X492 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X493 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X494 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+event:0X495 mmcr0:0X00000000 mmcr1:0X3055000AC080C080 mmcra:0X00000000
+
+#Group 74 pm_L2SB_trans, L2 slice B state transistions
+event:0X4A0 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4A1 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4A2 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4A3 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4A4 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+event:0X4A5 mmcr0:0X00000000 mmcr1:0X3055000AC282C282 mmcra:0X00000000
+
+#Group 75 pm_L2SC_trans, L2 slice C state transistions
+event:0X4B0 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4B1 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4B2 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4B3 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4B4 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+event:0X4B5 mmcr0:0X00000000 mmcr1:0X3055000AC484C484 mmcra:0X00000000
+
+#Group 76 pm_L3SAB_retry, L3 slice A/B snoop retry and all CI/CO busy
+event:0X4C0 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4C1 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4C2 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4C3 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4C4 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+event:0X4C5 mmcr0:0X00000000 mmcr1:0X3005100FC6C8C6C8 mmcra:0X00000000
+
+#Group 77 pm_L3SAB_hit, L3 slice A/B hit and reference
+event:0X4D0 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X4D1 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X4D2 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X4D3 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X4D4 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+event:0X4D5 mmcr0:0X00000000 mmcr1:0X3050100086888688 mmcra:0X00000000
+
+#Group 78 pm_L3SC_retry_hit, L3 slice C hit & snoop retry
+event:0X4E0 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X4E1 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X4E2 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X4E3 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X4E4 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+event:0X4E5 mmcr0:0X00000000 mmcr1:0X3055100ACA8ACA8A mmcra:0X00000000
+
+#Group 79 pm_fpu1, Floating Point events
+event:0X4F0 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X4F1 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X4F2 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X4F3 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X4F4 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+event:0X4F5 mmcr0:0X00000000 mmcr1:0X0000000010101020 mmcra:0X00000000
+
+#Group 80 pm_fpu2, Floating Point events
+event:0X500 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X501 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X502 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X503 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X504 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+event:0X505 mmcr0:0X00000000 mmcr1:0X0000000020202010 mmcra:0X00000000
+
+#Group 81 pm_fpu3, Floating point events
+event:0X510 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X511 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X512 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X513 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X514 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+event:0X515 mmcr0:0X00000000 mmcr1:0X0000000C1010868E mmcra:0X00000000
+
+#Group 82 pm_fpu4, Floating point events
+event:0X520 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X521 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X522 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X523 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X524 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+event:0X525 mmcr0:0X00000000 mmcr1:0X0430000C20200220 mmcra:0X00000001
+
+#Group 83 pm_fpu5, Floating point events by unit
+event:0X530 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X531 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X532 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X533 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X534 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+event:0X535 mmcr0:0X00000000 mmcr1:0X00000000848C848C mmcra:0X00000000
+
+#Group 84 pm_fpu6, Floating point events by unit
+event:0X540 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X541 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X542 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X543 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X544 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+event:0X545 mmcr0:0X00000000 mmcr1:0X0000000CC0C88088 mmcra:0X00000000
+
+#Group 85 pm_fpu7, Floating point events by unit
+event:0X550 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X551 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X552 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X553 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X554 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+event:0X555 mmcr0:0X00000000 mmcr1:0X000000008088828A mmcra:0X00000000
+
+#Group 86 pm_fpu8, Floating point events by unit
+event:0X560 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X561 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X562 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X563 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X564 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+event:0X565 mmcr0:0X00000000 mmcr1:0X0000000DC2CA02C0 mmcra:0X00000001
+
+#Group 87 pm_fpu9, Floating point events by unit
+event:0X570 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X571 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X572 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X573 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X574 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+event:0X575 mmcr0:0X00000000 mmcr1:0X0430000CC6CE8088 mmcra:0X00000000
+
+#Group 88 pm_fpu10, Floating point events by unit
+event:0X580 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X581 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X582 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X583 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X584 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+event:0X585 mmcr0:0X00000000 mmcr1:0X00000000828A028A mmcra:0X00000001
+
+#Group 89 pm_fpu11, Floating point events by unit
+event:0X590 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X591 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X592 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X593 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X594 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+event:0X595 mmcr0:0X00000000 mmcr1:0X00000000868E8602 mmcra:0X00000001
+
+#Group 90 pm_fpu12, Floating point events by unit
+event:0X5A0 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5A1 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5A2 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5A3 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5A4 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+event:0X5A5 mmcr0:0X00000000 mmcr1:0X0430000CC4CC8002 mmcra:0X00000001
+
+#Group 91 pm_fxu1, Fixed Point events
+event:0X5B0 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5B1 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5B2 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5B3 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5B4 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+event:0X5B5 mmcr0:0X00000000 mmcr1:0X0000000024242424 mmcra:0X00000000
+
+#Group 92 pm_fxu2, Fixed Point events
+event:0X5C0 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5C1 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5C2 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5C3 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5C4 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+event:0X5C5 mmcr0:0X00000000 mmcr1:0X4000000604221020 mmcra:0X00000001
+
+#Group 93 pm_fxu3, Fixed Point events
+event:0X5D0 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X5D1 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X5D2 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X5D3 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X5D4 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+event:0X5D5 mmcr0:0X00000000 mmcr1:0X404000038688C4CC mmcra:0X00000000
+
+#Group 94 pm_smt_priorities1, Thread priority events
+event:0X5E0 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X5E1 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X5E2 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X5E3 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X5E4 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+event:0X5E5 mmcr0:0X00000000 mmcr1:0X0005000FC6CCC6C8 mmcra:0X00000000
+
+#Group 95 pm_smt_priorities2, Thread priority events
+event:0X5F0 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X5F1 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X5F2 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X5F3 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X5F4 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+event:0X5F5 mmcr0:0X00000000 mmcr1:0X0005000FC4CACACC mmcra:0X00000000
+
+#Group 96 pm_smt_priorities3, Thread priority events
+event:0X600 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X601 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X602 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X603 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X604 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+event:0X605 mmcr0:0X00000000 mmcr1:0X0005000FC2C8C4C2 mmcra:0X00000000
+
+#Group 97 pm_smt_priorities4, Thread priority events
+event:0X610 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X611 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X612 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X613 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X614 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+event:0X615 mmcr0:0X00000000 mmcr1:0X0005000AC016C002 mmcra:0X00000001
+
+#Group 98 pm_smt_both, Thread common events
+event:0X620 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X621 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X622 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X623 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X624 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+event:0X625 mmcr0:0X00000000 mmcr1:0X0010000016260208 mmcra:0X00000001
+
+#Group 99 pm_smt_selection, Thread selection
+event:0X630 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X631 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X632 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X633 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X634 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+event:0X635 mmcr0:0X00000000 mmcr1:0X0090000086028082 mmcra:0X00000001
+
+#Group 100 pm_smt_selectover1, Thread selection overide
+event:0X640 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X641 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X642 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X643 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X644 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+event:0X645 mmcr0:0X00000000 mmcr1:0X0050000002808488 mmcra:0X00000001
+
+#Group 101 pm_smt_selectover2, Thread selection overide
+event:0X650 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X651 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X652 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X653 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X654 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+event:0X655 mmcr0:0X00000000 mmcr1:0X00100000021E8A86 mmcra:0X00000001
+
+#Group 102 pm_fabric1, Fabric events
+event:0X660 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X661 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X662 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X663 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X664 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+event:0X665 mmcr0:0X00000000 mmcr1:0X305500058ECE8ECE mmcra:0X00000000
+
+#Group 103 pm_fabric2, Fabric data movement
+event:0X670 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X671 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X672 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X673 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X674 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+event:0X675 mmcr0:0X00000000 mmcr1:0X305500858ECE8ECE mmcra:0X00000000
+
+#Group 104 pm_fabric3, Fabric data movement
+event:0X680 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X681 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X682 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X683 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X684 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+event:0X685 mmcr0:0X00000000 mmcr1:0X305501858ECE8ECE mmcra:0X00000000
+
+#Group 105 pm_fabric4, Fabric data movement
+event:0X690 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X691 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X692 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X693 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X694 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+event:0X695 mmcr0:0X00000000 mmcr1:0X705401068ECEC68E mmcra:0X00000000
+
+#Group 106 pm_snoop1, Snoop retry
+event:0X6A0 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6A1 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6A2 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6A3 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6A4 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+event:0X6A5 mmcr0:0X00000000 mmcr1:0X305500058CCC8CCC mmcra:0X00000000
+
+#Group 107 pm_snoop2, Snoop read retry
+event:0X6B0 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6B1 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6B2 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6B3 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6B4 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+event:0X6B5 mmcr0:0X00000000 mmcr1:0X30540A048CCC8C02 mmcra:0X00000001
+
+#Group 108 pm_snoop3, Snoop write retry
+event:0X6C0 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6C1 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6C2 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6C3 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6C4 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+event:0X6C5 mmcr0:0X00000000 mmcr1:0X30550C058CCC8CCC mmcra:0X00000000
+
+#Group 109 pm_snoop4, Snoop partial write retry
+event:0X6D0 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X6D1 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X6D2 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X6D3 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X6D4 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+event:0X6D5 mmcr0:0X00000000 mmcr1:0X30550E058CCC8CCC mmcra:0X00000000
+
+#Group 110 pm_mem_rq, Memory read queue dispatch
+event:0X6E0 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X6E1 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X6E2 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X6E3 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X6E4 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+event:0X6E5 mmcr0:0X00000000 mmcr1:0X705402058CCC8CCE mmcra:0X00000000
+
+#Group 111 pm_mem_read, Memory read complete and cancel
+event:0X6F0 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X6F1 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X6F2 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X6F3 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X6F4 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+event:0X6F5 mmcr0:0X00000000 mmcr1:0X305404048CCC8C06 mmcra:0X00000000
+
+#Group 112 pm_mem_wq, Memory write queue dispatch
+event:0X700 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X701 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X702 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X703 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X704 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+event:0X705 mmcr0:0X00000000 mmcr1:0X305506058CCC8CCC mmcra:0X00000000
+
+#Group 113 pm_mem_pwq, Memory partial write queue
+event:0X710 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X711 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X712 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X713 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X714 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+event:0X715 mmcr0:0X00000000 mmcr1:0X305508058CCC8CCC mmcra:0X00000000
+
+#Group 114 pm_threshold, Thresholding
+event:0X720 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X721 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X722 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X723 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X724 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+event:0X725 mmcr0:0X00000000 mmcr1:0X0008000404C41628 mmcra:0X00000001
+
+#Group 115 pm_mrk_grp1, Marked group events
+event:0X730 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X731 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X732 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X733 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X734 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+event:0X735 mmcr0:0X00000000 mmcr1:0X0008000404C60A26 mmcra:0X00000001
+
+#Group 116 pm_mrk_grp2, Marked group events
+event:0X740 mmcr0:0X00000000 mmcr1:0X410300022A0AC822 mmcra:0X00000001
+event:0X741 mmcr0:0X00000000 mmcr1:0X410300022A0AC822 mmcra:0X00000001
+event:0X742 mmcr0:0X00000000 mmcr1:0X410300022A0AC822 mmcra:0X00000001
+event:0X743 mmcr0:0X00000000 mmcr1:0X410300022A0AC822 mmcra:0X00000001
+event:0X744 mmcr0:0X00000000 mmcr1:0X410300022A0AC822 mmcra:0X00000001
+event:0X745 mmcr0:0X00000000 mmcr1:0X410300022A0AC822 mmcra:0X00000001
+
+#Group 117 pm_mrk_dsource1, Marked data from
+event:0X750 mmcr0:0X00000000 mmcr1:0X010B00030E404444 mmcra:0X00000001
+event:0X751 mmcr0:0X00000000 mmcr1:0X010B00030E404444 mmcra:0X00000001
+event:0X752 mmcr0:0X00000000 mmcr1:0X010B00030E404444 mmcra:0X00000001
+event:0X753 mmcr0:0X00000000 mmcr1:0X010B00030E404444 mmcra:0X00000001
+event:0X754 mmcr0:0X00000000 mmcr1:0X010B00030E404444 mmcra:0X00000001
+event:0X755 mmcr0:0X00000000 mmcr1:0X010B00030E404444 mmcra:0X00000001
+
+#Group 118 pm_mrk_dsource2, Marked data from
+event:0X760 mmcr0:0X00000000 mmcr1:0X010B00002E440210 mmcra:0X00000001
+event:0X761 mmcr0:0X00000000 mmcr1:0X010B00002E440210 mmcra:0X00000001
+event:0X762 mmcr0:0X00000000 mmcr1:0X010B00002E440210 mmcra:0X00000001
+event:0X763 mmcr0:0X00000000 mmcr1:0X010B00002E440210 mmcra:0X00000001
+event:0X764 mmcr0:0X00000000 mmcr1:0X010B00002E440210 mmcra:0X00000001
+event:0X765 mmcr0:0X00000000 mmcr1:0X010B00002E440210 mmcra:0X00000001
+
+#Group 119 pm_mrk_dsource3, Marked data from
+event:0X770 mmcr0:0X00000000 mmcr1:0X010B00031C484C4C mmcra:0X00000001
+event:0X771 mmcr0:0X00000000 mmcr1:0X010B00031C484C4C mmcra:0X00000001
+event:0X772 mmcr0:0X00000000 mmcr1:0X010B00031C484C4C mmcra:0X00000001
+event:0X773 mmcr0:0X00000000 mmcr1:0X010B00031C484C4C mmcra:0X00000001
+event:0X774 mmcr0:0X00000000 mmcr1:0X010B00031C484C4C mmcra:0X00000001
+event:0X775 mmcr0:0X00000000 mmcr1:0X010B00031C484C4C mmcra:0X00000001
+
+#Group 120 pm_mrk_dsource4, Marked data from
+event:0X780 mmcr0:0X00000000 mmcr1:0X010B000342462E42 mmcra:0X00000001
+event:0X781 mmcr0:0X00000000 mmcr1:0X010B000342462E42 mmcra:0X00000001
+event:0X782 mmcr0:0X00000000 mmcr1:0X010B000342462E42 mmcra:0X00000001
+event:0X783 mmcr0:0X00000000 mmcr1:0X010B000342462E42 mmcra:0X00000001
+event:0X784 mmcr0:0X00000000 mmcr1:0X010B000342462E42 mmcra:0X00000001
+event:0X785 mmcr0:0X00000000 mmcr1:0X010B000342462E42 mmcra:0X00000001
+
+#Group 121 pm_mrk_dsource5, Marked data from
+event:0X790 mmcr0:0X00000000 mmcr1:0X010B00033C4C4040 mmcra:0X00000001
+event:0X791 mmcr0:0X00000000 mmcr1:0X010B00033C4C4040 mmcra:0X00000001
+event:0X792 mmcr0:0X00000000 mmcr1:0X010B00033C4C4040 mmcra:0X00000001
+event:0X793 mmcr0:0X00000000 mmcr1:0X010B00033C4C4040 mmcra:0X00000001
+event:0X794 mmcr0:0X00000000 mmcr1:0X010B00033C4C4040 mmcra:0X00000001
+event:0X795 mmcr0:0X00000000 mmcr1:0X010B00033C4C4040 mmcra:0X00000001
+
+#Group 122 pm_mrk_dsource6, Marked data from
+event:0X7A0 mmcr0:0X00000000 mmcr1:0X010B000146460246 mmcra:0X00000001
+event:0X7A1 mmcr0:0X00000000 mmcr1:0X010B000146460246 mmcra:0X00000001
+event:0X7A2 mmcr0:0X00000000 mmcr1:0X010B000146460246 mmcra:0X00000001
+event:0X7A3 mmcr0:0X00000000 mmcr1:0X010B000146460246 mmcra:0X00000001
+event:0X7A4 mmcr0:0X00000000 mmcr1:0X010B000146460246 mmcra:0X00000001
+event:0X7A5 mmcr0:0X00000000 mmcr1:0X010B000146460246 mmcra:0X00000001
+
+#Group 123 pm_mrk_dsource7, Marked data from
+event:0X7B0 mmcr0:0X00000000 mmcr1:0X010B00034E4E3C4E mmcra:0X00000001
+event:0X7B1 mmcr0:0X00000000 mmcr1:0X010B00034E4E3C4E mmcra:0X00000001
+event:0X7B2 mmcr0:0X00000000 mmcr1:0X010B00034E4E3C4E mmcra:0X00000001
+event:0X7B3 mmcr0:0X00000000 mmcr1:0X010B00034E4E3C4E mmcra:0X00000001
+event:0X7B4 mmcr0:0X00000000 mmcr1:0X010B00034E4E3C4E mmcra:0X00000001
+event:0X7B5 mmcr0:0X00000000 mmcr1:0X010B00034E4E3C4E mmcra:0X00000001
+
+#Group 124 pm_mrk_lbmiss, Marked TLB and SLB misses
+event:0X7C0 mmcr0:0X00000000 mmcr1:0X0CF00000828A8C8E mmcra:0X00000001
+event:0X7C1 mmcr0:0X00000000 mmcr1:0X0CF00000828A8C8E mmcra:0X00000001
+event:0X7C2 mmcr0:0X00000000 mmcr1:0X0CF00000828A8C8E mmcra:0X00000001
+event:0X7C3 mmcr0:0X00000000 mmcr1:0X0CF00000828A8C8E mmcra:0X00000001
+event:0X7C4 mmcr0:0X00000000 mmcr1:0X0CF00000828A8C8E mmcra:0X00000001
+event:0X7C5 mmcr0:0X00000000 mmcr1:0X0CF00000828A8C8E mmcra:0X00000001
+
+#Group 125 pm_mrk_lbref, Marked TLB and SLB references
+event:0X7D0 mmcr0:0X00000000 mmcr1:0X0CF00000868E028E mmcra:0X00000001
+event:0X7D1 mmcr0:0X00000000 mmcr1:0X0CF00000868E028E mmcra:0X00000001
+event:0X7D2 mmcr0:0X00000000 mmcr1:0X0CF00000868E028E mmcra:0X00000001
+event:0X7D3 mmcr0:0X00000000 mmcr1:0X0CF00000868E028E mmcra:0X00000001
+event:0X7D4 mmcr0:0X00000000 mmcr1:0X0CF00000868E028E mmcra:0X00000001
+event:0X7D5 mmcr0:0X00000000 mmcr1:0X0CF00000868E028E mmcra:0X00000001
+
+#Group 126 pm_mrk_lsmiss, Marked load and store miss
+event:0X7E0 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X7E1 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X7E2 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X7E3 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X7E4 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+event:0X7E5 mmcr0:0X00000000 mmcr1:0X000800081002060A mmcra:0X00000001
+
+#Group 127 pm_mrk_ulsflush, Mark unaligned load and store flushes
+event:0X7F0 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X7F1 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X7F2 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X7F3 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X7F4 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+event:0X7F5 mmcr0:0X00000000 mmcr1:0X0028000406C62020 mmcra:0X00000001
+
+#Group 128 pm_mrk_misc, Misc marked instructions
+event:0X800 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X801 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X802 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X803 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X804 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+event:0X805 mmcr0:0X00000000 mmcr1:0X00080008CC062816 mmcra:0X00000001
+
+#Group 129 pm_lsref_L1, Load/Store operations and L1 activity
+event:0X810 mmcr0:0X00000000 mmcr1:0X803300040E1A2020 mmcra:0X00000000
+event:0X811 mmcr0:0X00000000 mmcr1:0X803300040E1A2020 mmcra:0X00000000
+event:0X812 mmcr0:0X00000000 mmcr1:0X803300040E1A2020 mmcra:0X00000000
+event:0X813 mmcr0:0X00000000 mmcr1:0X803300040E1A2020 mmcra:0X00000000
+event:0X814 mmcr0:0X00000000 mmcr1:0X803300040E1A2020 mmcra:0X00000000
+event:0X815 mmcr0:0X00000000 mmcr1:0X803300040E1A2020 mmcra:0X00000000
+
+#Group 130 pm_lsref_L2L3, Load/Store operations and L2,L3 activity
+event:0X820 mmcr0:0X00000000 mmcr1:0X003300001C0E2020 mmcra:0X00000000
+event:0X821 mmcr0:0X00000000 mmcr1:0X003300001C0E2020 mmcra:0X00000000
+event:0X822 mmcr0:0X00000000 mmcr1:0X003300001C0E2020 mmcra:0X00000000
+event:0X823 mmcr0:0X00000000 mmcr1:0X003300001C0E2020 mmcra:0X00000000
+event:0X824 mmcr0:0X00000000 mmcr1:0X003300001C0E2020 mmcra:0X00000000
+event:0X825 mmcr0:0X00000000 mmcr1:0X003300001C0E2020 mmcra:0X00000000
+
+#Group 131 pm_lsref_tlbmiss, Load/Store operations and TLB misses
+event:0X830 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X831 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X832 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X833 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X834 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+event:0X835 mmcr0:0X00000000 mmcr1:0X00B0000080882020 mmcra:0X00000000
+
+#Group 132 pm_Dmiss, Data cache misses
+event:0X840 mmcr0:0X00000000 mmcr1:0X003300001C0E1086 mmcra:0X00000000
+event:0X841 mmcr0:0X00000000 mmcr1:0X003300001C0E1086 mmcra:0X00000000
+event:0X842 mmcr0:0X00000000 mmcr1:0X003300001C0E1086 mmcra:0X00000000
+event:0X843 mmcr0:0X00000000 mmcr1:0X003300001C0E1086 mmcra:0X00000000
+event:0X844 mmcr0:0X00000000 mmcr1:0X003300001C0E1086 mmcra:0X00000000
+event:0X845 mmcr0:0X00000000 mmcr1:0X003300001C0E1086 mmcra:0X00000000
+
+#Group 133 pm_prefetchX, Prefetch events
+event:0X850 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X851 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X852 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X853 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X854 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+event:0X855 mmcr0:0X00000000 mmcr1:0X853300061ECCCE86 mmcra:0X00000000
+
+#Group 134 pm_branchX, Branch operations
+event:0X860 mmcr0:0X00000000 mmcr1:0X800000030E0E0EC8 mmcra:0X00000000
+event:0X861 mmcr0:0X00000000 mmcr1:0X800000030E0E0EC8 mmcra:0X00000000
+event:0X862 mmcr0:0X00000000 mmcr1:0X800000030E0E0EC8 mmcra:0X00000000
+event:0X863 mmcr0:0X00000000 mmcr1:0X800000030E0E0EC8 mmcra:0X00000000
+event:0X864 mmcr0:0X00000000 mmcr1:0X800000030E0E0EC8 mmcra:0X00000000
+event:0X865 mmcr0:0X00000000 mmcr1:0X800000030E0E0EC8 mmcra:0X00000000
+
+#Group 135 pm_fpuX1, Floating point events by unit
+event:0X870 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X871 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X872 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X873 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X874 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+event:0X875 mmcr0:0X00000000 mmcr1:0X0000000DC2CA86C0 mmcra:0X00000000
+
+#Group 136 pm_fpuX2, Floating point events by unit
+event:0X880 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X881 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X882 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X883 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X884 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+event:0X885 mmcr0:0X00000000 mmcr1:0X00000000828A828A mmcra:0X00000000
+
+#Group 137 pm_fpuX3, Floating point events by unit
+event:0X890 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X891 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X892 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X893 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X894 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+event:0X895 mmcr0:0X00000000 mmcr1:0X00000000868E868E mmcra:0X00000000
+
+#Group 138 pm_fpuX4, Floating point and L1 events
+event:0X8A0 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8A1 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8A2 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8A3 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8A4 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+event:0X8A5 mmcr0:0X00000000 mmcr1:0X0030000020102020 mmcra:0X00000000
+
+#Group 139 pm_fpuX5, Floating point events
+event:0X8B0 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X8B1 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X8B2 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X8B3 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X8B4 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+event:0X8B5 mmcr0:0X00000000 mmcr1:0X0000000C2020868E mmcra:0X00000000
+
+#Group 140 pm_fpuX6, Floating point events
+event:0X8C0 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X8C1 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X8C2 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X8C3 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X8C4 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+event:0X8C5 mmcr0:0X00000000 mmcr1:0X0000000010202010 mmcra:0X00000000
+
+#Group 141 pm_hpmcount1, HPM group for set 1
+event:0X8D0 mmcr0:0X00000000 mmcr1:0X00000000201E2810 mmcra:0X00000000
+event:0X8D1 mmcr0:0X00000000 mmcr1:0X00000000201E2810 mmcra:0X00000000
+event:0X8D2 mmcr0:0X00000000 mmcr1:0X00000000201E2810 mmcra:0X00000000
+event:0X8D3 mmcr0:0X00000000 mmcr1:0X00000000201E2810 mmcra:0X00000000
+event:0X8D4 mmcr0:0X00000000 mmcr1:0X00000000201E2810 mmcra:0X00000000
+event:0X8D5 mmcr0:0X00000000 mmcr1:0X00000000201E2810 mmcra:0X00000000
+
+#Group 142 pm_hpmcount2, HPM group for set 2
+event:0X8E0 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X8E1 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X8E2 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X8E3 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X8E4 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+event:0X8E5 mmcr0:0X00000000 mmcr1:0X043000041E201220 mmcra:0X00000000
+
+#Group 143 pm_hpmcount3, HPM group for set 3
+event:0X8F0 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+event:0X8F1 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+event:0X8F2 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+event:0X8F3 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+event:0X8F4 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+event:0X8F5 mmcr0:0X00000000 mmcr1:0X403000041EC21086 mmcra:0X00000000
+
+#Group 144 pm_hpmcount4, HPM group for set 7
+event:0X900 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X901 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X902 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X903 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X904 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+event:0X905 mmcr0:0X00000000 mmcr1:0X00B00000101E2020 mmcra:0X00000000
+
+#Group 145 pm_hpmcount5, HPM group for set 9
+event:0X910 mmcr0:0X00000000 mmcr1:0X400000031E2810C4 mmcra:0X00000000
+event:0X911 mmcr0:0X00000000 mmcr1:0X400000031E2810C4 mmcra:0X00000000
+event:0X912 mmcr0:0X00000000 mmcr1:0X400000031E2810C4 mmcra:0X00000000
+event:0X913 mmcr0:0X00000000 mmcr1:0X400000031E2810C4 mmcra:0X00000000
+event:0X914 mmcr0:0X00000000 mmcr1:0X400000031E2810C4 mmcra:0X00000000
+event:0X915 mmcr0:0X00000000 mmcr1:0X400000031E2810C4 mmcra:0X00000000
+
+#Group 146 pm_eprof1, Group for use with eprof
+event:0X920 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X921 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X922 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X923 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X924 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+event:0X925 mmcr0:0X00000000 mmcr1:0X00300000121E108E mmcra:0X00000000
+
+#Group 147 pm_eprof2, Group for use with eprof
+event:0X930 mmcr0:0X00000000 mmcr1:0X0038000810122020 mmcra:0X00000000
+event:0X931 mmcr0:0X00000000 mmcr1:0X0038000810122020 mmcra:0X00000000
+event:0X932 mmcr0:0X00000000 mmcr1:0X0038000810122020 mmcra:0X00000000
+event:0X933 mmcr0:0X00000000 mmcr1:0X0038000810122020 mmcra:0X00000000
+event:0X934 mmcr0:0X00000000 mmcr1:0X0038000810122020 mmcra:0X00000000
+event:0X935 mmcr0:0X00000000 mmcr1:0X0038000810122020 mmcra:0X00000000
+
+#Group 148 pm_eprof3, Group for use with eprof
+event:0X940 mmcr0:0X00000000 mmcr1:0X00380008C6121286 mmcra:0X00000000
+event:0X941 mmcr0:0X00000000 mmcr1:0X00380008C6121286 mmcra:0X00000000
+event:0X942 mmcr0:0X00000000 mmcr1:0X00380008C6121286 mmcra:0X00000000
+event:0X943 mmcr0:0X00000000 mmcr1:0X00380008C6121286 mmcra:0X00000000
+event:0X944 mmcr0:0X00000000 mmcr1:0X00380008C6121286 mmcra:0X00000000
+event:0X945 mmcr0:0X00000000 mmcr1:0X00380008C6121286 mmcra:0X00000000
diff --git a/events/ppc64/power5/events b/events/ppc64/power5/events
new file mode 100644
index 0000000..8f438bd
--- /dev/null
+++ b/events/ppc64/power5/events
@@ -0,0 +1,1202 @@
+#PPC64 POWER5 events
+#
+# Within each group the event names must be unique. Each event in a group is
+# assigned to a unique counter. The groups are from the groups defined in the
+# Performance Monitor Unit user guide for this processor.
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles using continuous sampling
+
+#Group 0 with random sampling
+event:0X002 counters:2 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
+
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
+event:0X011 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP1 : (Group 1 pm_utilization) IOPS instructions completed
+event:0X012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
+event:0X013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
+event:0X014 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Instructions completed
+event:0X015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
+
+#Group 2 pm_completion, Completion and cycle counts
+event:0X020 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP2 : (Group 2 pm_completion) One or more PPC instruction completed
+event:0X021 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP2 : (Group 2 pm_completion) Cycles GCT empty
+event:0X022 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP2 : (Group 2 pm_completion) Group completed
+event:0X023 counters:3 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_completion) Processor cycles
+event:0X024 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP2 : (Group 2 pm_completion) Instructions completed
+event:0X025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_completion) Run cycles
+
+#Group 3 pm_group_dispatch, Group dispatch events
+event:0X030 counters:0 um:zero minimum:1000 name:PM_GRP_DISP_VALID_GRP3 : (Group 3 pm_group_dispatch) Group dispatch valid
+event:0X031 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_REJECT_GRP3 : (Group 3 pm_group_dispatch) Group dispatch rejected
+event:0X032 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_BLK_SB_CYC_GRP3 : (Group 3 pm_group_dispatch) Cycles group dispatch blocked by scoreboard
+event:0X033 counters:3 um:zero minimum:1000 name:PM_INST_DISP_GRP3 : (Group 3 pm_group_dispatch) Instructions dispatched
+event:0X034 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP3 : (Group 3 pm_group_dispatch) Instructions completed
+event:0X035 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP3 : (Group 3 pm_group_dispatch) Run cycles
+
+#Group 4 pm_clb1, CLB fullness
+event:0X040 counters:0 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles no instructions in CLB
+event:0X041 counters:1 um:zero minimum:1000 name:PM_2INST_CLB_CYC_GRP4 : (Group 4 pm_clb1) Cycles 2 instructions in CLB
+event:0X042 counters:2 um:zero minimum:1000 name:PM_CLB_EMPTY_CYC_GRP4 : (Group 4 pm_clb1) Cycles CLB empty
+event:0X043 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_CYC_GRP4 : (Group 4 pm_clb1) Marked load latency from L3.5 modified
+event:0X044 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP4 : (Group 4 pm_clb1) Instructions completed
+event:0X045 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP4 : (Group 4 pm_clb1) Run cycles
+
+#Group 5 pm_clb2, CLB fullness
+event:0X050 counters:0 um:zero minimum:1000 name:PM_5INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 5 instructions in CLB
+event:0X051 counters:1 um:zero minimum:1000 name:PM_6INST_CLB_CYC_GRP5 : (Group 5 pm_clb2) Cycles 6 instructions in CLB
+event:0X052 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_SRQ_INST_VALID_GRP5 : (Group 5 pm_clb2) Marked instruction valid in SRQ
+event:0X053 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP5 : (Group 5 pm_clb2) IOPS instructions completed
+event:0X054 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP5 : (Group 5 pm_clb2) Instructions completed
+event:0X055 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP5 : (Group 5 pm_clb2) Run cycles
+
+#Group 6 pm_gct_empty, GCT empty reasons
+event:0X060 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP6 : (Group 6 pm_gct_empty) Cycles no GCT slot allocated
+event:0X061 counters:1 um:zero minimum:1000 name:PM_GCT_NOSLOT_IC_MISS_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by I cache miss
+event:0X062 counters:2 um:zero minimum:1000 name:PM_GCT_NOSLOT_SRQ_FULL_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by SRQ full
+event:0X063 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_GRP6 : (Group 6 pm_gct_empty) No slot in GCT caused by branch mispredict
+event:0X064 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP6 : (Group 6 pm_gct_empty) Instructions completed
+event:0X065 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP6 : (Group 6 pm_gct_empty) Run cycles
+
+#Group 7 pm_gct_usage, GCT Usage
+event:0X070 counters:0 um:zero minimum:1000 name:PM_GCT_USAGE_00to59_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT less than 60% full
+event:0X071 counters:1 um:zero minimum:1000 name:PM_GCT_USAGE_60to79_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT 60-79% full
+event:0X072 counters:2 um:zero minimum:1000 name:PM_GCT_USAGE_80to99_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT 80-99% full
+event:0X073 counters:3 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP7 : (Group 7 pm_gct_usage) Cycles GCT full
+event:0X074 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP7 : (Group 7 pm_gct_usage) Instructions completed
+event:0X075 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP7 : (Group 7 pm_gct_usage) Run cycles
+
+#Group 8 pm_lsu1, LSU LRQ and LMQ events
+event:0X080 counters:0 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP8 : (Group 8 pm_lsu1) LRQ slot 0 allocated
+event:0X081 counters:1 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP8 : (Group 8 pm_lsu1) LRQ slot 0 valid
+event:0X082 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP8 : (Group 8 pm_lsu1) LMQ slot 0 allocated
+event:0X083 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP8 : (Group 8 pm_lsu1) LMQ slot 0 valid
+event:0X084 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP8 : (Group 8 pm_lsu1) Instructions completed
+event:0X085 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP8 : (Group 8 pm_lsu1) Run cycles
+
+#Group 9 pm_lsu2, LSU SRQ events
+event:0X090 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP9 : (Group 9 pm_lsu2) SRQ slot 0 allocated
+event:0X091 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP9 : (Group 9 pm_lsu2) SRQ slot 0 valid
+event:0X092 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP9 : (Group 9 pm_lsu2) SRQ sync duration
+event:0X093 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP9 : (Group 9 pm_lsu2) Cycles SRQ full
+event:0X094 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP9 : (Group 9 pm_lsu2) Instructions completed
+event:0X095 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP9 : (Group 9 pm_lsu2) Run cycles
+
+#Group 10 pm_lsu3, LSU SRQ and LMQ events
+event:0X0A0 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_STFWD_GRP10 : (Group 10 pm_lsu3) SRQ store forwarded
+event:0X0A1 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP10 : (Group 10 pm_lsu3) Cycles LMQ and SRQ empty
+event:0X0A2 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_LHR_MERGE_GRP10 : (Group 10 pm_lsu3) LMQ LHR merges
+event:0X0A3 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP10 : (Group 10 pm_lsu3) Cycles SRQ empty
+event:0X0A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP10 : (Group 10 pm_lsu3) Instructions completed
+event:0X0A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP10 : (Group 10 pm_lsu3) Run cycles
+
+#Group 11 pm_prefetch1, Prefetch stream allocation
+event:0X0B0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP11 : (Group 11 pm_prefetch1) Instructions fetched missed L2
+event:0X0B1 counters:1 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP11 : (Group 11 pm_prefetch1) Cycles at least 1 instruction fetched
+event:0X0B2 counters:2 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_BLK_GRP11 : (Group 11 pm_prefetch1) D cache out of prefech streams
+event:0X0B3 counters:3 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_GRP11 : (Group 11 pm_prefetch1) D cache new prefetch stream allocated
+event:0X0B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP11 : (Group 11 pm_prefetch1) Instructions completed
+event:0X0B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP11 : (Group 11 pm_prefetch1) Run cycles
+
+#Group 12 pm_prefetch2, Prefetch events
+event:0X0C0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP12 : (Group 12 pm_prefetch2) IOPS instructions completed
+event:0X0C1 counters:1 um:zero minimum:1000 name:PM_CLB_FULL_CYC_GRP12 : (Group 12 pm_prefetch2) Cycles CLB full
+event:0X0C2 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP12 : (Group 12 pm_prefetch2) L1 cache data prefetches
+event:0X0C3 counters:3 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP12 : (Group 12 pm_prefetch2) Instruction prefetched installed in prefetch
+event:0X0C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP12 : (Group 12 pm_prefetch2) Instructions completed
+event:0X0C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP12 : (Group 12 pm_prefetch2) Run cycles
+
+#Group 13 pm_prefetch3, L2 prefetch and misc events
+event:0X0D0 counters:0 um:zero minimum:1000 name:PM_LSU_BUSY_REJECT_GRP13 : (Group 13 pm_prefetch3) LSU busy due to reject
+event:0X0D1 counters:1 um:zero minimum:1000 name:PM_1INST_CLB_CYC_GRP13 : (Group 13 pm_prefetch3) Cycles 1 instruction in CLB
+event:0X0D2 counters:2 um:zero minimum:1000 name:PM_L2_PREF_GRP13 : (Group 13 pm_prefetch3) L2 cache prefetches
+event:0X0D3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP13 : (Group 13 pm_prefetch3) IOPS instructions completed
+event:0X0D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP13 : (Group 13 pm_prefetch3) Instructions completed
+event:0X0D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP13 : (Group 13 pm_prefetch3) Run cycles
+
+#Group 14 pm_prefetch4, Misc prefetch and reject events
+event:0X0E0 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_SRQ_LHS_GRP14 : (Group 14 pm_prefetch4) LSU0 SRQ rejects
+event:0X0E1 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_SRQ_LHS_GRP14 : (Group 14 pm_prefetch4) LSU1 SRQ rejects
+event:0X0E2 counters:2 um:zero minimum:1000 name:PM_DC_PREF_DST_GRP14 : (Group 14 pm_prefetch4) DST (Data Stream Touch) stream start
+event:0X0E3 counters:3 um:zero minimum:1000 name:PM_L2_PREF_GRP14 : (Group 14 pm_prefetch4) L2 cache prefetches
+event:0X0E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP14 : (Group 14 pm_prefetch4) Instructions completed
+event:0X0E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP14 : (Group 14 pm_prefetch4) Run cycles
+
+#Group 15 pm_lsu_reject1, LSU reject events
+event:0X0F0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_ERAT_MISS_GRP15 : (Group 15 pm_lsu_reject1) LSU reject due to ERAT miss
+event:0X0F1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_LMQ_FULL_GRP15 : (Group 15 pm_lsu_reject1) LSU reject due to LMQ full or missed data coming
+event:0X0F2 counters:2 um:zero minimum:1000 name:PM_FLUSH_IMBAL_GRP15 : (Group 15 pm_lsu_reject1) Flush caused by thread GCT imbalance
+event:0X0F3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_GRP15 : (Group 15 pm_lsu_reject1) Marked SRQ flushes
+event:0X0F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP15 : (Group 15 pm_lsu_reject1) Instructions completed
+event:0X0F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP15 : (Group 15 pm_lsu_reject1) Run cycles
+
+#Group 16 pm_lsu_reject2, LSU rejects due to reload CDF or tag update collision
+event:0X100 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_RELOAD_CDF_GRP16 : (Group 16 pm_lsu_reject2) LSU0 reject due to reload CDF or tag update collision
+event:0X101 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_RELOAD_CDF_GRP16 : (Group 16 pm_lsu_reject2) LSU1 reject due to reload CDF or tag update collision
+event:0X102 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP16 : (Group 16 pm_lsu_reject2) IOPS instructions completed
+event:0X103 counters:3 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP16 : (Group 16 pm_lsu_reject2) Cycles writing to instruction L1
+event:0X104 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP16 : (Group 16 pm_lsu_reject2) Instructions completed
+event:0X105 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP16 : (Group 16 pm_lsu_reject2) Run cycles
+
+#Group 17 pm_lsu_reject3, LSU rejects due to ERAT, held instuctions
+event:0X110 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_ERAT_MISS_GRP17 : (Group 17 pm_lsu_reject3) LSU0 reject due to ERAT miss
+event:0X111 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_ERAT_MISS_GRP17 : (Group 17 pm_lsu_reject3) LSU1 reject due to ERAT miss
+event:0X112 counters:2 um:zero minimum:1000 name:PM_LWSYNC_HELD_GRP17 : (Group 17 pm_lsu_reject3) LWSYNC held at dispatch
+event:0X113 counters:3 um:zero minimum:1000 name:PM_TLBIE_HELD_GRP17 : (Group 17 pm_lsu_reject3) TLBIE held at dispatch
+event:0X114 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP17 : (Group 17 pm_lsu_reject3) Instructions completed
+event:0X115 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP17 : (Group 17 pm_lsu_reject3) Run cycles
+
+#Group 18 pm_lsu_reject4, LSU0/1 reject LMQ full
+event:0X120 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_LMQ_FULL_GRP18 : (Group 18 pm_lsu_reject4) LSU0 reject due to LMQ full or missed data coming
+event:0X121 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_LMQ_FULL_GRP18 : (Group 18 pm_lsu_reject4) LSU1 reject due to LMQ full or missed data coming
+event:0X122 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP18 : (Group 18 pm_lsu_reject4) IOPS instructions completed
+event:0X123 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP18 : (Group 18 pm_lsu_reject4) Branches issued
+event:0X124 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP18 : (Group 18 pm_lsu_reject4) Instructions completed
+event:0X125 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP18 : (Group 18 pm_lsu_reject4) Run cycles
+
+#Group 19 pm_lsu_reject5, LSU misc reject and flush events
+event:0X130 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_SRQ_LHS_GRP19 : (Group 19 pm_lsu_reject5) LSU SRQ rejects
+event:0X131 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_RELOAD_CDF_GRP19 : (Group 19 pm_lsu_reject5) LSU reject due to reload CDF or tag update collision
+event:0X132 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP19 : (Group 19 pm_lsu_reject5) Flush initiated by LSU
+event:0X133 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP19 : (Group 19 pm_lsu_reject5) Flushes
+event:0X134 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP19 : (Group 19 pm_lsu_reject5) Instructions completed
+event:0X135 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP19 : (Group 19 pm_lsu_reject5) Run cycles
+
+#Group 20 pm_flush1, Misc flush events
+event:0X140 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP20 : (Group 20 pm_flush1) IOPS instructions completed
+event:0X141 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP20 : (Group 20 pm_flush1) SRQ unaligned store flushes
+event:0X142 counters:2 um:zero minimum:1000 name:PM_FLUSH_IMBAL_GRP20 : (Group 20 pm_flush1) Flush caused by thread GCT imbalance
+event:0X143 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP20 : (Group 20 pm_flush1) L1 D cache entries invalidated from L2
+event:0X144 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP20 : (Group 20 pm_flush1) Instructions completed
+event:0X145 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP20 : (Group 20 pm_flush1) Run cycles
+
+#Group 21 pm_flush2, Flushes due to scoreboard and sync
+event:0X150 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP21 : (Group 21 pm_flush2) Instruction TLB misses
+event:0X151 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP21 : (Group 21 pm_flush2) IOPS instructions completed
+event:0X152 counters:2 um:zero minimum:1000 name:PM_FLUSH_SB_GRP21 : (Group 21 pm_flush2) Flush caused by scoreboard operation
+event:0X153 counters:3 um:zero minimum:1000 name:PM_FLUSH_SYNC_GRP21 : (Group 21 pm_flush2) Flush caused by sync
+event:0X154 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP21 : (Group 21 pm_flush2) Instructions completed
+event:0X155 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP21 : (Group 21 pm_flush2) Run cycles
+
+#Group 22 pm_lsu_flush_srq_lrq, LSU flush by SRQ and LRQ events
+event:0X160 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP22 : (Group 22 pm_lsu_flush_srq_lrq) SRQ flushes
+event:0X161 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP22 : (Group 22 pm_lsu_flush_srq_lrq) LRQ flushes
+event:0X162 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP22 : (Group 22 pm_lsu_flush_srq_lrq) IOPS instructions completed
+event:0X163 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP22 : (Group 22 pm_lsu_flush_srq_lrq) Flush initiated by LSU
+event:0X164 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP22 : (Group 22 pm_lsu_flush_srq_lrq) Instructions completed
+event:0X165 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP22 : (Group 22 pm_lsu_flush_srq_lrq) Run cycles
+
+#Group 23 pm_lsu_flush_lrq, LSU0/1 flush due to LRQ
+event:0X170 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP23 : (Group 23 pm_lsu_flush_lrq) LSU0 LRQ flushes
+event:0X171 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP23 : (Group 23 pm_lsu_flush_lrq) LSU1 LRQ flushes
+event:0X172 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP23 : (Group 23 pm_lsu_flush_lrq) Flush initiated by LSU
+event:0X173 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP23 : (Group 23 pm_lsu_flush_lrq) IOPS instructions completed
+event:0X174 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP23 : (Group 23 pm_lsu_flush_lrq) Instructions completed
+event:0X175 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP23 : (Group 23 pm_lsu_flush_lrq) Run cycles
+
+#Group 24 pm_lsu_flush_srq, LSU0/1 flush due to SRQ
+event:0X180 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP24 : (Group 24 pm_lsu_flush_srq) LSU0 SRQ flushes
+event:0X181 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP24 : (Group 24 pm_lsu_flush_srq) LSU1 SRQ flushes
+event:0X182 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP24 : (Group 24 pm_lsu_flush_srq) IOPS instructions completed
+event:0X183 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP24 : (Group 24 pm_lsu_flush_srq) Flush initiated by LSU
+event:0X184 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP24 : (Group 24 pm_lsu_flush_srq) Instructions completed
+event:0X185 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP24 : (Group 24 pm_lsu_flush_srq) Run cycles
+
+#Group 25 pm_lsu_flush_unaligned, LSU flush due to unaligned data
+event:0X190 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP25 : (Group 25 pm_lsu_flush_unaligned) LRQ unaligned load flushes
+event:0X191 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP25 : (Group 25 pm_lsu_flush_unaligned) SRQ unaligned store flushes
+event:0X192 counters:2 um:zero minimum:1000 name:PM_BR_ISSUED_GRP25 : (Group 25 pm_lsu_flush_unaligned) Branches issued
+event:0X193 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP25 : (Group 25 pm_lsu_flush_unaligned) IOPS instructions completed
+event:0X194 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP25 : (Group 25 pm_lsu_flush_unaligned) Instructions completed
+event:0X195 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP25 : (Group 25 pm_lsu_flush_unaligned) Run cycles
+
+#Group 26 pm_lsu_flush_uld, LSU0/1 flush due to unaligned load
+event:0X1A0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP26 : (Group 26 pm_lsu_flush_uld) LSU0 unaligned load flushes
+event:0X1A1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP26 : (Group 26 pm_lsu_flush_uld) LSU1 unaligned load flushes
+event:0X1A2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP26 : (Group 26 pm_lsu_flush_uld) Flush initiated by LSU
+event:0X1A3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP26 : (Group 26 pm_lsu_flush_uld) IOPS instructions completed
+event:0X1A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP26 : (Group 26 pm_lsu_flush_uld) Instructions completed
+event:0X1A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP26 : (Group 26 pm_lsu_flush_uld) Run cycles
+
+#Group 27 pm_lsu_flush_ust, LSU0/1 flush due to unaligned store
+event:0X1B0 counters:0 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP27 : (Group 27 pm_lsu_flush_ust) LSU0 unaligned store flushes
+event:0X1B1 counters:1 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP27 : (Group 27 pm_lsu_flush_ust) LSU1 unaligned store flushes
+event:0X1B2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP27 : (Group 27 pm_lsu_flush_ust) IOPS instructions completed
+event:0X1B3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP27 : (Group 27 pm_lsu_flush_ust) Flush initiated by LSU
+event:0X1B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP27 : (Group 27 pm_lsu_flush_ust) Instructions completed
+event:0X1B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP27 : (Group 27 pm_lsu_flush_ust) Run cycles
+
+#Group 28 pm_lsu_flush_full, LSU flush due to LRQ/SRQ full
+event:0X1C0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_FULL_GRP28 : (Group 28 pm_lsu_flush_full) Flush caused by LRQ full
+event:0X1C1 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP28 : (Group 28 pm_lsu_flush_full) IOPS instructions completed
+event:0X1C2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP28 : (Group 28 pm_lsu_flush_full) Marked LRQ flushes
+event:0X1C3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_FULL_GRP28 : (Group 28 pm_lsu_flush_full) Flush caused by SRQ full
+event:0X1C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP28 : (Group 28 pm_lsu_flush_full) Instructions completed
+event:0X1C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP28 : (Group 28 pm_lsu_flush_full) Run cycles
+
+#Group 29 pm_lsu_stall1, LSU Stalls
+event:0X1D0 counters:0 um:zero minimum:1000 name:PM_GRP_MRK_GRP29 : (Group 29 pm_lsu_stall1) Group marked in IDU
+event:0X1D1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP29 : (Group 29 pm_lsu_stall1) Completion stall caused by LSU instruction
+event:0X1D2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP29 : (Group 29 pm_lsu_stall1) IOPS instructions completed
+event:0X1D3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP29 : (Group 29 pm_lsu_stall1) Completion stall caused by reject
+event:0X1D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP29 : (Group 29 pm_lsu_stall1) Instructions completed
+event:0X1D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP29 : (Group 29 pm_lsu_stall1) Run cycles
+
+#Group 30 pm_lsu_stall2, LSU Stalls
+event:0X1E0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP30 : (Group 30 pm_lsu_stall2) IOPS instructions completed
+event:0X1E1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP30 : (Group 30 pm_lsu_stall2) Completion stall caused by D cache miss
+event:0X1E2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP30 : (Group 30 pm_lsu_stall2) Processor cycles
+event:0X1E3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP30 : (Group 30 pm_lsu_stall2) Completion stall caused by ERAT miss
+event:0X1E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP30 : (Group 30 pm_lsu_stall2) Instructions completed
+event:0X1E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP30 : (Group 30 pm_lsu_stall2) Run cycles
+
+#Group 31 pm_fxu_stall, FXU Stalls
+event:0X1F0 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_BR_REDIR_NONSPEC_GRP31 : (Group 31 pm_fxu_stall) Group experienced non-speculative I cache miss or branch redirect
+event:0X1F1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP31 : (Group 31 pm_fxu_stall) Completion stall caused by FXU instruction
+event:0X1F2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP31 : (Group 31 pm_fxu_stall) IOPS instructions completed
+event:0X1F3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP31 : (Group 31 pm_fxu_stall) Completion stall caused by DIV instruction
+event:0X1F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_fxu_stall) Instructions completed
+event:0X1F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP31 : (Group 31 pm_fxu_stall) Run cycles
+
+#Group 32 pm_fpu_stall, FPU Stalls
+event:0X200 counters:0 um:zero minimum:1000 name:PM_FPU_FULL_CYC_GRP32 : (Group 32 pm_fpu_stall) Cycles FPU issue queue full
+event:0X201 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FDIV_GRP32 : (Group 32 pm_fpu_stall) Completion stall caused by FDIV or FQRT instruction
+event:0X202 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP32 : (Group 32 pm_fpu_stall) IOPS instructions completed
+event:0X203 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_FPU_GRP32 : (Group 32 pm_fpu_stall) Completion stall caused by FPU instruction
+event:0X204 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_fpu_stall) Instructions completed
+event:0X205 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP32 : (Group 32 pm_fpu_stall) Run cycles
+
+#Group 33 pm_queue_full, BRQ LRQ LMQ queue full
+event:0X210 counters:0 um:zero minimum:1000 name:PM_LARX_LSU0_GRP33 : (Group 33 pm_queue_full) Larx executed on LSU0
+event:0X211 counters:1 um:zero minimum:1000 name:PM_BRQ_FULL_CYC_GRP33 : (Group 33 pm_queue_full) Cycles branch queue full
+event:0X212 counters:2 um:zero minimum:1000 name:PM_LSU_LRQ_FULL_CYC_GRP33 : (Group 33 pm_queue_full) Cycles LRQ full
+event:0X213 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP33 : (Group 33 pm_queue_full) Cycles LMQ full
+event:0X214 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP33 : (Group 33 pm_queue_full) Instructions completed
+event:0X215 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP33 : (Group 33 pm_queue_full) Run cycles
+
+#Group 34 pm_issueq_full, FPU FX full
+event:0X220 counters:0 um:zero minimum:1000 name:PM_FPU0_FULL_CYC_GRP34 : (Group 34 pm_issueq_full) Cycles FPU0 issue queue full
+event:0X221 counters:1 um:zero minimum:1000 name:PM_FPU1_FULL_CYC_GRP34 : (Group 34 pm_issueq_full) Cycles FPU1 issue queue full
+event:0X222 counters:2 um:zero minimum:1000 name:PM_FXLS0_FULL_CYC_GRP34 : (Group 34 pm_issueq_full) Cycles FXU0/LS0 queue full
+event:0X223 counters:3 um:zero minimum:1000 name:PM_FXLS1_FULL_CYC_GRP34 : (Group 34 pm_issueq_full) Cycles FXU1/LS1 queue full
+event:0X224 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP34 : (Group 34 pm_issueq_full) Instructions completed
+event:0X225 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP34 : (Group 34 pm_issueq_full) Run cycles
+
+#Group 35 pm_mapper_full1, CR CTR GPR mapper full
+event:0X230 counters:0 um:zero minimum:1000 name:PM_CR_MAP_FULL_CYC_GRP35 : (Group 35 pm_mapper_full1) Cycles CR logical operation mapper full
+event:0X231 counters:1 um:zero minimum:1000 name:PM_LR_CTR_MAP_FULL_CYC_GRP35 : (Group 35 pm_mapper_full1) Cycles LR/CTR mapper full
+event:0X232 counters:2 um:zero minimum:1000 name:PM_GPR_MAP_FULL_CYC_GRP35 : (Group 35 pm_mapper_full1) Cycles GPR mapper full
+event:0X233 counters:3 um:zero minimum:1000 name:PM_CRQ_FULL_CYC_GRP35 : (Group 35 pm_mapper_full1) Cycles CR issue queue full
+event:0X234 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP35 : (Group 35 pm_mapper_full1) Instructions completed
+event:0X235 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP35 : (Group 35 pm_mapper_full1) Run cycles
+
+#Group 36 pm_mapper_full2, FPR XER mapper full
+event:0X240 counters:0 um:zero minimum:1000 name:PM_FPR_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full2) Cycles FPR mapper full
+event:0X241 counters:1 um:zero minimum:1000 name:PM_XER_MAP_FULL_CYC_GRP36 : (Group 36 pm_mapper_full2) Cycles XER mapper full
+event:0X242 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2MISS_GRP36 : (Group 36 pm_mapper_full2) Marked data loaded missed L2
+event:0X243 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP36 : (Group 36 pm_mapper_full2) IOPS instructions completed
+event:0X244 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP36 : (Group 36 pm_mapper_full2) Instructions completed
+event:0X245 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP36 : (Group 36 pm_mapper_full2) Run cycles
+
+#Group 37 pm_misc_load, Non-cachable loads and stcx events
+event:0X250 counters:0 um:zero minimum:1000 name:PM_STCX_FAIL_GRP37 : (Group 37 pm_misc_load) STCX failed
+event:0X251 counters:1 um:zero minimum:1000 name:PM_STCX_PASS_GRP37 : (Group 37 pm_misc_load) Stcx passes
+event:0X252 counters:2 um:zero minimum:1000 name:PM_LSU0_NCLD_GRP37 : (Group 37 pm_misc_load) LSU0 non-cacheable loads
+event:0X253 counters:3 um:zero minimum:1000 name:PM_LSU1_NCLD_GRP37 : (Group 37 pm_misc_load) LSU1 non-cacheable loads
+event:0X254 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP37 : (Group 37 pm_misc_load) Instructions completed
+event:0X255 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP37 : (Group 37 pm_misc_load) Run cycles
+
+#Group 38 pm_ic_demand, ICache demand from BR redirect
+event:0X260 counters:0 um:zero minimum:1000 name:PM_LSU0_BUSY_REJECT_GRP38 : (Group 38 pm_ic_demand) LSU0 busy due to reject
+event:0X261 counters:1 um:zero minimum:1000 name:PM_LSU1_BUSY_REJECT_GRP38 : (Group 38 pm_ic_demand) LSU1 busy due to reject
+event:0X262 counters:2 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BHT_REDIRECT_GRP38 : (Group 38 pm_ic_demand) L2 I cache demand request due to BHT redirect
+event:0X263 counters:3 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_REDIRECT_GRP38 : (Group 38 pm_ic_demand) L2 I cache demand request due to branch redirect
+event:0X264 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP38 : (Group 38 pm_ic_demand) Instructions completed
+event:0X265 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP38 : (Group 38 pm_ic_demand) Run cycles
+
+#Group 39 pm_ic_pref, ICache prefetch
+event:0X270 counters:0 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_GRP39 : (Group 39 pm_ic_pref) Translation written to ierat
+event:0X271 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP39 : (Group 39 pm_ic_pref) Instruction prefetch requests
+event:0X272 counters:2 um:zero minimum:1000 name:PM_IC_PREF_INSTALL_GRP39 : (Group 39 pm_ic_pref) Instruction prefetched installed in prefetch
+event:0X273 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP39 : (Group 39 pm_ic_pref) No instructions fetched
+event:0X274 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP39 : (Group 39 pm_ic_pref) Instructions completed
+event:0X275 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP39 : (Group 39 pm_ic_pref) Run cycles
+
+#Group 40 pm_ic_miss, ICache misses
+event:0X280 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_NONSPEC_GRP40 : (Group 40 pm_ic_miss) Group experienced non-speculative I cache miss
+event:0X281 counters:1 um:zero minimum:1000 name:PM_GRP_IC_MISS_GRP40 : (Group 40 pm_ic_miss) Group experienced I cache miss
+event:0X282 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP40 : (Group 40 pm_ic_miss) L1 reload data source valid
+event:0X283 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP40 : (Group 40 pm_ic_miss) IOPS instructions completed
+event:0X284 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP40 : (Group 40 pm_ic_miss) Instructions completed
+event:0X285 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP40 : (Group 40 pm_ic_miss) Run cycles
+
+#Group 41 pm_branch_miss, Branch mispredict, TLB and SLB misses
+event:0X290 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP41 : (Group 41 pm_branch_miss) TLB misses
+event:0X291 counters:1 um:zero minimum:1000 name:PM_SLB_MISS_GRP41 : (Group 41 pm_branch_miss) SLB misses
+event:0X292 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP41 : (Group 41 pm_branch_miss) Branch mispredictions due to CR bit setting
+event:0X293 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP41 : (Group 41 pm_branch_miss) Branch mispredictions due to target address
+event:0X294 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP41 : (Group 41 pm_branch_miss) Instructions completed
+event:0X295 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP41 : (Group 41 pm_branch_miss) Run cycles
+
+#Group 42 pm_branch1, Branch operations
+event:0X2A0 counters:0 um:zero minimum:1000 name:PM_BR_UNCOND_GRP42 : (Group 42 pm_branch1) Unconditional branch
+event:0X2A1 counters:1 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP42 : (Group 42 pm_branch1) A conditional branch was predicted, target prediction
+event:0X2A2 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP42 : (Group 42 pm_branch1) A conditional branch was predicted, CR prediction
+event:0X2A3 counters:3 um:zero minimum:1000 name:PM_BR_PRED_CR_TA_GRP42 : (Group 42 pm_branch1) A conditional branch was predicted, CR and target prediction
+event:0X2A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP42 : (Group 42 pm_branch1) Instructions completed
+event:0X2A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP42 : (Group 42 pm_branch1) Run cycles
+
+#Group 43 pm_branch2, Branch operations
+event:0X2B0 counters:0 um:zero minimum:1000 name:PM_GRP_BR_REDIR_NONSPEC_GRP43 : (Group 43 pm_branch2) Group experienced non-speculative branch redirect
+event:0X2B1 counters:1 um:zero minimum:1000 name:PM_GRP_BR_REDIR_GRP43 : (Group 43 pm_branch2) Group experienced branch redirect
+event:0X2B2 counters:2 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP43 : (Group 43 pm_branch2) Flush caused by branch mispredict
+event:0X2B3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP43 : (Group 43 pm_branch2) IOPS instructions completed
+event:0X2B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP43 : (Group 43 pm_branch2) Instructions completed
+event:0X2B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP43 : (Group 43 pm_branch2) Run cycles
+
+#Group 44 pm_L1_tlbmiss, L1 load and TLB misses
+event:0X2C0 counters:0 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP44 : (Group 44 pm_L1_tlbmiss) Cycles doing data tablewalks
+event:0X2C1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP44 : (Group 44 pm_L1_tlbmiss) Data TLB misses
+event:0X2C2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP44 : (Group 44 pm_L1_tlbmiss) L1 D cache load misses
+event:0X2C3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP44 : (Group 44 pm_L1_tlbmiss) L1 D cache load references
+event:0X2C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP44 : (Group 44 pm_L1_tlbmiss) Instructions completed
+event:0X2C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP44 : (Group 44 pm_L1_tlbmiss) Run cycles
+
+#Group 45 pm_L1_DERAT_miss, L1 store and DERAT misses
+event:0X2D0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP45 : (Group 45 pm_L1_DERAT_miss) Data loaded from L2
+event:0X2D1 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP45 : (Group 45 pm_L1_DERAT_miss) DERAT misses
+event:0X2D2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP45 : (Group 45 pm_L1_DERAT_miss) L1 D cache store references
+event:0X2D3 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP45 : (Group 45 pm_L1_DERAT_miss) L1 D cache store misses
+event:0X2D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP45 : (Group 45 pm_L1_DERAT_miss) Instructions completed
+event:0X2D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP45 : (Group 45 pm_L1_DERAT_miss) Run cycles
+
+#Group 46 pm_L1_slbmiss, L1 load and SLB misses
+event:0X2E0 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_GRP46 : (Group 46 pm_L1_slbmiss) Data SLB misses
+event:0X2E1 counters:1 um:zero minimum:1000 name:PM_ISLB_MISS_GRP46 : (Group 46 pm_L1_slbmiss) Instruction SLB misses
+event:0X2E2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU0_GRP46 : (Group 46 pm_L1_slbmiss) LSU0 L1 D cache load misses
+event:0X2E3 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_LSU1_GRP46 : (Group 46 pm_L1_slbmiss) LSU1 L1 D cache load misses
+event:0X2E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP46 : (Group 46 pm_L1_slbmiss) Instructions completed
+event:0X2E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP46 : (Group 46 pm_L1_slbmiss) Run cycles
+
+#Group 47 pm_L1_dtlbmiss_4K, L1 load references and 4K Data TLB references and misses
+event:0X2F0 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_4K_GRP47 : (Group 47 pm_L1_dtlbmiss_4K) Data TLB reference for 4K page
+event:0X2F1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_4K_GRP47 : (Group 47 pm_L1_dtlbmiss_4K) Data TLB miss for 4K page
+event:0X2F2 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_GRP47 : (Group 47 pm_L1_dtlbmiss_4K) LSU0 L1 D cache load references
+event:0X2F3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_GRP47 : (Group 47 pm_L1_dtlbmiss_4K) LSU1 L1 D cache load references
+event:0X2F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP47 : (Group 47 pm_L1_dtlbmiss_4K) Instructions completed
+event:0X2F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP47 : (Group 47 pm_L1_dtlbmiss_4K) Run cycles
+
+#Group 48 pm_L1_dtlbmiss_16M, L1 store references and 16M Data TLB references and misses
+event:0X300 counters:0 um:zero minimum:1000 name:PM_DTLB_REF_16M_GRP48 : (Group 48 pm_L1_dtlbmiss_16M) Data TLB reference for 16M page
+event:0X301 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_16M_GRP48 : (Group 48 pm_L1_dtlbmiss_16M) Data TLB miss for 16M page
+event:0X302 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_LSU0_GRP48 : (Group 48 pm_L1_dtlbmiss_16M) LSU0 L1 D cache store references
+event:0X303 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_LSU1_GRP48 : (Group 48 pm_L1_dtlbmiss_16M) LSU1 L1 D cache store references
+event:0X304 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP48 : (Group 48 pm_L1_dtlbmiss_16M) Instructions completed
+event:0X305 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP48 : (Group 48 pm_L1_dtlbmiss_16M) Run cycles
+
+#Group 49 pm_dsource1, L3 cache and memory data access
+event:0X310 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP49 : (Group 49 pm_dsource1) Data loaded from L3
+event:0X311 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP49 : (Group 49 pm_dsource1) Data loaded from local memory
+event:0X312 counters:2 um:zero minimum:1000 name:PM_FLUSH_GRP49 : (Group 49 pm_dsource1) Flushes
+event:0X313 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP49 : (Group 49 pm_dsource1) IOPS instructions completed
+event:0X314 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP49 : (Group 49 pm_dsource1) Instructions completed
+event:0X315 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP49 : (Group 49 pm_dsource1) Run cycles
+
+#Group 50 pm_dsource2, L3 cache and memory data access
+event:0X320 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP50 : (Group 50 pm_dsource2) Data loaded from L3
+event:0X321 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP50 : (Group 50 pm_dsource2) Data loaded from local memory
+event:0X322 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP50 : (Group 50 pm_dsource2) Data loaded missed L2
+event:0X323 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP50 : (Group 50 pm_dsource2) Data loaded from remote memory
+event:0X324 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP50 : (Group 50 pm_dsource2) Instructions completed
+event:0X325 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP50 : (Group 50 pm_dsource2) Run cycles
+
+#Group 51 pm_dsource_L2, L2 cache data access
+event:0X330 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP51 : (Group 51 pm_dsource_L2) Data loaded from L2.5 shared
+event:0X331 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP51 : (Group 51 pm_dsource_L2) Data loaded from L2.5 modified
+event:0X332 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L275_SHR_GRP51 : (Group 51 pm_dsource_L2) Data loaded from L2.75 shared
+event:0X333 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L275_MOD_GRP51 : (Group 51 pm_dsource_L2) Data loaded from L2.75 modified
+event:0X334 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP51 : (Group 51 pm_dsource_L2) Instructions completed
+event:0X335 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP51 : (Group 51 pm_dsource_L2) Run cycles
+
+#Group 52 pm_dsource_L3, L3 cache data access
+event:0X340 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_GRP52 : (Group 52 pm_dsource_L3) Data loaded from L3.5 shared
+event:0X341 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP52 : (Group 52 pm_dsource_L3) Data loaded from L3.5 modified
+event:0X342 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L375_SHR_GRP52 : (Group 52 pm_dsource_L3) Data loaded from L3.75 shared
+event:0X343 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L375_MOD_GRP52 : (Group 52 pm_dsource_L3) Data loaded from L3.75 modified
+event:0X344 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP52 : (Group 52 pm_dsource_L3) Instructions completed
+event:0X345 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP52 : (Group 52 pm_dsource_L3) Run cycles
+
+#Group 53 pm_isource1, Instruction source information
+event:0X350 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP53 : (Group 53 pm_isource1) Instruction fetched from L3
+event:0X351 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP53 : (Group 53 pm_isource1) Instruction fetched from L1
+event:0X352 counters:2 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP53 : (Group 53 pm_isource1) Instructions fetched from prefetch
+event:0X353 counters:3 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP53 : (Group 53 pm_isource1) Instruction fetched from remote memory
+event:0X354 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP53 : (Group 53 pm_isource1) Instructions completed
+event:0X355 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP53 : (Group 53 pm_isource1) Run cycles
+
+#Group 54 pm_isource2, Instruction source information
+event:0X360 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP54 : (Group 54 pm_isource2) Instructions fetched from L2
+event:0X361 counters:1 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP54 : (Group 54 pm_isource2) Instruction fetched from local memory
+event:0X362 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP54 : (Group 54 pm_isource2) IOPS instructions completed
+event:0X363 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP54 : (Group 54 pm_isource2) No instructions fetched
+event:0X364 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP54 : (Group 54 pm_isource2) Instructions completed
+event:0X365 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP54 : (Group 54 pm_isource2) Run cycles
+
+#Group 55 pm_isource_L2, L2 instruction source information
+event:0X370 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L25_SHR_GRP55 : (Group 55 pm_isource_L2) Instruction fetched from L2.5 shared
+event:0X371 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP55 : (Group 55 pm_isource_L2) Instruction fetched from L2.5 modified
+event:0X372 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L275_SHR_GRP55 : (Group 55 pm_isource_L2) Instruction fetched from L2.75 shared
+event:0X373 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L275_MOD_GRP55 : (Group 55 pm_isource_L2) Instruction fetched from L2.75 modified
+event:0X374 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP55 : (Group 55 pm_isource_L2) Instructions completed
+event:0X375 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP55 : (Group 55 pm_isource_L2) Run cycles
+
+#Group 56 pm_isource_L3, L3 instruction source information
+event:0X380 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L35_SHR_GRP56 : (Group 56 pm_isource_L3) Instruction fetched from L3.5 shared
+event:0X381 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L35_MOD_GRP56 : (Group 56 pm_isource_L3) Instruction fetched from L3.5 modified
+event:0X382 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L375_SHR_GRP56 : (Group 56 pm_isource_L3) Instruction fetched from L3.75 shared
+event:0X383 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L375_MOD_GRP56 : (Group 56 pm_isource_L3) Instruction fetched from L3.75 modified
+event:0X384 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP56 : (Group 56 pm_isource_L3) Instructions completed
+event:0X385 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP56 : (Group 56 pm_isource_L3) Run cycles
+
+#Group 57 pm_pteg_source1, PTEG source information
+event:0X390 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L25_SHR_GRP57 : (Group 57 pm_pteg_source1) PTEG loaded from L2.5 shared
+event:0X391 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L25_MOD_GRP57 : (Group 57 pm_pteg_source1) PTEG loaded from L2.5 modified
+event:0X392 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L275_SHR_GRP57 : (Group 57 pm_pteg_source1) PTEG loaded from L2.75 shared
+event:0X393 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L275_MOD_GRP57 : (Group 57 pm_pteg_source1) PTEG loaded from L2.75 modified
+event:0X394 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP57 : (Group 57 pm_pteg_source1) Instructions completed
+event:0X395 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP57 : (Group 57 pm_pteg_source1) Run cycles
+
+#Group 58 pm_pteg_source2, PTEG source information
+event:0X3A0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L35_SHR_GRP58 : (Group 58 pm_pteg_source2) PTEG loaded from L3.5 shared
+event:0X3A1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L35_MOD_GRP58 : (Group 58 pm_pteg_source2) PTEG loaded from L3.5 modified
+event:0X3A2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L375_SHR_GRP58 : (Group 58 pm_pteg_source2) PTEG loaded from L3.75 shared
+event:0X3A3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L375_MOD_GRP58 : (Group 58 pm_pteg_source2) PTEG loaded from L3.75 modified
+event:0X3A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP58 : (Group 58 pm_pteg_source2) Instructions completed
+event:0X3A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP58 : (Group 58 pm_pteg_source2) Run cycles
+
+#Group 59 pm_pteg_source3, PTEG source information
+event:0X3B0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP59 : (Group 59 pm_pteg_source3) PTEG loaded from L2
+event:0X3B1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP59 : (Group 59 pm_pteg_source3) PTEG loaded from local memory
+event:0X3B2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP59 : (Group 59 pm_pteg_source3) PTEG loaded from L2 miss
+event:0X3B3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP59 : (Group 59 pm_pteg_source3) PTEG loaded from remote memory
+event:0X3B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP59 : (Group 59 pm_pteg_source3) Instructions completed
+event:0X3B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP59 : (Group 59 pm_pteg_source3) Run cycles
+
+#Group 60 pm_pteg_source4, L3 PTEG and group disptach events
+event:0X3C0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP60 : (Group 60 pm_pteg_source4) PTEG loaded from L3
+event:0X3C1 counters:1 um:zero minimum:1000 name:PM_GRP_DISP_GRP60 : (Group 60 pm_pteg_source4) Group dispatches
+event:0X3C2 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_SUCCESS_GRP60 : (Group 60 pm_pteg_source4) Group dispatch success
+event:0X3C3 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP60 : (Group 60 pm_pteg_source4) L1 D cache entries invalidated from L2
+event:0X3C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP60 : (Group 60 pm_pteg_source4) Instructions completed
+event:0X3C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP60 : (Group 60 pm_pteg_source4) Run cycles
+
+#Group 61 pm_L2SA_ld, L2 slice A load events
+event:0X3D0 counters:0 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_GRP61 : (Group 61 pm_L2SA_ld) L2 Slice A RC load dispatch attempt
+event:0X3D1 counters:1 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_RC_FULL_GRP61 : (Group 61 pm_L2SA_ld) L2 Slice A RC load dispatch attempt failed due to all RC full
+event:0X3D2 counters:2 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_ADDR_GRP61 : (Group 61 pm_L2SA_ld) L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X3D3 counters:3 um:zero minimum:1000 name:PM_L2SA_RCLD_DISP_FAIL_OTHER_GRP61 : (Group 61 pm_L2SA_ld) L2 Slice A RC load dispatch attempt failed due to other reasons
+event:0X3D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP61 : (Group 61 pm_L2SA_ld) Instructions completed
+event:0X3D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP61 : (Group 61 pm_L2SA_ld) Run cycles
+
+#Group 62 pm_L2SA_st, L2 slice A store events
+event:0X3E0 counters:0 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_GRP62 : (Group 62 pm_L2SA_st) L2 Slice A RC store dispatch attempt
+event:0X3E1 counters:1 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_RC_FULL_GRP62 : (Group 62 pm_L2SA_st) L2 Slice A RC store dispatch attempt failed due to all RC full
+event:0X3E2 counters:2 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_ADDR_GRP62 : (Group 62 pm_L2SA_st) L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X3E3 counters:3 um:zero minimum:1000 name:PM_L2SA_RCST_DISP_FAIL_OTHER_GRP62 : (Group 62 pm_L2SA_st) L2 Slice A RC store dispatch attempt failed due to other reasons
+event:0X3E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP62 : (Group 62 pm_L2SA_st) Instructions completed
+event:0X3E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP62 : (Group 62 pm_L2SA_st) Run cycles
+
+#Group 63 pm_L2SA_st2, L2 slice A store events
+event:0X3F0 counters:0 um:zero minimum:1000 name:PM_L2SA_RC_DISP_FAIL_CO_BUSY_GRP63 : (Group 63 pm_L2SA_st2) L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X3F1 counters:1 um:zero minimum:1000 name:PM_L2SA_ST_REQ_GRP63 : (Group 63 pm_L2SA_st2) L2 slice A store requests
+event:0X3F2 counters:2 um:zero minimum:1000 name:PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL_GRP63 : (Group 63 pm_L2SA_st2) L2 Slice A RC dispatch attempt failed due to all CO busy
+event:0X3F3 counters:3 um:zero minimum:1000 name:PM_L2SA_ST_HIT_GRP63 : (Group 63 pm_L2SA_st2) L2 slice A store hits
+event:0X3F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP63 : (Group 63 pm_L2SA_st2) Instructions completed
+event:0X3F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP63 : (Group 63 pm_L2SA_st2) Run cycles
+
+#Group 64 pm_L2SB_ld, L2 slice B load events
+event:0X400 counters:0 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_GRP64 : (Group 64 pm_L2SB_ld) L2 Slice B RC load dispatch attempt
+event:0X401 counters:1 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_RC_FULL_GRP64 : (Group 64 pm_L2SB_ld) L2 Slice B RC load dispatch attempt failed due to all RC full
+event:0X402 counters:2 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_ADDR_GRP64 : (Group 64 pm_L2SB_ld) L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X403 counters:3 um:zero minimum:1000 name:PM_L2SB_RCLD_DISP_FAIL_OTHER_GRP64 : (Group 64 pm_L2SB_ld) L2 Slice B RC load dispatch attempt failed due to other reasons
+event:0X404 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP64 : (Group 64 pm_L2SB_ld) Instructions completed
+event:0X405 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP64 : (Group 64 pm_L2SB_ld) Run cycles
+
+#Group 65 pm_L2SB_st, L2 slice B store events
+event:0X410 counters:0 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_GRP65 : (Group 65 pm_L2SB_st) L2 Slice B RC store dispatch attempt
+event:0X411 counters:1 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_RC_FULL_GRP65 : (Group 65 pm_L2SB_st) L2 Slice B RC store dispatch attempt failed due to all RC full
+event:0X412 counters:2 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_ADDR_GRP65 : (Group 65 pm_L2SB_st) L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X413 counters:3 um:zero minimum:1000 name:PM_L2SB_RCST_DISP_FAIL_OTHER_GRP65 : (Group 65 pm_L2SB_st) L2 Slice B RC store dispatch attempt failed due to other reasons
+event:0X414 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP65 : (Group 65 pm_L2SB_st) Instructions completed
+event:0X415 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP65 : (Group 65 pm_L2SB_st) Run cycles
+
+#Group 66 pm_L2SB_st2, L2 slice B store events
+event:0X420 counters:0 um:zero minimum:1000 name:PM_L2SB_RC_DISP_FAIL_CO_BUSY_GRP66 : (Group 66 pm_L2SB_st2) L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X421 counters:1 um:zero minimum:1000 name:PM_L2SB_ST_REQ_GRP66 : (Group 66 pm_L2SB_st2) L2 slice B store requests
+event:0X422 counters:2 um:zero minimum:1000 name:PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL_GRP66 : (Group 66 pm_L2SB_st2) L2 Slice B RC dispatch attempt failed due to all CO busy
+event:0X423 counters:3 um:zero minimum:1000 name:PM_L2SB_ST_HIT_GRP66 : (Group 66 pm_L2SB_st2) L2 slice B store hits
+event:0X424 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP66 : (Group 66 pm_L2SB_st2) Instructions completed
+event:0X425 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP66 : (Group 66 pm_L2SB_st2) Run cycles
+
+#Group 67 pm_L2SB_ld, L2 slice C load events
+event:0X430 counters:0 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_GRP67 : (Group 67 pm_L2SB_ld) L2 Slice C RC load dispatch attempt
+event:0X431 counters:1 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_RC_FULL_GRP67 : (Group 67 pm_L2SB_ld) L2 Slice C RC load dispatch attempt failed due to all RC full
+event:0X432 counters:2 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_ADDR_GRP67 : (Group 67 pm_L2SB_ld) L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X433 counters:3 um:zero minimum:1000 name:PM_L2SC_RCLD_DISP_FAIL_OTHER_GRP67 : (Group 67 pm_L2SB_ld) L2 Slice C RC load dispatch attempt failed due to other reasons
+event:0X434 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP67 : (Group 67 pm_L2SB_ld) Instructions completed
+event:0X435 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP67 : (Group 67 pm_L2SB_ld) Run cycles
+
+#Group 68 pm_L2SB_st, L2 slice C store events
+event:0X440 counters:0 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_GRP68 : (Group 68 pm_L2SB_st) L2 Slice C RC store dispatch attempt
+event:0X441 counters:1 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_RC_FULL_GRP68 : (Group 68 pm_L2SB_st) L2 Slice C RC store dispatch attempt failed due to all RC full
+event:0X442 counters:2 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_ADDR_GRP68 : (Group 68 pm_L2SB_st) L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X443 counters:3 um:zero minimum:1000 name:PM_L2SC_RCST_DISP_FAIL_OTHER_GRP68 : (Group 68 pm_L2SB_st) L2 Slice C RC store dispatch attempt failed due to other reasons
+event:0X444 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP68 : (Group 68 pm_L2SB_st) Instructions completed
+event:0X445 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP68 : (Group 68 pm_L2SB_st) Run cycles
+
+#Group 69 pm_L2SB_st2, L2 slice C store events
+event:0X450 counters:0 um:zero minimum:1000 name:PM_L2SC_RC_DISP_FAIL_CO_BUSY_GRP69 : (Group 69 pm_L2SB_st2) L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy
+event:0X451 counters:1 um:zero minimum:1000 name:PM_L2SC_ST_REQ_GRP69 : (Group 69 pm_L2SB_st2) L2 slice C store requests
+event:0X452 counters:2 um:zero minimum:1000 name:PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL_GRP69 : (Group 69 pm_L2SB_st2) L2 Slice C RC dispatch attempt failed due to all CO busy
+event:0X453 counters:3 um:zero minimum:1000 name:PM_L2SC_ST_HIT_GRP69 : (Group 69 pm_L2SB_st2) L2 slice C store hits
+event:0X454 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP69 : (Group 69 pm_L2SB_st2) Instructions completed
+event:0X455 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP69 : (Group 69 pm_L2SB_st2) Run cycles
+
+#Group 70 pm_L3SA_trans, L3 slice A state transistions
+event:0X460 counters:0 um:zero minimum:1000 name:PM_L3SA_MOD_TAG_GRP70 : (Group 70 pm_L3SA_trans) L3 slice A transition from modified to TAG
+event:0X461 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP70 : (Group 70 pm_L3SA_trans) IOPS instructions completed
+event:0X462 counters:2 um:zero minimum:1000 name:PM_L3SA_MOD_INV_GRP70 : (Group 70 pm_L3SA_trans) L3 slice A transition from modified to invalid
+event:0X463 counters:3 um:zero minimum:1000 name:PM_L3SA_SHR_INV_GRP70 : (Group 70 pm_L3SA_trans) L3 slice A transition from shared to invalid
+event:0X464 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP70 : (Group 70 pm_L3SA_trans) Instructions completed
+event:0X465 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP70 : (Group 70 pm_L3SA_trans) Run cycles
+
+#Group 71 pm_L3SB_trans, L3 slice B state transistions
+event:0X470 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP71 : (Group 71 pm_L3SB_trans) IOPS instructions completed
+event:0X471 counters:1 um:zero minimum:1000 name:PM_L3SB_MOD_TAG_GRP71 : (Group 71 pm_L3SB_trans) L3 slice B transition from modified to TAG
+event:0X472 counters:2 um:zero minimum:1000 name:PM_L3SB_MOD_INV_GRP71 : (Group 71 pm_L3SB_trans) L3 slice B transition from modified to invalid
+event:0X473 counters:3 um:zero minimum:1000 name:PM_L3SB_SHR_INV_GRP71 : (Group 71 pm_L3SB_trans) L3 slice B transition from shared to invalid
+event:0X474 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP71 : (Group 71 pm_L3SB_trans) Instructions completed
+event:0X475 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP71 : (Group 71 pm_L3SB_trans) Run cycles
+
+#Group 72 pm_L3SC_trans, L3 slice C state transistions
+event:0X480 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP72 : (Group 72 pm_L3SC_trans) IOPS instructions completed
+event:0X481 counters:1 um:zero minimum:1000 name:PM_L3SC_MOD_TAG_GRP72 : (Group 72 pm_L3SC_trans) L3 slice C transition from modified to TAG
+event:0X482 counters:2 um:zero minimum:1000 name:PM_L3SC_MOD_INV_GRP72 : (Group 72 pm_L3SC_trans) L3 slice C transition from modified to invalid
+event:0X483 counters:3 um:zero minimum:1000 name:PM_L3SC_SHR_INV_GRP72 : (Group 72 pm_L3SC_trans) L3 slice C transition from shared to invalid
+event:0X484 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP72 : (Group 72 pm_L3SC_trans) Instructions completed
+event:0X485 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP72 : (Group 72 pm_L3SC_trans) Run cycles
+
+#Group 73 pm_L2SA_trans, L2 slice A state transistions
+event:0X490 counters:0 um:zero minimum:1000 name:PM_L2SA_MOD_TAG_GRP73 : (Group 73 pm_L2SA_trans) L2 slice A transition from modified to tagged
+event:0X491 counters:1 um:zero minimum:1000 name:PM_L2SA_SHR_MOD_GRP73 : (Group 73 pm_L2SA_trans) L2 slice A transition from shared to modified
+event:0X492 counters:2 um:zero minimum:1000 name:PM_L2SA_MOD_INV_GRP73 : (Group 73 pm_L2SA_trans) L2 slice A transition from modified to invalid
+event:0X493 counters:3 um:zero minimum:1000 name:PM_L2SA_SHR_INV_GRP73 : (Group 73 pm_L2SA_trans) L2 slice A transition from shared to invalid
+event:0X494 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP73 : (Group 73 pm_L2SA_trans) Instructions completed
+event:0X495 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP73 : (Group 73 pm_L2SA_trans) Run cycles
+
+#Group 74 pm_L2SB_trans, L2 slice B state transistions
+event:0X4A0 counters:0 um:zero minimum:1000 name:PM_L2SB_MOD_TAG_GRP74 : (Group 74 pm_L2SB_trans) L2 slice B transition from modified to tagged
+event:0X4A1 counters:1 um:zero minimum:1000 name:PM_L2SB_SHR_MOD_GRP74 : (Group 74 pm_L2SB_trans) L2 slice B transition from shared to modified
+event:0X4A2 counters:2 um:zero minimum:1000 name:PM_L2SB_MOD_INV_GRP74 : (Group 74 pm_L2SB_trans) L2 slice B transition from modified to invalid
+event:0X4A3 counters:3 um:zero minimum:1000 name:PM_L2SB_SHR_INV_GRP74 : (Group 74 pm_L2SB_trans) L2 slice B transition from shared to invalid
+event:0X4A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP74 : (Group 74 pm_L2SB_trans) Instructions completed
+event:0X4A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP74 : (Group 74 pm_L2SB_trans) Run cycles
+
+#Group 75 pm_L2SC_trans, L2 slice C state transistions
+event:0X4B0 counters:0 um:zero minimum:1000 name:PM_L2SC_MOD_TAG_GRP75 : (Group 75 pm_L2SC_trans) L2 slice C transition from modified to tagged
+event:0X4B1 counters:1 um:zero minimum:1000 name:PM_L2SC_SHR_MOD_GRP75 : (Group 75 pm_L2SC_trans) L2 slice C transition from shared to modified
+event:0X4B2 counters:2 um:zero minimum:1000 name:PM_L2SC_MOD_INV_GRP75 : (Group 75 pm_L2SC_trans) L2 slice C transition from modified to invalid
+event:0X4B3 counters:3 um:zero minimum:1000 name:PM_L2SC_SHR_INV_GRP75 : (Group 75 pm_L2SC_trans) L2 slice C transition from shared to invalid
+event:0X4B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP75 : (Group 75 pm_L2SC_trans) Instructions completed
+event:0X4B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP75 : (Group 75 pm_L2SC_trans) Run cycles
+
+#Group 76 pm_L3SAB_retry, L3 slice A/B snoop retry and all CI/CO busy
+event:0X4C0 counters:0 um:zero minimum:1000 name:PM_L3SA_ALL_BUSY_GRP76 : (Group 76 pm_L3SAB_retry) L3 slice A active for every cycle all CI/CO machines busy
+event:0X4C1 counters:1 um:zero minimum:1000 name:PM_L3SB_ALL_BUSY_GRP76 : (Group 76 pm_L3SAB_retry) L3 slice B active for every cycle all CI/CO machines busy
+event:0X4C2 counters:2 um:zero minimum:1000 name:PM_L3SA_SNOOP_RETRY_GRP76 : (Group 76 pm_L3SAB_retry) L3 slice A snoop retries
+event:0X4C3 counters:3 um:zero minimum:1000 name:PM_L3SB_SNOOP_RETRY_GRP76 : (Group 76 pm_L3SAB_retry) L3 slice B snoop retries
+event:0X4C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP76 : (Group 76 pm_L3SAB_retry) Instructions completed
+event:0X4C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP76 : (Group 76 pm_L3SAB_retry) Run cycles
+
+#Group 77 pm_L3SAB_hit, L3 slice A/B hit and reference
+event:0X4D0 counters:0 um:zero minimum:1000 name:PM_L3SA_REF_GRP77 : (Group 77 pm_L3SAB_hit) L3 slice A references
+event:0X4D1 counters:1 um:zero minimum:1000 name:PM_L3SB_REF_GRP77 : (Group 77 pm_L3SAB_hit) L3 slice B references
+event:0X4D2 counters:2 um:zero minimum:1000 name:PM_L3SA_HIT_GRP77 : (Group 77 pm_L3SAB_hit) L3 slice A hits
+event:0X4D3 counters:3 um:zero minimum:1000 name:PM_L3SB_HIT_GRP77 : (Group 77 pm_L3SAB_hit) L3 slice B hits
+event:0X4D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP77 : (Group 77 pm_L3SAB_hit) Instructions completed
+event:0X4D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP77 : (Group 77 pm_L3SAB_hit) Run cycles
+
+#Group 78 pm_L3SC_retry_hit, L3 slice C hit & snoop retry
+event:0X4E0 counters:0 um:zero minimum:1000 name:PM_L3SC_ALL_BUSY_GRP78 : (Group 78 pm_L3SC_retry_hit) L3 slice C active for every cycle all CI/CO machines busy
+event:0X4E1 counters:1 um:zero minimum:1000 name:PM_L3SC_REF_GRP78 : (Group 78 pm_L3SC_retry_hit) L3 slice C references
+event:0X4E2 counters:2 um:zero minimum:1000 name:PM_L3SC_SNOOP_RETRY_GRP78 : (Group 78 pm_L3SC_retry_hit) L3 slice C snoop retries
+event:0X4E3 counters:3 um:zero minimum:1000 name:PM_L3SC_HIT_GRP78 : (Group 78 pm_L3SC_retry_hit) L3 Slice C hits
+event:0X4E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP78 : (Group 78 pm_L3SC_retry_hit) Instructions completed
+event:0X4E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP78 : (Group 78 pm_L3SC_retry_hit) Run cycles
+
+#Group 79 pm_fpu1, Floating Point events
+event:0X4F0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP79 : (Group 79 pm_fpu1) FPU executed FDIV instruction
+event:0X4F1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP79 : (Group 79 pm_fpu1) FPU executed multiply-add instruction
+event:0X4F2 counters:2 um:zero minimum:1000 name:PM_FPU_FMOV_FEST_GRP79 : (Group 79 pm_fpu1) FPU executing FMOV or FEST instructions
+event:0X4F3 counters:3 um:zero minimum:1000 name:PM_FPU_FEST_GRP79 : (Group 79 pm_fpu1) FPU executed FEST instruction
+event:0X4F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP79 : (Group 79 pm_fpu1) Instructions completed
+event:0X4F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP79 : (Group 79 pm_fpu1) Run cycles
+
+#Group 80 pm_fpu2, Floating Point events
+event:0X500 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP80 : (Group 80 pm_fpu2) FPU executed one flop instruction
+event:0X501 counters:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP80 : (Group 80 pm_fpu2) FPU executed FSQRT instruction
+event:0X502 counters:2 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP80 : (Group 80 pm_fpu2) FPU executed FRSP or FCONV instructions
+event:0X503 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP80 : (Group 80 pm_fpu2) FPU produced a result
+event:0X504 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP80 : (Group 80 pm_fpu2) Instructions completed
+event:0X505 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP80 : (Group 80 pm_fpu2) Run cycles
+
+#Group 81 pm_fpu3, Floating point events
+event:0X510 counters:0 um:zero minimum:1000 name:PM_FPU_DENORM_GRP81 : (Group 81 pm_fpu3) FPU received denormalized data
+event:0X511 counters:1 um:zero minimum:1000 name:PM_FPU_STALL3_GRP81 : (Group 81 pm_fpu3) FPU stalled in pipe3
+event:0X512 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP81 : (Group 81 pm_fpu3) FPU0 produced a result
+event:0X513 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP81 : (Group 81 pm_fpu3) FPU1 produced a result
+event:0X514 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP81 : (Group 81 pm_fpu3) Instructions completed
+event:0X515 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP81 : (Group 81 pm_fpu3) Run cycles
+
+#Group 82 pm_fpu4, Floating point events
+event:0X520 counters:0 um:zero minimum:1000 name:PM_FPU_SINGLE_GRP82 : (Group 82 pm_fpu4) FPU executed single precision instruction
+event:0X521 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP82 : (Group 82 pm_fpu4) FPU executed store instruction
+event:0X522 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP82 : (Group 82 pm_fpu4) IOPS instructions completed
+event:0X523 counters:3 um:zero minimum:1000 name:PM_LSU_LDF_GRP82 : (Group 82 pm_fpu4) LSU executed Floating Point load instruction
+event:0X524 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP82 : (Group 82 pm_fpu4) Instructions completed
+event:0X525 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP82 : (Group 82 pm_fpu4) Run cycles
+
+#Group 83 pm_fpu5, Floating point events by unit
+event:0X530 counters:0 um:zero minimum:1000 name:PM_FPU0_FSQRT_GRP83 : (Group 83 pm_fpu5) FPU0 executed FSQRT instruction
+event:0X531 counters:1 um:zero minimum:1000 name:PM_FPU1_FSQRT_GRP83 : (Group 83 pm_fpu5) FPU1 executed FSQRT instruction
+event:0X532 counters:2 um:zero minimum:1000 name:PM_FPU0_FEST_GRP83 : (Group 83 pm_fpu5) FPU0 executed FEST instruction
+event:0X533 counters:3 um:zero minimum:1000 name:PM_FPU1_FEST_GRP83 : (Group 83 pm_fpu5) FPU1 executed FEST instruction
+event:0X534 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP83 : (Group 83 pm_fpu5) Instructions completed
+event:0X535 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP83 : (Group 83 pm_fpu5) Run cycles
+
+#Group 84 pm_fpu6, Floating point events by unit
+event:0X540 counters:0 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP84 : (Group 84 pm_fpu6) FPU0 received denormalized data
+event:0X541 counters:1 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP84 : (Group 84 pm_fpu6) FPU1 received denormalized data
+event:0X542 counters:2 um:zero minimum:1000 name:PM_FPU0_FMOV_FEST_GRP84 : (Group 84 pm_fpu6) FPU0 executed FMOV or FEST instructions
+event:0X543 counters:3 um:zero minimum:1000 name:PM_FPU1_FMOV_FEST_GRP84 : (Group 84 pm_fpu6) FPU1 executing FMOV or FEST instructions
+event:0X544 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP84 : (Group 84 pm_fpu6) Instructions completed
+event:0X545 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP84 : (Group 84 pm_fpu6) Run cycles
+
+#Group 85 pm_fpu7, Floating point events by unit
+event:0X550 counters:0 um:zero minimum:1000 name:PM_FPU0_FDIV_GRP85 : (Group 85 pm_fpu7) FPU0 executed FDIV instruction
+event:0X551 counters:1 um:zero minimum:1000 name:PM_FPU1_FDIV_GRP85 : (Group 85 pm_fpu7) FPU1 executed FDIV instruction
+event:0X552 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP85 : (Group 85 pm_fpu7) FPU0 executed FRSP or FCONV instructions
+event:0X553 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP85 : (Group 85 pm_fpu7) FPU1 executed FRSP or FCONV instructions
+event:0X554 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP85 : (Group 85 pm_fpu7) Instructions completed
+event:0X555 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP85 : (Group 85 pm_fpu7) Run cycles
+
+#Group 86 pm_fpu8, Floating point events by unit
+event:0X560 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP86 : (Group 86 pm_fpu8) FPU0 stalled in pipe3
+event:0X561 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP86 : (Group 86 pm_fpu8) FPU1 stalled in pipe3
+event:0X562 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP86 : (Group 86 pm_fpu8) IOPS instructions completed
+event:0X563 counters:3 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP86 : (Group 86 pm_fpu8) FPU0 executed FPSCR instruction
+event:0X564 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP86 : (Group 86 pm_fpu8) Instructions completed
+event:0X565 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP86 : (Group 86 pm_fpu8) Run cycles
+
+#Group 87 pm_fpu9, Floating point events by unit
+event:0X570 counters:0 um:zero minimum:1000 name:PM_FPU0_SINGLE_GRP87 : (Group 87 pm_fpu9) FPU0 executed single precision instruction
+event:0X571 counters:1 um:zero minimum:1000 name:PM_FPU1_SINGLE_GRP87 : (Group 87 pm_fpu9) FPU1 executed single precision instruction
+event:0X572 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP87 : (Group 87 pm_fpu9) LSU0 executed Floating Point load instruction
+event:0X573 counters:3 um:zero minimum:1000 name:PM_LSU1_LDF_GRP87 : (Group 87 pm_fpu9) LSU1 executed Floating Point load instruction
+event:0X574 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP87 : (Group 87 pm_fpu9) Instructions completed
+event:0X575 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP87 : (Group 87 pm_fpu9) Run cycles
+
+#Group 88 pm_fpu10, Floating point events by unit
+event:0X580 counters:0 um:zero minimum:1000 name:PM_FPU0_FMA_GRP88 : (Group 88 pm_fpu10) FPU0 executed multiply-add instruction
+event:0X581 counters:1 um:zero minimum:1000 name:PM_FPU1_FMA_GRP88 : (Group 88 pm_fpu10) FPU1 executed multiply-add instruction
+event:0X582 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP88 : (Group 88 pm_fpu10) IOPS instructions completed
+event:0X583 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP88 : (Group 88 pm_fpu10) FPU1 executed FRSP or FCONV instructions
+event:0X584 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP88 : (Group 88 pm_fpu10) Instructions completed
+event:0X585 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP88 : (Group 88 pm_fpu10) Run cycles
+
+#Group 89 pm_fpu11, Floating point events by unit
+event:0X590 counters:0 um:zero minimum:1000 name:PM_FPU0_1FLOP_GRP89 : (Group 89 pm_fpu11) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X591 counters:1 um:zero minimum:1000 name:PM_FPU1_1FLOP_GRP89 : (Group 89 pm_fpu11) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X592 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP89 : (Group 89 pm_fpu11) FPU0 produced a result
+event:0X593 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP89 : (Group 89 pm_fpu11) IOPS instructions completed
+event:0X594 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP89 : (Group 89 pm_fpu11) Instructions completed
+event:0X595 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP89 : (Group 89 pm_fpu11) Run cycles
+
+#Group 90 pm_fpu12, Floating point events by unit
+event:0X5A0 counters:0 um:zero minimum:1000 name:PM_FPU0_STF_GRP90 : (Group 90 pm_fpu12) FPU0 executed store instruction
+event:0X5A1 counters:1 um:zero minimum:1000 name:PM_FPU1_STF_GRP90 : (Group 90 pm_fpu12) FPU1 executed store instruction
+event:0X5A2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP90 : (Group 90 pm_fpu12) LSU0 executed Floating Point load instruction
+event:0X5A3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP90 : (Group 90 pm_fpu12) IOPS instructions completed
+event:0X5A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP90 : (Group 90 pm_fpu12) Instructions completed
+event:0X5A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP90 : (Group 90 pm_fpu12) Run cycles
+
+#Group 91 pm_fxu1, Fixed Point events
+event:0X5B0 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP91 : (Group 91 pm_fxu1) FXU idle
+event:0X5B1 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP91 : (Group 91 pm_fxu1) FXU busy
+event:0X5B2 counters:2 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP91 : (Group 91 pm_fxu1) FXU0 busy FXU1 idle
+event:0X5B3 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP91 : (Group 91 pm_fxu1) FXU1 busy FXU0 idle
+event:0X5B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP91 : (Group 91 pm_fxu1) Instructions completed
+event:0X5B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP91 : (Group 91 pm_fxu1) Run cycles
+
+#Group 92 pm_fxu2, Fixed Point events
+event:0X5C0 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP92 : (Group 92 pm_fxu2) Marked group dispatched
+event:0X5C1 counters:1 um:zero minimum:1000 name:PM_MRK_GRP_BR_REDIR_GRP92 : (Group 92 pm_fxu2) Group experienced marked branch redirect
+event:0X5C2 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP92 : (Group 92 pm_fxu2) FXU produced a result
+event:0X5C3 counters:3 um:zero minimum:1000 name:PM_FXLS_FULL_CYC_GRP92 : (Group 92 pm_fxu2) Cycles FXLS queue is full
+event:0X5C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP92 : (Group 92 pm_fxu2) Instructions completed
+event:0X5C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP92 : (Group 92 pm_fxu2) Run cycles
+
+#Group 93 pm_fxu3, Fixed Point events
+event:0X5D0 counters:0 um:zero minimum:1000 name:PM_3INST_CLB_CYC_GRP93 : (Group 93 pm_fxu3) Cycles 3 instructions in CLB
+event:0X5D1 counters:1 um:zero minimum:1000 name:PM_4INST_CLB_CYC_GRP93 : (Group 93 pm_fxu3) Cycles 4 instructions in CLB
+event:0X5D2 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP93 : (Group 93 pm_fxu3) FXU0 produced a result
+event:0X5D3 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP93 : (Group 93 pm_fxu3) FXU1 produced a result
+event:0X5D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP93 : (Group 93 pm_fxu3) Instructions completed
+event:0X5D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP93 : (Group 93 pm_fxu3) Run cycles
+
+#Group 94 pm_smt_priorities1, Thread priority events
+event:0X5E0 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_4_CYC_GRP94 : (Group 94 pm_smt_priorities1) Cycles thread running at priority level 4
+event:0X5E1 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_7_CYC_GRP94 : (Group 94 pm_smt_priorities1) Cycles thread running at priority level 7
+event:0X5E2 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_0_CYC_GRP94 : (Group 94 pm_smt_priorities1) Cycles no thread priority difference
+event:0X5E3 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_1or2_CYC_GRP94 : (Group 94 pm_smt_priorities1) Cycles thread priority difference is 1 or 2
+event:0X5E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP94 : (Group 94 pm_smt_priorities1) Instructions completed
+event:0X5E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP94 : (Group 94 pm_smt_priorities1) Run cycles
+
+#Group 95 pm_smt_priorities2, Thread priority events
+event:0X5F0 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_3_CYC_GRP95 : (Group 95 pm_smt_priorities2) Cycles thread running at priority level 3
+event:0X5F1 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_6_CYC_GRP95 : (Group 95 pm_smt_priorities2) Cycles thread running at priority level 6
+event:0X5F2 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_3or4_CYC_GRP95 : (Group 95 pm_smt_priorities2) Cycles thread priority difference is 3 or 4
+event:0X5F3 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_5or6_CYC_GRP95 : (Group 95 pm_smt_priorities2) Cycles thread priority difference is 5 or 6
+event:0X5F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP95 : (Group 95 pm_smt_priorities2) Instructions completed
+event:0X5F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP95 : (Group 95 pm_smt_priorities2) Run cycles
+
+#Group 96 pm_smt_priorities3, Thread priority events
+event:0X600 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_2_CYC_GRP96 : (Group 96 pm_smt_priorities3) Cycles thread running at priority level 2
+event:0X601 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_5_CYC_GRP96 : (Group 96 pm_smt_priorities3) Cycles thread running at priority level 5
+event:0X602 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP96 : (Group 96 pm_smt_priorities3) Cycles thread priority difference is -1 or -2
+event:0X603 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP96 : (Group 96 pm_smt_priorities3) Cycles thread priority difference is -3 or -4
+event:0X604 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP96 : (Group 96 pm_smt_priorities3) Instructions completed
+event:0X605 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP96 : (Group 96 pm_smt_priorities3) Run cycles
+
+#Group 97 pm_smt_priorities4, Thread priority events
+event:0X610 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_1_CYC_GRP97 : (Group 97 pm_smt_priorities4) Cycles thread running at priority level 1
+event:0X611 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP97 : (Group 97 pm_smt_priorities4) Hypervisor Cycles
+event:0X612 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP97 : (Group 97 pm_smt_priorities4) Cycles thread priority difference is -5 or -6
+event:0X613 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP97 : (Group 97 pm_smt_priorities4) IOPS instructions completed
+event:0X614 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP97 : (Group 97 pm_smt_priorities4) Instructions completed
+event:0X615 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP97 : (Group 97 pm_smt_priorities4) Run cycles
+
+#Group 98 pm_smt_both, Thread common events
+event:0X620 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP98 : (Group 98 pm_smt_both) One of the threads in run cycles
+event:0X621 counters:1 um:zero minimum:1000 name:PM_THRD_GRP_CMPL_BOTH_CYC_GRP98 : (Group 98 pm_smt_both) Cycles group completed by both threads
+event:0X622 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP98 : (Group 98 pm_smt_both) IOPS instructions completed
+event:0X623 counters:3 um:zero minimum:1000 name:PM_THRD_L2MISS_BOTH_CYC_GRP98 : (Group 98 pm_smt_both) Cycles both threads in L2 misses
+event:0X624 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP98 : (Group 98 pm_smt_both) Instructions completed
+event:0X625 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP98 : (Group 98 pm_smt_both) Run cycles
+
+#Group 99 pm_smt_selection, Thread selection
+event:0X630 counters:0 um:zero minimum:1000 name:PM_SNOOP_TLBIE_GRP99 : (Group 99 pm_smt_selection) Snoop TLBIE
+event:0X631 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP99 : (Group 99 pm_smt_selection) IOPS instructions completed
+event:0X632 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_T0_GRP99 : (Group 99 pm_smt_selection) Decode selected thread 0
+event:0X633 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_T1_GRP99 : (Group 99 pm_smt_selection) Decode selected thread 1
+event:0X634 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP99 : (Group 99 pm_smt_selection) Instructions completed
+event:0X635 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP99 : (Group 99 pm_smt_selection) Run cycles
+
+#Group 100 pm_smt_selectover1, Thread selection overide
+event:0X640 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP100 : (Group 100 pm_smt_selectover1) IOPS instructions completed
+event:0X641 counters:1 um:zero minimum:1000 name:PM_0INST_CLB_CYC_GRP100 : (Group 100 pm_smt_selectover1) Cycles no instructions in CLB
+event:0X642 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_OVER_CLB_EMPTY_GRP100 : (Group 100 pm_smt_selectover1) Thread selection overides caused by CLB empty
+event:0X643 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_OVER_GCT_IMBAL_GRP100 : (Group 100 pm_smt_selectover1) Thread selection overides caused by GCT imbalance
+event:0X644 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP100 : (Group 100 pm_smt_selectover1) Instructions completed
+event:0X645 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP100 : (Group 100 pm_smt_selectover1) Run cycles
+
+#Group 101 pm_smt_selectover2, Thread selection overide
+event:0X650 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP101 : (Group 101 pm_smt_selectover2) IOPS instructions completed
+event:0X651 counters:1 um:zero minimum:10000 name:PM_CYC_GRP101 : (Group 101 pm_smt_selectover2) Processor cycles
+event:0X652 counters:2 um:zero minimum:1000 name:PM_THRD_SEL_OVER_ISU_HOLD_GRP101 : (Group 101 pm_smt_selectover2) Thread selection overides caused by ISU holds
+event:0X653 counters:3 um:zero minimum:1000 name:PM_THRD_SEL_OVER_L2MISS_GRP101 : (Group 101 pm_smt_selectover2) Thread selection overides caused by L2 misses
+event:0X654 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP101 : (Group 101 pm_smt_selectover2) Instructions completed
+event:0X655 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP101 : (Group 101 pm_smt_selectover2) Run cycles
+
+#Group 102 pm_fabric1, Fabric events
+event:0X660 counters:0 um:zero minimum:1000 name:PM_FAB_CMD_ISSUED_GRP102 : (Group 102 pm_fabric1) Fabric command issued
+event:0X661 counters:1 um:zero minimum:1000 name:PM_FAB_DCLAIM_ISSUED_GRP102 : (Group 102 pm_fabric1) dclaim issued
+event:0X662 counters:2 um:zero minimum:1000 name:PM_FAB_CMD_RETRIED_GRP102 : (Group 102 pm_fabric1) Fabric command retried
+event:0X663 counters:3 um:zero minimum:1000 name:PM_FAB_DCLAIM_RETRIED_GRP102 : (Group 102 pm_fabric1) dclaim retried
+event:0X664 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP102 : (Group 102 pm_fabric1) Instructions completed
+event:0X665 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP102 : (Group 102 pm_fabric1) Run cycles
+
+#Group 103 pm_fabric2, Fabric data movement
+event:0X670 counters:0 um:zero minimum:1000 name:PM_FAB_P1toM1_SIDECAR_EMPTY_GRP103 : (Group 103 pm_fabric2) P1 to M1 sidecar empty
+event:0X671 counters:1 um:zero minimum:1000 name:PM_FAB_HOLDtoVN_EMPTY_GRP103 : (Group 103 pm_fabric2) Hold buffer to VN empty
+event:0X672 counters:2 um:zero minimum:1000 name:PM_FAB_P1toVNorNN_SIDECAR_EMPTY_GRP103 : (Group 103 pm_fabric2) P1 to VN/NN sidecar empty
+event:0X673 counters:3 um:zero minimum:1000 name:PM_FAB_VBYPASS_EMPTY_GRP103 : (Group 103 pm_fabric2) Vertical bypass buffer empty
+event:0X674 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP103 : (Group 103 pm_fabric2) Instructions completed
+event:0X675 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP103 : (Group 103 pm_fabric2) Run cycles
+
+#Group 104 pm_fabric3, Fabric data movement
+event:0X680 counters:0 um:zero minimum:1000 name:PM_FAB_PNtoNN_DIRECT_GRP104 : (Group 104 pm_fabric3) PN to NN beat went straight to its destination
+event:0X681 counters:1 um:zero minimum:1000 name:PM_FAB_PNtoVN_DIRECT_GRP104 : (Group 104 pm_fabric3) PN to VN beat went straight to its destination
+event:0X682 counters:2 um:zero minimum:1000 name:PM_FAB_PNtoNN_SIDECAR_GRP104 : (Group 104 pm_fabric3) PN to NN beat went to sidecar first
+event:0X683 counters:3 um:zero minimum:1000 name:PM_FAB_PNtoVN_SIDECAR_GRP104 : (Group 104 pm_fabric3) PN to VN beat went to sidecar first
+event:0X684 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP104 : (Group 104 pm_fabric3) Instructions completed
+event:0X685 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP104 : (Group 104 pm_fabric3) Run cycles
+
+#Group 105 pm_fabric4, Fabric data movement
+event:0X690 counters:0 um:zero minimum:1000 name:PM_FAB_M1toP1_SIDECAR_EMPTY_GRP105 : (Group 105 pm_fabric4) M1 to P1 sidecar empty
+event:0X691 counters:1 um:zero minimum:1000 name:PM_FAB_HOLDtoNN_EMPTY_GRP105 : (Group 105 pm_fabric4) Hold buffer to NN empty
+event:0X692 counters:2 um:zero minimum:1000 name:PM_EE_OFF_GRP105 : (Group 105 pm_fabric4) Cycles MSR(EE) bit off
+event:0X693 counters:3 um:zero minimum:1000 name:PM_FAB_M1toVNorNN_SIDECAR_EMPTY_GRP105 : (Group 105 pm_fabric4) M1 to VN/NN sidecar empty
+event:0X694 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP105 : (Group 105 pm_fabric4) Instructions completed
+event:0X695 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP105 : (Group 105 pm_fabric4) Run cycles
+
+#Group 106 pm_snoop1, Snoop retry
+event:0X6A0 counters:0 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_QFULL_GRP106 : (Group 106 pm_snoop1) Snoop read retry due to read queue full
+event:0X6A1 counters:1 um:zero minimum:1000 name:PM_SNOOP_DCLAIM_RETRY_QFULL_GRP106 : (Group 106 pm_snoop1) Snoop dclaim/flush retry due to write/dclaim queues full
+event:0X6A2 counters:2 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_QFULL_GRP106 : (Group 106 pm_snoop1) Snoop read retry due to read queue full
+event:0X6A3 counters:3 um:zero minimum:1000 name:PM_SNOOP_PARTIAL_RTRY_QFULL_GRP106 : (Group 106 pm_snoop1) Snoop partial write retry due to partial-write queues full
+event:0X6A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP106 : (Group 106 pm_snoop1) Instructions completed
+event:0X6A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP106 : (Group 106 pm_snoop1) Run cycles
+
+#Group 107 pm_snoop2, Snoop read retry
+event:0X6B0 counters:0 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_RQ_GRP107 : (Group 107 pm_snoop2) Snoop read retry due to collision with active read queue
+event:0X6B1 counters:1 um:zero minimum:1000 name:PM_SNOOP_RETRY_1AHEAD_GRP107 : (Group 107 pm_snoop2) Snoop retry due to one ahead collision
+event:0X6B2 counters:2 um:zero minimum:1000 name:PM_SNOOP_RD_RETRY_WQ_GRP107 : (Group 107 pm_snoop2) Snoop read retry due to collision with active write queue
+event:0X6B3 counters:3 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP107 : (Group 107 pm_snoop2) IOPS instructions completed
+event:0X6B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP107 : (Group 107 pm_snoop2) Instructions completed
+event:0X6B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP107 : (Group 107 pm_snoop2) Run cycles
+
+#Group 108 pm_snoop3, Snoop write retry
+event:0X6C0 counters:0 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_RQ_GRP108 : (Group 108 pm_snoop3) Snoop write/dclaim retry due to collision with active read queue
+event:0X6C1 counters:1 um:zero minimum:1000 name:PM_MEM_HI_PRIO_WR_CMPL_GRP108 : (Group 108 pm_snoop3) High priority write completed
+event:0X6C2 counters:2 um:zero minimum:1000 name:PM_SNOOP_WR_RETRY_WQ_GRP108 : (Group 108 pm_snoop3) Snoop write/dclaim retry due to collision with active write queue
+event:0X6C3 counters:3 um:zero minimum:1000 name:PM_MEM_LO_PRIO_WR_CMPL_GRP108 : (Group 108 pm_snoop3) Low priority write completed
+event:0X6C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP108 : (Group 108 pm_snoop3) Instructions completed
+event:0X6C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP108 : (Group 108 pm_snoop3) Run cycles
+
+#Group 109 pm_snoop4, Snoop partial write retry
+event:0X6D0 counters:0 um:zero minimum:1000 name:PM_SNOOP_PW_RETRY_RQ_GRP109 : (Group 109 pm_snoop4) Snoop partial-write retry due to collision with active read queue
+event:0X6D1 counters:1 um:zero minimum:1000 name:PM_MEM_HI_PRIO_PW_CMPL_GRP109 : (Group 109 pm_snoop4) High priority partial-write completed
+event:0X6D2 counters:2 um:zero minimum:1000 name:PM_SNOOP_PW_RETRY_WQ_PWQ_GRP109 : (Group 109 pm_snoop4) Snoop partial-write retry due to collision with active write or partial-write queue
+event:0X6D3 counters:3 um:zero minimum:1000 name:PM_MEM_LO_PRIO_PW_CMPL_GRP109 : (Group 109 pm_snoop4) Low priority partial-write completed
+event:0X6D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP109 : (Group 109 pm_snoop4) Instructions completed
+event:0X6D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP109 : (Group 109 pm_snoop4) Run cycles
+
+#Group 110 pm_mem_rq, Memory read queue dispatch
+event:0X6E0 counters:0 um:zero minimum:1000 name:PM_MEM_RQ_DISP_GRP110 : (Group 110 pm_mem_rq) Memory read queue dispatched
+event:0X6E1 counters:1 um:zero minimum:1000 name:PM_MEM_RQ_DISP_BUSY8to15_GRP110 : (Group 110 pm_mem_rq) Memory read queue dispatched with 8-15 queues busy
+event:0X6E2 counters:2 um:zero minimum:1000 name:PM_MEM_RQ_DISP_BUSY1to7_GRP110 : (Group 110 pm_mem_rq) Memory read queue dispatched with 1-7 queues busy
+event:0X6E3 counters:3 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP110 : (Group 110 pm_mem_rq) Cycles MSR(EE) bit off and external interrupt pending
+event:0X6E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP110 : (Group 110 pm_mem_rq) Instructions completed
+event:0X6E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP110 : (Group 110 pm_mem_rq) Run cycles
+
+#Group 111 pm_mem_read, Memory read complete and cancel
+event:0X6F0 counters:0 um:zero minimum:1000 name:PM_MEM_READ_CMPL_GRP111 : (Group 111 pm_mem_read) Memory read completed or canceled
+event:0X6F1 counters:1 um:zero minimum:1000 name:PM_MEM_FAST_PATH_RD_CMPL_GRP111 : (Group 111 pm_mem_read) Fast path memory read completed
+event:0X6F2 counters:2 um:zero minimum:1000 name:PM_MEM_SPEC_RD_CANCEL_GRP111 : (Group 111 pm_mem_read) Speculative memory read canceled
+event:0X6F3 counters:3 um:zero minimum:1000 name:PM_EXT_INT_GRP111 : (Group 111 pm_mem_read) External interrupts
+event:0X6F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP111 : (Group 111 pm_mem_read) Instructions completed
+event:0X6F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP111 : (Group 111 pm_mem_read) Run cycles
+
+#Group 112 pm_mem_wq, Memory write queue dispatch
+event:0X700 counters:0 um:zero minimum:1000 name:PM_MEM_WQ_DISP_WRITE_GRP112 : (Group 112 pm_mem_wq) Memory write queue dispatched due to write
+event:0X701 counters:1 um:zero minimum:1000 name:PM_MEM_WQ_DISP_BUSY1to7_GRP112 : (Group 112 pm_mem_wq) Memory write queue dispatched with 1-7 queues busy
+event:0X702 counters:2 um:zero minimum:1000 name:PM_MEM_WQ_DISP_DCLAIM_GRP112 : (Group 112 pm_mem_wq) Memory write queue dispatched due to dclaim/flush
+event:0X703 counters:3 um:zero minimum:1000 name:PM_MEM_WQ_DISP_BUSY8to15_GRP112 : (Group 112 pm_mem_wq) Memory write queue dispatched with 8-15 queues busy
+event:0X704 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP112 : (Group 112 pm_mem_wq) Instructions completed
+event:0X705 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP112 : (Group 112 pm_mem_wq) Run cycles
+
+#Group 113 pm_mem_pwq, Memory partial write queue
+event:0X710 counters:0 um:zero minimum:1000 name:PM_MEM_PWQ_DISP_GRP113 : (Group 113 pm_mem_pwq) Memory partial-write queue dispatched
+event:0X711 counters:1 um:zero minimum:1000 name:PM_MEM_PWQ_DISP_BUSY2or3_GRP113 : (Group 113 pm_mem_pwq) Memory partial-write queue dispatched with 2-3 queues busy
+event:0X712 counters:2 um:zero minimum:1000 name:PM_MEM_PW_GATH_GRP113 : (Group 113 pm_mem_pwq) Memory partial-write gathered
+event:0X713 counters:3 um:zero minimum:1000 name:PM_MEM_PW_CMPL_GRP113 : (Group 113 pm_mem_pwq) Memory partial-write completed
+event:0X714 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP113 : (Group 113 pm_mem_pwq) Instructions completed
+event:0X715 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP113 : (Group 113 pm_mem_pwq) Run cycles
+
+#Group 114 pm_threshold, Thresholding
+event:0X720 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP114 : (Group 114 pm_threshold) Marked group dispatched
+event:0X721 counters:1 um:zero minimum:1000 name:PM_MRK_IMR_RELOAD_GRP114 : (Group 114 pm_threshold) Marked IMR reloaded
+event:0X722 counters:2 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP114 : (Group 114 pm_threshold) Threshold timeout
+event:0X723 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP114 : (Group 114 pm_threshold) Marked instruction LSU processing finished
+event:0X724 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP114 : (Group 114 pm_threshold) Instructions completed
+event:0X725 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP114 : (Group 114 pm_threshold) Run cycles
+
+#Group 115 pm_mrk_grp1, Marked group events
+event:0X730 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_DISP_GRP115 : (Group 115 pm_mrk_grp1) Marked group dispatched
+event:0X731 counters:1 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP115 : (Group 115 pm_mrk_grp1) Marked L1 D cache store misses
+event:0X732 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP115 : (Group 115 pm_mrk_grp1) Marked instruction finished
+event:0X733 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP115 : (Group 115 pm_mrk_grp1) Marked group completed
+event:0X734 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP115 : (Group 115 pm_mrk_grp1) Instructions completed
+event:0X735 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP115 : (Group 115 pm_mrk_grp1) Run cycles
+
+#Group 116 pm_mrk_grp2, Marked group events
+event:0X740 counters:0 um:zero minimum:1000 name:PM_MRK_GRP_ISSUED_GRP116 : (Group 116 pm_mrk_grp2) Marked group issued
+event:0X741 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP116 : (Group 116 pm_mrk_grp2) Marked instruction BRU processing finished
+event:0X742 counters:2 um:zero minimum:1000 name:PM_MRK_L1_RELOAD_VALID_GRP116 : (Group 116 pm_mrk_grp2) Marked L1 reload data source valid
+event:0X743 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_IC_MISS_GRP116 : (Group 116 pm_mrk_grp2) Group experienced marked I cache miss
+event:0X744 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP116 : (Group 116 pm_mrk_grp2) Instructions completed
+event:0X745 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP116 : (Group 116 pm_mrk_grp2) Run cycles
+
+#Group 117 pm_mrk_dsource1, Marked data from
+event:0X750 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP117 : (Group 117 pm_mrk_dsource1) Marked data loaded from L2
+event:0X751 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_CYC_GRP117 : (Group 117 pm_mrk_dsource1) Marked load latency from L2
+event:0X752 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP117 : (Group 117 pm_mrk_dsource1) Marked data loaded from L2.5 modified
+event:0X753 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_CYC_GRP117 : (Group 117 pm_mrk_dsource1) Marked load latency from L2.5 modified
+event:0X754 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP117 : (Group 117 pm_mrk_dsource1) Instructions completed
+event:0X755 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP117 : (Group 117 pm_mrk_dsource1) Run cycles
+
+#Group 118 pm_mrk_dsource2, Marked data from
+event:0X760 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP118 : (Group 118 pm_mrk_dsource2) Marked data loaded from L2.5 shared
+event:0X761 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_CYC_GRP118 : (Group 118 pm_mrk_dsource2) Marked load latency from L2.5 shared
+event:0X762 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP118 : (Group 118 pm_mrk_dsource2) IOPS instructions completed
+event:0X763 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP118 : (Group 118 pm_mrk_dsource2) FPU produced a result
+event:0X764 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP118 : (Group 118 pm_mrk_dsource2) Instructions completed
+event:0X765 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP118 : (Group 118 pm_mrk_dsource2) Run cycles
+
+#Group 119 pm_mrk_dsource3, Marked data from
+event:0X770 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP119 : (Group 119 pm_mrk_dsource3) Marked data loaded from L3
+event:0X771 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_CYC_GRP119 : (Group 119 pm_mrk_dsource3) Marked load latency from L3
+event:0X772 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_GRP119 : (Group 119 pm_mrk_dsource3) Marked data loaded from L3.5 modified
+event:0X773 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_CYC_GRP119 : (Group 119 pm_mrk_dsource3) Marked load latency from L3.5 modified
+event:0X774 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP119 : (Group 119 pm_mrk_dsource3) Instructions completed
+event:0X775 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP119 : (Group 119 pm_mrk_dsource3) Run cycles
+
+#Group 120 pm_mrk_dsource4, Marked data from
+event:0X780 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_GRP120 : (Group 120 pm_mrk_dsource4) Marked data loaded from remote memory
+event:0X781 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_CYC_GRP120 : (Group 120 pm_mrk_dsource4) Marked load latency from L2.75 shared
+event:0X782 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_GRP120 : (Group 120 pm_mrk_dsource4) Marked data loaded from L2.75 shared
+event:0X783 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_CYC_GRP120 : (Group 120 pm_mrk_dsource4) Marked load latency from remote memory
+event:0X784 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP120 : (Group 120 pm_mrk_dsource4) Instructions completed
+event:0X785 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP120 : (Group 120 pm_mrk_dsource4) Run cycles
+
+#Group 121 pm_mrk_dsource5, Marked data from
+event:0X790 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_GRP121 : (Group 121 pm_mrk_dsource5) Marked data loaded from L3.5 shared
+event:0X791 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_CYC_GRP121 : (Group 121 pm_mrk_dsource5) Marked load latency from L3.5 shared
+event:0X792 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_GRP121 : (Group 121 pm_mrk_dsource5) Marked data loaded from local memory
+event:0X793 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_CYC_GRP121 : (Group 121 pm_mrk_dsource5) Marked load latency from local memory
+event:0X794 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP121 : (Group 121 pm_mrk_dsource5) Instructions completed
+event:0X795 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP121 : (Group 121 pm_mrk_dsource5) Run cycles
+
+#Group 122 pm_mrk_dsource6, Marked data from
+event:0X7A0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_GRP122 : (Group 122 pm_mrk_dsource6) Marked data loaded from L2.75 modified
+event:0X7A1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_SHR_CYC_GRP122 : (Group 122 pm_mrk_dsource6) Marked load latency from L2.75 shared
+event:0X7A2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP122 : (Group 122 pm_mrk_dsource6) IOPS instructions completed
+event:0X7A3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L275_MOD_CYC_GRP122 : (Group 122 pm_mrk_dsource6) Marked load latency from L2.75 modified
+event:0X7A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP122 : (Group 122 pm_mrk_dsource6) Instructions completed
+event:0X7A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP122 : (Group 122 pm_mrk_dsource6) Run cycles
+
+#Group 123 pm_mrk_dsource7, Marked data from
+event:0X7B0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_MOD_GRP123 : (Group 123 pm_mrk_dsource7) Marked data loaded from L3.75 modified
+event:0X7B1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_SHR_CYC_GRP123 : (Group 123 pm_mrk_dsource7) Marked load latency from L3.75 shared
+event:0X7B2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_SHR_GRP123 : (Group 123 pm_mrk_dsource7) Marked data loaded from L3.75 shared
+event:0X7B3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L375_MOD_CYC_GRP123 : (Group 123 pm_mrk_dsource7) Marked load latency from L3.75 modified
+event:0X7B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP123 : (Group 123 pm_mrk_dsource7) Instructions completed
+event:0X7B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP123 : (Group 123 pm_mrk_dsource7) Run cycles
+
+#Group 124 pm_mrk_lbmiss, Marked TLB and SLB misses
+event:0X7C0 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP124 : (Group 124 pm_mrk_lbmiss) Marked Data TLB misses for 4K page
+event:0X7C1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16M_GRP124 : (Group 124 pm_mrk_lbmiss) Marked Data TLB misses for 16M page
+event:0X7C2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_GRP124 : (Group 124 pm_mrk_lbmiss) Marked Data TLB misses
+event:0X7C3 counters:3 um:zero minimum:1000 name:PM_MRK_DSLB_MISS_GRP124 : (Group 124 pm_mrk_lbmiss) Marked Data SLB misses
+event:0X7C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP124 : (Group 124 pm_mrk_lbmiss) Instructions completed
+event:0X7C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP124 : (Group 124 pm_mrk_lbmiss) Run cycles
+
+#Group 125 pm_mrk_lbref, Marked TLB and SLB references
+event:0X7D0 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_REF_4K_GRP125 : (Group 125 pm_mrk_lbref) Marked Data TLB reference for 4K page
+event:0X7D1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_REF_16M_GRP125 : (Group 125 pm_mrk_lbref) Marked Data TLB reference for 16M page
+event:0X7D2 counters:2 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP125 : (Group 125 pm_mrk_lbref) IOPS instructions completed
+event:0X7D3 counters:3 um:zero minimum:1000 name:PM_MRK_DSLB_MISS_GRP125 : (Group 125 pm_mrk_lbref) Marked Data SLB misses
+event:0X7D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP125 : (Group 125 pm_mrk_lbref) Instructions completed
+event:0X7D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP125 : (Group 125 pm_mrk_lbref) Run cycles
+
+#Group 126 pm_mrk_lsmiss, Marked load and store miss
+event:0X7E0 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP126 : (Group 126 pm_mrk_lsmiss) Marked L1 D cache load misses
+event:0X7E1 counters:1 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP126 : (Group 126 pm_mrk_lsmiss) IOPS instructions completed
+event:0X7E2 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP126 : (Group 126 pm_mrk_lsmiss) Marked store completed with intervention
+event:0X7E3 counters:3 um:zero minimum:1000 name:PM_MRK_CRU_FIN_GRP126 : (Group 126 pm_mrk_lsmiss) Marked instruction CRU processing finished
+event:0X7E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP126 : (Group 126 pm_mrk_lsmiss) Instructions completed
+event:0X7E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP126 : (Group 126 pm_mrk_lsmiss) Run cycles
+
+#Group 127 pm_mrk_ulsflush, Mark unaligned load and store flushes
+event:0X7F0 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP127 : (Group 127 pm_mrk_ulsflush) Marked store instruction completed
+event:0X7F1 counters:1 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP127 : (Group 127 pm_mrk_ulsflush) Marked L1 D cache store misses
+event:0X7F2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_UST_GRP127 : (Group 127 pm_mrk_ulsflush) Marked unaligned store flushes
+event:0X7F3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_ULD_GRP127 : (Group 127 pm_mrk_ulsflush) Marked unaligned load flushes
+event:0X7F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP127 : (Group 127 pm_mrk_ulsflush) Instructions completed
+event:0X7F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP127 : (Group 127 pm_mrk_ulsflush) Run cycles
+
+#Group 128 pm_mrk_misc, Misc marked instructions
+event:0X800 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP128 : (Group 128 pm_mrk_misc) Marked STCX failed
+event:0X801 counters:1 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP128 : (Group 128 pm_mrk_misc) Marked store sent to GPS
+event:0X802 counters:2 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP128 : (Group 128 pm_mrk_misc) Marked instruction FPU processing finished
+event:0X803 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_TIMEO_GRP128 : (Group 128 pm_mrk_misc) Marked group completion timeout
+event:0X804 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP128 : (Group 128 pm_mrk_misc) Instructions completed
+event:0X805 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP128 : (Group 128 pm_mrk_misc) Run cycles
+
+#Group 129 pm_lsref_L1, Load/Store operations and L1 activity
+event:0X810 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP129 : (Group 129 pm_lsref_L1) Data loaded from L2
+event:0X811 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP129 : (Group 129 pm_lsref_L1) Instruction fetched from L1
+event:0X812 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP129 : (Group 129 pm_lsref_L1) L1 D cache store references
+event:0X813 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP129 : (Group 129 pm_lsref_L1) L1 D cache load references
+event:0X814 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP129 : (Group 129 pm_lsref_L1) Instructions completed
+event:0X815 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP129 : (Group 129 pm_lsref_L1) Run cycles
+
+#Group 130 pm_lsref_L2L3, Load/Store operations and L2,L3 activity
+event:0X820 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP130 : (Group 130 pm_lsref_L2L3) Data loaded from L3
+event:0X821 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP130 : (Group 130 pm_lsref_L2L3) Data loaded from local memory
+event:0X822 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP130 : (Group 130 pm_lsref_L2L3) L1 D cache store references
+event:0X823 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP130 : (Group 130 pm_lsref_L2L3) L1 D cache load references
+event:0X824 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP130 : (Group 130 pm_lsref_L2L3) Instructions completed
+event:0X825 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP130 : (Group 130 pm_lsref_L2L3) Run cycles
+
+#Group 131 pm_lsref_tlbmiss, Load/Store operations and TLB misses
+event:0X830 counters:0 um:zero minimum:1000 name:PM_ITLB_MISS_GRP131 : (Group 131 pm_lsref_tlbmiss) Instruction TLB misses
+event:0X831 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_GRP131 : (Group 131 pm_lsref_tlbmiss) Data TLB misses
+event:0X832 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP131 : (Group 131 pm_lsref_tlbmiss) L1 D cache store references
+event:0X833 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP131 : (Group 131 pm_lsref_tlbmiss) L1 D cache load references
+event:0X834 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP131 : (Group 131 pm_lsref_tlbmiss) Instructions completed
+event:0X835 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP131 : (Group 131 pm_lsref_tlbmiss) Run cycles
+
+#Group 132 pm_Dmiss, Data cache misses
+event:0X840 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP132 : (Group 132 pm_Dmiss) Data loaded from L3
+event:0X841 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP132 : (Group 132 pm_Dmiss) Data loaded from local memory
+event:0X842 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP132 : (Group 132 pm_Dmiss) L1 D cache load misses
+event:0X843 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP132 : (Group 132 pm_Dmiss) L1 D cache store misses
+event:0X844 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP132 : (Group 132 pm_Dmiss) Instructions completed
+event:0X845 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP132 : (Group 132 pm_Dmiss) Run cycles
+
+#Group 133 pm_prefetchX, Prefetch events
+event:0X850 counters:0 um:zero minimum:10000 name:PM_CYC_GRP133 : (Group 133 pm_prefetchX) Processor cycles
+event:0X851 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP133 : (Group 133 pm_prefetchX) Instruction prefetch requests
+event:0X852 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP133 : (Group 133 pm_prefetchX) L1 cache data prefetches
+event:0X853 counters:3 um:zero minimum:1000 name:PM_L2_PREF_GRP133 : (Group 133 pm_prefetchX) L2 cache prefetches
+event:0X854 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP133 : (Group 133 pm_prefetchX) Instructions completed
+event:0X855 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP133 : (Group 133 pm_prefetchX) Run cycles
+
+#Group 134 pm_branchX, Branch operations
+event:0X860 counters:0 um:zero minimum:1000 name:PM_BR_UNCOND_GRP134 : (Group 134 pm_branchX) Unconditional branch
+event:0X861 counters:1 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP134 : (Group 134 pm_branchX) A conditional branch was predicted, target prediction
+event:0X862 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP134 : (Group 134 pm_branchX) A conditional branch was predicted, CR prediction
+event:0X863 counters:3 um:zero minimum:1000 name:PM_BR_ISSUED_GRP134 : (Group 134 pm_branchX) Branches issued
+event:0X864 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP134 : (Group 134 pm_branchX) Instructions completed
+event:0X865 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP134 : (Group 134 pm_branchX) Run cycles
+
+#Group 135 pm_fpuX1, Floating point events by unit
+event:0X870 counters:0 um:zero minimum:1000 name:PM_FPU0_STALL3_GRP135 : (Group 135 pm_fpuX1) FPU0 stalled in pipe3
+event:0X871 counters:1 um:zero minimum:1000 name:PM_FPU1_STALL3_GRP135 : (Group 135 pm_fpuX1) FPU1 stalled in pipe3
+event:0X872 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP135 : (Group 135 pm_fpuX1) FPU0 produced a result
+event:0X873 counters:3 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP135 : (Group 135 pm_fpuX1) FPU0 executed FPSCR instruction
+event:0X874 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP135 : (Group 135 pm_fpuX1) Instructions completed
+event:0X875 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP135 : (Group 135 pm_fpuX1) Run cycles
+
+#Group 136 pm_fpuX2, Floating point events by unit
+event:0X880 counters:0 um:zero minimum:1000 name:PM_FPU0_FMA_GRP136 : (Group 136 pm_fpuX2) FPU0 executed multiply-add instruction
+event:0X881 counters:1 um:zero minimum:1000 name:PM_FPU1_FMA_GRP136 : (Group 136 pm_fpuX2) FPU1 executed multiply-add instruction
+event:0X882 counters:2 um:zero minimum:1000 name:PM_FPU0_FRSP_FCONV_GRP136 : (Group 136 pm_fpuX2) FPU0 executed FRSP or FCONV instructions
+event:0X883 counters:3 um:zero minimum:1000 name:PM_FPU1_FRSP_FCONV_GRP136 : (Group 136 pm_fpuX2) FPU1 executed FRSP or FCONV instructions
+event:0X884 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP136 : (Group 136 pm_fpuX2) Instructions completed
+event:0X885 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP136 : (Group 136 pm_fpuX2) Run cycles
+
+#Group 137 pm_fpuX3, Floating point events by unit
+event:0X890 counters:0 um:zero minimum:1000 name:PM_FPU0_1FLOP_GRP137 : (Group 137 pm_fpuX3) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X891 counters:1 um:zero minimum:1000 name:PM_FPU1_1FLOP_GRP137 : (Group 137 pm_fpuX3) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X892 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP137 : (Group 137 pm_fpuX3) FPU0 produced a result
+event:0X893 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP137 : (Group 137 pm_fpuX3) FPU1 produced a result
+event:0X894 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP137 : (Group 137 pm_fpuX3) Instructions completed
+event:0X895 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP137 : (Group 137 pm_fpuX3) Run cycles
+
+#Group 138 pm_fpuX4, Floating point and L1 events
+event:0X8A0 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP138 : (Group 138 pm_fpuX4) FPU executed one flop instruction
+event:0X8A1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP138 : (Group 138 pm_fpuX4) FPU executed multiply-add instruction
+event:0X8A2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP138 : (Group 138 pm_fpuX4) L1 D cache store references
+event:0X8A3 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP138 : (Group 138 pm_fpuX4) L1 D cache load references
+event:0X8A4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP138 : (Group 138 pm_fpuX4) Instructions completed
+event:0X8A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP138 : (Group 138 pm_fpuX4) Run cycles
+
+#Group 139 pm_fpuX5, Floating point events
+event:0X8B0 counters:0 um:zero minimum:1000 name:PM_FPU_SINGLE_GRP139 : (Group 139 pm_fpuX5) FPU executed single precision instruction
+event:0X8B1 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP139 : (Group 139 pm_fpuX5) FPU executed store instruction
+event:0X8B2 counters:2 um:zero minimum:1000 name:PM_FPU0_FIN_GRP139 : (Group 139 pm_fpuX5) FPU0 produced a result
+event:0X8B3 counters:3 um:zero minimum:1000 name:PM_FPU1_FIN_GRP139 : (Group 139 pm_fpuX5) FPU1 produced a result
+event:0X8B4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP139 : (Group 139 pm_fpuX5) Instructions completed
+event:0X8B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP139 : (Group 139 pm_fpuX5) Run cycles
+
+#Group 140 pm_fpuX6, Floating point events
+event:0X8C0 counters:0 um:zero minimum:1000 name:PM_FPU_FDIV_GRP140 : (Group 140 pm_fpuX6) FPU executed FDIV instruction
+event:0X8C1 counters:1 um:zero minimum:1000 name:PM_FPU_FSQRT_GRP140 : (Group 140 pm_fpuX6) FPU executed FSQRT instruction
+event:0X8C2 counters:2 um:zero minimum:1000 name:PM_FPU_FRSP_FCONV_GRP140 : (Group 140 pm_fpuX6) FPU executed FRSP or FCONV instructions
+event:0X8C3 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP140 : (Group 140 pm_fpuX6) FPU produced a result
+event:0X8C4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP140 : (Group 140 pm_fpuX6) Instructions completed
+event:0X8C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP140 : (Group 140 pm_fpuX6) Run cycles
+
+#Group 141 pm_hpmcount1, HPM group for set 1
+event:0X8D0 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP141 : (Group 141 pm_hpmcount1) FPU executed one flop instruction
+event:0X8D1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP141 : (Group 141 pm_hpmcount1) Processor cycles
+event:0X8D2 counters:2 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP141 : (Group 141 pm_hpmcount1) Marked instruction FPU processing finished
+event:0X8D3 counters:3 um:zero minimum:1000 name:PM_FPU_FIN_GRP141 : (Group 141 pm_hpmcount1) FPU produced a result
+event:0X8D4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP141 : (Group 141 pm_hpmcount1) Instructions completed
+event:0X8D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP141 : (Group 141 pm_hpmcount1) Run cycles
+
+#Group 142 pm_hpmcount2, HPM group for set 2
+event:0X8E0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP142 : (Group 142 pm_hpmcount2) Processor cycles
+event:0X8E1 counters:1 um:zero minimum:1000 name:PM_FPU_STF_GRP142 : (Group 142 pm_hpmcount2) FPU executed store instruction
+event:0X8E2 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP142 : (Group 142 pm_hpmcount2) Instructions dispatched
+event:0X8E3 counters:3 um:zero minimum:1000 name:PM_LSU_LDF_GRP142 : (Group 142 pm_hpmcount2) LSU executed Floating Point load instruction
+event:0X8E4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP142 : (Group 142 pm_hpmcount2) Instructions completed
+event:0X8E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP142 : (Group 142 pm_hpmcount2) Run cycles
+
+#Group 143 pm_hpmcount3, HPM group for set 3
+event:0X8F0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP143 : (Group 143 pm_hpmcount3) Processor cycles
+event:0X8F1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_ATTEMPT_GRP143 : (Group 143 pm_hpmcount3) Instructions dispatch attempted
+event:0X8F2 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP143 : (Group 143 pm_hpmcount3) L1 D cache load misses
+event:0X8F3 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP143 : (Group 143 pm_hpmcount3) L1 D cache store misses
+event:0X8F4 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP143 : (Group 143 pm_hpmcount3) Instructions completed
+event:0X8F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP143 : (Group 143 pm_hpmcount3) Run cycles
+
+#Group 144 pm_hpmcount4, HPM group for set 7
+event:0X900 counters:0 um:zero minimum:1000 name:PM_TLB_MISS_GRP144 : (Group 144 pm_hpmcount4) TLB misses
+event:0X901 counters:1 um:zero minimum:10000 name:PM_CYC_GRP144 : (Group 144 pm_hpmcount4) Processor cycles
+event:0X902 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP144 : (Group 144 pm_hpmcount4) L1 D cache store references
+event:0X903 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP144 : (Group 144 pm_hpmcount4) L1 D cache load references
+event:0X904 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP144 : (Group 144 pm_hpmcount4) Instructions completed
+event:0X905 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP144 : (Group 144 pm_hpmcount4) Run cycles
+
+#Group 145 pm_hpmcount5, HPM group for set 9
+event:0X910 counters:0 um:zero minimum:10000 name:PM_CYC_GRP145 : (Group 145 pm_hpmcount5) Processor cycles
+event:0X911 counters:1 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP145 : (Group 145 pm_hpmcount5) Marked instruction FXU processing finished
+event:0X912 counters:2 um:zero minimum:1000 name:PM_FXU_FIN_GRP145 : (Group 145 pm_hpmcount5) FXU produced a result
+event:0X913 counters:3 um:zero minimum:1000 name:PM_FXU0_FIN_GRP145 : (Group 145 pm_hpmcount5) FXU0 produced a result
+event:0X914 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP145 : (Group 145 pm_hpmcount5) Instructions completed
+event:0X915 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP145 : (Group 145 pm_hpmcount5) Run cycles
+
+#Group 146 pm_eprof1, Group for use with eprof
+event:0X920 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP146 : (Group 146 pm_eprof1) Instructions completed
+event:0X921 counters:1 um:zero minimum:10000 name:PM_CYC_GRP146 : (Group 146 pm_eprof1) Processor cycles
+event:0X922 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP146 : (Group 146 pm_eprof1) L1 D cache load misses
+event:0X923 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP146 : (Group 146 pm_eprof1) L1 D cache entries invalidated from L2
+event:0X924 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP146 : (Group 146 pm_eprof1) Instructions completed
+event:0X925 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP146 : (Group 146 pm_eprof1) Run cycles
+
+#Group 147 pm_eprof2, Group for use with eprof
+event:0X930 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP147 : (Group 147 pm_eprof2) Marked L1 D cache load misses
+event:0X931 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP147 : (Group 147 pm_eprof2) Instructions completed
+event:0X932 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP147 : (Group 147 pm_eprof2) L1 D cache store references
+event:0X933 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP147 : (Group 147 pm_eprof2) L1 D cache load references
+event:0X934 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP147 : (Group 147 pm_eprof2) Instructions completed
+event:0X935 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP147 : (Group 147 pm_eprof2) Run cycles
+
+#Group 148 pm_eprof3, Group for use with eprof
+event:0X940 counters:0 um:zero minimum:1000 name:PM_MRK_ST_MISS_L1_GRP148 : (Group 148 pm_eprof3) Marked L1 D cache store misses
+event:0X941 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP148 : (Group 148 pm_eprof3) Instructions completed
+event:0X942 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP148 : (Group 148 pm_eprof3) Instructions dispatched
+event:0X943 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP148 : (Group 148 pm_eprof3) L1 D cache store misses
+event:0X944 counters:4 um:zero minimum:10000 name:PM_INST_CMPL_GRP148 : (Group 148 pm_eprof3) Instructions completed
+event:0X945 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP148 : (Group 148 pm_eprof3) Run cycles
diff --git a/events/ppc64/power5/unit_masks b/events/ppc64/power5/unit_masks
new file mode 100644
index 0000000..b2e5f30
--- /dev/null
+++ b/events/ppc64/power5/unit_masks
@@ -0,0 +1,4 @@
+# ppc64 POWER5 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/power6/event_mappings b/events/ppc64/power6/event_mappings
new file mode 100644
index 0000000..0d627b3
--- /dev/null
+++ b/events/ppc64/power6/event_mappings
@@ -0,0 +1,1201 @@
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2007.
+# Contributed by Dave Nomura <dcnltc@us.ibm.com>.
+#
+#Mapping of event groups to MMCR values
+
+
+#Group Default
+event:0X001 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+
+#Group 0 with random sampling
+event:0X002 mmcr0:0X00000000 mmcr1:0X000000001E1E021A mmcra:0X00000001
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X0010 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X0011 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X0012 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+event:0X0013 mmcr0:0X00000000 mmcr1:0X000000000A02121E mmcra:0X00000000
+
+#Group 2 pm_utilization_capacity, CPU utilization and capacity
+event:0X0020 mmcr0:0X00000000 mmcr1:0X00000000FA1EF4F4 mmcra:0X00000000
+event:0X0021 mmcr0:0X00000000 mmcr1:0X00000000FA1EF4F4 mmcra:0X00000000
+event:0X0022 mmcr0:0X00000000 mmcr1:0X00000000FA1EF4F4 mmcra:0X00000000
+event:0X0023 mmcr0:0X00000000 mmcr1:0X00000000FA1EF4F4 mmcra:0X00000000
+
+#Group 3 pm_branch, Branch operations
+event:0X0030 mmcr0:0X00000000 mmcr1:0X04000000A2A8808A mmcra:0X00000000
+event:0X0031 mmcr0:0X00000000 mmcr1:0X04000000A2A8808A mmcra:0X00000000
+event:0X0032 mmcr0:0X00000000 mmcr1:0X04000000A2A8808A mmcra:0X00000000
+event:0X0033 mmcr0:0X00000000 mmcr1:0X04000000A2A8808A mmcra:0X00000000
+
+#Group 4 pm_branch2, Branch operations
+event:0X0040 mmcr0:0X00000000 mmcr1:0X04000000A4A68E8C mmcra:0X00000000
+event:0X0041 mmcr0:0X00000000 mmcr1:0X04000000A4A68E8C mmcra:0X00000000
+event:0X0042 mmcr0:0X00000000 mmcr1:0X04000000A4A68E8C mmcra:0X00000000
+event:0X0043 mmcr0:0X00000000 mmcr1:0X04000000A4A68E8C mmcra:0X00000000
+
+#Group 5 pm_branch3, Branch operations
+event:0X0050 mmcr0:0X00000000 mmcr1:0X04000000A0A28486 mmcra:0X00000000
+event:0X0051 mmcr0:0X00000000 mmcr1:0X04000000A0A28486 mmcra:0X00000000
+event:0X0052 mmcr0:0X00000000 mmcr1:0X04000000A0A28486 mmcra:0X00000000
+event:0X0053 mmcr0:0X00000000 mmcr1:0X04000000A0A28486 mmcra:0X00000000
+
+#Group 6 pm_branch4, Branch operations
+event:0X0060 mmcr0:0X00000000 mmcr1:0X04000000A8AA8C8E mmcra:0X00000000
+event:0X0061 mmcr0:0X00000000 mmcr1:0X04000000A8AA8C8E mmcra:0X00000000
+event:0X0062 mmcr0:0X00000000 mmcr1:0X04000000A8AA8C8E mmcra:0X00000000
+event:0X0063 mmcr0:0X00000000 mmcr1:0X04000000A8AA8C8E mmcra:0X00000000
+
+#Group 7 pm_branch5, Branch operations
+event:0X0070 mmcr0:0X00000000 mmcr1:0X04040000A052C652 mmcra:0X00000000
+event:0X0071 mmcr0:0X00000000 mmcr1:0X04040000A052C652 mmcra:0X00000000
+event:0X0072 mmcr0:0X00000000 mmcr1:0X04040000A052C652 mmcra:0X00000000
+event:0X0073 mmcr0:0X00000000 mmcr1:0X04040000A052C652 mmcra:0X00000000
+
+#Group 8 pm_dsource, Data source
+event:0X0080 mmcr0:0X00000000 mmcr1:0X0000000058585656 mmcra:0X00000000
+event:0X0081 mmcr0:0X00000000 mmcr1:0X0000000058585656 mmcra:0X00000000
+event:0X0082 mmcr0:0X00000000 mmcr1:0X0000000058585656 mmcra:0X00000000
+event:0X0083 mmcr0:0X00000000 mmcr1:0X0000000058585656 mmcra:0X00000000
+
+#Group 9 pm_dsource2, Data sources
+event:0X0090 mmcr0:0X00000000 mmcr1:0X000000005A5A5856 mmcra:0X00000000
+event:0X0091 mmcr0:0X00000000 mmcr1:0X000000005A5A5856 mmcra:0X00000000
+event:0X0092 mmcr0:0X00000000 mmcr1:0X000000005A5A5856 mmcra:0X00000000
+event:0X0093 mmcr0:0X00000000 mmcr1:0X000000005A5A5856 mmcra:0X00000000
+
+#Group 10 pm_dsource3, Data sources
+event:0X00A0 mmcr0:0X00000000 mmcr1:0X000000005A5A5A5A mmcra:0X00000000
+event:0X00A1 mmcr0:0X00000000 mmcr1:0X000000005A5A5A5A mmcra:0X00000000
+event:0X00A2 mmcr0:0X00000000 mmcr1:0X000000005A5A5A5A mmcra:0X00000000
+event:0X00A3 mmcr0:0X00000000 mmcr1:0X000000005A5A5A5A mmcra:0X00000000
+
+#Group 11 pm_dsource4, Data sources
+event:0X00B0 mmcr0:0X00000000 mmcr1:0X000000005C5C5C5C mmcra:0X00000000
+event:0X00B1 mmcr0:0X00000000 mmcr1:0X000000005C5C5C5C mmcra:0X00000000
+event:0X00B2 mmcr0:0X00000000 mmcr1:0X000000005C5C5C5C mmcra:0X00000000
+event:0X00B3 mmcr0:0X00000000 mmcr1:0X000000005C5C5C5C mmcra:0X00000000
+
+#Group 12 pm_dsource5, Data sources
+event:0X00C0 mmcr0:0X00000000 mmcr1:0X000000005E5E5E5E mmcra:0X00000000
+event:0X00C1 mmcr0:0X00000000 mmcr1:0X000000005E5E5E5E mmcra:0X00000000
+event:0X00C2 mmcr0:0X00000000 mmcr1:0X000000005E5E5E5E mmcra:0X00000000
+event:0X00C3 mmcr0:0X00000000 mmcr1:0X000000005E5E5E5E mmcra:0X00000000
+
+#Group 13 pm_dlatencies, Data latencies
+event:0X00D0 mmcr0:0X00000000 mmcr1:0X000000000C281E24 mmcra:0X00000000
+event:0X00D1 mmcr0:0X00000000 mmcr1:0X000000000C281E24 mmcra:0X00000000
+event:0X00D2 mmcr0:0X00000000 mmcr1:0X000000000C281E24 mmcra:0X00000000
+event:0X00D3 mmcr0:0X00000000 mmcr1:0X000000000C281E24 mmcra:0X00000000
+
+#Group 14 pm_dlatencies2, Data latencies
+event:0X00E0 mmcr0:0X00000000 mmcr1:0X00000000022C1E2A mmcra:0X00000000
+event:0X00E1 mmcr0:0X00000000 mmcr1:0X00000000022C1E2A mmcra:0X00000000
+event:0X00E2 mmcr0:0X00000000 mmcr1:0X00000000022C1E2A mmcra:0X00000000
+event:0X00E3 mmcr0:0X00000000 mmcr1:0X00000000022C1E2A mmcra:0X00000000
+
+#Group 15 pm_dlatencies3, Data latencies
+event:0X00F0 mmcr0:0X00000000 mmcr1:0X00000000022E5E2C mmcra:0X00000000
+event:0X00F1 mmcr0:0X00000000 mmcr1:0X00000000022E5E2C mmcra:0X00000000
+event:0X00F2 mmcr0:0X00000000 mmcr1:0X00000000022E5E2C mmcra:0X00000000
+event:0X00F3 mmcr0:0X00000000 mmcr1:0X00000000022E5E2C mmcra:0X00000000
+
+#Group 16 pm_dlatencies4, Data latencies
+event:0X0100 mmcr0:0X00000000 mmcr1:0X000000005A2A5C26 mmcra:0X00000000
+event:0X0101 mmcr0:0X00000000 mmcr1:0X000000005A2A5C26 mmcra:0X00000000
+event:0X0102 mmcr0:0X00000000 mmcr1:0X000000005A2A5C26 mmcra:0X00000000
+event:0X0103 mmcr0:0X00000000 mmcr1:0X000000005A2A5C26 mmcra:0X00000000
+
+#Group 17 pm_dlatencies5, Data latencies
+event:0X0110 mmcr0:0X00000000 mmcr1:0X000000005C225828 mmcra:0X00000000
+event:0X0111 mmcr0:0X00000000 mmcr1:0X000000005C225828 mmcra:0X00000000
+event:0X0112 mmcr0:0X00000000 mmcr1:0X000000005C225828 mmcra:0X00000000
+event:0X0113 mmcr0:0X00000000 mmcr1:0X000000005C225828 mmcra:0X00000000
+
+#Group 18 pm_dlatencies6, Data latencies
+event:0X0120 mmcr0:0X00000000 mmcr1:0X000000005E245A2E mmcra:0X00000000
+event:0X0121 mmcr0:0X00000000 mmcr1:0X000000005E245A2E mmcra:0X00000000
+event:0X0122 mmcr0:0X00000000 mmcr1:0X000000005E245A2E mmcra:0X00000000
+event:0X0123 mmcr0:0X00000000 mmcr1:0X000000005E245A2E mmcra:0X00000000
+
+#Group 19 pm_dlatencies7, Data latencies
+event:0X0130 mmcr0:0X00000000 mmcr1:0X000000005820120E mmcra:0X00000000
+event:0X0131 mmcr0:0X00000000 mmcr1:0X000000005820120E mmcra:0X00000000
+event:0X0132 mmcr0:0X00000000 mmcr1:0X000000005820120E mmcra:0X00000000
+event:0X0133 mmcr0:0X00000000 mmcr1:0X000000005820120E mmcra:0X00000000
+
+#Group 20 pm_dlatencies8, Data latencies
+event:0X0140 mmcr0:0X00000000 mmcr1:0X0000000010581E20 mmcra:0X00000000
+event:0X0141 mmcr0:0X00000000 mmcr1:0X0000000010581E20 mmcra:0X00000000
+event:0X0142 mmcr0:0X00000000 mmcr1:0X0000000010581E20 mmcra:0X00000000
+event:0X0143 mmcr0:0X00000000 mmcr1:0X0000000010581E20 mmcra:0X00000000
+
+#Group 21 pm_dlatencies9, Data latencies
+event:0X0150 mmcr0:0X00000000 mmcr1:0X00000000122C125E mmcra:0X00000000
+event:0X0151 mmcr0:0X00000000 mmcr1:0X00000000122C125E mmcra:0X00000000
+event:0X0152 mmcr0:0X00000000 mmcr1:0X00000000122C125E mmcra:0X00000000
+event:0X0153 mmcr0:0X00000000 mmcr1:0X00000000122C125E mmcra:0X00000000
+
+#Group 22 pm_dlatencies10, Data latencies
+event:0X0160 mmcr0:0X00000000 mmcr1:0X000000005A261E26 mmcra:0X00000000
+event:0X0161 mmcr0:0X00000000 mmcr1:0X000000005A261E26 mmcra:0X00000000
+event:0X0162 mmcr0:0X00000000 mmcr1:0X000000005A261E26 mmcra:0X00000000
+event:0X0163 mmcr0:0X00000000 mmcr1:0X000000005A261E26 mmcra:0X00000000
+
+#Group 23 pm_isource, Instruction sources
+event:0X0170 mmcr0:0X00000000 mmcr1:0X0040000040404654 mmcra:0X00000000
+event:0X0171 mmcr0:0X00000000 mmcr1:0X0040000040404654 mmcra:0X00000000
+event:0X0172 mmcr0:0X00000000 mmcr1:0X0040000040404654 mmcra:0X00000000
+event:0X0173 mmcr0:0X00000000 mmcr1:0X0040000040404654 mmcra:0X00000000
+
+#Group 24 pm_isource2, Instruction sources
+event:0X0180 mmcr0:0X00000000 mmcr1:0X0040000046464046 mmcra:0X00000000
+event:0X0181 mmcr0:0X00000000 mmcr1:0X0040000046464046 mmcra:0X00000000
+event:0X0182 mmcr0:0X00000000 mmcr1:0X0040000046464046 mmcra:0X00000000
+event:0X0183 mmcr0:0X00000000 mmcr1:0X0040000046464046 mmcra:0X00000000
+
+#Group 25 pm_isource3, Instruction sources
+event:0X0190 mmcr0:0X00000000 mmcr1:0X0040000044444444 mmcra:0X00000000
+event:0X0191 mmcr0:0X00000000 mmcr1:0X0040000044444444 mmcra:0X00000000
+event:0X0192 mmcr0:0X00000000 mmcr1:0X0040000044444444 mmcra:0X00000000
+event:0X0193 mmcr0:0X00000000 mmcr1:0X0040000044444444 mmcra:0X00000000
+
+#Group 26 pm_isource4, Instruction sources
+event:0X01A0 mmcr0:0X00000000 mmcr1:0X0040000042424242 mmcra:0X00000000
+event:0X01A1 mmcr0:0X00000000 mmcr1:0X0040000042424242 mmcra:0X00000000
+event:0X01A2 mmcr0:0X00000000 mmcr1:0X0040000042424242 mmcra:0X00000000
+event:0X01A3 mmcr0:0X00000000 mmcr1:0X0040000042424242 mmcra:0X00000000
+
+#Group 27 pm_isource5, Instruction sources
+event:0X01B0 mmcr0:0X00000000 mmcr1:0X0040000040405454 mmcra:0X00000000
+event:0X01B1 mmcr0:0X00000000 mmcr1:0X0040000040405454 mmcra:0X00000000
+event:0X01B2 mmcr0:0X00000000 mmcr1:0X0040000040405454 mmcra:0X00000000
+event:0X01B3 mmcr0:0X00000000 mmcr1:0X0040000040405454 mmcra:0X00000000
+
+#Group 28 pm_pteg, PTEG sources
+event:0X01C0 mmcr0:0X00000000 mmcr1:0X0001000048484E4E mmcra:0X00000000
+event:0X01C1 mmcr0:0X00000000 mmcr1:0X0001000048484E4E mmcra:0X00000000
+event:0X01C2 mmcr0:0X00000000 mmcr1:0X0001000048484E4E mmcra:0X00000000
+event:0X01C3 mmcr0:0X00000000 mmcr1:0X0001000048484E4E mmcra:0X00000000
+
+#Group 29 pm_pteg2, PTEG sources
+event:0X01D0 mmcr0:0X00000000 mmcr1:0X000100002848484C mmcra:0X00000000
+event:0X01D1 mmcr0:0X00000000 mmcr1:0X000100002848484C mmcra:0X00000000
+event:0X01D2 mmcr0:0X00000000 mmcr1:0X000100002848484C mmcra:0X00000000
+event:0X01D3 mmcr0:0X00000000 mmcr1:0X000100002848484C mmcra:0X00000000
+
+#Group 30 pm_pteg3, PTEG sources
+event:0X01E0 mmcr0:0X00000000 mmcr1:0X000100004E4E284A mmcra:0X00000000
+event:0X01E1 mmcr0:0X00000000 mmcr1:0X000100004E4E284A mmcra:0X00000000
+event:0X01E2 mmcr0:0X00000000 mmcr1:0X000100004E4E284A mmcra:0X00000000
+event:0X01E3 mmcr0:0X00000000 mmcr1:0X000100004E4E284A mmcra:0X00000000
+
+#Group 31 pm_pteg4, PTEG sources
+event:0X01F0 mmcr0:0X00000000 mmcr1:0X000100004A4A4A4A mmcra:0X00000000
+event:0X01F1 mmcr0:0X00000000 mmcr1:0X000100004A4A4A4A mmcra:0X00000000
+event:0X01F2 mmcr0:0X00000000 mmcr1:0X000100004A4A4A4A mmcra:0X00000000
+event:0X01F3 mmcr0:0X00000000 mmcr1:0X000100004A4A4A4A mmcra:0X00000000
+
+#Group 32 pm_pteg5, PTEG sources
+event:0X0200 mmcr0:0X00000000 mmcr1:0X000100004C4C4CC8 mmcra:0X00000000
+event:0X0201 mmcr0:0X00000000 mmcr1:0X000100004C4C4CC8 mmcra:0X00000000
+event:0X0202 mmcr0:0X00000000 mmcr1:0X000100004C4C4CC8 mmcra:0X00000000
+event:0X0203 mmcr0:0X00000000 mmcr1:0X000100004C4C4CC8 mmcra:0X00000000
+
+#Group 33 pm_data_tablewalk, Data tablewalks
+event:0X0210 mmcr0:0X00000000 mmcr1:0X09900000A0A284E8 mmcra:0X00000000
+event:0X0211 mmcr0:0X00000000 mmcr1:0X09900000A0A284E8 mmcra:0X00000000
+event:0X0212 mmcr0:0X00000000 mmcr1:0X09900000A0A284E8 mmcra:0X00000000
+event:0X0213 mmcr0:0X00000000 mmcr1:0X09900000A0A284E8 mmcra:0X00000000
+
+#Group 34 pm_inst_tablewalk, Instruction tablewalks
+event:0X0220 mmcr0:0X00000000 mmcr1:0X09900000A8AA8CEA mmcra:0X00000000
+event:0X0221 mmcr0:0X00000000 mmcr1:0X09900000A8AA8CEA mmcra:0X00000000
+event:0X0222 mmcr0:0X00000000 mmcr1:0X09900000A8AA8CEA mmcra:0X00000000
+event:0X0223 mmcr0:0X00000000 mmcr1:0X09900000A8AA8CEA mmcra:0X00000000
+
+#Group 35 pm_freq, Frequency events
+event:0X0230 mmcr0:0X00000000 mmcr1:0X000000002A3C3C3C mmcra:0X00000000
+event:0X0231 mmcr0:0X00000000 mmcr1:0X000000002A3C3C3C mmcra:0X00000000
+event:0X0232 mmcr0:0X00000000 mmcr1:0X000000002A3C3C3C mmcra:0X00000000
+event:0X0233 mmcr0:0X00000000 mmcr1:0X000000002A3C3C3C mmcra:0X00000000
+
+#Group 36 pm_disp_wait, Dispatch stalls
+event:0X0240 mmcr0:0X00000000 mmcr1:0X00000000560C040C mmcra:0X00000000
+event:0X0241 mmcr0:0X00000000 mmcr1:0X00000000560C040C mmcra:0X00000000
+event:0X0242 mmcr0:0X00000000 mmcr1:0X00000000560C040C mmcra:0X00000000
+event:0X0243 mmcr0:0X00000000 mmcr1:0X00000000560C040C mmcra:0X00000000
+
+#Group 37 pm_disp_held, Dispatch held conditions
+event:0X0250 mmcr0:0X00000000 mmcr1:0X200000002A3C2AA2 mmcra:0X00000000
+event:0X0251 mmcr0:0X00000000 mmcr1:0X200000002A3C2AA2 mmcra:0X00000000
+event:0X0252 mmcr0:0X00000000 mmcr1:0X200000002A3C2AA2 mmcra:0X00000000
+event:0X0253 mmcr0:0X00000000 mmcr1:0X200000002A3C2AA2 mmcra:0X00000000
+
+#Group 38 pm_disp_held2, Dispatch held conditions
+event:0X0260 mmcr0:0X00000000 mmcr1:0X200000008004A4A6 mmcra:0X00000000
+event:0X0261 mmcr0:0X00000000 mmcr1:0X200000008004A4A6 mmcra:0X00000000
+event:0X0262 mmcr0:0X00000000 mmcr1:0X200000008004A4A6 mmcra:0X00000000
+event:0X0263 mmcr0:0X00000000 mmcr1:0X200000008004A4A6 mmcra:0X00000000
+
+#Group 39 pm_disp_held3, Dispatch held conditions
+event:0X0270 mmcr0:0X00000000 mmcr1:0X20000000888AACAE mmcra:0X00000000
+event:0X0271 mmcr0:0X00000000 mmcr1:0X20000000888AACAE mmcra:0X00000000
+event:0X0272 mmcr0:0X00000000 mmcr1:0X20000000888AACAE mmcra:0X00000000
+event:0X0273 mmcr0:0X00000000 mmcr1:0X20000000888AACAE mmcra:0X00000000
+
+#Group 40 pm_disp_held4, Dispatch held conditions
+event:0X0280 mmcr0:0X00000000 mmcr1:0X02000000A0A28486 mmcra:0X00000000
+event:0X0281 mmcr0:0X00000000 mmcr1:0X02000000A0A28486 mmcra:0X00000000
+event:0X0282 mmcr0:0X00000000 mmcr1:0X02000000A0A28486 mmcra:0X00000000
+event:0X0283 mmcr0:0X00000000 mmcr1:0X02000000A0A28486 mmcra:0X00000000
+
+#Group 41 pm_disp_held5, Dispatch held conditions
+event:0X0290 mmcr0:0X00000000 mmcr1:0X22000000A8AA8CA0 mmcra:0X00000000
+event:0X0291 mmcr0:0X00000000 mmcr1:0X22000000A8AA8CA0 mmcra:0X00000000
+event:0X0292 mmcr0:0X00000000 mmcr1:0X22000000A8AA8CA0 mmcra:0X00000000
+event:0X0293 mmcr0:0X00000000 mmcr1:0X22000000A8AA8CA0 mmcra:0X00000000
+
+#Group 42 pm_disp_held6, Dispatch held conditions
+event:0X02A0 mmcr0:0X00000000 mmcr1:0X33000000A882A4A6 mmcra:0X00000000
+event:0X02A1 mmcr0:0X00000000 mmcr1:0X33000000A882A4A6 mmcra:0X00000000
+event:0X02A2 mmcr0:0X00000000 mmcr1:0X33000000A882A4A6 mmcra:0X00000000
+event:0X02A3 mmcr0:0X00000000 mmcr1:0X33000000A882A4A6 mmcra:0X00000000
+
+#Group 43 pm_disp_held7, Dispatch held conditions
+event:0X02B0 mmcr0:0X00000000 mmcr1:0X30000000888AACAE mmcra:0X00000000
+event:0X02B1 mmcr0:0X00000000 mmcr1:0X30000000888AACAE mmcra:0X00000000
+event:0X02B2 mmcr0:0X00000000 mmcr1:0X30000000888AACAE mmcra:0X00000000
+event:0X02B3 mmcr0:0X00000000 mmcr1:0X30000000888AACAE mmcra:0X00000000
+
+#Group 44 pm_disp_held8, Dispatch held conditions
+event:0X02C0 mmcr0:0X00000000 mmcr1:0X220000008A8CAE80 mmcra:0X00000000
+event:0X02C1 mmcr0:0X00000000 mmcr1:0X220000008A8CAE80 mmcra:0X00000000
+event:0X02C2 mmcr0:0X00000000 mmcr1:0X220000008A8CAE80 mmcra:0X00000000
+event:0X02C3 mmcr0:0X00000000 mmcr1:0X220000008A8CAE80 mmcra:0X00000000
+
+#Group 45 pm_disp_held9, Dispatch held conditions
+event:0X02D0 mmcr0:0X00000000 mmcr1:0X220000008AA08A8C mmcra:0X00000000
+event:0X02D1 mmcr0:0X00000000 mmcr1:0X220000008AA08A8C mmcra:0X00000000
+event:0X02D2 mmcr0:0X00000000 mmcr1:0X220000008AA08A8C mmcra:0X00000000
+event:0X02D3 mmcr0:0X00000000 mmcr1:0X220000008AA08A8C mmcra:0X00000000
+
+#Group 46 pm_sync, Sync events
+event:0X02E0 mmcr0:0X00000000 mmcr1:0X38900000AE1EECA0 mmcra:0X00000000
+event:0X02E1 mmcr0:0X00000000 mmcr1:0X38900000AE1EECA0 mmcra:0X00000000
+event:0X02E2 mmcr0:0X00000000 mmcr1:0X38900000AE1EECA0 mmcra:0X00000000
+event:0X02E3 mmcr0:0X00000000 mmcr1:0X38900000AE1EECA0 mmcra:0X00000000
+
+#Group 47 pm_L1_ref, L1 references
+event:0X02F0 mmcr0:0X00000000 mmcr1:0X80000000368AA63A mmcra:0X00000000
+event:0X02F1 mmcr0:0X00000000 mmcr1:0X80000000368AA63A mmcra:0X00000000
+event:0X02F2 mmcr0:0X00000000 mmcr1:0X80000000368AA63A mmcra:0X00000000
+event:0X02F3 mmcr0:0X00000000 mmcr1:0X80000000368AA63A mmcra:0X00000000
+
+#Group 48 pm_L1_ldst, L1 load/store ref/miss
+event:0X0300 mmcr0:0X00000000 mmcr1:0X800000003230A8A0 mmcra:0X00000000
+event:0X0301 mmcr0:0X00000000 mmcr1:0X800000003230A8A0 mmcra:0X00000000
+event:0X0302 mmcr0:0X00000000 mmcr1:0X800000003230A8A0 mmcra:0X00000000
+event:0X0303 mmcr0:0X00000000 mmcr1:0X800000003230A8A0 mmcra:0X00000000
+
+#Group 49 pm_streams, Streams
+event:0X0310 mmcr0:0X00000000 mmcr1:0X48000000A0A284A4 mmcra:0X00000000
+event:0X0311 mmcr0:0X00000000 mmcr1:0X48000000A0A284A4 mmcra:0X00000000
+event:0X0312 mmcr0:0X00000000 mmcr1:0X48000000A0A284A4 mmcra:0X00000000
+event:0X0313 mmcr0:0X00000000 mmcr1:0X48000000A0A284A4 mmcra:0X00000000
+
+#Group 50 pm_flush, Flushes
+event:0X0320 mmcr0:0X00000000 mmcr1:0X0022000010CACCCA mmcra:0X00000000
+event:0X0321 mmcr0:0X00000000 mmcr1:0X0022000010CACCCA mmcra:0X00000000
+event:0X0322 mmcr0:0X00000000 mmcr1:0X0022000010CACCCA mmcra:0X00000000
+event:0X0323 mmcr0:0X00000000 mmcr1:0X0022000010CACCCA mmcra:0X00000000
+
+#Group 51 pm_prefetch, I cache Prefetches
+event:0X0330 mmcr0:0X00000000 mmcr1:0X400400008A8CAEC0 mmcra:0X00000000
+event:0X0331 mmcr0:0X00000000 mmcr1:0X400400008A8CAEC0 mmcra:0X00000000
+event:0X0332 mmcr0:0X00000000 mmcr1:0X400400008A8CAEC0 mmcra:0X00000000
+event:0X0333 mmcr0:0X00000000 mmcr1:0X400400008A8CAEC0 mmcra:0X00000000
+
+#Group 52 pm_stcx, STCX
+event:0X0340 mmcr0:0X00000000 mmcr1:0X00080000E6ECCECA mmcra:0X00000000
+event:0X0341 mmcr0:0X00000000 mmcr1:0X00080000E6ECCECA mmcra:0X00000000
+event:0X0342 mmcr0:0X00000000 mmcr1:0X00080000E6ECCECA mmcra:0X00000000
+event:0X0343 mmcr0:0X00000000 mmcr1:0X00080000E6ECCECA mmcra:0X00000000
+
+#Group 53 pm_larx, LARX
+event:0X0350 mmcr0:0X00000000 mmcr1:0X00080000EAE2C6CE mmcra:0X00000000
+event:0X0351 mmcr0:0X00000000 mmcr1:0X00080000EAE2C6CE mmcra:0X00000000
+event:0X0352 mmcr0:0X00000000 mmcr1:0X00080000EAE2C6CE mmcra:0X00000000
+event:0X0353 mmcr0:0X00000000 mmcr1:0X00080000EAE2C6CE mmcra:0X00000000
+
+#Group 54 pm_thread_cyc, Thread cycles
+event:0X0360 mmcr0:0X00000000 mmcr1:0X0000000016182604 mmcra:0X00000000
+event:0X0361 mmcr0:0X00000000 mmcr1:0X0000000016182604 mmcra:0X00000000
+event:0X0362 mmcr0:0X00000000 mmcr1:0X0000000016182604 mmcra:0X00000000
+event:0X0363 mmcr0:0X00000000 mmcr1:0X0000000016182604 mmcra:0X00000000
+
+#Group 55 pm_misc, Misc
+event:0X0370 mmcr0:0X00000000 mmcr1:0X0000000004161808 mmcra:0X00000001
+event:0X0371 mmcr0:0X00000000 mmcr1:0X0000000004161808 mmcra:0X00000001
+event:0X0372 mmcr0:0X00000000 mmcr1:0X0000000004161808 mmcra:0X00000001
+event:0X0373 mmcr0:0X00000000 mmcr1:0X0000000004161808 mmcra:0X00000001
+
+#Group 56 pm_misc2, Misc
+event:0X0380 mmcr0:0X00000000 mmcr1:0X40020000EEF8F8A0 mmcra:0X00000000
+event:0X0381 mmcr0:0X00000000 mmcr1:0X40020000EEF8F8A0 mmcra:0X00000000
+event:0X0382 mmcr0:0X00000000 mmcr1:0X40020000EEF8F8A0 mmcra:0X00000000
+event:0X0383 mmcr0:0X00000000 mmcr1:0X40020000EEF8F8A0 mmcra:0X00000000
+
+#Group 57 pm_misc3, Misc
+event:0X0390 mmcr0:0X00000000 mmcr1:0X0300000054A01E02 mmcra:0X00000000
+event:0X0391 mmcr0:0X00000000 mmcr1:0X0300000054A01E02 mmcra:0X00000000
+event:0X0392 mmcr0:0X00000000 mmcr1:0X0300000054A01E02 mmcra:0X00000000
+event:0X0393 mmcr0:0X00000000 mmcr1:0X0300000054A01E02 mmcra:0X00000000
+
+#Group 58 pm_tlb_slb, TLB and SLB events
+event:0X03A0 mmcr0:0X00000000 mmcr1:0X00980000E0E8E8E2 mmcra:0X00000000
+event:0X03A1 mmcr0:0X00000000 mmcr1:0X00980000E0E8E8E2 mmcra:0X00000000
+event:0X03A2 mmcr0:0X00000000 mmcr1:0X00980000E0E8E8E2 mmcra:0X00000000
+event:0X03A3 mmcr0:0X00000000 mmcr1:0X00980000E0E8E8E2 mmcra:0X00000000
+
+#Group 59 pm_slb_miss, SLB Misses
+event:0X03B0 mmcr0:0X00000000 mmcr1:0X00480001E0E8EE32 mmcra:0X00000000
+event:0X03B1 mmcr0:0X00000000 mmcr1:0X00480001E0E8EE32 mmcra:0X00000000
+event:0X03B2 mmcr0:0X00000000 mmcr1:0X00480001E0E8EE32 mmcra:0X00000000
+event:0X03B3 mmcr0:0X00000000 mmcr1:0X00480001E0E8EE32 mmcra:0X00000000
+
+#Group 60 pm_rejects, Reject events
+event:0X03C0 mmcr0:0X00000000 mmcr1:0XAA00000034303E30 mmcra:0X00000000
+event:0X03C1 mmcr0:0X00000000 mmcr1:0XAA00000034303E30 mmcra:0X00000000
+event:0X03C2 mmcr0:0X00000000 mmcr1:0XAA00000034303E30 mmcra:0X00000000
+event:0X03C3 mmcr0:0X00000000 mmcr1:0XAA00000034303E30 mmcra:0X00000000
+
+#Group 61 pm_rejects2, Reject events
+event:0X03D0 mmcr0:0X00000000 mmcr1:0X9A000000323830AC mmcra:0X00000000
+event:0X03D1 mmcr0:0X00000000 mmcr1:0X9A000000323830AC mmcra:0X00000000
+event:0X03D2 mmcr0:0X00000000 mmcr1:0X9A000000323830AC mmcra:0X00000000
+event:0X03D3 mmcr0:0X00000000 mmcr1:0X9A000000323830AC mmcra:0X00000000
+
+#Group 62 pm_rejects3, Reject events
+event:0X03E0 mmcr0:0X00000000 mmcr1:0XAA000000303E3234 mmcra:0X00000000
+event:0X03E1 mmcr0:0X00000000 mmcr1:0XAA000000303E3234 mmcra:0X00000000
+event:0X03E2 mmcr0:0X00000000 mmcr1:0XAA000000303E3234 mmcra:0X00000000
+event:0X03E3 mmcr0:0X00000000 mmcr1:0XAA000000303E3234 mmcra:0X00000000
+
+#Group 63 pm_rejects4, Unaligned store rejects
+event:0X03F0 mmcr0:0X00000000 mmcr1:0X900000003630A2AA mmcra:0X00000000
+event:0X03F1 mmcr0:0X00000000 mmcr1:0X900000003630A2AA mmcra:0X00000000
+event:0X03F2 mmcr0:0X00000000 mmcr1:0X900000003630A2AA mmcra:0X00000000
+event:0X03F3 mmcr0:0X00000000 mmcr1:0X900000003630A2AA mmcra:0X00000000
+
+#Group 64 pm_rejects5, Unaligned load rejects
+event:0X0400 mmcr0:0X00000000 mmcr1:0X900000003036A0A8 mmcra:0X00000000
+event:0X0401 mmcr0:0X00000000 mmcr1:0X900000003036A0A8 mmcra:0X00000000
+event:0X0402 mmcr0:0X00000000 mmcr1:0X900000003036A0A8 mmcra:0X00000000
+event:0X0403 mmcr0:0X00000000 mmcr1:0X900000003036A0A8 mmcra:0X00000000
+
+#Group 65 pm_rejects6, Set mispredictions rejects
+event:0X0410 mmcr0:0X00000000 mmcr1:0XA0000000848C341C mmcra:0X00000000
+event:0X0411 mmcr0:0X00000000 mmcr1:0XA0000000848C341C mmcra:0X00000000
+event:0X0412 mmcr0:0X00000000 mmcr1:0XA0000000848C341C mmcra:0X00000000
+event:0X0413 mmcr0:0X00000000 mmcr1:0XA0000000848C341C mmcra:0X00000000
+
+#Group 66 pm_rejects_unit, Unaligned reject events by unit
+event:0X0420 mmcr0:0X00000000 mmcr1:0X90000000808AA2A8 mmcra:0X00000000
+event:0X0421 mmcr0:0X00000000 mmcr1:0X90000000808AA2A8 mmcra:0X00000000
+event:0X0422 mmcr0:0X00000000 mmcr1:0X90000000808AA2A8 mmcra:0X00000000
+event:0X0423 mmcr0:0X00000000 mmcr1:0X90000000808AA2A8 mmcra:0X00000000
+
+#Group 67 pm_rejects_unit2, Reject events by unit
+event:0X0430 mmcr0:0X00000000 mmcr1:0XAA000000A6828E8A mmcra:0X00000000
+event:0X0431 mmcr0:0X00000000 mmcr1:0XAA000000A6828E8A mmcra:0X00000000
+event:0X0432 mmcr0:0X00000000 mmcr1:0XAA000000A6828E8A mmcra:0X00000000
+event:0X0433 mmcr0:0X00000000 mmcr1:0XAA000000A6828E8A mmcra:0X00000000
+
+#Group 68 pm_rejects_unit3, Reject events by unit
+event:0X0440 mmcr0:0X00000000 mmcr1:0X0A000000A4A08C88 mmcra:0X00000000
+event:0X0441 mmcr0:0X00000000 mmcr1:0X0A000000A4A08C88 mmcra:0X00000000
+event:0X0442 mmcr0:0X00000000 mmcr1:0X0A000000A4A08C88 mmcra:0X00000000
+event:0X0443 mmcr0:0X00000000 mmcr1:0X0A000000A4A08C88 mmcra:0X00000000
+
+#Group 69 pm_rejects_unit4, Reject events by unit
+event:0X0450 mmcr0:0X00000000 mmcr1:0XAA000000A2868AAE mmcra:0X00000000
+event:0X0451 mmcr0:0X00000000 mmcr1:0XAA000000A2868AAE mmcra:0X00000000
+event:0X0452 mmcr0:0X00000000 mmcr1:0XAA000000A2868AAE mmcra:0X00000000
+event:0X0453 mmcr0:0X00000000 mmcr1:0XAA000000A2868AAE mmcra:0X00000000
+
+#Group 70 pm_rejects_unit5, Reject events by unit
+event:0X0460 mmcr0:0X00000000 mmcr1:0X9900000086A6AE8E mmcra:0X00000000
+event:0X0461 mmcr0:0X00000000 mmcr1:0X9900000086A6AE8E mmcra:0X00000000
+event:0X0462 mmcr0:0X00000000 mmcr1:0X9900000086A6AE8E mmcra:0X00000000
+event:0X0463 mmcr0:0X00000000 mmcr1:0X9900000086A6AE8E mmcra:0X00000000
+
+#Group 71 pm_rejects_unit6, Reject events by unit
+event:0X0470 mmcr0:0X00000000 mmcr1:0XAA00000080A6A88E mmcra:0X00000000
+event:0X0471 mmcr0:0X00000000 mmcr1:0XAA00000080A6A88E mmcra:0X00000000
+event:0X0472 mmcr0:0X00000000 mmcr1:0XAA00000080A6A88E mmcra:0X00000000
+event:0X0473 mmcr0:0X00000000 mmcr1:0XAA00000080A6A88E mmcra:0X00000000
+
+#Group 72 pm_rejects_unit7, Reject events by unit
+event:0X0480 mmcr0:0X00000000 mmcr1:0XA900000082A6AA8E mmcra:0X00000000
+event:0X0481 mmcr0:0X00000000 mmcr1:0XA900000082A6AA8E mmcra:0X00000000
+event:0X0482 mmcr0:0X00000000 mmcr1:0XA900000082A6AA8E mmcra:0X00000000
+event:0X0483 mmcr0:0X00000000 mmcr1:0XA900000082A6AA8E mmcra:0X00000000
+
+#Group 73 pm_ldf, Floating Point loads
+event:0X0490 mmcr0:0X00000000 mmcr1:0X800000003832A4AC mmcra:0X00000000
+event:0X0491 mmcr0:0X00000000 mmcr1:0X800000003832A4AC mmcra:0X00000000
+event:0X0492 mmcr0:0X00000000 mmcr1:0X800000003832A4AC mmcra:0X00000000
+event:0X0493 mmcr0:0X00000000 mmcr1:0X800000003832A4AC mmcra:0X00000000
+
+#Group 74 pm_lsu_misc, LSU events
+event:0X04A0 mmcr0:0X00000000 mmcr1:0X08800000CACCEE8A mmcra:0X00000000
+event:0X04A1 mmcr0:0X00000000 mmcr1:0X08800000CACCEE8A mmcra:0X00000000
+event:0X04A2 mmcr0:0X00000000 mmcr1:0X08800000CACCEE8A mmcra:0X00000000
+event:0X04A3 mmcr0:0X00000000 mmcr1:0X08800000CACCEE8A mmcra:0X00000000
+
+#Group 75 pm_lsu_lmq, LSU LMQ events
+event:0X04B0 mmcr0:0X00000000 mmcr1:0X98000000AC1C1CA4 mmcra:0X00000000
+event:0X04B1 mmcr0:0X00000000 mmcr1:0X98000000AC1C1CA4 mmcra:0X00000000
+event:0X04B2 mmcr0:0X00000000 mmcr1:0X98000000AC1C1CA4 mmcra:0X00000000
+event:0X04B3 mmcr0:0X00000000 mmcr1:0X98000000AC1C1CA4 mmcra:0X00000000
+
+#Group 76 pm_lsu_flush_derat_miss, LSU flush and DERAT misses
+event:0X04C0 mmcr0:0X00000000 mmcr1:0X00200000FC0EECEE mmcra:0X00000000
+event:0X04C1 mmcr0:0X00000000 mmcr1:0X00200000FC0EECEE mmcra:0X00000000
+event:0X04C2 mmcr0:0X00000000 mmcr1:0X00200000FC0EECEE mmcra:0X00000000
+event:0X04C3 mmcr0:0X00000000 mmcr1:0X00200000FC0EECEE mmcra:0X00000000
+
+#Group 77 pm_lla, Look Load Ahead events
+event:0X04D0 mmcr0:0X00000000 mmcr1:0X33000000A2841208 mmcra:0X00000000
+event:0X04D1 mmcr0:0X00000000 mmcr1:0X33000000A2841208 mmcra:0X00000000
+event:0X04D2 mmcr0:0X00000000 mmcr1:0X33000000A2841208 mmcra:0X00000000
+event:0X04D3 mmcr0:0X00000000 mmcr1:0X33000000A2841208 mmcra:0X00000000
+
+#Group 78 pm_gct, GCT events
+event:0X04E0 mmcr0:0X00000000 mmcr1:0X404000000808A6E8 mmcra:0X00000000
+event:0X04E1 mmcr0:0X00000000 mmcr1:0X404000000808A6E8 mmcra:0X00000000
+event:0X04E2 mmcr0:0X00000000 mmcr1:0X404000000808A6E8 mmcra:0X00000000
+event:0X04E3 mmcr0:0X00000000 mmcr1:0X404000000808A6E8 mmcra:0X00000000
+
+#Group 79 pm_smt_priorities, Thread priority events
+event:0X04F0 mmcr0:0X00000000 mmcr1:0X0020000040404040 mmcra:0X00000000
+event:0X04F1 mmcr0:0X00000000 mmcr1:0X0020000040404040 mmcra:0X00000000
+event:0X04F2 mmcr0:0X00000000 mmcr1:0X0020000040404040 mmcra:0X00000000
+event:0X04F3 mmcr0:0X00000000 mmcr1:0X0020000040404040 mmcra:0X00000000
+
+#Group 80 pm_smt_priorities2, Thread priority events
+event:0X0500 mmcr0:0X00000000 mmcr1:0X0020000046464646 mmcra:0X00000000
+event:0X0501 mmcr0:0X00000000 mmcr1:0X0020000046464646 mmcra:0X00000000
+event:0X0502 mmcr0:0X00000000 mmcr1:0X0020000046464646 mmcra:0X00000000
+event:0X0503 mmcr0:0X00000000 mmcr1:0X0020000046464646 mmcra:0X00000000
+
+#Group 81 pm_smt_priorities3, Thread priority differences events
+event:0X0510 mmcr0:0X00000000 mmcr1:0X0002000040404040 mmcra:0X00000000
+event:0X0511 mmcr0:0X00000000 mmcr1:0X0002000040404040 mmcra:0X00000000
+event:0X0512 mmcr0:0X00000000 mmcr1:0X0002000040404040 mmcra:0X00000000
+event:0X0513 mmcr0:0X00000000 mmcr1:0X0002000040404040 mmcra:0X00000000
+
+#Group 82 pm_smt_priorities4, Thread priority differences events
+event:0X0520 mmcr0:0X00000000 mmcr1:0X03020000A6464646 mmcra:0X00000000
+event:0X0521 mmcr0:0X00000000 mmcr1:0X03020000A6464646 mmcra:0X00000000
+event:0X0522 mmcr0:0X00000000 mmcr1:0X03020000A6464646 mmcra:0X00000000
+event:0X0523 mmcr0:0X00000000 mmcr1:0X03020000A6464646 mmcra:0X00000000
+
+#Group 83 pm_fxu, FXU events
+event:0X0530 mmcr0:0X00000000 mmcr1:0X0000000050505050 mmcra:0X00000000
+event:0X0531 mmcr0:0X00000000 mmcr1:0X0000000050505050 mmcra:0X00000000
+event:0X0532 mmcr0:0X00000000 mmcr1:0X0000000050505050 mmcra:0X00000000
+event:0X0533 mmcr0:0X00000000 mmcr1:0X0000000050505050 mmcra:0X00000000
+
+#Group 84 pm_fxu2, FXU events
+event:0X0540 mmcr0:0X00000000 mmcr1:0X02040000AEE41616 mmcra:0X00000000
+event:0X0541 mmcr0:0X00000000 mmcr1:0X02040000AEE41616 mmcra:0X00000000
+event:0X0542 mmcr0:0X00000000 mmcr1:0X02040000AEE41616 mmcra:0X00000000
+event:0X0543 mmcr0:0X00000000 mmcr1:0X02040000AEE41616 mmcra:0X00000000
+
+#Group 85 pm_vmx, VMX events
+event:0X0550 mmcr0:0X00000000 mmcr1:0X700000008480A2A6 mmcra:0X00000000
+event:0X0551 mmcr0:0X00000000 mmcr1:0X700000008480A2A6 mmcra:0X00000000
+event:0X0552 mmcr0:0X00000000 mmcr1:0X700000008480A2A6 mmcra:0X00000000
+event:0X0553 mmcr0:0X00000000 mmcr1:0X700000008480A2A6 mmcra:0X00000000
+
+#Group 86 pm_vmx2, VMX events
+event:0X0560 mmcr0:0X00000000 mmcr1:0X600000008088A2AA mmcra:0X00000000
+event:0X0561 mmcr0:0X00000000 mmcr1:0X600000008088A2AA mmcra:0X00000000
+event:0X0562 mmcr0:0X00000000 mmcr1:0X600000008088A2AA mmcra:0X00000000
+event:0X0563 mmcr0:0X00000000 mmcr1:0X600000008088A2AA mmcra:0X00000000
+
+#Group 87 pm_vmx3, VMX events
+event:0X0570 mmcr0:0X00000000 mmcr1:0X600000008284AAAC mmcra:0X00000000
+event:0X0571 mmcr0:0X00000000 mmcr1:0X600000008284AAAC mmcra:0X00000000
+event:0X0572 mmcr0:0X00000000 mmcr1:0X600000008284AAAC mmcra:0X00000000
+event:0X0573 mmcr0:0X00000000 mmcr1:0X600000008284AAAC mmcra:0X00000000
+
+#Group 88 pm_vmx4, VMX events
+event:0X0580 mmcr0:0X00000000 mmcr1:0XB0000000828EA6A0 mmcra:0X00000000
+event:0X0581 mmcr0:0X00000000 mmcr1:0XB0000000828EA6A0 mmcra:0X00000000
+event:0X0582 mmcr0:0X00000000 mmcr1:0XB0000000828EA6A0 mmcra:0X00000000
+event:0X0583 mmcr0:0X00000000 mmcr1:0XB0000000828EA6A0 mmcra:0X00000000
+
+#Group 89 pm_vmx5, VMX events
+event:0X0590 mmcr0:0X00000000 mmcr1:0XB00000008084ACA2 mmcra:0X00000000
+event:0X0591 mmcr0:0X00000000 mmcr1:0XB00000008084ACA2 mmcra:0X00000000
+event:0X0592 mmcr0:0X00000000 mmcr1:0XB00000008084ACA2 mmcra:0X00000000
+event:0X0593 mmcr0:0X00000000 mmcr1:0XB00000008084ACA2 mmcra:0X00000000
+
+#Group 90 pm_dfu, DFU events
+event:0X05A0 mmcr0:0X00000000 mmcr1:0XE00000008C88A2AE mmcra:0X00000000
+event:0X05A1 mmcr0:0X00000000 mmcr1:0XE00000008C88A2AE mmcra:0X00000000
+event:0X05A2 mmcr0:0X00000000 mmcr1:0XE00000008C88A2AE mmcra:0X00000000
+event:0X05A3 mmcr0:0X00000000 mmcr1:0XE00000008C88A2AE mmcra:0X00000000
+
+#Group 91 pm_dfu2, DFU events
+event:0X05B0 mmcr0:0X00000000 mmcr1:0XE00000008A84A0A6 mmcra:0X00000000
+event:0X05B1 mmcr0:0X00000000 mmcr1:0XE00000008A84A0A6 mmcra:0X00000000
+event:0X05B2 mmcr0:0X00000000 mmcr1:0XE00000008A84A0A6 mmcra:0X00000000
+event:0X05B3 mmcr0:0X00000000 mmcr1:0XE00000008A84A0A6 mmcra:0X00000000
+
+#Group 92 pm_fab, Fabric events
+event:0X05C0 mmcr0:0X00000000 mmcr1:0X500020003030A4AC mmcra:0X00000000
+event:0X05C1 mmcr0:0X00000000 mmcr1:0X500020003030A4AC mmcra:0X00000000
+event:0X05C2 mmcr0:0X00000000 mmcr1:0X500020003030A4AC mmcra:0X00000000
+event:0X05C3 mmcr0:0X00000000 mmcr1:0X500020003030A4AC mmcra:0X00000000
+
+#Group 93 pm_fab2, Fabric events
+event:0X05D0 mmcr0:0X00000000 mmcr1:0X50002000888AA2A0 mmcra:0X00000000
+event:0X05D1 mmcr0:0X00000000 mmcr1:0X50002000888AA2A0 mmcra:0X00000000
+event:0X05D2 mmcr0:0X00000000 mmcr1:0X50002000888AA2A0 mmcra:0X00000000
+event:0X05D3 mmcr0:0X00000000 mmcr1:0X50002000888AA2A0 mmcra:0X00000000
+
+#Group 94 pm_fab3, Fabric events
+event:0X05E0 mmcr0:0X00000000 mmcr1:0X500020003030AEA6 mmcra:0X00000000
+event:0X05E1 mmcr0:0X00000000 mmcr1:0X500020003030AEA6 mmcra:0X00000000
+event:0X05E2 mmcr0:0X00000000 mmcr1:0X500020003030AEA6 mmcra:0X00000000
+event:0X05E3 mmcr0:0X00000000 mmcr1:0X500020003030AEA6 mmcra:0X00000000
+
+#Group 95 pm_mem_dblpump, Double pump
+event:0X05F0 mmcr0:0X00000000 mmcr1:0X5000400030303434 mmcra:0X00000000
+event:0X05F1 mmcr0:0X00000000 mmcr1:0X5000400030303434 mmcra:0X00000000
+event:0X05F2 mmcr0:0X00000000 mmcr1:0X5000400030303434 mmcra:0X00000000
+event:0X05F3 mmcr0:0X00000000 mmcr1:0X5000400030303434 mmcra:0X00000000
+
+#Group 96 pm_mem0_dblpump, MCS0 Double pump
+event:0X0600 mmcr0:0X00000000 mmcr1:0X500040008082A4A6 mmcra:0X00000000
+event:0X0601 mmcr0:0X00000000 mmcr1:0X500040008082A4A6 mmcra:0X00000000
+event:0X0602 mmcr0:0X00000000 mmcr1:0X500040008082A4A6 mmcra:0X00000000
+event:0X0603 mmcr0:0X00000000 mmcr1:0X500040008082A4A6 mmcra:0X00000000
+
+#Group 97 pm_mem1_dblpump, MCS1 Double pump
+event:0X0610 mmcr0:0X00000000 mmcr1:0X50004000888AACAE mmcra:0X00000000
+event:0X0611 mmcr0:0X00000000 mmcr1:0X50004000888AACAE mmcra:0X00000000
+event:0X0612 mmcr0:0X00000000 mmcr1:0X50004000888AACAE mmcra:0X00000000
+event:0X0613 mmcr0:0X00000000 mmcr1:0X50004000888AACAE mmcra:0X00000000
+
+#Group 98 pm_gxo, GX outbound
+event:0X0620 mmcr0:0X00000000 mmcr1:0X500060008082A4A6 mmcra:0X00000000
+event:0X0621 mmcr0:0X00000000 mmcr1:0X500060008082A4A6 mmcra:0X00000000
+event:0X0622 mmcr0:0X00000000 mmcr1:0X500060008082A4A6 mmcra:0X00000000
+event:0X0623 mmcr0:0X00000000 mmcr1:0X500060008082A4A6 mmcra:0X00000000
+
+#Group 99 pm_gxi, GX inbound
+event:0X0630 mmcr0:0X00000000 mmcr1:0X500060008688AAA0 mmcra:0X00000000
+event:0X0631 mmcr0:0X00000000 mmcr1:0X500060008688AAA0 mmcra:0X00000000
+event:0X0632 mmcr0:0X00000000 mmcr1:0X500060008688AAA0 mmcra:0X00000000
+event:0X0633 mmcr0:0X00000000 mmcr1:0X500060008688AAA0 mmcra:0X00000000
+
+#Group 100 pm_gx_dma, DMA events
+event:0X0640 mmcr0:0X00000000 mmcr1:0X500060008086ACAE mmcra:0X00000000
+event:0X0641 mmcr0:0X00000000 mmcr1:0X500060008086ACAE mmcra:0X00000000
+event:0X0642 mmcr0:0X00000000 mmcr1:0X500060008086ACAE mmcra:0X00000000
+event:0X0643 mmcr0:0X00000000 mmcr1:0X500060008086ACAE mmcra:0X00000000
+
+#Group 101 pm_L1_misc, L1 misc events
+event:0X0650 mmcr0:0X00000000 mmcr1:0X4004000082E2A80A mmcra:0X00000000
+event:0X0651 mmcr0:0X00000000 mmcr1:0X4004000082E2A80A mmcra:0X00000000
+event:0X0652 mmcr0:0X00000000 mmcr1:0X4004000082E2A80A mmcra:0X00000000
+event:0X0653 mmcr0:0X00000000 mmcr1:0X4004000082E2A80A mmcra:0X00000000
+
+#Group 102 pm_L2_data, L2 load and store data
+event:0X0660 mmcr0:0X00000000 mmcr1:0X5000800030303434 mmcra:0X00000000
+event:0X0661 mmcr0:0X00000000 mmcr1:0X5000800030303434 mmcra:0X00000000
+event:0X0662 mmcr0:0X00000000 mmcr1:0X5000800030303434 mmcra:0X00000000
+event:0X0663 mmcr0:0X00000000 mmcr1:0X5000800030303434 mmcra:0X00000000
+
+#Group 103 pm_L2_ld_inst, L2 Load instructions
+event:0X0670 mmcr0:0X00000000 mmcr1:0X5800A00030303486 mmcra:0X00000000
+event:0X0671 mmcr0:0X00000000 mmcr1:0X5800A00030303486 mmcra:0X00000000
+event:0X0672 mmcr0:0X00000000 mmcr1:0X5800A00030303486 mmcra:0X00000000
+event:0X0673 mmcr0:0X00000000 mmcr1:0X5800A00030303486 mmcra:0X00000000
+
+#Group 104 pm_L2_castout_invalidate, L2 castout and invalidate events
+event:0X0680 mmcr0:0X00000000 mmcr1:0X5000C00030303434 mmcra:0X00000000
+event:0X0681 mmcr0:0X00000000 mmcr1:0X5000C00030303434 mmcra:0X00000000
+event:0X0682 mmcr0:0X00000000 mmcr1:0X5000C00030303434 mmcra:0X00000000
+event:0X0683 mmcr0:0X00000000 mmcr1:0X5000C00030303434 mmcra:0X00000000
+
+#Group 105 pm_L2_ldst_reqhit, L2 load and store requests and hits
+event:0X0690 mmcr0:0X00000000 mmcr1:0X5000E00030303434 mmcra:0X00000000
+event:0X0691 mmcr0:0X00000000 mmcr1:0X5000E00030303434 mmcra:0X00000000
+event:0X0692 mmcr0:0X00000000 mmcr1:0X5000E00030303434 mmcra:0X00000000
+event:0X0693 mmcr0:0X00000000 mmcr1:0X5000E00030303434 mmcra:0X00000000
+
+#Group 106 pm_L2_ld_data_slice, L2 data loads by slice
+event:0X06A0 mmcr0:0X00000000 mmcr1:0X500080008082A8AA mmcra:0X00000000
+event:0X06A1 mmcr0:0X00000000 mmcr1:0X500080008082A8AA mmcra:0X00000000
+event:0X06A2 mmcr0:0X00000000 mmcr1:0X500080008082A8AA mmcra:0X00000000
+event:0X06A3 mmcr0:0X00000000 mmcr1:0X500080008082A8AA mmcra:0X00000000
+
+#Group 107 pm_L2_ld_inst_slice, L2 instruction loads by slice
+event:0X06B0 mmcr0:0X00000000 mmcr1:0X5000A0008082A8AA mmcra:0X00000000
+event:0X06B1 mmcr0:0X00000000 mmcr1:0X5000A0008082A8AA mmcra:0X00000000
+event:0X06B2 mmcr0:0X00000000 mmcr1:0X5000A0008082A8AA mmcra:0X00000000
+event:0X06B3 mmcr0:0X00000000 mmcr1:0X5000A0008082A8AA mmcra:0X00000000
+
+#Group 108 pm_L2_st_slice, L2 slice stores by slice
+event:0X06C0 mmcr0:0X00000000 mmcr1:0X500080008486ACAE mmcra:0X00000000
+event:0X06C1 mmcr0:0X00000000 mmcr1:0X500080008486ACAE mmcra:0X00000000
+event:0X06C2 mmcr0:0X00000000 mmcr1:0X500080008486ACAE mmcra:0X00000000
+event:0X06C3 mmcr0:0X00000000 mmcr1:0X500080008486ACAE mmcra:0X00000000
+
+#Group 109 pm_L2miss_slice, L2 misses by slice
+event:0X06D0 mmcr0:0X00000000 mmcr1:0X5000A000843256AC mmcra:0X00000000
+event:0X06D1 mmcr0:0X00000000 mmcr1:0X5000A000843256AC mmcra:0X00000000
+event:0X06D2 mmcr0:0X00000000 mmcr1:0X5000A000843256AC mmcra:0X00000000
+event:0X06D3 mmcr0:0X00000000 mmcr1:0X5000A000843256AC mmcra:0X00000000
+
+#Group 110 pm_L2_castout_slice, L2 castouts by slice
+event:0X06E0 mmcr0:0X00000000 mmcr1:0X5000C0008082A8AA mmcra:0X00000000
+event:0X06E1 mmcr0:0X00000000 mmcr1:0X5000C0008082A8AA mmcra:0X00000000
+event:0X06E2 mmcr0:0X00000000 mmcr1:0X5000C0008082A8AA mmcra:0X00000000
+event:0X06E3 mmcr0:0X00000000 mmcr1:0X5000C0008082A8AA mmcra:0X00000000
+
+#Group 111 pm_L2_invalidate_slice, L2 invalidate by slice
+event:0X06F0 mmcr0:0X00000000 mmcr1:0X5000C0008486ACAE mmcra:0X00000000
+event:0X06F1 mmcr0:0X00000000 mmcr1:0X5000C0008486ACAE mmcra:0X00000000
+event:0X06F2 mmcr0:0X00000000 mmcr1:0X5000C0008486ACAE mmcra:0X00000000
+event:0X06F3 mmcr0:0X00000000 mmcr1:0X5000C0008486ACAE mmcra:0X00000000
+
+#Group 112 pm_L2_ld_reqhit_slice, L2 load requests and hist by slice
+event:0X0700 mmcr0:0X00000000 mmcr1:0X5000E0008082A8AA mmcra:0X00000000
+event:0X0701 mmcr0:0X00000000 mmcr1:0X5000E0008082A8AA mmcra:0X00000000
+event:0X0702 mmcr0:0X00000000 mmcr1:0X5000E0008082A8AA mmcra:0X00000000
+event:0X0703 mmcr0:0X00000000 mmcr1:0X5000E0008082A8AA mmcra:0X00000000
+
+#Group 113 pm_L2_st_reqhit_slice, L2 store requests and hist by slice
+event:0X0710 mmcr0:0X00000000 mmcr1:0X5000E0008486ACAE mmcra:0X00000000
+event:0X0711 mmcr0:0X00000000 mmcr1:0X5000E0008486ACAE mmcra:0X00000000
+event:0X0712 mmcr0:0X00000000 mmcr1:0X5000E0008486ACAE mmcra:0X00000000
+event:0X0713 mmcr0:0X00000000 mmcr1:0X5000E0008486ACAE mmcra:0X00000000
+
+#Group 114 pm_L2_redir_pref, L2 redirect and prefetch
+event:0X0720 mmcr0:0X00000000 mmcr1:0X08400000CACC8886 mmcra:0X00000000
+event:0X0721 mmcr0:0X00000000 mmcr1:0X08400000CACC8886 mmcra:0X00000000
+event:0X0722 mmcr0:0X00000000 mmcr1:0X08400000CACC8886 mmcra:0X00000000
+event:0X0723 mmcr0:0X00000000 mmcr1:0X08400000CACC8886 mmcra:0X00000000
+
+#Group 115 pm_L3_SliceA, L3 slice A events
+event:0X0730 mmcr0:0X00000000 mmcr1:0X50000000303058A4 mmcra:0X00000000
+event:0X0731 mmcr0:0X00000000 mmcr1:0X50000000303058A4 mmcra:0X00000000
+event:0X0732 mmcr0:0X00000000 mmcr1:0X50000000303058A4 mmcra:0X00000000
+event:0X0733 mmcr0:0X00000000 mmcr1:0X50000000303058A4 mmcra:0X00000000
+
+#Group 116 pm_L3_SliceB, L3 slice B events
+event:0X0740 mmcr0:0X00000000 mmcr1:0X50000000888A58AC mmcra:0X00000000
+event:0X0741 mmcr0:0X00000000 mmcr1:0X50000000888A58AC mmcra:0X00000000
+event:0X0742 mmcr0:0X00000000 mmcr1:0X50000000888A58AC mmcra:0X00000000
+event:0X0743 mmcr0:0X00000000 mmcr1:0X50000000888A58AC mmcra:0X00000000
+
+#Group 117 pm_fpu_issue, FPU issue events
+event:0X0750 mmcr0:0X00000000 mmcr1:0X00300000C6C8EAE4 mmcra:0X00000000
+event:0X0751 mmcr0:0X00000000 mmcr1:0X00300000C6C8EAE4 mmcra:0X00000000
+event:0X0752 mmcr0:0X00000000 mmcr1:0X00300000C6C8EAE4 mmcra:0X00000000
+event:0X0753 mmcr0:0X00000000 mmcr1:0X00300000C6C8EAE4 mmcra:0X00000000
+
+#Group 118 pm_fpu_issue2, FPU issue events
+event:0X0760 mmcr0:0X00000000 mmcr1:0X00300000C0C2ECEE mmcra:0X00000000
+event:0X0761 mmcr0:0X00000000 mmcr1:0X00300000C0C2ECEE mmcra:0X00000000
+event:0X0762 mmcr0:0X00000000 mmcr1:0X00300000C0C2ECEE mmcra:0X00000000
+event:0X0763 mmcr0:0X00000000 mmcr1:0X00300000C0C2ECEE mmcra:0X00000000
+
+#Group 119 pm_fpu_issue3, FPU issue events
+event:0X0770 mmcr0:0X00000000 mmcr1:0X00330000E0E2ECEE mmcra:0X00000000
+event:0X0771 mmcr0:0X00000000 mmcr1:0X00330000E0E2ECEE mmcra:0X00000000
+event:0X0772 mmcr0:0X00000000 mmcr1:0X00330000E0E2ECEE mmcra:0X00000000
+event:0X0773 mmcr0:0X00000000 mmcr1:0X00330000E0E2ECEE mmcra:0X00000000
+
+#Group 120 pm_fpu0_flop, FPU0 flop events
+event:0X0780 mmcr0:0X00000000 mmcr1:0XCC0000008082A484 mmcra:0X00000000
+event:0X0781 mmcr0:0X00000000 mmcr1:0XCC0000008082A484 mmcra:0X00000000
+event:0X0782 mmcr0:0X00000000 mmcr1:0XCC0000008082A484 mmcra:0X00000000
+event:0X0783 mmcr0:0X00000000 mmcr1:0XCC0000008082A484 mmcra:0X00000000
+
+#Group 121 pm_fpu0_misc, FPU0 events
+event:0X0790 mmcr0:0X00000000 mmcr1:0XCC00000086A08286 mmcra:0X00000000
+event:0X0791 mmcr0:0X00000000 mmcr1:0XCC00000086A08286 mmcra:0X00000000
+event:0X0792 mmcr0:0X00000000 mmcr1:0XCC00000086A08286 mmcra:0X00000000
+event:0X0793 mmcr0:0X00000000 mmcr1:0XCC00000086A08286 mmcra:0X00000000
+
+#Group 122 pm_fpu0_misc2, FPU0 events
+event:0X07A0 mmcr0:0X00000000 mmcr1:0XDD00000080A6A4A6 mmcra:0X00000000
+event:0X07A1 mmcr0:0X00000000 mmcr1:0XDD00000080A6A4A6 mmcra:0X00000000
+event:0X07A2 mmcr0:0X00000000 mmcr1:0XDD00000080A6A4A6 mmcra:0X00000000
+event:0X07A3 mmcr0:0X00000000 mmcr1:0XDD00000080A6A4A6 mmcra:0X00000000
+
+#Group 123 pm_fpu0_misc3, FPU0 events
+event:0X07B0 mmcr0:0X00000000 mmcr1:0X0D000000A0A28486 mmcra:0X00000000
+event:0X07B1 mmcr0:0X00000000 mmcr1:0X0D000000A0A28486 mmcra:0X00000000
+event:0X07B2 mmcr0:0X00000000 mmcr1:0X0D000000A0A28486 mmcra:0X00000000
+event:0X07B3 mmcr0:0X00000000 mmcr1:0X0D000000A0A28486 mmcra:0X00000000
+
+#Group 124 pm_fpu1_flop, FPU1 flop events
+event:0X07C0 mmcr0:0X00000000 mmcr1:0XCC000000888AAC8C mmcra:0X00000000
+event:0X07C1 mmcr0:0X00000000 mmcr1:0XCC000000888AAC8C mmcra:0X00000000
+event:0X07C2 mmcr0:0X00000000 mmcr1:0XCC000000888AAC8C mmcra:0X00000000
+event:0X07C3 mmcr0:0X00000000 mmcr1:0XCC000000888AAC8C mmcra:0X00000000
+
+#Group 125 pm_fpu1_misc, FPU1 events
+event:0X07D0 mmcr0:0X00000000 mmcr1:0XCC0000008EA88A8E mmcra:0X00000000
+event:0X07D1 mmcr0:0X00000000 mmcr1:0XCC0000008EA88A8E mmcra:0X00000000
+event:0X07D2 mmcr0:0X00000000 mmcr1:0XCC0000008EA88A8E mmcra:0X00000000
+event:0X07D3 mmcr0:0X00000000 mmcr1:0XCC0000008EA88A8E mmcra:0X00000000
+
+#Group 126 pm_fpu1_misc2, FPU1 events
+event:0X07E0 mmcr0:0X00000000 mmcr1:0XDD00000088AEACAE mmcra:0X00000000
+event:0X07E1 mmcr0:0X00000000 mmcr1:0XDD00000088AEACAE mmcra:0X00000000
+event:0X07E2 mmcr0:0X00000000 mmcr1:0XDD00000088AEACAE mmcra:0X00000000
+event:0X07E3 mmcr0:0X00000000 mmcr1:0XDD00000088AEACAE mmcra:0X00000000
+
+#Group 127 pm_fpu1_misc3, FPU1 events
+event:0X07F0 mmcr0:0X00000000 mmcr1:0X0D000000A8AA8C8E mmcra:0X00000000
+event:0X07F1 mmcr0:0X00000000 mmcr1:0X0D000000A8AA8C8E mmcra:0X00000000
+event:0X07F2 mmcr0:0X00000000 mmcr1:0X0D000000A8AA8C8E mmcra:0X00000000
+event:0X07F3 mmcr0:0X00000000 mmcr1:0X0D000000A8AA8C8E mmcra:0X00000000
+
+#Group 128 pm_fpu_flop, FPU flop events
+event:0X0800 mmcr0:0X00000000 mmcr1:0XC000000030303434 mmcra:0X00000000
+event:0X0801 mmcr0:0X00000000 mmcr1:0XC000000030303434 mmcra:0X00000000
+event:0X0802 mmcr0:0X00000000 mmcr1:0XC000000030303434 mmcra:0X00000000
+event:0X0803 mmcr0:0X00000000 mmcr1:0XC000000030303434 mmcra:0X00000000
+
+#Group 129 pm_fpu_misc, FPU events
+event:0X0810 mmcr0:0X00000000 mmcr1:0XDD00000030343434 mmcra:0X00000000
+event:0X0811 mmcr0:0X00000000 mmcr1:0XDD00000030343434 mmcra:0X00000000
+event:0X0812 mmcr0:0X00000000 mmcr1:0XDD00000030343434 mmcra:0X00000000
+event:0X0813 mmcr0:0X00000000 mmcr1:0XDD00000030343434 mmcra:0X00000000
+
+#Group 130 pm_fpu_misc2, FPU events
+event:0X0820 mmcr0:0X00000000 mmcr1:0X0C00000034343030 mmcra:0X00000000
+event:0X0821 mmcr0:0X00000000 mmcr1:0X0C00000034343030 mmcra:0X00000000
+event:0X0822 mmcr0:0X00000000 mmcr1:0X0C00000034343030 mmcra:0X00000000
+event:0X0823 mmcr0:0X00000000 mmcr1:0X0C00000034343030 mmcra:0X00000000
+
+#Group 131 pm_fpu_misc3, FPU events
+event:0X0830 mmcr0:0X00000000 mmcr1:0X0D00000034343030 mmcra:0X00000000
+event:0X0831 mmcr0:0X00000000 mmcr1:0X0D00000034343030 mmcra:0X00000000
+event:0X0832 mmcr0:0X00000000 mmcr1:0X0D00000034343030 mmcra:0X00000000
+event:0X0833 mmcr0:0X00000000 mmcr1:0X0D00000034343030 mmcra:0X00000000
+
+#Group 132 pm_purr, PURR events
+event:0X0840 mmcr0:0X00000000 mmcr1:0X000000000EF41E02 mmcra:0X00000000
+event:0X0841 mmcr0:0X00000000 mmcr1:0X000000000EF41E02 mmcra:0X00000000
+event:0X0842 mmcr0:0X00000000 mmcr1:0X000000000EF41E02 mmcra:0X00000000
+event:0X0843 mmcr0:0X00000000 mmcr1:0X000000000EF41E02 mmcra:0X00000000
+
+#Group 133 pm_suspend, SUSPENDED events
+event:0X0850 mmcr0:0X00000000 mmcr1:0X00900000001EEC02 mmcra:0X00000000
+event:0X0851 mmcr0:0X00000000 mmcr1:0X00900000001EEC02 mmcra:0X00000000
+event:0X0852 mmcr0:0X00000000 mmcr1:0X00900000001EEC02 mmcra:0X00000000
+event:0X0853 mmcr0:0X00000000 mmcr1:0X00900000001EEC02 mmcra:0X00000000
+
+#Group 134 pm_dcache, D cache
+event:0X0860 mmcr0:0X00000000 mmcr1:0X000000000C0E0C06 mmcra:0X00000000
+event:0X0861 mmcr0:0X00000000 mmcr1:0X000000000C0E0C06 mmcra:0X00000000
+event:0X0862 mmcr0:0X00000000 mmcr1:0X000000000C0E0C06 mmcra:0X00000000
+event:0X0863 mmcr0:0X00000000 mmcr1:0X000000000C0E0C06 mmcra:0X00000000
+
+#Group 135 pm_derat_miss, DERAT miss
+event:0X0870 mmcr0:0X00000000 mmcr1:0X0090000F40404040 mmcra:0X00000000
+event:0X0871 mmcr0:0X00000000 mmcr1:0X0090000F40404040 mmcra:0X00000000
+event:0X0872 mmcr0:0X00000000 mmcr1:0X0090000F40404040 mmcra:0X00000000
+event:0X0873 mmcr0:0X00000000 mmcr1:0X0090000F40404040 mmcra:0X00000000
+
+#Group 136 pm_derat_ref, DERAT ref
+event:0X0880 mmcr0:0X00000000 mmcr1:0X0080000F40404040 mmcra:0X00000000
+event:0X0881 mmcr0:0X00000000 mmcr1:0X0080000F40404040 mmcra:0X00000000
+event:0X0882 mmcr0:0X00000000 mmcr1:0X0080000F40404040 mmcra:0X00000000
+event:0X0883 mmcr0:0X00000000 mmcr1:0X0080000F40404040 mmcra:0X00000000
+
+#Group 137 pm_ierat_miss, IERAT miss
+event:0X0890 mmcr0:0X00000000 mmcr1:0X0090000F46464646 mmcra:0X00000000
+event:0X0891 mmcr0:0X00000000 mmcr1:0X0090000F46464646 mmcra:0X00000000
+event:0X0892 mmcr0:0X00000000 mmcr1:0X0090000F46464646 mmcra:0X00000000
+event:0X0893 mmcr0:0X00000000 mmcr1:0X0090000F46464646 mmcra:0X00000000
+
+#Group 138 pm_mrk_br, Marked Branch events
+event:0X08A0 mmcr0:0X00000000 mmcr1:0X0000000052565202 mmcra:0X00000001
+event:0X08A1 mmcr0:0X00000000 mmcr1:0X0000000052565202 mmcra:0X00000001
+event:0X08A2 mmcr0:0X00000000 mmcr1:0X0000000052565202 mmcra:0X00000001
+event:0X08A3 mmcr0:0X00000000 mmcr1:0X0000000052565202 mmcra:0X00000001
+
+#Group 139 pm_mrk_dsource, Marked data sources
+event:0X08B0 mmcr0:0X00000000 mmcr1:0X00000000024A4C4C mmcra:0X00000001
+event:0X08B1 mmcr0:0X00000000 mmcr1:0X00000000024A4C4C mmcra:0X00000001
+event:0X08B2 mmcr0:0X00000000 mmcr1:0X00000000024A4C4C mmcra:0X00000001
+event:0X08B3 mmcr0:0X00000000 mmcr1:0X00000000024A4C4C mmcra:0X00000001
+
+#Group 140 pm_mrk_dsource2, Marked data sources
+event:0X08C0 mmcr0:0X00000000 mmcr1:0X0000000048484E02 mmcra:0X00000001
+event:0X08C1 mmcr0:0X00000000 mmcr1:0X0000000048484E02 mmcra:0X00000001
+event:0X08C2 mmcr0:0X00000000 mmcr1:0X0000000048484E02 mmcra:0X00000001
+event:0X08C3 mmcr0:0X00000000 mmcr1:0X0000000048484E02 mmcra:0X00000001
+
+#Group 141 pm_mrk_dsource3, Marked data sources
+event:0X08D0 mmcr0:0X00000000 mmcr1:0X000000002802484E mmcra:0X00000001
+event:0X08D1 mmcr0:0X00000000 mmcr1:0X000000002802484E mmcra:0X00000001
+event:0X08D2 mmcr0:0X00000000 mmcr1:0X000000002802484E mmcra:0X00000001
+event:0X08D3 mmcr0:0X00000000 mmcr1:0X000000002802484E mmcra:0X00000001
+
+#Group 142 pm_mrk_dsource4, Marked data sources
+event:0X08E0 mmcr0:0X00000000 mmcr1:0X000000004E4E2802 mmcra:0X00000001
+event:0X08E1 mmcr0:0X00000000 mmcr1:0X000000004E4E2802 mmcra:0X00000001
+event:0X08E2 mmcr0:0X00000000 mmcr1:0X000000004E4E2802 mmcra:0X00000001
+event:0X08E3 mmcr0:0X00000000 mmcr1:0X000000004E4E2802 mmcra:0X00000001
+
+#Group 143 pm_mrk_dsource5, Marked data sources
+event:0X08F0 mmcr0:0X00000000 mmcr1:0X000000004A4C024A mmcra:0X00000001
+event:0X08F1 mmcr0:0X00000000 mmcr1:0X000000004A4C024A mmcra:0X00000001
+event:0X08F2 mmcr0:0X00000000 mmcr1:0X000000004A4C024A mmcra:0X00000001
+event:0X08F3 mmcr0:0X00000000 mmcr1:0X000000004A4C024A mmcra:0X00000001
+
+#Group 144 pm_mrk_dsource6, Marked data sources
+event:0X0900 mmcr0:0X00000000 mmcr1:0X000000004C4C4A02 mmcra:0X00000001
+event:0X0901 mmcr0:0X00000000 mmcr1:0X000000004C4C4A02 mmcra:0X00000001
+event:0X0902 mmcr0:0X00000000 mmcr1:0X000000004C4C4A02 mmcra:0X00000001
+event:0X0903 mmcr0:0X00000000 mmcr1:0X000000004C4C4A02 mmcra:0X00000001
+
+#Group 145 pm_mrk_rejects, Marked rejects
+event:0X0910 mmcr0:0X00000000 mmcr1:0X0009000D34340230 mmcra:0X00000001
+event:0X0911 mmcr0:0X00000000 mmcr1:0X0009000D34340230 mmcra:0X00000001
+event:0X0912 mmcr0:0X00000000 mmcr1:0X0009000D34340230 mmcra:0X00000001
+event:0X0913 mmcr0:0X00000000 mmcr1:0X0009000D34340230 mmcra:0X00000001
+
+#Group 146 pm_mrk_rejects2, Marked rejects LSU0
+event:0X0920 mmcr0:0X00000000 mmcr1:0X00090000E6E0C202 mmcra:0X00000001
+event:0X0921 mmcr0:0X00000000 mmcr1:0X00090000E6E0C202 mmcra:0X00000001
+event:0X0922 mmcr0:0X00000000 mmcr1:0X00090000E6E0C202 mmcra:0X00000001
+event:0X0923 mmcr0:0X00000000 mmcr1:0X00090000E6E0C202 mmcra:0X00000001
+
+#Group 147 pm_mrk_rejects3, Marked rejects LSU1
+event:0X0930 mmcr0:0X00000000 mmcr1:0X00090000EEE8CA02 mmcra:0X00000001
+event:0X0931 mmcr0:0X00000000 mmcr1:0X00090000EEE8CA02 mmcra:0X00000001
+event:0X0932 mmcr0:0X00000000 mmcr1:0X00090000EEE8CA02 mmcra:0X00000001
+event:0X0933 mmcr0:0X00000000 mmcr1:0X00090000EEE8CA02 mmcra:0X00000001
+
+#Group 148 pm_mrk_inst, Marked instruction events
+event:0X0940 mmcr0:0X00000000 mmcr1:0X000000001C100A02 mmcra:0X00000001
+event:0X0941 mmcr0:0X00000000 mmcr1:0X000000001C100A02 mmcra:0X00000001
+event:0X0942 mmcr0:0X00000000 mmcr1:0X000000001C100A02 mmcra:0X00000001
+event:0X0943 mmcr0:0X00000000 mmcr1:0X000000001C100A02 mmcra:0X00000001
+
+#Group 149 pm_mrk_fpu_fin, Marked Floating Point instructions finished
+event:0X0950 mmcr0:0X00000000 mmcr1:0XD0000000828A1A02 mmcra:0X00000001
+event:0X0951 mmcr0:0X00000000 mmcr1:0XD0000000828A1A02 mmcra:0X00000001
+event:0X0952 mmcr0:0X00000000 mmcr1:0XD0000000828A1A02 mmcra:0X00000001
+event:0X0953 mmcr0:0X00000000 mmcr1:0XD0000000828A1A02 mmcra:0X00000001
+
+#Group 150 pm_mrk_misc, Marked misc events
+event:0X0960 mmcr0:0X00000000 mmcr1:0X00090008341A0802 mmcra:0X00000001
+event:0X0961 mmcr0:0X00000000 mmcr1:0X00090008341A0802 mmcra:0X00000001
+event:0X0962 mmcr0:0X00000000 mmcr1:0X00090008341A0802 mmcra:0X00000001
+event:0X0963 mmcr0:0X00000000 mmcr1:0X00090008341A0802 mmcra:0X00000001
+
+#Group 151 pm_mrk_misc2, Marked misc events
+event:0X0970 mmcr0:0X00000000 mmcr1:0X00080000E40A023E mmcra:0X00000001
+event:0X0971 mmcr0:0X00000000 mmcr1:0X00080000E40A023E mmcra:0X00000001
+event:0X0972 mmcr0:0X00000000 mmcr1:0X00080000E40A023E mmcra:0X00000001
+event:0X0973 mmcr0:0X00000000 mmcr1:0X00080000E40A023E mmcra:0X00000001
+
+#Group 152 pm_mrk_misc3, Marked misc events
+event:0X0980 mmcr0:0X00000000 mmcr1:0XB009000088E40212 mmcra:0X00000001
+event:0X0981 mmcr0:0X00000000 mmcr1:0XB009000088E40212 mmcra:0X00000001
+event:0X0982 mmcr0:0X00000000 mmcr1:0XB009000088E40212 mmcra:0X00000001
+event:0X0983 mmcr0:0X00000000 mmcr1:0XB009000088E40212 mmcra:0X00000001
+
+#Group 153 pm_mrk_misc4, Marked misc events
+event:0X0990 mmcr0:0X00000000 mmcr1:0X000000001E1E021A mmcra:0X00000001
+event:0X0991 mmcr0:0X00000000 mmcr1:0X000000001E1E021A mmcra:0X00000001
+event:0X0992 mmcr0:0X00000000 mmcr1:0X000000001E1E021A mmcra:0X00000001
+event:0X0993 mmcr0:0X00000000 mmcr1:0X000000001E1E021A mmcra:0X00000001
+
+#Group 154 pm_mrk_st, Marked stores events
+event:0X09A0 mmcr0:0X00000000 mmcr1:0X0000000006060602 mmcra:0X00000001
+event:0X09A1 mmcr0:0X00000000 mmcr1:0X0000000006060602 mmcra:0X00000001
+event:0X09A2 mmcr0:0X00000000 mmcr1:0X0000000006060602 mmcra:0X00000001
+event:0X09A3 mmcr0:0X00000000 mmcr1:0X0000000006060602 mmcra:0X00000001
+
+#Group 155 pm_mrk_pteg, Marked PTEG
+event:0X09B0 mmcr0:0X00000000 mmcr1:0X0010000040424402 mmcra:0X00000001
+event:0X09B1 mmcr0:0X00000000 mmcr1:0X0010000040424402 mmcra:0X00000001
+event:0X09B2 mmcr0:0X00000000 mmcr1:0X0010000040424402 mmcra:0X00000001
+event:0X09B3 mmcr0:0X00000000 mmcr1:0X0010000040424402 mmcra:0X00000001
+
+#Group 156 pm_mrk_pteg2, Marked PTEG
+event:0X09C0 mmcr0:0X00000000 mmcr1:0X0010000002404644 mmcra:0X00000001
+event:0X09C1 mmcr0:0X00000000 mmcr1:0X0010000002404644 mmcra:0X00000001
+event:0X09C2 mmcr0:0X00000000 mmcr1:0X0010000002404644 mmcra:0X00000001
+event:0X09C3 mmcr0:0X00000000 mmcr1:0X0010000002404644 mmcra:0X00000001
+
+#Group 157 pm_mrk_pteg3, Marked PTEG
+event:0X09D0 mmcr0:0X00000000 mmcr1:0X0010000046460246 mmcra:0X00000001
+event:0X09D1 mmcr0:0X00000000 mmcr1:0X0010000046460246 mmcra:0X00000001
+event:0X09D2 mmcr0:0X00000000 mmcr1:0X0010000046460246 mmcra:0X00000001
+event:0X09D3 mmcr0:0X00000000 mmcr1:0X0010000046460246 mmcra:0X00000001
+
+#Group 158 pm_mrk_pteg4, Marked PTEG
+event:0X09E0 mmcr0:0X00000000 mmcr1:0X0010000042024054 mmcra:0X00000001
+event:0X09E1 mmcr0:0X00000000 mmcr1:0X0010000042024054 mmcra:0X00000001
+event:0X09E2 mmcr0:0X00000000 mmcr1:0X0010000042024054 mmcra:0X00000001
+event:0X09E3 mmcr0:0X00000000 mmcr1:0X0010000042024054 mmcra:0X00000001
+
+#Group 159 pm_mrk_pteg5, Marked PTEG
+event:0X09F0 mmcr0:0X00000000 mmcr1:0X0010000044025442 mmcra:0X00000001
+event:0X09F1 mmcr0:0X00000000 mmcr1:0X0010000044025442 mmcra:0X00000001
+event:0X09F2 mmcr0:0X00000000 mmcr1:0X0010000044025442 mmcra:0X00000001
+event:0X09F3 mmcr0:0X00000000 mmcr1:0X0010000044025442 mmcra:0X00000001
+
+#Group 160 pm_mrk_pteg6, Marked PTEG
+event:0X0A00 mmcr0:0X00000000 mmcr1:0X001000001E444202 mmcra:0X00000001
+event:0X0A01 mmcr0:0X00000000 mmcr1:0X001000001E444202 mmcra:0X00000001
+event:0X0A02 mmcr0:0X00000000 mmcr1:0X001000001E444202 mmcra:0X00000001
+event:0X0A03 mmcr0:0X00000000 mmcr1:0X001000001E444202 mmcra:0X00000001
+
+#Group 161 pm_mrk_vmx, Marked VMX
+event:0X0A10 mmcr0:0X00000000 mmcr1:0X700000008C88AE02 mmcra:0X00000001
+event:0X0A11 mmcr0:0X00000000 mmcr1:0X700000008C88AE02 mmcra:0X00000001
+event:0X0A12 mmcr0:0X00000000 mmcr1:0X700000008C88AE02 mmcra:0X00000001
+event:0X0A13 mmcr0:0X00000000 mmcr1:0X700000008C88AE02 mmcra:0X00000001
+
+#Group 162 pm_mrk_vmx2, Marked VMX
+event:0X0A20 mmcr0:0X00000000 mmcr1:0X60900000868EE002 mmcra:0X00000001
+event:0X0A21 mmcr0:0X00000000 mmcr1:0X60900000868EE002 mmcra:0X00000001
+event:0X0A22 mmcr0:0X00000000 mmcr1:0X60900000868EE002 mmcra:0X00000001
+event:0X0A23 mmcr0:0X00000000 mmcr1:0X60900000868EE002 mmcra:0X00000001
+
+#Group 163 pm_mrk_vmx3, Marked VMX
+event:0X0A30 mmcr0:0X00000000 mmcr1:0X700000008A821E02 mmcra:0X00000001
+event:0X0A31 mmcr0:0X00000000 mmcr1:0X700000008A821E02 mmcra:0X00000001
+event:0X0A32 mmcr0:0X00000000 mmcr1:0X700000008A821E02 mmcra:0X00000001
+event:0X0A33 mmcr0:0X00000000 mmcr1:0X700000008A821E02 mmcra:0X00000001
+
+#Group 164 pm_mrk_fp, Marked FP events
+event:0X0A40 mmcr0:0X00000000 mmcr1:0XD00000008230AA02 mmcra:0X00000001
+event:0X0A41 mmcr0:0X00000000 mmcr1:0XD00000008230AA02 mmcra:0X00000001
+event:0X0A42 mmcr0:0X00000000 mmcr1:0XD00000008230AA02 mmcra:0X00000001
+event:0X0A43 mmcr0:0X00000000 mmcr1:0XD00000008230AA02 mmcra:0X00000001
+
+#Group 165 pm_mrk_derat_ref, Marked DERAT ref
+event:0X0A50 mmcr0:0X00000000 mmcr1:0X0080000044444402 mmcra:0X00000001
+event:0X0A51 mmcr0:0X00000000 mmcr1:0X0080000044444402 mmcra:0X00000001
+event:0X0A52 mmcr0:0X00000000 mmcr1:0X0080000044444402 mmcra:0X00000001
+event:0X0A53 mmcr0:0X00000000 mmcr1:0X0080000044444402 mmcra:0X00000001
+
+#Group 166 pm_mrk_derat_miss, Marked DERAT miss
+event:0X0A60 mmcr0:0X00000000 mmcr1:0X0090000044444402 mmcra:0X00000001
+event:0X0A61 mmcr0:0X00000000 mmcr1:0X0090000044444402 mmcra:0X00000001
+event:0X0A62 mmcr0:0X00000000 mmcr1:0X0090000044444402 mmcra:0X00000001
+event:0X0A63 mmcr0:0X00000000 mmcr1:0X0090000044444402 mmcra:0X00000001
+
+#Group 167 pm_dcache_edge, D cache - edge
+event:0X0A70 mmcr0:0X00000000 mmcr1:0X000000000D0E0C07 mmcra:0X00000000
+event:0X0A71 mmcr0:0X00000000 mmcr1:0X000000000D0E0C07 mmcra:0X00000000
+event:0X0A72 mmcr0:0X00000000 mmcr1:0X000000000D0E0C07 mmcra:0X00000000
+event:0X0A73 mmcr0:0X00000000 mmcr1:0X000000000D0E0C07 mmcra:0X00000000
+
+#Group 168 pm_lsu_lmq_edge, LSU LMQ events - edge
+event:0X0A80 mmcr0:0X00000000 mmcr1:0X98000000AC1D1DA4 mmcra:0X00000000
+event:0X0A81 mmcr0:0X00000000 mmcr1:0X98000000AC1D1DA4 mmcra:0X00000000
+event:0X0A82 mmcr0:0X00000000 mmcr1:0X98000000AC1D1DA4 mmcra:0X00000000
+event:0X0A83 mmcr0:0X00000000 mmcr1:0X98000000AC1D1DA4 mmcra:0X00000000
+
+#Group 169 pm_gct_edge, GCT events - edge
+event:0X0A90 mmcr0:0X00000000 mmcr1:0X404000000909A7E8 mmcra:0X00000000
+event:0X0A91 mmcr0:0X00000000 mmcr1:0X404000000909A7E8 mmcra:0X00000000
+event:0X0A92 mmcr0:0X00000000 mmcr1:0X404000000909A7E8 mmcra:0X00000000
+event:0X0A93 mmcr0:0X00000000 mmcr1:0X404000000909A7E8 mmcra:0X00000000
+
+#Group 170 pm_freq_edge, Frequency events - edge
+event:0X0AA0 mmcr0:0X00000000 mmcr1:0X000000002B3D3C3C mmcra:0X00000000
+event:0X0AA1 mmcr0:0X00000000 mmcr1:0X000000002B3D3C3C mmcra:0X00000000
+event:0X0AA2 mmcr0:0X00000000 mmcr1:0X000000002B3D3C3C mmcra:0X00000000
+event:0X0AA3 mmcr0:0X00000000 mmcr1:0X000000002B3D3C3C mmcra:0X00000000
+
+#Group 171 pm_disp_wait_edge, Dispatch stalls - edge
+event:0X0AB0 mmcr0:0X00000000 mmcr1:0X00000000560D050D mmcra:0X00000000
+event:0X0AB1 mmcr0:0X00000000 mmcr1:0X00000000560D050D mmcra:0X00000000
+event:0X0AB2 mmcr0:0X00000000 mmcr1:0X00000000560D050D mmcra:0X00000000
+event:0X0AB3 mmcr0:0X00000000 mmcr1:0X00000000560D050D mmcra:0X00000000
+
+#Group 172 pm_edge1, EDGE event group
+event:0X0AC0 mmcr0:0X00000000 mmcr1:0X000006300D0C1F1E mmcra:0X00000000
+event:0X0AC1 mmcr0:0X00000000 mmcr1:0X000006300D0C1F1E mmcra:0X00000000
+event:0X0AC2 mmcr0:0X00000000 mmcr1:0X000006300D0C1F1E mmcra:0X00000000
+event:0X0AC3 mmcr0:0X00000000 mmcr1:0X000006300D0C1F1E mmcra:0X00000000
+
+#Group 173 pm_edge2, EDGE event group
+event:0X0AD0 mmcr0:0X00000000 mmcr1:0X400000008180A5A4 mmcra:0X00000000
+event:0X0AD1 mmcr0:0X00000000 mmcr1:0X400000008180A5A4 mmcra:0X00000000
+event:0X0AD2 mmcr0:0X00000000 mmcr1:0X400000008180A5A4 mmcra:0X00000000
+event:0X0AD3 mmcr0:0X00000000 mmcr1:0X400000008180A5A4 mmcra:0X00000000
+
+#Group 174 pm_edge3, EDGE event group
+event:0X0AE0 mmcr0:0X00000000 mmcr1:0X009000000BF4EBEA mmcra:0X00000000
+event:0X0AE1 mmcr0:0X00000000 mmcr1:0X009000000BF4EBEA mmcra:0X00000000
+event:0X0AE2 mmcr0:0X00000000 mmcr1:0X009000000BF4EBEA mmcra:0X00000000
+event:0X0AE3 mmcr0:0X00000000 mmcr1:0X009000000BF4EBEA mmcra:0X00000000
+
+#Group 175 pm_edge4, EDGE event group
+event:0X0AF0 mmcr0:0X00000000 mmcr1:0X400000008786A9A8 mmcra:0X00000000
+event:0X0AF1 mmcr0:0X00000000 mmcr1:0X400000008786A9A8 mmcra:0X00000000
+event:0X0AF2 mmcr0:0X00000000 mmcr1:0X400000008786A9A8 mmcra:0X00000000
+event:0X0AF3 mmcr0:0X00000000 mmcr1:0X400000008786A9A8 mmcra:0X00000000
+
+#Group 176 pm_edge5, EDGE event group
+event:0X0B00 mmcr0:0X00000000 mmcr1:0X00900000FB17EDEC mmcra:0X00000000
+event:0X0B01 mmcr0:0X00000000 mmcr1:0X00900000FB17EDEC mmcra:0X00000000
+event:0X0B02 mmcr0:0X00000000 mmcr1:0X00900000FB17EDEC mmcra:0X00000000
+event:0X0B03 mmcr0:0X00000000 mmcr1:0X00900000FB17EDEC mmcra:0X00000000
+
+#Group 177 pm_noedge5, EDGE event group
+event:0X0B10 mmcr0:0X00000000 mmcr1:0X00900000FA16EDEC mmcra:0X00000000
+event:0X0B11 mmcr0:0X00000000 mmcr1:0X00900000FA16EDEC mmcra:0X00000000
+event:0X0B12 mmcr0:0X00000000 mmcr1:0X00900000FA16EDEC mmcra:0X00000000
+event:0X0B13 mmcr0:0X00000000 mmcr1:0X00900000FA16EDEC mmcra:0X00000000
+
+#Group 178 pm_edge6, EDGE event group
+event:0X0B20 mmcr0:0X00000000 mmcr1:0X000000002B05050D mmcra:0X00000000
+event:0X0B21 mmcr0:0X00000000 mmcr1:0X000000002B05050D mmcra:0X00000000
+event:0X0B22 mmcr0:0X00000000 mmcr1:0X000000002B05050D mmcra:0X00000000
+event:0X0B23 mmcr0:0X00000000 mmcr1:0X000000002B05050D mmcra:0X00000000
+
+#Group 179 pm_noedge6, EDGE event group
+event:0X0B30 mmcr0:0X00000000 mmcr1:0X000000002A04040C mmcra:0X00000000
+event:0X0B31 mmcr0:0X00000000 mmcr1:0X000000002A04040C mmcra:0X00000000
+event:0X0B32 mmcr0:0X00000000 mmcr1:0X000000002A04040C mmcra:0X00000000
+event:0X0B33 mmcr0:0X00000000 mmcr1:0X000000002A04040C mmcra:0X00000000
+
+#Group 180 pm_edge7, EDGE event group
+event:0X0B40 mmcr0:0X00000000 mmcr1:0X0000000009091D1D mmcra:0X00000000
+event:0X0B41 mmcr0:0X00000000 mmcr1:0X0000000009091D1D mmcra:0X00000000
+event:0X0B42 mmcr0:0X00000000 mmcr1:0X0000000009091D1D mmcra:0X00000000
+event:0X0B43 mmcr0:0X00000000 mmcr1:0X0000000009091D1D mmcra:0X00000000
+
+#Group 181 pm_noedge7, NOEDGE event group
+event:0X0B50 mmcr0:0X00000000 mmcr1:0X0000000008081C1C mmcra:0X00000000
+event:0X0B51 mmcr0:0X00000000 mmcr1:0X0000000008081C1C mmcra:0X00000000
+event:0X0B52 mmcr0:0X00000000 mmcr1:0X0000000008081C1C mmcra:0X00000000
+event:0X0B53 mmcr0:0X00000000 mmcr1:0X0000000008081C1C mmcra:0X00000000
+
+#Group 182 pm_edge8, EDGE event group
+event:0X0B60 mmcr0:0X00000000 mmcr1:0X00900000CD1DEC07 mmcra:0X00000000
+event:0X0B61 mmcr0:0X00000000 mmcr1:0X00900000CD1DEC07 mmcra:0X00000000
+event:0X0B62 mmcr0:0X00000000 mmcr1:0X00900000CD1DEC07 mmcra:0X00000000
+event:0X0B63 mmcr0:0X00000000 mmcr1:0X00900000CD1DEC07 mmcra:0X00000000
+
+#Group 183 pm_noedge8, NOEDGE event group
+event:0X0B70 mmcr0:0X00000000 mmcr1:0X00900000CC1CED06 mmcra:0X00000000
+event:0X0B71 mmcr0:0X00000000 mmcr1:0X00900000CC1CED06 mmcra:0X00000000
+event:0X0B72 mmcr0:0X00000000 mmcr1:0X00900000CC1CED06 mmcra:0X00000000
+event:0X0B73 mmcr0:0X00000000 mmcr1:0X00900000CC1CED06 mmcra:0X00000000
+
+#Group 184 pm_edge9, EDGE event group
+event:0X0B80 mmcr0:0X00000000 mmcr1:0X80000000880D0CA2 mmcra:0X00000000
+event:0X0B81 mmcr0:0X00000000 mmcr1:0X80000000880D0CA2 mmcra:0X00000000
+event:0X0B82 mmcr0:0X00000000 mmcr1:0X80000000880D0CA2 mmcra:0X00000000
+event:0X0B83 mmcr0:0X00000000 mmcr1:0X80000000880D0CA2 mmcra:0X00000000
+
+#Group 185 pm_edge10, EDGE event group
+event:0X0B90 mmcr0:0X00000000 mmcr1:0X32000000AC3DAE05 mmcra:0X00000000
+event:0X0B91 mmcr0:0X00000000 mmcr1:0X32000000AC3DAE05 mmcra:0X00000000
+event:0X0B92 mmcr0:0X00000000 mmcr1:0X32000000AC3DAE05 mmcra:0X00000000
+event:0X0B93 mmcr0:0X00000000 mmcr1:0X32000000AC3DAE05 mmcra:0X00000000
+
+#Group 186 pm_noedge10, NOEDGE event group
+event:0X0BA0 mmcr0:0X00000000 mmcr1:0X32000000AC3CAE04 mmcra:0X00000000
+event:0X0BA1 mmcr0:0X00000000 mmcr1:0X32000000AC3CAE04 mmcra:0X00000000
+event:0X0BA2 mmcr0:0X00000000 mmcr1:0X32000000AC3CAE04 mmcra:0X00000000
+event:0X0BA3 mmcr0:0X00000000 mmcr1:0X32000000AC3CAE04 mmcra:0X00000000
+
+#Group 187 pm_hpm1, HPM group
+event:0X0BB0 mmcr0:0X00000000 mmcr1:0XC00000003030341E mmcra:0X00000000
+event:0X0BB1 mmcr0:0X00000000 mmcr1:0XC00000003030341E mmcra:0X00000000
+event:0X0BB2 mmcr0:0X00000000 mmcr1:0XC00000003030341E mmcra:0X00000000
+event:0X0BB3 mmcr0:0X00000000 mmcr1:0XC00000003030341E mmcra:0X00000000
+
+#Group 188 pm_hpm2, HPM group
+event:0X0BC0 mmcr0:0X00000000 mmcr1:0X8C0000000232301E mmcra:0X00000000
+event:0X0BC1 mmcr0:0X00000000 mmcr1:0X8C0000000232301E mmcra:0X00000000
+event:0X0BC2 mmcr0:0X00000000 mmcr1:0X8C0000000232301E mmcra:0X00000000
+event:0X0BC3 mmcr0:0X00000000 mmcr1:0X8C0000000232301E mmcra:0X00000000
+
+#Group 189 pm_hpm3, HPM group
+event:0X0BD0 mmcr0:0X00000000 mmcr1:0X800000001E80F002 mmcra:0X00000000
+event:0X0BD1 mmcr0:0X00000000 mmcr1:0X800000001E80F002 mmcra:0X00000000
+event:0X0BD2 mmcr0:0X00000000 mmcr1:0X800000001E80F002 mmcra:0X00000000
+event:0X0BD3 mmcr0:0X00000000 mmcr1:0X800000001E80F002 mmcra:0X00000000
+
+#Group 190 pm_hpm4, HPM group
+event:0X0BE0 mmcr0:0X00000000 mmcr1:0X800000000212A234 mmcra:0X00000000
+event:0X0BE1 mmcr0:0X00000000 mmcr1:0X800000000212A234 mmcra:0X00000000
+event:0X0BE2 mmcr0:0X00000000 mmcr1:0X800000000212A234 mmcra:0X00000000
+event:0X0BE3 mmcr0:0X00000000 mmcr1:0X800000000212A234 mmcra:0X00000000
+
+#Group 191 pm_hpm5, HPM group
+event:0X0BF0 mmcr0:0X00000000 mmcr1:0XD0000000301E1616 mmcra:0X00000000
+event:0X0BF1 mmcr0:0X00000000 mmcr1:0XD0000000301E1616 mmcra:0X00000000
+event:0X0BF2 mmcr0:0X00000000 mmcr1:0XD0000000301E1616 mmcra:0X00000000
+event:0X0BF3 mmcr0:0X00000000 mmcr1:0XD0000000301E1616 mmcra:0X00000000
+
+#Group 192 pm_hpm6, HPM group
+event:0X0C00 mmcr0:0X00000000 mmcr1:0X0000000058585A5A mmcra:0X00000000
+event:0X0C01 mmcr0:0X00000000 mmcr1:0X0000000058585A5A mmcra:0X00000000
+event:0X0C02 mmcr0:0X00000000 mmcr1:0X0000000058585A5A mmcra:0X00000000
+event:0X0C03 mmcr0:0X00000000 mmcr1:0X0000000058585A5A mmcra:0X00000000
+
+#Group 193 pm_hpm7, HPM group
+event:0X0C10 mmcr0:0X00000000 mmcr1:0X000000005A5A581E mmcra:0X00000000
+event:0X0C11 mmcr0:0X00000000 mmcr1:0X000000005A5A581E mmcra:0X00000000
+event:0X0C12 mmcr0:0X00000000 mmcr1:0X000000005A5A581E mmcra:0X00000000
+event:0X0C13 mmcr0:0X00000000 mmcr1:0X000000005A5A581E mmcra:0X00000000
+
+#Group 194 pm_hpm8, HPM group
+event:0X0C20 mmcr0:0X00000000 mmcr1:0XCC000000303030F0 mmcra:0X00000000
+event:0X0C21 mmcr0:0X00000000 mmcr1:0XCC000000303030F0 mmcra:0X00000000
+event:0X0C22 mmcr0:0X00000000 mmcr1:0XCC000000303030F0 mmcra:0X00000000
+event:0X0C23 mmcr0:0X00000000 mmcr1:0XCC000000303030F0 mmcra:0X00000000
+
+#Group 195 pm_hpm9, HPM group
+event:0X0C30 mmcr0:0X00000000 mmcr1:0X80000000801E34A8 mmcra:0X00000000
+event:0X0C31 mmcr0:0X00000000 mmcr1:0X80000000801E34A8 mmcra:0X00000000
+event:0X0C32 mmcr0:0X00000000 mmcr1:0X80000000801E34A8 mmcra:0X00000000
+event:0X0C33 mmcr0:0X00000000 mmcr1:0X80000000801E34A8 mmcra:0X00000000
+
+#Group 196 pm_hpm10, HPM group
+event:0X0C40 mmcr0:0X00000000 mmcr1:0X5040A00002325456 mmcra:0X00000000
+event:0X0C41 mmcr0:0X00000000 mmcr1:0X5040A00002325456 mmcra:0X00000000
+event:0X0C42 mmcr0:0X00000000 mmcr1:0X5040A00002325456 mmcra:0X00000000
+event:0X0C43 mmcr0:0X00000000 mmcr1:0X5040A00002325456 mmcra:0X00000000
+
+#Group 197 pm_mrk_derat_ref2, Marked DERAT ref
+event:0X0C50 mmcr0:0X00000000 mmcr1:0X0080000044440244 mmcra:0X00000001
+event:0X0C51 mmcr0:0X00000000 mmcr1:0X0080000044440244 mmcra:0X00000001
+event:0X0C52 mmcr0:0X00000000 mmcr1:0X0080000044440244 mmcra:0X00000001
+event:0X0C53 mmcr0:0X00000000 mmcr1:0X0080000044440244 mmcra:0X00000001
+
+#Group 198 pm_mrk_derat_miss2, Marked DERAT miss
+event:0X0C60 mmcr0:0X00000000 mmcr1:0X0090000044440244 mmcra:0X00000001
+event:0X0C61 mmcr0:0X00000000 mmcr1:0X0090000044440244 mmcra:0X00000001
+event:0X0C62 mmcr0:0X00000000 mmcr1:0X0090000044440244 mmcra:0X00000001
+event:0X0C63 mmcr0:0X00000000 mmcr1:0X0090000044440244 mmcra:0X00000001
diff --git a/events/ppc64/power6/events b/events/ppc64/power6/events
new file mode 100644
index 0000000..ee5be72
--- /dev/null
+++ b/events/ppc64/power6/events
@@ -0,0 +1,1211 @@
+#PPC64 POWER6 events
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2007.
+# Contributed by Dave Nomura <dcnltc@us.ibm.com>.
+#
+#
+# Within each group the event names must be unique. Each event in a group is
+# assigned to a unique counter. The groups are from the groups defined in the
+# Performance Monitor Unit user guide for this processor.
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:3 um:zero minimum:10000 name:CYCLES : Processor Cycles
+
+#Group 0 with random sampling
+event:0X002 counters:1 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
+
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X0010 counters:0 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Run cycles
+event:0X0011 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Instructions completed
+event:0X0012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Instructions dispatched
+event:0X0013 counters:3 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor cycles
+
+#Group 2 pm_utilization_capacity, CPU utilization and capacity
+event:0X0020 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP2 : (Group 2 pm_utilization_capacity) One of the threads in run cycles
+event:0X0021 counters:1 um:zero minimum:10000 name:PM_CYC_GRP2 : (Group 2 pm_utilization_capacity) Processor cycles
+event:0X0022 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP2 : (Group 2 pm_utilization_capacity) Concurrent run instructions
+event:0X0023 counters:3 um:zero minimum:1000 name:PM_RUN_PURR_GRP2 : (Group 2 pm_utilization_capacity) Run PURR Event
+
+#Group 3 pm_branch, Branch operations
+event:0X0030 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP3 : (Group 3 pm_branch) A conditional branch was predicted, CR prediction
+event:0X0031 counters:1 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP3 : (Group 3 pm_branch) Branch mispredictions due to CR bit setting
+event:0X0032 counters:2 um:zero minimum:1000 name:PM_BR_PRED_GRP3 : (Group 3 pm_branch) A conditional branch was predicted
+event:0X0033 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_COUNT_GRP3 : (Group 3 pm_branch) Branch misprediction due to count prediction
+
+#Group 4 pm_branch2, Branch operations
+event:0X0040 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP4 : (Group 4 pm_branch2) Branch count cache prediction
+event:0X0041 counters:1 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP4 : (Group 4 pm_branch2) A conditional branch was predicted, link stack
+event:0X0042 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP4 : (Group 4 pm_branch2) Branch misprediction due to count cache prediction
+event:0X0043 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP4 : (Group 4 pm_branch2) Branch mispredictions due to target address
+
+#Group 5 pm_branch3, Branch operations
+event:0X0050 counters:0 um:zero minimum:1000 name:PM_BR_PRED_GRP5 : (Group 5 pm_branch3) A conditional branch was predicted
+event:0X0051 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP5 : (Group 5 pm_branch3) A conditional branch was predicted, CR prediction
+event:0X0052 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP5 : (Group 5 pm_branch3) Branch count cache prediction
+event:0X0053 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP5 : (Group 5 pm_branch3) A conditional branch was predicted, link stack
+
+#Group 6 pm_branch4, Branch operations
+event:0X0060 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP6 : (Group 6 pm_branch4) Branch mispredictions due to CR bit setting
+event:0X0061 counters:1 um:zero minimum:1000 name:PM_BR_MPRED_COUNT_GRP6 : (Group 6 pm_branch4) Branch misprediction due to count prediction
+event:0X0062 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP6 : (Group 6 pm_branch4) Branch mispredictions due to target address
+event:0X0063 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP6 : (Group 6 pm_branch4) Branch misprediction due to count cache prediction
+
+#Group 7 pm_branch5, Branch operations
+event:0X0070 counters:0 um:zero minimum:1000 name:PM_BR_PRED_GRP7 : (Group 7 pm_branch5) A conditional branch was predicted
+event:0X0071 counters:1 um:zero minimum:1000 name:PM_BR_TAKEN_GRP7 : (Group 7 pm_branch5) Branches taken
+event:0X0072 counters:2 um:zero minimum:1000 name:PM_BRU_FIN_GRP7 : (Group 7 pm_branch5) BRU produced a result
+event:0X0073 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP7 : (Group 7 pm_branch5) Branches incorrectly predicted
+
+#Group 8 pm_dsource, Data source
+event:0X0080 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP8 : (Group 8 pm_dsource) Data loaded from L2
+event:0X0081 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L21_GRP8 : (Group 8 pm_dsource) Data loaded from private L2 other core
+event:0X0082 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP8 : (Group 8 pm_dsource) Data loaded missed L2
+event:0X0083 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP8 : (Group 8 pm_dsource) Data loaded from private L3 miss
+
+#Group 9 pm_dsource2, Data sources
+event:0X0090 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP9 : (Group 9 pm_dsource2) Data loaded from L3.5 modified
+event:0X0091 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_GRP9 : (Group 9 pm_dsource2) Data loaded from L3.5 shared
+event:0X0092 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP9 : (Group 9 pm_dsource2) Data loaded from L3
+event:0X0093 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP9 : (Group 9 pm_dsource2) Data loaded from private L3 miss
+
+#Group 10 pm_dsource3, Data sources
+event:0X00A0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP10 : (Group 10 pm_dsource3) Data loaded from L3.5 modified
+event:0X00A1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_GRP10 : (Group 10 pm_dsource3) Data loaded from L3.5 shared
+event:0X00A2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP10 : (Group 10 pm_dsource3) Data loaded from L2.5 modified
+event:0X00A3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP10 : (Group 10 pm_dsource3) Data loaded from L2.5 shared
+
+#Group 11 pm_dsource4, Data sources
+event:0X00B0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP11 : (Group 11 pm_dsource4) Data loaded from remote L2 or L3 modified
+event:0X00B1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP11 : (Group 11 pm_dsource4) Data loaded from remote L2 or L3 shared
+event:0X00B2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_GRP11 : (Group 11 pm_dsource4) Data loaded from distant L2 or L3 shared
+event:0X00B3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP11 : (Group 11 pm_dsource4) Data loaded from distant L2 or L3 modified
+
+#Group 12 pm_dsource5, Data sources
+event:0X00C0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_MEM_DP_GRP12 : (Group 12 pm_dsource5) Data loaded from double pump memory
+event:0X00C1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP12 : (Group 12 pm_dsource5) Data loaded from distant memory
+event:0X00C2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP12 : (Group 12 pm_dsource5) Data loaded from remote memory
+event:0X00C3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP12 : (Group 12 pm_dsource5) Data loaded from local memory
+
+#Group 13 pm_dlatencies, Data latencies
+event:0X00D0 counters:0 um:zero minimum:1000 name:PM_LD_MISS_L1_CYC_GRP13 : (Group 13 pm_dlatencies) L1 data load miss cycles
+event:0X00D1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_CYC_GRP13 : (Group 13 pm_dlatencies) Load latency from remote L2 or L3 shared
+event:0X00D2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP13 : (Group 13 pm_dlatencies) Processor cycles
+event:0X00D3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_CYC_GRP13 : (Group 13 pm_dlatencies) Load latency from L2.5 modified
+
+#Group 14 pm_dlatencies2, Data latencies
+event:0X00E0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP14 : (Group 14 pm_dlatencies2) Instructions completed
+event:0X00E1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_CYC_GRP14 : (Group 14 pm_dlatencies2) Load latency from local memory
+event:0X00E2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP14 : (Group 14 pm_dlatencies2) Processor cycles
+event:0X00E3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_CYC_GRP14 : (Group 14 pm_dlatencies2) Load latency from distant L2 or L3 modified
+
+#Group 15 pm_dlatencies3, Data latencies
+event:0X00F0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP15 : (Group 15 pm_dlatencies3) Instructions completed
+event:0X00F1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_CYC_GRP15 : (Group 15 pm_dlatencies3) Load latency from distant memory
+event:0X00F2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP15 : (Group 15 pm_dlatencies3) Data loaded from remote memory
+event:0X00F3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_CYC_GRP15 : (Group 15 pm_dlatencies3) Load latency from remote memory
+
+#Group 16 pm_dlatencies4, Data latencies
+event:0X0100 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP16 : (Group 16 pm_dlatencies4) Data loaded from L3.5 modified
+event:0X0101 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_CYC_GRP16 : (Group 16 pm_dlatencies4) Load latency from distant L2 or L3 shared
+event:0X0102 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_GRP16 : (Group 16 pm_dlatencies4) Data loaded from distant L2 or L3 shared
+event:0X0103 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_CYC_GRP16 : (Group 16 pm_dlatencies4) Load latency from L3.5 modified
+
+#Group 17 pm_dlatencies5, Data latencies
+event:0X0110 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP17 : (Group 17 pm_dlatencies5) Data loaded from remote L2 or L3 modified
+event:0X0111 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3_CYC_GRP17 : (Group 17 pm_dlatencies5) Load latency from L3
+event:0X0112 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP17 : (Group 17 pm_dlatencies5) Data loaded from L3
+event:0X0113 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_CYC_GRP17 : (Group 17 pm_dlatencies5) Load latency from remote L2 or L3 modified
+
+#Group 18 pm_dlatencies6, Data latencies
+event:0X0120 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_MEM_DP_GRP18 : (Group 18 pm_dlatencies6) Data loaded from double pump memory
+event:0X0121 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_CYC_GRP18 : (Group 18 pm_dlatencies6) Load latency from L2.5 shared
+event:0X0122 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP18 : (Group 18 pm_dlatencies6) Data loaded from L2.5 modified
+event:0X0123 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_MEM_DP_CYC_GRP18 : (Group 18 pm_dlatencies6) Load latency from double pump memory
+
+#Group 19 pm_dlatencies7, Data latencies
+event:0X0130 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP19 : (Group 19 pm_dlatencies7) Data loaded from L2
+event:0X0131 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2_CYC_GRP19 : (Group 19 pm_dlatencies7) Load latency from L2
+event:0X0132 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP19 : (Group 19 pm_dlatencies7) Instructions dispatched
+event:0X0133 counters:3 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP19 : (Group 19 pm_dlatencies7) L1 reload data source valid
+
+#Group 20 pm_dlatencies8, Data latencies
+event:0X0140 counters:0 um:zero minimum:1000 name:PM_FLUSH_GRP20 : (Group 20 pm_dlatencies8) Flushes
+event:0X0141 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L21_GRP20 : (Group 20 pm_dlatencies8) Data loaded from private L2 other core
+event:0X0142 counters:2 um:zero minimum:10000 name:PM_CYC_GRP20 : (Group 20 pm_dlatencies8) Processor cycles
+event:0X0143 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L21_CYC_GRP20 : (Group 20 pm_dlatencies8) Load latency from private L2 other core
+
+#Group 21 pm_dlatencies9, Data latencies
+event:0X0150 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP21 : (Group 21 pm_dlatencies9) Cycles at least one instruction dispatched
+event:0X0151 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_CYC_GRP21 : (Group 21 pm_dlatencies9) Load latency from local memory
+event:0X0152 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP21 : (Group 21 pm_dlatencies9) Instructions dispatched
+event:0X0153 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP21 : (Group 21 pm_dlatencies9) Data loaded from local memory
+
+#Group 22 pm_dlatencies10, Data latencies
+event:0X0160 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP22 : (Group 22 pm_dlatencies10) Data loaded from L3.5 modified
+event:0X0161 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_CYC_GRP22 : (Group 22 pm_dlatencies10) Load latency from L3.5 shared
+event:0X0162 counters:2 um:zero minimum:10000 name:PM_CYC_GRP22 : (Group 22 pm_dlatencies10) Processor cycles
+event:0X0163 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_CYC_GRP22 : (Group 22 pm_dlatencies10) Load latency from L3.5 modified
+
+#Group 23 pm_isource, Instruction sources
+event:0X0170 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP23 : (Group 23 pm_isource) Instructions fetched from L2
+event:0X0171 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L21_GRP23 : (Group 23 pm_isource) Instruction fetched from private L2 other core
+event:0X0172 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L25_MOD_GRP23 : (Group 23 pm_isource) Instruction fetched from L2.5 modified
+event:0X0173 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP23 : (Group 23 pm_isource) Instructions fetched missed L2
+
+#Group 24 pm_isource2, Instruction sources
+event:0X0180 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L35_MOD_GRP24 : (Group 24 pm_isource2) Instruction fetched from L3.5 modified
+event:0X0181 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L35_SHR_GRP24 : (Group 24 pm_isource2) Instruction fetched from L3.5 shared
+event:0X0182 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP24 : (Group 24 pm_isource2) Instruction fetched from L3
+event:0X0183 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L25_SHR_GRP24 : (Group 24 pm_isource2) Instruction fetched from L2.5 shared
+
+#Group 25 pm_isource3, Instruction sources
+event:0X0190 counters:0 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_MOD_GRP25 : (Group 25 pm_isource3) Instruction fetched from remote L2 or L3 modified
+event:0X0191 counters:1 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP25 : (Group 25 pm_isource3) Instruction fetched from remote L2 or L3 shared
+event:0X0192 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_SHR_GRP25 : (Group 25 pm_isource3) Instruction fetched from distant L2 or L3 shared
+event:0X0193 counters:3 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP25 : (Group 25 pm_isource3) Instruction fetched from distant L2 or L3 modified
+
+#Group 26 pm_isource4, Instruction sources
+event:0X01A0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_MEM_DP_GRP26 : (Group 26 pm_isource4) Instruction fetched from double pump memory
+event:0X01A1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP26 : (Group 26 pm_isource4) Instruction fetched from distant memory
+event:0X01A2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP26 : (Group 26 pm_isource4) Instruction fetched from remote memory
+event:0X01A3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP26 : (Group 26 pm_isource4) Instruction fetched from local memory
+
+#Group 27 pm_isource5, Instruction sources
+event:0X01B0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP27 : (Group 27 pm_isource5) Instructions fetched from L2
+event:0X01B1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L21_GRP27 : (Group 27 pm_isource5) Instruction fetched from private L2 other core
+event:0X01B2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP27 : (Group 27 pm_isource5) Instruction fetched missed L3
+event:0X01B3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP27 : (Group 27 pm_isource5) Instructions fetched missed L2
+
+#Group 28 pm_pteg, PTEG sources
+event:0X01C0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP28 : (Group 28 pm_pteg) PTEG loaded from L2
+event:0X01C1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L21_GRP28 : (Group 28 pm_pteg) PTEG loaded from private L2 other core
+event:0X01C2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L25_MOD_GRP28 : (Group 28 pm_pteg) PTEG loaded from L2.5 modified
+event:0X01C3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L25_SHR_GRP28 : (Group 28 pm_pteg) PTEG loaded from L2.5 shared
+
+#Group 29 pm_pteg2, PTEG sources
+event:0X01D0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP29 : (Group 29 pm_pteg2) PTEG loaded from L2 miss
+event:0X01D1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L21_GRP29 : (Group 29 pm_pteg2) PTEG loaded from private L2 other core
+event:0X01D2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP29 : (Group 29 pm_pteg2) PTEG loaded from L3
+event:0X01D3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_DL2L3_MOD_GRP29 : (Group 29 pm_pteg2) PTEG loaded from distant L2 or L3 modified
+
+#Group 30 pm_pteg3, PTEG sources
+event:0X01E0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L35_MOD_GRP30 : (Group 30 pm_pteg3) PTEG loaded from L3.5 modified
+event:0X01E1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L35_SHR_GRP30 : (Group 30 pm_pteg3) PTEG loaded from L3.5 shared
+event:0X01E2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L3MISS_GRP30 : (Group 30 pm_pteg3) PTEG loaded from L3 miss
+event:0X01E3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP30 : (Group 30 pm_pteg3) PTEG loaded from local memory
+
+#Group 31 pm_pteg4, PTEG sources
+event:0X01F0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_MEM_DP_GRP31 : (Group 31 pm_pteg4) PTEG loaded from double pump memory
+event:0X01F1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_DMEM_GRP31 : (Group 31 pm_pteg4) PTEG loaded from distant memory
+event:0X01F2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP31 : (Group 31 pm_pteg4) PTEG loaded from remote memory
+event:0X01F3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP31 : (Group 31 pm_pteg4) PTEG loaded from local memory
+
+#Group 32 pm_pteg5, PTEG sources
+event:0X0200 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_RL2L3_MOD_GRP32 : (Group 32 pm_pteg5) PTEG loaded from remote L2 or L3 modified
+event:0X0201 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_RL2L3_SHR_GRP32 : (Group 32 pm_pteg5) PTEG loaded from remote L2 or L3 shared
+event:0X0202 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_DL2L3_SHR_GRP32 : (Group 32 pm_pteg5) PTEG loaded from distant L2 or L3 shared
+event:0X0203 counters:3 um:zero minimum:1000 name:PM_PTEG_RELOAD_VALID_GRP32 : (Group 32 pm_pteg5) TLB reload valid
+
+#Group 33 pm_data_tablewalk, Data tablewalks
+event:0X0210 counters:0 um:zero minimum:1000 name:PM_DATA_PTEG_1ST_HALF_GRP33 : (Group 33 pm_data_tablewalk) Data table walk matched in first half primary PTEG
+event:0X0211 counters:1 um:zero minimum:1000 name:PM_DATA_PTEG_2ND_HALF_GRP33 : (Group 33 pm_data_tablewalk) Data table walk matched in second half pri­mary PTEG
+event:0X0212 counters:2 um:zero minimum:1000 name:PM_DATA_PTEG_SECONDARY_GRP33 : (Group 33 pm_data_tablewalk) Data table walk matched in secondary PTEG
+event:0X0213 counters:3 um:zero minimum:1000 name:PM_TLB_REF_GRP33 : (Group 33 pm_data_tablewalk) TLB reference
+
+#Group 34 pm_inst_tablewalk, Instruction tablewalks
+event:0X0220 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_1ST_HALF_GRP34 : (Group 34 pm_inst_tablewalk) Instruction table walk matched in first half primary PTEG
+event:0X0221 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_2ND_HALF_GRP34 : (Group 34 pm_inst_tablewalk) Instruction table walk matched in second half primary PTEG
+event:0X0222 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_SECONDARY_GRP34 : (Group 34 pm_inst_tablewalk) Instruction table walk matched in secondary PTEG
+event:0X0223 counters:3 um:zero minimum:1000 name:PM_INST_TABLEWALK_CYC_GRP34 : (Group 34 pm_inst_tablewalk) Cycles doing instruction tablewalks
+
+#Group 35 pm_freq, Frequency events
+event:0X0230 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_THERMAL_GRP35 : (Group 35 pm_freq) DISP unit held due to thermal condition
+event:0X0231 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP35 : (Group 35 pm_freq) DISP unit held due to Power Management
+event:0X0232 counters:2 um:zero minimum:1000 name:PM_FREQ_DOWN_GRP35 : (Group 35 pm_freq) Frequency is being slewed down due to Power Management
+event:0X0233 counters:3 um:zero minimum:1000 name:PM_FREQ_UP_GRP35 : (Group 35 pm_freq) Frequency is being slewed up due to Power Management
+
+#Group 36 pm_disp_wait, Dispatch stalls
+event:0X0240 counters:0 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP36 : (Group 36 pm_disp_wait) L1 I cache miss count
+event:0X0241 counters:1 um:zero minimum:1000 name:PM_DPU_WT_IC_MISS_GRP36 : (Group 36 pm_disp_wait) Cycles DISP unit is stalled due to I cache miss
+event:0X0242 counters:2 um:zero minimum:1000 name:PM_DPU_WT_GRP36 : (Group 36 pm_disp_wait) Cycles DISP unit is stalled waiting for instructions
+event:0X0243 counters:3 um:zero minimum:1000 name:PM_DPU_WT_BR_MPRED_GRP36 : (Group 36 pm_disp_wait) Cycles DISP unit is stalled due to branch misprediction
+
+#Group 37 pm_disp_held, Dispatch held conditions
+event:0X0250 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_THERMAL_GRP37 : (Group 37 pm_disp_held) DISP unit held due to thermal condition
+event:0X0251 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP37 : (Group 37 pm_disp_held) DISP unit held due to Power Management
+event:0X0252 counters:2 um:zero minimum:1000 name:PM_THERMAL_MAX_GRP37 : (Group 37 pm_disp_held) Processor in thermal MAX
+event:0X0253 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_SMT_GRP37 : (Group 37 pm_disp_held) DISP unit held due to SMT conflicts
+
+#Group 38 pm_disp_held2, Dispatch held conditions
+event:0X0260 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_GPR_GRP38 : (Group 38 pm_disp_held2) DISP unit held due to GPR dependencies
+event:0X0261 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_GRP38 : (Group 38 pm_disp_held2) DISP unit held
+event:0X0262 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_CW_GRP38 : (Group 38 pm_disp_held2) DISP unit held due to cache writes
+event:0X0263 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_FPQ_GRP38 : (Group 38 pm_disp_held2) DISP unit held due to FPU issue queue full
+
+#Group 39 pm_disp_held3, Dispatch held conditions
+event:0X0270 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_XER_GRP39 : (Group 39 pm_disp_held3) DISP unit held due to XER dependency
+event:0X0271 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_ISYNC_GRP39 : (Group 39 pm_disp_held3) DISP unit held due to ISYNC
+event:0X0272 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_STCX_CR_GRP39 : (Group 39 pm_disp_held3) DISP unit held due to STCX updating CR
+event:0X0273 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_RU_WQ_GRP39 : (Group 39 pm_disp_held3) DISP unit held due to RU FXU write queue full
+
+#Group 40 pm_disp_held4, Dispatch held conditions
+event:0X0280 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_FPU_CR_GRP40 : (Group 40 pm_disp_held4) DISP unit held due to FPU updating CR
+event:0X0281 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_LSU_GRP40 : (Group 40 pm_disp_held4) DISP unit held due to LSU move or invalidate SLB and SR
+event:0X0282 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_ITLB_ISLB_GRP40 : (Group 40 pm_disp_held4) DISP unit held due to SLB or TLB invalidates
+event:0X0283 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_FXU_MULTI_GRP40 : (Group 40 pm_disp_held4) DISP unit held due to FXU multicycle
+
+#Group 41 pm_disp_held5, Dispatch held conditions
+event:0X0290 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_FP_FX_MULT_GRP41 : (Group 41 pm_disp_held5) DISP unit held due to non fixed multiple/divide after fixed multiply/divide
+event:0X0291 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_MULT_GPR_GRP41 : (Group 41 pm_disp_held5) DISP unit held due to multiple/divide multiply/divide GPR dependencies
+event:0X0292 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_COMPLETION_GRP41 : (Group 41 pm_disp_held5) DISP unit held due to completion holding dispatch
+event:0X0293 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_GPR_GRP41 : (Group 41 pm_disp_held5) DISP unit held due to GPR dependencies
+
+#Group 42 pm_disp_held6, Dispatch held conditions
+event:0X02A0 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_INT_GRP42 : (Group 42 pm_disp_held6) DISP unit held due to exception
+event:0X02A1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_XTHRD_GRP42 : (Group 42 pm_disp_held6) DISP unit held due to cross thread resource conflicts
+event:0X02A2 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_LLA_END_GRP42 : (Group 42 pm_disp_held6) DISP unit held due to load look ahead ended
+event:0X02A3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_RESTART_GRP42 : (Group 42 pm_disp_held6) DISP unit held after restart coming
+
+#Group 43 pm_disp_held7, Dispatch held conditions
+event:0X02B0 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_FXU_SOPS_GRP43 : (Group 43 pm_disp_held7) DISP unit held due to FXU slow ops (mtmsr, scv, rfscv)
+event:0X02B1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_THRD_PRIO_GRP43 : (Group 43 pm_disp_held7) DISP unit held due to lower priority thread
+event:0X02B2 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_SPR_GRP43 : (Group 43 pm_disp_held7) DISP unit held due to MTSPR/MFSPR
+event:0X02B3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_CR_LOGICAL_GRP43 : (Group 43 pm_disp_held7) DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR
+
+#Group 44 pm_disp_held8, Dispatch held conditions
+event:0X02C0 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_ISYNC_GRP44 : (Group 44 pm_disp_held8) DISP unit held due to ISYNC
+event:0X02C1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_STCX_CR_GRP44 : (Group 44 pm_disp_held8) DISP unit held due to STCX updating CR
+event:0X02C2 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_RU_WQ_GRP44 : (Group 44 pm_disp_held8) DISP unit held due to RU FXU write queue full
+event:0X02C3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_FPU_CR_GRP44 : (Group 44 pm_disp_held8) DISP unit held due to FPU updating CR
+
+#Group 45 pm_disp_held9, Dispatch held conditions
+event:0X02D0 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_ISYNC_GRP45 : (Group 45 pm_disp_held9) DISP unit held due to ISYNC
+event:0X02D1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_FPU_CR_GRP45 : (Group 45 pm_disp_held9) DISP unit held due to FPU updating CR
+event:0X02D2 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_MULT_GPR_GRP45 : (Group 45 pm_disp_held9) DISP unit held due to multiple/divide multiply/divide GPR dependencies
+event:0X02D3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_COMPLETION_GRP45 : (Group 45 pm_disp_held9) DISP unit held due to completion holding dispatch
+
+#Group 46 pm_sync, Sync events
+event:0X02E0 counters:0 um:zero minimum:1000 name:PM_LWSYNC_GRP46 : (Group 46 pm_sync) Isync instruction completed
+event:0X02E1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP46 : (Group 46 pm_sync) Processor cycles
+event:0X02E2 counters:2 um:zero minimum:1000 name:PM_SYNC_CYC_GRP46 : (Group 46 pm_sync) Sync duration
+event:0X02E3 counters:3 um:zero minimum:1000 name:PM_DPU_HELD_LSU_SOPS_GRP46 : (Group 46 pm_sync) DISP unit held due to LSU slow ops (sync, tlbie, stcx)
+
+#Group 47 pm_L1_ref, L1 references
+event:0X02F0 counters:0 um:zero minimum:1000 name:PM_LD_REF_L1_BOTH_GRP47 : (Group 47 pm_L1_ref) Both units L1 D cache load reference
+event:0X02F1 counters:1 um:zero minimum:1000 name:PM_LD_REF_L1_GRP47 : (Group 47 pm_L1_ref) L1 D cache load references
+event:0X02F2 counters:2 um:zero minimum:1000 name:PM_ST_REF_L1_GRP47 : (Group 47 pm_L1_ref) L1 D cache store references
+event:0X02F3 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_BOTH_GRP47 : (Group 47 pm_L1_ref) Both units L1 D cache store reference
+
+#Group 48 pm_L1_ldst, L1 load/store ref/miss
+event:0X0300 counters:0 um:zero minimum:1000 name:PM_ST_REF_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache store references
+event:0X0301 counters:1 um:zero minimum:1000 name:PM_LD_REF_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache load references
+event:0X0302 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache store misses
+event:0X0303 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP48 : (Group 48 pm_L1_ldst) L1 D cache load misses
+
+#Group 49 pm_streams, Streams
+event:0X0310 counters:0 um:zero minimum:1000 name:PM_DC_PREF_OUT_OF_STREAMS_GRP49 : (Group 49 pm_streams) D cache out of streams
+event:0X0311 counters:1 um:zero minimum:1000 name:PM_DC_PREF_STREAM_ALLOC_GRP49 : (Group 49 pm_streams) D cache new prefetch stream allocated
+event:0X0312 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP49 : (Group 49 pm_streams) L1 cache data prefetches
+event:0X0313 counters:3 um:zero minimum:1000 name:PM_IBUF_FULL_CYC_GRP49 : (Group 49 pm_streams) Cycles instruction buffer full
+
+#Group 50 pm_flush, Flushes
+event:0X0320 counters:0 um:zero minimum:1000 name:PM_FLUSH_GRP50 : (Group 50 pm_flush) Flushes
+event:0X0321 counters:1 um:zero minimum:1000 name:PM_FLUSH_ASYNC_GRP50 : (Group 50 pm_flush) Flush caused by asynchronous exception
+event:0X0322 counters:2 um:zero minimum:1000 name:PM_FLUSH_FPU_GRP50 : (Group 50 pm_flush) Flush caused by FPU exception
+event:0X0323 counters:3 um:zero minimum:1000 name:PM_FLUSH_FXU_GRP50 : (Group 50 pm_flush) Flush caused by FXU exception
+
+#Group 51 pm_prefetch, I cache Prefetches
+event:0X0330 counters:0 um:zero minimum:1000 name:PM_IC_REQ_GRP51 : (Group 51 pm_prefetch) I cache demand of prefetch request
+event:0X0331 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP51 : (Group 51 pm_prefetch) Instruction prefetch requests
+event:0X0332 counters:2 um:zero minimum:1000 name:PM_IC_RELOAD_SHR_GRP51 : (Group 51 pm_prefetch) I cache line reloading to be shared by threads
+event:0X0333 counters:3 um:zero minimum:1000 name:PM_IC_PREF_WRITE_GRP51 : (Group 51 pm_prefetch) Instruction prefetch written into I cache
+
+#Group 52 pm_stcx, STCX
+event:0X0340 counters:0 um:zero minimum:1000 name:PM_STCX_GRP52 : (Group 52 pm_stcx) STCX executed
+event:0X0341 counters:1 um:zero minimum:1000 name:PM_STCX_CANCEL_GRP52 : (Group 52 pm_stcx) stcx cancel by core
+event:0X0342 counters:2 um:zero minimum:1000 name:PM_STCX_FAIL_GRP52 : (Group 52 pm_stcx) STCX failed
+event:0X0343 counters:3 um:zero minimum:1000 name:PM_LARX_GRP52 : (Group 52 pm_stcx) Larx executed
+
+#Group 53 pm_larx, LARX
+event:0X0350 counters:0 um:zero minimum:1000 name:PM_LARX_GRP53 : (Group 53 pm_larx) Larx executed
+event:0X0351 counters:1 um:zero minimum:1000 name:PM_LARX_L1HIT_GRP53 : (Group 53 pm_larx) larx hits in L1
+event:0X0352 counters:2 um:zero minimum:1000 name:PM_STCX_GRP53 : (Group 53 pm_larx) STCX executed
+event:0X0353 counters:3 um:zero minimum:1000 name:PM_STCX_FAIL_GRP53 : (Group 53 pm_larx) STCX failed
+
+#Group 54 pm_thread_cyc, Thread cycles
+event:0X0360 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP54 : (Group 54 pm_thread_cyc) One of the threads in run cycles
+event:0X0361 counters:1 um:zero minimum:1000 name:PM_THRD_GRP_CMPL_BOTH_CYC_GRP54 : (Group 54 pm_thread_cyc) Cycles group completed by both threads
+event:0X0362 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP54 : (Group 54 pm_thread_cyc) Concurrent run instructions
+event:0X0363 counters:3 um:zero minimum:1000 name:PM_THRD_BOTH_RUN_CYC_GRP54 : (Group 54 pm_thread_cyc) Both threads in run cycles
+
+#Group 55 pm_misc, Misc
+event:0X0370 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP55 : (Group 55 pm_misc) One or more PPC instruction completed
+event:0X0371 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP55 : (Group 55 pm_misc) Hypervisor Cycles
+event:0X0372 counters:2 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP55 : (Group 55 pm_misc) Threshold timeout
+event:0X0373 counters:3 um:zero minimum:1000 name:PM_THRD_LLA_BOTH_CYC_GRP55 : (Group 55 pm_misc) Both threads in Load Look Ahead
+
+#Group 56 pm_misc2, Misc
+event:0X0380 counters:0 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP56 : (Group 56 pm_misc2) Cycles MSR(EE) bit off and external interrupt pending
+event:0X0381 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP56 : (Group 56 pm_misc2) External interrupts
+event:0X0382 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP56 : (Group 56 pm_misc2) Time Base bit transition
+event:0X0383 counters:3 um:zero minimum:1000 name:PM_0INST_FETCH_GRP56 : (Group 56 pm_misc2) No instructions fetched
+
+#Group 57 pm_misc3, Misc
+event:0X0390 counters:0 um:zero minimum:1000 name:PM_ST_FIN_GRP57 : (Group 57 pm_misc3) Store instructions finished
+event:0X0391 counters:1 um:zero minimum:1000 name:PM_THRD_L2MISS_GRP57 : (Group 57 pm_misc3) Thread in L2 miss
+event:0X0392 counters:2 um:zero minimum:10000 name:PM_CYC_GRP57 : (Group 57 pm_misc3) Processor cycles
+event:0X0393 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP57 : (Group 57 pm_misc3) Instructions completed
+
+#Group 58 pm_tlb_slb, TLB and SLB events
+event:0X03A0 counters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP58 : (Group 58 pm_tlb_slb) Instruction SLB misses
+event:0X03A1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP58 : (Group 58 pm_tlb_slb) Data SLB misses
+event:0X03A2 counters:2 um:zero minimum:1000 name:PM_TLB_REF_GRP58 : (Group 58 pm_tlb_slb) TLB reference
+event:0X03A3 counters:3 um:zero minimum:1000 name:PM_ITLB_REF_GRP58 : (Group 58 pm_tlb_slb) Instruction TLB reference
+
+#Group 59 pm_slb_miss, SLB Misses
+event:0X03B0 counters:0 um:zero minimum:1000 name:PM_ISLB_MISS_GRP59 : (Group 59 pm_slb_miss) Instruction SLB misses
+event:0X03B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP59 : (Group 59 pm_slb_miss) Data SLB misses
+event:0X03B2 counters:2 um:zero minimum:1000 name:PM_IERAT_MISS_GRP59 : (Group 59 pm_slb_miss) IERAT miss count
+event:0X03B3 counters:3 um:zero minimum:1000 name:PM_SLB_MISS_GRP59 : (Group 59 pm_slb_miss) SLB misses
+
+#Group 60 pm_rejects, Reject events
+event:0X03C0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_L2_CORR_GRP60 : (Group 60 pm_rejects) LSU reject due to L2 correctable error
+event:0X03C1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_DERAT_MPRED_GRP60 : (Group 60 pm_rejects) LSU reject due to mispredicted DERAT
+event:0X03C2 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_FAST_GRP60 : (Group 60 pm_rejects) LSU fast reject
+event:0X03C3 counters:3 um:zero minimum:1000 name:PM_LSU_REJECT_GRP60 : (Group 60 pm_rejects) LSU reject
+
+#Group 61 pm_rejects2, Reject events
+event:0X03D0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_LHS_GRP61 : (Group 61 pm_rejects2) Load hit store reject
+event:0X03D1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_LHS_BOTH_GRP61 : (Group 61 pm_rejects2) Load hit store reject both units
+event:0X03D2 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_EXTERN_GRP61 : (Group 61 pm_rejects2) LSU external reject request
+event:0X03D3 counters:3 um:zero minimum:1000 name:PM_LSU_REJECT_STEAL_GRP61 : (Group 61 pm_rejects2) LSU reject due to steal
+
+#Group 62 pm_rejects3, Reject events
+event:0X03E0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_STQ_FULL_GRP62 : (Group 62 pm_rejects3) LSU reject due to store queue full
+event:0X03E1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_SLOW_GRP62 : (Group 62 pm_rejects3) LSU slow reject
+event:0X03E2 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_NO_SCRATCH_GRP62 : (Group 62 pm_rejects3) LSU reject due to scratch register not available
+event:0X03E3 counters:3 um:zero minimum:1000 name:PM_LSU_REJECT_PARTIAL_SECTOR_GRP62 : (Group 62 pm_rejects3) LSU reject due to partial sector valid
+
+#Group 63 pm_rejects4, Unaligned store rejects
+event:0X03F0 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_UST_BOTH_GRP63 : (Group 63 pm_rejects4) Unaligned store reject both units
+event:0X03F1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_UST_GRP63 : (Group 63 pm_rejects4) Unaligned store reject
+event:0X03F2 counters:2 um:zero minimum:1000 name:PM_LSU0_REJECT_UST_GRP63 : (Group 63 pm_rejects4) LSU0 unaligned store reject
+event:0X03F3 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_UST_GRP63 : (Group 63 pm_rejects4) LSU1 unaligned store reject
+
+#Group 64 pm_rejects5, Unaligned load rejects
+event:0X0400 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_ULD_GRP64 : (Group 64 pm_rejects5) Unaligned load reject
+event:0X0401 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_ULD_BOTH_GRP64 : (Group 64 pm_rejects5) Unaligned load reject both units
+event:0X0402 counters:2 um:zero minimum:1000 name:PM_LSU0_REJECT_ULD_GRP64 : (Group 64 pm_rejects5) LSU0 unaligned load reject
+event:0X0403 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_ULD_GRP64 : (Group 64 pm_rejects5) LSU1 unaligned load reject
+
+#Group 65 pm_rejects6, Set mispredictions rejects
+event:0X0410 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_SET_MPRED_GRP65 : (Group 65 pm_rejects6) LSU0 reject due to mispredicted set
+event:0X0411 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_SET_MPRED_GRP65 : (Group 65 pm_rejects6) LSU1 reject due to mispredicted set
+event:0X0412 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_SET_MPRED_GRP65 : (Group 65 pm_rejects6) LSU reject due to mispredicted set
+event:0X0413 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP65 : (Group 65 pm_rejects6) Cycles SRQ empty
+
+#Group 66 pm_rejects_unit, Unaligned reject events by unit
+event:0X0420 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_ULD_GRP66 : (Group 66 pm_rejects_unit) LSU0 unaligned load reject
+event:0X0421 counters:1 um:zero minimum:1000 name:PM_LSU1_REJECT_UST_GRP66 : (Group 66 pm_rejects_unit) LSU1 unaligned store reject
+event:0X0422 counters:2 um:zero minimum:1000 name:PM_LSU0_REJECT_UST_GRP66 : (Group 66 pm_rejects_unit) LSU0 unaligned store reject
+event:0X0423 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_ULD_GRP66 : (Group 66 pm_rejects_unit) LSU1 unaligned load reject
+
+#Group 67 pm_rejects_unit2, Reject events by unit
+event:0X0430 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_GRP67 : (Group 67 pm_rejects_unit2) LSU0 reject
+event:0X0431 counters:1 um:zero minimum:1000 name:PM_LSU0_REJECT_DERAT_MPRED_GRP67 : (Group 67 pm_rejects_unit2) LSU0 reject due to mispredicted DERAT
+event:0X0432 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_GRP67 : (Group 67 pm_rejects_unit2) LSU1 reject
+event:0X0433 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_NO_SCRATCH_GRP67 : (Group 67 pm_rejects_unit2) LSU1 reject due to scratch register not available
+
+#Group 68 pm_rejects_unit3, Reject events by unit
+event:0X0440 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_EXTERN_GRP68 : (Group 68 pm_rejects_unit3) LSU0 external reject request
+event:0X0441 counters:1 um:zero minimum:1000 name:PM_LSU0_REJECT_L2_CORR_GRP68 : (Group 68 pm_rejects_unit3) LSU0 reject due to L2 correctable error
+event:0X0442 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_EXTERN_GRP68 : (Group 68 pm_rejects_unit3) LSU1 external reject request
+event:0X0443 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_L2_CORR_GRP68 : (Group 68 pm_rejects_unit3) LSU1 reject due to L2 correctable error
+
+#Group 69 pm_rejects_unit4, Reject events by unit
+event:0X0450 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_NO_SCRATCH_GRP69 : (Group 69 pm_rejects_unit4) LSU0 reject due to scratch register not available
+event:0X0451 counters:1 um:zero minimum:1000 name:PM_LSU0_REJECT_PARTIAL_SECTOR_GRP69 : (Group 69 pm_rejects_unit4) LSU0 reject due to partial sector valid
+event:0X0452 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_NO_SCRATCH_GRP69 : (Group 69 pm_rejects_unit4) LSU1 reject due to scratch register not available
+event:0X0453 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_PARTIAL_SECTOR_GRP69 : (Group 69 pm_rejects_unit4) LSU1 reject due to partial sector valid
+
+#Group 70 pm_rejects_unit5, Reject events by unit
+event:0X0460 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_LHS_GRP70 : (Group 70 pm_rejects_unit5) LSU0 load hit store reject
+event:0X0461 counters:1 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP70 : (Group 70 pm_rejects_unit5) LSU0 DERAT misses
+event:0X0462 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_LHS_GRP70 : (Group 70 pm_rejects_unit5) LSU1 load hit store reject
+event:0X0463 counters:3 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP70 : (Group 70 pm_rejects_unit5) LSU1 DERAT misses
+
+#Group 71 pm_rejects_unit6, Reject events by unit
+event:0X0470 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_STQ_FULL_GRP71 : (Group 71 pm_rejects_unit6) LSU0 reject due to store queue full
+event:0X0471 counters:1 um:zero minimum:1000 name:PM_LSU0_REJECT_GRP71 : (Group 71 pm_rejects_unit6) LSU0 reject
+event:0X0472 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_STQ_FULL_GRP71 : (Group 71 pm_rejects_unit6) LSU1 reject due to store queue full
+event:0X0473 counters:3 um:zero minimum:1000 name:PM_LSU1_REJECT_GRP71 : (Group 71 pm_rejects_unit6) LSU1 reject
+
+#Group 72 pm_rejects_unit7, Reject events by unit
+event:0X0480 counters:0 um:zero minimum:1000 name:PM_LSU0_REJECT_DERAT_MPRED_GRP72 : (Group 72 pm_rejects_unit7) LSU0 reject due to mispredicted DERAT
+event:0X0481 counters:1 um:zero minimum:1000 name:PM_LSU0_DERAT_MISS_GRP72 : (Group 72 pm_rejects_unit7) LSU0 DERAT misses
+event:0X0482 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_DERAT_MPRED_GRP72 : (Group 72 pm_rejects_unit7) LSU1 reject due to mispredicted DERAT
+event:0X0483 counters:3 um:zero minimum:1000 name:PM_LSU1_DERAT_MISS_GRP72 : (Group 72 pm_rejects_unit7) LSU1 DERAT misses
+
+#Group 73 pm_ldf, Floating Point loads
+event:0X0490 counters:0 um:zero minimum:1000 name:PM_LSU_LDF_BOTH_GRP73 : (Group 73 pm_ldf) Both LSU units executed Floating Point load instruction
+event:0X0491 counters:1 um:zero minimum:1000 name:PM_LSU_LDF_GRP73 : (Group 73 pm_ldf) LSU executed Floating Point load instruction
+event:0X0492 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP73 : (Group 73 pm_ldf) LSU0 executed Floating Point load instruction
+event:0X0493 counters:3 um:zero minimum:1000 name:PM_LSU1_LDF_GRP73 : (Group 73 pm_ldf) LSU1 executed Floating Point load instruction
+
+#Group 74 pm_lsu_misc, LSU events
+event:0X04A0 counters:0 um:zero minimum:1000 name:PM_LSU0_NCLD_GRP74 : (Group 74 pm_lsu_misc) LSU0 non-cacheable loads
+event:0X04A1 counters:1 um:zero minimum:1000 name:PM_LSU0_NCST_GRP74 : (Group 74 pm_lsu_misc) LSU0 non-cachable stores
+event:0X04A2 counters:2 um:zero minimum:1000 name:PM_LSU_ST_CHAINED_GRP74 : (Group 74 pm_lsu_misc) number of chained stores
+event:0X04A3 counters:3 um:zero minimum:1000 name:PM_LSU_BOTH_BUS_GRP74 : (Group 74 pm_lsu_misc) Both data return buses busy simultaneously
+
+#Group 75 pm_lsu_lmq, LSU LMQ events
+event:0X04B0 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP75 : (Group 75 pm_lsu_lmq) Cycles LMQ full
+event:0X04B1 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP75 : (Group 75 pm_lsu_lmq) Cycles LMQ and SRQ empty
+event:0X04B2 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC_GRP75 : (Group 75 pm_lsu_lmq) Cycles both threads LMQ and SRQ empty
+event:0X04B3 counters:3 um:zero minimum:1000 name:PM_LSU0_REJECT_L2MISS_GRP75 : (Group 75 pm_lsu_lmq) LSU0 L2 miss reject
+
+#Group 76 pm_lsu_flush_derat_miss, LSU flush and DERAT misses
+event:0X04C0 counters:0 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_CYC_GRP76 : (Group 76 pm_lsu_flush_derat_miss) DERAT miss latency
+event:0X04C1 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP76 : (Group 76 pm_lsu_flush_derat_miss) DERAT misses
+event:0X04C2 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_ALIGN_GRP76 : (Group 76 pm_lsu_flush_derat_miss) Flush caused by alignement exception
+event:0X04C3 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_DSI_GRP76 : (Group 76 pm_lsu_flush_derat_miss) Flush caused by DSI
+
+#Group 77 pm_lla, Look Load Ahead events
+event:0X04D0 counters:0 um:zero minimum:1000 name:PM_INST_DISP_LLA_GRP77 : (Group 77 pm_lla) Instruction dispatched under load look ahead
+event:0X04D1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_LLA_END_GRP77 : (Group 77 pm_lla) DISP unit held due to load look ahead ended
+event:0X04D2 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP77 : (Group 77 pm_lla) Instructions dispatched
+event:0X04D3 counters:3 um:zero minimum:1000 name:PM_THRD_LLA_BOTH_CYC_GRP77 : (Group 77 pm_lla) Both threads in Load Look Ahead
+
+#Group 78 pm_gct, GCT events
+event:0X04E0 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP78 : (Group 78 pm_gct) Cycles no GCT slot allocated
+event:0X04E1 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP78 : (Group 78 pm_gct) Cycles GCT empty
+event:0X04E2 counters:2 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP78 : (Group 78 pm_gct) Cycles GCT full
+event:0X04E3 counters:3 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP78 : (Group 78 pm_gct) Cycles at least 1 instruction fetched
+
+#Group 79 pm_smt_priorities, Thread priority events
+event:0X04F0 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_0_CYC_GRP79 : (Group 79 pm_smt_priorities) Cycles thread running at priority level 0
+event:0X04F1 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_1_CYC_GRP79 : (Group 79 pm_smt_priorities) Cycles thread running at priority level 1
+event:0X04F2 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_2_CYC_GRP79 : (Group 79 pm_smt_priorities) Cycles thread running at priority level 2
+event:0X04F3 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_3_CYC_GRP79 : (Group 79 pm_smt_priorities) Cycles thread running at priority level 3
+
+#Group 80 pm_smt_priorities2, Thread priority events
+event:0X0500 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_7_CYC_GRP80 : (Group 80 pm_smt_priorities2) Cycles thread running at priority level 7
+event:0X0501 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_6_CYC_GRP80 : (Group 80 pm_smt_priorities2) Cycles thread running at priority level 6
+event:0X0502 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_5_CYC_GRP80 : (Group 80 pm_smt_priorities2) Cycles thread running at priority level 5
+event:0X0503 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_4_CYC_GRP80 : (Group 80 pm_smt_priorities2) Cycles thread running at priority level 4
+
+#Group 81 pm_smt_priorities3, Thread priority differences events
+event:0X0510 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_0_CYC_GRP81 : (Group 81 pm_smt_priorities3) Cycles no thread priority difference
+event:0X0511 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_1or2_CYC_GRP81 : (Group 81 pm_smt_priorities3) Cycles thread priority difference is 1 or 2
+event:0X0512 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_3or4_CYC_GRP81 : (Group 81 pm_smt_priorities3) Cycles thread priority difference is 3 or 4
+event:0X0513 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_5or6_CYC_GRP81 : (Group 81 pm_smt_priorities3) Cycles thread priority difference is 5 or 6
+
+#Group 82 pm_smt_priorities4, Thread priority differences events
+event:0X0520 counters:0 um:zero minimum:1000 name:PM_THRD_SEL_T0_GRP82 : (Group 82 pm_smt_priorities4) Decode selected thread 0
+event:0X0521 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP82 : (Group 82 pm_smt_priorities4) Cycles thread priority difference is -1 or -2
+event:0X0522 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP82 : (Group 82 pm_smt_priorities4) Cycles thread priority difference is -3 or -4
+event:0X0523 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP82 : (Group 82 pm_smt_priorities4) Cycles thread priority difference is -5 or -6
+
+#Group 83 pm_fxu, FXU events
+event:0X0530 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP83 : (Group 83 pm_fxu) FXU idle
+event:0X0531 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP83 : (Group 83 pm_fxu) FXU busy
+event:0X0532 counters:2 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP83 : (Group 83 pm_fxu) FXU0 busy FXU1 idle
+event:0X0533 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP83 : (Group 83 pm_fxu) FXU1 busy FXU0 idle
+
+#Group 84 pm_fxu2, FXU events
+event:0X0540 counters:0 um:zero minimum:1000 name:PM_FXU_PIPELINED_MULT_DIV_GRP84 : (Group 84 pm_fxu2) Fix point multiply/divide pipelined
+event:0X0541 counters:1 um:zero minimum:1000 name:PM_IFU_FIN_GRP84 : (Group 84 pm_fxu2) IFU finished an instruction
+event:0X0542 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP84 : (Group 84 pm_fxu2) FXU0 produced a result
+event:0X0543 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP84 : (Group 84 pm_fxu2) FXU1 produced a result
+
+#Group 85 pm_vmx, VMX events
+event:0X0550 counters:0 um:zero minimum:1000 name:PM_VMX_COMPLEX_ISUED_GRP85 : (Group 85 pm_vmx) VMX instruction issued to complex
+event:0X0551 counters:1 um:zero minimum:1000 name:PM_VMX_FLOAT_ISSUED_GRP85 : (Group 85 pm_vmx) VMX instruction issued to float
+event:0X0552 counters:2 um:zero minimum:1000 name:PM_VMX_SIMPLE_ISSUED_GRP85 : (Group 85 pm_vmx) VMX instruction issued to simple
+event:0X0553 counters:3 um:zero minimum:1000 name:PM_VMX_PERMUTE_ISSUED_GRP85 : (Group 85 pm_vmx) VMX instruction issued to permute
+
+#Group 86 pm_vmx2, VMX events
+event:0X0560 counters:0 um:zero minimum:1000 name:PM_VMX0_INST_ISSUED_GRP86 : (Group 86 pm_vmx2) VMX0 instruction issued
+event:0X0561 counters:1 um:zero minimum:1000 name:PM_VMX1_INST_ISSUED_GRP86 : (Group 86 pm_vmx2) VMX1 instruction issued
+event:0X0562 counters:2 um:zero minimum:1000 name:PM_VMX0_LD_ISSUED_GRP86 : (Group 86 pm_vmx2) VMX0 load issued
+event:0X0563 counters:3 um:zero minimum:1000 name:PM_VMX1_LD_ISSUED_GRP86 : (Group 86 pm_vmx2) VMX1 load issued
+
+#Group 87 pm_vmx3, VMX events
+event:0X0570 counters:0 um:zero minimum:1000 name:PM_VMX0_LD_ISSUED_GRP87 : (Group 87 pm_vmx3) VMX0 load issued
+event:0X0571 counters:1 um:zero minimum:1000 name:PM_VMX0_LD_WRBACK_GRP87 : (Group 87 pm_vmx3) VMX0 load writeback valid
+event:0X0572 counters:2 um:zero minimum:1000 name:PM_VMX1_LD_ISSUED_GRP87 : (Group 87 pm_vmx3) VMX1 load issued
+event:0X0573 counters:3 um:zero minimum:1000 name:PM_VMX1_LD_WRBACK_GRP87 : (Group 87 pm_vmx3) VMX1 load writeback valid
+
+#Group 88 pm_vmx4, VMX events
+event:0X0580 counters:0 um:zero minimum:1000 name:PM_VMX_FLOAT_MULTICYCLE_GRP88 : (Group 88 pm_vmx4) VMX multi-cycle floating point instruction issued
+event:0X0581 counters:1 um:zero minimum:1000 name:PM_VMX_RESULT_SAT_0_1_GRP88 : (Group 88 pm_vmx4) VMX valid result with sat bit is set (0->1)
+event:0X0582 counters:2 um:zero minimum:1000 name:PM_VMX_RESULT_SAT_1_GRP88 : (Group 88 pm_vmx4) VMX valid result with sat=1
+event:0X0583 counters:3 um:zero minimum:1000 name:PM_VMX_ST_ISSUED_GRP88 : (Group 88 pm_vmx4) VMX store issued
+
+#Group 89 pm_vmx5, VMX events
+event:0X0590 counters:0 um:zero minimum:1000 name:PM_VMX_ST_ISSUED_GRP89 : (Group 89 pm_vmx5) VMX store issued
+event:0X0591 counters:1 um:zero minimum:1000 name:PM_VMX0_STALL_GRP89 : (Group 89 pm_vmx5) VMX0 stall
+event:0X0592 counters:2 um:zero minimum:1000 name:PM_VMX1_STALL_GRP89 : (Group 89 pm_vmx5) VMX1 stall
+event:0X0593 counters:3 um:zero minimum:1000 name:PM_VMX_FLOAT_MULTICYCLE_GRP89 : (Group 89 pm_vmx5) VMX multi-cycle floating point instruction issued
+
+#Group 90 pm_dfu, DFU events
+event:0X05A0 counters:0 um:zero minimum:1000 name:PM_DFU_ADD_GRP90 : (Group 90 pm_dfu) DFU add type instruction
+event:0X05A1 counters:1 um:zero minimum:1000 name:PM_DFU_ADD_SHIFTED_BOTH_GRP90 : (Group 90 pm_dfu) DFU add type with both operands shifted
+event:0X05A2 counters:2 um:zero minimum:1000 name:PM_DFU_BACK2BACK_GRP90 : (Group 90 pm_dfu) DFU back to back operations executed
+event:0X05A3 counters:3 um:zero minimum:1000 name:PM_DFU_CONV_GRP90 : (Group 90 pm_dfu) DFU convert from fixed op
+
+#Group 91 pm_dfu2, DFU events
+event:0X05B0 counters:0 um:zero minimum:1000 name:PM_DFU_ENC_BCD_DPD_GRP91 : (Group 91 pm_dfu2) DFU Encode BCD to DPD
+event:0X05B1 counters:1 um:zero minimum:1000 name:PM_DFU_EXP_EQ_GRP91 : (Group 91 pm_dfu2) DFU operand exponents are equal for add type
+event:0X05B2 counters:2 um:zero minimum:1000 name:PM_DFU_FIN_GRP91 : (Group 91 pm_dfu2) DFU instruction finish
+event:0X05B3 counters:3 um:zero minimum:1000 name:PM_DFU_SUBNORM_GRP91 : (Group 91 pm_dfu2) DFU result is a subnormal
+
+#Group 92 pm_fab, Fabric events
+event:0X05C0 counters:0 um:zero minimum:1000 name:PM_FAB_CMD_ISSUED_GRP92 : (Group 92 pm_fab) Fabric command issued
+event:0X05C1 counters:1 um:zero minimum:1000 name:PM_FAB_CMD_RETRIED_GRP92 : (Group 92 pm_fab) Fabric command retried
+event:0X05C2 counters:2 um:zero minimum:1000 name:PM_FAB_DCLAIM_GRP92 : (Group 92 pm_fab) Dclaim operation, locally mastered
+event:0X05C3 counters:3 um:zero minimum:1000 name:PM_FAB_DMA_GRP92 : (Group 92 pm_fab) DMA operation, locally mastered
+
+#Group 93 pm_fab2, Fabric events
+event:0X05D0 counters:0 um:zero minimum:1000 name:PM_FAB_NODE_PUMP_GRP93 : (Group 93 pm_fab2) Node pump operation, locally mastered
+event:0X05D1 counters:1 um:zero minimum:1000 name:PM_FAB_RETRY_NODE_PUMP_GRP93 : (Group 93 pm_fab2) Retry of a node pump, locally mastered
+event:0X05D2 counters:2 um:zero minimum:1000 name:PM_FAB_RETRY_SYS_PUMP_GRP93 : (Group 93 pm_fab2) Retry of a system pump, locally mastered
+event:0X05D3 counters:3 um:zero minimum:1000 name:PM_FAB_SYS_PUMP_GRP93 : (Group 93 pm_fab2) System pump operation, locally mastered
+
+#Group 94 pm_fab3, Fabric events
+event:0X05E0 counters:0 um:zero minimum:1000 name:PM_FAB_CMD_ISSUED_GRP94 : (Group 94 pm_fab3) Fabric command issued
+event:0X05E1 counters:1 um:zero minimum:1000 name:PM_FAB_CMD_RETRIED_GRP94 : (Group 94 pm_fab3) Fabric command retried
+event:0X05E2 counters:2 um:zero minimum:1000 name:PM_FAB_ADDR_COLLISION_GRP94 : (Group 94 pm_fab3) local node launch collision with off-node address
+event:0X05E3 counters:3 um:zero minimum:1000 name:PM_FAB_MMIO_GRP94 : (Group 94 pm_fab3) MMIO operation, locally mastered
+
+#Group 95 pm_mem_dblpump, Double pump
+event:0X05F0 counters:0 um:zero minimum:1000 name:PM_MEM_DP_RQ_GLOB_LOC_GRP95 : (Group 95 pm_mem_dblpump) Memory read queue marking cache line double pump state from global to local
+event:0X05F1 counters:1 um:zero minimum:1000 name:PM_MEM_DP_RQ_LOC_GLOB_GRP95 : (Group 95 pm_mem_dblpump) Memory read queue marking cache line double pump state from local to global
+event:0X05F2 counters:2 um:zero minimum:1000 name:PM_MEM_DP_CL_WR_GLOB_GRP95 : (Group 95 pm_mem_dblpump) cache line write setting double pump state to global
+event:0X05F3 counters:3 um:zero minimum:1000 name:PM_MEM_DP_CL_WR_LOC_GRP95 : (Group 95 pm_mem_dblpump) cache line write setting double pump state to local
+
+#Group 96 pm_mem0_dblpump, MCS0 Double pump
+event:0X0600 counters:0 um:zero minimum:1000 name:PM_MEM0_DP_RQ_GLOB_LOC_GRP96 : (Group 96 pm_mem0_dblpump) Memory read queue marking cache line double pump state from global to local side 0
+event:0X0601 counters:1 um:zero minimum:1000 name:PM_MEM0_DP_RQ_LOC_GLOB_GRP96 : (Group 96 pm_mem0_dblpump) Memory read queue marking cache line double pump state from local to global side 0
+event:0X0602 counters:2 um:zero minimum:1000 name:PM_MEM0_DP_CL_WR_GLOB_GRP96 : (Group 96 pm_mem0_dblpump) cacheline write setting dp to global side 0
+event:0X0603 counters:3 um:zero minimum:1000 name:PM_MEM0_DP_CL_WR_LOC_GRP96 : (Group 96 pm_mem0_dblpump) cacheline write setting dp to local side 0
+
+#Group 97 pm_mem1_dblpump, MCS1 Double pump
+event:0X0610 counters:0 um:zero minimum:1000 name:PM_MEM1_DP_RQ_GLOB_LOC_GRP97 : (Group 97 pm_mem1_dblpump) Memory read queue marking cache line double pump state from global to local side 1
+event:0X0611 counters:1 um:zero minimum:1000 name:PM_MEM1_DP_RQ_LOC_GLOB_GRP97 : (Group 97 pm_mem1_dblpump) Memory read queue marking cache line double pump state from local to global side 1
+event:0X0612 counters:2 um:zero minimum:1000 name:PM_MEM1_DP_CL_WR_GLOB_GRP97 : (Group 97 pm_mem1_dblpump) cacheline write setting dp to global side 1
+event:0X0613 counters:3 um:zero minimum:1000 name:PM_MEM1_DP_CL_WR_LOC_GRP97 : (Group 97 pm_mem1_dblpump) cacheline write setting dp to local side 1
+
+#Group 98 pm_gxo, GX outbound
+event:0X0620 counters:0 um:zero minimum:1000 name:PM_GXO_CYC_BUSY_GRP98 : (Group 98 pm_gxo) Outbound GX bus utilizations (# of cycles in use)
+event:0X0621 counters:1 um:zero minimum:1000 name:PM_GXO_ADDR_CYC_BUSY_GRP98 : (Group 98 pm_gxo) Outbound GX address utilization (# of cycles address out is valid)
+event:0X0622 counters:2 um:zero minimum:1000 name:PM_GXO_DATA_CYC_BUSY_GRP98 : (Group 98 pm_gxo) Outbound GX Data utilization (# of cycles data out is valid)
+event:0X0623 counters:3 um:zero minimum:1000 name:PM_GXI_CYC_BUSY_GRP98 : (Group 98 pm_gxo) Inbound GX bus utilizations (# of cycles in use)
+
+#Group 99 pm_gxi, GX inbound
+event:0X0630 counters:0 um:zero minimum:1000 name:PM_GXI_CYC_BUSY_GRP99 : (Group 99 pm_gxi) Inbound GX bus utilizations (# of cycles in use)
+event:0X0631 counters:1 um:zero minimum:1000 name:PM_GXI_ADDR_CYC_BUSY_GRP99 : (Group 99 pm_gxi) Inbound GX address utilization (# of cycle address is in valid)
+event:0X0632 counters:2 um:zero minimum:1000 name:PM_GXI_DATA_CYC_BUSY_GRP99 : (Group 99 pm_gxi) Inbound GX Data utilization (# of cycle data in is valid)
+event:0X0633 counters:3 um:zero minimum:1000 name:PM_GXO_CYC_BUSY_GRP99 : (Group 99 pm_gxi) Outbound GX bus utilizations (# of cycles in use)
+
+#Group 100 pm_gx_dma, DMA events
+event:0X0640 counters:0 um:zero minimum:1000 name:PM_GXO_CYC_BUSY_GRP100 : (Group 100 pm_gx_dma) Outbound GX bus utilizations (# of cycles in use)
+event:0X0641 counters:1 um:zero minimum:1000 name:PM_GXI_CYC_BUSY_GRP100 : (Group 100 pm_gx_dma) Inbound GX bus utilizations (# of cycles in use)
+event:0X0642 counters:2 um:zero minimum:1000 name:PM_GX_DMA_READ_GRP100 : (Group 100 pm_gx_dma) DMA Read Request
+event:0X0643 counters:3 um:zero minimum:1000 name:PM_GX_DMA_WRITE_GRP100 : (Group 100 pm_gx_dma) All DMA Write Requests (including dma wrt lgcy)
+
+#Group 101 pm_L1_misc, L1 misc events
+event:0X0650 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP101 : (Group 101 pm_L1_misc) Instruction fetched from L1
+event:0X0651 counters:1 um:zero minimum:1000 name:PM_L1_WRITE_CYC_GRP101 : (Group 101 pm_L1_misc) Cycles writing to instruction L1
+event:0X0652 counters:2 um:zero minimum:1000 name:PM_NO_ITAG_CYC_GRP101 : (Group 101 pm_L1_misc) Cyles no ITAG available
+event:0X0653 counters:3 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP101 : (Group 101 pm_L1_misc) IMC matched instructions completed
+
+#Group 102 pm_L2_data, L2 load and store data
+event:0X0660 counters:0 um:zero minimum:1000 name:PM_L2_LD_REQ_DATA_GRP102 : (Group 102 pm_L2_data) L2 data load requests
+event:0X0661 counters:1 um:zero minimum:1000 name:PM_L2_LD_MISS_DATA_GRP102 : (Group 102 pm_L2_data) L2 data load misses
+event:0X0662 counters:2 um:zero minimum:1000 name:PM_L2_ST_REQ_DATA_GRP102 : (Group 102 pm_L2_data) L2 data store requests
+event:0X0663 counters:3 um:zero minimum:1000 name:PM_L2_ST_MISS_DATA_GRP102 : (Group 102 pm_L2_data) L2 data store misses
+
+#Group 103 pm_L2_ld_inst, L2 Load instructions
+event:0X0670 counters:0 um:zero minimum:1000 name:PM_L2_LD_REQ_INST_GRP103 : (Group 103 pm_L2_ld_inst) L2 instruction load requests
+event:0X0671 counters:1 um:zero minimum:1000 name:PM_L2_LD_MISS_INST_GRP103 : (Group 103 pm_L2_ld_inst) L2 instruction load misses
+event:0X0672 counters:2 um:zero minimum:1000 name:PM_L2_MISS_GRP103 : (Group 103 pm_L2_ld_inst) L2 cache misses
+event:0X0673 counters:3 um:zero minimum:1000 name:PM_L2_PREF_LD_GRP103 : (Group 103 pm_L2_ld_inst) L2 cache prefetches
+
+#Group 104 pm_L2_castout_invalidate, L2 castout and invalidate events
+event:0X0680 counters:0 um:zero minimum:1000 name:PM_L2_CASTOUT_MOD_GRP104 : (Group 104 pm_L2_castout_invalidate) L2 castouts - Modified (M, Mu, Me)
+event:0X0681 counters:1 um:zero minimum:1000 name:PM_L2_CASTOUT_SHR_GRP104 : (Group 104 pm_L2_castout_invalidate) L2 castouts - Shared (T, Te, Si, S)
+event:0X0682 counters:2 um:zero minimum:1000 name:PM_IC_INV_L2_GRP104 : (Group 104 pm_L2_castout_invalidate) L1 I cache entries invalidated from L2
+event:0X0683 counters:3 um:zero minimum:1000 name:PM_DC_INV_L2_GRP104 : (Group 104 pm_L2_castout_invalidate) L1 D cache entries invalidated from L2
+
+#Group 105 pm_L2_ldst_reqhit, L2 load and store requests and hits
+event:0X0690 counters:0 um:zero minimum:1000 name:PM_LD_REQ_L2_GRP105 : (Group 105 pm_L2_ldst_reqhit) L2 load requests
+event:0X0691 counters:1 um:zero minimum:1000 name:PM_LD_HIT_L2_GRP105 : (Group 105 pm_L2_ldst_reqhit) L2 D cache load hits
+event:0X0692 counters:2 um:zero minimum:1000 name:PM_ST_REQ_L2_GRP105 : (Group 105 pm_L2_ldst_reqhit) L2 store requests
+event:0X0693 counters:3 um:zero minimum:1000 name:PM_ST_HIT_L2_GRP105 : (Group 105 pm_L2_ldst_reqhit) L2 D cache store hits
+
+#Group 106 pm_L2_ld_data_slice, L2 data loads by slice
+event:0X06A0 counters:0 um:zero minimum:1000 name:PM_L2SA_LD_REQ_DATA_GRP106 : (Group 106 pm_L2_ld_data_slice) L2 slice A data load requests
+event:0X06A1 counters:1 um:zero minimum:1000 name:PM_L2SA_LD_MISS_DATA_GRP106 : (Group 106 pm_L2_ld_data_slice) L2 slice A data load misses
+event:0X06A2 counters:2 um:zero minimum:1000 name:PM_L2SB_LD_REQ_DATA_GRP106 : (Group 106 pm_L2_ld_data_slice) L2 slice B data load requests
+event:0X06A3 counters:3 um:zero minimum:1000 name:PM_L2SB_LD_MISS_DATA_GRP106 : (Group 106 pm_L2_ld_data_slice) L2 slice B data load misses
+
+#Group 107 pm_L2_ld_inst_slice, L2 instruction loads by slice
+event:0X06B0 counters:0 um:zero minimum:1000 name:PM_L2SA_LD_REQ_INST_GRP107 : (Group 107 pm_L2_ld_inst_slice) L2 slice A instruction load requests
+event:0X06B1 counters:1 um:zero minimum:1000 name:PM_L2SA_LD_MISS_INST_GRP107 : (Group 107 pm_L2_ld_inst_slice) L2 slice A instruction load misses
+event:0X06B2 counters:2 um:zero minimum:1000 name:PM_L2SB_LD_REQ_INST_GRP107 : (Group 107 pm_L2_ld_inst_slice) L2 slice B instruction load requests
+event:0X06B3 counters:3 um:zero minimum:1000 name:PM_L2SB_LD_MISS_INST_GRP107 : (Group 107 pm_L2_ld_inst_slice) L2 slice B instruction load misses
+
+#Group 108 pm_L2_st_slice, L2 slice stores by slice
+event:0X06C0 counters:0 um:zero minimum:1000 name:PM_L2SA_ST_REQ_GRP108 : (Group 108 pm_L2_st_slice) L2 slice A store requests
+event:0X06C1 counters:1 um:zero minimum:1000 name:PM_L2SA_ST_MISS_GRP108 : (Group 108 pm_L2_st_slice) L2 slice A store misses
+event:0X06C2 counters:2 um:zero minimum:1000 name:PM_L2SB_ST_REQ_GRP108 : (Group 108 pm_L2_st_slice) L2 slice B store requests
+event:0X06C3 counters:3 um:zero minimum:1000 name:PM_L2SB_ST_MISS_GRP108 : (Group 108 pm_L2_st_slice) L2 slice B store misses
+
+#Group 109 pm_L2miss_slice, L2 misses by slice
+event:0X06D0 counters:0 um:zero minimum:1000 name:PM_L2SA_MISS_GRP109 : (Group 109 pm_L2miss_slice) L2 slice A misses
+event:0X06D1 counters:1 um:zero minimum:1000 name:PM_L2_MISS_GRP109 : (Group 109 pm_L2miss_slice) L2 cache misses
+event:0X06D2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP109 : (Group 109 pm_L2miss_slice) Data loaded missed L2
+event:0X06D3 counters:3 um:zero minimum:1000 name:PM_L2SB_MISS_GRP109 : (Group 109 pm_L2miss_slice) L2 slice B misses
+
+#Group 110 pm_L2_castout_slice, L2 castouts by slice
+event:0X06E0 counters:0 um:zero minimum:1000 name:PM_L2SA_CASTOUT_MOD_GRP110 : (Group 110 pm_L2_castout_slice) L2 slice A castouts - Modified
+event:0X06E1 counters:1 um:zero minimum:1000 name:PM_L2SA_CASTOUT_SHR_GRP110 : (Group 110 pm_L2_castout_slice) L2 slice A castouts - Shared
+event:0X06E2 counters:2 um:zero minimum:1000 name:PM_L2SB_CASTOUT_MOD_GRP110 : (Group 110 pm_L2_castout_slice) L2 slice B castouts - Modified
+event:0X06E3 counters:3 um:zero minimum:1000 name:PM_L2SB_CASTOUT_SHR_GRP110 : (Group 110 pm_L2_castout_slice) L2 slice B castouts - Shared
+
+#Group 111 pm_L2_invalidate_slice, L2 invalidate by slice
+event:0X06F0 counters:0 um:zero minimum:1000 name:PM_L2SA_IC_INV_GRP111 : (Group 111 pm_L2_invalidate_slice) L2 slice A I cache invalidate
+event:0X06F1 counters:1 um:zero minimum:1000 name:PM_L2SA_DC_INV_GRP111 : (Group 111 pm_L2_invalidate_slice) L2 slice A D cache invalidate
+event:0X06F2 counters:2 um:zero minimum:1000 name:PM_L2SB_IC_INV_GRP111 : (Group 111 pm_L2_invalidate_slice) L2 slice B I cache invalidate
+event:0X06F3 counters:3 um:zero minimum:1000 name:PM_L2SB_DC_INV_GRP111 : (Group 111 pm_L2_invalidate_slice) L2 slice B D cache invalidate
+
+#Group 112 pm_L2_ld_reqhit_slice, L2 load requests and hist by slice
+event:0X0700 counters:0 um:zero minimum:1000 name:PM_L2SA_LD_REQ_GRP112 : (Group 112 pm_L2_ld_reqhit_slice) L2 slice A load requests
+event:0X0701 counters:1 um:zero minimum:1000 name:PM_L2SA_LD_HIT_GRP112 : (Group 112 pm_L2_ld_reqhit_slice) L2 slice A load hits
+event:0X0702 counters:2 um:zero minimum:1000 name:PM_L2SB_LD_REQ_GRP112 : (Group 112 pm_L2_ld_reqhit_slice) L2 slice B load requests
+event:0X0703 counters:3 um:zero minimum:1000 name:PM_L2SB_LD_HIT_GRP112 : (Group 112 pm_L2_ld_reqhit_slice) L2 slice B load hits
+
+#Group 113 pm_L2_st_reqhit_slice, L2 store requests and hist by slice
+event:0X0710 counters:0 um:zero minimum:1000 name:PM_L2SA_ST_REQ_GRP113 : (Group 113 pm_L2_st_reqhit_slice) L2 slice A store requests
+event:0X0711 counters:1 um:zero minimum:1000 name:PM_L2SA_ST_HIT_GRP113 : (Group 113 pm_L2_st_reqhit_slice) L2 slice A store hits
+event:0X0712 counters:2 um:zero minimum:1000 name:PM_L2SB_ST_REQ_GRP113 : (Group 113 pm_L2_st_reqhit_slice) L2 slice B store requests
+event:0X0713 counters:3 um:zero minimum:1000 name:PM_L2SB_ST_HIT_GRP113 : (Group 113 pm_L2_st_reqhit_slice) L2 slice B store hits
+
+#Group 114 pm_L2_redir_pref, L2 redirect and prefetch
+event:0X0720 counters:0 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BHT_REDIRECT_GRP114 : (Group 114 pm_L2_redir_pref) L2 I cache demand request due to BHT redirect
+event:0X0721 counters:1 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_REDIRECT_GRP114 : (Group 114 pm_L2_redir_pref) L2 I cache demand request due to branch redirect
+event:0X0722 counters:2 um:zero minimum:1000 name:PM_L2_PREF_ST_GRP114 : (Group 114 pm_L2_redir_pref) L2 cache prefetches
+event:0X0723 counters:3 um:zero minimum:1000 name:PM_L2_PREF_LD_GRP114 : (Group 114 pm_L2_redir_pref) L2 cache prefetches
+
+#Group 115 pm_L3_SliceA, L3 slice A events
+event:0X0730 counters:0 um:zero minimum:1000 name:PM_L3SA_REF_GRP115 : (Group 115 pm_L3_SliceA) L3 slice A references
+event:0X0731 counters:1 um:zero minimum:1000 name:PM_L3SA_HIT_GRP115 : (Group 115 pm_L3_SliceA) L3 slice A hits
+event:0X0732 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP115 : (Group 115 pm_L3_SliceA) Data loaded from L3
+event:0X0733 counters:3 um:zero minimum:1000 name:PM_L3SA_MISS_GRP115 : (Group 115 pm_L3_SliceA) L3 slice A misses
+
+#Group 116 pm_L3_SliceB, L3 slice B events
+event:0X0740 counters:0 um:zero minimum:1000 name:PM_L3SB_REF_GRP116 : (Group 116 pm_L3_SliceB) L3 slice B references
+event:0X0741 counters:1 um:zero minimum:1000 name:PM_L3SB_HIT_GRP116 : (Group 116 pm_L3_SliceB) L3 slice B hits
+event:0X0742 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP116 : (Group 116 pm_L3_SliceB) Data loaded from L3
+event:0X0743 counters:3 um:zero minimum:1000 name:PM_L3SB_MISS_GRP116 : (Group 116 pm_L3_SliceB) L3 slice B misses
+
+#Group 117 pm_fpu_issue, FPU issue events
+event:0X0750 counters:0 um:zero minimum:1000 name:PM_FPU_ISSUE_0_GRP117 : (Group 117 pm_fpu_issue) FPU issue 0 per cycle
+event:0X0751 counters:1 um:zero minimum:1000 name:PM_FPU_ISSUE_1_GRP117 : (Group 117 pm_fpu_issue) FPU issue 1 per cycle
+event:0X0752 counters:2 um:zero minimum:1000 name:PM_FPU_ISSUE_2_GRP117 : (Group 117 pm_fpu_issue) FPU issue 2 per cycle
+event:0X0753 counters:3 um:zero minimum:1000 name:PM_FPU_ISSUE_STEERING_GRP117 : (Group 117 pm_fpu_issue) FPU issue steering
+
+#Group 118 pm_fpu_issue2, FPU issue events
+event:0X0760 counters:0 um:zero minimum:1000 name:PM_FPU_ISSUE_OOO_GRP118 : (Group 118 pm_fpu_issue2) FPU issue out-of-order
+event:0X0761 counters:1 um:zero minimum:1000 name:PM_FPU_ISSUE_ST_FOLDED_GRP118 : (Group 118 pm_fpu_issue2) FPU issue a folded store
+event:0X0762 counters:2 um:zero minimum:1000 name:PM_FPU_ISSUE_DIV_SQRT_OVERLAP_GRP118 : (Group 118 pm_fpu_issue2) FPU divide/sqrt overlapped with other divide/sqrt
+event:0X0763 counters:3 um:zero minimum:1000 name:PM_FPU_ISSUE_STALL_ST_GRP118 : (Group 118 pm_fpu_issue2) FPU issue stalled due to store
+
+#Group 119 pm_fpu_issue3, FPU issue events
+event:0X0770 counters:0 um:zero minimum:1000 name:PM_FPU_ISSUE_STALL_THRD_GRP119 : (Group 119 pm_fpu_issue3) FPU issue stalled due to thread resource conflict
+event:0X0771 counters:1 um:zero minimum:1000 name:PM_FPU_ISSUE_STALL_FPR_GRP119 : (Group 119 pm_fpu_issue3) FPU issue stalled due to FPR dependencies
+event:0X0772 counters:2 um:zero minimum:1000 name:PM_FPU_ISSUE_DIV_SQRT_OVERLAP_GRP119 : (Group 119 pm_fpu_issue3) FPU divide/sqrt overlapped with other divide/sqrt
+event:0X0773 counters:3 um:zero minimum:1000 name:PM_FPU_ISSUE_STALL_ST_GRP119 : (Group 119 pm_fpu_issue3) FPU issue stalled due to store
+
+#Group 120 pm_fpu0_flop, FPU0 flop events
+event:0X0780 counters:0 um:zero minimum:1000 name:PM_FPU0_1FLOP_GRP120 : (Group 120 pm_fpu0_flop) FPU0 executed add, mult, sub, cmp or sel instruction
+event:0X0781 counters:1 um:zero minimum:1000 name:PM_FPU0_FMA_GRP120 : (Group 120 pm_fpu0_flop) FPU0 executed multiply-add instruction
+event:0X0782 counters:2 um:zero minimum:1000 name:PM_FPU0_FSQRT_FDIV_GRP120 : (Group 120 pm_fpu0_flop) FPU0 executed FSQRT or FDIV instruction
+event:0X0783 counters:3 um:zero minimum:1000 name:PM_FPU0_STF_GRP120 : (Group 120 pm_fpu0_flop) FPU0 executed store instruction
+
+#Group 121 pm_fpu0_misc, FPU0 events
+event:0X0790 counters:0 um:zero minimum:1000 name:PM_FPU0_FLOP_GRP121 : (Group 121 pm_fpu0_misc) FPU0 executed 1FLOP, FMA, FSQRT or FDIV instruction
+event:0X0791 counters:1 um:zero minimum:1000 name:PM_FPU0_FXDIV_GRP121 : (Group 121 pm_fpu0_misc) FPU0 executed fixed point division
+event:0X0792 counters:2 um:zero minimum:1000 name:PM_FPU0_DENORM_GRP121 : (Group 121 pm_fpu0_misc) FPU0 received denormalized data
+event:0X0793 counters:3 um:zero minimum:1000 name:PM_FPU0_SINGLE_GRP121 : (Group 121 pm_fpu0_misc) FPU0 executed single precision instruction
+
+#Group 122 pm_fpu0_misc2, FPU0 events
+event:0X07A0 counters:0 um:zero minimum:1000 name:PM_FPU0_FIN_GRP122 : (Group 122 pm_fpu0_misc2) FPU0 produced a result
+event:0X07A1 counters:1 um:zero minimum:1000 name:PM_FPU0_FEST_GRP122 : (Group 122 pm_fpu0_misc2) FPU0 executed FEST instruction
+event:0X07A2 counters:2 um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP122 : (Group 122 pm_fpu0_misc2) FPU0 executed FPSCR instruction
+event:0X07A3 counters:3 um:zero minimum:1000 name:PM_FPU0_FXMULT_GRP122 : (Group 122 pm_fpu0_misc2) FPU0 executed fixed point multiplication
+
+#Group 123 pm_fpu0_misc3, FPU0 events
+event:0X07B0 counters:0 um:zero minimum:1000 name:PM_FPU0_FCONV_GRP123 : (Group 123 pm_fpu0_misc3) FPU0 executed FCONV instruction
+event:0X07B1 counters:1 um:zero minimum:1000 name:PM_FPU0_FRSP_GRP123 : (Group 123 pm_fpu0_misc3) FPU0 executed FRSP instruction
+event:0X07B2 counters:2 um:zero minimum:1000 name:PM_FPU0_ST_FOLDED_GRP123 : (Group 123 pm_fpu0_misc3) FPU0 folded store
+event:0X07B3 counters:3 um:zero minimum:1000 name:PM_FPU0_FEST_GRP123 : (Group 123 pm_fpu0_misc3) FPU0 executed FEST instruction
+
+#Group 124 pm_fpu1_flop, FPU1 flop events
+event:0X07C0 counters:0 um:zero minimum:1000 name:PM_FPU1_1FLOP_GRP124 : (Group 124 pm_fpu1_flop) FPU1 executed add, mult, sub, cmp or sel instruction
+event:0X07C1 counters:1 um:zero minimum:1000 name:PM_FPU1_FMA_GRP124 : (Group 124 pm_fpu1_flop) FPU1 executed multiply-add instruction
+event:0X07C2 counters:2 um:zero minimum:1000 name:PM_FPU1_FSQRT_FDIV_GRP124 : (Group 124 pm_fpu1_flop) FPU1 executed FSQRT or FDIV instruction
+event:0X07C3 counters:3 um:zero minimum:1000 name:PM_FPU1_STF_GRP124 : (Group 124 pm_fpu1_flop) FPU1 executed store instruction
+
+#Group 125 pm_fpu1_misc, FPU1 events
+event:0X07D0 counters:0 um:zero minimum:1000 name:PM_FPU1_FLOP_GRP125 : (Group 125 pm_fpu1_misc) FPU1 executed 1FLOP, FMA, FSQRT or FDIV instruction
+event:0X07D1 counters:1 um:zero minimum:1000 name:PM_FPU1_FXDIV_GRP125 : (Group 125 pm_fpu1_misc) FPU1 executed fixed point division
+event:0X07D2 counters:2 um:zero minimum:1000 name:PM_FPU1_DENORM_GRP125 : (Group 125 pm_fpu1_misc) FPU1 received denormalized data
+event:0X07D3 counters:3 um:zero minimum:1000 name:PM_FPU1_SINGLE_GRP125 : (Group 125 pm_fpu1_misc) FPU1 executed single precision instruction
+
+#Group 126 pm_fpu1_misc2, FPU1 events
+event:0X07E0 counters:0 um:zero minimum:1000 name:PM_FPU1_FIN_GRP126 : (Group 126 pm_fpu1_misc2) FPU1 produced a result
+event:0X07E1 counters:1 um:zero minimum:1000 name:PM_FPU1_FEST_GRP126 : (Group 126 pm_fpu1_misc2) FPU1 executed FEST instruction
+event:0X07E2 counters:2 um:zero minimum:1000 name:PM_FPU1_FPSCR_GRP126 : (Group 126 pm_fpu1_misc2) FPU1 executed FPSCR instruction
+event:0X07E3 counters:3 um:zero minimum:1000 name:PM_FPU1_FXMULT_GRP126 : (Group 126 pm_fpu1_misc2) FPU1 executed fixed point multiplication
+
+#Group 127 pm_fpu1_misc3, FPU1 events
+event:0X07F0 counters:0 um:zero minimum:1000 name:PM_FPU1_FCONV_GRP127 : (Group 127 pm_fpu1_misc3) FPU1 executed FCONV instruction
+event:0X07F1 counters:1 um:zero minimum:1000 name:PM_FPU1_FRSP_GRP127 : (Group 127 pm_fpu1_misc3) FPU1 executed FRSP instruction
+event:0X07F2 counters:2 um:zero minimum:1000 name:PM_FPU1_ST_FOLDED_GRP127 : (Group 127 pm_fpu1_misc3) FPU1 folded store
+event:0X07F3 counters:3 um:zero minimum:1000 name:PM_FPU1_FEST_GRP127 : (Group 127 pm_fpu1_misc3) FPU1 executed FEST instruction
+
+#Group 128 pm_fpu_flop, FPU flop events
+event:0X0800 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP128 : (Group 128 pm_fpu_flop) FPU executed one flop instruction
+event:0X0801 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP128 : (Group 128 pm_fpu_flop) FPU executed multiply-add instruction
+event:0X0802 counters:2 um:zero minimum:1000 name:PM_FPU_FSQRT_FDIV_GRP128 : (Group 128 pm_fpu_flop) FPU executed FSQRT or FDIV instruction
+event:0X0803 counters:3 um:zero minimum:1000 name:PM_FPU_FLOP_GRP128 : (Group 128 pm_fpu_flop) FPU executed 1FLOP, FMA, FSQRT or FDIV instruction
+
+#Group 129 pm_fpu_misc, FPU events
+event:0X0810 counters:0 um:zero minimum:1000 name:PM_FPU_FIN_GRP129 : (Group 129 pm_fpu_misc) FPU produced a result
+event:0X0811 counters:1 um:zero minimum:1000 name:PM_FPU_FRSP_GRP129 : (Group 129 pm_fpu_misc) FPU executed FRSP instruction
+event:0X0812 counters:2 um:zero minimum:1000 name:PM_FPU_FPSCR_GRP129 : (Group 129 pm_fpu_misc) FPU executed FPSCR instruction
+event:0X0813 counters:3 um:zero minimum:1000 name:PM_FPU_FXMULT_GRP129 : (Group 129 pm_fpu_misc) FPU executed fixed point multiplication
+
+#Group 130 pm_fpu_misc2, FPU events
+event:0X0820 counters:0 um:zero minimum:1000 name:PM_FPU_FXDIV_GRP130 : (Group 130 pm_fpu_misc2) FPU executed fixed point division
+event:0X0821 counters:1 um:zero minimum:1000 name:PM_FPU_DENORM_GRP130 : (Group 130 pm_fpu_misc2) FPU received denormalized data
+event:0X0822 counters:2 um:zero minimum:1000 name:PM_FPU_STF_GRP130 : (Group 130 pm_fpu_misc2) FPU executed store instruction
+event:0X0823 counters:3 um:zero minimum:1000 name:PM_FPU_SINGLE_GRP130 : (Group 130 pm_fpu_misc2) FPU executed single precision instruction
+
+#Group 131 pm_fpu_misc3, FPU events
+event:0X0830 counters:0 um:zero minimum:1000 name:PM_FPU_FCONV_GRP131 : (Group 131 pm_fpu_misc3) FPU executed FCONV instruction
+event:0X0831 counters:1 um:zero minimum:1000 name:PM_FPU_FRSP_GRP131 : (Group 131 pm_fpu_misc3) FPU executed FRSP instruction
+event:0X0832 counters:2 um:zero minimum:1000 name:PM_FPU_ST_FOLDED_GRP131 : (Group 131 pm_fpu_misc3) FPU folded store
+event:0X0833 counters:3 um:zero minimum:1000 name:PM_FPU_FEST_GRP131 : (Group 131 pm_fpu_misc3) FPU executed FEST instruction
+
+#Group 132 pm_purr, PURR events
+event:0X0840 counters:0 um:zero minimum:1000 name:PM_PURR_GRP132 : (Group 132 pm_purr) PURR Event
+event:0X0841 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP132 : (Group 132 pm_purr) Run cycles
+event:0X0842 counters:2 um:zero minimum:10000 name:PM_CYC_GRP132 : (Group 132 pm_purr) Processor cycles
+event:0X0843 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP132 : (Group 132 pm_purr) Instructions completed
+
+#Group 133 pm_suspend, SUSPENDED events
+event:0X0850 counters:0 um:zero minimum:1000 name:PM_SUSPENDED_GRP133 : (Group 133 pm_suspend) Suspended
+event:0X0851 counters:1 um:zero minimum:10000 name:PM_CYC_GRP133 : (Group 133 pm_suspend) Processor cycles
+event:0X0852 counters:2 um:zero minimum:1000 name:PM_SYNC_CYC_GRP133 : (Group 133 pm_suspend) Sync duration
+event:0X0853 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP133 : (Group 133 pm_suspend) Instructions completed
+
+#Group 134 pm_dcache, D cache
+event:0X0860 counters:0 um:zero minimum:1000 name:PM_LD_MISS_L1_CYC_GRP134 : (Group 134 pm_dcache) L1 data load miss cycles
+event:0X0861 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP134 : (Group 134 pm_dcache) DERAT misses
+event:0X0862 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP134 : (Group 134 pm_dcache) L1 D cache load misses
+event:0X0863 counters:3 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_CYC_GRP134 : (Group 134 pm_dcache) DERAT miss latency
+
+#Group 135 pm_derat_miss, DERAT miss
+event:0X0870 counters:0 um:zero minimum:1000 name:PM_DERAT_MISS_4K_GRP135 : (Group 135 pm_derat_miss) DERAT misses for 4K page
+event:0X0871 counters:1 um:zero minimum:1000 name:PM_DERAT_MISS_64K_GRP135 : (Group 135 pm_derat_miss) DERAT misses for 64K page
+event:0X0872 counters:2 um:zero minimum:1000 name:PM_DERAT_MISS_16M_GRP135 : (Group 135 pm_derat_miss) DERAT misses for 16M page
+event:0X0873 counters:3 um:zero minimum:1000 name:PM_DERAT_MISS_16G_GRP135 : (Group 135 pm_derat_miss) DERAT misses for 16G page
+
+#Group 136 pm_derat_ref, DERAT ref
+event:0X0880 counters:0 um:zero minimum:1000 name:PM_DERAT_REF_4K_GRP136 : (Group 136 pm_derat_ref) DERAT reference for 4K page
+event:0X0881 counters:1 um:zero minimum:1000 name:PM_DERAT_REF_64K_GRP136 : (Group 136 pm_derat_ref) DERAT reference for 64K page
+event:0X0882 counters:2 um:zero minimum:1000 name:PM_DERAT_REF_16M_GRP136 : (Group 136 pm_derat_ref) DERAT reference for 16M page
+event:0X0883 counters:3 um:zero minimum:1000 name:PM_DERAT_REF_16G_GRP136 : (Group 136 pm_derat_ref) DERAT reference for 16G page
+
+#Group 137 pm_ierat_miss, IERAT miss
+event:0X0890 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_16G_GRP137 : (Group 137 pm_ierat_miss) IERAT misses for 16G page
+event:0X0891 counters:1 um:zero minimum:1000 name:PM_IERAT_MISS_16M_GRP137 : (Group 137 pm_ierat_miss) IERAT misses for 16M page
+event:0X0892 counters:2 um:zero minimum:1000 name:PM_IERAT_MISS_64K_GRP137 : (Group 137 pm_ierat_miss) IERAT misses for 64K page
+event:0X0893 counters:3 um:zero minimum:1000 name:PM_IERAT_MISS_4K_GRP137 : (Group 137 pm_ierat_miss) IERAT misses for 4K page
+
+#Group 138 pm_mrk_br, Marked Branch events
+event:0X08A0 counters:0 um:zero minimum:1000 name:PM_MRK_BR_TAKEN_GRP138 : (Group 138 pm_mrk_br) Marked branch taken
+event:0X08A1 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP138 : (Group 138 pm_mrk_br) Marked L1 D cache load misses
+event:0X08A2 counters:2 um:zero minimum:1000 name:PM_MRK_BR_MPRED_GRP138 : (Group 138 pm_mrk_br) Marked branch mispredicted
+event:0X08A3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP138 : (Group 138 pm_mrk_br) Instructions completed
+
+#Group 139 pm_mrk_dsource, Marked data sources
+event:0X08B0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP139 : (Group 139 pm_mrk_dsource) Instructions completed
+event:0X08B1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DMEM_GRP139 : (Group 139 pm_mrk_dsource) Marked data loaded from distant memory
+event:0X08B2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_SHR_GRP139 : (Group 139 pm_mrk_dsource) Marked data loaded from distant L2 or L3 shared
+event:0X08B3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_MOD_GRP139 : (Group 139 pm_mrk_dsource) Marked data loaded from distant L2 or L3 modified
+
+#Group 140 pm_mrk_dsource2, Marked data sources
+event:0X08C0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP140 : (Group 140 pm_mrk_dsource2) Marked data loaded from L2
+event:0X08C1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_GRP140 : (Group 140 pm_mrk_dsource2) Marked data loaded from private L2 other core
+event:0X08C2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_MOD_GRP140 : (Group 140 pm_mrk_dsource2) Marked data loaded from L2.5 modified
+event:0X08C3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP140 : (Group 140 pm_mrk_dsource2) Instructions completed
+
+#Group 141 pm_mrk_dsource3, Marked data sources
+event:0X08D0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2MISS_GRP141 : (Group 141 pm_mrk_dsource3) Marked data loaded missed L2
+event:0X08D1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP141 : (Group 141 pm_mrk_dsource3) Instructions completed
+event:0X08D2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP141 : (Group 141 pm_mrk_dsource3) Marked data loaded from L3
+event:0X08D3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L25_SHR_GRP141 : (Group 141 pm_mrk_dsource3) Marked data loaded from L2.5 shared
+
+#Group 142 pm_mrk_dsource4, Marked data sources
+event:0X08E0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_MOD_GRP142 : (Group 142 pm_mrk_dsource4) Marked data loaded from L3.5 modified
+event:0X08E1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L35_SHR_GRP142 : (Group 142 pm_mrk_dsource4) Marked data loaded from L3.5 shared
+event:0X08E2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3MISS_GRP142 : (Group 142 pm_mrk_dsource4) Marked data loaded from L3 miss
+event:0X08E3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP142 : (Group 142 pm_mrk_dsource4) Instructions completed
+
+#Group 143 pm_mrk_dsource5, Marked data sources
+event:0X08F0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_MEM_DP_GRP143 : (Group 143 pm_mrk_dsource5) Marked data loaded from double pump memory
+event:0X08F1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_SHR_GRP143 : (Group 143 pm_mrk_dsource5) Marked data loaded from remote L2 or L3 shared
+event:0X08F2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP143 : (Group 143 pm_mrk_dsource5) Instructions completed
+event:0X08F3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_GRP143 : (Group 143 pm_mrk_dsource5) Marked data loaded from local memory
+
+#Group 144 pm_mrk_dsource6, Marked data sources
+event:0X0900 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_MOD_GRP144 : (Group 144 pm_mrk_dsource6) Marked data loaded from remote L2 or L3 modified
+event:0X0901 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_SHR_GRP144 : (Group 144 pm_mrk_dsource6) Marked data loaded from remote L2 or L3 shared
+event:0X0902 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_GRP144 : (Group 144 pm_mrk_dsource6) Marked data loaded from remote memory
+event:0X0903 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP144 : (Group 144 pm_mrk_dsource6) Instructions completed
+
+#Group 145 pm_mrk_rejects, Marked rejects
+event:0X0910 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_ULD_GRP145 : (Group 145 pm_mrk_rejects) Marked unaligned load reject
+event:0X0911 counters:1 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_UST_GRP145 : (Group 145 pm_mrk_rejects) Marked unaligned store reject
+event:0X0912 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP145 : (Group 145 pm_mrk_rejects) Instructions completed
+event:0X0913 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_LHS_GRP145 : (Group 145 pm_mrk_rejects) Marked load hit store reject
+
+#Group 146 pm_mrk_rejects2, Marked rejects LSU0
+event:0X0920 counters:0 um:zero minimum:1000 name:PM_MRK_LSU0_REJECT_LHS_GRP146 : (Group 146 pm_mrk_rejects2) LSU0 marked load hit store reject
+event:0X0921 counters:1 um:zero minimum:1000 name:PM_MRK_LSU0_REJECT_ULD_GRP146 : (Group 146 pm_mrk_rejects2) LSU0 marked unaligned load reject
+event:0X0922 counters:2 um:zero minimum:1000 name:PM_MRK_LSU0_REJECT_UST_GRP146 : (Group 146 pm_mrk_rejects2) LSU0 marked unaligned store reject
+event:0X0923 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP146 : (Group 146 pm_mrk_rejects2) Instructions completed
+
+#Group 147 pm_mrk_rejects3, Marked rejects LSU1
+event:0X0930 counters:0 um:zero minimum:1000 name:PM_MRK_LSU1_REJECT_LHS_GRP147 : (Group 147 pm_mrk_rejects3) LSU1 marked load hit store reject
+event:0X0931 counters:1 um:zero minimum:1000 name:PM_MRK_LSU1_REJECT_ULD_GRP147 : (Group 147 pm_mrk_rejects3) LSU1 marked unaligned load reject
+event:0X0932 counters:2 um:zero minimum:1000 name:PM_MRK_LSU1_REJECT_UST_GRP147 : (Group 147 pm_mrk_rejects3) LSU1 marked unaligned store reject
+event:0X0933 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP147 : (Group 147 pm_mrk_rejects3) Instructions completed
+
+#Group 148 pm_mrk_inst, Marked instruction events
+event:0X0940 counters:0 um:zero minimum:1000 name:PM_MRK_INST_ISSUED_GRP148 : (Group 148 pm_mrk_inst) Marked instruction issued
+event:0X0941 counters:1 um:zero minimum:1000 name:PM_MRK_INST_DISP_GRP148 : (Group 148 pm_mrk_inst) Marked instruction dispatched
+event:0X0942 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP148 : (Group 148 pm_mrk_inst) Marked instruction finished
+event:0X0943 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP148 : (Group 148 pm_mrk_inst) Instructions completed
+
+#Group 149 pm_mrk_fpu_fin, Marked Floating Point instructions finished
+event:0X0950 counters:0 um:zero minimum:1000 name:PM_MRK_FPU0_FIN_GRP149 : (Group 149 pm_mrk_fpu_fin) Marked instruction FPU0 processing finished
+event:0X0951 counters:1 um:zero minimum:1000 name:PM_MRK_FPU1_FIN_GRP149 : (Group 149 pm_mrk_fpu_fin) Marked instruction FPU1 processing finished
+event:0X0952 counters:2 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP149 : (Group 149 pm_mrk_fpu_fin) Marked instruction FPU processing finished
+event:0X0953 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP149 : (Group 149 pm_mrk_fpu_fin) Instructions completed
+
+#Group 150 pm_mrk_misc, Marked misc events
+event:0X0960 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_ULD_GRP150 : (Group 150 pm_mrk_misc) Marked unaligned load reject
+event:0X0961 counters:1 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP150 : (Group 150 pm_mrk_misc) Marked instruction FXU processing finished
+event:0X0962 counters:2 um:zero minimum:1000 name:PM_MRK_DFU_FIN_GRP150 : (Group 150 pm_mrk_misc) DFU marked instruction finish
+event:0X0963 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP150 : (Group 150 pm_mrk_misc) Instructions completed
+
+#Group 151 pm_mrk_misc2, Marked misc events
+event:0X0970 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP151 : (Group 151 pm_mrk_misc2) Marked STCX failed
+event:0X0971 counters:1 um:zero minimum:1000 name:PM_MRK_IFU_FIN_GRP151 : (Group 151 pm_mrk_misc2) Marked instruction IFU processing finished
+event:0X0972 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP151 : (Group 151 pm_mrk_misc2) Instructions completed
+event:0X0973 counters:3 um:zero minimum:1000 name:PM_MRK_INST_TIMEO_GRP151 : (Group 151 pm_mrk_misc2) Marked Instruction finish timeout
+
+#Group 152 pm_mrk_misc3, Marked misc events
+event:0X0980 counters:0 um:zero minimum:1000 name:PM_MRK_VMX_ST_ISSUED_GRP152 : (Group 152 pm_mrk_misc3) Marked VMX store issued
+event:0X0981 counters:1 um:zero minimum:1000 name:PM_MRK_LSU0_REJECT_L2MISS_GRP152 : (Group 152 pm_mrk_misc3) LSU0 marked L2 miss reject
+event:0X0982 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP152 : (Group 152 pm_mrk_misc3) Instructions completed
+event:0X0983 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_DERAT_MISS_GRP152 : (Group 152 pm_mrk_misc3) Marked DERAT miss
+
+#Group 153 pm_mrk_misc4, Marked misc events
+event:0X0990 counters:0 um:zero minimum:10000 name:PM_CYC_GRP153 : (Group 153 pm_mrk_misc4) Processor cycles
+event:0X0991 counters:1 um:zero minimum:10000 name:PM_CYC_GRP153 : (Group 153 pm_mrk_misc4) Processor cycles
+event:0X0992 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP153 : (Group 153 pm_mrk_misc4) Instructions completed
+event:0X0993 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP153 : (Group 153 pm_mrk_misc4) Marked instruction LSU processing finished
+
+#Group 154 pm_mrk_st, Marked stores events
+event:0X09A0 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP154 : (Group 154 pm_mrk_st) Marked store instruction completed
+event:0X09A1 counters:1 um:zero minimum:1000 name:PM_MRK_ST_GPS_GRP154 : (Group 154 pm_mrk_st) Marked store sent to GPS
+event:0X09A2 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP154 : (Group 154 pm_mrk_st) Marked store completed with intervention
+event:0X09A3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP154 : (Group 154 pm_mrk_st) Instructions completed
+
+#Group 155 pm_mrk_pteg, Marked PTEG
+event:0X09B0 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L2_GRP155 : (Group 155 pm_mrk_pteg) Marked PTEG loaded from L2.5 modified
+event:0X09B1 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DMEM_GRP155 : (Group 155 pm_mrk_pteg) Marked PTEG loaded from distant memory
+event:0X09B2 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DL2L3_SHR_GRP155 : (Group 155 pm_mrk_pteg) Marked PTEG loaded from distant L2 or L3 shared
+event:0X09B3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP155 : (Group 155 pm_mrk_pteg) Instructions completed
+
+#Group 156 pm_mrk_pteg2, Marked PTEG
+event:0X09C0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP156 : (Group 156 pm_mrk_pteg2) Instructions completed
+event:0X09C1 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L21_GRP156 : (Group 156 pm_mrk_pteg2) Marked PTEG loaded from private L2 other core
+event:0X09C2 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L25_MOD_GRP156 : (Group 156 pm_mrk_pteg2) Marked PTEG loaded from L2.5 modified
+event:0X09C3 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DL2L3_MOD_GRP156 : (Group 156 pm_mrk_pteg2) Marked PTEG loaded from distant L2 or L3 modified
+
+#Group 157 pm_mrk_pteg3, Marked PTEG
+event:0X09D0 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L35_MOD_GRP157 : (Group 157 pm_mrk_pteg3) Marked PTEG loaded from L3.5 modified
+event:0X09D1 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L35_SHR_GRP157 : (Group 157 pm_mrk_pteg3) Marked PTEG loaded from L3.5 shared
+event:0X09D2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP157 : (Group 157 pm_mrk_pteg3) Instructions completed
+event:0X09D3 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L25_SHR_GRP157 : (Group 157 pm_mrk_pteg3) Marked PTEG loaded from L2.5 shared
+
+#Group 158 pm_mrk_pteg4, Marked PTEG
+event:0X09E0 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_MEM_DP_GRP158 : (Group 158 pm_mrk_pteg4) Marked PTEG loaded from double pump memory
+event:0X09E1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP158 : (Group 158 pm_mrk_pteg4) Instructions completed
+event:0X09E2 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L3_GRP158 : (Group 158 pm_mrk_pteg4) Marked PTEG loaded from L3
+event:0X09E3 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L2MISS_GRP158 : (Group 158 pm_mrk_pteg4) Marked PTEG loaded from L2 miss
+
+#Group 159 pm_mrk_pteg5, Marked PTEG
+event:0X09F0 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RL2L3_MOD_GRP159 : (Group 159 pm_mrk_pteg5) Marked PTEG loaded from remote L2 or L3 modified
+event:0X09F1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP159 : (Group 159 pm_mrk_pteg5) Instructions completed
+event:0X09F2 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L3MISS_GRP159 : (Group 159 pm_mrk_pteg5) Marked PTEG loaded from L3 miss
+event:0X09F3 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_LMEM_GRP159 : (Group 159 pm_mrk_pteg5) Marked PTEG loaded from local memory
+
+#Group 160 pm_mrk_pteg6, Marked PTEG
+event:0X0A00 counters:0 um:zero minimum:10000 name:PM_CYC_GRP160 : (Group 160 pm_mrk_pteg6) Processor cycles
+event:0X0A01 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RL2L3_SHR_GRP160 : (Group 160 pm_mrk_pteg6) Marked PTEG loaded from remote L2 or L3 shared
+event:0X0A02 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RMEM_GRP160 : (Group 160 pm_mrk_pteg6) Marked PTEG loaded from remote memory
+event:0X0A03 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP160 : (Group 160 pm_mrk_pteg6) Instructions completed
+
+#Group 161 pm_mrk_vmx, Marked VMX
+event:0X0A10 counters:0 um:zero minimum:1000 name:PM_MRK_VMX_COMPLEX_ISSUED_GRP161 : (Group 161 pm_mrk_vmx) Marked VMX instruction issued to complex
+event:0X0A11 counters:1 um:zero minimum:1000 name:PM_MRK_VMX_FLOAT_ISSUED_GRP161 : (Group 161 pm_mrk_vmx) Marked VMX instruction issued to float
+event:0X0A12 counters:2 um:zero minimum:1000 name:PM_MRK_VMX_PERMUTE_ISSUED_GRP161 : (Group 161 pm_mrk_vmx) Marked VMX instruction issued to permute
+event:0X0A13 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP161 : (Group 161 pm_mrk_vmx) Instructions completed
+
+#Group 162 pm_mrk_vmx2, Marked VMX
+event:0X0A20 counters:0 um:zero minimum:1000 name:PM_MRK_VMX0_LD_WRBACK_GRP162 : (Group 162 pm_mrk_vmx2) Marked VMX0 load writeback valid
+event:0X0A21 counters:1 um:zero minimum:1000 name:PM_MRK_VMX1_LD_WRBACK_GRP162 : (Group 162 pm_mrk_vmx2) Marked VMX1 load writeback valid
+event:0X0A22 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_REF_GRP162 : (Group 162 pm_mrk_vmx2) Marked Data TLB reference
+event:0X0A23 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP162 : (Group 162 pm_mrk_vmx2) Instructions completed
+
+#Group 163 pm_mrk_vmx3, Marked VMX
+event:0X0A30 counters:0 um:zero minimum:1000 name:PM_MRK_VMX_SIMPLE_ISSUED_GRP163 : (Group 163 pm_mrk_vmx3) Marked VMX instruction issued to simple
+event:0X0A31 counters:1 um:zero minimum:1000 name:PM_VMX_SIMPLE_ISSUED_GRP163 : (Group 163 pm_mrk_vmx3) VMX instruction issued to simple
+event:0X0A32 counters:2 um:zero minimum:10000 name:PM_CYC_GRP163 : (Group 163 pm_mrk_vmx3) Processor cycles
+event:0X0A33 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP163 : (Group 163 pm_mrk_vmx3) Instructions completed
+
+#Group 164 pm_mrk_fp, Marked FP events
+event:0X0A40 counters:0 um:zero minimum:1000 name:PM_MRK_FPU0_FIN_GRP164 : (Group 164 pm_mrk_fp) Marked instruction FPU0 processing finished
+event:0X0A41 counters:1 um:zero minimum:1000 name:PM_MRK_FPU_FIN_GRP164 : (Group 164 pm_mrk_fp) Marked instruction FPU processing finished
+event:0X0A42 counters:2 um:zero minimum:1000 name:PM_MRK_FPU1_FIN_GRP164 : (Group 164 pm_mrk_fp) Marked instruction FPU1 processing finished
+event:0X0A43 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP164 : (Group 164 pm_mrk_fp) Instructions completed
+
+#Group 165 pm_mrk_derat_ref, Marked DERAT ref
+event:0X0A50 counters:0 um:zero minimum:1000 name:PM_MRK_DERAT_REF_64K_GRP165 : (Group 165 pm_mrk_derat_ref) Marked DERAT reference for 64K page
+event:0X0A51 counters:1 um:zero minimum:1000 name:PM_MRK_DERAT_REF_4K_GRP165 : (Group 165 pm_mrk_derat_ref) Marked DERAT reference for 4K page
+event:0X0A52 counters:2 um:zero minimum:1000 name:PM_MRK_DERAT_REF_16M_GRP165 : (Group 165 pm_mrk_derat_ref) Marked DERAT reference for 16M page
+event:0X0A53 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP165 : (Group 165 pm_mrk_derat_ref) Instructions completed
+
+#Group 166 pm_mrk_derat_miss, Marked DERAT miss
+event:0X0A60 counters:0 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_64K_GRP166 : (Group 166 pm_mrk_derat_miss) Marked DERAT misses for 64K page
+event:0X0A61 counters:1 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_4K_GRP166 : (Group 166 pm_mrk_derat_miss) Marked DERAT misses for 4K page
+event:0X0A62 counters:2 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_16M_GRP166 : (Group 166 pm_mrk_derat_miss) Marked DERAT misses for 16M page
+event:0X0A63 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP166 : (Group 166 pm_mrk_derat_miss) Instructions completed
+
+#Group 167 pm_dcache_edge, D cache - edge
+event:0X0A70 counters:0 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP167 : (Group 167 pm_dcache_edge) L1 D cache load misses
+event:0X0A71 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP167 : (Group 167 pm_dcache_edge) DERAT misses
+event:0X0A72 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP167 : (Group 167 pm_dcache_edge) L1 D cache load misses
+event:0X0A73 counters:3 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP167 : (Group 167 pm_dcache_edge) DERAT misses
+
+#Group 168 pm_lsu_lmq_edge, LSU LMQ events - edge
+event:0X0A80 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP168 : (Group 168 pm_lsu_lmq_edge) Cycles LMQ full
+event:0X0A81 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_COUNT_GRP168 : (Group 168 pm_lsu_lmq_edge) Periods LMQ and SRQ empty
+event:0X0A82 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT_GRP168 : (Group 168 pm_lsu_lmq_edge) Periods both threads LMQ and SRQ empty
+event:0X0A83 counters:3 um:zero minimum:1000 name:PM_LSU0_REJECT_L2MISS_GRP168 : (Group 168 pm_lsu_lmq_edge) LSU0 L2 miss reject
+
+#Group 169 pm_gct_edge, GCT events - edge
+event:0X0A90 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_COUNT_GRP169 : (Group 169 pm_gct_edge) Periods no GCT slot allocated
+event:0X0A91 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_COUNT_GRP169 : (Group 169 pm_gct_edge) Periods GCT empty
+event:0X0A92 counters:2 um:zero minimum:1000 name:PM_GCT_FULL_COUNT_GRP169 : (Group 169 pm_gct_edge) Periods GCT full
+event:0X0A93 counters:3 um:zero minimum:1000 name:PM_INST_FETCH_CYC_GRP169 : (Group 169 pm_gct_edge) Cycles at least 1 instruction fetched
+
+#Group 170 pm_freq_edge, Frequency events - edge
+event:0X0AA0 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_THERMAL_COUNT_GRP170 : (Group 170 pm_freq_edge) Periods DISP unit held due to thermal condition
+event:0X0AA1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_COUNT_GRP170 : (Group 170 pm_freq_edge) Periods DISP unit held due to Power Management
+event:0X0AA2 counters:2 um:zero minimum:1000 name:PM_FREQ_DOWN_GRP170 : (Group 170 pm_freq_edge) Frequency is being slewed down due to Power Management
+event:0X0AA3 counters:3 um:zero minimum:1000 name:PM_FREQ_UP_GRP170 : (Group 170 pm_freq_edge) Frequency is being slewed up due to Power Management
+
+#Group 171 pm_disp_wait_edge, Dispatch stalls - edge
+event:0X0AB0 counters:0 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP171 : (Group 171 pm_disp_wait_edge) L1 I cache miss count
+event:0X0AB1 counters:1 um:zero minimum:1000 name:PM_DPU_WT_IC_MISS_COUNT_GRP171 : (Group 171 pm_disp_wait_edge) Periods DISP unit is stalled due to I cache miss
+event:0X0AB2 counters:2 um:zero minimum:1000 name:PM_DPU_WT_COUNT_GRP171 : (Group 171 pm_disp_wait_edge) Periods DISP unit is stalled waiting for instructions
+event:0X0AB3 counters:3 um:zero minimum:1000 name:PM_DPU_WT_BR_MPRED_COUNT_GRP171 : (Group 171 pm_disp_wait_edge) Periods DISP unit is stalled due to branch misprediction
+
+#Group 172 pm_edge1, EDGE event group
+event:0X0AC0 counters:0 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP172 : (Group 172 pm_edge1) L1 D cache load misses
+event:0X0AC1 counters:1 um:zero minimum:1000 name:PM_DPU_WT_IC_MISS_GRP172 : (Group 172 pm_edge1) Cycles DISP unit is stalled due to I cache miss
+event:0X0AC2 counters:2 um:zero minimum:1000 name:PM_LLA_COUNT_GRP172 : (Group 172 pm_edge1) Transitions into Load Look Ahead mode
+event:0X0AC3 counters:3 um:zero minimum:1000 name:PM_LLA_CYC_GRP172 : (Group 172 pm_edge1) Load Look Ahead Active
+
+#Group 173 pm_edge2, EDGE event group
+event:0X0AD0 counters:0 um:zero minimum:1000 name:PM_0INST_FETCH_COUNT_GRP173 : (Group 173 pm_edge2) Periods with no instructions fetched
+event:0X0AD1 counters:1 um:zero minimum:1000 name:PM_0INST_FETCH_GRP173 : (Group 173 pm_edge2) No instructions fetched
+event:0X0AD2 counters:2 um:zero minimum:1000 name:PM_IBUF_FULL_COUNT_GRP173 : (Group 173 pm_edge2) Periods instruction buffer full
+event:0X0AD3 counters:3 um:zero minimum:1000 name:PM_IBUF_FULL_CYC_GRP173 : (Group 173 pm_edge2) Cycles instruction buffer full
+
+#Group 174 pm_edge3, EDGE event group
+event:0X0AE0 counters:0 um:zero minimum:1000 name:PM_RUN_COUNT_GRP174 : (Group 174 pm_edge3) Run Periods
+event:0X0AE1 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP174 : (Group 174 pm_edge3) Run cycles
+event:0X0AE2 counters:2 um:zero minimum:1000 name:PM_INST_TABLEWALK_COUNT_GRP174 : (Group 174 pm_edge3) Periods doing instruction tablewalks
+event:0X0AE3 counters:3 um:zero minimum:1000 name:PM_INST_TABLEWALK_CYC_GRP174 : (Group 174 pm_edge3) Cycles doing instruction tablewalks
+
+#Group 175 pm_edge4, EDGE event group
+event:0X0AF0 counters:0 um:zero minimum:1000 name:PM_GCT_FULL_COUNT_GRP175 : (Group 175 pm_edge4) Periods GCT full
+event:0X0AF1 counters:1 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP175 : (Group 175 pm_edge4) Cycles GCT full
+event:0X0AF2 counters:2 um:zero minimum:1000 name:PM_NO_ITAG_COUNT_GRP175 : (Group 175 pm_edge4) Periods no ITAG available
+event:0X0AF3 counters:3 um:zero minimum:1000 name:PM_NO_ITAG_CYC_GRP175 : (Group 175 pm_edge4) Cyles no ITAG available
+
+#Group 176 pm_edge5, EDGE event group
+event:0X0B00 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_COUNT_GRP176 : (Group 176 pm_edge5) Periods one of the threads in run cycles
+event:0X0B01 counters:1 um:zero minimum:1000 name:PM_HV_COUNT_GRP176 : (Group 176 pm_edge5) Hypervisor Periods
+event:0X0B02 counters:2 um:zero minimum:1000 name:PM_SYNC_COUNT_GRP176 : (Group 176 pm_edge5) SYNC instructions completed
+event:0X0B03 counters:3 um:zero minimum:1000 name:PM_SYNC_CYC_GRP176 : (Group 176 pm_edge5) Sync duration
+
+#Group 177 pm_noedge5, EDGE event group
+event:0X0B10 counters:0 um:zero minimum:1000 name:PM_THRD_ONE_RUN_CYC_GRP177 : (Group 177 pm_noedge5) One of the threads in run cycles
+event:0X0B11 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP177 : (Group 177 pm_noedge5) Hypervisor Cycles
+event:0X0B12 counters:2 um:zero minimum:1000 name:PM_SYNC_COUNT_GRP177 : (Group 177 pm_noedge5) SYNC instructions completed
+event:0X0B13 counters:3 um:zero minimum:1000 name:PM_SYNC_CYC_GRP177 : (Group 177 pm_noedge5) Sync duration
+
+#Group 178 pm_edge6, EDGE event group
+event:0X0B20 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_THERMAL_COUNT_GRP178 : (Group 178 pm_edge6) Periods DISP unit held due to thermal condition
+event:0X0B21 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_COUNT_GRP178 : (Group 178 pm_edge6) Periods DISP unit held
+event:0X0B22 counters:2 um:zero minimum:1000 name:PM_DPU_WT_COUNT_GRP178 : (Group 178 pm_edge6) Periods DISP unit is stalled waiting for instructions
+event:0X0B23 counters:3 um:zero minimum:1000 name:PM_DPU_WT_BR_MPRED_COUNT_GRP178 : (Group 178 pm_edge6) Periods DISP unit is stalled due to branch misprediction
+
+#Group 179 pm_noedge6, EDGE event group
+event:0X0B30 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_THERMAL_GRP179 : (Group 179 pm_noedge6) DISP unit held due to thermal condition
+event:0X0B31 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_GRP179 : (Group 179 pm_noedge6) DISP unit held
+event:0X0B32 counters:2 um:zero minimum:1000 name:PM_DPU_WT_GRP179 : (Group 179 pm_noedge6) Cycles DISP unit is stalled waiting for instructions
+event:0X0B33 counters:3 um:zero minimum:1000 name:PM_DPU_WT_BR_MPRED_GRP179 : (Group 179 pm_noedge6) Cycles DISP unit is stalled due to branch misprediction
+
+#Group 180 pm_edge7, EDGE event group
+event:0X0B40 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_COUNT_GRP180 : (Group 180 pm_edge7) Periods no GCT slot allocated
+event:0X0B41 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_COUNT_GRP180 : (Group 180 pm_edge7) Periods GCT empty
+event:0X0B42 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_BOTH_COUNT_GRP180 : (Group 180 pm_edge7) Periods both threads LMQ and SRQ empty
+event:0X0B43 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_COUNT_GRP180 : (Group 180 pm_edge7) Periods SRQ empty
+
+#Group 181 pm_noedge7, NOEDGE event group
+event:0X0B50 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP181 : (Group 181 pm_noedge7) Cycles no GCT slot allocated
+event:0X0B51 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP181 : (Group 181 pm_noedge7) Cycles GCT empty
+event:0X0B52 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_BOTH_CYC_GRP181 : (Group 181 pm_noedge7) Cycles both threads LMQ and SRQ empty
+event:0X0B53 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP181 : (Group 181 pm_noedge7) Cycles SRQ empty
+
+#Group 182 pm_edge8, EDGE event group
+event:0X0B60 counters:0 um:zero minimum:1000 name:PM_SYNC_COUNT_GRP182 : (Group 182 pm_edge8) SYNC instructions completed
+event:0X0B61 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_COUNT_GRP182 : (Group 182 pm_edge8) Periods LMQ and SRQ empty
+event:0X0B62 counters:2 um:zero minimum:1000 name:PM_SYNC_CYC_GRP182 : (Group 182 pm_edge8) Sync duration
+event:0X0B63 counters:3 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP182 : (Group 182 pm_edge8) DERAT misses
+
+#Group 183 pm_noedge8, NOEDGE event group
+event:0X0B70 counters:0 um:zero minimum:1000 name:PM_SYNC_CYC_GRP183 : (Group 183 pm_noedge8) Sync duration
+event:0X0B71 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP183 : (Group 183 pm_noedge8) Cycles LMQ and SRQ empty
+event:0X0B72 counters:2 um:zero minimum:1000 name:PM_SYNC_COUNT_GRP183 : (Group 183 pm_noedge8) SYNC instructions completed
+event:0X0B73 counters:3 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_CYC_GRP183 : (Group 183 pm_noedge8) DERAT miss latency
+
+#Group 184 pm_edge9, EDGE event group
+event:0X0B80 counters:0 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP184 : (Group 184 pm_edge9) L1 D cache store misses
+event:0X0B81 counters:1 um:zero minimum:1000 name:PM_DPU_WT_IC_MISS_COUNT_GRP184 : (Group 184 pm_edge9) Periods DISP unit is stalled due to I cache miss
+event:0X0B82 counters:2 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP184 : (Group 184 pm_edge9) L1 D cache load misses
+event:0X0B83 counters:3 um:zero minimum:1000 name:PM_LD_REF_L1_GRP184 : (Group 184 pm_edge9) L1 D cache load references
+
+#Group 185 pm_edge10, EDGE event group
+event:0X0B90 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_COMPLETION_GRP185 : (Group 185 pm_edge10) DISP unit held due to completion holding dispatch
+event:0X0B91 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_COUNT_GRP185 : (Group 185 pm_edge10) Periods DISP unit held due to Power Management
+event:0X0B92 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_CR_LOGICAL_GRP185 : (Group 185 pm_edge10) DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR
+event:0X0B93 counters:3 um:zero minimum:1000 name:PM_THRD_BOTH_RUN_COUNT_GRP185 : (Group 185 pm_edge10) Periods both threads in run cycles
+
+#Group 186 pm_noedge10, NOEDGE event group
+event:0X0BA0 counters:0 um:zero minimum:1000 name:PM_DPU_HELD_COMPLETION_GRP186 : (Group 186 pm_noedge10) DISP unit held due to completion holding dispatch
+event:0X0BA1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP186 : (Group 186 pm_noedge10) DISP unit held due to Power Management
+event:0X0BA2 counters:2 um:zero minimum:1000 name:PM_DPU_HELD_CR_LOGICAL_GRP186 : (Group 186 pm_noedge10) DISP unit held due to CR, LR or CTR updated by CR logical, MTCRF, MTLR or MTCTR
+event:0X0BA3 counters:3 um:zero minimum:1000 name:PM_THRD_BOTH_RUN_CYC_GRP186 : (Group 186 pm_noedge10) Both threads in run cycles
+
+#Group 187 pm_hpm1, HPM group
+event:0X0BB0 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP187 : (Group 187 pm_hpm1) FPU executed one flop instruction
+event:0X0BB1 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP187 : (Group 187 pm_hpm1) FPU executed multiply-add instruction
+event:0X0BB2 counters:2 um:zero minimum:1000 name:PM_FPU_FSQRT_FDIV_GRP187 : (Group 187 pm_hpm1) FPU executed FSQRT or FDIV instruction
+event:0X0BB3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP187 : (Group 187 pm_hpm1) Processor cycles
+
+#Group 188 pm_hpm2, HPM group
+event:0X0BC0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP188 : (Group 188 pm_hpm2) Instructions completed
+event:0X0BC1 counters:1 um:zero minimum:1000 name:PM_LSU_LDF_GRP188 : (Group 188 pm_hpm2) LSU executed Floating Point load instruction
+event:0X0BC2 counters:2 um:zero minimum:1000 name:PM_FPU_STF_GRP188 : (Group 188 pm_hpm2) FPU executed store instruction
+event:0X0BC3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP188 : (Group 188 pm_hpm2) Processor cycles
+
+#Group 189 pm_hpm3, HPM group
+event:0X0BD0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP189 : (Group 189 pm_hpm3) Processor cycles
+event:0X0BD1 counters:1 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP189 : (Group 189 pm_hpm3) L1 D cache load misses
+event:0X0BD2 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP189 : (Group 189 pm_hpm3) L1 D cache store misses
+event:0X0BD3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP189 : (Group 189 pm_hpm3) Instructions completed
+
+#Group 190 pm_hpm4, HPM group
+event:0X0BE0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP190 : (Group 190 pm_hpm4) Instructions completed
+event:0X0BE1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP190 : (Group 190 pm_hpm4) Instructions dispatched
+event:0X0BE2 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_GRP190 : (Group 190 pm_hpm4) L1 D cache load references
+event:0X0BE3 counters:3 um:zero minimum:1000 name:PM_ST_REF_L1_GRP190 : (Group 190 pm_hpm4) L1 D cache store references
+
+#Group 191 pm_hpm5, HPM group
+event:0X0BF0 counters:0 um:zero minimum:1000 name:PM_FPU_FIN_GRP191 : (Group 191 pm_hpm5) FPU produced a result
+event:0X0BF1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP191 : (Group 191 pm_hpm5) Processor cycles
+event:0X0BF2 counters:2 um:zero minimum:1000 name:PM_FXU0_FIN_GRP191 : (Group 191 pm_hpm5) FXU0 produced a result
+event:0X0BF3 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP191 : (Group 191 pm_hpm5) FXU1 produced a result
+
+#Group 192 pm_hpm6, HPM group
+event:0X0C00 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP192 : (Group 192 pm_hpm6) Data loaded from L2
+event:0X0C01 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L21_GRP192 : (Group 192 pm_hpm6) Data loaded from private L2 other core
+event:0X0C02 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L25_MOD_GRP192 : (Group 192 pm_hpm6) Data loaded from L2.5 modified
+event:0X0C03 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L25_SHR_GRP192 : (Group 192 pm_hpm6) Data loaded from L2.5 shared
+
+#Group 193 pm_hpm7, HPM group
+event:0X0C10 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L35_MOD_GRP193 : (Group 193 pm_hpm7) Data loaded from L3.5 modified
+event:0X0C11 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L35_SHR_GRP193 : (Group 193 pm_hpm7) Data loaded from L3.5 shared
+event:0X0C12 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP193 : (Group 193 pm_hpm7) Data loaded from L3
+event:0X0C13 counters:3 um:zero minimum:10000 name:PM_CYC_GRP193 : (Group 193 pm_hpm7) Processor cycles
+
+#Group 194 pm_hpm8, HPM group
+event:0X0C20 counters:0 um:zero minimum:1000 name:PM_FPU_1FLOP_GRP194 : (Group 194 pm_hpm8) FPU executed one flop instruction
+event:0X0C21 counters:1 um:zero minimum:1000 name:PM_FPU_FMA_GRP194 : (Group 194 pm_hpm8) FPU executed multiply-add instruction
+event:0X0C22 counters:2 um:zero minimum:1000 name:PM_FPU_STF_GRP194 : (Group 194 pm_hpm8) FPU executed store instruction
+event:0X0C23 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP194 : (Group 194 pm_hpm8) L1 D cache load misses
+
+#Group 195 pm_hpm9, HPM group
+event:0X0C30 counters:0 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP195 : (Group 195 pm_hpm9) L1 D cache load misses
+event:0X0C31 counters:1 um:zero minimum:10000 name:PM_CYC_GRP195 : (Group 195 pm_hpm9) Processor cycles
+event:0X0C32 counters:2 um:zero minimum:1000 name:PM_LSU_LDF_GRP195 : (Group 195 pm_hpm9) LSU executed Floating Point load instruction
+event:0X0C33 counters:3 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP195 : (Group 195 pm_hpm9) L1 D cache store misses
+
+#Group 196 pm_hpm10, HPM group
+event:0X0C40 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP196 : (Group 196 pm_hpm10) Instructions completed
+event:0X0C41 counters:1 um:zero minimum:1000 name:PM_L2_MISS_GRP196 : (Group 196 pm_hpm10) L2 cache misses
+event:0X0C42 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP196 : (Group 196 pm_hpm10) Instruction fetched missed L3
+event:0X0C43 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP196 : (Group 196 pm_hpm10) Data loaded from private L3 miss
+
+#Group 197 pm_mrk_derat_ref2, Marked DERAT ref
+event:0X0C50 counters:0 um:zero minimum:1000 name:PM_MRK_DERAT_REF_64K_GRP197 : (Group 197 pm_mrk_derat_ref2) Marked DERAT reference for 64K page
+event:0X0C51 counters:1 um:zero minimum:1000 name:PM_MRK_DERAT_REF_4K_GRP197 : (Group 197 pm_mrk_derat_ref2) Marked DERAT reference for 4K page
+event:0X0C52 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP197 : (Group 197 pm_mrk_derat_ref2) Instructions completed
+event:0X0C53 counters:3 um:zero minimum:1000 name:PM_MRK_DERAT_REF_16G_GRP197 : (Group 197 pm_mrk_derat_ref2) Marked DERAT reference for 16G page
+
+#Group 198 pm_mrk_derat_miss2, Marked DERAT miss
+event:0X0C60 counters:0 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_64K_GRP198 : (Group 198 pm_mrk_derat_miss2) Marked DERAT misses for 64K page
+event:0X0C61 counters:1 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_4K_GRP198 : (Group 198 pm_mrk_derat_miss2) Marked DERAT misses for 4K page
+event:0X0C62 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP198 : (Group 198 pm_mrk_derat_miss2) Instructions completed
+event:0X0C63 counters:3 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_16G_GRP198 : (Group 198 pm_mrk_derat_miss2) Marked DERAT misses for 16G page
diff --git a/events/ppc64/power6/unit_masks b/events/ppc64/power6/unit_masks
new file mode 100644
index 0000000..b58835f
--- /dev/null
+++ b/events/ppc64/power6/unit_masks
@@ -0,0 +1,9 @@
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2006.
+# Contributed by Dave Nomura <dcnltc@us.ibm.com>.
+#
+# ppc64 POWER6 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/ppc64/power7/event_mappings b/events/ppc64/power7/event_mappings
new file mode 100644
index 0000000..f8ef5f4
--- /dev/null
+++ b/events/ppc64/power7/event_mappings
@@ -0,0 +1,2020 @@
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2009.
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>.
+#
+#Mapping of event groups to MMCR values
+
+#Group Default
+event:0X001 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
+
+#Group 0 with random sampling
+event:0X002 mmcr0:0X00000000 mmcr1:0XDD0000008486021E mmcra:0X00000001
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X0010 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
+event:0X0011 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
+event:0X0012 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
+event:0X0013 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
+event:0X0014 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
+event:0X0015 mmcr0:0X00000000 mmcr1:0X000000001EF4F202 mmcra:0X00000000
+
+#Group 2 pm_branch1, Branch operations
+event:0X0020 mmcr0:0X00000000 mmcr1:0X44440000A0A2A4AE mmcra:0X00000000
+event:0X0021 mmcr0:0X00000000 mmcr1:0X44440000A0A2A4AE mmcra:0X00000000
+event:0X0022 mmcr0:0X00000000 mmcr1:0X44440000A0A2A4AE mmcra:0X00000000
+event:0X0023 mmcr0:0X00000000 mmcr1:0X44440000A0A2A4AE mmcra:0X00000000
+event:0X0024 mmcr0:0X00000000 mmcr1:0X44440000A0A2A4AE mmcra:0X00000000
+event:0X0025 mmcr0:0X00000000 mmcr1:0X44440000A0A2A4AE mmcra:0X00000000
+
+#Group 3 pm_branch2, Branch operations
+event:0X0030 mmcr0:0X00000000 mmcr1:0X444400009CA8A0A2 mmcra:0X00000000
+event:0X0031 mmcr0:0X00000000 mmcr1:0X444400009CA8A0A2 mmcra:0X00000000
+event:0X0032 mmcr0:0X00000000 mmcr1:0X444400009CA8A0A2 mmcra:0X00000000
+event:0X0033 mmcr0:0X00000000 mmcr1:0X444400009CA8A0A2 mmcra:0X00000000
+event:0X0034 mmcr0:0X00000000 mmcr1:0X444400009CA8A0A2 mmcra:0X00000000
+event:0X0035 mmcr0:0X00000000 mmcr1:0X444400009CA8A0A2 mmcra:0X00000000
+
+#Group 4 pm_branch3, Branch operations
+event:0X0040 mmcr0:0X00000000 mmcr1:0X0040000068049CF6 mmcra:0X00000000
+event:0X0041 mmcr0:0X00000000 mmcr1:0X0040000068049CF6 mmcra:0X00000000
+event:0X0042 mmcr0:0X00000000 mmcr1:0X0040000068049CF6 mmcra:0X00000000
+event:0X0043 mmcr0:0X00000000 mmcr1:0X0040000068049CF6 mmcra:0X00000000
+event:0X0044 mmcr0:0X00000000 mmcr1:0X0040000068049CF6 mmcra:0X00000000
+event:0X0045 mmcr0:0X00000000 mmcr1:0X0040000068049CF6 mmcra:0X00000000
+
+#Group 5 pm_branch4, Branch operations
+event:0X0050 mmcr0:0X00000000 mmcr1:0X44440000AC9EAEA4 mmcra:0X00000000
+event:0X0051 mmcr0:0X00000000 mmcr1:0X44440000AC9EAEA4 mmcra:0X00000000
+event:0X0052 mmcr0:0X00000000 mmcr1:0X44440000AC9EAEA4 mmcra:0X00000000
+event:0X0053 mmcr0:0X00000000 mmcr1:0X44440000AC9EAEA4 mmcra:0X00000000
+event:0X0054 mmcr0:0X00000000 mmcr1:0X44440000AC9EAEA4 mmcra:0X00000000
+event:0X0055 mmcr0:0X00000000 mmcr1:0X44440000AC9EAEA4 mmcra:0X00000000
+
+#Group 6 pm_branch5, Branch operations
+event:0X0060 mmcr0:0X00000000 mmcr1:0X4444000CAAAE9CA8 mmcra:0X00000000
+event:0X0061 mmcr0:0X00000000 mmcr1:0X4444000CAAAE9CA8 mmcra:0X00000000
+event:0X0062 mmcr0:0X00000000 mmcr1:0X4444000CAAAE9CA8 mmcra:0X00000000
+event:0X0063 mmcr0:0X00000000 mmcr1:0X4444000CAAAE9CA8 mmcra:0X00000000
+event:0X0064 mmcr0:0X00000000 mmcr1:0X4444000CAAAE9CA8 mmcra:0X00000000
+event:0X0065 mmcr0:0X00000000 mmcr1:0X4444000CAAAE9CA8 mmcra:0X00000000
+
+#Group 7 pm_branch6, Branch operations
+event:0X0070 mmcr0:0X00000000 mmcr1:0X44440000A0A2A8AA mmcra:0X00000000
+event:0X0071 mmcr0:0X00000000 mmcr1:0X44440000A0A2A8AA mmcra:0X00000000
+event:0X0072 mmcr0:0X00000000 mmcr1:0X44440000A0A2A8AA mmcra:0X00000000
+event:0X0073 mmcr0:0X00000000 mmcr1:0X44440000A0A2A8AA mmcra:0X00000000
+event:0X0074 mmcr0:0X00000000 mmcr1:0X44440000A0A2A8AA mmcra:0X00000000
+event:0X0075 mmcr0:0X00000000 mmcr1:0X44440000A0A2A8AA mmcra:0X00000000
+
+#Group 8 pm_branch7, Branch operations
+event:0X0080 mmcr0:0X00000000 mmcr1:0X44440000ACA8A0A2 mmcra:0X00000000
+event:0X0081 mmcr0:0X00000000 mmcr1:0X44440000ACA8A0A2 mmcra:0X00000000
+event:0X0082 mmcr0:0X00000000 mmcr1:0X44440000ACA8A0A2 mmcra:0X00000000
+event:0X0083 mmcr0:0X00000000 mmcr1:0X44440000ACA8A0A2 mmcra:0X00000000
+event:0X0084 mmcr0:0X00000000 mmcr1:0X44440000ACA8A0A2 mmcra:0X00000000
+event:0X0085 mmcr0:0X00000000 mmcr1:0X44440000ACA8A0A2 mmcra:0X00000000
+
+#Group 9 pm_branch8, Branch operations
+event:0X0090 mmcr0:0X00000000 mmcr1:0X44440000AEA8A0A2 mmcra:0X00000000
+event:0X0091 mmcr0:0X00000000 mmcr1:0X44440000AEA8A0A2 mmcra:0X00000000
+event:0X0092 mmcr0:0X00000000 mmcr1:0X44440000AEA8A0A2 mmcra:0X00000000
+event:0X0093 mmcr0:0X00000000 mmcr1:0X44440000AEA8A0A2 mmcra:0X00000000
+event:0X0094 mmcr0:0X00000000 mmcr1:0X44440000AEA8A0A2 mmcra:0X00000000
+event:0X0095 mmcr0:0X00000000 mmcr1:0X44440000AEA8A0A2 mmcra:0X00000000
+
+#Group 10 pm_branch9, Branch operations
+event:0X00A0 mmcr0:0X00000000 mmcr1:0X44440000A4A8A0A2 mmcra:0X00000000
+event:0X00A1 mmcr0:0X00000000 mmcr1:0X44440000A4A8A0A2 mmcra:0X00000000
+event:0X00A2 mmcr0:0X00000000 mmcr1:0X44440000A4A8A0A2 mmcra:0X00000000
+event:0X00A3 mmcr0:0X00000000 mmcr1:0X44440000A4A8A0A2 mmcra:0X00000000
+event:0X00A4 mmcr0:0X00000000 mmcr1:0X44440000A4A8A0A2 mmcra:0X00000000
+event:0X00A5 mmcr0:0X00000000 mmcr1:0X44440000A4A8A0A2 mmcra:0X00000000
+
+#Group 11 pm_slb_miss, SLB Misses
+event:0X00B0 mmcr0:0X00000000 mmcr1:0X0DDD0001F6909290 mmcra:0X00000000
+event:0X00B1 mmcr0:0X00000000 mmcr1:0X0DDD0001F6909290 mmcra:0X00000000
+event:0X00B2 mmcr0:0X00000000 mmcr1:0X0DDD0001F6909290 mmcra:0X00000000
+event:0X00B3 mmcr0:0X00000000 mmcr1:0X0DDD0001F6909290 mmcra:0X00000000
+event:0X00B4 mmcr0:0X00000000 mmcr1:0X0DDD0001F6909290 mmcra:0X00000000
+event:0X00B5 mmcr0:0X00000000 mmcr1:0X0DDD0001F6909290 mmcra:0X00000000
+
+#Group 12 pm_tlb_miss, TLB Misses
+event:0X00C0 mmcr0:0X00000000 mmcr1:0X500000008866FCFC mmcra:0X00000000
+event:0X00C1 mmcr0:0X00000000 mmcr1:0X500000008866FCFC mmcra:0X00000000
+event:0X00C2 mmcr0:0X00000000 mmcr1:0X500000008866FCFC mmcra:0X00000000
+event:0X00C3 mmcr0:0X00000000 mmcr1:0X500000008866FCFC mmcra:0X00000000
+event:0X00C4 mmcr0:0X00000000 mmcr1:0X500000008866FCFC mmcra:0X00000000
+event:0X00C5 mmcr0:0X00000000 mmcr1:0X500000008866FCFC mmcra:0X00000000
+
+#Group 13 pm_dtlb_miss, DTLB Misses
+event:0X00D0 mmcr0:0X00000000 mmcr1:0XCCCC00005E5E5E5E mmcra:0X00000000
+event:0X00D1 mmcr0:0X00000000 mmcr1:0XCCCC00005E5E5E5E mmcra:0X00000000
+event:0X00D2 mmcr0:0X00000000 mmcr1:0XCCCC00005E5E5E5E mmcra:0X00000000
+event:0X00D3 mmcr0:0X00000000 mmcr1:0XCCCC00005E5E5E5E mmcra:0X00000000
+event:0X00D4 mmcr0:0X00000000 mmcr1:0XCCCC00005E5E5E5E mmcra:0X00000000
+event:0X00D5 mmcr0:0X00000000 mmcr1:0XCCCC00005E5E5E5E mmcra:0X00000000
+
+#Group 14 pm_derat_miss1, DERAT misses
+event:0X00E0 mmcr0:0X00000000 mmcr1:0XCCCC00005C5C5C5C mmcra:0X00000000
+event:0X00E1 mmcr0:0X00000000 mmcr1:0XCCCC00005C5C5C5C mmcra:0X00000000
+event:0X00E2 mmcr0:0X00000000 mmcr1:0XCCCC00005C5C5C5C mmcra:0X00000000
+event:0X00E3 mmcr0:0X00000000 mmcr1:0XCCCC00005C5C5C5C mmcra:0X00000000
+event:0X00E4 mmcr0:0X00000000 mmcr1:0XCCCC00005C5C5C5C mmcra:0X00000000
+event:0X00E5 mmcr0:0X00000000 mmcr1:0XCCCC00005C5C5C5C mmcra:0X00000000
+
+#Group 15 pm_derat_miss2, DERAT misses
+event:0X00F0 mmcr0:0X00000000 mmcr1:0X0CCC0000025C5C5C mmcra:0X00000000
+event:0X00F1 mmcr0:0X00000000 mmcr1:0X0CCC0000025C5C5C mmcra:0X00000000
+event:0X00F2 mmcr0:0X00000000 mmcr1:0X0CCC0000025C5C5C mmcra:0X00000000
+event:0X00F3 mmcr0:0X00000000 mmcr1:0X0CCC0000025C5C5C mmcra:0X00000000
+event:0X00F4 mmcr0:0X00000000 mmcr1:0X0CCC0000025C5C5C mmcra:0X00000000
+event:0X00F5 mmcr0:0X00000000 mmcr1:0X0CCC0000025C5C5C mmcra:0X00000000
+
+#Group 16 pm_misc_miss1, Misses
+event:0X0100 mmcr0:0X00000000 mmcr1:0XD0C0000090FE5AF0 mmcra:0X00000000
+event:0X0101 mmcr0:0X00000000 mmcr1:0XD0C0000090FE5AF0 mmcra:0X00000000
+event:0X0102 mmcr0:0X00000000 mmcr1:0XD0C0000090FE5AF0 mmcra:0X00000000
+event:0X0103 mmcr0:0X00000000 mmcr1:0XD0C0000090FE5AF0 mmcra:0X00000000
+event:0X0104 mmcr0:0X00000000 mmcr1:0XD0C0000090FE5AF0 mmcra:0X00000000
+event:0X0105 mmcr0:0X00000000 mmcr1:0XD0C0000090FE5AF0 mmcra:0X00000000
+
+#Group 17 pm_misc_miss2, Misses
+event:0X0110 mmcr0:0X00000000 mmcr1:0X0CC000001E585AFA mmcra:0X00000000
+event:0X0111 mmcr0:0X00000000 mmcr1:0X0CC000001E585AFA mmcra:0X00000000
+event:0X0112 mmcr0:0X00000000 mmcr1:0X0CC000001E585AFA mmcra:0X00000000
+event:0X0113 mmcr0:0X00000000 mmcr1:0X0CC000001E585AFA mmcra:0X00000000
+event:0X0114 mmcr0:0X00000000 mmcr1:0X0CC000001E585AFA mmcra:0X00000000
+event:0X0115 mmcr0:0X00000000 mmcr1:0X0CC000001E585AFA mmcra:0X00000000
+
+#Group 18 pm_misc_miss3, Misses
+event:0X0120 mmcr0:0X00000000 mmcr1:0X0CCC00001E585A58 mmcra:0X00000000
+event:0X0121 mmcr0:0X00000000 mmcr1:0X0CCC00001E585A58 mmcra:0X00000000
+event:0X0122 mmcr0:0X00000000 mmcr1:0X0CCC00001E585A58 mmcra:0X00000000
+event:0X0123 mmcr0:0X00000000 mmcr1:0X0CCC00001E585A58 mmcra:0X00000000
+event:0X0124 mmcr0:0X00000000 mmcr1:0X0CCC00001E585A58 mmcra:0X00000000
+event:0X0125 mmcr0:0X00000000 mmcr1:0X0CCC00001E585A58 mmcra:0X00000000
+
+#Group 19 pm_misc_miss4, Misses
+event:0X0130 mmcr0:0X00000000 mmcr1:0XD4000000904802FA mmcra:0X00000000
+event:0X0131 mmcr0:0X00000000 mmcr1:0XD4000000904802FA mmcra:0X00000000
+event:0X0132 mmcr0:0X00000000 mmcr1:0XD4000000904802FA mmcra:0X00000000
+event:0X0133 mmcr0:0X00000000 mmcr1:0XD4000000904802FA mmcra:0X00000000
+event:0X0134 mmcr0:0X00000000 mmcr1:0XD4000000904802FA mmcra:0X00000000
+event:0X0135 mmcr0:0X00000000 mmcr1:0XD4000000904802FA mmcra:0X00000000
+
+#Group 20 pm_misc_miss5, Misses
+event:0X0140 mmcr0:0X00000000 mmcr1:0X0DD00000F6909202 mmcra:0X00000000
+event:0X0141 mmcr0:0X00000000 mmcr1:0X0DD00000F6909202 mmcra:0X00000000
+event:0X0142 mmcr0:0X00000000 mmcr1:0X0DD00000F6909202 mmcra:0X00000000
+event:0X0143 mmcr0:0X00000000 mmcr1:0X0DD00000F6909202 mmcra:0X00000000
+event:0X0144 mmcr0:0X00000000 mmcr1:0X0DD00000F6909202 mmcra:0X00000000
+event:0X0145 mmcr0:0X00000000 mmcr1:0X0DD00000F6909202 mmcra:0X00000000
+
+#Group 21 pm_pteg1, PTEG sources
+event:0X0150 mmcr0:0X00000000 mmcr1:0XCECE000050505654 mmcra:0X00000000
+event:0X0151 mmcr0:0X00000000 mmcr1:0XCECE000050505654 mmcra:0X00000000
+event:0X0152 mmcr0:0X00000000 mmcr1:0XCECE000050505654 mmcra:0X00000000
+event:0X0153 mmcr0:0X00000000 mmcr1:0XCECE000050505654 mmcra:0X00000000
+event:0X0154 mmcr0:0X00000000 mmcr1:0XCECE000050505654 mmcra:0X00000000
+event:0X0155 mmcr0:0X00000000 mmcr1:0XCECE000050505654 mmcra:0X00000000
+
+#Group 22 pm_pteg2, PTEG sources
+event:0X0160 mmcr0:0X00000000 mmcr1:0XEEEC000050545454 mmcra:0X00000000
+event:0X0161 mmcr0:0X00000000 mmcr1:0XEEEC000050545454 mmcra:0X00000000
+event:0X0162 mmcr0:0X00000000 mmcr1:0XEEEC000050545454 mmcra:0X00000000
+event:0X0163 mmcr0:0X00000000 mmcr1:0XEEEC000050545454 mmcra:0X00000000
+event:0X0164 mmcr0:0X00000000 mmcr1:0XEEEC000050545454 mmcra:0X00000000
+event:0X0165 mmcr0:0X00000000 mmcr1:0XEEEC000050545454 mmcra:0X00000000
+
+#Group 23 pm_pteg3, PTEG sources
+event:0X0170 mmcr0:0X00000000 mmcr1:0XCCEC000054585252 mmcra:0X00000000
+event:0X0171 mmcr0:0X00000000 mmcr1:0XCCEC000054585252 mmcra:0X00000000
+event:0X0172 mmcr0:0X00000000 mmcr1:0XCCEC000054585252 mmcra:0X00000000
+event:0X0173 mmcr0:0X00000000 mmcr1:0XCCEC000054585252 mmcra:0X00000000
+event:0X0174 mmcr0:0X00000000 mmcr1:0XCCEC000054585252 mmcra:0X00000000
+event:0X0175 mmcr0:0X00000000 mmcr1:0XCCEC000054585252 mmcra:0X00000000
+
+#Group 24 pm_pteg4, PTEG sources
+event:0X0180 mmcr0:0X00000000 mmcr1:0XECCC000052525252 mmcra:0X00000000
+event:0X0181 mmcr0:0X00000000 mmcr1:0XECCC000052525252 mmcra:0X00000000
+event:0X0182 mmcr0:0X00000000 mmcr1:0XECCC000052525252 mmcra:0X00000000
+event:0X0183 mmcr0:0X00000000 mmcr1:0XECCC000052525252 mmcra:0X00000000
+event:0X0184 mmcr0:0X00000000 mmcr1:0XECCC000052525252 mmcra:0X00000000
+event:0X0185 mmcr0:0X00000000 mmcr1:0XECCC000052525252 mmcra:0X00000000
+
+#Group 25 pm_pteg5, PTEG sources
+event:0X0190 mmcr0:0X00000000 mmcr1:0XCCCC000052565456 mmcra:0X00000000
+event:0X0191 mmcr0:0X00000000 mmcr1:0XCCCC000052565456 mmcra:0X00000000
+event:0X0192 mmcr0:0X00000000 mmcr1:0XCCCC000052565456 mmcra:0X00000000
+event:0X0193 mmcr0:0X00000000 mmcr1:0XCCCC000052565456 mmcra:0X00000000
+event:0X0194 mmcr0:0X00000000 mmcr1:0XCCCC000052565456 mmcra:0X00000000
+event:0X0195 mmcr0:0X00000000 mmcr1:0XCCCC000052565456 mmcra:0X00000000
+
+#Group 26 pm_pteg6, PTEG sources
+event:0X01A0 mmcr0:0X00000000 mmcr1:0XEEEE000054525652 mmcra:0X00000000
+event:0X01A1 mmcr0:0X00000000 mmcr1:0XEEEE000054525652 mmcra:0X00000000
+event:0X01A2 mmcr0:0X00000000 mmcr1:0XEEEE000054525652 mmcra:0X00000000
+event:0X01A3 mmcr0:0X00000000 mmcr1:0XEEEE000054525652 mmcra:0X00000000
+event:0X01A4 mmcr0:0X00000000 mmcr1:0XEEEE000054525652 mmcra:0X00000000
+event:0X01A5 mmcr0:0X00000000 mmcr1:0XEEEE000054525652 mmcra:0X00000000
+
+#Group 27 pm_pteg7, PTEG sources
+event:0X01B0 mmcr0:0X00000000 mmcr1:0XEEEE000054565656 mmcra:0X00000000
+event:0X01B1 mmcr0:0X00000000 mmcr1:0XEEEE000054565656 mmcra:0X00000000
+event:0X01B2 mmcr0:0X00000000 mmcr1:0XEEEE000054565656 mmcra:0X00000000
+event:0X01B3 mmcr0:0X00000000 mmcr1:0XEEEE000054565656 mmcra:0X00000000
+event:0X01B4 mmcr0:0X00000000 mmcr1:0XEEEE000054565656 mmcra:0X00000000
+event:0X01B5 mmcr0:0X00000000 mmcr1:0XEEEE000054565656 mmcra:0X00000000
+
+#Group 28 pm_pteg8, PTEG sources
+event:0X01C0 mmcr0:0X00000000 mmcr1:0XEEEE000050585258 mmcra:0X00000000
+event:0X01C1 mmcr0:0X00000000 mmcr1:0XEEEE000050585258 mmcra:0X00000000
+event:0X01C2 mmcr0:0X00000000 mmcr1:0XEEEE000050585258 mmcra:0X00000000
+event:0X01C3 mmcr0:0X00000000 mmcr1:0XEEEE000050585258 mmcra:0X00000000
+event:0X01C4 mmcr0:0X00000000 mmcr1:0XEEEE000050585258 mmcra:0X00000000
+event:0X01C5 mmcr0:0X00000000 mmcr1:0XEEEE000050585258 mmcra:0X00000000
+
+#Group 29 pm_pteg9, PTEG sources
+event:0X01D0 mmcr0:0X00000000 mmcr1:0XCCCC000050505258 mmcra:0X00000000
+event:0X01D1 mmcr0:0X00000000 mmcr1:0XCCCC000050505258 mmcra:0X00000000
+event:0X01D2 mmcr0:0X00000000 mmcr1:0XCCCC000050505258 mmcra:0X00000000
+event:0X01D3 mmcr0:0X00000000 mmcr1:0XCCCC000050505258 mmcra:0X00000000
+event:0X01D4 mmcr0:0X00000000 mmcr1:0XCCCC000050505258 mmcra:0X00000000
+event:0X01D5 mmcr0:0X00000000 mmcr1:0XCCCC000050505258 mmcra:0X00000000
+
+#Group 30 pm_pteg10, PTEG sources
+event:0X01E0 mmcr0:0X00000000 mmcr1:0XCC0000005050021E mmcra:0X00000000
+event:0X01E1 mmcr0:0X00000000 mmcr1:0XCC0000005050021E mmcra:0X00000000
+event:0X01E2 mmcr0:0X00000000 mmcr1:0XCC0000005050021E mmcra:0X00000000
+event:0X01E3 mmcr0:0X00000000 mmcr1:0XCC0000005050021E mmcra:0X00000000
+event:0X01E4 mmcr0:0X00000000 mmcr1:0XCC0000005050021E mmcra:0X00000000
+event:0X01E5 mmcr0:0X00000000 mmcr1:0XCC0000005050021E mmcra:0X00000000
+
+#Group 31 pm_pteg11, PTEG sources
+event:0X01F0 mmcr0:0X00000000 mmcr1:0XCC0C000052540254 mmcra:0X00000000
+event:0X01F1 mmcr0:0X00000000 mmcr1:0XCC0C000052540254 mmcra:0X00000000
+event:0X01F2 mmcr0:0X00000000 mmcr1:0XCC0C000052540254 mmcra:0X00000000
+event:0X01F3 mmcr0:0X00000000 mmcr1:0XCC0C000052540254 mmcra:0X00000000
+event:0X01F4 mmcr0:0X00000000 mmcr1:0XCC0C000052540254 mmcra:0X00000000
+event:0X01F5 mmcr0:0X00000000 mmcr1:0XCC0C000052540254 mmcra:0X00000000
+
+#Group 32 pm_pteg12, PTEG sources
+event:0X0200 mmcr0:0X00000000 mmcr1:0X0CCC000002525252 mmcra:0X00000000
+event:0X0201 mmcr0:0X00000000 mmcr1:0X0CCC000002525252 mmcra:0X00000000
+event:0X0202 mmcr0:0X00000000 mmcr1:0X0CCC000002525252 mmcra:0X00000000
+event:0X0203 mmcr0:0X00000000 mmcr1:0X0CCC000002525252 mmcra:0X00000000
+event:0X0204 mmcr0:0X00000000 mmcr1:0X0CCC000002525252 mmcra:0X00000000
+event:0X0205 mmcr0:0X00000000 mmcr1:0X0CCC000002525252 mmcra:0X00000000
+
+#Group 33 pm_freq1, Frequency events
+event:0X0210 mmcr0:0X00000000 mmcr1:0X000000006E060C0C mmcra:0X00000000
+event:0X0211 mmcr0:0X00000000 mmcr1:0X000000006E060C0C mmcra:0X00000000
+event:0X0212 mmcr0:0X00000000 mmcr1:0X000000006E060C0C mmcra:0X00000000
+event:0X0213 mmcr0:0X00000000 mmcr1:0X000000006E060C0C mmcra:0X00000000
+event:0X0214 mmcr0:0X00000000 mmcr1:0X000000006E060C0C mmcra:0X00000000
+event:0X0215 mmcr0:0X00000000 mmcr1:0X000000006E060C0C mmcra:0X00000000
+
+#Group 34 pm_freq2, Frequency events
+event:0X0220 mmcr0:0X00000000 mmcr1:0X000000006E06060C mmcra:0X00000000
+event:0X0221 mmcr0:0X00000000 mmcr1:0X000000006E06060C mmcra:0X00000000
+event:0X0222 mmcr0:0X00000000 mmcr1:0X000000006E06060C mmcra:0X00000000
+event:0X0223 mmcr0:0X00000000 mmcr1:0X000000006E06060C mmcra:0X00000000
+event:0X0224 mmcr0:0X00000000 mmcr1:0X000000006E06060C mmcra:0X00000000
+event:0X0225 mmcr0:0X00000000 mmcr1:0X000000006E06060C mmcra:0X00000000
+
+#Group 35 pm_L1_ref, L1 references
+event:0X0230 mmcr0:0X00000000 mmcr1:0XCCCD0008808082A6 mmcra:0X00000000
+event:0X0231 mmcr0:0X00000000 mmcr1:0XCCCD0008808082A6 mmcra:0X00000000
+event:0X0232 mmcr0:0X00000000 mmcr1:0XCCCD0008808082A6 mmcra:0X00000000
+event:0X0233 mmcr0:0X00000000 mmcr1:0XCCCD0008808082A6 mmcra:0X00000000
+event:0X0234 mmcr0:0X00000000 mmcr1:0XCCCD0008808082A6 mmcra:0X00000000
+event:0X0235 mmcr0:0X00000000 mmcr1:0XCCCD0008808082A6 mmcra:0X00000000
+
+#Group 36 pm_flush1, Flushes
+event:0X0240 mmcr0:0X00000000 mmcr1:0X22200000888A8CF8 mmcra:0X00000000
+event:0X0241 mmcr0:0X00000000 mmcr1:0X22200000888A8CF8 mmcra:0X00000000
+event:0X0242 mmcr0:0X00000000 mmcr1:0X22200000888A8CF8 mmcra:0X00000000
+event:0X0243 mmcr0:0X00000000 mmcr1:0X22200000888A8CF8 mmcra:0X00000000
+event:0X0244 mmcr0:0X00000000 mmcr1:0X22200000888A8CF8 mmcra:0X00000000
+event:0X0245 mmcr0:0X00000000 mmcr1:0X22200000888A8CF8 mmcra:0X00000000
+
+#Group 37 pm_flush2, Flushes
+event:0X0250 mmcr0:0X00000000 mmcr1:0X222C000086828EAA mmcra:0X00000000
+event:0X0251 mmcr0:0X00000000 mmcr1:0X222C000086828EAA mmcra:0X00000000
+event:0X0252 mmcr0:0X00000000 mmcr1:0X222C000086828EAA mmcra:0X00000000
+event:0X0253 mmcr0:0X00000000 mmcr1:0X222C000086828EAA mmcra:0X00000000
+event:0X0254 mmcr0:0X00000000 mmcr1:0X222C000086828EAA mmcra:0X00000000
+event:0X0255 mmcr0:0X00000000 mmcr1:0X222C000086828EAA mmcra:0X00000000
+
+#Group 38 pm_flush, Flushes
+event:0X0260 mmcr0:0X00000000 mmcr1:0X20000000821E12F8 mmcra:0X00000000
+event:0X0261 mmcr0:0X00000000 mmcr1:0X20000000821E12F8 mmcra:0X00000000
+event:0X0262 mmcr0:0X00000000 mmcr1:0X20000000821E12F8 mmcra:0X00000000
+event:0X0263 mmcr0:0X00000000 mmcr1:0X20000000821E12F8 mmcra:0X00000000
+event:0X0264 mmcr0:0X00000000 mmcr1:0X20000000821E12F8 mmcra:0X00000000
+event:0X0265 mmcr0:0X00000000 mmcr1:0X20000000821E12F8 mmcra:0X00000000
+
+#Group 39 pm_lsu_flush1, LSU Flush
+event:0X0270 mmcr0:0X00000000 mmcr1:0XCCCC000FB0B4B8BC mmcra:0X00000000
+event:0X0271 mmcr0:0X00000000 mmcr1:0XCCCC000FB0B4B8BC mmcra:0X00000000
+event:0X0272 mmcr0:0X00000000 mmcr1:0XCCCC000FB0B4B8BC mmcra:0X00000000
+event:0X0273 mmcr0:0X00000000 mmcr1:0XCCCC000FB0B4B8BC mmcra:0X00000000
+event:0X0274 mmcr0:0X00000000 mmcr1:0XCCCC000FB0B4B8BC mmcra:0X00000000
+event:0X0275 mmcr0:0X00000000 mmcr1:0XCCCC000FB0B4B8BC mmcra:0X00000000
+
+#Group 40 pm_lsu_flush2, LSU Flush ULD
+event:0X0280 mmcr0:0X00000000 mmcr1:0XCCC00008B0B0B2F8 mmcra:0X00000000
+event:0X0281 mmcr0:0X00000000 mmcr1:0XCCC00008B0B0B2F8 mmcra:0X00000000
+event:0X0282 mmcr0:0X00000000 mmcr1:0XCCC00008B0B0B2F8 mmcra:0X00000000
+event:0X0283 mmcr0:0X00000000 mmcr1:0XCCC00008B0B0B2F8 mmcra:0X00000000
+event:0X0284 mmcr0:0X00000000 mmcr1:0XCCC00008B0B0B2F8 mmcra:0X00000000
+event:0X0285 mmcr0:0X00000000 mmcr1:0XCCC00008B0B0B2F8 mmcra:0X00000000
+
+#Group 41 pm_lsu_flush3, LSU Flush UST
+event:0X0290 mmcr0:0X00000000 mmcr1:0XCCC00008B4B4B6F8 mmcra:0X00000000
+event:0X0291 mmcr0:0X00000000 mmcr1:0XCCC00008B4B4B6F8 mmcra:0X00000000
+event:0X0292 mmcr0:0X00000000 mmcr1:0XCCC00008B4B4B6F8 mmcra:0X00000000
+event:0X0293 mmcr0:0X00000000 mmcr1:0XCCC00008B4B4B6F8 mmcra:0X00000000
+event:0X0294 mmcr0:0X00000000 mmcr1:0XCCC00008B4B4B6F8 mmcra:0X00000000
+event:0X0295 mmcr0:0X00000000 mmcr1:0XCCC00008B4B4B6F8 mmcra:0X00000000
+
+#Group 42 pm_lsu_flush4, LSU Flush LRQ
+event:0X02A0 mmcr0:0X00000000 mmcr1:0XCCC00008B8B8BAF8 mmcra:0X00000000
+event:0X02A1 mmcr0:0X00000000 mmcr1:0XCCC00008B8B8BAF8 mmcra:0X00000000
+event:0X02A2 mmcr0:0X00000000 mmcr1:0XCCC00008B8B8BAF8 mmcra:0X00000000
+event:0X02A3 mmcr0:0X00000000 mmcr1:0XCCC00008B8B8BAF8 mmcra:0X00000000
+event:0X02A4 mmcr0:0X00000000 mmcr1:0XCCC00008B8B8BAF8 mmcra:0X00000000
+event:0X02A5 mmcr0:0X00000000 mmcr1:0XCCC00008B8B8BAF8 mmcra:0X00000000
+
+#Group 43 pm_lsu_flush5, LSU Flush SRQ
+event:0X02B0 mmcr0:0X00000000 mmcr1:0XCCC00008BCBCBEF8 mmcra:0X00000000
+event:0X02B1 mmcr0:0X00000000 mmcr1:0XCCC00008BCBCBEF8 mmcra:0X00000000
+event:0X02B2 mmcr0:0X00000000 mmcr1:0XCCC00008BCBCBEF8 mmcra:0X00000000
+event:0X02B3 mmcr0:0X00000000 mmcr1:0XCCC00008BCBCBEF8 mmcra:0X00000000
+event:0X02B4 mmcr0:0X00000000 mmcr1:0XCCC00008BCBCBEF8 mmcra:0X00000000
+event:0X02B5 mmcr0:0X00000000 mmcr1:0XCCC00008BCBCBEF8 mmcra:0X00000000
+
+#Group 44 pm_prefetch, I cache Prefetches
+event:0X02C0 mmcr0:0X00000000 mmcr1:0X04440000188A968E mmcra:0X00000000
+event:0X02C1 mmcr0:0X00000000 mmcr1:0X04440000188A968E mmcra:0X00000000
+event:0X02C2 mmcr0:0X00000000 mmcr1:0X04440000188A968E mmcra:0X00000000
+event:0X02C3 mmcr0:0X00000000 mmcr1:0X04440000188A968E mmcra:0X00000000
+event:0X02C4 mmcr0:0X00000000 mmcr1:0X04440000188A968E mmcra:0X00000000
+event:0X02C5 mmcr0:0X00000000 mmcr1:0X04440000188A968E mmcra:0X00000000
+
+#Group 45 pm_thread_cyc2, Thread cycles
+event:0X02D0 mmcr0:0X00000000 mmcr1:0X00040000120CF4B0 mmcra:0X00000000
+event:0X02D1 mmcr0:0X00000000 mmcr1:0X00040000120CF4B0 mmcra:0X00000000
+event:0X02D2 mmcr0:0X00000000 mmcr1:0X00040000120CF4B0 mmcra:0X00000000
+event:0X02D3 mmcr0:0X00000000 mmcr1:0X00040000120CF4B0 mmcra:0X00000000
+event:0X02D4 mmcr0:0X00000000 mmcr1:0X00040000120CF4B0 mmcra:0X00000000
+event:0X02D5 mmcr0:0X00000000 mmcr1:0X00040000120CF4B0 mmcra:0X00000000
+
+#Group 46 pm_thread_cyc5, Thread cycles
+event:0X02E0 mmcr0:0X00000000 mmcr1:0X44440000B0B2B4B6 mmcra:0X00000000
+event:0X02E1 mmcr0:0X00000000 mmcr1:0X44440000B0B2B4B6 mmcra:0X00000000
+event:0X02E2 mmcr0:0X00000000 mmcr1:0X44440000B0B2B4B6 mmcra:0X00000000
+event:0X02E3 mmcr0:0X00000000 mmcr1:0X44440000B0B2B4B6 mmcra:0X00000000
+event:0X02E4 mmcr0:0X00000000 mmcr1:0X44440000B0B2B4B6 mmcra:0X00000000
+event:0X02E5 mmcr0:0X00000000 mmcr1:0X44440000B0B2B4B6 mmcra:0X00000000
+
+#Group 47 pm_fxu1, FXU events
+event:0X02F0 mmcr0:0X00000000 mmcr1:0X000000000E0E0E0E mmcra:0X00000000
+event:0X02F1 mmcr0:0X00000000 mmcr1:0X000000000E0E0E0E mmcra:0X00000000
+event:0X02F2 mmcr0:0X00000000 mmcr1:0X000000000E0E0E0E mmcra:0X00000000
+event:0X02F3 mmcr0:0X00000000 mmcr1:0X000000000E0E0E0E mmcra:0X00000000
+event:0X02F4 mmcr0:0X00000000 mmcr1:0X000000000E0E0E0E mmcra:0X00000000
+event:0X02F5 mmcr0:0X00000000 mmcr1:0X000000000E0E0E0E mmcra:0X00000000
+
+#Group 48 pm_fxu2, FXU events
+event:0X0300 mmcr0:0X00000000 mmcr1:0X0000000004F40204 mmcra:0X00000000
+event:0X0301 mmcr0:0X00000000 mmcr1:0X0000000004F40204 mmcra:0X00000000
+event:0X0302 mmcr0:0X00000000 mmcr1:0X0000000004F40204 mmcra:0X00000000
+event:0X0303 mmcr0:0X00000000 mmcr1:0X0000000004F40204 mmcra:0X00000000
+event:0X0304 mmcr0:0X00000000 mmcr1:0X0000000004F40204 mmcra:0X00000000
+event:0X0305 mmcr0:0X00000000 mmcr1:0X0000000004F40204 mmcra:0X00000000
+
+#Group 49 pm_fxu3, FXU events
+event:0X0310 mmcr0:0X00000000 mmcr1:0X000000001E0E0E0E mmcra:0X00000000
+event:0X0311 mmcr0:0X00000000 mmcr1:0X000000001E0E0E0E mmcra:0X00000000
+event:0X0312 mmcr0:0X00000000 mmcr1:0X000000001E0E0E0E mmcra:0X00000000
+event:0X0313 mmcr0:0X00000000 mmcr1:0X000000001E0E0E0E mmcra:0X00000000
+event:0X0314 mmcr0:0X00000000 mmcr1:0X000000001E0E0E0E mmcra:0X00000000
+event:0X0315 mmcr0:0X00000000 mmcr1:0X000000001E0E0E0E mmcra:0X00000000
+
+#Group 50 pm_fxu4, FXU events
+event:0X0320 mmcr0:0X00000000 mmcr1:0X000000000E0E1E02 mmcra:0X00000000
+event:0X0321 mmcr0:0X00000000 mmcr1:0X000000000E0E1E02 mmcra:0X00000000
+event:0X0322 mmcr0:0X00000000 mmcr1:0X000000000E0E1E02 mmcra:0X00000000
+event:0X0323 mmcr0:0X00000000 mmcr1:0X000000000E0E1E02 mmcra:0X00000000
+event:0X0324 mmcr0:0X00000000 mmcr1:0X000000000E0E1E02 mmcra:0X00000000
+event:0X0325 mmcr0:0X00000000 mmcr1:0X000000000E0E1E02 mmcra:0X00000000
+
+#Group 51 pm_L2_RCLD, L2 RC load events
+event:0X0330 mmcr0:0X00000000 mmcr1:0X6666400080808082 mmcra:0X00000000
+event:0X0331 mmcr0:0X00000000 mmcr1:0X6666400080808082 mmcra:0X00000000
+event:0X0332 mmcr0:0X00000000 mmcr1:0X6666400080808082 mmcra:0X00000000
+event:0X0333 mmcr0:0X00000000 mmcr1:0X6666400080808082 mmcra:0X00000000
+event:0X0334 mmcr0:0X00000000 mmcr1:0X6666400080808082 mmcra:0X00000000
+event:0X0335 mmcr0:0X00000000 mmcr1:0X6666400080808082 mmcra:0X00000000
+
+#Group 52 pm_L2_RC, RC related events
+event:0X0340 mmcr0:0X00000000 mmcr1:0X60606000821E8002 mmcra:0X00000000
+event:0X0341 mmcr0:0X00000000 mmcr1:0X60606000821E8002 mmcra:0X00000000
+event:0X0342 mmcr0:0X00000000 mmcr1:0X60606000821E8002 mmcra:0X00000000
+event:0X0343 mmcr0:0X00000000 mmcr1:0X60606000821E8002 mmcra:0X00000000
+event:0X0344 mmcr0:0X00000000 mmcr1:0X60606000821E8002 mmcra:0X00000000
+event:0X0345 mmcr0:0X00000000 mmcr1:0X60606000821E8002 mmcra:0X00000000
+
+#Group 53 pm_L2_RCST, L2 RC Store Events
+event:0X0350 mmcr0:0X00000000 mmcr1:0X6666400080808280 mmcra:0X00000000
+event:0X0351 mmcr0:0X00000000 mmcr1:0X6666400080808280 mmcra:0X00000000
+event:0X0352 mmcr0:0X00000000 mmcr1:0X6666400080808280 mmcra:0X00000000
+event:0X0353 mmcr0:0X00000000 mmcr1:0X6666400080808280 mmcra:0X00000000
+event:0X0354 mmcr0:0X00000000 mmcr1:0X6666400080808280 mmcra:0X00000000
+event:0X0355 mmcr0:0X00000000 mmcr1:0X6666400080808280 mmcra:0X00000000
+
+#Group 54 pm_L2_ldst_1, L2 load/store
+event:0X0360 mmcr0:0X00000000 mmcr1:0X660000008280021E mmcra:0X00000000
+event:0X0361 mmcr0:0X00000000 mmcr1:0X660000008280021E mmcra:0X00000000
+event:0X0362 mmcr0:0X00000000 mmcr1:0X660000008280021E mmcra:0X00000000
+event:0X0363 mmcr0:0X00000000 mmcr1:0X660000008280021E mmcra:0X00000000
+event:0X0364 mmcr0:0X00000000 mmcr1:0X660000008280021E mmcra:0X00000000
+event:0X0365 mmcr0:0X00000000 mmcr1:0X660000008280021E mmcra:0X00000000
+
+#Group 55 pm_L2_ldst_2, L2 load/store
+event:0X0370 mmcr0:0X00000000 mmcr1:0X00662000021E8282 mmcra:0X00000000
+event:0X0371 mmcr0:0X00000000 mmcr1:0X00662000021E8282 mmcra:0X00000000
+event:0X0372 mmcr0:0X00000000 mmcr1:0X00662000021E8282 mmcra:0X00000000
+event:0X0373 mmcr0:0X00000000 mmcr1:0X00662000021E8282 mmcra:0X00000000
+event:0X0374 mmcr0:0X00000000 mmcr1:0X00662000021E8282 mmcra:0X00000000
+event:0X0375 mmcr0:0X00000000 mmcr1:0X00662000021E8282 mmcra:0X00000000
+
+#Group 56 pm_L2_ldst_3, L2 load/store
+event:0X0380 mmcr0:0X00000000 mmcr1:0X00662000021E8080 mmcra:0X00000000
+event:0X0381 mmcr0:0X00000000 mmcr1:0X00662000021E8080 mmcra:0X00000000
+event:0X0382 mmcr0:0X00000000 mmcr1:0X00662000021E8080 mmcra:0X00000000
+event:0X0383 mmcr0:0X00000000 mmcr1:0X00662000021E8080 mmcra:0X00000000
+event:0X0384 mmcr0:0X00000000 mmcr1:0X00662000021E8080 mmcra:0X00000000
+event:0X0385 mmcr0:0X00000000 mmcr1:0X00662000021E8080 mmcra:0X00000000
+
+#Group 57 pm_L2_RCSTLD, L2 RC Load/Store Events
+event:0X0390 mmcr0:0X00000000 mmcr1:0X660040008282021E mmcra:0X00000000
+event:0X0391 mmcr0:0X00000000 mmcr1:0X660040008282021E mmcra:0X00000000
+event:0X0392 mmcr0:0X00000000 mmcr1:0X660040008282021E mmcra:0X00000000
+event:0X0393 mmcr0:0X00000000 mmcr1:0X660040008282021E mmcra:0X00000000
+event:0X0394 mmcr0:0X00000000 mmcr1:0X660040008282021E mmcra:0X00000000
+event:0X0395 mmcr0:0X00000000 mmcr1:0X660040008282021E mmcra:0X00000000
+
+#Group 58 pm_nest1, Nest Events
+event:0X03A0 mmcr0:0X00000000 mmcr1:0X0000000081818181 mmcra:0X00000000
+event:0X03A1 mmcr0:0X00000000 mmcr1:0X0000000081818181 mmcra:0X00000000
+event:0X03A2 mmcr0:0X00000000 mmcr1:0X0000000081818181 mmcra:0X00000000
+event:0X03A3 mmcr0:0X00000000 mmcr1:0X0000000081818181 mmcra:0X00000000
+event:0X03A4 mmcr0:0X00000000 mmcr1:0X0000000081818181 mmcra:0X00000000
+event:0X03A5 mmcr0:0X00000000 mmcr1:0X0000000081818181 mmcra:0X00000000
+
+#Group 59 pm_nest2, Nest Events
+event:0X03B0 mmcr0:0X00000000 mmcr1:0X0000000083838383 mmcra:0X00000000
+event:0X03B1 mmcr0:0X00000000 mmcr1:0X0000000083838383 mmcra:0X00000000
+event:0X03B2 mmcr0:0X00000000 mmcr1:0X0000000083838383 mmcra:0X00000000
+event:0X03B3 mmcr0:0X00000000 mmcr1:0X0000000083838383 mmcra:0X00000000
+event:0X03B4 mmcr0:0X00000000 mmcr1:0X0000000083838383 mmcra:0X00000000
+event:0X03B5 mmcr0:0X00000000 mmcr1:0X0000000083838383 mmcra:0X00000000
+
+#Group 60 pm_nest3, Nest Events
+event:0X03C0 mmcr0:0X00000000 mmcr1:0X0000000F81818181 mmcra:0X00000000
+event:0X03C1 mmcr0:0X00000000 mmcr1:0X0000000F81818181 mmcra:0X00000000
+event:0X03C2 mmcr0:0X00000000 mmcr1:0X0000000F81818181 mmcra:0X00000000
+event:0X03C3 mmcr0:0X00000000 mmcr1:0X0000000F81818181 mmcra:0X00000000
+event:0X03C4 mmcr0:0X00000000 mmcr1:0X0000000F81818181 mmcra:0X00000000
+event:0X03C5 mmcr0:0X00000000 mmcr1:0X0000000F81818181 mmcra:0X00000000
+
+#Group 61 pm_nest4, Nest Events
+event:0X03D0 mmcr0:0X00000000 mmcr1:0X0000000F83838383 mmcra:0X00000000
+event:0X03D1 mmcr0:0X00000000 mmcr1:0X0000000F83838383 mmcra:0X00000000
+event:0X03D2 mmcr0:0X00000000 mmcr1:0X0000000F83838383 mmcra:0X00000000
+event:0X03D3 mmcr0:0X00000000 mmcr1:0X0000000F83838383 mmcra:0X00000000
+event:0X03D4 mmcr0:0X00000000 mmcr1:0X0000000F83838383 mmcra:0X00000000
+event:0X03D5 mmcr0:0X00000000 mmcr1:0X0000000F83838383 mmcra:0X00000000
+
+#Group 62 pm_L2_redir_pref, L2 redirect and prefetch
+event:0X03E0 mmcr0:0X00000000 mmcr1:0X44440000989A8882 mmcra:0X00000000
+event:0X03E1 mmcr0:0X00000000 mmcr1:0X44440000989A8882 mmcra:0X00000000
+event:0X03E2 mmcr0:0X00000000 mmcr1:0X44440000989A8882 mmcra:0X00000000
+event:0X03E3 mmcr0:0X00000000 mmcr1:0X44440000989A8882 mmcra:0X00000000
+event:0X03E4 mmcr0:0X00000000 mmcr1:0X44440000989A8882 mmcra:0X00000000
+event:0X03E5 mmcr0:0X00000000 mmcr1:0X44440000989A8882 mmcra:0X00000000
+
+#Group 63 pm_dlatencies1, Data latencies
+event:0X03F0 mmcr0:0X00000000 mmcr1:0XC000000040F2F6F2 mmcra:0X00000000
+event:0X03F1 mmcr0:0X00000000 mmcr1:0XC000000040F2F6F2 mmcra:0X00000000
+event:0X03F2 mmcr0:0X00000000 mmcr1:0XC000000040F2F6F2 mmcra:0X00000000
+event:0X03F3 mmcr0:0X00000000 mmcr1:0XC000000040F2F6F2 mmcra:0X00000000
+event:0X03F4 mmcr0:0X00000000 mmcr1:0XC000000040F2F6F2 mmcra:0X00000000
+event:0X03F5 mmcr0:0X00000000 mmcr1:0XC000000040F2F6F2 mmcra:0X00000000
+
+#Group 64 pm_dlatencies2, Data latencies
+event:0X0400 mmcr0:0X00000000 mmcr1:0XC0000000481EF602 mmcra:0X00000000
+event:0X0401 mmcr0:0X00000000 mmcr1:0XC0000000481EF602 mmcra:0X00000000
+event:0X0402 mmcr0:0X00000000 mmcr1:0XC0000000481EF602 mmcra:0X00000000
+event:0X0403 mmcr0:0X00000000 mmcr1:0XC0000000481EF602 mmcra:0X00000000
+event:0X0404 mmcr0:0X00000000 mmcr1:0XC0000000481EF602 mmcra:0X00000000
+event:0X0405 mmcr0:0X00000000 mmcr1:0XC0000000481EF602 mmcra:0X00000000
+
+#Group 65 pm_dlatencies3, Data latencies
+event:0X0410 mmcr0:0X00000000 mmcr1:0XCC0000004244F602 mmcra:0X00000000
+event:0X0411 mmcr0:0X00000000 mmcr1:0XCC0000004244F602 mmcra:0X00000000
+event:0X0412 mmcr0:0X00000000 mmcr1:0XCC0000004244F602 mmcra:0X00000000
+event:0X0413 mmcr0:0X00000000 mmcr1:0XCC0000004244F602 mmcra:0X00000000
+event:0X0414 mmcr0:0X00000000 mmcr1:0XCC0000004244F602 mmcra:0X00000000
+event:0X0415 mmcr0:0X00000000 mmcr1:0XCC0000004244F602 mmcra:0X00000000
+
+#Group 66 pm_rejects1, Reject event
+event:0X0420 mmcr0:0X00000000 mmcr1:0X0CCC000164ACAEAC mmcra:0X00000000
+event:0X0421 mmcr0:0X00000000 mmcr1:0X0CCC000164ACAEAC mmcra:0X00000000
+event:0X0422 mmcr0:0X00000000 mmcr1:0X0CCC000164ACAEAC mmcra:0X00000000
+event:0X0423 mmcr0:0X00000000 mmcr1:0X0CCC000164ACAEAC mmcra:0X00000000
+event:0X0424 mmcr0:0X00000000 mmcr1:0X0CCC000164ACAEAC mmcra:0X00000000
+event:0X0425 mmcr0:0X00000000 mmcr1:0X0CCC000164ACAEAC mmcra:0X00000000
+
+#Group 67 pm_rejects2, Reject events
+event:0X0430 mmcr0:0X00000000 mmcr1:0X00C000026464A808 mmcra:0X00000000
+event:0X0431 mmcr0:0X00000000 mmcr1:0X00C000026464A808 mmcra:0X00000000
+event:0X0432 mmcr0:0X00000000 mmcr1:0X00C000026464A808 mmcra:0X00000000
+event:0X0433 mmcr0:0X00000000 mmcr1:0X00C000026464A808 mmcra:0X00000000
+event:0X0434 mmcr0:0X00000000 mmcr1:0X00C000026464A808 mmcra:0X00000000
+event:0X0435 mmcr0:0X00000000 mmcr1:0X00C000026464A808 mmcra:0X00000000
+
+#Group 68 pm_rejects3, Set mispredictions rejects
+event:0X0440 mmcr0:0X00000000 mmcr1:0XCC000008A8A81E02 mmcra:0X00000000
+event:0X0441 mmcr0:0X00000000 mmcr1:0XCC000008A8A81E02 mmcra:0X00000000
+event:0X0442 mmcr0:0X00000000 mmcr1:0XCC000008A8A81E02 mmcra:0X00000000
+event:0X0443 mmcr0:0X00000000 mmcr1:0XCC000008A8A81E02 mmcra:0X00000000
+event:0X0444 mmcr0:0X00000000 mmcr1:0XCC000008A8A81E02 mmcra:0X00000000
+event:0X0445 mmcr0:0X00000000 mmcr1:0XCC000008A8A81E02 mmcra:0X00000000
+
+#Group 69 pm_lsu_reject, LSU Reject Event
+event:0X0450 mmcr0:0X00000000 mmcr1:0XCCC00008A4A4A602 mmcra:0X00000000
+event:0X0451 mmcr0:0X00000000 mmcr1:0XCCC00008A4A4A602 mmcra:0X00000000
+event:0X0452 mmcr0:0X00000000 mmcr1:0XCCC00008A4A4A602 mmcra:0X00000000
+event:0X0453 mmcr0:0X00000000 mmcr1:0XCCC00008A4A4A602 mmcra:0X00000000
+event:0X0454 mmcr0:0X00000000 mmcr1:0XCCC00008A4A4A602 mmcra:0X00000000
+event:0X0455 mmcr0:0X00000000 mmcr1:0XCCC00008A4A4A602 mmcra:0X00000000
+
+#Group 70 pm_lsu_ncld, Non cachable loads
+event:0X0460 mmcr0:0X00000000 mmcr1:0XCCC000088C8C8E02 mmcra:0X00000000
+event:0X0461 mmcr0:0X00000000 mmcr1:0XCCC000088C8C8E02 mmcra:0X00000000
+event:0X0462 mmcr0:0X00000000 mmcr1:0XCCC000088C8C8E02 mmcra:0X00000000
+event:0X0463 mmcr0:0X00000000 mmcr1:0XCCC000088C8C8E02 mmcra:0X00000000
+event:0X0464 mmcr0:0X00000000 mmcr1:0XCCC000088C8C8E02 mmcra:0X00000000
+event:0X0465 mmcr0:0X00000000 mmcr1:0XCCC000088C8C8E02 mmcra:0X00000000
+
+#Group 71 pm_gct1, GCT events
+event:0X0470 mmcr0:0X00000000 mmcr1:0X00400000F808861E mmcra:0X00000000
+event:0X0471 mmcr0:0X00000000 mmcr1:0X00400000F808861E mmcra:0X00000000
+event:0X0472 mmcr0:0X00000000 mmcr1:0X00400000F808861E mmcra:0X00000000
+event:0X0473 mmcr0:0X00000000 mmcr1:0X00400000F808861E mmcra:0X00000000
+event:0X0474 mmcr0:0X00000000 mmcr1:0X00400000F808861E mmcra:0X00000000
+event:0X0475 mmcr0:0X00000000 mmcr1:0X00400000F808861E mmcra:0X00000000
+
+#Group 72 pm_gct2, GCT Events
+event:0X0480 mmcr0:0X00000000 mmcr1:0X222200009C9EA0A2 mmcra:0X00000000
+event:0X0481 mmcr0:0X00000000 mmcr1:0X222200009C9EA0A2 mmcra:0X00000000
+event:0X0482 mmcr0:0X00000000 mmcr1:0X222200009C9EA0A2 mmcra:0X00000000
+event:0X0483 mmcr0:0X00000000 mmcr1:0X222200009C9EA0A2 mmcra:0X00000000
+event:0X0484 mmcr0:0X00000000 mmcr1:0X222200009C9EA0A2 mmcra:0X00000000
+event:0X0485 mmcr0:0X00000000 mmcr1:0X222200009C9EA0A2 mmcra:0X00000000
+
+#Group 73 pm_L2_castout_invalidate_1, L2 castout and invalidate events
+event:0X0490 mmcr0:0X00000000 mmcr1:0X660020008082021E mmcra:0X00000000
+event:0X0491 mmcr0:0X00000000 mmcr1:0X660020008082021E mmcra:0X00000000
+event:0X0492 mmcr0:0X00000000 mmcr1:0X660020008082021E mmcra:0X00000000
+event:0X0493 mmcr0:0X00000000 mmcr1:0X660020008082021E mmcra:0X00000000
+event:0X0494 mmcr0:0X00000000 mmcr1:0X660020008082021E mmcra:0X00000000
+event:0X0495 mmcr0:0X00000000 mmcr1:0X660020008082021E mmcra:0X00000000
+
+#Group 74 pm_L2_castout_invalidate_2, L2 castout and invalidate events
+event:0X04A0 mmcr0:0X00000000 mmcr1:0X660020008280021E mmcra:0X00000000
+event:0X04A1 mmcr0:0X00000000 mmcr1:0X660020008280021E mmcra:0X00000000
+event:0X04A2 mmcr0:0X00000000 mmcr1:0X660020008280021E mmcra:0X00000000
+event:0X04A3 mmcr0:0X00000000 mmcr1:0X660020008280021E mmcra:0X00000000
+event:0X04A4 mmcr0:0X00000000 mmcr1:0X660020008280021E mmcra:0X00000000
+event:0X04A5 mmcr0:0X00000000 mmcr1:0X660020008280021E mmcra:0X00000000
+
+#Group 75 pm_disp_held1, Dispatch held conditions
+event:0X04B0 mmcr0:0X00000000 mmcr1:0X00000000060606F2 mmcra:0X00000000
+event:0X04B1 mmcr0:0X00000000 mmcr1:0X00000000060606F2 mmcra:0X00000000
+event:0X04B2 mmcr0:0X00000000 mmcr1:0X00000000060606F2 mmcra:0X00000000
+event:0X04B3 mmcr0:0X00000000 mmcr1:0X00000000060606F2 mmcra:0X00000000
+event:0X04B4 mmcr0:0X00000000 mmcr1:0X00000000060606F2 mmcra:0X00000000
+event:0X04B5 mmcr0:0X00000000 mmcr1:0X00000000060606F2 mmcra:0X00000000
+
+#Group 76 pm_disp_held2, Dispatch held conditions
+event:0X04C0 mmcr0:0X00000000 mmcr1:0X0000000016060606 mmcra:0X00000000
+event:0X04C1 mmcr0:0X00000000 mmcr1:0X0000000016060606 mmcra:0X00000000
+event:0X04C2 mmcr0:0X00000000 mmcr1:0X0000000016060606 mmcra:0X00000000
+event:0X04C3 mmcr0:0X00000000 mmcr1:0X0000000016060606 mmcra:0X00000000
+event:0X04C4 mmcr0:0X00000000 mmcr1:0X0000000016060606 mmcra:0X00000000
+event:0X04C5 mmcr0:0X00000000 mmcr1:0X0000000016060606 mmcra:0X00000000
+
+#Group 77 pm_disp_clb_held, Display CLB held conditions
+event:0X04D0 mmcr0:0X00000000 mmcr1:0X2222000092949698 mmcra:0X00000000
+event:0X04D1 mmcr0:0X00000000 mmcr1:0X2222000092949698 mmcra:0X00000000
+event:0X04D2 mmcr0:0X00000000 mmcr1:0X2222000092949698 mmcra:0X00000000
+event:0X04D3 mmcr0:0X00000000 mmcr1:0X2222000092949698 mmcra:0X00000000
+event:0X04D4 mmcr0:0X00000000 mmcr1:0X2222000092949698 mmcra:0X00000000
+event:0X04D5 mmcr0:0X00000000 mmcr1:0X2222000092949698 mmcra:0X00000000
+
+#Group 78 pm_power, Power Events
+event:0X04E0 mmcr0:0X00000000 mmcr1:0X000000006E6E6E6E mmcra:0X00000000
+event:0X04E1 mmcr0:0X00000000 mmcr1:0X000000006E6E6E6E mmcra:0X00000000
+event:0X04E2 mmcr0:0X00000000 mmcr1:0X000000006E6E6E6E mmcra:0X00000000
+event:0X04E3 mmcr0:0X00000000 mmcr1:0X000000006E6E6E6E mmcra:0X00000000
+event:0X04E4 mmcr0:0X00000000 mmcr1:0X000000006E6E6E6E mmcra:0X00000000
+event:0X04E5 mmcr0:0X00000000 mmcr1:0X000000006E6E6E6E mmcra:0X00000000
+
+#Group 79 pm_dispatch1, Groups and instructions dispatched
+event:0X04F0 mmcr0:0X00000000 mmcr1:0X00000000F2F20AF2 mmcra:0X00000000
+event:0X04F1 mmcr0:0X00000000 mmcr1:0X00000000F2F20AF2 mmcra:0X00000000
+event:0X04F2 mmcr0:0X00000000 mmcr1:0X00000000F2F20AF2 mmcra:0X00000000
+event:0X04F3 mmcr0:0X00000000 mmcr1:0X00000000F2F20AF2 mmcra:0X00000000
+event:0X04F4 mmcr0:0X00000000 mmcr1:0X00000000F2F20AF2 mmcra:0X00000000
+event:0X04F5 mmcr0:0X00000000 mmcr1:0X00000000F2F20AF2 mmcra:0X00000000
+
+#Group 80 pm_dispatch2, Groups and instructions dispatched
+event:0X0500 mmcr0:0X00000000 mmcr1:0X00000000F21E02F2 mmcra:0X00000000
+event:0X0501 mmcr0:0X00000000 mmcr1:0X00000000F21E02F2 mmcra:0X00000000
+event:0X0502 mmcr0:0X00000000 mmcr1:0X00000000F21E02F2 mmcra:0X00000000
+event:0X0503 mmcr0:0X00000000 mmcr1:0X00000000F21E02F2 mmcra:0X00000000
+event:0X0504 mmcr0:0X00000000 mmcr1:0X00000000F21E02F2 mmcra:0X00000000
+event:0X0505 mmcr0:0X00000000 mmcr1:0X00000000F21E02F2 mmcra:0X00000000
+
+#Group 81 pm_ic, I cache operations
+event:0X0510 mmcr0:0X00000000 mmcr1:0X4444000F888C9098 mmcra:0X00000000
+event:0X0511 mmcr0:0X00000000 mmcr1:0X4444000F888C9098 mmcra:0X00000000
+event:0X0512 mmcr0:0X00000000 mmcr1:0X4444000F888C9098 mmcra:0X00000000
+event:0X0513 mmcr0:0X00000000 mmcr1:0X4444000F888C9098 mmcra:0X00000000
+event:0X0514 mmcr0:0X00000000 mmcr1:0X4444000F888C9098 mmcra:0X00000000
+event:0X0515 mmcr0:0X00000000 mmcr1:0X4444000F888C9098 mmcra:0X00000000
+
+#Group 82 pm_ic_pref_cancel, Instruction pre-fetched cancelled
+event:0X0520 mmcr0:0X00000000 mmcr1:0X4444000190929490 mmcra:0X00000000
+event:0X0521 mmcr0:0X00000000 mmcr1:0X4444000190929490 mmcra:0X00000000
+event:0X0522 mmcr0:0X00000000 mmcr1:0X4444000190929490 mmcra:0X00000000
+event:0X0523 mmcr0:0X00000000 mmcr1:0X4444000190929490 mmcra:0X00000000
+event:0X0524 mmcr0:0X00000000 mmcr1:0X4444000190929490 mmcra:0X00000000
+event:0X0525 mmcr0:0X00000000 mmcr1:0X4444000190929490 mmcra:0X00000000
+
+#Group 83 pm_ic_miss, Icache and Ierat miss events
+event:0X0530 mmcr0:0X00000000 mmcr1:0X00000000F6FC021E mmcra:0X00000000
+event:0X0531 mmcr0:0X00000000 mmcr1:0X00000000F6FC021E mmcra:0X00000000
+event:0X0532 mmcr0:0X00000000 mmcr1:0X00000000F6FC021E mmcra:0X00000000
+event:0X0533 mmcr0:0X00000000 mmcr1:0X00000000F6FC021E mmcra:0X00000000
+event:0X0534 mmcr0:0X00000000 mmcr1:0X00000000F6FC021E mmcra:0X00000000
+event:0X0535 mmcr0:0X00000000 mmcr1:0X00000000F6FC021E mmcra:0X00000000
+
+#Group 84 pm_cpi_stack1, CPI stack breakdown
+event:0X0540 mmcr0:0X00000000 mmcr1:0XC00000004016F618 mmcra:0X00000000
+event:0X0541 mmcr0:0X00000000 mmcr1:0XC00000004016F618 mmcra:0X00000000
+event:0X0542 mmcr0:0X00000000 mmcr1:0XC00000004016F618 mmcra:0X00000000
+event:0X0543 mmcr0:0X00000000 mmcr1:0XC00000004016F618 mmcra:0X00000000
+event:0X0544 mmcr0:0X00000000 mmcr1:0XC00000004016F618 mmcra:0X00000000
+event:0X0545 mmcr0:0X00000000 mmcr1:0XC00000004016F618 mmcra:0X00000000
+
+#Group 85 pm_cpi_stack2, CPI stack breakdown
+event:0X0550 mmcr0:0X00000000 mmcr1:0X000000000E140414 mmcra:0X00000000
+event:0X0551 mmcr0:0X00000000 mmcr1:0X000000000E140414 mmcra:0X00000000
+event:0X0552 mmcr0:0X00000000 mmcr1:0X000000000E140414 mmcra:0X00000000
+event:0X0553 mmcr0:0X00000000 mmcr1:0X000000000E140414 mmcra:0X00000000
+event:0X0554 mmcr0:0X00000000 mmcr1:0X000000000E140414 mmcra:0X00000000
+event:0X0555 mmcr0:0X00000000 mmcr1:0X000000000E140414 mmcra:0X00000000
+
+#Group 86 pm_cpi_stack3, CPI stack breakdown
+event:0X0560 mmcr0:0X00000000 mmcr1:0X0000000026121A16 mmcra:0X00000000
+event:0X0561 mmcr0:0X00000000 mmcr1:0X0000000026121A16 mmcra:0X00000000
+event:0X0562 mmcr0:0X00000000 mmcr1:0X0000000026121A16 mmcra:0X00000000
+event:0X0563 mmcr0:0X00000000 mmcr1:0X0000000026121A16 mmcra:0X00000000
+event:0X0564 mmcr0:0X00000000 mmcr1:0X0000000026121A16 mmcra:0X00000000
+event:0X0565 mmcr0:0X00000000 mmcr1:0X0000000026121A16 mmcra:0X00000000
+
+#Group 87 pm_cpi_stack4, CPI stack breakdown
+event:0X0570 mmcr0:0X00000000 mmcr1:0X00000000F4183E12 mmcra:0X00000000
+event:0X0571 mmcr0:0X00000000 mmcr1:0X00000000F4183E12 mmcra:0X00000000
+event:0X0572 mmcr0:0X00000000 mmcr1:0X00000000F4183E12 mmcra:0X00000000
+event:0X0573 mmcr0:0X00000000 mmcr1:0X00000000F4183E12 mmcra:0X00000000
+event:0X0574 mmcr0:0X00000000 mmcr1:0X00000000F4183E12 mmcra:0X00000000
+event:0X0575 mmcr0:0X00000000 mmcr1:0X00000000F4183E12 mmcra:0X00000000
+
+#Group 88 pm_cpi_stack5, CPI stack breakdown
+event:0X0580 mmcr0:0X00000000 mmcr1:0X00000000281C3F0A mmcra:0X00000000
+event:0X0581 mmcr0:0X00000000 mmcr1:0X00000000281C3F0A mmcra:0X00000000
+event:0X0582 mmcr0:0X00000000 mmcr1:0X00000000281C3F0A mmcra:0X00000000
+event:0X0583 mmcr0:0X00000000 mmcr1:0X00000000281C3F0A mmcra:0X00000000
+event:0X0584 mmcr0:0X00000000 mmcr1:0X00000000281C3F0A mmcra:0X00000000
+event:0X0585 mmcr0:0X00000000 mmcr1:0X00000000281C3F0A mmcra:0X00000000
+
+#Group 89 pm_cpi_stack6, CPI stack breakdown
+event:0X0590 mmcr0:0X00000000 mmcr1:0X000000001C3C021C mmcra:0X00000000
+event:0X0591 mmcr0:0X00000000 mmcr1:0X000000001C3C021C mmcra:0X00000000
+event:0X0592 mmcr0:0X00000000 mmcr1:0X000000001C3C021C mmcra:0X00000000
+event:0X0593 mmcr0:0X00000000 mmcr1:0X000000001C3C021C mmcra:0X00000000
+event:0X0594 mmcr0:0X00000000 mmcr1:0X000000001C3C021C mmcra:0X00000000
+event:0X0595 mmcr0:0X00000000 mmcr1:0X000000001C3C021C mmcra:0X00000000
+
+#Group 90 pm_cpi_stack7, CPI stack breakdown
+event:0X05A0 mmcr0:0X00000000 mmcr1:0X00000000F81A141A mmcra:0X00000000
+event:0X05A1 mmcr0:0X00000000 mmcr1:0X00000000F81A141A mmcra:0X00000000
+event:0X05A2 mmcr0:0X00000000 mmcr1:0X00000000F81A141A mmcra:0X00000000
+event:0X05A3 mmcr0:0X00000000 mmcr1:0X00000000F81A141A mmcra:0X00000000
+event:0X05A4 mmcr0:0X00000000 mmcr1:0X00000000F81A141A mmcra:0X00000000
+event:0X05A5 mmcr0:0X00000000 mmcr1:0X00000000F81A141A mmcra:0X00000000
+
+#Group 91 pm_dsource1, Data source information
+event:0X05B0 mmcr0:0X00000000 mmcr1:0XCCCC000040404242 mmcra:0X00000000
+event:0X05B1 mmcr0:0X00000000 mmcr1:0XCCCC000040404242 mmcra:0X00000000
+event:0X05B2 mmcr0:0X00000000 mmcr1:0XCCCC000040404242 mmcra:0X00000000
+event:0X05B3 mmcr0:0X00000000 mmcr1:0XCCCC000040404242 mmcra:0X00000000
+event:0X05B4 mmcr0:0X00000000 mmcr1:0XCCCC000040404242 mmcra:0X00000000
+event:0X05B5 mmcr0:0X00000000 mmcr1:0XCCCC000040404242 mmcra:0X00000000
+
+#Group 92 pm_dsource2, Data source information
+event:0X05C0 mmcr0:0X00000000 mmcr1:0XCCCC000048464A48 mmcra:0X00000000
+event:0X05C1 mmcr0:0X00000000 mmcr1:0XCCCC000048464A48 mmcra:0X00000000
+event:0X05C2 mmcr0:0X00000000 mmcr1:0XCCCC000048464A48 mmcra:0X00000000
+event:0X05C3 mmcr0:0X00000000 mmcr1:0XCCCC000048464A48 mmcra:0X00000000
+event:0X05C4 mmcr0:0X00000000 mmcr1:0XCCCC000048464A48 mmcra:0X00000000
+event:0X05C5 mmcr0:0X00000000 mmcr1:0XCCCC000048464A48 mmcra:0X00000000
+
+#Group 93 pm_dsource3, Data source information
+event:0X05D0 mmcr0:0X00000000 mmcr1:0XCCCC00004A484648 mmcra:0X00000000
+event:0X05D1 mmcr0:0X00000000 mmcr1:0XCCCC00004A484648 mmcra:0X00000000
+event:0X05D2 mmcr0:0X00000000 mmcr1:0XCCCC00004A484648 mmcra:0X00000000
+event:0X05D3 mmcr0:0X00000000 mmcr1:0XCCCC00004A484648 mmcra:0X00000000
+event:0X05D4 mmcr0:0X00000000 mmcr1:0XCCCC00004A484648 mmcra:0X00000000
+event:0X05D5 mmcr0:0X00000000 mmcr1:0XCCCC00004A484648 mmcra:0X00000000
+
+#Group 94 pm_dsource4, Data source information
+event:0X05E0 mmcr0:0X00000000 mmcr1:0XCCCC000044444C44 mmcra:0X00000000
+event:0X05E1 mmcr0:0X00000000 mmcr1:0XCCCC000044444C44 mmcra:0X00000000
+event:0X05E2 mmcr0:0X00000000 mmcr1:0XCCCC000044444C44 mmcra:0X00000000
+event:0X05E3 mmcr0:0X00000000 mmcr1:0XCCCC000044444C44 mmcra:0X00000000
+event:0X05E4 mmcr0:0X00000000 mmcr1:0XCCCC000044444C44 mmcra:0X00000000
+event:0X05E5 mmcr0:0X00000000 mmcr1:0XCCCC000044444C44 mmcra:0X00000000
+
+#Group 95 pm_dsource5, Data source information
+event:0X05F0 mmcr0:0X00000000 mmcr1:0XCCCC00004E424446 mmcra:0X00000000
+event:0X05F1 mmcr0:0X00000000 mmcr1:0XCCCC00004E424446 mmcra:0X00000000
+event:0X05F2 mmcr0:0X00000000 mmcr1:0XCCCC00004E424446 mmcra:0X00000000
+event:0X05F3 mmcr0:0X00000000 mmcr1:0XCCCC00004E424446 mmcra:0X00000000
+event:0X05F4 mmcr0:0X00000000 mmcr1:0XCCCC00004E424446 mmcra:0X00000000
+event:0X05F5 mmcr0:0X00000000 mmcr1:0XCCCC00004E424446 mmcra:0X00000000
+
+#Group 96 pm_dsource6, Data source information
+event:0X0600 mmcr0:0X00000000 mmcr1:0XCCCC000042444E48 mmcra:0X00000000
+event:0X0601 mmcr0:0X00000000 mmcr1:0XCCCC000042444E48 mmcra:0X00000000
+event:0X0602 mmcr0:0X00000000 mmcr1:0XCCCC000042444E48 mmcra:0X00000000
+event:0X0603 mmcr0:0X00000000 mmcr1:0XCCCC000042444E48 mmcra:0X00000000
+event:0X0604 mmcr0:0X00000000 mmcr1:0XCCCC000042444E48 mmcra:0X00000000
+event:0X0605 mmcr0:0X00000000 mmcr1:0XCCCC000042444E48 mmcra:0X00000000
+
+#Group 97 pm_dsource7, Data source information
+event:0X0610 mmcr0:0X00000000 mmcr1:0XCCCC00004C484C44 mmcra:0X00000000
+event:0X0611 mmcr0:0X00000000 mmcr1:0XCCCC00004C484C44 mmcra:0X00000000
+event:0X0612 mmcr0:0X00000000 mmcr1:0XCCCC00004C484C44 mmcra:0X00000000
+event:0X0613 mmcr0:0X00000000 mmcr1:0XCCCC00004C484C44 mmcra:0X00000000
+event:0X0614 mmcr0:0X00000000 mmcr1:0XCCCC00004C484C44 mmcra:0X00000000
+event:0X0615 mmcr0:0X00000000 mmcr1:0XCCCC00004C484C44 mmcra:0X00000000
+
+#Group 98 pm_dsource8, Data source information
+event:0X0620 mmcr0:0X00000000 mmcr1:0X0C0C00000240FE42 mmcra:0X00000000
+event:0X0621 mmcr0:0X00000000 mmcr1:0X0C0C00000240FE42 mmcra:0X00000000
+event:0X0622 mmcr0:0X00000000 mmcr1:0X0C0C00000240FE42 mmcra:0X00000000
+event:0X0623 mmcr0:0X00000000 mmcr1:0X0C0C00000240FE42 mmcra:0X00000000
+event:0X0624 mmcr0:0X00000000 mmcr1:0X0C0C00000240FE42 mmcra:0X00000000
+event:0X0625 mmcr0:0X00000000 mmcr1:0X0C0C00000240FE42 mmcra:0X00000000
+
+#Group 99 pm_dsource9, Data source information
+event:0X0630 mmcr0:0X00000000 mmcr1:0XC000000040FEF6F0 mmcra:0X00000000
+event:0X0631 mmcr0:0X00000000 mmcr1:0XC000000040FEF6F0 mmcra:0X00000000
+event:0X0632 mmcr0:0X00000000 mmcr1:0XC000000040FEF6F0 mmcra:0X00000000
+event:0X0633 mmcr0:0X00000000 mmcr1:0XC000000040FEF6F0 mmcra:0X00000000
+event:0X0634 mmcr0:0X00000000 mmcr1:0XC000000040FEF6F0 mmcra:0X00000000
+event:0X0635 mmcr0:0X00000000 mmcr1:0XC000000040FEF6F0 mmcra:0X00000000
+
+#Group 100 pm_dsource10, Data source information
+event:0X0640 mmcr0:0X00000000 mmcr1:0XCCCC000042444444 mmcra:0X00000000
+event:0X0641 mmcr0:0X00000000 mmcr1:0XCCCC000042444444 mmcra:0X00000000
+event:0X0642 mmcr0:0X00000000 mmcr1:0XCCCC000042444444 mmcra:0X00000000
+event:0X0643 mmcr0:0X00000000 mmcr1:0XCCCC000042444444 mmcra:0X00000000
+event:0X0644 mmcr0:0X00000000 mmcr1:0XCCCC000042444444 mmcra:0X00000000
+event:0X0645 mmcr0:0X00000000 mmcr1:0XCCCC000042444444 mmcra:0X00000000
+
+#Group 101 pm_dsource11, Data source information
+event:0X0650 mmcr0:0X00000000 mmcr1:0XC000000040FEFEFA mmcra:0X00000000
+event:0X0651 mmcr0:0X00000000 mmcr1:0XC000000040FEFEFA mmcra:0X00000000
+event:0X0652 mmcr0:0X00000000 mmcr1:0XC000000040FEFEFA mmcra:0X00000000
+event:0X0653 mmcr0:0X00000000 mmcr1:0XC000000040FEFEFA mmcra:0X00000000
+event:0X0654 mmcr0:0X00000000 mmcr1:0XC000000040FEFEFA mmcra:0X00000000
+event:0X0655 mmcr0:0X00000000 mmcr1:0XC000000040FEFEFA mmcra:0X00000000
+
+#Group 102 pm_dsource12, Data source information
+event:0X0660 mmcr0:0X00000000 mmcr1:0XCCCC000042424242 mmcra:0X00000000
+event:0X0661 mmcr0:0X00000000 mmcr1:0XCCCC000042424242 mmcra:0X00000000
+event:0X0662 mmcr0:0X00000000 mmcr1:0XCCCC000042424242 mmcra:0X00000000
+event:0X0663 mmcr0:0X00000000 mmcr1:0XCCCC000042424242 mmcra:0X00000000
+event:0X0664 mmcr0:0X00000000 mmcr1:0XCCCC000042424242 mmcra:0X00000000
+event:0X0665 mmcr0:0X00000000 mmcr1:0XCCCC000042424242 mmcra:0X00000000
+
+#Group 103 pm_dsource13, Data source information
+event:0X0670 mmcr0:0X00000000 mmcr1:0XC0CC00005C024444 mmcra:0X00000000
+event:0X0671 mmcr0:0X00000000 mmcr1:0XC0CC00005C024444 mmcra:0X00000000
+event:0X0672 mmcr0:0X00000000 mmcr1:0XC0CC00005C024444 mmcra:0X00000000
+event:0X0673 mmcr0:0X00000000 mmcr1:0XC0CC00005C024444 mmcra:0X00000000
+event:0X0674 mmcr0:0X00000000 mmcr1:0XC0CC00005C024444 mmcra:0X00000000
+event:0X0675 mmcr0:0X00000000 mmcr1:0XC0CC00005C024444 mmcra:0X00000000
+
+#Group 104 pm_dsource14, Data source information
+event:0X0680 mmcr0:0X00000000 mmcr1:0XC0CC00004A024242 mmcra:0X00000000
+event:0X0681 mmcr0:0X00000000 mmcr1:0XC0CC00004A024242 mmcra:0X00000000
+event:0X0682 mmcr0:0X00000000 mmcr1:0XC0CC00004A024242 mmcra:0X00000000
+event:0X0683 mmcr0:0X00000000 mmcr1:0XC0CC00004A024242 mmcra:0X00000000
+event:0X0684 mmcr0:0X00000000 mmcr1:0XC0CC00004A024242 mmcra:0X00000000
+event:0X0685 mmcr0:0X00000000 mmcr1:0XC0CC00004A024242 mmcra:0X00000000
+
+#Group 105 pm_dsource15, Data source information
+event:0X0690 mmcr0:0X00000000 mmcr1:0XC00C00004A02F642 mmcra:0X00000000
+event:0X0691 mmcr0:0X00000000 mmcr1:0XC00C00004A02F642 mmcra:0X00000000
+event:0X0692 mmcr0:0X00000000 mmcr1:0XC00C00004A02F642 mmcra:0X00000000
+event:0X0693 mmcr0:0X00000000 mmcr1:0XC00C00004A02F642 mmcra:0X00000000
+event:0X0694 mmcr0:0X00000000 mmcr1:0XC00C00004A02F642 mmcra:0X00000000
+event:0X0695 mmcr0:0X00000000 mmcr1:0XC00C00004A02F642 mmcra:0X00000000
+
+#Group 106 pm_isource1, Instruction source information
+event:0X06A0 mmcr0:0X00000000 mmcr1:0X4444000040404A48 mmcra:0X00000000
+event:0X06A1 mmcr0:0X00000000 mmcr1:0X4444000040404A48 mmcra:0X00000000
+event:0X06A2 mmcr0:0X00000000 mmcr1:0X4444000040404A48 mmcra:0X00000000
+event:0X06A3 mmcr0:0X00000000 mmcr1:0X4444000040404A48 mmcra:0X00000000
+event:0X06A4 mmcr0:0X00000000 mmcr1:0X4444000040404A48 mmcra:0X00000000
+event:0X06A5 mmcr0:0X00000000 mmcr1:0X4444000040404A48 mmcra:0X00000000
+
+#Group 107 pm_isource2, Instruction source information
+event:0X06B0 mmcr0:0X00000000 mmcr1:0X4444000048424C42 mmcra:0X00000000
+event:0X06B1 mmcr0:0X00000000 mmcr1:0X4444000048424C42 mmcra:0X00000000
+event:0X06B2 mmcr0:0X00000000 mmcr1:0X4444000048424C42 mmcra:0X00000000
+event:0X06B3 mmcr0:0X00000000 mmcr1:0X4444000048424C42 mmcra:0X00000000
+event:0X06B4 mmcr0:0X00000000 mmcr1:0X4444000048424C42 mmcra:0X00000000
+event:0X06B5 mmcr0:0X00000000 mmcr1:0X4444000048424C42 mmcra:0X00000000
+
+#Group 108 pm_isource3, Instruction source information
+event:0X06C0 mmcr0:0X00000000 mmcr1:0X444400004A484444 mmcra:0X00000000
+event:0X06C1 mmcr0:0X00000000 mmcr1:0X444400004A484444 mmcra:0X00000000
+event:0X06C2 mmcr0:0X00000000 mmcr1:0X444400004A484444 mmcra:0X00000000
+event:0X06C3 mmcr0:0X00000000 mmcr1:0X444400004A484444 mmcra:0X00000000
+event:0X06C4 mmcr0:0X00000000 mmcr1:0X444400004A484444 mmcra:0X00000000
+event:0X06C5 mmcr0:0X00000000 mmcr1:0X444400004A484444 mmcra:0X00000000
+
+#Group 109 pm_isource4, Instruction source information
+event:0X06D0 mmcr0:0X00000000 mmcr1:0X4444000044464646 mmcra:0X00000000
+event:0X06D1 mmcr0:0X00000000 mmcr1:0X4444000044464646 mmcra:0X00000000
+event:0X06D2 mmcr0:0X00000000 mmcr1:0X4444000044464646 mmcra:0X00000000
+event:0X06D3 mmcr0:0X00000000 mmcr1:0X4444000044464646 mmcra:0X00000000
+event:0X06D4 mmcr0:0X00000000 mmcr1:0X4444000044464646 mmcra:0X00000000
+event:0X06D5 mmcr0:0X00000000 mmcr1:0X4444000044464646 mmcra:0X00000000
+
+#Group 110 pm_isource5, Instruction source information
+event:0X06E0 mmcr0:0X00000000 mmcr1:0X444400004E444E48 mmcra:0X00000000
+event:0X06E1 mmcr0:0X00000000 mmcr1:0X444400004E444E48 mmcra:0X00000000
+event:0X06E2 mmcr0:0X00000000 mmcr1:0X444400004E444E48 mmcra:0X00000000
+event:0X06E3 mmcr0:0X00000000 mmcr1:0X444400004E444E48 mmcra:0X00000000
+event:0X06E4 mmcr0:0X00000000 mmcr1:0X444400004E444E48 mmcra:0X00000000
+event:0X06E5 mmcr0:0X00000000 mmcr1:0X444400004E444E48 mmcra:0X00000000
+
+#Group 111 pm_isource6, Instruction source information
+event:0X06F0 mmcr0:0X00000000 mmcr1:0X4444000046484A48 mmcra:0X00000000
+event:0X06F1 mmcr0:0X00000000 mmcr1:0X4444000046484A48 mmcra:0X00000000
+event:0X06F2 mmcr0:0X00000000 mmcr1:0X4444000046484A48 mmcra:0X00000000
+event:0X06F3 mmcr0:0X00000000 mmcr1:0X4444000046484A48 mmcra:0X00000000
+event:0X06F4 mmcr0:0X00000000 mmcr1:0X4444000046484A48 mmcra:0X00000000
+event:0X06F5 mmcr0:0X00000000 mmcr1:0X4444000046484A48 mmcra:0X00000000
+
+#Group 112 pm_isource7, Instruction source information
+event:0X0700 mmcr0:0X00000000 mmcr1:0X4444000042444444 mmcra:0X00000000
+event:0X0701 mmcr0:0X00000000 mmcr1:0X4444000042444444 mmcra:0X00000000
+event:0X0702 mmcr0:0X00000000 mmcr1:0X4444000042444444 mmcra:0X00000000
+event:0X0703 mmcr0:0X00000000 mmcr1:0X4444000042444444 mmcra:0X00000000
+event:0X0704 mmcr0:0X00000000 mmcr1:0X4444000042444444 mmcra:0X00000000
+event:0X0705 mmcr0:0X00000000 mmcr1:0X4444000042444444 mmcra:0X00000000
+
+#Group 113 pm_isource8, Instruction source information
+event:0X0710 mmcr0:0X00000000 mmcr1:0X444400004C484A48 mmcra:0X00000000
+event:0X0711 mmcr0:0X00000000 mmcr1:0X444400004C484A48 mmcra:0X00000000
+event:0X0712 mmcr0:0X00000000 mmcr1:0X444400004C484A48 mmcra:0X00000000
+event:0X0713 mmcr0:0X00000000 mmcr1:0X444400004C484A48 mmcra:0X00000000
+event:0X0714 mmcr0:0X00000000 mmcr1:0X444400004C484A48 mmcra:0X00000000
+event:0X0715 mmcr0:0X00000000 mmcr1:0X444400004C484A48 mmcra:0X00000000
+
+#Group 114 pm_isource9, Instruction source information
+event:0X0720 mmcr0:0X00000000 mmcr1:0X4444000046424242 mmcra:0X00000000
+event:0X0721 mmcr0:0X00000000 mmcr1:0X4444000046424242 mmcra:0X00000000
+event:0X0722 mmcr0:0X00000000 mmcr1:0X4444000046424242 mmcra:0X00000000
+event:0X0723 mmcr0:0X00000000 mmcr1:0X4444000046424242 mmcra:0X00000000
+event:0X0724 mmcr0:0X00000000 mmcr1:0X4444000046424242 mmcra:0X00000000
+event:0X0725 mmcr0:0X00000000 mmcr1:0X4444000046424242 mmcra:0X00000000
+
+#Group 115 pm_isource10, Instruction source information
+event:0X0730 mmcr0:0X00000000 mmcr1:0X440000004040021E mmcra:0X00000000
+event:0X0731 mmcr0:0X00000000 mmcr1:0X440000004040021E mmcra:0X00000000
+event:0X0732 mmcr0:0X00000000 mmcr1:0X440000004040021E mmcra:0X00000000
+event:0X0733 mmcr0:0X00000000 mmcr1:0X440000004040021E mmcra:0X00000000
+event:0X0734 mmcr0:0X00000000 mmcr1:0X440000004040021E mmcra:0X00000000
+event:0X0735 mmcr0:0X00000000 mmcr1:0X440000004040021E mmcra:0X00000000
+
+#Group 116 pm_isource11, Instruction source information
+event:0X0740 mmcr0:0X00000000 mmcr1:0X4440000042444A02 mmcra:0X00000000
+event:0X0741 mmcr0:0X00000000 mmcr1:0X4440000042444A02 mmcra:0X00000000
+event:0X0742 mmcr0:0X00000000 mmcr1:0X4440000042444A02 mmcra:0X00000000
+event:0X0743 mmcr0:0X00000000 mmcr1:0X4440000042444A02 mmcra:0X00000000
+event:0X0744 mmcr0:0X00000000 mmcr1:0X4440000042444A02 mmcra:0X00000000
+event:0X0745 mmcr0:0X00000000 mmcr1:0X4440000042444A02 mmcra:0X00000000
+
+#Group 117 pm_isource12, Instruction source information
+event:0X0750 mmcr0:0X00000000 mmcr1:0X004400001E024444 mmcra:0X00000000
+event:0X0751 mmcr0:0X00000000 mmcr1:0X004400001E024444 mmcra:0X00000000
+event:0X0752 mmcr0:0X00000000 mmcr1:0X004400001E024444 mmcra:0X00000000
+event:0X0753 mmcr0:0X00000000 mmcr1:0X004400001E024444 mmcra:0X00000000
+event:0X0754 mmcr0:0X00000000 mmcr1:0X004400001E024444 mmcra:0X00000000
+event:0X0755 mmcr0:0X00000000 mmcr1:0X004400001E024444 mmcra:0X00000000
+
+#Group 118 pm_isource13, Instruction source information
+event:0X0760 mmcr0:0X00000000 mmcr1:0X404400004A024242 mmcra:0X00000000
+event:0X0761 mmcr0:0X00000000 mmcr1:0X404400004A024242 mmcra:0X00000000
+event:0X0762 mmcr0:0X00000000 mmcr1:0X404400004A024242 mmcra:0X00000000
+event:0X0763 mmcr0:0X00000000 mmcr1:0X404400004A024242 mmcra:0X00000000
+event:0X0764 mmcr0:0X00000000 mmcr1:0X404400004A024242 mmcra:0X00000000
+event:0X0765 mmcr0:0X00000000 mmcr1:0X404400004A024242 mmcra:0X00000000
+
+#Group 119 pm_prefetch1, Prefetch events
+event:0X0770 mmcr0:0X00000000 mmcr1:0XDDDD000FA8ACB4B8 mmcra:0X00000000
+event:0X0771 mmcr0:0X00000000 mmcr1:0XDDDD000FA8ACB4B8 mmcra:0X00000000
+event:0X0772 mmcr0:0X00000000 mmcr1:0XDDDD000FA8ACB4B8 mmcra:0X00000000
+event:0X0773 mmcr0:0X00000000 mmcr1:0XDDDD000FA8ACB4B8 mmcra:0X00000000
+event:0X0774 mmcr0:0X00000000 mmcr1:0XDDDD000FA8ACB4B8 mmcra:0X00000000
+event:0X0775 mmcr0:0X00000000 mmcr1:0XDDDD000FA8ACB4B8 mmcra:0X00000000
+
+#Group 120 pm_prefetch2, Prefetch events
+event:0X0780 mmcr0:0X00000000 mmcr1:0XDC00000CBC8066F0 mmcra:0X00000000
+event:0X0781 mmcr0:0X00000000 mmcr1:0XDC00000CBC8066F0 mmcra:0X00000000
+event:0X0782 mmcr0:0X00000000 mmcr1:0XDC00000CBC8066F0 mmcra:0X00000000
+event:0X0783 mmcr0:0X00000000 mmcr1:0XDC00000CBC8066F0 mmcra:0X00000000
+event:0X0784 mmcr0:0X00000000 mmcr1:0XDC00000CBC8066F0 mmcra:0X00000000
+event:0X0785 mmcr0:0X00000000 mmcr1:0XDC00000CBC8066F0 mmcra:0X00000000
+
+#Group 121 pm_vsu0, VSU Execution
+event:0X0790 mmcr0:0X00000000 mmcr1:0XAAAA00008082989A mmcra:0X00000000
+event:0X0791 mmcr0:0X00000000 mmcr1:0XAAAA00008082989A mmcra:0X00000000
+event:0X0792 mmcr0:0X00000000 mmcr1:0XAAAA00008082989A mmcra:0X00000000
+event:0X0793 mmcr0:0X00000000 mmcr1:0XAAAA00008082989A mmcra:0X00000000
+event:0X0794 mmcr0:0X00000000 mmcr1:0XAAAA00008082989A mmcra:0X00000000
+event:0X0795 mmcr0:0X00000000 mmcr1:0XAAAA00008082989A mmcra:0X00000000
+
+#Group 122 pm_vsu1, VSU Execution
+event:0X07A0 mmcr0:0X00000000 mmcr1:0XAAAA00009C9EA0A2 mmcra:0X00000000
+event:0X07A1 mmcr0:0X00000000 mmcr1:0XAAAA00009C9EA0A2 mmcra:0X00000000
+event:0X07A2 mmcr0:0X00000000 mmcr1:0XAAAA00009C9EA0A2 mmcra:0X00000000
+event:0X07A3 mmcr0:0X00000000 mmcr1:0XAAAA00009C9EA0A2 mmcra:0X00000000
+event:0X07A4 mmcr0:0X00000000 mmcr1:0XAAAA00009C9EA0A2 mmcra:0X00000000
+event:0X07A5 mmcr0:0X00000000 mmcr1:0XAAAA00009C9EA0A2 mmcra:0X00000000
+
+#Group 123 pm_vsu2, VSU Execution
+event:0X07B0 mmcr0:0X00000000 mmcr1:0XAAAA000C988C8C8E mmcra:0X00000000
+event:0X07B1 mmcr0:0X00000000 mmcr1:0XAAAA000C988C8C8E mmcra:0X00000000
+event:0X07B2 mmcr0:0X00000000 mmcr1:0XAAAA000C988C8C8E mmcra:0X00000000
+event:0X07B3 mmcr0:0X00000000 mmcr1:0XAAAA000C988C8C8E mmcra:0X00000000
+event:0X07B4 mmcr0:0X00000000 mmcr1:0XAAAA000C988C8C8E mmcra:0X00000000
+event:0X07B5 mmcr0:0X00000000 mmcr1:0XAAAA000C988C8C8E mmcra:0X00000000
+
+#Group 124 pm_vsu3, VSU Execution
+event:0X07C0 mmcr0:0X00000000 mmcr1:0XAAA0000284868402 mmcra:0X00000000
+event:0X07C1 mmcr0:0X00000000 mmcr1:0XAAA0000284868402 mmcra:0X00000000
+event:0X07C2 mmcr0:0X00000000 mmcr1:0XAAA0000284868402 mmcra:0X00000000
+event:0X07C3 mmcr0:0X00000000 mmcr1:0XAAA0000284868402 mmcra:0X00000000
+event:0X07C4 mmcr0:0X00000000 mmcr1:0XAAA0000284868402 mmcra:0X00000000
+event:0X07C5 mmcr0:0X00000000 mmcr1:0XAAA0000284868402 mmcra:0X00000000
+
+#Group 125 pm_vsu4, VSU Execution
+event:0X07D0 mmcr0:0X00000000 mmcr1:0XAAA0000290929002 mmcra:0X00000000
+event:0X07D1 mmcr0:0X00000000 mmcr1:0XAAA0000290929002 mmcra:0X00000000
+event:0X07D2 mmcr0:0X00000000 mmcr1:0XAAA0000290929002 mmcra:0X00000000
+event:0X07D3 mmcr0:0X00000000 mmcr1:0XAAA0000290929002 mmcra:0X00000000
+event:0X07D4 mmcr0:0X00000000 mmcr1:0XAAA0000290929002 mmcra:0X00000000
+event:0X07D5 mmcr0:0X00000000 mmcr1:0XAAA0000290929002 mmcra:0X00000000
+
+#Group 126 pm_vsu5, VSU Execution
+event:0X07E0 mmcr0:0X00000000 mmcr1:0XBBB0000880808202 mmcra:0X00000000
+event:0X07E1 mmcr0:0X00000000 mmcr1:0XBBB0000880808202 mmcra:0X00000000
+event:0X07E2 mmcr0:0X00000000 mmcr1:0XBBB0000880808202 mmcra:0X00000000
+event:0X07E3 mmcr0:0X00000000 mmcr1:0XBBB0000880808202 mmcra:0X00000000
+event:0X07E4 mmcr0:0X00000000 mmcr1:0XBBB0000880808202 mmcra:0X00000000
+event:0X07E5 mmcr0:0X00000000 mmcr1:0XBBB0000880808202 mmcra:0X00000000
+
+#Group 127 pm_vsu6, VSU Execution
+event:0X07F0 mmcr0:0X00000000 mmcr1:0XAAA00008ACACAE02 mmcra:0X00000000
+event:0X07F1 mmcr0:0X00000000 mmcr1:0XAAA00008ACACAE02 mmcra:0X00000000
+event:0X07F2 mmcr0:0X00000000 mmcr1:0XAAA00008ACACAE02 mmcra:0X00000000
+event:0X07F3 mmcr0:0X00000000 mmcr1:0XAAA00008ACACAE02 mmcra:0X00000000
+event:0X07F4 mmcr0:0X00000000 mmcr1:0XAAA00008ACACAE02 mmcra:0X00000000
+event:0X07F5 mmcr0:0X00000000 mmcr1:0XAAA00008ACACAE02 mmcra:0X00000000
+
+#Group 128 pm_vsu7, VSU Execution
+event:0X0800 mmcr0:0X00000000 mmcr1:0XAAA00008BCBCBE02 mmcra:0X00000000
+event:0X0801 mmcr0:0X00000000 mmcr1:0XAAA00008BCBCBE02 mmcra:0X00000000
+event:0X0802 mmcr0:0X00000000 mmcr1:0XAAA00008BCBCBE02 mmcra:0X00000000
+event:0X0803 mmcr0:0X00000000 mmcr1:0XAAA00008BCBCBE02 mmcra:0X00000000
+event:0X0804 mmcr0:0X00000000 mmcr1:0XAAA00008BCBCBE02 mmcra:0X00000000
+event:0X0805 mmcr0:0X00000000 mmcr1:0XAAA00008BCBCBE02 mmcra:0X00000000
+
+#Group 129 pm_vsu8, VSU Execution
+event:0X0810 mmcr0:0X00000000 mmcr1:0XBBB000088C8C8E02 mmcra:0X00000000
+event:0X0811 mmcr0:0X00000000 mmcr1:0XBBB000088C8C8E02 mmcra:0X00000000
+event:0X0812 mmcr0:0X00000000 mmcr1:0XBBB000088C8C8E02 mmcra:0X00000000
+event:0X0813 mmcr0:0X00000000 mmcr1:0XBBB000088C8C8E02 mmcra:0X00000000
+event:0X0814 mmcr0:0X00000000 mmcr1:0XBBB000088C8C8E02 mmcra:0X00000000
+event:0X0815 mmcr0:0X00000000 mmcr1:0XBBB000088C8C8E02 mmcra:0X00000000
+
+#Group 130 pm_vsu9, VSU Execution
+event:0X0820 mmcr0:0X00000000 mmcr1:0XAAAA0008A8A8AAA4 mmcra:0X00000000
+event:0X0821 mmcr0:0X00000000 mmcr1:0XAAAA0008A8A8AAA4 mmcra:0X00000000
+event:0X0822 mmcr0:0X00000000 mmcr1:0XAAAA0008A8A8AAA4 mmcra:0X00000000
+event:0X0823 mmcr0:0X00000000 mmcr1:0XAAAA0008A8A8AAA4 mmcra:0X00000000
+event:0X0824 mmcr0:0X00000000 mmcr1:0XAAAA0008A8A8AAA4 mmcra:0X00000000
+event:0X0825 mmcr0:0X00000000 mmcr1:0XAAAA0008A8A8AAA4 mmcra:0X00000000
+
+#Group 131 pm_vsu10, VSU Execution
+event:0X0830 mmcr0:0X00000000 mmcr1:0XAAA0000888888A02 mmcra:0X00000000
+event:0X0831 mmcr0:0X00000000 mmcr1:0XAAA0000888888A02 mmcra:0X00000000
+event:0X0832 mmcr0:0X00000000 mmcr1:0XAAA0000888888A02 mmcra:0X00000000
+event:0X0833 mmcr0:0X00000000 mmcr1:0XAAA0000888888A02 mmcra:0X00000000
+event:0X0834 mmcr0:0X00000000 mmcr1:0XAAA0000888888A02 mmcra:0X00000000
+event:0X0835 mmcr0:0X00000000 mmcr1:0XAAA0000888888A02 mmcra:0X00000000
+
+#Group 132 pm_vsu11, VSU Execution
+event:0X0840 mmcr0:0X00000000 mmcr1:0XAAA0000894949602 mmcra:0X00000000
+event:0X0841 mmcr0:0X00000000 mmcr1:0XAAA0000894949602 mmcra:0X00000000
+event:0X0842 mmcr0:0X00000000 mmcr1:0XAAA0000894949602 mmcra:0X00000000
+event:0X0843 mmcr0:0X00000000 mmcr1:0XAAA0000894949602 mmcra:0X00000000
+event:0X0844 mmcr0:0X00000000 mmcr1:0XAAA0000894949602 mmcra:0X00000000
+event:0X0845 mmcr0:0X00000000 mmcr1:0XAAA0000894949602 mmcra:0X00000000
+
+#Group 133 pm_vsu12, VSU Execution
+event:0X0850 mmcr0:0X00000000 mmcr1:0XBBB0000888888A02 mmcra:0X00000000
+event:0X0851 mmcr0:0X00000000 mmcr1:0XBBB0000888888A02 mmcra:0X00000000
+event:0X0852 mmcr0:0X00000000 mmcr1:0XBBB0000888888A02 mmcra:0X00000000
+event:0X0853 mmcr0:0X00000000 mmcr1:0XBBB0000888888A02 mmcra:0X00000000
+event:0X0854 mmcr0:0X00000000 mmcr1:0XBBB0000888888A02 mmcra:0X00000000
+event:0X0855 mmcr0:0X00000000 mmcr1:0XBBB0000888888A02 mmcra:0X00000000
+
+#Group 134 pm_vsu13, VSU Execution
+event:0X0860 mmcr0:0X00000000 mmcr1:0XBBB0000884848602 mmcra:0X00000000
+event:0X0861 mmcr0:0X00000000 mmcr1:0XBBB0000884848602 mmcra:0X00000000
+event:0X0862 mmcr0:0X00000000 mmcr1:0XBBB0000884848602 mmcra:0X00000000
+event:0X0863 mmcr0:0X00000000 mmcr1:0XBBB0000884848602 mmcra:0X00000000
+event:0X0864 mmcr0:0X00000000 mmcr1:0XBBB0000884848602 mmcra:0X00000000
+event:0X0865 mmcr0:0X00000000 mmcr1:0XBBB0000884848602 mmcra:0X00000000
+
+#Group 135 pm_vsu14, VSU Execution
+event:0X0870 mmcr0:0X00000000 mmcr1:0XAAAA000F809CA098 mmcra:0X00000000
+event:0X0871 mmcr0:0X00000000 mmcr1:0XAAAA000F809CA098 mmcra:0X00000000
+event:0X0872 mmcr0:0X00000000 mmcr1:0XAAAA000F809CA098 mmcra:0X00000000
+event:0X0873 mmcr0:0X00000000 mmcr1:0XAAAA000F809CA098 mmcra:0X00000000
+event:0X0874 mmcr0:0X00000000 mmcr1:0XAAAA000F809CA098 mmcra:0X00000000
+event:0X0875 mmcr0:0X00000000 mmcr1:0XAAAA000F809CA098 mmcra:0X00000000
+
+#Group 136 pm_vsu15, VSU Execution
+event:0X0880 mmcr0:0X00000000 mmcr1:0XBBB0000890909C02 mmcra:0X00000000
+event:0X0881 mmcr0:0X00000000 mmcr1:0XBBB0000890909C02 mmcra:0X00000000
+event:0X0882 mmcr0:0X00000000 mmcr1:0XBBB0000890909C02 mmcra:0X00000000
+event:0X0883 mmcr0:0X00000000 mmcr1:0XBBB0000890909C02 mmcra:0X00000000
+event:0X0884 mmcr0:0X00000000 mmcr1:0XBBB0000890909C02 mmcra:0X00000000
+event:0X0885 mmcr0:0X00000000 mmcr1:0XBBB0000890909C02 mmcra:0X00000000
+
+#Group 137 pm_vsu16, VSU Execution
+event:0X0890 mmcr0:0X00000000 mmcr1:0XBBBB0008949496A0 mmcra:0X00000000
+event:0X0891 mmcr0:0X00000000 mmcr1:0XBBBB0008949496A0 mmcra:0X00000000
+event:0X0892 mmcr0:0X00000000 mmcr1:0XBBBB0008949496A0 mmcra:0X00000000
+event:0X0893 mmcr0:0X00000000 mmcr1:0XBBBB0008949496A0 mmcra:0X00000000
+event:0X0894 mmcr0:0X00000000 mmcr1:0XBBBB0008949496A0 mmcra:0X00000000
+event:0X0895 mmcr0:0X00000000 mmcr1:0XBBBB0008949496A0 mmcra:0X00000000
+
+#Group 138 pm_vsu17, VSU Execution
+event:0X08A0 mmcr0:0X00000000 mmcr1:0XBBBB0000989A929E mmcra:0X00000000
+event:0X08A1 mmcr0:0X00000000 mmcr1:0XBBBB0000989A929E mmcra:0X00000000
+event:0X08A2 mmcr0:0X00000000 mmcr1:0XBBBB0000989A929E mmcra:0X00000000
+event:0X08A3 mmcr0:0X00000000 mmcr1:0XBBBB0000989A929E mmcra:0X00000000
+event:0X08A4 mmcr0:0X00000000 mmcr1:0XBBBB0000989A929E mmcra:0X00000000
+event:0X08A5 mmcr0:0X00000000 mmcr1:0XBBBB0000989A929E mmcra:0X00000000
+
+#Group 139 pm_vsu18, VSU Execution
+event:0X08B0 mmcr0:0X00000000 mmcr1:0XAAA00008B0B0B202 mmcra:0X00000000
+event:0X08B1 mmcr0:0X00000000 mmcr1:0XAAA00008B0B0B202 mmcra:0X00000000
+event:0X08B2 mmcr0:0X00000000 mmcr1:0XAAA00008B0B0B202 mmcra:0X00000000
+event:0X08B3 mmcr0:0X00000000 mmcr1:0XAAA00008B0B0B202 mmcra:0X00000000
+event:0X08B4 mmcr0:0X00000000 mmcr1:0XAAA00008B0B0B202 mmcra:0X00000000
+event:0X08B5 mmcr0:0X00000000 mmcr1:0XAAA00008B0B0B202 mmcra:0X00000000
+
+#Group 140 pm_vsu19, VSU Execution
+event:0X08C0 mmcr0:0X00000000 mmcr1:0XAAA00008B4B4B602 mmcra:0X00000000
+event:0X08C1 mmcr0:0X00000000 mmcr1:0XAAA00008B4B4B602 mmcra:0X00000000
+event:0X08C2 mmcr0:0X00000000 mmcr1:0XAAA00008B4B4B602 mmcra:0X00000000
+event:0X08C3 mmcr0:0X00000000 mmcr1:0XAAA00008B4B4B602 mmcra:0X00000000
+event:0X08C4 mmcr0:0X00000000 mmcr1:0XAAA00008B4B4B602 mmcra:0X00000000
+event:0X08C5 mmcr0:0X00000000 mmcr1:0XAAA00008B4B4B602 mmcra:0X00000000
+
+#Group 141 pm_vsu20, VSU Execution
+event:0X08D0 mmcr0:0X00000000 mmcr1:0XAAA00008B8B8BA02 mmcra:0X00000000
+event:0X08D1 mmcr0:0X00000000 mmcr1:0XAAA00008B8B8BA02 mmcra:0X00000000
+event:0X08D2 mmcr0:0X00000000 mmcr1:0XAAA00008B8B8BA02 mmcra:0X00000000
+event:0X08D3 mmcr0:0X00000000 mmcr1:0XAAA00008B8B8BA02 mmcra:0X00000000
+event:0X08D4 mmcr0:0X00000000 mmcr1:0XAAA00008B8B8BA02 mmcra:0X00000000
+event:0X08D5 mmcr0:0X00000000 mmcr1:0XAAA00008B8B8BA02 mmcra:0X00000000
+
+#Group 142 pm_vsu21, VSU Execution
+event:0X08E0 mmcr0:0X00000000 mmcr1:0X000A000168F402BC mmcra:0X00000000
+event:0X08E1 mmcr0:0X00000000 mmcr1:0X000A000168F402BC mmcra:0X00000000
+event:0X08E2 mmcr0:0X00000000 mmcr1:0X000A000168F402BC mmcra:0X00000000
+event:0X08E3 mmcr0:0X00000000 mmcr1:0X000A000168F402BC mmcra:0X00000000
+event:0X08E4 mmcr0:0X00000000 mmcr1:0X000A000168F402BC mmcra:0X00000000
+event:0X08E5 mmcr0:0X00000000 mmcr1:0X000A000168F402BC mmcra:0X00000000
+
+#Group 143 pm_vsu22, VSU Execution
+event:0X08F0 mmcr0:0X00000000 mmcr1:0XCBAA000F848C8480 mmcra:0X00000000
+event:0X08F1 mmcr0:0X00000000 mmcr1:0XCBAA000F848C8480 mmcra:0X00000000
+event:0X08F2 mmcr0:0X00000000 mmcr1:0XCBAA000F848C8480 mmcra:0X00000000
+event:0X08F3 mmcr0:0X00000000 mmcr1:0XCBAA000F848C8480 mmcra:0X00000000
+event:0X08F4 mmcr0:0X00000000 mmcr1:0XCBAA000F848C8480 mmcra:0X00000000
+event:0X08F5 mmcr0:0X00000000 mmcr1:0XCBAA000F848C8480 mmcra:0X00000000
+
+#Group 144 pm_vsu23, VSU Execution
+event:0X0900 mmcr0:0X00000000 mmcr1:0XAAAA000F88BC8480 mmcra:0X00000000
+event:0X0901 mmcr0:0X00000000 mmcr1:0XAAAA000F88BC8480 mmcra:0X00000000
+event:0X0902 mmcr0:0X00000000 mmcr1:0XAAAA000F88BC8480 mmcra:0X00000000
+event:0X0903 mmcr0:0X00000000 mmcr1:0XAAAA000F88BC8480 mmcra:0X00000000
+event:0X0904 mmcr0:0X00000000 mmcr1:0XAAAA000F88BC8480 mmcra:0X00000000
+event:0X0905 mmcr0:0X00000000 mmcr1:0XAAAA000F88BC8480 mmcra:0X00000000
+
+#Group 145 pm_vsu24, VSU Execution
+event:0X0910 mmcr0:0X00000000 mmcr1:0X0AAA0007F4BCB880 mmcra:0X00000000
+event:0X0911 mmcr0:0X00000000 mmcr1:0X0AAA0007F4BCB880 mmcra:0X00000000
+event:0X0912 mmcr0:0X00000000 mmcr1:0X0AAA0007F4BCB880 mmcra:0X00000000
+event:0X0913 mmcr0:0X00000000 mmcr1:0X0AAA0007F4BCB880 mmcra:0X00000000
+event:0X0914 mmcr0:0X00000000 mmcr1:0X0AAA0007F4BCB880 mmcra:0X00000000
+event:0X0915 mmcr0:0X00000000 mmcr1:0X0AAA0007F4BCB880 mmcra:0X00000000
+
+#Group 146 pm_vsu25, VSU Execution
+event:0X0920 mmcr0:0X00000000 mmcr1:0XBAAA000F8CBCB4B0 mmcra:0X00000000
+event:0X0921 mmcr0:0X00000000 mmcr1:0XBAAA000F8CBCB4B0 mmcra:0X00000000
+event:0X0922 mmcr0:0X00000000 mmcr1:0XBAAA000F8CBCB4B0 mmcra:0X00000000
+event:0X0923 mmcr0:0X00000000 mmcr1:0XBAAA000F8CBCB4B0 mmcra:0X00000000
+event:0X0924 mmcr0:0X00000000 mmcr1:0XBAAA000F8CBCB4B0 mmcra:0X00000000
+event:0X0925 mmcr0:0X00000000 mmcr1:0XBAAA000F8CBCB4B0 mmcra:0X00000000
+
+#Group 147 pm_lsu1, LSU LMQ SRQ events
+event:0X0930 mmcr0:0X00000000 mmcr1:0XD0000000A43E1C08 mmcra:0X00000000
+event:0X0931 mmcr0:0X00000000 mmcr1:0XD0000000A43E1C08 mmcra:0X00000000
+event:0X0932 mmcr0:0X00000000 mmcr1:0XD0000000A43E1C08 mmcra:0X00000000
+event:0X0933 mmcr0:0X00000000 mmcr1:0XD0000000A43E1C08 mmcra:0X00000000
+event:0X0934 mmcr0:0X00000000 mmcr1:0XD0000000A43E1C08 mmcra:0X00000000
+event:0X0935 mmcr0:0X00000000 mmcr1:0XD0000000A43E1C08 mmcra:0X00000000
+
+#Group 148 pm_lsu2, LSU events
+event:0X0940 mmcr0:0X00000000 mmcr1:0X0C0200006690668E mmcra:0X00000000
+event:0X0941 mmcr0:0X00000000 mmcr1:0X0C0200006690668E mmcra:0X00000000
+event:0X0942 mmcr0:0X00000000 mmcr1:0X0C0200006690668E mmcra:0X00000000
+event:0X0943 mmcr0:0X00000000 mmcr1:0X0C0200006690668E mmcra:0X00000000
+event:0X0944 mmcr0:0X00000000 mmcr1:0X0C0200006690668E mmcra:0X00000000
+event:0X0945 mmcr0:0X00000000 mmcr1:0X0C0200006690668E mmcra:0X00000000
+
+#Group 149 pm_lsu_lmq, LSU LMQ Events
+event:0X0950 mmcr0:0X00000000 mmcr1:0XDDDD0000989AA0A4 mmcra:0X00000000
+event:0X0951 mmcr0:0X00000000 mmcr1:0XDDDD0000989AA0A4 mmcra:0X00000000
+event:0X0952 mmcr0:0X00000000 mmcr1:0XDDDD0000989AA0A4 mmcra:0X00000000
+event:0X0953 mmcr0:0X00000000 mmcr1:0XDDDD0000989AA0A4 mmcra:0X00000000
+event:0X0954 mmcr0:0X00000000 mmcr1:0XDDDD0000989AA0A4 mmcra:0X00000000
+event:0X0955 mmcr0:0X00000000 mmcr1:0XDDDD0000989AA0A4 mmcra:0X00000000
+
+#Group 150 pm_lsu_srq1, Store Request Queue Info
+event:0X0960 mmcr0:0X00000000 mmcr1:0XCCC00008A0A0A202 mmcra:0X00000000
+event:0X0961 mmcr0:0X00000000 mmcr1:0XCCC00008A0A0A202 mmcra:0X00000000
+event:0X0962 mmcr0:0X00000000 mmcr1:0XCCC00008A0A0A202 mmcra:0X00000000
+event:0X0963 mmcr0:0X00000000 mmcr1:0XCCC00008A0A0A202 mmcra:0X00000000
+event:0X0964 mmcr0:0X00000000 mmcr1:0XCCC00008A0A0A202 mmcra:0X00000000
+event:0X0965 mmcr0:0X00000000 mmcr1:0XCCC00008A0A0A202 mmcra:0X00000000
+
+#Group 151 pm_lsu_srq2, Store Request Queue Info
+event:0X0970 mmcr0:0X00000000 mmcr1:0XDDD0000096979C02 mmcra:0X00000000
+event:0X0971 mmcr0:0X00000000 mmcr1:0XDDD0000096979C02 mmcra:0X00000000
+event:0X0972 mmcr0:0X00000000 mmcr1:0XDDD0000096979C02 mmcra:0X00000000
+event:0X0973 mmcr0:0X00000000 mmcr1:0XDDD0000096979C02 mmcra:0X00000000
+event:0X0974 mmcr0:0X00000000 mmcr1:0XDDD0000096979C02 mmcra:0X00000000
+event:0X0975 mmcr0:0X00000000 mmcr1:0XDDD0000096979C02 mmcra:0X00000000
+
+#Group 152 pm_lsu_s0_valid, LSU Events
+event:0X0980 mmcr0:0X00000000 mmcr1:0XDDD000009C9EA002 mmcra:0X00000000
+event:0X0981 mmcr0:0X00000000 mmcr1:0XDDD000009C9EA002 mmcra:0X00000000
+event:0X0982 mmcr0:0X00000000 mmcr1:0XDDD000009C9EA002 mmcra:0X00000000
+event:0X0983 mmcr0:0X00000000 mmcr1:0XDDD000009C9EA002 mmcra:0X00000000
+event:0X0984 mmcr0:0X00000000 mmcr1:0XDDD000009C9EA002 mmcra:0X00000000
+event:0X0985 mmcr0:0X00000000 mmcr1:0XDDD000009C9EA002 mmcra:0X00000000
+
+#Group 153 pm_lsu_s0_alloc, LSU Events
+event:0X0990 mmcr0:0X00000000 mmcr1:0XDDD00000A19F9D02 mmcra:0X00000000
+event:0X0991 mmcr0:0X00000000 mmcr1:0XDDD00000A19F9D02 mmcra:0X00000000
+event:0X0992 mmcr0:0X00000000 mmcr1:0XDDD00000A19F9D02 mmcra:0X00000000
+event:0X0993 mmcr0:0X00000000 mmcr1:0XDDD00000A19F9D02 mmcra:0X00000000
+event:0X0994 mmcr0:0X00000000 mmcr1:0XDDD00000A19F9D02 mmcra:0X00000000
+event:0X0995 mmcr0:0X00000000 mmcr1:0XDDD00000A19F9D02 mmcra:0X00000000
+
+#Group 154 pm_l1_pref, L1 pref Events
+event:0X09A0 mmcr0:0X00000000 mmcr1:0XDDD00008B8B8BA02 mmcra:0X00000000
+event:0X09A1 mmcr0:0X00000000 mmcr1:0XDDD00008B8B8BA02 mmcra:0X00000000
+event:0X09A2 mmcr0:0X00000000 mmcr1:0XDDD00008B8B8BA02 mmcra:0X00000000
+event:0X09A3 mmcr0:0X00000000 mmcr1:0XDDD00008B8B8BA02 mmcra:0X00000000
+event:0X09A4 mmcr0:0X00000000 mmcr1:0XDDD00008B8B8BA02 mmcra:0X00000000
+event:0X09A5 mmcr0:0X00000000 mmcr1:0XDDD00008B8B8BA02 mmcra:0X00000000
+
+#Group 155 pm_l2_guess_1, L2_Guess_events
+event:0X09B0 mmcr0:0X00000000 mmcr1:0X6600800080801E02 mmcra:0X00000000
+event:0X09B1 mmcr0:0X00000000 mmcr1:0X6600800080801E02 mmcra:0X00000000
+event:0X09B2 mmcr0:0X00000000 mmcr1:0X6600800080801E02 mmcra:0X00000000
+event:0X09B3 mmcr0:0X00000000 mmcr1:0X6600800080801E02 mmcra:0X00000000
+event:0X09B4 mmcr0:0X00000000 mmcr1:0X6600800080801E02 mmcra:0X00000000
+event:0X09B5 mmcr0:0X00000000 mmcr1:0X6600800080801E02 mmcra:0X00000000
+
+#Group 156 pm_l2_guess_2, L2_Guess_events
+event:0X09C0 mmcr0:0X00000000 mmcr1:0X6600800082821E02 mmcra:0X00000000
+event:0X09C1 mmcr0:0X00000000 mmcr1:0X6600800082821E02 mmcra:0X00000000
+event:0X09C2 mmcr0:0X00000000 mmcr1:0X6600800082821E02 mmcra:0X00000000
+event:0X09C3 mmcr0:0X00000000 mmcr1:0X6600800082821E02 mmcra:0X00000000
+event:0X09C4 mmcr0:0X00000000 mmcr1:0X6600800082821E02 mmcra:0X00000000
+event:0X09C5 mmcr0:0X00000000 mmcr1:0X6600800082821E02 mmcra:0X00000000
+
+#Group 157 pm_misc1, Misc events
+event:0X09D0 mmcr0:0X00000000 mmcr1:0X04000000F0801602 mmcra:0X00000000
+event:0X09D1 mmcr0:0X00000000 mmcr1:0X04000000F0801602 mmcra:0X00000000
+event:0X09D2 mmcr0:0X00000000 mmcr1:0X04000000F0801602 mmcra:0X00000000
+event:0X09D3 mmcr0:0X00000000 mmcr1:0X04000000F0801602 mmcra:0X00000000
+event:0X09D4 mmcr0:0X00000000 mmcr1:0X04000000F0801602 mmcra:0X00000000
+event:0X09D5 mmcr0:0X00000000 mmcr1:0X04000000F0801602 mmcra:0X00000000
+
+#Group 158 pm_misc2, Misc events
+event:0X09E0 mmcr0:0X00000000 mmcr1:0X2000000080F8F81E mmcra:0X00000000
+event:0X09E1 mmcr0:0X00000000 mmcr1:0X2000000080F8F81E mmcra:0X00000000
+event:0X09E2 mmcr0:0X00000000 mmcr1:0X2000000080F8F81E mmcra:0X00000000
+event:0X09E3 mmcr0:0X00000000 mmcr1:0X2000000080F8F81E mmcra:0X00000000
+event:0X09E4 mmcr0:0X00000000 mmcr1:0X2000000080F8F81E mmcra:0X00000000
+event:0X09E5 mmcr0:0X00000000 mmcr1:0X2000000080F8F81E mmcra:0X00000000
+
+#Group 159 pm_misc3, Misc events
+event:0X09F0 mmcr0:0X00000000 mmcr1:0X00000000F20AF2F2 mmcra:0X00000000
+event:0X09F1 mmcr0:0X00000000 mmcr1:0X00000000F20AF2F2 mmcra:0X00000000
+event:0X09F2 mmcr0:0X00000000 mmcr1:0X00000000F20AF2F2 mmcra:0X00000000
+event:0X09F3 mmcr0:0X00000000 mmcr1:0X00000000F20AF2F2 mmcra:0X00000000
+event:0X09F4 mmcr0:0X00000000 mmcr1:0X00000000F20AF2F2 mmcra:0X00000000
+event:0X09F5 mmcr0:0X00000000 mmcr1:0X00000000F20AF2F2 mmcra:0X00000000
+
+#Group 160 pm_misc4, Misc events
+event:0X0A00 mmcr0:0X00000000 mmcr1:0X000000000C1A1E1C mmcra:0X00000000
+event:0X0A01 mmcr0:0X00000000 mmcr1:0X000000000C1A1E1C mmcra:0X00000000
+event:0X0A02 mmcr0:0X00000000 mmcr1:0X000000000C1A1E1C mmcra:0X00000000
+event:0X0A03 mmcr0:0X00000000 mmcr1:0X000000000C1A1E1C mmcra:0X00000000
+event:0X0A04 mmcr0:0X00000000 mmcr1:0X000000000C1A1E1C mmcra:0X00000000
+event:0X0A05 mmcr0:0X00000000 mmcr1:0X000000000C1A1E1C mmcra:0X00000000
+
+#Group 161 pm_misc5, Misc events
+event:0X0A10 mmcr0:0X00000000 mmcr1:0X044000040AAEA4F6 mmcra:0X00000000
+event:0X0A11 mmcr0:0X00000000 mmcr1:0X044000040AAEA4F6 mmcra:0X00000000
+event:0X0A12 mmcr0:0X00000000 mmcr1:0X044000040AAEA4F6 mmcra:0X00000000
+event:0X0A13 mmcr0:0X00000000 mmcr1:0X044000040AAEA4F6 mmcra:0X00000000
+event:0X0A14 mmcr0:0X00000000 mmcr1:0X044000040AAEA4F6 mmcra:0X00000000
+event:0X0A15 mmcr0:0X00000000 mmcr1:0X044000040AAEA4F6 mmcra:0X00000000
+
+#Group 162 pm_misc6, Misc events
+event:0X0A20 mmcr0:0X00000000 mmcr1:0X444000028C8E8C02 mmcra:0X00000000
+event:0X0A21 mmcr0:0X00000000 mmcr1:0X444000028C8E8C02 mmcra:0X00000000
+event:0X0A22 mmcr0:0X00000000 mmcr1:0X444000028C8E8C02 mmcra:0X00000000
+event:0X0A23 mmcr0:0X00000000 mmcr1:0X444000028C8E8C02 mmcra:0X00000000
+event:0X0A24 mmcr0:0X00000000 mmcr1:0X444000028C8E8C02 mmcra:0X00000000
+event:0X0A25 mmcr0:0X00000000 mmcr1:0X444000028C8E8C02 mmcra:0X00000000
+
+#Group 163 pm_misc7, Misc events
+event:0X0A30 mmcr0:0X00000000 mmcr1:0X00000000380A1E66 mmcra:0X00000000
+event:0X0A31 mmcr0:0X00000000 mmcr1:0X00000000380A1E66 mmcra:0X00000000
+event:0X0A32 mmcr0:0X00000000 mmcr1:0X00000000380A1E66 mmcra:0X00000000
+event:0X0A33 mmcr0:0X00000000 mmcr1:0X00000000380A1E66 mmcra:0X00000000
+event:0X0A34 mmcr0:0X00000000 mmcr1:0X00000000380A1E66 mmcra:0X00000000
+event:0X0A35 mmcr0:0X00000000 mmcr1:0X00000000380A1E66 mmcra:0X00000000
+
+#Group 164 pm_misc8, Misc events
+event:0X0A40 mmcr0:0X00000000 mmcr1:0X40000000A6F8F6F6 mmcra:0X00000000
+event:0X0A41 mmcr0:0X00000000 mmcr1:0X40000000A6F8F6F6 mmcra:0X00000000
+event:0X0A42 mmcr0:0X00000000 mmcr1:0X40000000A6F8F6F6 mmcra:0X00000000
+event:0X0A43 mmcr0:0X00000000 mmcr1:0X40000000A6F8F6F6 mmcra:0X00000000
+event:0X0A44 mmcr0:0X00000000 mmcr1:0X40000000A6F8F6F6 mmcra:0X00000000
+event:0X0A45 mmcr0:0X00000000 mmcr1:0X40000000A6F8F6F6 mmcra:0X00000000
+
+#Group 165 pm_misc9, Misc events
+event:0X0A50 mmcr0:0X00000000 mmcr1:0X22C000008486A8F6 mmcra:0X00000000
+event:0X0A51 mmcr0:0X00000000 mmcr1:0X22C000008486A8F6 mmcra:0X00000000
+event:0X0A52 mmcr0:0X00000000 mmcr1:0X22C000008486A8F6 mmcra:0X00000000
+event:0X0A53 mmcr0:0X00000000 mmcr1:0X22C000008486A8F6 mmcra:0X00000000
+event:0X0A54 mmcr0:0X00000000 mmcr1:0X22C000008486A8F6 mmcra:0X00000000
+event:0X0A55 mmcr0:0X00000000 mmcr1:0X22C000008486A8F6 mmcra:0X00000000
+
+#Group 166 pm_misc10, Misc events
+event:0X0A60 mmcr0:0X00000000 mmcr1:0X0DD400061AA8B884 mmcra:0X00000000
+event:0X0A61 mmcr0:0X00000000 mmcr1:0X0DD400061AA8B884 mmcra:0X00000000
+event:0X0A62 mmcr0:0X00000000 mmcr1:0X0DD400061AA8B884 mmcra:0X00000000
+event:0X0A63 mmcr0:0X00000000 mmcr1:0X0DD400061AA8B884 mmcra:0X00000000
+event:0X0A64 mmcr0:0X00000000 mmcr1:0X0DD400061AA8B884 mmcra:0X00000000
+event:0X0A65 mmcr0:0X00000000 mmcr1:0X0DD400061AA8B884 mmcra:0X00000000
+
+#Group 167 pm_misc11, Misc events
+event:0X0A70 mmcr0:0X00000000 mmcr1:0X00000000F41E0402 mmcra:0X00000000
+event:0X0A71 mmcr0:0X00000000 mmcr1:0X00000000F41E0402 mmcra:0X00000000
+event:0X0A72 mmcr0:0X00000000 mmcr1:0X00000000F41E0402 mmcra:0X00000000
+event:0X0A73 mmcr0:0X00000000 mmcr1:0X00000000F41E0402 mmcra:0X00000000
+event:0X0A74 mmcr0:0X00000000 mmcr1:0X00000000F41E0402 mmcra:0X00000000
+event:0X0A75 mmcr0:0X00000000 mmcr1:0X00000000F41E0402 mmcra:0X00000000
+
+#Group 168 pm_misc_12, Misc Events
+event:0X0A80 mmcr0:0X00000000 mmcr1:0X0000000002F0F8F8 mmcra:0X00000000
+event:0X0A81 mmcr0:0X00000000 mmcr1:0X0000000002F0F8F8 mmcra:0X00000000
+event:0X0A82 mmcr0:0X00000000 mmcr1:0X0000000002F0F8F8 mmcra:0X00000000
+event:0X0A83 mmcr0:0X00000000 mmcr1:0X0000000002F0F8F8 mmcra:0X00000000
+event:0X0A84 mmcr0:0X00000000 mmcr1:0X0000000002F0F8F8 mmcra:0X00000000
+event:0X0A85 mmcr0:0X00000000 mmcr1:0X0000000002F0F8F8 mmcra:0X00000000
+
+#Group 169 pm_misc_13, Misc Events
+event:0X0A90 mmcr0:0X00000000 mmcr1:0X00000000F8F0FCF6 mmcra:0X00000000
+event:0X0A91 mmcr0:0X00000000 mmcr1:0X00000000F8F0FCF6 mmcra:0X00000000
+event:0X0A92 mmcr0:0X00000000 mmcr1:0X00000000F8F0FCF6 mmcra:0X00000000
+event:0X0A93 mmcr0:0X00000000 mmcr1:0X00000000F8F0FCF6 mmcra:0X00000000
+event:0X0A94 mmcr0:0X00000000 mmcr1:0X00000000F8F0FCF6 mmcra:0X00000000
+event:0X0A95 mmcr0:0X00000000 mmcr1:0X00000000F8F0FCF6 mmcra:0X00000000
+
+#Group 170 pm_misc_14, Misc Events
+event:0X0AA0 mmcr0:0X00000000 mmcr1:0X000000001E1E0266 mmcra:0X00000000
+event:0X0AA1 mmcr0:0X00000000 mmcr1:0X000000001E1E0266 mmcra:0X00000000
+event:0X0AA2 mmcr0:0X00000000 mmcr1:0X000000001E1E0266 mmcra:0X00000000
+event:0X0AA3 mmcr0:0X00000000 mmcr1:0X000000001E1E0266 mmcra:0X00000000
+event:0X0AA4 mmcr0:0X00000000 mmcr1:0X000000001E1E0266 mmcra:0X00000000
+event:0X0AA5 mmcr0:0X00000000 mmcr1:0X000000001E1E0266 mmcra:0X00000000
+
+#Group 171 pm_misc_15, Misc Events
+event:0X0AB0 mmcr0:0X00000000 mmcr1:0XD0000000A24AF64A mmcra:0X00000000
+event:0X0AB1 mmcr0:0X00000000 mmcr1:0XD0000000A24AF64A mmcra:0X00000000
+event:0X0AB2 mmcr0:0X00000000 mmcr1:0XD0000000A24AF64A mmcra:0X00000000
+event:0X0AB3 mmcr0:0X00000000 mmcr1:0XD0000000A24AF64A mmcra:0X00000000
+event:0X0AB4 mmcr0:0X00000000 mmcr1:0XD0000000A24AF64A mmcra:0X00000000
+event:0X0AB5 mmcr0:0X00000000 mmcr1:0XD0000000A24AF64A mmcra:0X00000000
+
+#Group 172 pm_misc_16, Misc Events
+event:0X0AC0 mmcr0:0X00000000 mmcr1:0X0CC00000289C9E4C mmcra:0X00000000
+event:0X0AC1 mmcr0:0X00000000 mmcr1:0X0CC00000289C9E4C mmcra:0X00000000
+event:0X0AC2 mmcr0:0X00000000 mmcr1:0X0CC00000289C9E4C mmcra:0X00000000
+event:0X0AC3 mmcr0:0X00000000 mmcr1:0X0CC00000289C9E4C mmcra:0X00000000
+event:0X0AC4 mmcr0:0X00000000 mmcr1:0X0CC00000289C9E4C mmcra:0X00000000
+event:0X0AC5 mmcr0:0X00000000 mmcr1:0X0CC00000289C9E4C mmcra:0X00000000
+
+#Group 173 pm_misc_17, Misc Events
+event:0X0AD0 mmcr0:0X00000000 mmcr1:0X00D0000068F0544E mmcra:0X00000000
+event:0X0AD1 mmcr0:0X00000000 mmcr1:0X00D0000068F0544E mmcra:0X00000000
+event:0X0AD2 mmcr0:0X00000000 mmcr1:0X00D0000068F0544E mmcra:0X00000000
+event:0X0AD3 mmcr0:0X00000000 mmcr1:0X00D0000068F0544E mmcra:0X00000000
+event:0X0AD4 mmcr0:0X00000000 mmcr1:0X00D0000068F0544E mmcra:0X00000000
+event:0X0AD5 mmcr0:0X00000000 mmcr1:0X00D0000068F0544E mmcra:0X00000000
+
+#Group 174 pm_suspend, SUSPENDED events
+event:0X0AE0 mmcr0:0X00000000 mmcr1:0X00D00000001E9402 mmcra:0X00000000
+event:0X0AE1 mmcr0:0X00000000 mmcr1:0X00D00000001E9402 mmcra:0X00000000
+event:0X0AE2 mmcr0:0X00000000 mmcr1:0X00D00000001E9402 mmcra:0X00000000
+event:0X0AE3 mmcr0:0X00000000 mmcr1:0X00D00000001E9402 mmcra:0X00000000
+event:0X0AE4 mmcr0:0X00000000 mmcr1:0X00D00000001E9402 mmcra:0X00000000
+event:0X0AE5 mmcr0:0X00000000 mmcr1:0X00D00000001E9402 mmcra:0X00000000
+
+#Group 175 pm_iops, Internal Operations events
+event:0X0AF0 mmcr0:0X00000000 mmcr1:0X00000000141E1402 mmcra:0X00000000
+event:0X0AF1 mmcr0:0X00000000 mmcr1:0X00000000141E1402 mmcra:0X00000000
+event:0X0AF2 mmcr0:0X00000000 mmcr1:0X00000000141E1402 mmcra:0X00000000
+event:0X0AF3 mmcr0:0X00000000 mmcr1:0X00000000141E1402 mmcra:0X00000000
+event:0X0AF4 mmcr0:0X00000000 mmcr1:0X00000000141E1402 mmcra:0X00000000
+event:0X0AF5 mmcr0:0X00000000 mmcr1:0X00000000141E1402 mmcra:0X00000000
+
+#Group 176 pm_sync, sync
+event:0X0B00 mmcr0:0X00000000 mmcr1:0XD0200000941E9A02 mmcra:0X00000000
+event:0X0B01 mmcr0:0X00000000 mmcr1:0XD0200000941E9A02 mmcra:0X00000000
+event:0X0B02 mmcr0:0X00000000 mmcr1:0XD0200000941E9A02 mmcra:0X00000000
+event:0X0B03 mmcr0:0X00000000 mmcr1:0XD0200000941E9A02 mmcra:0X00000000
+event:0X0B04 mmcr0:0X00000000 mmcr1:0XD0200000941E9A02 mmcra:0X00000000
+event:0X0B05 mmcr0:0X00000000 mmcr1:0XD0200000941E9A02 mmcra:0X00000000
+
+#Group 177 pm_seg, Segment events
+event:0X0B10 mmcr0:0X00000000 mmcr1:0X022200041EA4A4A6 mmcra:0X00000000
+event:0X0B11 mmcr0:0X00000000 mmcr1:0X022200041EA4A4A6 mmcra:0X00000000
+event:0X0B12 mmcr0:0X00000000 mmcr1:0X022200041EA4A4A6 mmcra:0X00000000
+event:0X0B13 mmcr0:0X00000000 mmcr1:0X022200041EA4A4A6 mmcra:0X00000000
+event:0X0B14 mmcr0:0X00000000 mmcr1:0X022200041EA4A4A6 mmcra:0X00000000
+event:0X0B15 mmcr0:0X00000000 mmcr1:0X022200041EA4A4A6 mmcra:0X00000000
+
+#Group 178 pm_l3_hit, L3 Hit Events
+event:0X0B20 mmcr0:0X00000000 mmcr1:0XFFFF000080808082 mmcra:0X00000000
+event:0X0B21 mmcr0:0X00000000 mmcr1:0XFFFF000080808082 mmcra:0X00000000
+event:0X0B22 mmcr0:0X00000000 mmcr1:0XFFFF000080808082 mmcra:0X00000000
+event:0X0B23 mmcr0:0X00000000 mmcr1:0XFFFF000080808082 mmcra:0X00000000
+event:0X0B24 mmcr0:0X00000000 mmcr1:0XFFFF000080808082 mmcra:0X00000000
+event:0X0B25 mmcr0:0X00000000 mmcr1:0XFFFF000080808082 mmcra:0X00000000
+
+#Group 179 pm_shl, Shell Events
+event:0X0B30 mmcr0:0X00000000 mmcr1:0X5555000080828486 mmcra:0X00000000
+event:0X0B31 mmcr0:0X00000000 mmcr1:0X5555000080828486 mmcra:0X00000000
+event:0X0B32 mmcr0:0X00000000 mmcr1:0X5555000080828486 mmcra:0X00000000
+event:0X0B33 mmcr0:0X00000000 mmcr1:0X5555000080828486 mmcra:0X00000000
+event:0X0B34 mmcr0:0X00000000 mmcr1:0X5555000080828486 mmcra:0X00000000
+event:0X0B35 mmcr0:0X00000000 mmcr1:0X5555000080828486 mmcra:0X00000000
+
+#Group 180 pm_l3_pref, L3 Prefetch events
+event:0X0B40 mmcr0:0X00000000 mmcr1:0XDDDD0003ACAEACB8 mmcra:0X00000000
+event:0X0B41 mmcr0:0X00000000 mmcr1:0XDDDD0003ACAEACB8 mmcra:0X00000000
+event:0X0B42 mmcr0:0X00000000 mmcr1:0XDDDD0003ACAEACB8 mmcra:0X00000000
+event:0X0B43 mmcr0:0X00000000 mmcr1:0XDDDD0003ACAEACB8 mmcra:0X00000000
+event:0X0B44 mmcr0:0X00000000 mmcr1:0XDDDD0003ACAEACB8 mmcra:0X00000000
+event:0X0B45 mmcr0:0X00000000 mmcr1:0XDDDD0003ACAEACB8 mmcra:0X00000000
+
+#Group 181 pm_l3, L3 events
+event:0X0B50 mmcr0:0X00000000 mmcr1:0XFFFF000082828280 mmcra:0X00000000
+event:0X0B51 mmcr0:0X00000000 mmcr1:0XFFFF000082828280 mmcra:0X00000000
+event:0X0B52 mmcr0:0X00000000 mmcr1:0XFFFF000082828280 mmcra:0X00000000
+event:0X0B53 mmcr0:0X00000000 mmcr1:0XFFFF000082828280 mmcra:0X00000000
+event:0X0B54 mmcr0:0X00000000 mmcr1:0XFFFF000082828280 mmcra:0X00000000
+event:0X0B55 mmcr0:0X00000000 mmcr1:0XFFFF000082828280 mmcra:0X00000000
+
+#Group 182 pm_streams1, Streams
+event:0X0B60 mmcr0:0X00000000 mmcr1:0X0DDD00041EB4B4B6 mmcra:0X00000000
+event:0X0B61 mmcr0:0X00000000 mmcr1:0X0DDD00041EB4B4B6 mmcra:0X00000000
+event:0X0B62 mmcr0:0X00000000 mmcr1:0X0DDD00041EB4B4B6 mmcra:0X00000000
+event:0X0B63 mmcr0:0X00000000 mmcr1:0X0DDD00041EB4B4B6 mmcra:0X00000000
+event:0X0B64 mmcr0:0X00000000 mmcr1:0X0DDD00041EB4B4B6 mmcra:0X00000000
+event:0X0B65 mmcr0:0X00000000 mmcr1:0X0DDD00041EB4B4B6 mmcra:0X00000000
+
+#Group 183 pm_streams2, Streams
+event:0X0B70 mmcr0:0X00000000 mmcr1:0X0DDD00041EBCBCBE mmcra:0X00000000
+event:0X0B71 mmcr0:0X00000000 mmcr1:0X0DDD00041EBCBCBE mmcra:0X00000000
+event:0X0B72 mmcr0:0X00000000 mmcr1:0X0DDD00041EBCBCBE mmcra:0X00000000
+event:0X0B73 mmcr0:0X00000000 mmcr1:0X0DDD00041EBCBCBE mmcra:0X00000000
+event:0X0B74 mmcr0:0X00000000 mmcr1:0X0DDD00041EBCBCBE mmcra:0X00000000
+event:0X0B75 mmcr0:0X00000000 mmcr1:0X0DDD00041EBCBCBE mmcra:0X00000000
+
+#Group 184 pm_streams3, Streams
+event:0X0B80 mmcr0:0X00000000 mmcr1:0XDDDD0004B0A8A8AA mmcra:0X00000000
+event:0X0B81 mmcr0:0X00000000 mmcr1:0XDDDD0004B0A8A8AA mmcra:0X00000000
+event:0X0B82 mmcr0:0X00000000 mmcr1:0XDDDD0004B0A8A8AA mmcra:0X00000000
+event:0X0B83 mmcr0:0X00000000 mmcr1:0XDDDD0004B0A8A8AA mmcra:0X00000000
+event:0X0B84 mmcr0:0X00000000 mmcr1:0XDDDD0004B0A8A8AA mmcra:0X00000000
+event:0X0B85 mmcr0:0X00000000 mmcr1:0XDDDD0004B0A8A8AA mmcra:0X00000000
+
+#Group 185 pm_larx, LARX
+event:0X0B90 mmcr0:0X00000000 mmcr1:0XCC0C000194961E94 mmcra:0X00000000
+event:0X0B91 mmcr0:0X00000000 mmcr1:0XCC0C000194961E94 mmcra:0X00000000
+event:0X0B92 mmcr0:0X00000000 mmcr1:0XCC0C000194961E94 mmcra:0X00000000
+event:0X0B93 mmcr0:0X00000000 mmcr1:0XCC0C000194961E94 mmcra:0X00000000
+event:0X0B94 mmcr0:0X00000000 mmcr1:0XCC0C000194961E94 mmcra:0X00000000
+event:0X0B95 mmcr0:0X00000000 mmcr1:0XCC0C000194961E94 mmcra:0X00000000
+
+#Group 186 pm_ldf, Floating Point loads
+event:0X0BA0 mmcr0:0X00000000 mmcr1:0X0CCC00041E848486 mmcra:0X00000000
+event:0X0BA1 mmcr0:0X00000000 mmcr1:0X0CCC00041E848486 mmcra:0X00000000
+event:0X0BA2 mmcr0:0X00000000 mmcr1:0X0CCC00041E848486 mmcra:0X00000000
+event:0X0BA3 mmcr0:0X00000000 mmcr1:0X0CCC00041E848486 mmcra:0X00000000
+event:0X0BA4 mmcr0:0X00000000 mmcr1:0X0CCC00041E848486 mmcra:0X00000000
+event:0X0BA5 mmcr0:0X00000000 mmcr1:0X0CCC00041E848486 mmcra:0X00000000
+
+#Group 187 pm_ldx, Vector Load
+event:0X0BB0 mmcr0:0X00000000 mmcr1:0X0CCC00041E88888A mmcra:0X00000000
+event:0X0BB1 mmcr0:0X00000000 mmcr1:0X0CCC00041E88888A mmcra:0X00000000
+event:0X0BB2 mmcr0:0X00000000 mmcr1:0X0CCC00041E88888A mmcra:0X00000000
+event:0X0BB3 mmcr0:0X00000000 mmcr1:0X0CCC00041E88888A mmcra:0X00000000
+event:0X0BB4 mmcr0:0X00000000 mmcr1:0X0CCC00041E88888A mmcra:0X00000000
+event:0X0BB5 mmcr0:0X00000000 mmcr1:0X0CCC00041E88888A mmcra:0X00000000
+
+#Group 188 pm_l2_ld_st, L2 load and store events
+event:0X0BC0 mmcr0:0X00000000 mmcr1:0X66F000008082801E mmcra:0X00000000
+event:0X0BC1 mmcr0:0X00000000 mmcr1:0X66F000008082801E mmcra:0X00000000
+event:0X0BC2 mmcr0:0X00000000 mmcr1:0X66F000008082801E mmcra:0X00000000
+event:0X0BC3 mmcr0:0X00000000 mmcr1:0X66F000008082801E mmcra:0X00000000
+event:0X0BC4 mmcr0:0X00000000 mmcr1:0X66F000008082801E mmcra:0X00000000
+event:0X0BC5 mmcr0:0X00000000 mmcr1:0X66F000008082801E mmcra:0X00000000
+
+#Group 189 pm_stcx, STCX
+event:0X0BD0 mmcr0:0X00000000 mmcr1:0XCCCC000C94AC989A mmcra:0X00000000
+event:0X0BD1 mmcr0:0X00000000 mmcr1:0XCCCC000C94AC989A mmcra:0X00000000
+event:0X0BD2 mmcr0:0X00000000 mmcr1:0XCCCC000C94AC989A mmcra:0X00000000
+event:0X0BD3 mmcr0:0X00000000 mmcr1:0XCCCC000C94AC989A mmcra:0X00000000
+event:0X0BD4 mmcr0:0X00000000 mmcr1:0XCCCC000C94AC989A mmcra:0X00000000
+event:0X0BD5 mmcr0:0X00000000 mmcr1:0XCCCC000C94AC989A mmcra:0X00000000
+
+#Group 190 pm_btac, BTAC
+event:0X0BE0 mmcr0:0X00000000 mmcr1:0X55CC00008A88989A mmcra:0X00000000
+event:0X0BE1 mmcr0:0X00000000 mmcr1:0X55CC00008A88989A mmcra:0X00000000
+event:0X0BE2 mmcr0:0X00000000 mmcr1:0X55CC00008A88989A mmcra:0X00000000
+event:0X0BE3 mmcr0:0X00000000 mmcr1:0X55CC00008A88989A mmcra:0X00000000
+event:0X0BE4 mmcr0:0X00000000 mmcr1:0X55CC00008A88989A mmcra:0X00000000
+event:0X0BE5 mmcr0:0X00000000 mmcr1:0X55CC00008A88989A mmcra:0X00000000
+
+#Group 191 pm_br_bc, Branch BC events
+event:0X0BF0 mmcr0:0X00000000 mmcr1:0X44000000B8BA1E02 mmcra:0X00000000
+event:0X0BF1 mmcr0:0X00000000 mmcr1:0X44000000B8BA1E02 mmcra:0X00000000
+event:0X0BF2 mmcr0:0X00000000 mmcr1:0X44000000B8BA1E02 mmcra:0X00000000
+event:0X0BF3 mmcr0:0X00000000 mmcr1:0X44000000B8BA1E02 mmcra:0X00000000
+event:0X0BF4 mmcr0:0X00000000 mmcr1:0X44000000B8BA1E02 mmcra:0X00000000
+event:0X0BF5 mmcr0:0X00000000 mmcr1:0X44000000B8BA1E02 mmcra:0X00000000
+
+#Group 192 pm_inst_imc, inst imc events
+event:0X0C00 mmcr0:0X00000000 mmcr1:0X00000000F0F21602 mmcra:0X00000000
+event:0X0C01 mmcr0:0X00000000 mmcr1:0X00000000F0F21602 mmcra:0X00000000
+event:0X0C02 mmcr0:0X00000000 mmcr1:0X00000000F0F21602 mmcra:0X00000000
+event:0X0C03 mmcr0:0X00000000 mmcr1:0X00000000F0F21602 mmcra:0X00000000
+event:0X0C04 mmcr0:0X00000000 mmcr1:0X00000000F0F21602 mmcra:0X00000000
+event:0X0C05 mmcr0:0X00000000 mmcr1:0X00000000F0F21602 mmcra:0X00000000
+
+#Group 193 pm_l2_misc1, L2 load/store Miss events
+event:0X0C10 mmcr0:0X00000000 mmcr1:0X6666000C80808280 mmcra:0X00000000
+event:0X0C11 mmcr0:0X00000000 mmcr1:0X6666000C80808280 mmcra:0X00000000
+event:0X0C12 mmcr0:0X00000000 mmcr1:0X6666000C80808280 mmcra:0X00000000
+event:0X0C13 mmcr0:0X00000000 mmcr1:0X6666000C80808280 mmcra:0X00000000
+event:0X0C14 mmcr0:0X00000000 mmcr1:0X6666000C80808280 mmcra:0X00000000
+event:0X0C15 mmcr0:0X00000000 mmcr1:0X6666000C80808280 mmcra:0X00000000
+
+#Group 194 pm_l2_misc2, L2 Events
+event:0X0C20 mmcr0:0X00000000 mmcr1:0X00660000021E8080 mmcra:0X00000000
+event:0X0C21 mmcr0:0X00000000 mmcr1:0X00660000021E8080 mmcra:0X00000000
+event:0X0C22 mmcr0:0X00000000 mmcr1:0X00660000021E8080 mmcra:0X00000000
+event:0X0C23 mmcr0:0X00000000 mmcr1:0X00660000021E8080 mmcra:0X00000000
+event:0X0C24 mmcr0:0X00000000 mmcr1:0X00660000021E8080 mmcra:0X00000000
+event:0X0C25 mmcr0:0X00000000 mmcr1:0X00660000021E8080 mmcra:0X00000000
+
+#Group 195 pm_l2_misc3, L2 Events
+event:0X0C30 mmcr0:0X00000000 mmcr1:0X00608000021E82FA mmcra:0X00000000
+event:0X0C31 mmcr0:0X00000000 mmcr1:0X00608000021E82FA mmcra:0X00000000
+event:0X0C32 mmcr0:0X00000000 mmcr1:0X00608000021E82FA mmcra:0X00000000
+event:0X0C33 mmcr0:0X00000000 mmcr1:0X00608000021E82FA mmcra:0X00000000
+event:0X0C34 mmcr0:0X00000000 mmcr1:0X00608000021E82FA mmcra:0X00000000
+event:0X0C35 mmcr0:0X00000000 mmcr1:0X00608000021E82FA mmcra:0X00000000
+
+#Group 196 pm_l2_misc4, L2 Events
+event:0X0C40 mmcr0:0X00000000 mmcr1:0X00666000021E8282 mmcra:0X00000000
+event:0X0C41 mmcr0:0X00000000 mmcr1:0X00666000021E8282 mmcra:0X00000000
+event:0X0C42 mmcr0:0X00000000 mmcr1:0X00666000021E8282 mmcra:0X00000000
+event:0X0C43 mmcr0:0X00000000 mmcr1:0X00666000021E8282 mmcra:0X00000000
+event:0X0C44 mmcr0:0X00000000 mmcr1:0X00666000021E8282 mmcra:0X00000000
+event:0X0C45 mmcr0:0X00000000 mmcr1:0X00666000021E8282 mmcra:0X00000000
+
+#Group 197 pm_l2_misc5, L2 Events
+event:0X0C50 mmcr0:0X00000000 mmcr1:0X00608000021E80FA mmcra:0X00000000
+event:0X0C51 mmcr0:0X00000000 mmcr1:0X00608000021E80FA mmcra:0X00000000
+event:0X0C52 mmcr0:0X00000000 mmcr1:0X00608000021E80FA mmcra:0X00000000
+event:0X0C53 mmcr0:0X00000000 mmcr1:0X00608000021E80FA mmcra:0X00000000
+event:0X0C54 mmcr0:0X00000000 mmcr1:0X00608000021E80FA mmcra:0X00000000
+event:0X0C55 mmcr0:0X00000000 mmcr1:0X00608000021E80FA mmcra:0X00000000
+
+#Group 198 pm_l2_misc6, L2 Events
+event:0X0C60 mmcr0:0X00000000 mmcr1:0X0006600002F41E80 mmcra:0X00000000
+event:0X0C61 mmcr0:0X00000000 mmcr1:0X0006600002F41E80 mmcra:0X00000000
+event:0X0C62 mmcr0:0X00000000 mmcr1:0X0006600002F41E80 mmcra:0X00000000
+event:0X0C63 mmcr0:0X00000000 mmcr1:0X0006600002F41E80 mmcra:0X00000000
+event:0X0C64 mmcr0:0X00000000 mmcr1:0X0006600002F41E80 mmcra:0X00000000
+event:0X0C65 mmcr0:0X00000000 mmcr1:0X0006600002F41E80 mmcra:0X00000000
+
+#Group 199 pm_ierat, IERAT Events
+event:0X0C70 mmcr0:0X00000000 mmcr1:0X04400000F6BCBE02 mmcra:0X00000000
+event:0X0C71 mmcr0:0X00000000 mmcr1:0X04400000F6BCBE02 mmcra:0X00000000
+event:0X0C72 mmcr0:0X00000000 mmcr1:0X04400000F6BCBE02 mmcra:0X00000000
+event:0X0C73 mmcr0:0X00000000 mmcr1:0X04400000F6BCBE02 mmcra:0X00000000
+event:0X0C74 mmcr0:0X00000000 mmcr1:0X04400000F6BCBE02 mmcra:0X00000000
+event:0X0C75 mmcr0:0X00000000 mmcr1:0X04400000F6BCBE02 mmcra:0X00000000
+
+#Group 200 pm_disp_clb, Dispatch CLB Events
+event:0X0C80 mmcr0:0X00000000 mmcr1:0X2200000090A81E02 mmcra:0X00000000
+event:0X0C81 mmcr0:0X00000000 mmcr1:0X2200000090A81E02 mmcra:0X00000000
+event:0X0C82 mmcr0:0X00000000 mmcr1:0X2200000090A81E02 mmcra:0X00000000
+event:0X0C83 mmcr0:0X00000000 mmcr1:0X2200000090A81E02 mmcra:0X00000000
+event:0X0C84 mmcr0:0X00000000 mmcr1:0X2200000090A81E02 mmcra:0X00000000
+event:0X0C85 mmcr0:0X00000000 mmcr1:0X2200000090A81E02 mmcra:0X00000000
+
+#Group 201 pm_dpu, DPU Events
+event:0X0C90 mmcr0:0X00000000 mmcr1:0X000000001E060802 mmcra:0X00000000
+event:0X0C91 mmcr0:0X00000000 mmcr1:0X000000001E060802 mmcra:0X00000000
+event:0X0C92 mmcr0:0X00000000 mmcr1:0X000000001E060802 mmcra:0X00000000
+event:0X0C93 mmcr0:0X00000000 mmcr1:0X000000001E060802 mmcra:0X00000000
+event:0X0C94 mmcr0:0X00000000 mmcr1:0X000000001E060802 mmcra:0X00000000
+event:0X0C95 mmcr0:0X00000000 mmcr1:0X000000001E060802 mmcra:0X00000000
+
+#Group 202 pm_cpu_util, Basic CPU utilization
+event:0X0CA0 mmcr0:0X00000000 mmcr1:0X0000000008F41EF4 mmcra:0X00000000
+event:0X0CA1 mmcr0:0X00000000 mmcr1:0X0000000008F41EF4 mmcra:0X00000000
+event:0X0CA2 mmcr0:0X00000000 mmcr1:0X0000000008F41EF4 mmcra:0X00000000
+event:0X0CA3 mmcr0:0X00000000 mmcr1:0X0000000008F41EF4 mmcra:0X00000000
+event:0X0CA4 mmcr0:0X00000000 mmcr1:0X0000000008F41EF4 mmcra:0X00000000
+event:0X0CA5 mmcr0:0X00000000 mmcr1:0X0000000008F41EF4 mmcra:0X00000000
+
+#Group 203 pm_overflow1, Overflow events
+event:0X0CB0 mmcr0:0X00000000 mmcr1:0X0000000010101010 mmcra:0X00000000
+event:0X0CB1 mmcr0:0X00000000 mmcr1:0X0000000010101010 mmcra:0X00000000
+event:0X0CB2 mmcr0:0X00000000 mmcr1:0X0000000010101010 mmcra:0X00000000
+event:0X0CB3 mmcr0:0X00000000 mmcr1:0X0000000010101010 mmcra:0X00000000
+event:0X0CB4 mmcr0:0X00000000 mmcr1:0X0000000010101010 mmcra:0X00000000
+event:0X0CB5 mmcr0:0X00000000 mmcr1:0X0000000010101010 mmcra:0X00000000
+
+#Group 204 pm_overflow2, Overflow events
+event:0X0CC0 mmcr0:0X00000000 mmcr1:0X0000000024102410 mmcra:0X00000000
+event:0X0CC1 mmcr0:0X00000000 mmcr1:0X0000000024102410 mmcra:0X00000000
+event:0X0CC2 mmcr0:0X00000000 mmcr1:0X0000000024102410 mmcra:0X00000000
+event:0X0CC3 mmcr0:0X00000000 mmcr1:0X0000000024102410 mmcra:0X00000000
+event:0X0CC4 mmcr0:0X00000000 mmcr1:0X0000000024102410 mmcra:0X00000000
+event:0X0CC5 mmcr0:0X00000000 mmcr1:0X0000000024102410 mmcra:0X00000000
+
+#Group 205 pm_rewind, Rewind events
+event:0X0CD0 mmcr0:0X00000000 mmcr1:0X0000000020F42002 mmcra:0X00000000
+event:0X0CD1 mmcr0:0X00000000 mmcr1:0X0000000020F42002 mmcra:0X00000000
+event:0X0CD2 mmcr0:0X00000000 mmcr1:0X0000000020F42002 mmcra:0X00000000
+event:0X0CD3 mmcr0:0X00000000 mmcr1:0X0000000020F42002 mmcra:0X00000000
+event:0X0CD4 mmcr0:0X00000000 mmcr1:0X0000000020F42002 mmcra:0X00000000
+event:0X0CD5 mmcr0:0X00000000 mmcr1:0X0000000020F42002 mmcra:0X00000000
+
+#Group 206 pm_saved, Saved Events
+event:0X0CE0 mmcr0:0X00000000 mmcr1:0X0000000022F42202 mmcra:0X00000000
+event:0X0CE1 mmcr0:0X00000000 mmcr1:0X0000000022F42202 mmcra:0X00000000
+event:0X0CE2 mmcr0:0X00000000 mmcr1:0X0000000022F42202 mmcra:0X00000000
+event:0X0CE3 mmcr0:0X00000000 mmcr1:0X0000000022F42202 mmcra:0X00000000
+event:0X0CE4 mmcr0:0X00000000 mmcr1:0X0000000022F42202 mmcra:0X00000000
+event:0X0CE5 mmcr0:0X00000000 mmcr1:0X0000000022F42202 mmcra:0X00000000
+
+#Group 207 pm_tlbie, TLBIE Events
+event:0X0CF0 mmcr0:0X00000000 mmcr1:0X22D000008A96B202 mmcra:0X00000000
+event:0X0CF1 mmcr0:0X00000000 mmcr1:0X22D000008A96B202 mmcra:0X00000000
+event:0X0CF2 mmcr0:0X00000000 mmcr1:0X22D000008A96B202 mmcra:0X00000000
+event:0X0CF3 mmcr0:0X00000000 mmcr1:0X22D000008A96B202 mmcra:0X00000000
+event:0X0CF4 mmcr0:0X00000000 mmcr1:0X22D000008A96B202 mmcra:0X00000000
+event:0X0CF5 mmcr0:0X00000000 mmcr1:0X22D000008A96B202 mmcra:0X00000000
+
+#Group 208 pm_id_miss_erat_l1, Instruction/Data miss from ERAT/L1 cache
+event:0X0D00 mmcr0:0X00000000 mmcr1:0X00000000F6FCF0F0 mmcra:0X00000000
+event:0X0D01 mmcr0:0X00000000 mmcr1:0X00000000F6FCF0F0 mmcra:0X00000000
+event:0X0D02 mmcr0:0X00000000 mmcr1:0X00000000F6FCF0F0 mmcra:0X00000000
+event:0X0D03 mmcr0:0X00000000 mmcr1:0X00000000F6FCF0F0 mmcra:0X00000000
+event:0X0D04 mmcr0:0X00000000 mmcr1:0X00000000F6FCF0F0 mmcra:0X00000000
+event:0X0D05 mmcr0:0X00000000 mmcr1:0X00000000F6FCF0F0 mmcra:0X00000000
+
+#Group 209 pm_id_miss_erat_tlab, Instruction/Data miss from ERAT/TLB
+event:0X0D10 mmcr0:0X00000000 mmcr1:0X000000001EF6FCFC mmcra:0X00000000
+event:0X0D11 mmcr0:0X00000000 mmcr1:0X000000001EF6FCFC mmcra:0X00000000
+event:0X0D12 mmcr0:0X00000000 mmcr1:0X000000001EF6FCFC mmcra:0X00000000
+event:0X0D13 mmcr0:0X00000000 mmcr1:0X000000001EF6FCFC mmcra:0X00000000
+event:0X0D14 mmcr0:0X00000000 mmcr1:0X000000001EF6FCFC mmcra:0X00000000
+event:0X0D15 mmcr0:0X00000000 mmcr1:0X000000001EF6FCFC mmcra:0X00000000
+
+#Group 210 pm_compat_utilization1, Basic CPU utilization
+event:0X0D20 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+event:0X0D21 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+event:0X0D22 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+event:0X0D23 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+event:0X0D24 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+event:0X0D25 mmcr0:0X00000000 mmcr1:0X00000000FAF41EF4 mmcra:0X00000000
+
+#Group 211 pm_compat_utilization2, CPI and utilization data
+event:0X0D30 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+event:0X0D31 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+event:0X0D32 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+event:0X0D33 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+event:0X0D34 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+event:0X0D35 mmcr0:0X00000000 mmcr1:0X00000000F4F41EFA mmcra:0X00000000
+
+#Group 212 pm_compat_cpi_1plus_ppc, Misc CPI and utilization data
+event:0X0D40 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+event:0X0D41 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+event:0X0D42 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+event:0X0D43 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+event:0X0D44 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+event:0X0D45 mmcr0:0X00000000 mmcr1:0X00000000F2F4F2F2 mmcra:0X00000000
+
+#Group 213 pm_compat_l1_dcache_load_store_miss, L1 D-Cache load/store miss
+event:0X0D50 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+event:0X0D51 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+event:0X0D52 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+event:0X0D53 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+event:0X0D54 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+event:0X0D55 mmcr0:0X00000000 mmcr1:0X0000000002F0F0F0 mmcra:0X00000000
+
+#Group 214 pm_compat_l1_cache_load, L1 Cache loads
+event:0X0D60 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+event:0X0D61 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+event:0X0D62 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+event:0X0D63 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+event:0X0D64 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+event:0X0D65 mmcr0:0X00000000 mmcr1:0X0000000002FEF6F0 mmcra:0X00000000
+
+#Group 215 pm_compat_instruction_directory, Instruction Directory
+event:0X0D70 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+event:0X0D71 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+event:0X0D72 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+event:0X0D73 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+event:0X0D74 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+event:0X0D75 mmcr0:0X00000000 mmcr1:0X00000000F6FC02FC mmcra:0X00000000
+
+#Group 216 pm_compat_suspend, Suspend Events
+event:0X0D80 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+event:0X0D81 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+event:0X0D82 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+event:0X0D83 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+event:0X0D84 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+event:0X0D85 mmcr0:0X00000000 mmcr1:0X0000000000000000 mmcra:0X00000000
+
+#Group 217 pm_compat_misc_events1, Misc Events
+event:0X0D90 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+event:0X0D91 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+event:0X0D92 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+event:0X0D93 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+event:0X0D94 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+event:0X0D95 mmcr0:0X00000000 mmcr1:0X0000000002F8F81E mmcra:0X00000000
+
+#Group 218 pm_compat_misc_events2, Misc Events
+event:0X0DA0 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+event:0X0DA1 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+event:0X0DA2 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+event:0X0DA3 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+event:0X0DA4 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+event:0X0DA5 mmcr0:0X00000000 mmcr1:0X00000000F0F2F4F8 mmcra:0X00000000
+
+#Group 219 pm_compat_misc_events3, Misc Events
+event:0X0DB0 mmcr0:0X00000000 mmcr1:0X00000000F8F21EF6 mmcra:0X00000000
+event:0X0DB1 mmcr0:0X00000000 mmcr1:0X00000000F8F21EF6 mmcra:0X00000000
+event:0X0DB2 mmcr0:0X00000000 mmcr1:0X00000000F8F21EF6 mmcra:0X00000000
+event:0X0DB3 mmcr0:0X00000000 mmcr1:0X00000000F8F21EF6 mmcra:0X00000000
+event:0X0DB4 mmcr0:0X00000000 mmcr1:0X00000000F8F21EF6 mmcra:0X00000000
+event:0X0DB5 mmcr0:0X00000000 mmcr1:0X00000000F8F21EF6 mmcra:0X00000000
+
+#Group 220 pm_mrk_br, Marked Branch events
+event:0X0DC0 mmcr0:0X00000000 mmcr1:0X0000000036363602 mmcra:0X00000001
+event:0X0DC1 mmcr0:0X00000000 mmcr1:0X0000000036363602 mmcra:0X00000001
+event:0X0DC2 mmcr0:0X00000000 mmcr1:0X0000000036363602 mmcra:0X00000001
+event:0X0DC3 mmcr0:0X00000000 mmcr1:0X0000000036363602 mmcra:0X00000001
+event:0X0DC4 mmcr0:0X00000000 mmcr1:0X0000000036363602 mmcra:0X00000001
+event:0X0DC5 mmcr0:0X00000000 mmcr1:0X0000000036363602 mmcra:0X00000001
+
+#Group 221 pm_mrk_dsource1, Marked data sources
+event:0X0DD0 mmcr0:0X00000000 mmcr1:0XD0D000004A2E4624 mmcra:0X00000001
+event:0X0DD1 mmcr0:0X00000000 mmcr1:0XD0D000004A2E4624 mmcra:0X00000001
+event:0X0DD2 mmcr0:0X00000000 mmcr1:0XD0D000004A2E4624 mmcra:0X00000001
+event:0X0DD3 mmcr0:0X00000000 mmcr1:0XD0D000004A2E4624 mmcra:0X00000001
+event:0X0DD4 mmcr0:0X00000000 mmcr1:0XD0D000004A2E4624 mmcra:0X00000001
+event:0X0DD5 mmcr0:0X00000000 mmcr1:0XD0D000004A2E4624 mmcra:0X00000001
+
+#Group 222 pm_mrk_dsource2, Marked data sources
+event:0X0DE0 mmcr0:0X00000000 mmcr1:0XD0D00000482C4A20 mmcra:0X00000001
+event:0X0DE1 mmcr0:0X00000000 mmcr1:0XD0D00000482C4A20 mmcra:0X00000001
+event:0X0DE2 mmcr0:0X00000000 mmcr1:0XD0D00000482C4A20 mmcra:0X00000001
+event:0X0DE3 mmcr0:0X00000000 mmcr1:0XD0D00000482C4A20 mmcra:0X00000001
+event:0X0DE4 mmcr0:0X00000000 mmcr1:0XD0D00000482C4A20 mmcra:0X00000001
+event:0X0DE5 mmcr0:0X00000000 mmcr1:0XD0D00000482C4A20 mmcra:0X00000001
+
+#Group 223 pm_mrk_dsource3, Marked data sources
+event:0X0DF0 mmcr0:0X00000000 mmcr1:0XD0D0000044244E26 mmcra:0X00000001
+event:0X0DF1 mmcr0:0X00000000 mmcr1:0XD0D0000044244E26 mmcra:0X00000001
+event:0X0DF2 mmcr0:0X00000000 mmcr1:0XD0D0000044244E26 mmcra:0X00000001
+event:0X0DF3 mmcr0:0X00000000 mmcr1:0XD0D0000044244E26 mmcra:0X00000001
+event:0X0DF4 mmcr0:0X00000000 mmcr1:0XD0D0000044244E26 mmcra:0X00000001
+event:0X0DF5 mmcr0:0X00000000 mmcr1:0XD0D0000044244E26 mmcra:0X00000001
+
+#Group 224 pm_mrk_dsource4, Marked data sources
+event:0X0E00 mmcr0:0X00000000 mmcr1:0XD0CC000040204242 mmcra:0X00000001
+event:0X0E01 mmcr0:0X00000000 mmcr1:0XD0CC000040204242 mmcra:0X00000001
+event:0X0E02 mmcr0:0X00000000 mmcr1:0XD0CC000040204242 mmcra:0X00000001
+event:0X0E03 mmcr0:0X00000000 mmcr1:0XD0CC000040204242 mmcra:0X00000001
+event:0X0E04 mmcr0:0X00000000 mmcr1:0XD0CC000040204242 mmcra:0X00000001
+event:0X0E05 mmcr0:0X00000000 mmcr1:0XD0CC000040204242 mmcra:0X00000001
+
+#Group 225 pm_mrk_dsource5, Marked data sources
+event:0X0E10 mmcr0:0X00000000 mmcr1:0XD0D00000422A4428 mmcra:0X00000001
+event:0X0E11 mmcr0:0X00000000 mmcr1:0XD0D00000422A4428 mmcra:0X00000001
+event:0X0E12 mmcr0:0X00000000 mmcr1:0XD0D00000422A4428 mmcra:0X00000001
+event:0X0E13 mmcr0:0X00000000 mmcr1:0XD0D00000422A4428 mmcra:0X00000001
+event:0X0E14 mmcr0:0X00000000 mmcr1:0XD0D00000422A4428 mmcra:0X00000001
+event:0X0E15 mmcr0:0X00000000 mmcr1:0XD0D00000422A4428 mmcra:0X00000001
+
+#Group 226 pm_mrk_dsource6, Marked data sources
+event:0X0E20 mmcr0:0X00000000 mmcr1:0XD0D000004C28422C mmcra:0X00000001
+event:0X0E21 mmcr0:0X00000000 mmcr1:0XD0D000004C28422C mmcra:0X00000001
+event:0X0E22 mmcr0:0X00000000 mmcr1:0XD0D000004C28422C mmcra:0X00000001
+event:0X0E23 mmcr0:0X00000000 mmcr1:0XD0D000004C28422C mmcra:0X00000001
+event:0X0E24 mmcr0:0X00000000 mmcr1:0XD0D000004C28422C mmcra:0X00000001
+event:0X0E25 mmcr0:0X00000000 mmcr1:0XD0D000004C28422C mmcra:0X00000001
+
+#Group 227 pm_mrk_dsource7, Marked data sources
+event:0X0E30 mmcr0:0X00000000 mmcr1:0XD00D00004E263048 mmcra:0X00000001
+event:0X0E31 mmcr0:0X00000000 mmcr1:0XD00D00004E263048 mmcra:0X00000001
+event:0X0E32 mmcr0:0X00000000 mmcr1:0XD00D00004E263048 mmcra:0X00000001
+event:0X0E33 mmcr0:0X00000000 mmcr1:0XD00D00004E263048 mmcra:0X00000001
+event:0X0E34 mmcr0:0X00000000 mmcr1:0XD00D00004E263048 mmcra:0X00000001
+event:0X0E35 mmcr0:0X00000000 mmcr1:0XD00D00004E263048 mmcra:0X00000001
+
+#Group 228 pm_mrk_dsource8, Marked data sources
+event:0X0E40 mmcr0:0X00000000 mmcr1:0X0DD000003F484C2A mmcra:0X00000001
+event:0X0E41 mmcr0:0X00000000 mmcr1:0X0DD000003F484C2A mmcra:0X00000001
+event:0X0E42 mmcr0:0X00000000 mmcr1:0X0DD000003F484C2A mmcra:0X00000001
+event:0X0E43 mmcr0:0X00000000 mmcr1:0X0DD000003F484C2A mmcra:0X00000001
+event:0X0E44 mmcr0:0X00000000 mmcr1:0X0DD000003F484C2A mmcra:0X00000001
+event:0X0E45 mmcr0:0X00000000 mmcr1:0X0DD000003F484C2A mmcra:0X00000001
+
+#Group 229 pm_mrk_lsu_flush1, Marked LSU Flush
+event:0X0E50 mmcr0:0X00000000 mmcr1:0XDD0000008486021E mmcra:0X00000001
+event:0X0E51 mmcr0:0X00000000 mmcr1:0XDD0000008486021E mmcra:0X00000001
+event:0X0E52 mmcr0:0X00000000 mmcr1:0XDD0000008486021E mmcra:0X00000001
+event:0X0E53 mmcr0:0X00000000 mmcr1:0XDD0000008486021E mmcra:0X00000001
+event:0X0E54 mmcr0:0X00000000 mmcr1:0XDD0000008486021E mmcra:0X00000001
+event:0X0E55 mmcr0:0X00000000 mmcr1:0XDD0000008486021E mmcra:0X00000001
+
+#Group 230 pm_mrk_lsu_flush2, Marked LSU Flush
+event:0X0E60 mmcr0:0X00000000 mmcr1:0X00DD0000021E888A mmcra:0X00000001
+event:0X0E61 mmcr0:0X00000000 mmcr1:0X00DD0000021E888A mmcra:0X00000001
+event:0X0E62 mmcr0:0X00000000 mmcr1:0X00DD0000021E888A mmcra:0X00000001
+event:0X0E63 mmcr0:0X00000000 mmcr1:0X00DD0000021E888A mmcra:0X00000001
+event:0X0E64 mmcr0:0X00000000 mmcr1:0X00DD0000021E888A mmcra:0X00000001
+event:0X0E65 mmcr0:0X00000000 mmcr1:0X00DD0000021E888A mmcra:0X00000001
+
+#Group 231 pm_mrk_rejects, Marked rejects
+event:0X0E70 mmcr0:0X00000000 mmcr1:0XDD000000828C0264 mmcra:0X00000001
+event:0X0E71 mmcr0:0X00000000 mmcr1:0XDD000000828C0264 mmcra:0X00000001
+event:0X0E72 mmcr0:0X00000000 mmcr1:0XDD000000828C0264 mmcra:0X00000001
+event:0X0E73 mmcr0:0X00000000 mmcr1:0XDD000000828C0264 mmcra:0X00000001
+event:0X0E74 mmcr0:0X00000000 mmcr1:0XDD000000828C0264 mmcra:0X00000001
+event:0X0E75 mmcr0:0X00000000 mmcr1:0XDD000000828C0264 mmcra:0X00000001
+
+#Group 232 pm_mrk_inst, Marked instruction events
+event:0X0E80 mmcr0:0X00000000 mmcr1:0X0000000032303002 mmcra:0X00000001
+event:0X0E81 mmcr0:0X00000000 mmcr1:0X0000000032303002 mmcra:0X00000001
+event:0X0E82 mmcr0:0X00000000 mmcr1:0X0000000032303002 mmcra:0X00000001
+event:0X0E83 mmcr0:0X00000000 mmcr1:0X0000000032303002 mmcra:0X00000001
+event:0X0E84 mmcr0:0X00000000 mmcr1:0X0000000032303002 mmcra:0X00000001
+event:0X0E85 mmcr0:0X00000000 mmcr1:0X0000000032303002 mmcra:0X00000001
+
+#Group 233 pm_mrk_st, Marked stores events
+event:0X0E90 mmcr0:0X00000000 mmcr1:0X0000000034343402 mmcra:0X00000001
+event:0X0E91 mmcr0:0X00000000 mmcr1:0X0000000034343402 mmcra:0X00000001
+event:0X0E92 mmcr0:0X00000000 mmcr1:0X0000000034343402 mmcra:0X00000001
+event:0X0E93 mmcr0:0X00000000 mmcr1:0X0000000034343402 mmcra:0X00000001
+event:0X0E94 mmcr0:0X00000000 mmcr1:0X0000000034343402 mmcra:0X00000001
+event:0X0E95 mmcr0:0X00000000 mmcr1:0X0000000034343402 mmcra:0X00000001
+
+#Group 234 pm_mrk_dtlb_miss1, Marked Data TLB Miss
+event:0X0EA0 mmcr0:0X00000000 mmcr1:0X0DDD0000025E5E5E mmcra:0X00000001
+event:0X0EA1 mmcr0:0X00000000 mmcr1:0X0DDD0000025E5E5E mmcra:0X00000001
+event:0X0EA2 mmcr0:0X00000000 mmcr1:0X0DDD0000025E5E5E mmcra:0X00000001
+event:0X0EA3 mmcr0:0X00000000 mmcr1:0X0DDD0000025E5E5E mmcra:0X00000001
+event:0X0EA4 mmcr0:0X00000000 mmcr1:0X0DDD0000025E5E5E mmcra:0X00000001
+event:0X0EA5 mmcr0:0X00000000 mmcr1:0X0DDD0000025E5E5E mmcra:0X00000001
+
+#Group 235 pm_mrk_dtlb_miss2, Marked Data TLB Miss
+event:0X0EB0 mmcr0:0X00000000 mmcr1:0XDDD000005E5E5E02 mmcra:0X00000001
+event:0X0EB1 mmcr0:0X00000000 mmcr1:0XDDD000005E5E5E02 mmcra:0X00000001
+event:0X0EB2 mmcr0:0X00000000 mmcr1:0XDDD000005E5E5E02 mmcra:0X00000001
+event:0X0EB3 mmcr0:0X00000000 mmcr1:0XDDD000005E5E5E02 mmcra:0X00000001
+event:0X0EB4 mmcr0:0X00000000 mmcr1:0XDDD000005E5E5E02 mmcra:0X00000001
+event:0X0EB5 mmcr0:0X00000000 mmcr1:0XDDD000005E5E5E02 mmcra:0X00000001
+
+#Group 236 pm_mrk_derat_miss1, Marked DERAT Miss events
+event:0X0EC0 mmcr0:0X00000000 mmcr1:0X0DDD0000025C5C5C mmcra:0X00000001
+event:0X0EC1 mmcr0:0X00000000 mmcr1:0X0DDD0000025C5C5C mmcra:0X00000001
+event:0X0EC2 mmcr0:0X00000000 mmcr1:0X0DDD0000025C5C5C mmcra:0X00000001
+event:0X0EC3 mmcr0:0X00000000 mmcr1:0X0DDD0000025C5C5C mmcra:0X00000001
+event:0X0EC4 mmcr0:0X00000000 mmcr1:0X0DDD0000025C5C5C mmcra:0X00000001
+event:0X0EC5 mmcr0:0X00000000 mmcr1:0X0DDD0000025C5C5C mmcra:0X00000001
+
+#Group 237 pm_mrk_derat_miss2, Marked DERAT Miss events
+event:0X0ED0 mmcr0:0X00000000 mmcr1:0XDDD000005C5C5C02 mmcra:0X00000001
+event:0X0ED1 mmcr0:0X00000000 mmcr1:0XDDD000005C5C5C02 mmcra:0X00000001
+event:0X0ED2 mmcr0:0X00000000 mmcr1:0XDDD000005C5C5C02 mmcra:0X00000001
+event:0X0ED3 mmcr0:0X00000000 mmcr1:0XDDD000005C5C5C02 mmcra:0X00000001
+event:0X0ED4 mmcr0:0X00000000 mmcr1:0XDDD000005C5C5C02 mmcra:0X00000001
+event:0X0ED5 mmcr0:0X00000000 mmcr1:0XDDD000005C5C5C02 mmcra:0X00000001
+
+#Group 238 pm_mrk_misc_miss, marked Miss Events
+event:0X0EE0 mmcr0:0X00000000 mmcr1:0X00D000003E025A3E mmcra:0X00000001
+event:0X0EE1 mmcr0:0X00000000 mmcr1:0X00D000003E025A3E mmcra:0X00000001
+event:0X0EE2 mmcr0:0X00000000 mmcr1:0X00D000003E025A3E mmcra:0X00000001
+event:0X0EE3 mmcr0:0X00000000 mmcr1:0X00D000003E025A3E mmcra:0X00000001
+event:0X0EE4 mmcr0:0X00000000 mmcr1:0X00D000003E025A3E mmcra:0X00000001
+event:0X0EE5 mmcr0:0X00000000 mmcr1:0X00D000003E025A3E mmcra:0X00000001
+
+#Group 239 pm_mrk_pteg1, Marked PTEG
+event:0X0EF0 mmcr0:0X00000000 mmcr1:0X0DDD000002525656 mmcra:0X00000001
+event:0X0EF1 mmcr0:0X00000000 mmcr1:0X0DDD000002525656 mmcra:0X00000001
+event:0X0EF2 mmcr0:0X00000000 mmcr1:0X0DDD000002525656 mmcra:0X00000001
+event:0X0EF3 mmcr0:0X00000000 mmcr1:0X0DDD000002525656 mmcra:0X00000001
+event:0X0EF4 mmcr0:0X00000000 mmcr1:0X0DDD000002525656 mmcra:0X00000001
+event:0X0EF5 mmcr0:0X00000000 mmcr1:0X0DDD000002525656 mmcra:0X00000001
+
+#Group 240 pm_mrk_pteg2, Marked PTEG
+event:0X0F00 mmcr0:0X00000000 mmcr1:0XDDD0000050545202 mmcra:0X00000001
+event:0X0F01 mmcr0:0X00000000 mmcr1:0XDDD0000050545202 mmcra:0X00000001
+event:0X0F02 mmcr0:0X00000000 mmcr1:0XDDD0000050545202 mmcra:0X00000001
+event:0X0F03 mmcr0:0X00000000 mmcr1:0XDDD0000050545202 mmcra:0X00000001
+event:0X0F04 mmcr0:0X00000000 mmcr1:0XDDD0000050545202 mmcra:0X00000001
+event:0X0F05 mmcr0:0X00000000 mmcr1:0XDDD0000050545202 mmcra:0X00000001
+
+#Group 241 pm_mrk_pteg3, Marked PTEG
+event:0X0F10 mmcr0:0X00000000 mmcr1:0X0DDD000002565654 mmcra:0X00000001
+event:0X0F11 mmcr0:0X00000000 mmcr1:0X0DDD000002565654 mmcra:0X00000001
+event:0X0F12 mmcr0:0X00000000 mmcr1:0X0DDD000002565654 mmcra:0X00000001
+event:0X0F13 mmcr0:0X00000000 mmcr1:0X0DDD000002565654 mmcra:0X00000001
+event:0X0F14 mmcr0:0X00000000 mmcr1:0X0DDD000002565654 mmcra:0X00000001
+event:0X0F15 mmcr0:0X00000000 mmcr1:0X0DDD000002565654 mmcra:0X00000001
+
+#Group 242 pm_mrk_pteg4, Marked PTEG
+event:0X0F20 mmcr0:0X00000000 mmcr1:0XDD0D000054500258 mmcra:0X00000001
+event:0X0F21 mmcr0:0X00000000 mmcr1:0XDD0D000054500258 mmcra:0X00000001
+event:0X0F22 mmcr0:0X00000000 mmcr1:0XDD0D000054500258 mmcra:0X00000001
+event:0X0F23 mmcr0:0X00000000 mmcr1:0XDD0D000054500258 mmcra:0X00000001
+event:0X0F24 mmcr0:0X00000000 mmcr1:0XDD0D000054500258 mmcra:0X00000001
+event:0X0F25 mmcr0:0X00000000 mmcr1:0XDD0D000054500258 mmcra:0X00000001
+
+#Group 243 pm_mrk_pteg5, Marked PTEG
+event:0X0F30 mmcr0:0X00000000 mmcr1:0XDD0D000052580252 mmcra:0X00000001
+event:0X0F31 mmcr0:0X00000000 mmcr1:0XDD0D000052580252 mmcra:0X00000001
+event:0X0F32 mmcr0:0X00000000 mmcr1:0XDD0D000052580252 mmcra:0X00000001
+event:0X0F33 mmcr0:0X00000000 mmcr1:0XDD0D000052580252 mmcra:0X00000001
+event:0X0F34 mmcr0:0X00000000 mmcr1:0XDD0D000052580252 mmcra:0X00000001
+event:0X0F35 mmcr0:0X00000000 mmcr1:0XDD0D000052580252 mmcra:0X00000001
+
+#Group 244 pm_mrk_misc1, Marked misc events
+event:0X0F40 mmcr0:0X00000000 mmcr1:0XD00000008E023A34 mmcra:0X00000001
+event:0X0F41 mmcr0:0X00000000 mmcr1:0XD00000008E023A34 mmcra:0X00000001
+event:0X0F42 mmcr0:0X00000000 mmcr1:0XD00000008E023A34 mmcra:0X00000001
+event:0X0F43 mmcr0:0X00000000 mmcr1:0XD00000008E023A34 mmcra:0X00000001
+event:0X0F44 mmcr0:0X00000000 mmcr1:0XD00000008E023A34 mmcra:0X00000001
+event:0X0F45 mmcr0:0X00000000 mmcr1:0XD00000008E023A34 mmcra:0X00000001
+
+#Group 245 pm_mrk_misc2, Marked misc events
+event:0X0F50 mmcr0:0X00000000 mmcr1:0X0000000002383A32 mmcra:0X00000001
+event:0X0F51 mmcr0:0X00000000 mmcr1:0X0000000002383A32 mmcra:0X00000001
+event:0X0F52 mmcr0:0X00000000 mmcr1:0X0000000002383A32 mmcra:0X00000001
+event:0X0F53 mmcr0:0X00000000 mmcr1:0X0000000002383A32 mmcra:0X00000001
+event:0X0F54 mmcr0:0X00000000 mmcr1:0X0000000002383A32 mmcra:0X00000001
+event:0X0F55 mmcr0:0X00000000 mmcr1:0X0000000002383A32 mmcra:0X00000001
+
+#Group 246 pm_mrk_misc3, Marked misc events
+event:0X0F60 mmcr0:0X00000000 mmcr1:0X00D00000023A8032 mmcra:0X00000001
+event:0X0F61 mmcr0:0X00000000 mmcr1:0X00D00000023A8032 mmcra:0X00000001
+event:0X0F62 mmcr0:0X00000000 mmcr1:0X00D00000023A8032 mmcra:0X00000001
+event:0X0F63 mmcr0:0X00000000 mmcr1:0X00D00000023A8032 mmcra:0X00000001
+event:0X0F64 mmcr0:0X00000000 mmcr1:0X00D00000023A8032 mmcra:0X00000001
+event:0X0F65 mmcr0:0X00000000 mmcr1:0X00D00000023A8032 mmcra:0X00000001
+
+#Group 247 pm_mrk_misc4, Marked misc events
+event:0X0F70 mmcr0:0X00000000 mmcr1:0X000000003C023238 mmcra:0X00000001
+event:0X0F71 mmcr0:0X00000000 mmcr1:0X000000003C023238 mmcra:0X00000001
+event:0X0F72 mmcr0:0X00000000 mmcr1:0X000000003C023238 mmcra:0X00000001
+event:0X0F73 mmcr0:0X00000000 mmcr1:0X000000003C023238 mmcra:0X00000001
+event:0X0F74 mmcr0:0X00000000 mmcr1:0X000000003C023238 mmcra:0X00000001
+event:0X0F75 mmcr0:0X00000000 mmcr1:0X000000003C023238 mmcra:0X00000001
+
+#Group 248 pm_mrk_misc5, Marked misc events
+event:0X0F80 mmcr0:0X00000000 mmcr1:0X000000003D323F02 mmcra:0X00000001
+event:0X0F81 mmcr0:0X00000000 mmcr1:0X000000003D323F02 mmcra:0X00000001
+event:0X0F82 mmcr0:0X00000000 mmcr1:0X000000003D323F02 mmcra:0X00000001
+event:0X0F83 mmcr0:0X00000000 mmcr1:0X000000003D323F02 mmcra:0X00000001
+event:0X0F84 mmcr0:0X00000000 mmcr1:0X000000003D323F02 mmcra:0X00000001
+event:0X0F85 mmcr0:0X00000000 mmcr1:0X000000003D323F02 mmcra:0X00000001
+
+#Group 249 pm_mrk_misc6, Marked misc events
+event:0X0F90 mmcr0:0X00000000 mmcr1:0X0000000030F40230 mmcra:0X00000001
+event:0X0F91 mmcr0:0X00000000 mmcr1:0X0000000030F40230 mmcra:0X00000001
+event:0X0F92 mmcr0:0X00000000 mmcr1:0X0000000030F40230 mmcra:0X00000001
+event:0X0F93 mmcr0:0X00000000 mmcr1:0X0000000030F40230 mmcra:0X00000001
+event:0X0F94 mmcr0:0X00000000 mmcr1:0X0000000030F40230 mmcra:0X00000001
+event:0X0F95 mmcr0:0X00000000 mmcr1:0X0000000030F40230 mmcra:0X00000001
+
+#Group 250 pm_mrk_misc7, Marked misc events
+event:0X0FA0 mmcr0:0X00000000 mmcr1:0XD000000082026464 mmcra:0X00000001
+event:0X0FA1 mmcr0:0X00000000 mmcr1:0XD000000082026464 mmcra:0X00000001
+event:0X0FA2 mmcr0:0X00000000 mmcr1:0XD000000082026464 mmcra:0X00000001
+event:0X0FA3 mmcr0:0X00000000 mmcr1:0XD000000082026464 mmcra:0X00000001
+event:0X0FA4 mmcr0:0X00000000 mmcr1:0XD000000082026464 mmcra:0X00000001
+event:0X0FA5 mmcr0:0X00000000 mmcr1:0XD000000082026464 mmcra:0X00000001
+
+#Group 251 pm_mrk_misc8, Marked misc events
+event:0X0FB0 mmcr0:0X00000000 mmcr1:0X000000001E1E0232 mmcra:0X00000001
+event:0X0FB1 mmcr0:0X00000000 mmcr1:0X000000001E1E0232 mmcra:0X00000001
+event:0X0FB2 mmcr0:0X00000000 mmcr1:0X000000001E1E0232 mmcra:0X00000001
+event:0X0FB3 mmcr0:0X00000000 mmcr1:0X000000001E1E0232 mmcra:0X00000001
+event:0X0FB4 mmcr0:0X00000000 mmcr1:0X000000001E1E0232 mmcra:0X00000001
+event:0X0FB5 mmcr0:0X00000000 mmcr1:0X000000001E1E0232 mmcra:0X00000001
diff --git a/events/ppc64/power7/events b/events/ppc64/power7/events
new file mode 100644
index 0000000..66c9068
--- /dev/null
+++ b/events/ppc64/power7/events
@@ -0,0 +1,2027 @@
+#PPC64 POWER7 events
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2009.
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>.
+#
+#
+# Only events within the same group can be selected simultaneously.
+# Each event is given a unique event number. The event number is used by the
+# OProfile code to resolve event names for the post-processing. This is done
+# to preserve compatibility with the rest of the OProfile code. The event
+# numbers are formatted as follows: <group_num>concat(<counter for the event>).
+
+#Group Default
+event:0X001 counters:0 um:zero minimum:10000 name:CYCLES : Processor Cycles
+
+#Group 0 with random sampling
+event:0X002 counters:3 um:zero minimum:10000 name:CYCLES_RND_SMPL : Processor Cycles with random sampling
+
+
+#Group 1 pm_utilization, CPI and utilization data
+event:0X0010 counters:0 um:zero minimum:10000 name:PM_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles
+event:0X0011 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0012 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP1 : (Group 1 pm_utilization) Number of PowerPC instructions successfully dispatched.
+event:0X0013 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP1 : (Group 1 pm_utilization) Number of PowerPC Instructions that completed.
+event:0X0014 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP1 : (Group 1 pm_utilization) Number of run instructions completed.
+event:0X0015 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP1 : (Group 1 pm_utilization) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 2 pm_branch1, Branch operations
+event:0X0020 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP2 : (Group 2 pm_branch1) The count value of a Branch and Count instruction was predicted
+event:0X0021 counters:1 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP2 : (Group 2 pm_branch1) The target address of a Branch to Link instruction was predicted by the link stack.
+event:0X0022 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP2 : (Group 2 pm_branch1) A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
+event:0X0023 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP2 : (Group 2 pm_branch1) A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
+event:0X0024 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP2 : (Group 2 pm_branch1) Number of run instructions completed.
+event:0X0025 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP2 : (Group 2 pm_branch1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 3 pm_branch2, Branch operations
+event:0X0030 counters:0 um:zero minimum:1000 name:PM_BR_PRED_GRP3 : (Group 3 pm_branch2) A branch prediction was made. This could have been a target prediction, a condition prediction, or both
+event:0X0031 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP3 : (Group 3 pm_branch2) A conditional branch instruction was predicted as taken or not taken.
+event:0X0032 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP3 : (Group 3 pm_branch2) The count value of a Branch and Count instruction was predicted
+event:0X0033 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP3 : (Group 3 pm_branch2) The target address of a Branch to Link instruction was predicted by the link stack.
+event:0X0034 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP3 : (Group 3 pm_branch2) Number of run instructions completed.
+event:0X0035 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP3 : (Group 3 pm_branch2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 4 pm_branch3, Branch operations
+event:0X0040 counters:0 um:zero minimum:1000 name:PM_BRU_FIN_GRP4 : (Group 4 pm_branch3) The Branch execution unit finished an instruction
+event:0X0041 counters:1 um:zero minimum:1000 name:PM_BR_TAKEN_GRP4 : (Group 4 pm_branch3) A branch instruction was taken. This could have been a conditional branch or an unconditional branch
+event:0X0042 counters:2 um:zero minimum:1000 name:PM_BR_PRED_GRP4 : (Group 4 pm_branch3) A branch prediction was made. This could have been a target prediction, a condition prediction, or both
+event:0X0043 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP4 : (Group 4 pm_branch3) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
+event:0X0044 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP4 : (Group 4 pm_branch3) Number of run instructions completed.
+event:0X0045 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP4 : (Group 4 pm_branch3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 5 pm_branch4, Branch operations
+event:0X0050 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP5 : (Group 5 pm_branch4) A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
+event:0X0051 counters:1 um:zero minimum:1000 name:PM_BR_UNCOND_GRP5 : (Group 5 pm_branch4) An unconditional branch was executed.
+event:0X0052 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP5 : (Group 5 pm_branch4) A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
+event:0X0053 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP5 : (Group 5 pm_branch4) A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
+event:0X0054 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP5 : (Group 5 pm_branch4) Number of run instructions completed.
+event:0X0055 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP5 : (Group 5 pm_branch4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 6 pm_branch5, Branch operations
+event:0X0060 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CR_TA_GRP6 : (Group 6 pm_branch5) Both the condition (taken or not taken) and the target address of a branch instruction was predicted.
+event:0X0061 counters:1 um:zero minimum:1000 name:PM_BR_MPRED_CR_TA_GRP6 : (Group 6 pm_branch5) Branch mispredict - taken/not taken and target
+event:0X0062 counters:2 um:zero minimum:1000 name:PM_BR_PRED_GRP6 : (Group 6 pm_branch5) A branch prediction was made. This could have been a target prediction, a condition prediction, or both
+event:0X0063 counters:3 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP6 : (Group 6 pm_branch5) A conditional branch instruction was predicted as taken or not taken.
+event:0X0064 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP6 : (Group 6 pm_branch5) Number of run instructions completed.
+event:0X0065 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP6 : (Group 6 pm_branch5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 7 pm_branch6, Branch operations
+event:0X0070 counters:0 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP7 : (Group 7 pm_branch6) The count value of a Branch and Count instruction was predicted
+event:0X0071 counters:1 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP7 : (Group 7 pm_branch6) The target address of a Branch to Link instruction was predicted by the link stack.
+event:0X0072 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP7 : (Group 7 pm_branch6) A conditional branch instruction was predicted as taken or not taken.
+event:0X0073 counters:3 um:zero minimum:1000 name:PM_BR_PRED_TA_GRP7 : (Group 7 pm_branch6) The target address of a branch instruction was predicted.
+event:0X0074 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP7 : (Group 7 pm_branch6) Number of run instructions completed.
+event:0X0075 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP7 : (Group 7 pm_branch6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 8 pm_branch7, Branch operations
+event:0X0080 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_CR_GRP8 : (Group 8 pm_branch7) A conditional branch instruction was incorrectly predicted as taken or not taken. The branch execution unit detects a branch mispredict because the CR value is opposite of the predicted value. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
+event:0X0081 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP8 : (Group 8 pm_branch7) A conditional branch instruction was predicted as taken or not taken.
+event:0X0082 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP8 : (Group 8 pm_branch7) The count value of a Branch and Count instruction was predicted
+event:0X0083 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP8 : (Group 8 pm_branch7) The target address of a Branch to Link instruction was predicted by the link stack.
+event:0X0084 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP8 : (Group 8 pm_branch7) Number of run instructions completed.
+event:0X0085 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP8 : (Group 8 pm_branch7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 9 pm_branch8, Branch operations
+event:0X0090 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_TA_GRP9 : (Group 9 pm_branch8) A branch instruction target was incorrectly predicted. This will result in a branch mispredict flush unless a flush is detected from an older instruction.
+event:0X0091 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP9 : (Group 9 pm_branch8) A conditional branch instruction was predicted as taken or not taken.
+event:0X0092 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP9 : (Group 9 pm_branch8) The count value of a Branch and Count instruction was predicted
+event:0X0093 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP9 : (Group 9 pm_branch8) The target address of a Branch to Link instruction was predicted by the link stack.
+event:0X0094 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP9 : (Group 9 pm_branch8) Number of run instructions completed.
+event:0X0095 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP9 : (Group 9 pm_branch8) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 10 pm_branch9, Branch operations
+event:0X00A0 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP10 : (Group 10 pm_branch9) A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
+event:0X00A1 counters:1 um:zero minimum:1000 name:PM_BR_PRED_CR_GRP10 : (Group 10 pm_branch9) A conditional branch instruction was predicted as taken or not taken.
+event:0X00A2 counters:2 um:zero minimum:1000 name:PM_BR_PRED_CCACHE_GRP10 : (Group 10 pm_branch9) The count value of a Branch and Count instruction was predicted
+event:0X00A3 counters:3 um:zero minimum:1000 name:PM_BR_PRED_LSTACK_GRP10 : (Group 10 pm_branch9) The target address of a Branch to Link instruction was predicted by the link stack.
+event:0X00A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP10 : (Group 10 pm_branch9) Number of run instructions completed.
+event:0X00A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP10 : (Group 10 pm_branch9) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 11 pm_slb_miss, SLB Misses
+event:0X00B0 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP11 : (Group 11 pm_slb_miss) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
+event:0X00B1 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP11 : (Group 11 pm_slb_miss) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
+event:0X00B2 counters:2 um:zero minimum:1000 name:PM_ISLB_MISS_GRP11 : (Group 11 pm_slb_miss) A SLB miss for an instruction fetch as occurred
+event:0X00B3 counters:3 um:zero minimum:1000 name:PM_SLB_MISS_GRP11 : (Group 11 pm_slb_miss) Total of all Segment Lookaside Buffer (SLB) misses, Instructions + Data.
+event:0X00B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP11 : (Group 11 pm_slb_miss) Number of run instructions completed.
+event:0X00B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP11 : (Group 11 pm_slb_miss) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 12 pm_tlb_miss, TLB Misses
+event:0X00C0 counters:0 um:zero minimum:1000 name:PM_BTAC_MISS_GRP12 : (Group 12 pm_tlb_miss) BTAC Mispredicted
+event:0X00C1 counters:1 um:zero minimum:1000 name:PM_TLB_MISS_GRP12 : (Group 12 pm_tlb_miss) Total of Data TLB mises + Instruction TLB misses
+event:0X00C2 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP12 : (Group 12 pm_tlb_miss) Data TLB misses, all page sizes.
+event:0X00C3 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP12 : (Group 12 pm_tlb_miss) A TLB miss for an Instruction Fetch has occurred
+event:0X00C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP12 : (Group 12 pm_tlb_miss) Number of run instructions completed.
+event:0X00C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP12 : (Group 12 pm_tlb_miss) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 13 pm_dtlb_miss, DTLB Misses
+event:0X00D0 counters:0 um:zero minimum:1000 name:PM_DTLB_MISS_16G_GRP13 : (Group 13 pm_dtlb_miss) Data TLB references to 16GB pages that missed the TLB. Page size is determined at TLB reload time.
+event:0X00D1 counters:1 um:zero minimum:1000 name:PM_DTLB_MISS_4K_GRP13 : (Group 13 pm_dtlb_miss) Data TLB references to 4KB pages that missed the TLB. Page size is determined at TLB reload time.
+event:0X00D2 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_64K_GRP13 : (Group 13 pm_dtlb_miss) Data TLB references to 64KB pages that missed the TLB. Page size is determined at TLB reload time.
+event:0X00D3 counters:3 um:zero minimum:1000 name:PM_DTLB_MISS_16M_GRP13 : (Group 13 pm_dtlb_miss) Data TLB references to 16MB pages that missed the TLB. Page size is determined at TLB reload time.
+event:0X00D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP13 : (Group 13 pm_dtlb_miss) Number of run instructions completed.
+event:0X00D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP13 : (Group 13 pm_dtlb_miss) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 14 pm_derat_miss1, DERAT misses
+event:0X00E0 counters:0 um:zero minimum:1000 name:PM_DERAT_MISS_4K_GRP14 : (Group 14 pm_derat_miss1) A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.
+event:0X00E1 counters:1 um:zero minimum:1000 name:PM_DERAT_MISS_64K_GRP14 : (Group 14 pm_derat_miss1) A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
+event:0X00E2 counters:2 um:zero minimum:1000 name:PM_DERAT_MISS_16M_GRP14 : (Group 14 pm_derat_miss1) A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
+event:0X00E3 counters:3 um:zero minimum:1000 name:PM_DERAT_MISS_16G_GRP14 : (Group 14 pm_derat_miss1) A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.
+event:0X00E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP14 : (Group 14 pm_derat_miss1) Number of run instructions completed.
+event:0X00E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP14 : (Group 14 pm_derat_miss1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 15 pm_derat_miss2, DERAT misses
+event:0X00F0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP15 : (Group 15 pm_derat_miss2) Number of PowerPC Instructions that completed.
+event:0X00F1 counters:1 um:zero minimum:1000 name:PM_DERAT_MISS_64K_GRP15 : (Group 15 pm_derat_miss2) A data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
+event:0X00F2 counters:2 um:zero minimum:1000 name:PM_DERAT_MISS_16M_GRP15 : (Group 15 pm_derat_miss2) A data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
+event:0X00F3 counters:3 um:zero minimum:1000 name:PM_DERAT_MISS_16G_GRP15 : (Group 15 pm_derat_miss2) A data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.
+event:0X00F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP15 : (Group 15 pm_derat_miss2) Number of run instructions completed.
+event:0X00F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP15 : (Group 15 pm_derat_miss2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 16 pm_misc_miss1, Misses
+event:0X0100 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_GRP16 : (Group 16 pm_misc_miss1) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
+event:0X0101 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP16 : (Group 16 pm_misc_miss1) The processor's Data Cache was reloaded but not from the local L2.
+event:0X0102 counters:2 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP16 : (Group 16 pm_misc_miss1) Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.
+event:0X0103 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP16 : (Group 16 pm_misc_miss1) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
+event:0X0104 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP16 : (Group 16 pm_misc_miss1) Number of run instructions completed.
+event:0X0105 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP16 : (Group 16 pm_misc_miss1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 17 pm_misc_miss2, Misses
+event:0X0110 counters:0 um:zero minimum:10000 name:PM_CYC_GRP17 : (Group 17 pm_misc_miss2) Processor Cycles
+event:0X0111 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3MISS_GRP17 : (Group 17 pm_misc_miss2) Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.
+event:0X0112 counters:2 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP17 : (Group 17 pm_misc_miss2) Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.
+event:0X0113 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP17 : (Group 17 pm_misc_miss2) Number of run instructions completed.
+event:0X0114 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP17 : (Group 17 pm_misc_miss2) Number of run instructions completed.
+event:0X0115 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP17 : (Group 17 pm_misc_miss2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 18 pm_misc_miss3, Misses
+event:0X0120 counters:0 um:zero minimum:10000 name:PM_CYC_GRP18 : (Group 18 pm_misc_miss3) Processor Cycles
+event:0X0121 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3MISS_GRP18 : (Group 18 pm_misc_miss3) Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.
+event:0X0122 counters:2 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP18 : (Group 18 pm_misc_miss3) Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.
+event:0X0123 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP18 : (Group 18 pm_misc_miss3) A Page Table Entry was loaded into the TLB but not from the local L2.
+event:0X0124 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP18 : (Group 18 pm_misc_miss3) Number of run instructions completed.
+event:0X0125 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP18 : (Group 18 pm_misc_miss3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 19 pm_misc_miss4, Misses
+event:0X0130 counters:0 um:zero minimum:1000 name:PM_DSLB_MISS_GRP19 : (Group 19 pm_misc_miss4) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
+event:0X0131 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP19 : (Group 19 pm_misc_miss4) An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
+event:0X0132 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP19 : (Group 19 pm_misc_miss4) Number of PowerPC Instructions that completed.
+event:0X0133 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP19 : (Group 19 pm_misc_miss4) Number of run instructions completed.
+event:0X0134 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP19 : (Group 19 pm_misc_miss4) Number of run instructions completed.
+event:0X0135 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP19 : (Group 19 pm_misc_miss4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 20 pm_misc_miss5, Misses
+event:0X0140 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP20 : (Group 20 pm_misc_miss5) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
+event:0X0141 counters:1 um:zero minimum:1000 name:PM_DSLB_MISS_GRP20 : (Group 20 pm_misc_miss5) A SLB miss for a data request occurred. SLB misses trap to the operating system to resolve.
+event:0X0142 counters:2 um:zero minimum:1000 name:PM_ISLB_MISS_GRP20 : (Group 20 pm_misc_miss5) A SLB miss for an instruction fetch as occurred
+event:0X0143 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP20 : (Group 20 pm_misc_miss5) Number of PowerPC Instructions that completed.
+event:0X0144 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP20 : (Group 20 pm_misc_miss5) Number of run instructions completed.
+event:0X0145 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP20 : (Group 20 pm_misc_miss5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 21 pm_pteg1, PTEG sources
+event:0X0150 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP21 : (Group 21 pm_pteg1) A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.
+event:0X0151 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L3_GRP21 : (Group 21 pm_pteg1) Instruction PTEG loaded from L3
+event:0X0152 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_L21_MOD_GRP21 : (Group 21 pm_pteg1) PTEG loaded from another L2 on same chip modified
+event:0X0153 counters:3 um:zero minimum:1000 name:PM_INST_PTEG_FROM_DL2L3_MOD_GRP21 : (Group 21 pm_pteg1) Instruction PTEG loaded from distant L2 or L3 modified
+event:0X0154 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP21 : (Group 21 pm_pteg1) Number of run instructions completed.
+event:0X0155 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP21 : (Group 21 pm_pteg1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 22 pm_pteg2, PTEG sources
+event:0X0160 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L2_GRP22 : (Group 22 pm_pteg2) Instruction PTEG loaded from L2
+event:0X0161 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_RL2L3_SHR_GRP22 : (Group 22 pm_pteg2) Instruction PTEG loaded from remote L2 or L3 shared
+event:0X0162 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_DL2L3_SHR_GRP22 : (Group 22 pm_pteg2) Instruction PTEG loaded from remote L2 or L3 shared
+event:0X0163 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_DL2L3_MOD_GRP22 : (Group 22 pm_pteg2) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store.
+event:0X0164 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP22 : (Group 22 pm_pteg2) Number of run instructions completed.
+event:0X0165 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP22 : (Group 22 pm_pteg2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 23 pm_pteg3, PTEG sources
+event:0X0170 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L31_MOD_GRP23 : (Group 23 pm_pteg3) PTEG loaded from another L3 on same chip modified
+event:0X0171 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3MISS_GRP23 : (Group 23 pm_pteg3) Page Table Entry was loaded into the ERAT from beyond the L3 due to a demand load or store.
+event:0X0172 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_RMEM_GRP23 : (Group 23 pm_pteg3) Instruction PTEG loaded from remote memory
+event:0X0173 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP23 : (Group 23 pm_pteg3) A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.
+event:0X0174 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP23 : (Group 23 pm_pteg3) Number of run instructions completed.
+event:0X0175 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP23 : (Group 23 pm_pteg3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 24 pm_pteg4, PTEG sources
+event:0X0180 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_RL2L3_MOD_GRP24 : (Group 24 pm_pteg4) Instruction PTEG loaded from remote L2 or L3 modified
+event:0X0181 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_DMEM_GRP24 : (Group 24 pm_pteg4) A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.
+event:0X0182 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP24 : (Group 24 pm_pteg4) A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.
+event:0X0183 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP24 : (Group 24 pm_pteg4) A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.
+event:0X0184 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP24 : (Group 24 pm_pteg4) Number of run instructions completed.
+event:0X0185 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP24 : (Group 24 pm_pteg4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 25 pm_pteg5, PTEG sources
+event:0X0190 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_RL2L3_MOD_GRP25 : (Group 25 pm_pteg5) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store.
+event:0X0191 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L31_SHR_GRP25 : (Group 25 pm_pteg5) PTEG loaded from another L3 on same chip shared
+event:0X0192 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_DL2L3_SHR_GRP25 : (Group 25 pm_pteg5) A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.
+event:0X0193 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L21_SHR_GRP25 : (Group 25 pm_pteg5) PTEG loaded from another L2 on same chip shared
+event:0X0194 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP25 : (Group 25 pm_pteg5) Number of run instructions completed.
+event:0X0195 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP25 : (Group 25 pm_pteg5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 26 pm_pteg6, PTEG sources
+event:0X01A0 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L31_MOD_GRP26 : (Group 26 pm_pteg6) Instruction PTEG loaded from another L3 on same chip modified
+event:0X01A1 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_DMEM_GRP26 : (Group 26 pm_pteg6) Instruction PTEG loaded from distant memory
+event:0X01A2 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L21_MOD_GRP26 : (Group 26 pm_pteg6) Instruction PTEG loaded from another L2 on same chip modified
+event:0X01A3 counters:3 um:zero minimum:1000 name:PM_INST_PTEG_FROM_LMEM_GRP26 : (Group 26 pm_pteg6) Instruction PTEG loaded from local memory
+event:0X01A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP26 : (Group 26 pm_pteg6) Number of run instructions completed.
+event:0X01A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP26 : (Group 26 pm_pteg6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 27 pm_pteg7, PTEG sources
+event:0X01B0 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L31_MOD_GRP27 : (Group 27 pm_pteg7) Instruction PTEG loaded from another L3 on same chip modified
+event:0X01B1 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L31_SHR_GRP27 : (Group 27 pm_pteg7) Instruction PTEG loaded from another L3 on same chip shared
+event:0X01B2 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L21_MOD_GRP27 : (Group 27 pm_pteg7) Instruction PTEG loaded from another L2 on same chip modified
+event:0X01B3 counters:3 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L21_SHR_GRP27 : (Group 27 pm_pteg7) Instruction PTEG loaded from another L2 on same chip shared
+event:0X01B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP27 : (Group 27 pm_pteg7) Number of run instructions completed.
+event:0X01B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP27 : (Group 27 pm_pteg7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 28 pm_pteg8, PTEG sources
+event:0X01C0 counters:0 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L2_GRP28 : (Group 28 pm_pteg8) Instruction PTEG loaded from L2
+event:0X01C1 counters:1 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L3MISS_GRP28 : (Group 28 pm_pteg8) Instruction PTEG loaded from L3 miss
+event:0X01C2 counters:2 um:zero minimum:1000 name:PM_INST_PTEG_FROM_RMEM_GRP28 : (Group 28 pm_pteg8) Instruction PTEG loaded from remote memory
+event:0X01C3 counters:3 um:zero minimum:1000 name:PM_INST_PTEG_FROM_L2MISS_GRP28 : (Group 28 pm_pteg8) Instruction PTEG loaded from L2 miss
+event:0X01C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP28 : (Group 28 pm_pteg8) Number of run instructions completed.
+event:0X01C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP28 : (Group 28 pm_pteg8) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 29 pm_pteg9, PTEG sources
+event:0X01D0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP29 : (Group 29 pm_pteg9) A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.
+event:0X01D1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP29 : (Group 29 pm_pteg9) A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.
+event:0X01D2 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP29 : (Group 29 pm_pteg9) A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.
+event:0X01D3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_L2MISS_GRP29 : (Group 29 pm_pteg9) A Page Table Entry was loaded into the TLB but not from the local L2.
+event:0X01D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP29 : (Group 29 pm_pteg9) Number of run instructions completed.
+event:0X01D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP29 : (Group 29 pm_pteg9) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 30 pm_pteg10, PTEG sources
+event:0X01E0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_L2_GRP30 : (Group 30 pm_pteg10) A Page Table Entry was loaded into the ERAT from the local L2 due to a demand load or store.
+event:0X01E1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_L3_GRP30 : (Group 30 pm_pteg10) A Page Table Entry was loaded into the TLB from the local L3 due to a demand load.
+event:0X01E2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP30 : (Group 30 pm_pteg10) Number of PowerPC Instructions that completed.
+event:0X01E3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP30 : (Group 30 pm_pteg10) Processor Cycles
+event:0X01E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP30 : (Group 30 pm_pteg10) Number of run instructions completed.
+event:0X01E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP30 : (Group 30 pm_pteg10) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 31 pm_pteg11, PTEG sources
+event:0X01F0 counters:0 um:zero minimum:1000 name:PM_PTEG_FROM_RL2L3_MOD_GRP31 : (Group 31 pm_pteg11) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a remote module due to a demand load or store.
+event:0X01F1 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_RL2L3_SHR_GRP31 : (Group 31 pm_pteg11) A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load or store.
+event:0X01F2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP31 : (Group 31 pm_pteg11) Number of PowerPC Instructions that completed.
+event:0X01F3 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_DL2L3_MOD_GRP31 : (Group 31 pm_pteg11) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a demand load or store.
+event:0X01F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP31 : (Group 31 pm_pteg11) Number of run instructions completed.
+event:0X01F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP31 : (Group 31 pm_pteg11) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 32 pm_pteg12, PTEG sources
+event:0X0200 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP32 : (Group 32 pm_pteg12) Number of PowerPC Instructions that completed.
+event:0X0201 counters:1 um:zero minimum:1000 name:PM_PTEG_FROM_DMEM_GRP32 : (Group 32 pm_pteg12) A Page Table Entry was loaded into the ERAT with data from memory attached to a distant module due to a demand load or store.
+event:0X0202 counters:2 um:zero minimum:1000 name:PM_PTEG_FROM_RMEM_GRP32 : (Group 32 pm_pteg12) A Page Table Entry was loaded into the TLB from memory attached to a different module than this proccessor is located on.
+event:0X0203 counters:3 um:zero minimum:1000 name:PM_PTEG_FROM_LMEM_GRP32 : (Group 32 pm_pteg12) A Page Table Entry was loaded into the TLB from memory attached to the same module this proccessor is located on.
+event:0X0204 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP32 : (Group 32 pm_pteg12) Number of run instructions completed.
+event:0X0205 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP32 : (Group 32 pm_pteg12) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 33 pm_freq1, Frequency events
+event:0X0210 counters:0 um:zero minimum:1000 name:PM_POWER_EVENT1_GRP33 : (Group 33 pm_freq1) Power Management Event 1
+event:0X0211 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP33 : (Group 33 pm_freq1) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
+event:0X0212 counters:2 um:zero minimum:1000 name:PM_FREQ_DOWN_GRP33 : (Group 33 pm_freq1) Processor frequency was slowed down due to power management
+event:0X0213 counters:3 um:zero minimum:1000 name:PM_FREQ_UP_GRP33 : (Group 33 pm_freq1) Processor frequency was sped up due to power management
+event:0X0214 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP33 : (Group 33 pm_freq1) Number of run instructions completed.
+event:0X0215 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP33 : (Group 33 pm_freq1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 34 pm_freq2, Frequency events
+event:0X0220 counters:0 um:zero minimum:1000 name:PM_POWER_EVENT1_GRP34 : (Group 34 pm_freq2) Power Management Event 1
+event:0X0221 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP34 : (Group 34 pm_freq2) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
+event:0X0222 counters:2 um:zero minimum:1000 name:PM_DISP_HELD_THERMAL_GRP34 : (Group 34 pm_freq2) Dispatch Held due to Thermal
+event:0X0223 counters:3 um:zero minimum:1000 name:PM_FREQ_UP_GRP34 : (Group 34 pm_freq2) Processor frequency was sped up due to power management
+event:0X0224 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP34 : (Group 34 pm_freq2) Number of run instructions completed.
+event:0X0225 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP34 : (Group 34 pm_freq2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 35 pm_L1_ref, L1 references
+event:0X0230 counters:0 um:zero minimum:1000 name:PM_LD_REF_L1_GRP35 : (Group 35 pm_L1_ref) L1 D cache load references counted at finish
+event:0X0231 counters:1 um:zero minimum:1000 name:PM_LD_REF_L1_LSU0_GRP35 : (Group 35 pm_L1_ref) Load references to Level 1 Data Cache, by unit 0.
+event:0X0232 counters:2 um:zero minimum:1000 name:PM_LD_REF_L1_LSU1_GRP35 : (Group 35 pm_L1_ref) Load references to Level 1 Data Cache, by unit 1.
+event:0X0233 counters:3 um:zero minimum:1000 name:PM_LSU_TWO_TABLEWALK_CYC_GRP35 : (Group 35 pm_L1_ref) Cycles when two tablewalks pending on this thread
+event:0X0234 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP35 : (Group 35 pm_L1_ref) Number of run instructions completed.
+event:0X0235 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP35 : (Group 35 pm_L1_ref) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 36 pm_flush1, Flushes
+event:0X0240 counters:0 um:zero minimum:1000 name:PM_FLUSH_DISP_SYNC_GRP36 : (Group 36 pm_flush1) Dispatch Flush: Sync
+event:0X0241 counters:1 um:zero minimum:1000 name:PM_FLUSH_DISP_TLBIE_GRP36 : (Group 36 pm_flush1) Dispatch Flush: TLBIE
+event:0X0242 counters:2 um:zero minimum:1000 name:PM_FLUSH_DISP_SB_GRP36 : (Group 36 pm_flush1) Dispatch Flush: Scoreboard
+event:0X0243 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP36 : (Group 36 pm_flush1) Flushes occurred including LSU and Branch flushes.
+event:0X0244 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP36 : (Group 36 pm_flush1) Number of run instructions completed.
+event:0X0245 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP36 : (Group 36 pm_flush1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 37 pm_flush2, Flushes
+event:0X0250 counters:0 um:zero minimum:1000 name:PM_FLUSH_PARTIAL_GRP37 : (Group 37 pm_flush2) Partial flush
+event:0X0251 counters:1 um:zero minimum:1000 name:PM_FLUSH_DISP_GRP37 : (Group 37 pm_flush2) Dispatch flush
+event:0X0252 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP37 : (Group 37 pm_flush2) A flush was initiated by the Load Store Unit.
+event:0X0253 counters:3 um:zero minimum:1000 name:PM_LSU_PARTIAL_CDF_GRP37 : (Group 37 pm_flush2) A partial cacheline was returned from the L3
+event:0X0254 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP37 : (Group 37 pm_flush2) Number of run instructions completed.
+event:0X0255 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP37 : (Group 37 pm_flush2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 38 pm_flush, Flushes
+event:0X0260 counters:0 um:zero minimum:1000 name:PM_FLUSH_DISP_GRP38 : (Group 38 pm_flush) Dispatch flush
+event:0X0261 counters:1 um:zero minimum:10000 name:PM_CYC_GRP38 : (Group 38 pm_flush) Processor Cycles
+event:0X0262 counters:2 um:zero minimum:1000 name:PM_FLUSH_COMPLETION_GRP38 : (Group 38 pm_flush) Completion Flush
+event:0X0263 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP38 : (Group 38 pm_flush) Flushes occurred including LSU and Branch flushes.
+event:0X0264 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP38 : (Group 38 pm_flush) Number of run instructions completed.
+event:0X0265 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP38 : (Group 38 pm_flush) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 39 pm_lsu_flush1, LSU Flush
+event:0X0270 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP39 : (Group 39 pm_lsu_flush1) A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.
+event:0X0271 counters:1 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP39 : (Group 39 pm_lsu_flush1) A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.
+event:0X0272 counters:2 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP39 : (Group 39 pm_lsu_flush1) Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1.
+event:0X0273 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP39 : (Group 39 pm_lsu_flush1) Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1.
+event:0X0274 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP39 : (Group 39 pm_lsu_flush1) Number of run instructions completed.
+event:0X0275 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP39 : (Group 39 pm_lsu_flush1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 40 pm_lsu_flush2, LSU Flush ULD
+event:0X0280 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_ULD_GRP40 : (Group 40 pm_lsu_flush2) A load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1). Combined Unit 0 + 1.
+event:0X0281 counters:1 um:zero minimum:1000 name:PM_LSU0_FLUSH_ULD_GRP40 : (Group 40 pm_lsu_flush2) A load was flushed from unit 0 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1)
+event:0X0282 counters:2 um:zero minimum:1000 name:PM_LSU1_FLUSH_ULD_GRP40 : (Group 40 pm_lsu_flush2) A load was flushed from unit 1 because it was unaligned (crossed a 64 byte boundary, or 32 byte if it missed the L1).
+event:0X0283 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP40 : (Group 40 pm_lsu_flush2) Flushes occurred including LSU and Branch flushes.
+event:0X0284 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP40 : (Group 40 pm_lsu_flush2) Number of run instructions completed.
+event:0X0285 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP40 : (Group 40 pm_lsu_flush2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 41 pm_lsu_flush3, LSU Flush UST
+event:0X0290 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_UST_GRP41 : (Group 41 pm_lsu_flush3) A store was flushed because it was unaligned (crossed a 4K boundary). Combined Unit 0 + 1.
+event:0X0291 counters:1 um:zero minimum:1000 name:PM_LSU0_FLUSH_UST_GRP41 : (Group 41 pm_lsu_flush3) A store was flushed from unit 0 because it was unaligned (crossed a 4K boundary).
+event:0X0292 counters:2 um:zero minimum:1000 name:PM_LSU1_FLUSH_UST_GRP41 : (Group 41 pm_lsu_flush3) A store was flushed from unit 1 because it was unaligned (crossed a 4K boundary)
+event:0X0293 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP41 : (Group 41 pm_lsu_flush3) Flushes occurred including LSU and Branch flushes.
+event:0X0294 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP41 : (Group 41 pm_lsu_flush3) Number of run instructions completed.
+event:0X0295 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP41 : (Group 41 pm_lsu_flush3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 42 pm_lsu_flush4, LSU Flush LRQ
+event:0X02A0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_LRQ_GRP42 : (Group 42 pm_lsu_flush4) Load Hit Load or Store Hit Load flush. A younger load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte. Combined Unit 0 + 1.
+event:0X02A1 counters:1 um:zero minimum:1000 name:PM_LSU0_FLUSH_LRQ_GRP42 : (Group 42 pm_lsu_flush4) Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 0 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.
+event:0X02A2 counters:2 um:zero minimum:1000 name:PM_LSU1_FLUSH_LRQ_GRP42 : (Group 42 pm_lsu_flush4) Load Hit Load or Store Hit Load flush. A younger load was flushed from unit 1 because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.
+event:0X02A3 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP42 : (Group 42 pm_lsu_flush4) Flushes occurred including LSU and Branch flushes.
+event:0X02A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP42 : (Group 42 pm_lsu_flush4) Number of run instructions completed.
+event:0X02A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP42 : (Group 42 pm_lsu_flush4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 43 pm_lsu_flush5, LSU Flush SRQ
+event:0X02B0 counters:0 um:zero minimum:1000 name:PM_LSU_FLUSH_SRQ_GRP43 : (Group 43 pm_lsu_flush5) Load Hit Store flush. A younger load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions. Combined Unit 0 + 1.
+event:0X02B1 counters:1 um:zero minimum:1000 name:PM_LSU0_FLUSH_SRQ_GRP43 : (Group 43 pm_lsu_flush5) Load Hit Store flush. A younger load was flushed from unit 0 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions.
+event:0X02B2 counters:2 um:zero minimum:1000 name:PM_LSU1_FLUSH_SRQ_GRP43 : (Group 43 pm_lsu_flush5) Load Hit Store flush. A younger load was flushed from unit 1 because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions.
+event:0X02B3 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP43 : (Group 43 pm_lsu_flush5) Flushes occurred including LSU and Branch flushes.
+event:0X02B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP43 : (Group 43 pm_lsu_flush5) Number of run instructions completed.
+event:0X02B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP43 : (Group 43 pm_lsu_flush5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 44 pm_prefetch, I cache Prefetches
+event:0X02C0 counters:0 um:zero minimum:1000 name:PM_IC_DEMAND_CYC_GRP44 : (Group 44 pm_prefetch) Cycles when a demand ifetch was pending
+event:0X02C1 counters:1 um:zero minimum:1000 name:PM_IC_PREF_REQ_GRP44 : (Group 44 pm_prefetch) An instruction prefetch request has been made.
+event:0X02C2 counters:2 um:zero minimum:1000 name:PM_IC_RELOAD_SHR_GRP44 : (Group 44 pm_prefetch) An Instruction Cache request was made by this thread and the cache line was already in the cache for the other thread. The line is marked valid for all threads.
+event:0X02C3 counters:3 um:zero minimum:1000 name:PM_IC_PREF_WRITE_GRP44 : (Group 44 pm_prefetch) Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.
+event:0X02C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP44 : (Group 44 pm_prefetch) Number of run instructions completed.
+event:0X02C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP44 : (Group 44 pm_prefetch) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 45 pm_thread_cyc2, Thread cycles
+event:0X02D0 counters:0 um:zero minimum:1000 name:PM_THRD_GRP_CMPL_BOTH_CYC_GRP45 : (Group 45 pm_thread_cyc2) Cycles that both threads completed.
+event:0X02D1 counters:1 um:zero minimum:1000 name:PM_THRD_ALL_RUN_CYC_GRP45 : (Group 45 pm_thread_cyc2) Cycles when all threads had their run latches set. Operating systems use the run latch to indicate when they are doing useful work.
+event:0X02D2 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP45 : (Group 45 pm_thread_cyc2) Instructions completed by this thread when both threads had their run latches set.
+event:0X02D3 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_0_1_CYC_GRP45 : (Group 45 pm_thread_cyc2) Cycles thread running at priority level 0 or 1
+event:0X02D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP45 : (Group 45 pm_thread_cyc2) Number of run instructions completed.
+event:0X02D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP45 : (Group 45 pm_thread_cyc2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 46 pm_thread_cyc5, Thread cycles
+event:0X02E0 counters:0 um:zero minimum:1000 name:PM_THRD_PRIO_0_1_CYC_GRP46 : (Group 46 pm_thread_cyc5) Cycles thread running at priority level 0 or 1
+event:0X02E1 counters:1 um:zero minimum:1000 name:PM_THRD_PRIO_2_3_CYC_GRP46 : (Group 46 pm_thread_cyc5) Cycles thread running at priority level 2 or 3
+event:0X02E2 counters:2 um:zero minimum:1000 name:PM_THRD_PRIO_4_5_CYC_GRP46 : (Group 46 pm_thread_cyc5) Cycles thread running at priority level 4 or 5
+event:0X02E3 counters:3 um:zero minimum:1000 name:PM_THRD_PRIO_6_7_CYC_GRP46 : (Group 46 pm_thread_cyc5) Cycles thread running at priority level 6 or 7
+event:0X02E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP46 : (Group 46 pm_thread_cyc5) Number of run instructions completed.
+event:0X02E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP46 : (Group 46 pm_thread_cyc5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 47 pm_fxu1, FXU events
+event:0X02F0 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP47 : (Group 47 pm_fxu1) FXU0 and FXU1 are both idle.
+event:0X02F1 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP47 : (Group 47 pm_fxu1) Cycles when both FXU0 and FXU1 are busy.
+event:0X02F2 counters:2 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP47 : (Group 47 pm_fxu1) FXU0 is busy while FXU1 was idle
+event:0X02F3 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP47 : (Group 47 pm_fxu1) FXU0 was idle while FXU1 was busy
+event:0X02F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP47 : (Group 47 pm_fxu1) Number of run instructions completed.
+event:0X02F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP47 : (Group 47 pm_fxu1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 48 pm_fxu2, FXU events
+event:0X0300 counters:0 um:zero minimum:1000 name:PM_FXU0_FIN_GRP48 : (Group 48 pm_fxu2) The Fixed Point unit 0 finished an instruction and produced a result. Instructions that finish may not necessary complete.
+event:0X0301 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP48 : (Group 48 pm_fxu2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0302 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP48 : (Group 48 pm_fxu2) Number of PowerPC Instructions that completed.
+event:0X0303 counters:3 um:zero minimum:1000 name:PM_FXU1_FIN_GRP48 : (Group 48 pm_fxu2) The Fixed Point unit 1 finished an instruction and produced a result. Instructions that finish may not necessary complete.
+event:0X0304 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP48 : (Group 48 pm_fxu2) Number of run instructions completed.
+event:0X0305 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP48 : (Group 48 pm_fxu2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 49 pm_fxu3, FXU events
+event:0X0310 counters:0 um:zero minimum:10000 name:PM_CYC_GRP49 : (Group 49 pm_fxu3) Processor Cycles
+event:0X0311 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP49 : (Group 49 pm_fxu3) Cycles when both FXU0 and FXU1 are busy.
+event:0X0312 counters:2 um:zero minimum:1000 name:PM_FXU0_BUSY_FXU1_IDLE_GRP49 : (Group 49 pm_fxu3) FXU0 is busy while FXU1 was idle
+event:0X0313 counters:3 um:zero minimum:1000 name:PM_FXU1_BUSY_FXU0_IDLE_GRP49 : (Group 49 pm_fxu3) FXU0 was idle while FXU1 was busy
+event:0X0314 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP49 : (Group 49 pm_fxu3) Number of run instructions completed.
+event:0X0315 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP49 : (Group 49 pm_fxu3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 50 pm_fxu4, FXU events
+event:0X0320 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP50 : (Group 50 pm_fxu4) FXU0 and FXU1 are both idle.
+event:0X0321 counters:1 um:zero minimum:1000 name:PM_FXU_BUSY_GRP50 : (Group 50 pm_fxu4) Cycles when both FXU0 and FXU1 are busy.
+event:0X0322 counters:2 um:zero minimum:10000 name:PM_CYC_GRP50 : (Group 50 pm_fxu4) Processor Cycles
+event:0X0323 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP50 : (Group 50 pm_fxu4) Number of PowerPC Instructions that completed.
+event:0X0324 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP50 : (Group 50 pm_fxu4) Number of run instructions completed.
+event:0X0325 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP50 : (Group 50 pm_fxu4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 51 pm_L2_RCLD, L2 RC load events
+event:0X0330 counters:0 um:zero minimum:1000 name:PM_L2_RCLD_DISP_GRP51 : (Group 51 pm_L2_RCLD) L2 RC load dispatch attempt
+event:0X0331 counters:1 um:zero minimum:1000 name:PM_L2_RCLD_DISP_FAIL_OTHER_GRP51 : (Group 51 pm_L2_RCLD) L2 RC load dispatch attempt failed due to other reasons
+event:0X0332 counters:2 um:zero minimum:1000 name:PM_L2_RCST_DISP_GRP51 : (Group 51 pm_L2_RCLD) L2 RC store dispatch attempt
+event:0X0333 counters:3 um:zero minimum:1000 name:PM_L2_RCLD_BUSY_RC_FULL_GRP51 : (Group 51 pm_L2_RCLD) L2 activated Busy to the core for loads due to all RC full
+event:0X0334 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP51 : (Group 51 pm_L2_RCLD) Number of run instructions completed.
+event:0X0335 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP51 : (Group 51 pm_L2_RCLD) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 52 pm_L2_RC, RC related events
+event:0X0340 counters:0 um:zero minimum:1000 name:PM_L2_CO_FAIL_BUSY_GRP52 : (Group 52 pm_L2_RC) L2 RC Cast Out dispatch attempt failed due to all CO machines busy
+event:0X0341 counters:1 um:zero minimum:10000 name:PM_CYC_GRP52 : (Group 52 pm_L2_RC) Processor Cycles
+event:0X0342 counters:2 um:zero minimum:1000 name:PM_L2_RC_ST_DONE_GRP52 : (Group 52 pm_L2_RC) RC did st to line that was Tx or Sx
+event:0X0343 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP52 : (Group 52 pm_L2_RC) Number of PowerPC Instructions that completed.
+event:0X0344 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP52 : (Group 52 pm_L2_RC) Number of run instructions completed.
+event:0X0345 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP52 : (Group 52 pm_L2_RC) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 53 pm_L2_RCST, L2 RC Store Events
+event:0X0350 counters:0 um:zero minimum:1000 name:PM_L2_RCLD_DISP_GRP53 : (Group 53 pm_L2_RCST) L2 RC load dispatch attempt
+event:0X0351 counters:1 um:zero minimum:1000 name:PM_L2_RCLD_DISP_FAIL_OTHER_GRP53 : (Group 53 pm_L2_RCST) L2 RC load dispatch attempt failed due to other reasons
+event:0X0352 counters:2 um:zero minimum:1000 name:PM_L2_RCST_DISP_FAIL_ADDR_GRP53 : (Group 53 pm_L2_RCST) L2 RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X0353 counters:3 um:zero minimum:1000 name:PM_L2_RCST_DISP_FAIL_OTHER_GRP53 : (Group 53 pm_L2_RCST) L2 RC store dispatch attempt failed due to other reasons
+event:0X0354 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP53 : (Group 53 pm_L2_RCST) Number of run instructions completed.
+event:0X0355 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP53 : (Group 53 pm_L2_RCST) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 54 pm_L2_ldst_1, L2 load/store
+event:0X0360 counters:0 um:zero minimum:1000 name:PM_L2_ST_GRP54 : (Group 54 pm_L2_ldst_1) Data Store Count
+event:0X0361 counters:1 um:zero minimum:1000 name:PM_L2_LD_MISS_GRP54 : (Group 54 pm_L2_ldst_1) Data Load Miss
+event:0X0362 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP54 : (Group 54 pm_L2_ldst_1) Number of PowerPC Instructions that completed.
+event:0X0363 counters:3 um:zero minimum:10000 name:PM_CYC_GRP54 : (Group 54 pm_L2_ldst_1) Processor Cycles
+event:0X0364 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP54 : (Group 54 pm_L2_ldst_1) Number of run instructions completed.
+event:0X0365 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP54 : (Group 54 pm_L2_ldst_1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 55 pm_L2_ldst_2, L2 load/store
+event:0X0370 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP55 : (Group 55 pm_L2_ldst_2) Number of PowerPC Instructions that completed.
+event:0X0371 counters:1 um:zero minimum:10000 name:PM_CYC_GRP55 : (Group 55 pm_L2_ldst_2) Processor Cycles
+event:0X0372 counters:2 um:zero minimum:1000 name:PM_L2_LD_HIT_GRP55 : (Group 55 pm_L2_ldst_2) A load request (data or instruction) hit in the L2 directory. Includes speculative, prefetched, and demand requests. This event includes all requests to this L2 from all sources. Total for all slices
+event:0X0373 counters:3 um:zero minimum:1000 name:PM_L2_ST_HIT_GRP55 : (Group 55 pm_L2_ldst_2) A store request hit in the L2 directory. This event includes all requests to this L2 from all sources. Total for all slices.
+event:0X0374 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP55 : (Group 55 pm_L2_ldst_2) Number of run instructions completed.
+event:0X0375 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP55 : (Group 55 pm_L2_ldst_2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 56 pm_L2_ldst_3, L2 load/store
+event:0X0380 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP56 : (Group 56 pm_L2_ldst_3) Number of PowerPC Instructions that completed.
+event:0X0381 counters:1 um:zero minimum:10000 name:PM_CYC_GRP56 : (Group 56 pm_L2_ldst_3) Processor Cycles
+event:0X0382 counters:2 um:zero minimum:1000 name:PM_L2_LD_DISP_GRP56 : (Group 56 pm_L2_ldst_3) All successful load dispatches
+event:0X0383 counters:3 um:zero minimum:1000 name:PM_L2_ST_DISP_GRP56 : (Group 56 pm_L2_ldst_3) All successful store dispatches
+event:0X0384 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP56 : (Group 56 pm_L2_ldst_3) Number of run instructions completed.
+event:0X0385 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP56 : (Group 56 pm_L2_ldst_3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 57 pm_L2_RCSTLD, L2 RC Load/Store Events
+event:0X0390 counters:0 um:zero minimum:1000 name:PM_L2_RCLD_DISP_FAIL_ADDR_GRP57 : (Group 57 pm_L2_RCSTLD) L2 RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ
+event:0X0391 counters:1 um:zero minimum:1000 name:PM_L2_RCST_BUSY_RC_FULL_GRP57 : (Group 57 pm_L2_RCSTLD) L2 activated Busy to the core for stores due to all RC full
+event:0X0392 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP57 : (Group 57 pm_L2_RCSTLD) Number of PowerPC Instructions that completed.
+event:0X0393 counters:3 um:zero minimum:10000 name:PM_CYC_GRP57 : (Group 57 pm_L2_RCSTLD) Processor Cycles
+event:0X0394 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP57 : (Group 57 pm_L2_RCSTLD) Number of run instructions completed.
+event:0X0395 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP57 : (Group 57 pm_L2_RCSTLD) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 58 pm_nest1, Nest Events
+event:0X03A0 counters:0 um:zero minimum:1000 name:PM_PB_NODE_PUMP_GRP58 : (Group 58 pm_nest1) Nest events (MC0/MC1/PB/GX), Pair0 Bit0
+event:0X03A1 counters:1 um:zero minimum:1000 name:PM_PB_SYS_PUMP_GRP58 : (Group 58 pm_nest1) Nest events (MC0/MC1/PB/GX), Pair1 Bit0
+event:0X03A2 counters:2 um:zero minimum:1000 name:PM_PB_RETRY_NODE_PUMP_GRP58 : (Group 58 pm_nest1) Nest events (MC0/MC1/PB/GX), Pair2 Bit0
+event:0X03A3 counters:3 um:zero minimum:1000 name:PM_PB_RETRY_SYS_PUMP_GRP58 : (Group 58 pm_nest1) Nest events (MC0/MC1/PB/GX), Pair3 Bit0
+event:0X03A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP58 : (Group 58 pm_nest1) Number of run instructions completed.
+event:0X03A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP58 : (Group 58 pm_nest1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 59 pm_nest2, Nest Events
+event:0X03B0 counters:0 um:zero minimum:1000 name:PM_MEM0_RQ_DISP_GRP59 : (Group 59 pm_nest2) Nest events (MC0/MC1/PB/GX), Pair0 Bit1
+event:0X03B1 counters:1 um:zero minimum:1000 name:PM_MEM0_PREFETCH_DISP_GRP59 : (Group 59 pm_nest2) Nest events (MC0/MC1/PB/GX), Pair1 Bit1
+event:0X03B2 counters:2 um:zero minimum:1000 name:PM_MEM0_RD_CANCEL_TOTAL_GRP59 : (Group 59 pm_nest2) Nest events (MC0/MC1/PB/GX), Pair2 Bit1
+event:0X03B3 counters:3 um:zero minimum:1000 name:PM_MEM0_WQ_DISP_GRP59 : (Group 59 pm_nest2) Nest events (MC0/MC1/PB/GX), Pair3 Bit1
+event:0X03B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP59 : (Group 59 pm_nest2) Number of run instructions completed.
+event:0X03B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP59 : (Group 59 pm_nest2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 60 pm_nest3, Nest Events
+event:0X03C0 counters:0 um:zero minimum:1000 name:PM_NEST_PAIR0_ADD_GRP60 : (Group 60 pm_nest3) Nest events (MC0/MC1/PB/GX), Pair0 ADD
+event:0X03C1 counters:1 um:zero minimum:1000 name:PM_NEST_PAIR1_ADD_GRP60 : (Group 60 pm_nest3) Nest events (MC0/MC1/PB/GX), Pair1 ADD
+event:0X03C2 counters:2 um:zero minimum:1000 name:PM_NEST_PAIR2_ADD_GRP60 : (Group 60 pm_nest3) Nest events (MC0/MC1/PB/GX), Pair2 ADD
+event:0X03C3 counters:3 um:zero minimum:1000 name:PM_NEST_PAIR3_ADD_GRP60 : (Group 60 pm_nest3) Nest events (MC0/MC1/PB/GX), Pair3 ADD
+event:0X03C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP60 : (Group 60 pm_nest3) Number of run instructions completed.
+event:0X03C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP60 : (Group 60 pm_nest3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 61 pm_nest4, Nest Events
+event:0X03D0 counters:0 um:zero minimum:1000 name:PM_NEST_PAIR0_AND_GRP61 : (Group 61 pm_nest4) Nest events (MC0/MC1/PB/GX), Pair0 AND
+event:0X03D1 counters:1 um:zero minimum:1000 name:PM_NEST_PAIR1_AND_GRP61 : (Group 61 pm_nest4) Nest events (MC0/MC1/PB/GX), Pair1 AND
+event:0X03D2 counters:2 um:zero minimum:1000 name:PM_NEST_PAIR2_AND_GRP61 : (Group 61 pm_nest4) Nest events (MC0/MC1/PB/GX), Pair2 AND
+event:0X03D3 counters:3 um:zero minimum:1000 name:PM_NEST_PAIR3_AND_GRP61 : (Group 61 pm_nest4) Nest events (MC0/MC1/PB/GX), Pair3 AND
+event:0X03D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP61 : (Group 61 pm_nest4) Number of run instructions completed.
+event:0X03D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP61 : (Group 61 pm_nest4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 62 pm_L2_redir_pref, L2 redirect and prefetch
+event:0X03E0 counters:0 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BHT_REDIRECT_GRP62 : (Group 62 pm_L2_redir_pref) A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (CR mispredict).
+event:0X03E1 counters:1 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_REDIRECT_GRP62 : (Group 62 pm_L2_redir_pref) A demand (not prefetch) miss to the instruction cache was sent to the L2 as a result of a branch prediction redirect (either ALL mispredicted or Target).
+event:0X03E2 counters:2 um:zero minimum:1000 name:PM_IC_DEMAND_REQ_GRP62 : (Group 62 pm_L2_redir_pref) Demand Instruction fetch request
+event:0X03E3 counters:3 um:zero minimum:1000 name:PM_IC_BANK_CONFLICT_GRP62 : (Group 62 pm_L2_redir_pref) Read blocked due to interleave conflict.
+event:0X03E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP62 : (Group 62 pm_L2_redir_pref) Number of run instructions completed.
+event:0X03E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP62 : (Group 62 pm_L2_redir_pref) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 63 pm_dlatencies1, Data latencies
+event:0X03F0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP63 : (Group 63 pm_dlatencies1) The processor's Data Cache was reloaded from the local L2 due to a demand load.
+event:0X03F1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP63 : (Group 63 pm_dlatencies1) Number of PowerPC instructions successfully dispatched.
+event:0X03F2 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP63 : (Group 63 pm_dlatencies1) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X03F3 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP63 : (Group 63 pm_dlatencies1) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X03F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP63 : (Group 63 pm_dlatencies1) Number of run instructions completed.
+event:0X03F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP63 : (Group 63 pm_dlatencies1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 64 pm_dlatencies2, Data latencies
+event:0X0400 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP64 : (Group 64 pm_dlatencies2) The processor's Data Cache was reloaded from the local L3 due to a demand load.
+event:0X0401 counters:1 um:zero minimum:10000 name:PM_CYC_GRP64 : (Group 64 pm_dlatencies2) Processor Cycles
+event:0X0402 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP64 : (Group 64 pm_dlatencies2) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X0403 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP64 : (Group 64 pm_dlatencies2) Number of PowerPC Instructions that completed.
+event:0X0404 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP64 : (Group 64 pm_dlatencies2) Number of run instructions completed.
+event:0X0405 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP64 : (Group 64 pm_dlatencies2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 65 pm_dlatencies3, Data latencies
+event:0X0410 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP65 : (Group 65 pm_dlatencies3) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load
+event:0X0411 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP65 : (Group 65 pm_dlatencies3) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
+event:0X0412 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP65 : (Group 65 pm_dlatencies3) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X0413 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP65 : (Group 65 pm_dlatencies3) Number of PowerPC Instructions that completed.
+event:0X0414 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP65 : (Group 65 pm_dlatencies3) Number of run instructions completed.
+event:0X0415 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP65 : (Group 65 pm_dlatencies3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 66 pm_rejects1, Reject event
+event:0X0420 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_GRP66 : (Group 66 pm_rejects1) The Load Store Unit rejected an instruction. Combined Unit 0 + 1
+event:0X0421 counters:1 um:zero minimum:1000 name:PM_LSU0_REJECT_LHS_GRP66 : (Group 66 pm_rejects1) Load Store Unit 0 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
+event:0X0422 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_LHS_GRP66 : (Group 66 pm_rejects1) Load Store Unit 1 rejected a load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully.
+event:0X0423 counters:3 um:zero minimum:1000 name:PM_LSU_REJECT_LHS_GRP66 : (Group 66 pm_rejects1) The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1
+event:0X0424 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP66 : (Group 66 pm_rejects1) Number of run instructions completed.
+event:0X0425 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP66 : (Group 66 pm_rejects1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 67 pm_rejects2, Reject events
+event:0X0430 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_GRP67 : (Group 67 pm_rejects2) The Load Store Unit rejected an instruction. Combined Unit 0 + 1
+event:0X0431 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_ERAT_MISS_GRP67 : (Group 67 pm_rejects2) Total cycles the Load Store Unit is busy rejecting instructions due to an ERAT miss. Combined unit 0 + 1. Requests that miss the Derat are rejected and retried until the request hits in the Erat.
+event:0X0432 counters:2 um:zero minimum:1000 name:PM_LSU_REJECT_SET_MPRED_GRP67 : (Group 67 pm_rejects2) The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
+event:0X0433 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP67 : (Group 67 pm_rejects2) The Store Request Queue is empty
+event:0X0434 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP67 : (Group 67 pm_rejects2) Number of run instructions completed.
+event:0X0435 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP67 : (Group 67 pm_rejects2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 68 pm_rejects3, Set mispredictions rejects
+event:0X0440 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_SET_MPRED_GRP68 : (Group 68 pm_rejects3) The Load Store Unit rejected an instruction because the cache set was improperly predicted. This is a fast reject and will be immediately redispatched. Combined Unit 0 + 1
+event:0X0441 counters:1 um:zero minimum:1000 name:PM_LSU_SET_MPRED_GRP68 : (Group 68 pm_rejects3) Line already in cache at reload time
+event:0X0442 counters:2 um:zero minimum:10000 name:PM_CYC_GRP68 : (Group 68 pm_rejects3) Processor Cycles
+event:0X0443 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP68 : (Group 68 pm_rejects3) Number of PowerPC Instructions that completed.
+event:0X0444 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP68 : (Group 68 pm_rejects3) Number of run instructions completed.
+event:0X0445 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP68 : (Group 68 pm_rejects3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 69 pm_lsu_reject, LSU Reject Event
+event:0X0450 counters:0 um:zero minimum:1000 name:PM_LSU_REJECT_LMQ_FULL_GRP69 : (Group 69 pm_lsu_reject) Total cycles the Load Store Unit is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all the eight entries are full, subsequent load instructions are rejected. Combined unit 0 + 1.
+event:0X0451 counters:1 um:zero minimum:1000 name:PM_LSU0_REJECT_LMQ_FULL_GRP69 : (Group 69 pm_lsu_reject) Total cycles the Load Store Unit 0 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.
+event:0X0452 counters:2 um:zero minimum:1000 name:PM_LSU1_REJECT_LMQ_FULL_GRP69 : (Group 69 pm_lsu_reject) Total cycles the Load Store Unit 1 is busy rejecting instructions because the Load Miss Queue was full. The LMQ has eight entries. If all eight entries are full, subsequent load instructions are rejected.
+event:0X0453 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP69 : (Group 69 pm_lsu_reject) Number of PowerPC Instructions that completed.
+event:0X0454 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP69 : (Group 69 pm_lsu_reject) Number of run instructions completed.
+event:0X0455 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP69 : (Group 69 pm_lsu_reject) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 70 pm_lsu_ncld, Non cachable loads
+event:0X0460 counters:0 um:zero minimum:1000 name:PM_LSU_NCLD_GRP70 : (Group 70 pm_lsu_ncld) A non-cacheable load was executed. Combined Unit 0 + 1.
+event:0X0461 counters:1 um:zero minimum:1000 name:PM_LSU0_NCLD_GRP70 : (Group 70 pm_lsu_ncld) A non-cacheable load was executed by unit 0.
+event:0X0462 counters:2 um:zero minimum:1000 name:PM_LSU1_NCLD_GRP70 : (Group 70 pm_lsu_ncld) A non-cacheable load was executed by Unit 0.
+event:0X0463 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP70 : (Group 70 pm_lsu_ncld) Number of PowerPC Instructions that completed.
+event:0X0464 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP70 : (Group 70 pm_lsu_ncld) Number of run instructions completed.
+event:0X0465 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP70 : (Group 70 pm_lsu_ncld) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 71 pm_gct1, GCT events
+event:0X0470 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP71 : (Group 71 pm_gct1) Cycles when the Global Completion Table has no slots from this thread.
+event:0X0471 counters:1 um:zero minimum:1000 name:PM_GCT_EMPTY_CYC_GRP71 : (Group 71 pm_gct1) Cycles when the Global Completion Table was completely empty. No thread had an entry allocated.
+event:0X0472 counters:2 um:zero minimum:1000 name:PM_GCT_FULL_CYC_GRP71 : (Group 71 pm_gct1) The Global Completion Table is completely full.
+event:0X0473 counters:3 um:zero minimum:10000 name:PM_CYC_GRP71 : (Group 71 pm_gct1) Processor Cycles
+event:0X0474 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP71 : (Group 71 pm_gct1) Number of run instructions completed.
+event:0X0475 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP71 : (Group 71 pm_gct1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 72 pm_gct2, GCT Events
+event:0X0480 counters:0 um:zero minimum:1000 name:PM_GCT_UTIL_1_TO_2_SLOTS_GRP72 : (Group 72 pm_gct2) GCT Utilization 1-2 entries
+event:0X0481 counters:1 um:zero minimum:1000 name:PM_GCT_UTIL_3_TO_6_SLOTS_GRP72 : (Group 72 pm_gct2) GCT Utilization 3-6 entries
+event:0X0482 counters:2 um:zero minimum:1000 name:PM_GCT_UTIL_7_TO_10_SLOTS_GRP72 : (Group 72 pm_gct2) GCT Utilization 7-10 entries
+event:0X0483 counters:3 um:zero minimum:1000 name:PM_GCT_UTIL_11_PLUS_SLOTS_GRP72 : (Group 72 pm_gct2) GCT Utilization 11+ entries
+event:0X0484 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP72 : (Group 72 pm_gct2) Number of run instructions completed.
+event:0X0485 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP72 : (Group 72 pm_gct2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 73 pm_L2_castout_invalidate_1, L2 castout and invalidate events
+event:0X0490 counters:0 um:zero minimum:1000 name:PM_L2_CASTOUT_MOD_GRP73 : (Group 73 pm_L2_castout_invalidate_1) An L2 line in the Modified state was castout. Total for all slices.
+event:0X0491 counters:1 um:zero minimum:1000 name:PM_L2_DC_INV_GRP73 : (Group 73 pm_L2_castout_invalidate_1) The L2 invalidated a line in processor's data cache. This is caused by the L2 line being cast out or invalidated. Total for all slices
+event:0X0492 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP73 : (Group 73 pm_L2_castout_invalidate_1) Number of PowerPC Instructions that completed.
+event:0X0493 counters:3 um:zero minimum:10000 name:PM_CYC_GRP73 : (Group 73 pm_L2_castout_invalidate_1) Processor Cycles
+event:0X0494 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP73 : (Group 73 pm_L2_castout_invalidate_1) Number of run instructions completed.
+event:0X0495 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP73 : (Group 73 pm_L2_castout_invalidate_1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 74 pm_L2_castout_invalidate_2, L2 castout and invalidate events
+event:0X04A0 counters:0 um:zero minimum:1000 name:PM_L2_CASTOUT_SHR_GRP74 : (Group 74 pm_L2_castout_invalidate_2) An L2 line in the Shared state was castout. Total for all slices.
+event:0X04A1 counters:1 um:zero minimum:1000 name:PM_L2_IC_INV_GRP74 : (Group 74 pm_L2_castout_invalidate_2) Icache Invalidates from L2
+event:0X04A2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP74 : (Group 74 pm_L2_castout_invalidate_2) Number of PowerPC Instructions that completed.
+event:0X04A3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP74 : (Group 74 pm_L2_castout_invalidate_2) Processor Cycles
+event:0X04A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP74 : (Group 74 pm_L2_castout_invalidate_2) Number of run instructions completed.
+event:0X04A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP74 : (Group 74 pm_L2_castout_invalidate_2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 75 pm_disp_held1, Dispatch held conditions
+event:0X04B0 counters:0 um:zero minimum:1000 name:PM_DISP_HELD_GRP75 : (Group 75 pm_disp_held1) Dispatch Held
+event:0X04B1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP75 : (Group 75 pm_disp_held1) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
+event:0X04B2 counters:2 um:zero minimum:1000 name:PM_DISP_HELD_THERMAL_GRP75 : (Group 75 pm_disp_held1) Dispatch Held due to Thermal
+event:0X04B3 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP75 : (Group 75 pm_disp_held1) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X04B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP75 : (Group 75 pm_disp_held1) Number of run instructions completed.
+event:0X04B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP75 : (Group 75 pm_disp_held1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 76 pm_disp_held2, Dispatch held conditions
+event:0X04C0 counters:0 um:zero minimum:1000 name:PM_THERMAL_WARN_GRP76 : (Group 76 pm_disp_held2) Processor in Thermal Warning
+event:0X04C1 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP76 : (Group 76 pm_disp_held2) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
+event:0X04C2 counters:2 um:zero minimum:1000 name:PM_DISP_HELD_THERMAL_GRP76 : (Group 76 pm_disp_held2) Dispatch Held due to Thermal
+event:0X04C3 counters:3 um:zero minimum:1000 name:PM_THERMAL_MAX_GRP76 : (Group 76 pm_disp_held2) The processor experienced a thermal overload condition. This bit is sticky, it remains set until cleared by software.
+event:0X04C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP76 : (Group 76 pm_disp_held2) Number of run instructions completed.
+event:0X04C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP76 : (Group 76 pm_disp_held2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 77 pm_disp_clb_held, Display CLB held conditions
+event:0X04D0 counters:0 um:zero minimum:1000 name:PM_DISP_CLB_HELD_BAL_GRP77 : (Group 77 pm_disp_clb_held) Dispatch/CLB Hold: Balance
+event:0X04D1 counters:1 um:zero minimum:1000 name:PM_DISP_CLB_HELD_RES_GRP77 : (Group 77 pm_disp_clb_held) Dispatch/CLB Hold: Resource
+event:0X04D2 counters:2 um:zero minimum:1000 name:PM_DISP_CLB_HELD_TLBIE_GRP77 : (Group 77 pm_disp_clb_held) Dispatch Hold: Due to TLBIE
+event:0X04D3 counters:3 um:zero minimum:1000 name:PM_DISP_CLB_HELD_SYNC_GRP77 : (Group 77 pm_disp_clb_held) Dispatch/CLB Hold: Sync type instruction
+event:0X04D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP77 : (Group 77 pm_disp_clb_held) Number of run instructions completed.
+event:0X04D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP77 : (Group 77 pm_disp_clb_held) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 78 pm_power, Power Events
+event:0X04E0 counters:0 um:zero minimum:1000 name:PM_POWER_EVENT1_GRP78 : (Group 78 pm_power) Power Management Event 1
+event:0X04E1 counters:1 um:zero minimum:1000 name:PM_POWER_EVENT2_GRP78 : (Group 78 pm_power) Power Management Event 2
+event:0X04E2 counters:2 um:zero minimum:1000 name:PM_POWER_EVENT3_GRP78 : (Group 78 pm_power) Power Management Event 3
+event:0X04E3 counters:3 um:zero minimum:1000 name:PM_POWER_EVENT4_GRP78 : (Group 78 pm_power) Power Management Event 4
+event:0X04E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP78 : (Group 78 pm_power) Number of run instructions completed.
+event:0X04E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP78 : (Group 78 pm_power) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 79 pm_dispatch1, Groups and instructions dispatched
+event:0X04F0 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP79 : (Group 79 pm_dispatch1) A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X04F1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP79 : (Group 79 pm_dispatch1) Number of PowerPC instructions successfully dispatched.
+event:0X04F2 counters:2 um:zero minimum:1000 name:PM_GRP_DISP_GRP79 : (Group 79 pm_dispatch1) A group was dispatched
+event:0X04F3 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP79 : (Group 79 pm_dispatch1) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X04F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP79 : (Group 79 pm_dispatch1) Number of run instructions completed.
+event:0X04F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP79 : (Group 79 pm_dispatch1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 80 pm_dispatch2, Groups and instructions dispatched
+event:0X0500 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP80 : (Group 80 pm_dispatch2) A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X0501 counters:1 um:zero minimum:10000 name:PM_CYC_GRP80 : (Group 80 pm_dispatch2) Processor Cycles
+event:0X0502 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP80 : (Group 80 pm_dispatch2) Number of PowerPC Instructions that completed.
+event:0X0503 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP80 : (Group 80 pm_dispatch2) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X0504 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP80 : (Group 80 pm_dispatch2) Number of run instructions completed.
+event:0X0505 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP80 : (Group 80 pm_dispatch2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 81 pm_ic, I cache operations
+event:0X0510 counters:0 um:zero minimum:1000 name:PM_IC_REQ_ALL_GRP81 : (Group 81 pm_ic) Icache requests, prefetch + demand
+event:0X0511 counters:1 um:zero minimum:1000 name:PM_IC_WRITE_ALL_GRP81 : (Group 81 pm_ic) Icache sectors written, prefetch + demand
+event:0X0512 counters:2 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_ALL_GRP81 : (Group 81 pm_ic) Prefetch Canceled due to page boundary or icache hit
+event:0X0513 counters:3 um:zero minimum:1000 name:PM_IC_DEMAND_L2_BR_ALL_GRP81 : (Group 81 pm_ic) L2 I cache demand request due to BHT or redirect
+event:0X0514 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP81 : (Group 81 pm_ic) Number of run instructions completed.
+event:0X0515 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP81 : (Group 81 pm_ic) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 82 pm_ic_pref_cancel, Instruction pre-fetched cancelled
+event:0X0520 counters:0 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_PAGE_GRP82 : (Group 82 pm_ic_pref_cancel) Prefetch Canceled due to page boundary
+event:0X0521 counters:1 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_HIT_GRP82 : (Group 82 pm_ic_pref_cancel) Prefetch Canceled due to icache hit
+event:0X0522 counters:2 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_L2_GRP82 : (Group 82 pm_ic_pref_cancel) L2 Squashed request
+event:0X0523 counters:3 um:zero minimum:1000 name:PM_IC_PREF_CANCEL_ALL_GRP82 : (Group 82 pm_ic_pref_cancel) Prefetch Canceled due to page boundary or icache hit
+event:0X0524 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP82 : (Group 82 pm_ic_pref_cancel) Number of run instructions completed.
+event:0X0525 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP82 : (Group 82 pm_ic_pref_cancel) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 83 pm_ic_miss, Icache and Ierat miss events
+event:0X0530 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP83 : (Group 83 pm_ic_miss) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
+event:0X0531 counters:1 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP83 : (Group 83 pm_ic_miss) An instruction fetch request missed the L1 cache.
+event:0X0532 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP83 : (Group 83 pm_ic_miss) Number of PowerPC Instructions that completed.
+event:0X0533 counters:3 um:zero minimum:10000 name:PM_CYC_GRP83 : (Group 83 pm_ic_miss) Processor Cycles
+event:0X0534 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP83 : (Group 83 pm_ic_miss) Number of run instructions completed.
+event:0X0535 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP83 : (Group 83 pm_ic_miss) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 84 pm_cpi_stack1, CPI stack breakdown
+event:0X0540 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP84 : (Group 84 pm_cpi_stack1) The processor's Data Cache was reloaded from the local L2 due to a demand load.
+event:0X0541 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DCACHE_MISS_GRP84 : (Group 84 pm_cpi_stack1) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a Data Cache Miss. Data Cache Miss has higher priority than any other Load/Store delay, so if an instruction encounters multiple delays only the Data Cache Miss will be reported and the entire delay period will be charged to Data Cache Miss. This is a subset of PM_CMPLU_STALL_LSU.
+event:0X0542 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP84 : (Group 84 pm_cpi_stack1) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X0543 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_ERAT_MISS_GRP84 : (Group 84 pm_cpi_stack1) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered an ERAT miss. This is a subset of PM_CMPLU_STALL_REJECT.
+event:0X0544 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP84 : (Group 84 pm_cpi_stack1) Number of run instructions completed.
+event:0X0545 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP84 : (Group 84 pm_cpi_stack1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 85 pm_cpi_stack2, CPI stack breakdown
+event:0X0550 counters:0 um:zero minimum:1000 name:PM_FXU_IDLE_GRP85 : (Group 85 pm_cpi_stack2) FXU0 and FXU1 are both idle.
+event:0X0551 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_FXU_GRP85 : (Group 85 pm_cpi_stack2) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point instruction.
+event:0X0552 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP85 : (Group 85 pm_cpi_stack2) A group completed. Microcoded instructions that span multiple groups will generate this event once per group.
+event:0X0553 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_DIV_GRP85 : (Group 85 pm_cpi_stack2) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a fixed point divide instruction. This is a subset of PM_CMPLU_STALL_FXU.
+event:0X0554 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP85 : (Group 85 pm_cpi_stack2) Number of run instructions completed.
+event:0X0555 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP85 : (Group 85 pm_cpi_stack2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 86 pm_cpi_stack3, CPI stack breakdown
+event:0X0560 counters:0 um:zero minimum:1000 name:PM_TABLEWALK_CYC_GRP86 : (Group 86 pm_cpi_stack3) Cycles doing instruction or data tablewalks
+event:0X0561 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_LSU_GRP86 : (Group 86 pm_cpi_stack3) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes was a load/store instruction.
+event:0X0562 counters:2 um:zero minimum:1000 name:PM_DATA_TABLEWALK_CYC_GRP86 : (Group 86 pm_cpi_stack3) Cycles a translation tablewalk is active. While a tablewalk is active any request attempting to access the TLB will be rejected and retried.
+event:0X0563 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_REJECT_GRP86 : (Group 86 pm_cpi_stack3) Following a completion stall (any period when no groups completed) the last instruction to finish before completion resumes suffered a load/store reject. This is a subset of PM_CMPLU_STALL_LSU.
+event:0X0564 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP86 : (Group 86 pm_cpi_stack3) Number of run instructions completed.
+event:0X0565 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP86 : (Group 86 pm_cpi_stack3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 87 pm_cpi_stack4, CPI stack breakdown
+event:0X0570 counters:0 um:zero minimum:1000 name:PM_FLOP_GRP87 : (Group 87 pm_cpi_stack4) A floating point operation has completed
+event:0X0571 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_SCALAR_LONG_GRP87 : (Group 87 pm_cpi_stack4) Completion stall caused by long latency scalar instruction
+event:0X0572 counters:2 um:zero minimum:1000 name:PM_MRK_STALL_CMPLU_CYC_GRP87 : (Group 87 pm_cpi_stack4) Marked Group Completion Stall cycles
+event:0X0573 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_SCALAR_GRP87 : (Group 87 pm_cpi_stack4) Completion stall caused by FPU instruction
+event:0X0574 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP87 : (Group 87 pm_cpi_stack4) Number of run instructions completed.
+event:0X0575 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP87 : (Group 87 pm_cpi_stack4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 88 pm_cpi_stack5, CPI stack breakdown
+event:0X0580 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_END_GCT_NOSLOT_GRP88 : (Group 88 pm_cpi_stack5) Count ended because GCT went empty
+event:0X0581 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_VECTOR_GRP88 : (Group 88 pm_cpi_stack5) Completion stall caused by Vector instruction
+event:0X0582 counters:2 um:zero minimum:1000 name:PM_MRK_STALL_CMPLU_CYC_COUNT_GRP88 : (Group 88 pm_cpi_stack5) Marked Group Completion Stall cycles (use edge detect to count #)
+event:0X0583 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_GRP88 : (Group 88 pm_cpi_stack5) No groups completed, GCT not empty
+event:0X0584 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP88 : (Group 88 pm_cpi_stack5) Number of run instructions completed.
+event:0X0585 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP88 : (Group 88 pm_cpi_stack5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 89 pm_cpi_stack6, CPI stack breakdown
+event:0X0590 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_THRD_GRP89 : (Group 89 pm_cpi_stack6) Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn
+event:0X0591 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_DFU_GRP89 : (Group 89 pm_cpi_stack6) Completion stall caused by Decimal Floating Point Unit
+event:0X0592 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP89 : (Group 89 pm_cpi_stack6) Number of PowerPC Instructions that completed.
+event:0X0593 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP89 : (Group 89 pm_cpi_stack6) No slot in GCT caused by branch mispredict or I cache miss
+event:0X0594 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP89 : (Group 89 pm_cpi_stack6) Number of run instructions completed.
+event:0X0595 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP89 : (Group 89 pm_cpi_stack6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 90 pm_cpi_stack7, CPI stack breakdown
+event:0X05A0 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP90 : (Group 90 pm_cpi_stack7) Cycles when the Global Completion Table has no slots from this thread.
+event:0X05A1 counters:1 um:zero minimum:1000 name:PM_GCT_NOSLOT_IC_MISS_GRP90 : (Group 90 pm_cpi_stack7) Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.
+event:0X05A2 counters:2 um:zero minimum:1000 name:PM_IOPS_DISP_GRP90 : (Group 90 pm_cpi_stack7) IOPS dispatched
+event:0X05A3 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_GRP90 : (Group 90 pm_cpi_stack7) Cycles when the Global Completion Table has no slots from this thread because of a branch misprediction.
+event:0X05A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP90 : (Group 90 pm_cpi_stack7) Number of run instructions completed.
+event:0X05A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP90 : (Group 90 pm_cpi_stack7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 91 pm_dsource1, Data source information
+event:0X05B0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP91 : (Group 91 pm_dsource1) The processor's Data Cache was reloaded from the local L2 due to a demand load.
+event:0X05B1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP91 : (Group 91 pm_dsource1) The processor's Data Cache was reloaded from the local L3 due to a demand load.
+event:0X05B2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP91 : (Group 91 pm_dsource1) The processor’s Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
+event:0X05B3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP91 : (Group 91 pm_dsource1) The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
+event:0X05B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP91 : (Group 91 pm_dsource1) Number of run instructions completed.
+event:0X05B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP91 : (Group 91 pm_dsource1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 92 pm_dsource2, Data source information
+event:0X05C0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP92 : (Group 92 pm_dsource2) The processor's Data Cache was reloaded from the local L3 due to a demand load.
+event:0X05C1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L31_SHR_GRP92 : (Group 92 pm_dsource2) Data loaded from another L3 on same chip shared
+event:0X05C2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP92 : (Group 92 pm_dsource2) The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
+event:0X05C3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP92 : (Group 92 pm_dsource2) The processor's Data Cache was reloaded but not from the local L2.
+event:0X05C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP92 : (Group 92 pm_dsource2) Number of run instructions completed.
+event:0X05C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP92 : (Group 92 pm_dsource2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 93 pm_dsource3, Data source information
+event:0X05D0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP93 : (Group 93 pm_dsource3) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
+event:0X05D1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP93 : (Group 93 pm_dsource3) The processor's Data Cache was reloaded from beyond L3 due to a demand load
+event:0X05D2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L21_MOD_GRP93 : (Group 93 pm_dsource3) Data loaded from another L2 on same chip modified
+event:0X05D3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP93 : (Group 93 pm_dsource3) The processor's Data Cache was reloaded but not from the local L2.
+event:0X05D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP93 : (Group 93 pm_dsource3) Number of run instructions completed.
+event:0X05D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP93 : (Group 93 pm_dsource3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 94 pm_dsource4, Data source information
+event:0X05E0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L31_MOD_GRP94 : (Group 94 pm_dsource4) Data loaded from another L3 on same chip modified
+event:0X05E1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP94 : (Group 94 pm_dsource4) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
+event:0X05E2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP94 : (Group 94 pm_dsource4) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load
+event:0X05E3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP94 : (Group 94 pm_dsource4) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load
+event:0X05E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP94 : (Group 94 pm_dsource4) Number of run instructions completed.
+event:0X05E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP94 : (Group 94 pm_dsource4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 95 pm_dsource5, Data source information
+event:0X05F0 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L31_SHR_GRP95 : (Group 95 pm_dsource5) Data loaded from another L3 on same chip shared
+event:0X05F1 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP95 : (Group 95 pm_dsource5) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
+event:0X05F2 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_GRP95 : (Group 95 pm_dsource5) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load
+event:0X05F3 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L21_SHR_GRP95 : (Group 95 pm_dsource5) Data loaded from another L2 on same chip shared
+event:0X05F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP95 : (Group 95 pm_dsource5) Number of run instructions completed.
+event:0X05F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP95 : (Group 95 pm_dsource5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 96 pm_dsource6, Data source information
+event:0X0600 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP96 : (Group 96 pm_dsource6) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load
+event:0X0601 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP96 : (Group 96 pm_dsource6) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
+event:0X0602 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L21_SHR_GRP96 : (Group 96 pm_dsource6) Data loaded from another L2 on same chip shared
+event:0X0603 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP96 : (Group 96 pm_dsource6) The processor's Data Cache was reloaded but not from the local L2.
+event:0X0604 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP96 : (Group 96 pm_dsource6) Number of run instructions completed.
+event:0X0605 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP96 : (Group 96 pm_dsource6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 97 pm_dsource7, Data source information
+event:0X0610 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP97 : (Group 97 pm_dsource7) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
+event:0X0611 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP97 : (Group 97 pm_dsource7) The processor's Data Cache was reloaded from beyond L3 due to a demand load
+event:0X0612 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP97 : (Group 97 pm_dsource7) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load
+event:0X0613 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP97 : (Group 97 pm_dsource7) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load
+event:0X0614 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP97 : (Group 97 pm_dsource7) Number of run instructions completed.
+event:0X0615 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP97 : (Group 97 pm_dsource7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 98 pm_dsource8, Data source information
+event:0X0620 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP98 : (Group 98 pm_dsource8) Number of PowerPC Instructions that completed.
+event:0X0621 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L3_GRP98 : (Group 98 pm_dsource8) The processor's Data Cache was reloaded from the local L3 due to a demand load.
+event:0X0622 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP98 : (Group 98 pm_dsource8) The processor's Data Cache was reloaded from beyond L3 due to a demand load
+event:0X0623 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP98 : (Group 98 pm_dsource8) The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
+event:0X0624 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP98 : (Group 98 pm_dsource8) Number of run instructions completed.
+event:0X0625 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP98 : (Group 98 pm_dsource8) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 99 pm_dsource9, Data source information
+event:0X0630 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP99 : (Group 99 pm_dsource9) The processor's Data Cache was reloaded from the local L2 due to a demand load.
+event:0X0631 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP99 : (Group 99 pm_dsource9) The processor's Data Cache was reloaded but not from the local L2.
+event:0X0632 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP99 : (Group 99 pm_dsource9) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X0633 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP99 : (Group 99 pm_dsource9) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
+event:0X0634 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP99 : (Group 99 pm_dsource9) Number of run instructions completed.
+event:0X0635 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP99 : (Group 99 pm_dsource9) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 100 pm_dsource10, Data source information
+event:0X0640 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP100 : (Group 100 pm_dsource10) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load
+event:0X0641 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_SHR_GRP100 : (Group 100 pm_dsource10) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a demand load
+event:0X0642 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_GRP100 : (Group 100 pm_dsource10) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load
+event:0X0643 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP100 : (Group 100 pm_dsource10) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load
+event:0X0644 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP100 : (Group 100 pm_dsource10) Number of run instructions completed.
+event:0X0645 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP100 : (Group 100 pm_dsource10) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 101 pm_dsource11, Data source information
+event:0X0650 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_L2_GRP101 : (Group 101 pm_dsource11) The processor's Data Cache was reloaded from the local L2 due to a demand load.
+event:0X0651 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP101 : (Group 101 pm_dsource11) The processor's Data Cache was reloaded but not from the local L2.
+event:0X0652 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_L3MISS_GRP101 : (Group 101 pm_dsource11) The processor's Data Cache was reloaded from beyond L3 due to a demand load
+event:0X0653 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP101 : (Group 101 pm_dsource11) Number of run instructions completed.
+event:0X0654 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP101 : (Group 101 pm_dsource11) Number of run instructions completed.
+event:0X0655 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP101 : (Group 101 pm_dsource11) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 102 pm_dsource12, Data source information
+event:0X0660 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_RL2L3_MOD_GRP102 : (Group 102 pm_dsource12) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a demand load
+event:0X0661 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP102 : (Group 102 pm_dsource12) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
+event:0X0662 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP102 : (Group 102 pm_dsource12) The processor’s Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
+event:0X0663 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP102 : (Group 102 pm_dsource12) The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
+event:0X0664 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP102 : (Group 102 pm_dsource12) Number of run instructions completed.
+event:0X0665 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP102 : (Group 102 pm_dsource12) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 103 pm_dsource13, Data source information
+event:0X0670 counters:0 um:zero minimum:1000 name:PM_DERAT_MISS_4K_GRP103 : (Group 103 pm_dsource13) A data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.
+event:0X0671 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP103 : (Group 103 pm_dsource13) Number of PowerPC Instructions that completed.
+event:0X0672 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_SHR_GRP103 : (Group 103 pm_dsource13) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a demand load
+event:0X0673 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_DL2L3_MOD_GRP103 : (Group 103 pm_dsource13) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a demand load
+event:0X0674 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP103 : (Group 103 pm_dsource13) Number of run instructions completed.
+event:0X0675 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP103 : (Group 103 pm_dsource13) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 104 pm_dsource14, Data source information
+event:0X0680 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP104 : (Group 104 pm_dsource14) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
+event:0X0681 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP104 : (Group 104 pm_dsource14) Number of PowerPC Instructions that completed.
+event:0X0682 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP104 : (Group 104 pm_dsource14) The processor’s Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
+event:0X0683 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP104 : (Group 104 pm_dsource14) The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
+event:0X0684 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP104 : (Group 104 pm_dsource14) Number of run instructions completed.
+event:0X0685 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP104 : (Group 104 pm_dsource14) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 105 pm_dsource15, Data source information
+event:0X0690 counters:0 um:zero minimum:1000 name:PM_DATA_FROM_DMEM_GRP105 : (Group 105 pm_dsource15) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a demand load
+event:0X0691 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP105 : (Group 105 pm_dsource15) Number of PowerPC Instructions that completed.
+event:0X0692 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP105 : (Group 105 pm_dsource15) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X0693 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP105 : (Group 105 pm_dsource15) The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
+event:0X0694 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP105 : (Group 105 pm_dsource15) Number of run instructions completed.
+event:0X0695 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP105 : (Group 105 pm_dsource15) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 106 pm_isource1, Instruction source information
+event:0X06A0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP106 : (Group 106 pm_isource1) An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions
+event:0X06A1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP106 : (Group 106 pm_isource1) An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions
+event:0X06A2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP106 : (Group 106 pm_isource1) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X06A3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP106 : (Group 106 pm_isource1) An instruction fetch group was fetched from beyond the local L2.
+event:0X06A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP106 : (Group 106 pm_isource1) Number of run instructions completed.
+event:0X06A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP106 : (Group 106 pm_isource1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 107 pm_isource2, Instruction source information
+event:0X06B0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP107 : (Group 107 pm_isource2) An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions
+event:0X06B1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP107 : (Group 107 pm_isource2) An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
+event:0X06B2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP107 : (Group 107 pm_isource2) An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
+event:0X06B3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP107 : (Group 107 pm_isource2) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X06B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP107 : (Group 107 pm_isource2) Number of run instructions completed.
+event:0X06B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP107 : (Group 107 pm_isource2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 108 pm_isource3, Instruction source information
+event:0X06C0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP108 : (Group 108 pm_isource3) An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
+event:0X06C1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP108 : (Group 108 pm_isource3) An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
+event:0X06C2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_SHR_GRP108 : (Group 108 pm_isource3) An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
+event:0X06C3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP108 : (Group 108 pm_isource3) An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
+event:0X06C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP108 : (Group 108 pm_isource3) Number of run instructions completed.
+event:0X06C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP108 : (Group 108 pm_isource3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 109 pm_isource4, Instruction source information
+event:0X06D0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L31_MOD_GRP109 : (Group 109 pm_isource4) Instruction fetched from another L3 on same chip modified
+event:0X06D1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L31_SHR_GRP109 : (Group 109 pm_isource4) Instruction fetched from another L3 on same chip shared
+event:0X06D2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L21_MOD_GRP109 : (Group 109 pm_isource4) Instruction fetched from another L2 on same chip modified
+event:0X06D3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L21_SHR_GRP109 : (Group 109 pm_isource4) Instruction fetched from another L2 on same chip shared
+event:0X06D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP109 : (Group 109 pm_isource4) Number of run instructions completed.
+event:0X06D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP109 : (Group 109 pm_isource4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 110 pm_isource5, Instruction source information
+event:0X06E0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L31_SHR_GRP110 : (Group 110 pm_isource5) Instruction fetched from another L3 on same chip shared
+event:0X06E1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP110 : (Group 110 pm_isource5) An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
+event:0X06E2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_L21_SHR_GRP110 : (Group 110 pm_isource5) Instruction fetched from another L2 on same chip shared
+event:0X06E3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP110 : (Group 110 pm_isource5) An instruction fetch group was fetched from beyond the local L2.
+event:0X06E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP110 : (Group 110 pm_isource5) Number of run instructions completed.
+event:0X06E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP110 : (Group 110 pm_isource5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 111 pm_isource6, Instruction source information
+event:0X06F0 counters:0 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP111 : (Group 111 pm_isource6) An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions
+event:0X06F1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP111 : (Group 111 pm_isource6) An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
+event:0X06F2 counters:2 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP111 : (Group 111 pm_isource6) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X06F3 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP111 : (Group 111 pm_isource6) An instruction fetch group was fetched from beyond the local L2.
+event:0X06F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP111 : (Group 111 pm_isource6) Number of run instructions completed.
+event:0X06F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP111 : (Group 111 pm_isource6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 112 pm_isource7, Instruction source information
+event:0X0700 counters:0 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_MOD_GRP112 : (Group 112 pm_isource7) An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
+event:0X0701 counters:1 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP112 : (Group 112 pm_isource7) An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
+event:0X0702 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_SHR_GRP112 : (Group 112 pm_isource7) An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
+event:0X0703 counters:3 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP112 : (Group 112 pm_isource7) An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
+event:0X0704 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP112 : (Group 112 pm_isource7) Number of run instructions completed.
+event:0X0705 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP112 : (Group 112 pm_isource7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 113 pm_isource8, Instruction source information
+event:0X0710 counters:0 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP113 : (Group 113 pm_isource8) An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
+event:0X0711 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3MISS_GRP113 : (Group 113 pm_isource8) An instruction fetch group was fetched from beyond L3. Fetch groups can contain up to 8 instructions.
+event:0X0712 counters:2 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP113 : (Group 113 pm_isource8) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X0713 counters:3 um:zero minimum:1000 name:PM_INST_FROM_L2MISS_GRP113 : (Group 113 pm_isource8) An instruction fetch group was fetched from beyond the local L2.
+event:0X0714 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP113 : (Group 113 pm_isource8) Number of run instructions completed.
+event:0X0715 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP113 : (Group 113 pm_isource8) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 114 pm_isource9, Instruction source information
+event:0X0720 counters:0 um:zero minimum:1000 name:PM_INST_FROM_PREF_GRP114 : (Group 114 pm_isource9) An instruction fetch group was fetched from the prefetch buffer. Fetch groups can contain up to 8 instructions
+event:0X0721 counters:1 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP114 : (Group 114 pm_isource9) An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
+event:0X0722 counters:2 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP114 : (Group 114 pm_isource9) An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X0723 counters:3 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP114 : (Group 114 pm_isource9) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X0724 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP114 : (Group 114 pm_isource9) Number of run instructions completed.
+event:0X0725 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP114 : (Group 114 pm_isource9) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 115 pm_isource10, Instruction source information
+event:0X0730 counters:0 um:zero minimum:1000 name:PM_INST_FROM_L2_GRP115 : (Group 115 pm_isource10) An instruction fetch group was fetched from L2. Fetch Groups can contain up to 8 instructions
+event:0X0731 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L3_GRP115 : (Group 115 pm_isource10) An instruction fetch group was fetched from L3. Fetch Groups can contain up to 8 instructions
+event:0X0732 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP115 : (Group 115 pm_isource10) Number of PowerPC Instructions that completed.
+event:0X0733 counters:3 um:zero minimum:10000 name:PM_CYC_GRP115 : (Group 115 pm_isource10) Processor Cycles
+event:0X0734 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP115 : (Group 115 pm_isource10) Number of run instructions completed.
+event:0X0735 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP115 : (Group 115 pm_isource10) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 116 pm_isource11, Instruction source information
+event:0X0740 counters:0 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_MOD_GRP116 : (Group 116 pm_isource11) An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
+event:0X0741 counters:1 um:zero minimum:1000 name:PM_INST_FROM_RL2L3_SHR_GRP116 : (Group 116 pm_isource11) An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a remote module. Fetch groups can contain up to 8 instructions
+event:0X0742 counters:2 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP116 : (Group 116 pm_isource11) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X0743 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP116 : (Group 116 pm_isource11) Number of PowerPC Instructions that completed.
+event:0X0744 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP116 : (Group 116 pm_isource11) Number of run instructions completed.
+event:0X0745 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP116 : (Group 116 pm_isource11) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 117 pm_isource12, Instruction source information
+event:0X0750 counters:0 um:zero minimum:10000 name:PM_CYC_GRP117 : (Group 117 pm_isource12) Processor Cycles
+event:0X0751 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP117 : (Group 117 pm_isource12) Number of PowerPC Instructions that completed.
+event:0X0752 counters:2 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_SHR_GRP117 : (Group 117 pm_isource12) An instruction fetch group was fetched with shared (S) data from the L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
+event:0X0753 counters:3 um:zero minimum:1000 name:PM_INST_FROM_DL2L3_MOD_GRP117 : (Group 117 pm_isource12) An instruction fetch group was fetched with modified (M) data from an L2 or L3 on a distant module. Fetch groups can contain up to 8 instructions
+event:0X0754 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP117 : (Group 117 pm_isource12) Number of run instructions completed.
+event:0X0755 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP117 : (Group 117 pm_isource12) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 118 pm_isource13, Instruction source information
+event:0X0760 counters:0 um:zero minimum:1000 name:PM_INST_FROM_DMEM_GRP118 : (Group 118 pm_isource13) An instruction fetch group was fetched from memory attached to a distant module. Fetch groups can contain up to 8 instructions
+event:0X0761 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP118 : (Group 118 pm_isource13) Number of PowerPC Instructions that completed.
+event:0X0762 counters:2 um:zero minimum:1000 name:PM_INST_FROM_RMEM_GRP118 : (Group 118 pm_isource13) An instruction fetch group was fetched from memory attached to a different module than this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X0763 counters:3 um:zero minimum:1000 name:PM_INST_FROM_LMEM_GRP118 : (Group 118 pm_isource13) An instruction fetch group was fetched from memory attached to the same module this proccessor is located on. Fetch groups can contain up to 8 instructions
+event:0X0764 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP118 : (Group 118 pm_isource13) Number of run instructions completed.
+event:0X0765 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP118 : (Group 118 pm_isource13) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 119 pm_prefetch1, Prefetch events
+event:0X0770 counters:0 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_ALLOC_GRP119 : (Group 119 pm_prefetch1) D cache new prefetch stream allocated
+event:0X0771 counters:1 um:zero minimum:1000 name:PM_L3_PREF_LDST_GRP119 : (Group 119 pm_prefetch1) L3 cache prefetches LD + ST
+event:0X0772 counters:2 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_CONFIRM_GRP119 : (Group 119 pm_prefetch1) Dcache new prefetch stream confirmed
+event:0X0773 counters:3 um:zero minimum:1000 name:PM_L1_PREF_GRP119 : (Group 119 pm_prefetch1) A request to prefetch data into the L1 was made
+event:0X0774 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP119 : (Group 119 pm_prefetch1) Number of run instructions completed.
+event:0X0775 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP119 : (Group 119 pm_prefetch1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 120 pm_prefetch2, Prefetch events
+event:0X0780 counters:0 um:zero minimum:1000 name:PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM_GRP120 : (Group 120 pm_prefetch2) Dcache Strided prefetch stream confirmed (software + hardware)
+event:0X0781 counters:1 um:zero minimum:1000 name:PM_LD_REF_L1_GRP120 : (Group 120 pm_prefetch2) L1 D cache load references counted at finish
+event:0X0782 counters:2 um:zero minimum:1000 name:PM_LSU_FIN_GRP120 : (Group 120 pm_prefetch2) LSU Finished an instruction (up to 2 per cycle)
+event:0X0783 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP120 : (Group 120 pm_prefetch2) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
+event:0X0784 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP120 : (Group 120 pm_prefetch2) Number of run instructions completed.
+event:0X0785 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP120 : (Group 120 pm_prefetch2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 121 pm_vsu0, VSU Execution
+event:0X0790 counters:0 um:zero minimum:1000 name:PM_VSU0_1FLOP_GRP121 : (Group 121 pm_vsu0) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished
+event:0X0791 counters:1 um:zero minimum:1000 name:PM_VSU1_1FLOP_GRP121 : (Group 121 pm_vsu0) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg, xsadd, xsmul, xssub, xscmp, xssel, xsabs, xsnabs, xsre, xssqrte, xsneg) operation finished
+event:0X0792 counters:2 um:zero minimum:1000 name:PM_VSU0_2FLOP_GRP121 : (Group 121 pm_vsu0) two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)
+event:0X0793 counters:3 um:zero minimum:1000 name:PM_VSU1_2FLOP_GRP121 : (Group 121 pm_vsu0) two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)
+event:0X0794 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP121 : (Group 121 pm_vsu0) Number of run instructions completed.
+event:0X0795 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP121 : (Group 121 pm_vsu0) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 122 pm_vsu1, VSU Execution
+event:0X07A0 counters:0 um:zero minimum:1000 name:PM_VSU0_4FLOP_GRP122 : (Group 122 pm_vsu1) four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)
+event:0X07A1 counters:1 um:zero minimum:1000 name:PM_VSU1_4FLOP_GRP122 : (Group 122 pm_vsu1) four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)
+event:0X07A2 counters:2 um:zero minimum:1000 name:PM_VSU0_8FLOP_GRP122 : (Group 122 pm_vsu1) eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)
+event:0X07A3 counters:3 um:zero minimum:1000 name:PM_VSU1_8FLOP_GRP122 : (Group 122 pm_vsu1) eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)
+event:0X07A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP122 : (Group 122 pm_vsu1) Number of run instructions completed.
+event:0X07A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP122 : (Group 122 pm_vsu1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 123 pm_vsu2, VSU Execution
+event:0X07B0 counters:0 um:zero minimum:1000 name:PM_VSU_2FLOP_GRP123 : (Group 123 pm_vsu2) two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)
+event:0X07B1 counters:1 um:zero minimum:1000 name:PM_VSU_2FLOP_DOUBLE_GRP123 : (Group 123 pm_vsu2) DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg
+event:0X07B2 counters:2 um:zero minimum:1000 name:PM_VSU0_2FLOP_DOUBLE_GRP123 : (Group 123 pm_vsu2) two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)
+event:0X07B3 counters:3 um:zero minimum:1000 name:PM_VSU1_2FLOP_DOUBLE_GRP123 : (Group 123 pm_vsu2) two flop DP vector operation (xvadddp, xvmuldp, xvsubdp, xvcmpdp, xvseldp, xvabsdp, xvnabsdp, xvredp ,xvsqrtedp, vxnegdp)
+event:0X07B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP123 : (Group 123 pm_vsu2) Number of run instructions completed.
+event:0X07B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP123 : (Group 123 pm_vsu2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 124 pm_vsu3, VSU Execution
+event:0X07C0 counters:0 um:zero minimum:1000 name:PM_VSU0_FMA_GRP124 : (Group 124 pm_vsu3) two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!
+event:0X07C1 counters:1 um:zero minimum:1000 name:PM_VSU1_FMA_GRP124 : (Group 124 pm_vsu3) two flops operation (fmadd, fnmadd, fmsub, fnmsub, xsmadd, xsnmadd, xsmsub, xsnmsub) Scalar instructions only!
+event:0X07C2 counters:2 um:zero minimum:1000 name:PM_VSU_FMA_GRP124 : (Group 124 pm_vsu3) two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!
+event:0X07C3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP124 : (Group 124 pm_vsu3) Number of PowerPC Instructions that completed.
+event:0X07C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP124 : (Group 124 pm_vsu3) Number of run instructions completed.
+event:0X07C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP124 : (Group 124 pm_vsu3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 125 pm_vsu4, VSU Execution
+event:0X07D0 counters:0 um:zero minimum:1000 name:PM_VSU0_FMA_DOUBLE_GRP125 : (Group 125 pm_vsu4) four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)
+event:0X07D1 counters:1 um:zero minimum:1000 name:PM_VSU1_FMA_DOUBLE_GRP125 : (Group 125 pm_vsu4) four flop DP vector operations (xvmadddp, xvnmadddp, xvmsubdp, xvmsubdp)
+event:0X07D2 counters:2 um:zero minimum:1000 name:PM_VSU_FMA_DOUBLE_GRP125 : (Group 125 pm_vsu4) DP vector version of fmadd,fnmadd,fmsub,fnmsub
+event:0X07D3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP125 : (Group 125 pm_vsu4) Number of PowerPC Instructions that completed.
+event:0X07D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP125 : (Group 125 pm_vsu4) Number of run instructions completed.
+event:0X07D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP125 : (Group 125 pm_vsu4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 126 pm_vsu5, VSU Execution
+event:0X07E0 counters:0 um:zero minimum:1000 name:PM_VSU_VECTOR_DOUBLE_ISSUED_GRP126 : (Group 126 pm_vsu5) Double Precision vector instruction issued on Pipe0
+event:0X07E1 counters:1 um:zero minimum:1000 name:PM_VSU0_VECT_DOUBLE_ISSUED_GRP126 : (Group 126 pm_vsu5) Double Precision vector instruction issued on Pipe0
+event:0X07E2 counters:2 um:zero minimum:1000 name:PM_VSU1_VECT_DOUBLE_ISSUED_GRP126 : (Group 126 pm_vsu5) Double Precision vector instruction issued on Pipe1
+event:0X07E3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP126 : (Group 126 pm_vsu5) Number of PowerPC Instructions that completed.
+event:0X07E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP126 : (Group 126 pm_vsu5) Number of run instructions completed.
+event:0X07E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP126 : (Group 126 pm_vsu5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 127 pm_vsu6, VSU Execution
+event:0X07F0 counters:0 um:zero minimum:1000 name:PM_VSU_DENORM_GRP127 : (Group 127 pm_vsu6) Vector or Scalar denorm operand
+event:0X07F1 counters:1 um:zero minimum:1000 name:PM_VSU0_DENORM_GRP127 : (Group 127 pm_vsu6) VSU0 received denormalized data
+event:0X07F2 counters:2 um:zero minimum:1000 name:PM_VSU1_DENORM_GRP127 : (Group 127 pm_vsu6) VSU1 received denormalized data
+event:0X07F3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP127 : (Group 127 pm_vsu6) Number of PowerPC Instructions that completed.
+event:0X07F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP127 : (Group 127 pm_vsu6) Number of run instructions completed.
+event:0X07F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP127 : (Group 127 pm_vsu6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 128 pm_vsu7, VSU Execution
+event:0X0800 counters:0 um:zero minimum:1000 name:PM_VSU_FIN_GRP128 : (Group 128 pm_vsu7) VSU0 Finished an instruction
+event:0X0801 counters:1 um:zero minimum:1000 name:PM_VSU0_FIN_GRP128 : (Group 128 pm_vsu7) VSU0 Finished an instruction
+event:0X0802 counters:2 um:zero minimum:1000 name:PM_VSU1_FIN_GRP128 : (Group 128 pm_vsu7) VSU1 Finished an instruction
+event:0X0803 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP128 : (Group 128 pm_vsu7) Number of PowerPC Instructions that completed.
+event:0X0804 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP128 : (Group 128 pm_vsu7) Number of run instructions completed.
+event:0X0805 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP128 : (Group 128 pm_vsu7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 129 pm_vsu8, VSU Execution
+event:0X0810 counters:0 um:zero minimum:1000 name:PM_VSU_STF_GRP129 : (Group 129 pm_vsu8) FPU store (SP or DP) issued on Pipe0
+event:0X0811 counters:1 um:zero minimum:1000 name:PM_VSU0_STF_GRP129 : (Group 129 pm_vsu8) FPU store (SP or DP) issued on Pipe0
+event:0X0812 counters:2 um:zero minimum:1000 name:PM_VSU1_STF_GRP129 : (Group 129 pm_vsu8) FPU store (SP or DP) issued on Pipe1
+event:0X0813 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP129 : (Group 129 pm_vsu8) Number of PowerPC Instructions that completed.
+event:0X0814 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP129 : (Group 129 pm_vsu8) Number of run instructions completed.
+event:0X0815 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP129 : (Group 129 pm_vsu8) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 130 pm_vsu9, VSU Execution
+event:0X0820 counters:0 um:zero minimum:1000 name:PM_VSU_SINGLE_GRP130 : (Group 130 pm_vsu9) Vector or Scalar single precision
+event:0X0821 counters:1 um:zero minimum:1000 name:PM_VSU0_SINGLE_GRP130 : (Group 130 pm_vsu9) VSU0 executed single precision instruction
+event:0X0822 counters:2 um:zero minimum:1000 name:PM_VSU1_SINGLE_GRP130 : (Group 130 pm_vsu9) VSU1 executed single precision instruction
+event:0X0823 counters:3 um:zero minimum:1000 name:PM_VSU0_16FLOP_GRP130 : (Group 130 pm_vsu9) Sixteen flops operation (SP vector versions of fdiv,fsqrt)
+event:0X0824 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP130 : (Group 130 pm_vsu9) Number of run instructions completed.
+event:0X0825 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP130 : (Group 130 pm_vsu9) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 131 pm_vsu10, VSU Execution
+event:0X0830 counters:0 um:zero minimum:1000 name:PM_VSU_FSQRT_FDIV_GRP131 : (Group 131 pm_vsu10) DP vector versions of fdiv,fsqrt
+event:0X0831 counters:1 um:zero minimum:1000 name:PM_VSU0_FSQRT_FDIV_GRP131 : (Group 131 pm_vsu10) four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!
+event:0X0832 counters:2 um:zero minimum:1000 name:PM_VSU1_FSQRT_FDIV_GRP131 : (Group 131 pm_vsu10) four flops operation (fdiv,fsqrt,xsdiv,xssqrt) Scalar Instructions only!
+event:0X0833 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP131 : (Group 131 pm_vsu10) Number of PowerPC Instructions that completed.
+event:0X0834 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP131 : (Group 131 pm_vsu10) Number of run instructions completed.
+event:0X0835 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP131 : (Group 131 pm_vsu10) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 132 pm_vsu11, VSU Execution
+event:0X0840 counters:0 um:zero minimum:1000 name:PM_VSU_FSQRT_FDIV_DOUBLE_GRP132 : (Group 132 pm_vsu11) DP vector versions of fdiv,fsqrt
+event:0X0841 counters:1 um:zero minimum:1000 name:PM_VSU0_FSQRT_FDIV_DOUBLE_GRP132 : (Group 132 pm_vsu11) eight flop DP vector operations (xvfdivdp, xvsqrtdp
+event:0X0842 counters:2 um:zero minimum:1000 name:PM_VSU1_FSQRT_FDIV_DOUBLE_GRP132 : (Group 132 pm_vsu11) eight flop DP vector operations (xvfdivdp, xvsqrtdp
+event:0X0843 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP132 : (Group 132 pm_vsu11) Number of PowerPC Instructions that completed.
+event:0X0844 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP132 : (Group 132 pm_vsu11) Number of run instructions completed.
+event:0X0845 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP132 : (Group 132 pm_vsu11) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 133 pm_vsu12, VSU Execution
+event:0X0850 counters:0 um:zero minimum:1000 name:PM_VSU_SCALAR_DOUBLE_ISSUED_GRP133 : (Group 133 pm_vsu12) Double Precision scalar instruction issued on Pipe0
+event:0X0851 counters:1 um:zero minimum:1000 name:PM_VSU0_SCAL_DOUBLE_ISSUED_GRP133 : (Group 133 pm_vsu12) Double Precision scalar instruction issued on Pipe0
+event:0X0852 counters:2 um:zero minimum:1000 name:PM_VSU1_SCAL_DOUBLE_ISSUED_GRP133 : (Group 133 pm_vsu12) Double Precision scalar instruction issued on Pipe1
+event:0X0853 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP133 : (Group 133 pm_vsu12) Number of PowerPC Instructions that completed.
+event:0X0854 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP133 : (Group 133 pm_vsu12) Number of run instructions completed.
+event:0X0855 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP133 : (Group 133 pm_vsu12) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 134 pm_vsu13, VSU Execution
+event:0X0860 counters:0 um:zero minimum:1000 name:PM_VSU_SCALAR_SINGLE_ISSUED_GRP134 : (Group 134 pm_vsu13) Single Precision scalar instruction issued on Pipe0
+event:0X0861 counters:1 um:zero minimum:1000 name:PM_VSU0_SCAL_SINGLE_ISSUED_GRP134 : (Group 134 pm_vsu13) Single Precision scalar instruction issued on Pipe0
+event:0X0862 counters:2 um:zero minimum:1000 name:PM_VSU1_SCAL_SINGLE_ISSUED_GRP134 : (Group 134 pm_vsu13) Single Precision scalar instruction issued on Pipe1
+event:0X0863 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP134 : (Group 134 pm_vsu13) Number of PowerPC Instructions that completed.
+event:0X0864 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP134 : (Group 134 pm_vsu13) Number of run instructions completed.
+event:0X0865 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP134 : (Group 134 pm_vsu13) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 135 pm_vsu14, VSU Execution
+event:0X0870 counters:0 um:zero minimum:1000 name:PM_VSU_1FLOP_GRP135 : (Group 135 pm_vsu14) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished
+event:0X0871 counters:1 um:zero minimum:1000 name:PM_VSU_4FLOP_GRP135 : (Group 135 pm_vsu14) four flops operation (scalar fdiv, fsqrt; DP vector version of fmadd, fnmadd, fmsub, fnmsub; SP vector versions of single flop instructions)
+event:0X0872 counters:2 um:zero minimum:1000 name:PM_VSU_8FLOP_GRP135 : (Group 135 pm_vsu14) eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub)
+event:0X0873 counters:3 um:zero minimum:1000 name:PM_VSU_2FLOP_GRP135 : (Group 135 pm_vsu14) two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions)
+event:0X0874 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP135 : (Group 135 pm_vsu14) Number of run instructions completed.
+event:0X0875 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP135 : (Group 135 pm_vsu14) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 136 pm_vsu15, VSU Execution
+event:0X0880 counters:0 um:zero minimum:1000 name:PM_VSU_VECTOR_SINGLE_ISSUED_GRP136 : (Group 136 pm_vsu15) Single Precision vector instruction issued (executed)
+event:0X0881 counters:1 um:zero minimum:1000 name:PM_VSU0_VECTOR_SP_ISSUED_GRP136 : (Group 136 pm_vsu15) Single Precision vector instruction issued (executed)
+event:0X0882 counters:2 um:zero minimum:1000 name:PM_VSU0_FPSCR_GRP136 : (Group 136 pm_vsu15) Move to/from FPSCR type instruction issued on Pipe 0
+event:0X0883 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP136 : (Group 136 pm_vsu15) Number of PowerPC Instructions that completed.
+event:0X0884 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP136 : (Group 136 pm_vsu15) Number of run instructions completed.
+event:0X0885 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP136 : (Group 136 pm_vsu15) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 137 pm_vsu16, VSU Execution
+event:0X0890 counters:0 um:zero minimum:1000 name:PM_VSU_SIMPLE_ISSUED_GRP137 : (Group 137 pm_vsu16) Simple VMX instruction issued
+event:0X0891 counters:1 um:zero minimum:1000 name:PM_VSU0_SIMPLE_ISSUED_GRP137 : (Group 137 pm_vsu16) Simple VMX instruction issued
+event:0X0892 counters:2 um:zero minimum:1000 name:PM_VSU0_COMPLEX_ISSUED_GRP137 : (Group 137 pm_vsu16) Complex VMX instruction issued
+event:0X0893 counters:3 um:zero minimum:1000 name:PM_VMX_RESULT_SAT_1_GRP137 : (Group 137 pm_vsu16) Valid result with sat=1
+event:0X0894 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP137 : (Group 137 pm_vsu16) Number of run instructions completed.
+event:0X0895 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP137 : (Group 137 pm_vsu16) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 138 pm_vsu17, VSU Execution
+event:0X08A0 counters:0 um:zero minimum:1000 name:PM_VSU1_DD_ISSUED_GRP138 : (Group 138 pm_vsu17) 64BIT Decimal Issued on Pipe1
+event:0X08A1 counters:1 um:zero minimum:1000 name:PM_VSU1_DQ_ISSUED_GRP138 : (Group 138 pm_vsu17) 128BIT Decimal Issued on Pipe1
+event:0X08A2 counters:2 um:zero minimum:1000 name:PM_VSU1_PERMUTE_ISSUED_GRP138 : (Group 138 pm_vsu17) Permute VMX Instruction Issued
+event:0X08A3 counters:3 um:zero minimum:1000 name:PM_VSU1_SQ_GRP138 : (Group 138 pm_vsu17) Store Vector Issued on Pipe1
+event:0X08A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP138 : (Group 138 pm_vsu17) Number of run instructions completed.
+event:0X08A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP138 : (Group 138 pm_vsu17) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 139 pm_vsu18, VSU Execution
+event:0X08B0 counters:0 um:zero minimum:1000 name:PM_VSU_FCONV_GRP139 : (Group 139 pm_vsu18) Convert instruction executed
+event:0X08B1 counters:1 um:zero minimum:1000 name:PM_VSU0_FCONV_GRP139 : (Group 139 pm_vsu18) Convert instruction executed
+event:0X08B2 counters:2 um:zero minimum:1000 name:PM_VSU1_FCONV_GRP139 : (Group 139 pm_vsu18) Convert instruction executed
+event:0X08B3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP139 : (Group 139 pm_vsu18) Number of PowerPC Instructions that completed.
+event:0X08B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP139 : (Group 139 pm_vsu18) Number of run instructions completed.
+event:0X08B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP139 : (Group 139 pm_vsu18) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 140 pm_vsu19, VSU Execution
+event:0X08C0 counters:0 um:zero minimum:1000 name:PM_VSU_FRSP_GRP140 : (Group 140 pm_vsu19) Round to single precision instruction executed
+event:0X08C1 counters:1 um:zero minimum:1000 name:PM_VSU0_FRSP_GRP140 : (Group 140 pm_vsu19) Round to single precision instruction executed
+event:0X08C2 counters:2 um:zero minimum:1000 name:PM_VSU1_FRSP_GRP140 : (Group 140 pm_vsu19) Round to single precision instruction executed
+event:0X08C3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP140 : (Group 140 pm_vsu19) Number of PowerPC Instructions that completed.
+event:0X08C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP140 : (Group 140 pm_vsu19) Number of run instructions completed.
+event:0X08C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP140 : (Group 140 pm_vsu19) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 141 pm_vsu20, VSU Execution
+event:0X08D0 counters:0 um:zero minimum:1000 name:PM_VSU_FEST_GRP141 : (Group 141 pm_vsu20) Estimate instruction executed
+event:0X08D1 counters:1 um:zero minimum:1000 name:PM_VSU0_FEST_GRP141 : (Group 141 pm_vsu20) Estimate instruction executed
+event:0X08D2 counters:2 um:zero minimum:1000 name:PM_VSU1_FEST_GRP141 : (Group 141 pm_vsu20) Estimate instruction executed
+event:0X08D3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP141 : (Group 141 pm_vsu20) Number of PowerPC Instructions that completed.
+event:0X08D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP141 : (Group 141 pm_vsu20) Number of run instructions completed.
+event:0X08D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP141 : (Group 141 pm_vsu20) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 142 pm_vsu21, VSU Execution
+event:0X08E0 counters:0 um:zero minimum:1000 name:PM_BRU_FIN_GRP142 : (Group 142 pm_vsu21) The Branch execution unit finished an instruction
+event:0X08E1 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP142 : (Group 142 pm_vsu21) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X08E2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP142 : (Group 142 pm_vsu21) Number of PowerPC Instructions that completed.
+event:0X08E3 counters:3 um:zero minimum:1000 name:PM_VSU_FIN_GRP142 : (Group 142 pm_vsu21) VSU0 Finished an instruction
+event:0X08E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP142 : (Group 142 pm_vsu21) Number of run instructions completed.
+event:0X08E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP142 : (Group 142 pm_vsu21) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 143 pm_vsu22, VSU Execution
+event:0X08F0 counters:0 um:zero minimum:1000 name:PM_LSU_LDF_GRP143 : (Group 143 pm_vsu22) LSU executed Floating Point load instruction. Combined Unit 0 + 1.
+event:0X08F1 counters:1 um:zero minimum:1000 name:PM_VSU_STF_GRP143 : (Group 143 pm_vsu22) FPU store (SP or DP) issued on Pipe0
+event:0X08F2 counters:2 um:zero minimum:1000 name:PM_VSU_FMA_GRP143 : (Group 143 pm_vsu22) two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!
+event:0X08F3 counters:3 um:zero minimum:1000 name:PM_VSU_1FLOP_GRP143 : (Group 143 pm_vsu22) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished
+event:0X08F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP143 : (Group 143 pm_vsu22) Number of run instructions completed.
+event:0X08F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP143 : (Group 143 pm_vsu22) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 144 pm_vsu23, VSU Execution
+event:0X0900 counters:0 um:zero minimum:1000 name:PM_VSU_FSQRT_FDIV_GRP144 : (Group 144 pm_vsu23) DP vector versions of fdiv,fsqrt
+event:0X0901 counters:1 um:zero minimum:1000 name:PM_VSU_FIN_GRP144 : (Group 144 pm_vsu23) VSU0 Finished an instruction
+event:0X0902 counters:2 um:zero minimum:1000 name:PM_VSU_FMA_GRP144 : (Group 144 pm_vsu23) two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only!
+event:0X0903 counters:3 um:zero minimum:1000 name:PM_VSU_1FLOP_GRP144 : (Group 144 pm_vsu23) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished
+event:0X0904 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP144 : (Group 144 pm_vsu23) Number of run instructions completed.
+event:0X0905 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP144 : (Group 144 pm_vsu23) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 145 pm_vsu24, VSU Execution
+event:0X0910 counters:0 um:zero minimum:1000 name:PM_FLOP_GRP145 : (Group 145 pm_vsu24) A floating point operation has completed
+event:0X0911 counters:1 um:zero minimum:1000 name:PM_VSU_FIN_GRP145 : (Group 145 pm_vsu24) VSU0 Finished an instruction
+event:0X0912 counters:2 um:zero minimum:1000 name:PM_VSU_FEST_GRP145 : (Group 145 pm_vsu24) Estimate instruction executed
+event:0X0913 counters:3 um:zero minimum:1000 name:PM_VSU_1FLOP_GRP145 : (Group 145 pm_vsu24) one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished
+event:0X0914 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP145 : (Group 145 pm_vsu24) Number of run instructions completed.
+event:0X0915 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP145 : (Group 145 pm_vsu24) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 146 pm_vsu25, VSU Execution
+event:0X0920 counters:0 um:zero minimum:1000 name:PM_VSU_STF_GRP146 : (Group 146 pm_vsu25) FPU store (SP or DP) issued on Pipe0
+event:0X0921 counters:1 um:zero minimum:1000 name:PM_VSU_FIN_GRP146 : (Group 146 pm_vsu25) VSU0 Finished an instruction
+event:0X0922 counters:2 um:zero minimum:1000 name:PM_VSU_FRSP_GRP146 : (Group 146 pm_vsu25) Round to single precision instruction executed
+event:0X0923 counters:3 um:zero minimum:1000 name:PM_VSU_FCONV_GRP146 : (Group 146 pm_vsu25) Convert instruction executed
+event:0X0924 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP146 : (Group 146 pm_vsu25) Number of run instructions completed.
+event:0X0925 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP146 : (Group 146 pm_vsu25) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 147 pm_lsu1, LSU LMQ SRQ events
+event:0X0930 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP147 : (Group 147 pm_lsu1) The Load Miss Queue was full.
+event:0X0931 counters:1 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP147 : (Group 147 pm_lsu1) Cycles when both the LMQ and SRQ are empty (LSU is idle)
+event:0X0932 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC_GRP147 : (Group 147 pm_lsu1) ALL threads lsu empty (lmq and srq empty)
+event:0X0933 counters:3 um:zero minimum:1000 name:PM_LSU_SRQ_EMPTY_CYC_GRP147 : (Group 147 pm_lsu1) The Store Request Queue is empty
+event:0X0934 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP147 : (Group 147 pm_lsu1) Number of run instructions completed.
+event:0X0935 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP147 : (Group 147 pm_lsu1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 148 pm_lsu2, LSU events
+event:0X0940 counters:0 um:zero minimum:1000 name:PM_LSU_FX_FIN_GRP148 : (Group 148 pm_lsu2) LSU Finished a FX operation (up to 2 per cycle)
+event:0X0941 counters:1 um:zero minimum:1000 name:PM_LSU_NCST_GRP148 : (Group 148 pm_lsu2) Non-cachable Stores sent to nest
+event:0X0942 counters:2 um:zero minimum:1000 name:PM_LSU_FIN_GRP148 : (Group 148 pm_lsu2) LSU Finished an instruction (up to 2 per cycle)
+event:0X0943 counters:3 um:zero minimum:1000 name:PM_LSU_FLUSH_GRP148 : (Group 148 pm_lsu2) A flush was initiated by the Load Store Unit.
+event:0X0944 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP148 : (Group 148 pm_lsu2) Number of run instructions completed.
+event:0X0945 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP148 : (Group 148 pm_lsu2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 149 pm_lsu_lmq, LSU LMQ Events
+event:0X0950 counters:0 um:zero minimum:1000 name:PM_LSU0_LMQ_LHR_MERGE_GRP149 : (Group 149 pm_lsu_lmq) LS0 Load Merged with another cacheline request
+event:0X0951 counters:1 um:zero minimum:1000 name:PM_LSU1_LMQ_LHR_MERGE_GRP149 : (Group 149 pm_lsu_lmq) LS1 Load Merge with another cacheline request
+event:0X0952 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP149 : (Group 149 pm_lsu_lmq) This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).
+event:0X0953 counters:3 um:zero minimum:1000 name:PM_LSU_LMQ_FULL_CYC_GRP149 : (Group 149 pm_lsu_lmq) The Load Miss Queue was full.
+event:0X0954 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP149 : (Group 149 pm_lsu_lmq) Number of run instructions completed.
+event:0X0955 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP149 : (Group 149 pm_lsu_lmq) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 150 pm_lsu_srq1, Store Request Queue Info
+event:0X0960 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_STFWD_GRP150 : (Group 150 pm_lsu_srq1) Data from a store instruction was forwarded to a load. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss. Combined Unit 0 + 1.
+event:0X0961 counters:1 um:zero minimum:1000 name:PM_LSU0_SRQ_STFWD_GRP150 : (Group 150 pm_lsu_srq1) Data from a store instruction was forwarded to a load on unit 0. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.
+event:0X0962 counters:2 um:zero minimum:1000 name:PM_LSU1_SRQ_STFWD_GRP150 : (Group 150 pm_lsu_srq1) Data from a store instruction was forwarded to a load on unit 1. A load that misses L1 but becomes a store forward is treated as a load miss and it causes the DL1 load miss event to be counted. It does not go into the LMQ. If a load that hits L1 but becomes a store forward, then it's not treated as a load miss.
+event:0X0963 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP150 : (Group 150 pm_lsu_srq1) Number of PowerPC Instructions that completed.
+event:0X0964 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP150 : (Group 150 pm_lsu_srq1) Number of run instructions completed.
+event:0X0965 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP150 : (Group 150 pm_lsu_srq1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 151 pm_lsu_srq2, Store Request Queue Info
+event:0X0970 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_CYC_GRP151 : (Group 151 pm_lsu_srq2) Cycles that a sync instruction is active in the Store Request Queue.
+event:0X0971 counters:1 um:zero minimum:1000 name:PM_LSU_SRQ_SYNC_COUNT_GRP151 : (Group 151 pm_lsu_srq2) SRQ sync count (edge of PM_LSU_SRQ_SYNC_CYC)
+event:0X0972 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP151 : (Group 151 pm_lsu_srq2) This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).
+event:0X0973 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP151 : (Group 151 pm_lsu_srq2) Number of PowerPC Instructions that completed.
+event:0X0974 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP151 : (Group 151 pm_lsu_srq2) Number of run instructions completed.
+event:0X0975 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP151 : (Group 151 pm_lsu_srq2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 152 pm_lsu_s0_valid, LSU Events
+event:0X0980 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_S0_VALID_GRP152 : (Group 152 pm_lsu_s0_valid) This signal is asserted every cycle that the Store Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the SRQ is split between the two threads (16 entries each).
+event:0X0981 counters:1 um:zero minimum:1000 name:PM_LSU_LRQ_S0_VALID_GRP152 : (Group 152 pm_lsu_s0_valid) This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).
+event:0X0982 counters:2 um:zero minimum:1000 name:PM_LSU_LMQ_S0_VALID_GRP152 : (Group 152 pm_lsu_s0_valid) This signal is asserted every cycle that the Load Request Queue slot zero is valid. The SRQ is 32 entries long and is allocated round-robin. In SMT mode the LRQ is split between the two threads (16 entries each).
+event:0X0983 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP152 : (Group 152 pm_lsu_s0_valid) Number of PowerPC Instructions that completed.
+event:0X0984 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP152 : (Group 152 pm_lsu_s0_valid) Number of run instructions completed.
+event:0X0985 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP152 : (Group 152 pm_lsu_s0_valid) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 153 pm_lsu_s0_alloc, LSU Events
+event:0X0990 counters:0 um:zero minimum:1000 name:PM_LSU_LMQ_S0_ALLOC_GRP153 : (Group 153 pm_lsu_s0_alloc) Slot 0 of LMQ valid
+event:0X0991 counters:1 um:zero minimum:1000 name:PM_LSU_LRQ_S0_ALLOC_GRP153 : (Group 153 pm_lsu_s0_alloc) Slot 0 of LRQ valid
+event:0X0992 counters:2 um:zero minimum:1000 name:PM_LSU_SRQ_S0_ALLOC_GRP153 : (Group 153 pm_lsu_s0_alloc) Slot 0 of SRQ valid
+event:0X0993 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP153 : (Group 153 pm_lsu_s0_alloc) Number of PowerPC Instructions that completed.
+event:0X0994 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP153 : (Group 153 pm_lsu_s0_alloc) Number of run instructions completed.
+event:0X0995 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP153 : (Group 153 pm_lsu_s0_alloc) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 154 pm_l1_pref, L1 pref Events
+event:0X09A0 counters:0 um:zero minimum:1000 name:PM_L1_PREF_GRP154 : (Group 154 pm_l1_pref) A request to prefetch data into the L1 was made
+event:0X09A1 counters:1 um:zero minimum:1000 name:PM_LSU0_L1_PREF_GRP154 : (Group 154 pm_l1_pref) LS0 L1 cache data prefetches
+event:0X09A2 counters:2 um:zero minimum:1000 name:PM_LSU1_L1_PREF_GRP154 : (Group 154 pm_l1_pref) LS1 L1 cache data prefetches
+event:0X09A3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP154 : (Group 154 pm_l1_pref) Number of PowerPC Instructions that completed.
+event:0X09A4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP154 : (Group 154 pm_l1_pref) Number of run instructions completed.
+event:0X09A5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP154 : (Group 154 pm_l1_pref) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 155 pm_l2_guess_1, L2_Guess_events
+event:0X09B0 counters:0 um:zero minimum:1000 name:PM_L2_LOC_GUESS_CORRECT_GRP155 : (Group 155 pm_l2_guess_1) L2 guess loc and guess was correct (ie data local)
+event:0X09B1 counters:1 um:zero minimum:1000 name:PM_L2_LOC_GUESS_WRONG_GRP155 : (Group 155 pm_l2_guess_1) L2 guess loc and guess was not correct (ie data remote)
+event:0X09B2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP155 : (Group 155 pm_l2_guess_1) Processor Cycles
+event:0X09B3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP155 : (Group 155 pm_l2_guess_1) Number of PowerPC Instructions that completed.
+event:0X09B4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP155 : (Group 155 pm_l2_guess_1) Number of run instructions completed.
+event:0X09B5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP155 : (Group 155 pm_l2_guess_1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 156 pm_l2_guess_2, L2_Guess_events
+event:0X09C0 counters:0 um:zero minimum:1000 name:PM_L2_GLOB_GUESS_CORRECT_GRP156 : (Group 156 pm_l2_guess_2) L2 guess glb and guess was correct (ie data remote)
+event:0X09C1 counters:1 um:zero minimum:1000 name:PM_L2_GLOB_GUESS_WRONG_GRP156 : (Group 156 pm_l2_guess_2) L2 guess glb and guess was not correct (ie data local)
+event:0X09C2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP156 : (Group 156 pm_l2_guess_2) Processor Cycles
+event:0X09C3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP156 : (Group 156 pm_l2_guess_2) Number of PowerPC Instructions that completed.
+event:0X09C4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP156 : (Group 156 pm_l2_guess_2) Number of run instructions completed.
+event:0X09C5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP156 : (Group 156 pm_l2_guess_2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 157 pm_misc1, Misc events
+event:0X09D0 counters:0 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP157 : (Group 157 pm_misc1) Number of instructions resulting from the marked instructions expansion that completed.
+event:0X09D1 counters:1 um:zero minimum:1000 name:PM_INST_FROM_L1_GRP157 : (Group 157 pm_misc1) An instruction fetch group was fetched from L1. Fetch Groups can contain up to 8 instructions
+event:0X09D2 counters:2 um:zero minimum:1000 name:PM_INST_IMC_MATCH_DISP_GRP157 : (Group 157 pm_misc1) IMC Matches dispatched
+event:0X09D3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP157 : (Group 157 pm_misc1) Number of PowerPC Instructions that completed.
+event:0X09D4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP157 : (Group 157 pm_misc1) Number of run instructions completed.
+event:0X09D5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP157 : (Group 157 pm_misc1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 158 pm_misc2, Misc events
+event:0X09E0 counters:0 um:zero minimum:1000 name:PM_EE_OFF_EXT_INT_GRP158 : (Group 158 pm_misc2) Cycles when an interrupt due to an external exception is pending but external exceptions were masked.
+event:0X09E1 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP158 : (Group 158 pm_misc2) An interrupt due to an external exception occurred
+event:0X09E2 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP158 : (Group 158 pm_misc2) When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1
+event:0X09E3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP158 : (Group 158 pm_misc2) Processor Cycles
+event:0X09E4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP158 : (Group 158 pm_misc2) Number of run instructions completed.
+event:0X09E5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP158 : (Group 158 pm_misc2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 159 pm_misc3, Misc events
+event:0X09F0 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP159 : (Group 159 pm_misc3) A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X09F1 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP159 : (Group 159 pm_misc3) Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)
+event:0X09F2 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP159 : (Group 159 pm_misc3) Number of PowerPC instructions successfully dispatched.
+event:0X09F3 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP159 : (Group 159 pm_misc3) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X09F4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP159 : (Group 159 pm_misc3) Number of run instructions completed.
+event:0X09F5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP159 : (Group 159 pm_misc3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 160 pm_misc4, Misc events
+event:0X0A00 counters:0 um:zero minimum:1000 name:PM_GRP_IC_MISS_NONSPEC_GRP160 : (Group 160 pm_misc4) Number of groups, counted at completion, that have encountered an instruction cache miss.
+event:0X0A01 counters:1 um:zero minimum:1000 name:PM_GCT_NOSLOT_IC_MISS_GRP160 : (Group 160 pm_misc4) Cycles when the Global Completion Table has no slots from this thread because of an Instruction Cache miss.
+event:0X0A02 counters:2 um:zero minimum:10000 name:PM_CYC_GRP160 : (Group 160 pm_misc4) Processor Cycles
+event:0X0A03 counters:3 um:zero minimum:1000 name:PM_GCT_NOSLOT_BR_MPRED_IC_MISS_GRP160 : (Group 160 pm_misc4) No slot in GCT caused by branch mispredict or I cache miss
+event:0X0A04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP160 : (Group 160 pm_misc4) Number of run instructions completed.
+event:0X0A05 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP160 : (Group 160 pm_misc4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 161 pm_misc5, Misc events
+event:0X0A10 counters:0 um:zero minimum:1000 name:PM_GRP_BR_MPRED_NONSPEC_GRP161 : (Group 161 pm_misc5) Group experienced non-speculative branch redirect
+event:0X0A11 counters:1 um:zero minimum:1000 name:PM_BR_MPRED_CR_TA_GRP161 : (Group 161 pm_misc5) Branch mispredict - taken/not taken and target
+event:0X0A12 counters:2 um:zero minimum:1000 name:PM_BR_MPRED_CCACHE_GRP161 : (Group 161 pm_misc5) A branch instruction target was incorrectly predicted by the ccount cache. This will result in a branch redirect flush if not overfidden by a flush of an older instruction.
+event:0X0A13 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP161 : (Group 161 pm_misc5) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
+event:0X0A14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP161 : (Group 161 pm_misc5) Number of run instructions completed.
+event:0X0A15 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP161 : (Group 161 pm_misc5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 162 pm_misc6, Misc events
+event:0X0A20 counters:0 um:zero minimum:1000 name:PM_L1_DEMAND_WRITE_GRP162 : (Group 162 pm_misc6) Instruction Demand sectors wriittent into IL1
+event:0X0A21 counters:1 um:zero minimum:1000 name:PM_IC_PREF_WRITE_GRP162 : (Group 162 pm_misc6) Number of Instruction Cache entries written because of prefetch. Prefetch entries are marked least recently used and are candidates for eviction if they are not needed to satify a demand fetch.
+event:0X0A22 counters:2 um:zero minimum:1000 name:PM_IC_WRITE_ALL_GRP162 : (Group 162 pm_misc6) Icache sectors written, prefetch + demand
+event:0X0A23 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP162 : (Group 162 pm_misc6) Number of PowerPC Instructions that completed.
+event:0X0A24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP162 : (Group 162 pm_misc6) Number of run instructions completed.
+event:0X0A25 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP162 : (Group 162 pm_misc6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 163 pm_misc7, Misc events
+event:0X0A30 counters:0 um:zero minimum:1000 name:PM_THRESH_TIMEO_GRP163 : (Group 163 pm_misc7) The threshold timer expired
+event:0X0A31 counters:1 um:zero minimum:1000 name:PM_HV_CYC_GRP163 : (Group 163 pm_misc7) Cycles when the processor is executing in Hypervisor (MSR[HV] = 1 and MSR[PR]=0)
+event:0X0A32 counters:2 um:zero minimum:10000 name:PM_CYC_GRP163 : (Group 163 pm_misc7) Processor Cycles
+event:0X0A33 counters:3 um:zero minimum:1000 name:PM_IFU_FIN_GRP163 : (Group 163 pm_misc7) The Instruction Fetch Unit finished an instruction
+event:0X0A34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP163 : (Group 163 pm_misc7) Number of run instructions completed.
+event:0X0A35 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP163 : (Group 163 pm_misc7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 164 pm_misc8, Misc events
+event:0X0A40 counters:0 um:zero minimum:1000 name:PM_BR_MPRED_LSTACK_GRP164 : (Group 164 pm_misc8) Branch Mispredict due to Link Stack
+event:0X0A41 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP164 : (Group 164 pm_misc8) An interrupt due to an external exception occurred
+event:0X0A42 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP164 : (Group 164 pm_misc8) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X0A43 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP164 : (Group 164 pm_misc8) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
+event:0X0A44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP164 : (Group 164 pm_misc8) Number of run instructions completed.
+event:0X0A45 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP164 : (Group 164 pm_misc8) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 165 pm_misc9, Misc events
+event:0X0A50 counters:0 um:zero minimum:1000 name:PM_FLUSH_BR_MPRED_GRP165 : (Group 165 pm_misc9) A flush was caused by a branch mispredict.
+event:0X0A51 counters:1 um:zero minimum:1000 name:PM_FLUSH_PARTIAL_GRP165 : (Group 165 pm_misc9) Partial flush
+event:0X0A52 counters:2 um:zero minimum:1000 name:PM_LSU_SET_MPRED_GRP165 : (Group 165 pm_misc9) Line already in cache at reload time
+event:0X0A53 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP165 : (Group 165 pm_misc9) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
+event:0X0A54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP165 : (Group 165 pm_misc9) Number of run instructions completed.
+event:0X0A55 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP165 : (Group 165 pm_misc9) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 166 pm_misc10, Misc events
+event:0X0A60 counters:0 um:zero minimum:1000 name:PM_LSU_SRQ_FULL_CYC_GRP166 : (Group 166 pm_misc10) Cycles the Store Request Queue is full.
+event:0X0A61 counters:1 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_ALLOC_GRP166 : (Group 166 pm_misc10) D cache new prefetch stream allocated
+event:0X0A62 counters:2 um:zero minimum:1000 name:PM_L1_PREF_GRP166 : (Group 166 pm_misc10) A request to prefetch data into the L1 was made
+event:0X0A63 counters:3 um:zero minimum:1000 name:PM_IBUF_FULL_CYC_GRP166 : (Group 166 pm_misc10) Cycles with the Instruction Buffer was full. The Instruction Buffer is a circular queue of 64 instructions per thread, organized as 16 groups of 4 instructions.
+event:0X0A64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP166 : (Group 166 pm_misc10) Number of run instructions completed.
+event:0X0A65 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP166 : (Group 166 pm_misc10) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 167 pm_misc11, Misc events
+event:0X0A70 counters:0 um:zero minimum:1000 name:PM_FLOP_GRP167 : (Group 167 pm_misc11) A floating point operation has completed
+event:0X0A71 counters:1 um:zero minimum:10000 name:PM_CYC_GRP167 : (Group 167 pm_misc11) Processor Cycles
+event:0X0A72 counters:2 um:zero minimum:1000 name:PM_GRP_CMPL_GRP167 : (Group 167 pm_misc11) A group completed. Microcoded instructions that span multiple groups will generate this event once per group.
+event:0X0A73 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP167 : (Group 167 pm_misc11) Number of PowerPC Instructions that completed.
+event:0X0A74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP167 : (Group 167 pm_misc11) Number of run instructions completed.
+event:0X0A75 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP167 : (Group 167 pm_misc11) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 168 pm_misc_12, Misc Events
+event:0X0A80 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP168 : (Group 168 pm_misc_12) Number of PowerPC Instructions that completed.
+event:0X0A81 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP168 : (Group 168 pm_misc_12) Store requests sent to the nest.
+event:0X0A82 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP168 : (Group 168 pm_misc_12) When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1
+event:0X0A83 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP168 : (Group 168 pm_misc_12) Flushes occurred including LSU and Branch flushes.
+event:0X0A84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP168 : (Group 168 pm_misc_12) Number of run instructions completed.
+event:0X0A85 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP168 : (Group 168 pm_misc_12) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 169 pm_misc_13, Misc Events
+event:0X0A90 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP169 : (Group 169 pm_misc_13) Cycles when the Global Completion Table has no slots from this thread.
+event:0X0A91 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP169 : (Group 169 pm_misc_13) Store requests sent to the nest.
+event:0X0A92 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP169 : (Group 169 pm_misc_13) Data TLB misses, all page sizes.
+event:0X0A93 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP169 : (Group 169 pm_misc_13) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
+event:0X0A94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP169 : (Group 169 pm_misc_13) Number of run instructions completed.
+event:0X0A95 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP169 : (Group 169 pm_misc_13) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 170 pm_misc_14, Misc Events
+event:0X0AA0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP170 : (Group 170 pm_misc_14) Processor Cycles
+event:0X0AA1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP170 : (Group 170 pm_misc_14) Processor Cycles
+event:0X0AA2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP170 : (Group 170 pm_misc_14) Number of PowerPC Instructions that completed.
+event:0X0AA3 counters:3 um:zero minimum:1000 name:PM_IFU_FIN_GRP170 : (Group 170 pm_misc_14) The Instruction Fetch Unit finished an instruction
+event:0X0AA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP170 : (Group 170 pm_misc_14) Number of run instructions completed.
+event:0X0AA5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP170 : (Group 170 pm_misc_14) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 171 pm_misc_15, Misc Events
+event:0X0AB0 counters:0 um:zero minimum:1000 name:PM_LSU_DCACHE_RELOAD_VALID_GRP171 : (Group 171 pm_misc_15) count per sector of lines reloaded in L1 (demand + prefetch)
+event:0X0AB1 counters:1 um:zero minimum:1000 name:PM_CMPLU_STALL_STORE_GRP171 : (Group 171 pm_misc_15) Completion stall due to store instruction
+event:0X0AB2 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP171 : (Group 171 pm_misc_15) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X0AB3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_VECTOR_LONG_GRP171 : (Group 171 pm_misc_15) completion stall due to long latency vector instruction
+event:0X0AB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP171 : (Group 171 pm_misc_15) Number of run instructions completed.
+event:0X0AB5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP171 : (Group 171 pm_misc_15) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 172 pm_misc_16, Misc Events
+event:0X0AC0 counters:0 um:zero minimum:1000 name:PM_CMPLU_STALL_END_GCT_NOSLOT_GRP172 : (Group 172 pm_misc_16) Count ended because GCT went empty
+event:0X0AC1 counters:1 um:zero minimum:1000 name:PM_LSU0_L1_SW_PREF_GRP172 : (Group 172 pm_misc_16) LSU0 Software L1 Prefetches, including SW Transient Prefetches
+event:0X0AC2 counters:2 um:zero minimum:1000 name:PM_LSU1_L1_SW_PREF_GRP172 : (Group 172 pm_misc_16) LSU1 Software L1 Prefetches, including SW Transient Prefetches
+event:0X0AC3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_IFU_GRP172 : (Group 172 pm_misc_16) Completion stall due to IFU
+event:0X0AC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP172 : (Group 172 pm_misc_16) Number of run instructions completed.
+event:0X0AC5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP172 : (Group 172 pm_misc_16) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 173 pm_misc_17, Misc Events
+event:0X0AD0 counters:0 um:zero minimum:1000 name:PM_BRU_FIN_GRP173 : (Group 173 pm_misc_17) The Branch execution unit finished an instruction
+event:0X0AD1 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP173 : (Group 173 pm_misc_17) Store requests sent to the nest.
+event:0X0AD2 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DL2L3_SHR_GRP173 : (Group 173 pm_misc_17) A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.
+event:0X0AD3 counters:3 um:zero minimum:1000 name:PM_CMPLU_STALL_BRU_GRP173 : (Group 173 pm_misc_17) Completion stall due to BRU
+event:0X0AD4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP173 : (Group 173 pm_misc_17) Number of run instructions completed.
+event:0X0AD5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP173 : (Group 173 pm_misc_17) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 174 pm_suspend, SUSPENDED events
+event:0X0AE0 counters:0 um:zero minimum:1000 name:PM_SUSPENDED_GRP174 : (Group 174 pm_suspend) The counter is suspended (does not count)
+event:0X0AE1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP174 : (Group 174 pm_suspend) Processor Cycles
+event:0X0AE2 counters:2 um:zero minimum:1000 name:PM_LWSYNC_GRP174 : (Group 174 pm_suspend) lwsync count (easier to use than IMC)
+event:0X0AE3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP174 : (Group 174 pm_suspend) Number of PowerPC Instructions that completed.
+event:0X0AE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP174 : (Group 174 pm_suspend) Number of run instructions completed.
+event:0X0AE5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP174 : (Group 174 pm_suspend) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 175 pm_iops, Internal Operations events
+event:0X0AF0 counters:0 um:zero minimum:1000 name:PM_IOPS_CMPL_GRP175 : (Group 175 pm_iops) Number of internal operations that completed.
+event:0X0AF1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP175 : (Group 175 pm_iops) Processor Cycles
+event:0X0AF2 counters:2 um:zero minimum:1000 name:PM_IOPS_DISP_GRP175 : (Group 175 pm_iops) IOPS dispatched
+event:0X0AF3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP175 : (Group 175 pm_iops) Number of PowerPC Instructions that completed.
+event:0X0AF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP175 : (Group 175 pm_iops) Number of run instructions completed.
+event:0X0AF5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP175 : (Group 175 pm_iops) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 176 pm_sync, sync
+event:0X0B00 counters:0 um:zero minimum:1000 name:PM_LWSYNC_GRP176 : (Group 176 pm_sync) lwsync count (easier to use than IMC)
+event:0X0B01 counters:1 um:zero minimum:10000 name:PM_CYC_GRP176 : (Group 176 pm_sync) Processor Cycles
+event:0X0B02 counters:2 um:zero minimum:1000 name:PM_LWSYNC_HELD_GRP176 : (Group 176 pm_sync) Cycles a LWSYNC instruction was held at dispatch. LWSYNC instructions are held at dispatch until all previous loads are done and all previous stores have issued. LWSYNC enters the Store Request Queue and is sent to the storage subsystem but does not wait for a response.
+event:0X0B03 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP176 : (Group 176 pm_sync) Number of PowerPC Instructions that completed.
+event:0X0B04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP176 : (Group 176 pm_sync) Number of run instructions completed.
+event:0X0B05 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP176 : (Group 176 pm_sync) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 177 pm_seg, Segment events
+event:0X0B10 counters:0 um:zero minimum:10000 name:PM_CYC_GRP177 : (Group 177 pm_seg) Processor Cycles
+event:0X0B11 counters:1 um:zero minimum:1000 name:PM_SEG_EXCEPTION_GRP177 : (Group 177 pm_seg) ISEG + DSEG Exception
+event:0X0B12 counters:2 um:zero minimum:1000 name:PM_ISEG_GRP177 : (Group 177 pm_seg) ISEG Exception
+event:0X0B13 counters:3 um:zero minimum:1000 name:PM_DSEG_GRP177 : (Group 177 pm_seg) DSEG Exception
+event:0X0B14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP177 : (Group 177 pm_seg) Number of run instructions completed.
+event:0X0B15 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP177 : (Group 177 pm_seg) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 178 pm_l3_hit, L3 Hit Events
+event:0X0B20 counters:0 um:zero minimum:1000 name:PM_L3_HIT_GRP178 : (Group 178 pm_l3_hit) L3 Hits
+event:0X0B21 counters:1 um:zero minimum:1000 name:PM_L3_LD_HIT_GRP178 : (Group 178 pm_l3_hit) L3 demand LD Hits
+event:0X0B22 counters:2 um:zero minimum:1000 name:PM_L3_PREF_HIT_GRP178 : (Group 178 pm_l3_hit) L3 Prefetch Directory Hit
+event:0X0B23 counters:3 um:zero minimum:1000 name:PM_L3_CO_L31_GRP178 : (Group 178 pm_l3_hit) L3 Castouts to Memory
+event:0X0B24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP178 : (Group 178 pm_l3_hit) Number of run instructions completed.
+event:0X0B25 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP178 : (Group 178 pm_l3_hit) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 179 pm_shl, Shell Events
+event:0X0B30 counters:0 um:zero minimum:1000 name:PM_SHL_DEALLOCATED_GRP179 : (Group 179 pm_shl) SHL Table entry deallocated
+event:0X0B31 counters:1 um:zero minimum:1000 name:PM_SHL_CREATED_GRP179 : (Group 179 pm_shl) SHL table entry Created
+event:0X0B32 counters:2 um:zero minimum:1000 name:PM_SHL_MERGED_GRP179 : (Group 179 pm_shl) SHL table entry merged with existing
+event:0X0B33 counters:3 um:zero minimum:1000 name:PM_SHL_MATCH_GRP179 : (Group 179 pm_shl) SHL Table Match
+event:0X0B34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP179 : (Group 179 pm_shl) Number of run instructions completed.
+event:0X0B35 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP179 : (Group 179 pm_shl) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 180 pm_l3_pref, L3 Prefetch events
+event:0X0B40 counters:0 um:zero minimum:1000 name:PM_L3_PREF_LD_GRP180 : (Group 180 pm_l3_pref) L3 cache LD prefetches
+event:0X0B41 counters:1 um:zero minimum:1000 name:PM_L3_PREF_ST_GRP180 : (Group 180 pm_l3_pref) L3 cache ST prefetches
+event:0X0B42 counters:2 um:zero minimum:1000 name:PM_L3_PREF_LDST_GRP180 : (Group 180 pm_l3_pref) L3 cache prefetches LD + ST
+event:0X0B43 counters:3 um:zero minimum:1000 name:PM_L1_PREF_GRP180 : (Group 180 pm_l3_pref) A request to prefetch data into the L1 was made
+event:0X0B44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP180 : (Group 180 pm_l3_pref) Number of run instructions completed.
+event:0X0B45 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP180 : (Group 180 pm_l3_pref) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 181 pm_l3, L3 events
+event:0X0B50 counters:0 um:zero minimum:1000 name:PM_L3_MISS_GRP181 : (Group 181 pm_l3) L3 Misses
+event:0X0B51 counters:1 um:zero minimum:1000 name:PM_L3_LD_MISS_GRP181 : (Group 181 pm_l3) L3 demand LD Miss
+event:0X0B52 counters:2 um:zero minimum:1000 name:PM_L3_PREF_MISS_GRP181 : (Group 181 pm_l3) L3 Prefetch Directory Miss
+event:0X0B53 counters:3 um:zero minimum:1000 name:PM_L3_CO_MEM_GRP181 : (Group 181 pm_l3) L3 Castouts to L3.1
+event:0X0B54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP181 : (Group 181 pm_l3) Number of run instructions completed.
+event:0X0B55 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP181 : (Group 181 pm_l3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 182 pm_streams1, Streams
+event:0X0B60 counters:0 um:zero minimum:10000 name:PM_CYC_GRP182 : (Group 182 pm_streams1) Processor Cycles
+event:0X0B61 counters:1 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_CONFIRM_GRP182 : (Group 182 pm_streams1) Dcache new prefetch stream confirmed
+event:0X0B62 counters:2 um:zero minimum:1000 name:PM_LSU0_DC_PREF_STREAM_CONFIRM_GRP182 : (Group 182 pm_streams1) LS0 Dcache prefetch stream confirmed
+event:0X0B63 counters:3 um:zero minimum:1000 name:PM_LSU1_DC_PREF_STREAM_CONFIRM_GRP182 : (Group 182 pm_streams1) LS1 'Dcache prefetch stream confirmed
+event:0X0B64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP182 : (Group 182 pm_streams1) Number of run instructions completed.
+event:0X0B65 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP182 : (Group 182 pm_streams1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 183 pm_streams2, Streams
+event:0X0B70 counters:0 um:zero minimum:10000 name:PM_CYC_GRP183 : (Group 183 pm_streams2) Processor Cycles
+event:0X0B71 counters:1 um:zero minimum:1000 name:PM_LSU_DC_PREF_STRIDED_STREAM_CONFIRM_GRP183 : (Group 183 pm_streams2) Dcache Strided prefetch stream confirmed (software + hardware)
+event:0X0B72 counters:2 um:zero minimum:1000 name:PM_LSU0_DC_PREF_STREAM_CONFIRM_STRIDE_GRP183 : (Group 183 pm_streams2) LS0 Dcache Strided prefetch stream confirmed
+event:0X0B73 counters:3 um:zero minimum:1000 name:PM_LSU1_DC_PREF_STREAM_CONFIRM_STRIDE_GRP183 : (Group 183 pm_streams2) LS1 Dcache Strided prefetch stream confirmed
+event:0X0B74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP183 : (Group 183 pm_streams2) Number of run instructions completed.
+event:0X0B75 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP183 : (Group 183 pm_streams2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 184 pm_streams3, Streams
+event:0X0B80 counters:0 um:zero minimum:1000 name:PM_DC_PREF_DST_GRP184 : (Group 184 pm_streams3) A prefetch stream was started using the DST instruction.
+event:0X0B81 counters:1 um:zero minimum:1000 name:PM_LSU_DC_PREF_STREAM_ALLOC_GRP184 : (Group 184 pm_streams3) D cache new prefetch stream allocated
+event:0X0B82 counters:2 um:zero minimum:1000 name:PM_LSU0_DC_PREF_STREAM_ALLOC_GRP184 : (Group 184 pm_streams3) LS0 D cache new prefetch stream allocated
+event:0X0B83 counters:3 um:zero minimum:1000 name:PM_LSU1_DC_PREF_STREAM_ALLOC_GRP184 : (Group 184 pm_streams3) LS 1 D cache new prefetch stream allocated
+event:0X0B84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP184 : (Group 184 pm_streams3) Number of run instructions completed.
+event:0X0B85 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP184 : (Group 184 pm_streams3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 185 pm_larx, LARX
+event:0X0B90 counters:0 um:zero minimum:1000 name:PM_LARX_LSU0_GRP185 : (Group 185 pm_larx) A larx (lwarx or ldarx) was executed on side 0
+event:0X0B91 counters:1 um:zero minimum:1000 name:PM_LARX_LSU1_GRP185 : (Group 185 pm_larx) A larx (lwarx or ldarx) was executed on side 1
+event:0X0B92 counters:2 um:zero minimum:10000 name:PM_CYC_GRP185 : (Group 185 pm_larx) Processor Cycles
+event:0X0B93 counters:3 um:zero minimum:1000 name:PM_LARX_LSU_GRP185 : (Group 185 pm_larx) Larx Finished
+event:0X0B94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP185 : (Group 185 pm_larx) Number of run instructions completed.
+event:0X0B95 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP185 : (Group 185 pm_larx) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 186 pm_ldf, Floating Point loads
+event:0X0BA0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP186 : (Group 186 pm_ldf) Processor Cycles
+event:0X0BA1 counters:1 um:zero minimum:1000 name:PM_LSU_LDF_GRP186 : (Group 186 pm_ldf) LSU executed Floating Point load instruction. Combined Unit 0 + 1.
+event:0X0BA2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDF_GRP186 : (Group 186 pm_ldf) A floating point load was executed by LSU0
+event:0X0BA3 counters:3 um:zero minimum:1000 name:PM_LSU1_LDF_GRP186 : (Group 186 pm_ldf) A floating point load was executed by LSU1
+event:0X0BA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP186 : (Group 186 pm_ldf) Number of run instructions completed.
+event:0X0BA5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP186 : (Group 186 pm_ldf) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 187 pm_ldx, Vector Load
+event:0X0BB0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP187 : (Group 187 pm_ldx) Processor Cycles
+event:0X0BB1 counters:1 um:zero minimum:1000 name:PM_LSU_LDX_GRP187 : (Group 187 pm_ldx) All Vector loads (vsx vector + vmx vector)
+event:0X0BB2 counters:2 um:zero minimum:1000 name:PM_LSU0_LDX_GRP187 : (Group 187 pm_ldx) LS0 Vector Loads
+event:0X0BB3 counters:3 um:zero minimum:1000 name:PM_LSU1_LDX_GRP187 : (Group 187 pm_ldx) LS1 Vector Loads
+event:0X0BB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP187 : (Group 187 pm_ldx) Number of run instructions completed.
+event:0X0BB5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP187 : (Group 187 pm_ldx) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 188 pm_l2_ld_st, L2 load and store events
+event:0X0BC0 counters:0 um:zero minimum:1000 name:PM_L2_LD_GRP188 : (Group 188 pm_l2_ld_st) Data Load Count
+event:0X0BC1 counters:1 um:zero minimum:1000 name:PM_L2_ST_MISS_GRP188 : (Group 188 pm_l2_ld_st) Data Store Miss
+event:0X0BC2 counters:2 um:zero minimum:1000 name:PM_L3_PREF_HIT_GRP188 : (Group 188 pm_l2_ld_st) L3 Prefetch Directory Hit
+event:0X0BC3 counters:3 um:zero minimum:10000 name:PM_CYC_GRP188 : (Group 188 pm_l2_ld_st) Processor Cycles
+event:0X0BC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP188 : (Group 188 pm_l2_ld_st) Number of run instructions completed.
+event:0X0BC5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP188 : (Group 188 pm_l2_ld_st) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 189 pm_stcx, STCX
+event:0X0BD0 counters:0 um:zero minimum:1000 name:PM_LARX_LSU_GRP189 : (Group 189 pm_stcx) Larx Finished
+event:0X0BD1 counters:1 um:zero minimum:1000 name:PM_LSU_REJECT_LHS_GRP189 : (Group 189 pm_stcx) The Load Store Unit rejected a load load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully. Combined Unit 0 + 1
+event:0X0BD2 counters:2 um:zero minimum:1000 name:PM_STCX_CMPL_GRP189 : (Group 189 pm_stcx) Conditional stores with reservation completed
+event:0X0BD3 counters:3 um:zero minimum:1000 name:PM_STCX_FAIL_GRP189 : (Group 189 pm_stcx) A stcx (stwcx or stdcx) failed
+event:0X0BD4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP189 : (Group 189 pm_stcx) Number of run instructions completed.
+event:0X0BD5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP189 : (Group 189 pm_stcx) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 190 pm_btac, BTAC
+event:0X0BE0 counters:0 um:zero minimum:1000 name:PM_BTAC_HIT_GRP190 : (Group 190 pm_btac) BTAC Correct Prediction
+event:0X0BE1 counters:1 um:zero minimum:1000 name:PM_BTAC_MISS_GRP190 : (Group 190 pm_btac) BTAC Mispredicted
+event:0X0BE2 counters:2 um:zero minimum:1000 name:PM_STCX_CMPL_GRP190 : (Group 190 pm_btac) Conditional stores with reservation completed
+event:0X0BE3 counters:3 um:zero minimum:1000 name:PM_STCX_FAIL_GRP190 : (Group 190 pm_btac) A stcx (stwcx or stdcx) failed
+event:0X0BE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP190 : (Group 190 pm_btac) Number of run instructions completed.
+event:0X0BE5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP190 : (Group 190 pm_btac) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 191 pm_br_bc, Branch BC events
+event:0X0BF0 counters:0 um:zero minimum:1000 name:PM_BC_PLUS_8_CONV_GRP191 : (Group 191 pm_br_bc) BC+8 Converted
+event:0X0BF1 counters:1 um:zero minimum:1000 name:PM_BC_PLUS_8_RSLV_TAKEN_GRP191 : (Group 191 pm_br_bc) BC+8 Resolve outcome was Taken, resulting in the conditional instruction being canceled
+event:0X0BF2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP191 : (Group 191 pm_br_bc) Processor Cycles
+event:0X0BF3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP191 : (Group 191 pm_br_bc) Number of PowerPC Instructions that completed.
+event:0X0BF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP191 : (Group 191 pm_br_bc) Number of run instructions completed.
+event:0X0BF5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP191 : (Group 191 pm_br_bc) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 192 pm_inst_imc, inst imc events
+event:0X0C00 counters:0 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP192 : (Group 192 pm_inst_imc) Number of instructions resulting from the marked instructions expansion that completed.
+event:0X0C01 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP192 : (Group 192 pm_inst_imc) Number of PowerPC instructions successfully dispatched.
+event:0X0C02 counters:2 um:zero minimum:1000 name:PM_INST_IMC_MATCH_DISP_GRP192 : (Group 192 pm_inst_imc) IMC Matches dispatched
+event:0X0C03 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP192 : (Group 192 pm_inst_imc) Number of PowerPC Instructions that completed.
+event:0X0C04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP192 : (Group 192 pm_inst_imc) Number of run instructions completed.
+event:0X0C05 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP192 : (Group 192 pm_inst_imc) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 193 pm_l2_misc1, L2 load/store Miss events
+event:0X0C10 counters:0 um:zero minimum:1000 name:PM_L2_LDST_GRP193 : (Group 193 pm_l2_misc1) Data Load+Store Count
+event:0X0C11 counters:1 um:zero minimum:1000 name:PM_L2_LDST_MISS_GRP193 : (Group 193 pm_l2_misc1) Data Load+Store Miss
+event:0X0C12 counters:2 um:zero minimum:1000 name:PM_L2_INST_MISS_GRP193 : (Group 193 pm_l2_misc1) Instruction Load Misses
+event:0X0C13 counters:3 um:zero minimum:1000 name:PM_L2_DISP_ALL_GRP193 : (Group 193 pm_l2_misc1) All successful LD/ST dispatches for this thread(i+d)
+event:0X0C14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP193 : (Group 193 pm_l2_misc1) Number of run instructions completed.
+event:0X0C15 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP193 : (Group 193 pm_l2_misc1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 194 pm_l2_misc2, L2 Events
+event:0X0C20 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP194 : (Group 194 pm_l2_misc2) Number of PowerPC Instructions that completed.
+event:0X0C21 counters:1 um:zero minimum:10000 name:PM_CYC_GRP194 : (Group 194 pm_l2_misc2) Processor Cycles
+event:0X0C22 counters:2 um:zero minimum:1000 name:PM_L2_INST_GRP194 : (Group 194 pm_l2_misc2) Instruction Load Count
+event:0X0C23 counters:3 um:zero minimum:1000 name:PM_L2_DISP_ALL_GRP194 : (Group 194 pm_l2_misc2) All successful LD/ST dispatches for this thread(i+d)
+event:0X0C24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP194 : (Group 194 pm_l2_misc2) Number of run instructions completed.
+event:0X0C25 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP194 : (Group 194 pm_l2_misc2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 195 pm_l2_misc3, L2 Events
+event:0X0C30 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP195 : (Group 195 pm_l2_misc3) Number of PowerPC Instructions that completed.
+event:0X0C31 counters:1 um:zero minimum:10000 name:PM_CYC_GRP195 : (Group 195 pm_l2_misc3) Processor Cycles
+event:0X0C32 counters:2 um:zero minimum:1000 name:PM_L2_SYS_PUMP_GRP195 : (Group 195 pm_l2_misc3) RC req that was a global (aka system) pump attempt
+event:0X0C33 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP195 : (Group 195 pm_l2_misc3) Number of run instructions completed.
+event:0X0C34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP195 : (Group 195 pm_l2_misc3) Number of run instructions completed.
+event:0X0C35 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP195 : (Group 195 pm_l2_misc3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 196 pm_l2_misc4, L2 Events
+event:0X0C40 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP196 : (Group 196 pm_l2_misc4) Number of PowerPC Instructions that completed.
+event:0X0C41 counters:1 um:zero minimum:10000 name:PM_CYC_GRP196 : (Group 196 pm_l2_misc4) Processor Cycles
+event:0X0C42 counters:2 um:zero minimum:1000 name:PM_L2_SN_SX_I_DONE_GRP196 : (Group 196 pm_l2_misc4) SNP dispatched and went from Sx or Tx to Ix
+event:0X0C43 counters:3 um:zero minimum:1000 name:PM_L2_SN_M_WR_DONE_GRP196 : (Group 196 pm_l2_misc4) SNP dispatched for a write and was M
+event:0X0C44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP196 : (Group 196 pm_l2_misc4) Number of run instructions completed.
+event:0X0C45 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP196 : (Group 196 pm_l2_misc4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 197 pm_l2_misc5, L2 Events
+event:0X0C50 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP197 : (Group 197 pm_l2_misc5) Number of PowerPC Instructions that completed.
+event:0X0C51 counters:1 um:zero minimum:10000 name:PM_CYC_GRP197 : (Group 197 pm_l2_misc5) Processor Cycles
+event:0X0C52 counters:2 um:zero minimum:1000 name:PM_L2_NODE_PUMP_GRP197 : (Group 197 pm_l2_misc5) RC req that was a local (aka node) pump attempt
+event:0X0C53 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP197 : (Group 197 pm_l2_misc5) Number of run instructions completed.
+event:0X0C54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP197 : (Group 197 pm_l2_misc5) Number of run instructions completed.
+event:0X0C55 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP197 : (Group 197 pm_l2_misc5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 198 pm_l2_misc6, L2 Events
+event:0X0C60 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP198 : (Group 198 pm_l2_misc6) Number of PowerPC Instructions that completed.
+event:0X0C61 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP198 : (Group 198 pm_l2_misc6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0C62 counters:2 um:zero minimum:10000 name:PM_CYC_GRP198 : (Group 198 pm_l2_misc6) Processor Cycles
+event:0X0C63 counters:3 um:zero minimum:1000 name:PM_L2_SN_M_RD_DONE_GRP198 : (Group 198 pm_l2_misc6) SNP dispatched for a read and was M
+event:0X0C64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP198 : (Group 198 pm_l2_misc6) Number of run instructions completed.
+event:0X0C65 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP198 : (Group 198 pm_l2_misc6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 199 pm_ierat, IERAT Events
+event:0X0C70 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP199 : (Group 199 pm_ierat) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
+event:0X0C71 counters:1 um:zero minimum:1000 name:PM_IERAT_XLATE_WR_16MPLUS_GRP199 : (Group 199 pm_ierat) large page 16M+
+event:0X0C72 counters:2 um:zero minimum:1000 name:PM_IERAT_WR_64K_GRP199 : (Group 199 pm_ierat) large page 64k
+event:0X0C73 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP199 : (Group 199 pm_ierat) Number of PowerPC Instructions that completed.
+event:0X0C74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP199 : (Group 199 pm_ierat) Number of run instructions completed.
+event:0X0C75 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP199 : (Group 199 pm_ierat) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 200 pm_disp_clb, Dispatch CLB Events
+event:0X0C80 counters:0 um:zero minimum:1000 name:PM_DISP_CLB_HELD_GRP200 : (Group 200 pm_disp_clb) CLB Hold: Any Reason
+event:0X0C81 counters:1 um:zero minimum:1000 name:PM_DISP_CLB_HELD_SB_GRP200 : (Group 200 pm_disp_clb) Dispatch/CLB Hold: Scoreboard
+event:0X0C82 counters:2 um:zero minimum:10000 name:PM_CYC_GRP200 : (Group 200 pm_disp_clb) Processor Cycles
+event:0X0C83 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP200 : (Group 200 pm_disp_clb) Number of PowerPC Instructions that completed.
+event:0X0C84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP200 : (Group 200 pm_disp_clb) Number of run instructions completed.
+event:0X0C85 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP200 : (Group 200 pm_disp_clb) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 201 pm_dpu, DPU Events
+event:0X0C90 counters:0 um:zero minimum:10000 name:PM_CYC_GRP201 : (Group 201 pm_dpu) Processor Cycles
+event:0X0C91 counters:1 um:zero minimum:1000 name:PM_DPU_HELD_POWER_GRP201 : (Group 201 pm_dpu) Cycles that Instruction Dispatch was held due to power management. More than one hold condition can exist at the same time
+event:0X0C92 counters:2 um:zero minimum:1000 name:PM_DISP_WT_GRP201 : (Group 201 pm_dpu) Dispatched Starved (not held, nothing to dispatch)
+event:0X0C93 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP201 : (Group 201 pm_dpu) Number of PowerPC Instructions that completed.
+event:0X0C94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP201 : (Group 201 pm_dpu) Number of run instructions completed.
+event:0X0C95 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP201 : (Group 201 pm_dpu) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 202 pm_cpu_util, Basic CPU utilization
+event:0X0CA0 counters:0 um:zero minimum:1000 name:PM_RUN_SPURR_GRP202 : (Group 202 pm_cpu_util) Run SPURR
+event:0X0CA1 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP202 : (Group 202 pm_cpu_util) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0CA2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP202 : (Group 202 pm_cpu_util) Processor Cycles
+event:0X0CA3 counters:3 um:zero minimum:1000 name:PM_RUN_PURR_GRP202 : (Group 202 pm_cpu_util) The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads.
+event:0X0CA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP202 : (Group 202 pm_cpu_util) Number of run instructions completed.
+event:0X0CA5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP202 : (Group 202 pm_cpu_util) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 203 pm_overflow1, Overflow events
+event:0X0CB0 counters:0 um:zero minimum:1000 name:PM_PMC4_OVERFLOW_GRP203 : (Group 203 pm_overflow1) Overflows from PMC4 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
+event:0X0CB1 counters:1 um:zero minimum:1000 name:PM_PMC1_OVERFLOW_GRP203 : (Group 203 pm_overflow1) Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
+event:0X0CB2 counters:2 um:zero minimum:1000 name:PM_PMC2_OVERFLOW_GRP203 : (Group 203 pm_overflow1) Overflows from PMC2 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
+event:0X0CB3 counters:3 um:zero minimum:1000 name:PM_PMC3_OVERFLOW_GRP203 : (Group 203 pm_overflow1) Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
+event:0X0CB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP203 : (Group 203 pm_overflow1) Number of run instructions completed.
+event:0X0CB5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP203 : (Group 203 pm_overflow1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 204 pm_overflow2, Overflow events
+event:0X0CC0 counters:0 um:zero minimum:1000 name:PM_PMC5_OVERFLOW_GRP204 : (Group 204 pm_overflow2) Overflows from PMC5 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
+event:0X0CC1 counters:1 um:zero minimum:1000 name:PM_PMC1_OVERFLOW_GRP204 : (Group 204 pm_overflow2) Overflows from PMC1 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
+event:0X0CC2 counters:2 um:zero minimum:1000 name:PM_PMC6_OVERFLOW_GRP204 : (Group 204 pm_overflow2) Overflows from PMC6 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
+event:0X0CC3 counters:3 um:zero minimum:1000 name:PM_PMC3_OVERFLOW_GRP204 : (Group 204 pm_overflow2) Overflows from PMC3 are counted. This effectively widens the PMC. The Overflow from the original PMC will not trigger an exception even if the PMU is configured to generate exceptions on overflow.
+event:0X0CC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP204 : (Group 204 pm_overflow2) Number of run instructions completed.
+event:0X0CC5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP204 : (Group 204 pm_overflow2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 205 pm_rewind, Rewind events
+event:0X0CD0 counters:0 um:zero minimum:1000 name:PM_PMC4_REWIND_GRP205 : (Group 205 pm_rewind) PMC4 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.
+event:0X0CD1 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP205 : (Group 205 pm_rewind) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0CD2 counters:2 um:zero minimum:1000 name:PM_PMC2_REWIND_GRP205 : (Group 205 pm_rewind) PMC2 was counting speculatively. The speculative condition was not met and the counter was restored to its previous value.
+event:0X0CD3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP205 : (Group 205 pm_rewind) Number of PowerPC Instructions that completed.
+event:0X0CD4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP205 : (Group 205 pm_rewind) Number of run instructions completed.
+event:0X0CD5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP205 : (Group 205 pm_rewind) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 206 pm_saved, Saved Events
+event:0X0CE0 counters:0 um:zero minimum:1000 name:PM_PMC2_SAVED_GRP206 : (Group 206 pm_saved) PMC2 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.
+event:0X0CE1 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP206 : (Group 206 pm_saved) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0CE2 counters:2 um:zero minimum:1000 name:PM_PMC4_SAVED_GRP206 : (Group 206 pm_saved) PMC4 was counting speculatively. The speculative condition was met and the counter value was committed by copying it to the backup register.
+event:0X0CE3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP206 : (Group 206 pm_saved) Number of PowerPC Instructions that completed.
+event:0X0CE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP206 : (Group 206 pm_saved) Number of run instructions completed.
+event:0X0CE5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP206 : (Group 206 pm_saved) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 207 pm_tlbie, TLBIE Events
+event:0X0CF0 counters:0 um:zero minimum:1000 name:PM_FLUSH_DISP_TLBIE_GRP207 : (Group 207 pm_tlbie) Dispatch Flush: TLBIE
+event:0X0CF1 counters:1 um:zero minimum:1000 name:PM_DISP_CLB_HELD_TLBIE_GRP207 : (Group 207 pm_tlbie) Dispatch Hold: Due to TLBIE
+event:0X0CF2 counters:2 um:zero minimum:1000 name:PM_SNOOP_TLBIE_GRP207 : (Group 207 pm_tlbie) A tlbie was snooped from another processor.
+event:0X0CF3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP207 : (Group 207 pm_tlbie) Number of PowerPC Instructions that completed.
+event:0X0CF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP207 : (Group 207 pm_tlbie) Number of run instructions completed.
+event:0X0CF5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP207 : (Group 207 pm_tlbie) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 208 pm_id_miss_erat_l1, Instruction/Data miss from ERAT/L1 cache
+event:0X0D00 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP208 : (Group 208 pm_id_miss_erat_l1) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
+event:0X0D01 counters:1 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP208 : (Group 208 pm_id_miss_erat_l1) An instruction fetch request missed the L1 cache.
+event:0X0D02 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP208 : (Group 208 pm_id_miss_erat_l1) A store missed the dcache. Combined Unit 0 + 1.
+event:0X0D03 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP208 : (Group 208 pm_id_miss_erat_l1) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
+event:0X0D04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP208 : (Group 208 pm_id_miss_erat_l1) Number of run instructions completed.
+event:0X0D05 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP208 : (Group 208 pm_id_miss_erat_l1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 209 pm_id_miss_erat_tlab, Instruction/Data miss from ERAT/TLB
+event:0X0D10 counters:0 um:zero minimum:10000 name:PM_CYC_GRP209 : (Group 209 pm_id_miss_erat_tlab) Processor Cycles
+event:0X0D11 counters:1 um:zero minimum:1000 name:PM_LSU_DERAT_MISS_GRP209 : (Group 209 pm_id_miss_erat_tlab) Total D-ERAT Misses. Requests that miss the Derat are rejected and retried until the request hits in the Erat. This may result in multiple erat misses for the same instruction. Combined Unit 0 + 1.
+event:0X0D12 counters:2 um:zero minimum:1000 name:PM_DTLB_MISS_GRP209 : (Group 209 pm_id_miss_erat_tlab) Data TLB misses, all page sizes.
+event:0X0D13 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP209 : (Group 209 pm_id_miss_erat_tlab) A TLB miss for an Instruction Fetch has occurred
+event:0X0D14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP209 : (Group 209 pm_id_miss_erat_tlab) Number of run instructions completed.
+event:0X0D15 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP209 : (Group 209 pm_id_miss_erat_tlab) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 210 pm_compat_utilization1, Basic CPU utilization
+event:0X0D20 counters:0 um:zero minimum:1000 name:PM_ANY_THRD_RUN_CYC_GRP210 : (Group 210 pm_compat_utilization1) One of threads in run_cycles
+event:0X0D21 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP210 : (Group 210 pm_compat_utilization1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0D22 counters:2 um:zero minimum:10000 name:PM_CYC_GRP210 : (Group 210 pm_compat_utilization1) Processor Cycles
+event:0X0D23 counters:3 um:zero minimum:1000 name:PM_RUN_PURR_GRP210 : (Group 210 pm_compat_utilization1) The Processor Utilization of Resources Register was incremented while the run latch was set. The PURR registers will be incremented roughly in the ratio in which the instructions are dispatched from the two threads.
+event:0X0D24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP210 : (Group 210 pm_compat_utilization1) Number of run instructions completed.
+event:0X0D25 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP210 : (Group 210 pm_compat_utilization1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 211 pm_compat_utilization2, CPI and utilization data
+event:0X0D30 counters:0 um:zero minimum:1000 name:PM_FLOP_GRP211 : (Group 211 pm_compat_utilization2) A floating point operation has completed
+event:0X0D31 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP211 : (Group 211 pm_compat_utilization2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0D32 counters:2 um:zero minimum:10000 name:PM_CYC_GRP211 : (Group 211 pm_compat_utilization2) Processor Cycles
+event:0X0D33 counters:3 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP211 : (Group 211 pm_compat_utilization2) Number of run instructions completed.
+event:0X0D34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP211 : (Group 211 pm_compat_utilization2) Number of run instructions completed.
+event:0X0D35 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP211 : (Group 211 pm_compat_utilization2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 212 pm_compat_cpi_1plus_ppc, Misc CPI and utilization data
+event:0X0D40 counters:0 um:zero minimum:1000 name:PM_1PLUS_PPC_CMPL_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) A group containing at least one PPC instruction completed. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X0D41 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0D42 counters:2 um:zero minimum:1000 name:PM_INST_DISP_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) Number of PowerPC instructions successfully dispatched.
+event:0X0D43 counters:3 um:zero minimum:1000 name:PM_1PLUS_PPC_DISP_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) A group containing at least one PPC instruction was dispatched. For microcoded instructions that span multiple groups, this will only occur once.
+event:0X0D44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) Number of run instructions completed.
+event:0X0D45 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP212 : (Group 212 pm_compat_cpi_1plus_ppc) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 213 pm_compat_l1_dcache_load_store_miss, L1 D-Cache load/store miss
+event:0X0D50 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) Number of PowerPC Instructions that completed.
+event:0X0D51 counters:1 um:zero minimum:1000 name:PM_ST_FIN_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) Store requests sent to the nest.
+event:0X0D52 counters:2 um:zero minimum:1000 name:PM_ST_MISS_L1_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) A store missed the dcache. Combined Unit 0 + 1.
+event:0X0D53 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
+event:0X0D54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) Number of run instructions completed.
+event:0X0D55 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP213 : (Group 213 pm_compat_l1_dcache_load_store_miss) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 214 pm_compat_l1_cache_load, L1 Cache loads
+event:0X0D60 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP214 : (Group 214 pm_compat_l1_cache_load) Number of PowerPC Instructions that completed.
+event:0X0D61 counters:1 um:zero minimum:1000 name:PM_DATA_FROM_L2MISS_GRP214 : (Group 214 pm_compat_l1_cache_load) The processor's Data Cache was reloaded but not from the local L2.
+event:0X0D62 counters:2 um:zero minimum:1000 name:PM_L1_DCACHE_RELOAD_VALID_GRP214 : (Group 214 pm_compat_l1_cache_load) The data source information is valid,the data cache has been reloaded. Prior to POWER5+ this included data cache reloads due to prefetch activity. With POWER5+ this now only includes reloads due to demand loads.
+event:0X0D63 counters:3 um:zero minimum:1000 name:PM_LD_MISS_L1_GRP214 : (Group 214 pm_compat_l1_cache_load) Load references that miss the Level 1 Data cache. Combined unit 0 + 1.
+event:0X0D64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP214 : (Group 214 pm_compat_l1_cache_load) Number of run instructions completed.
+event:0X0D65 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP214 : (Group 214 pm_compat_l1_cache_load) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 215 pm_compat_instruction_directory, Instruction Directory
+event:0X0D70 counters:0 um:zero minimum:1000 name:PM_IERAT_MISS_GRP215 : (Group 215 pm_compat_instruction_directory) A translation request missed the Instruction Effective to Real Address Translation (ERAT) table
+event:0X0D71 counters:1 um:zero minimum:1000 name:PM_L1_ICACHE_MISS_GRP215 : (Group 215 pm_compat_instruction_directory) An instruction fetch request missed the L1 cache.
+event:0X0D72 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP215 : (Group 215 pm_compat_instruction_directory) Number of PowerPC Instructions that completed.
+event:0X0D73 counters:3 um:zero minimum:1000 name:PM_ITLB_MISS_GRP215 : (Group 215 pm_compat_instruction_directory) A TLB miss for an Instruction Fetch has occurred
+event:0X0D74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP215 : (Group 215 pm_compat_instruction_directory) Number of run instructions completed.
+event:0X0D75 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP215 : (Group 215 pm_compat_instruction_directory) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 216 pm_compat_suspend, Suspend Events
+event:0X0D80 counters:0 um:zero minimum:1000 name:PM_SUSPENDED_GRP216 : (Group 216 pm_compat_suspend) The counter is suspended (does not count)
+event:0X0D81 counters:1 um:zero minimum:1000 name:PM_SUSPENDED_GRP216 : (Group 216 pm_compat_suspend) The counter is suspended (does not count)
+event:0X0D82 counters:2 um:zero minimum:1000 name:PM_SUSPENDED_GRP216 : (Group 216 pm_compat_suspend) The counter is suspended (does not count)
+event:0X0D83 counters:3 um:zero minimum:1000 name:PM_SUSPENDED_GRP216 : (Group 216 pm_compat_suspend) The counter is suspended (does not count)
+event:0X0D84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP216 : (Group 216 pm_compat_suspend) Number of run instructions completed.
+event:0X0D85 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP216 : (Group 216 pm_compat_suspend) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 217 pm_compat_misc_events1, Misc Events
+event:0X0D90 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP217 : (Group 217 pm_compat_misc_events1) Number of PowerPC Instructions that completed.
+event:0X0D91 counters:1 um:zero minimum:1000 name:PM_EXT_INT_GRP217 : (Group 217 pm_compat_misc_events1) An interrupt due to an external exception occurred
+event:0X0D92 counters:2 um:zero minimum:1000 name:PM_TB_BIT_TRANS_GRP217 : (Group 217 pm_compat_misc_events1) When the selected time base bit (as specified in MMCR0[TBSEL])transitions from 0 to 1
+event:0X0D93 counters:3 um:zero minimum:10000 name:PM_CYC_GRP217 : (Group 217 pm_compat_misc_events1) Processor Cycles
+event:0X0D94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP217 : (Group 217 pm_compat_misc_events1) Number of run instructions completed.
+event:0X0D95 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP217 : (Group 217 pm_compat_misc_events1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 218 pm_compat_misc_events2, Misc Events
+event:0X0DA0 counters:0 um:zero minimum:1000 name:PM_INST_IMC_MATCH_CMPL_GRP218 : (Group 218 pm_compat_misc_events2) Number of instructions resulting from the marked instructions expansion that completed.
+event:0X0DA1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP218 : (Group 218 pm_compat_misc_events2) Number of PowerPC instructions successfully dispatched.
+event:0X0DA2 counters:2 um:zero minimum:1000 name:PM_THRD_CONC_RUN_INST_GRP218 : (Group 218 pm_compat_misc_events2) Instructions completed by this thread when both threads had their run latches set.
+event:0X0DA3 counters:3 um:zero minimum:1000 name:PM_FLUSH_GRP218 : (Group 218 pm_compat_misc_events2) Flushes occurred including LSU and Branch flushes.
+event:0X0DA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP218 : (Group 218 pm_compat_misc_events2) Number of run instructions completed.
+event:0X0DA5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP218 : (Group 218 pm_compat_misc_events2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 219 pm_compat_misc_events3, Misc Events
+event:0X0DB0 counters:0 um:zero minimum:1000 name:PM_GCT_NOSLOT_CYC_GRP219 : (Group 219 pm_compat_misc_events3) Cycles when the Global Completion Table has no slots from this thread.
+event:0X0DB1 counters:1 um:zero minimum:1000 name:PM_INST_DISP_GRP219 : (Group 219 pm_compat_misc_events3) Number of PowerPC instructions successfully dispatched.
+event:0X0DB2 counters:2 um:zero minimum:10000 name:PM_CYC_GRP219 : (Group 219 pm_compat_misc_events3) Processor Cycles
+event:0X0DB3 counters:3 um:zero minimum:1000 name:PM_BR_MPRED_GRP219 : (Group 219 pm_compat_misc_events3) A branch instruction was incorrectly predicted. This could have been a target prediction, a condition prediction, or both
+event:0X0DB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP219 : (Group 219 pm_compat_misc_events3) Number of run instructions completed.
+event:0X0DB5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP219 : (Group 219 pm_compat_misc_events3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 220 pm_mrk_br, Marked Branch events
+event:0X0DC0 counters:0 um:zero minimum:1000 name:PM_MRK_BR_TAKEN_GRP220 : (Group 220 pm_mrk_br) A marked branch was taken
+event:0X0DC1 counters:1 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_GRP220 : (Group 220 pm_mrk_br) Marked L1 D cache load misses
+event:0X0DC2 counters:2 um:zero minimum:1000 name:PM_MRK_BR_MPRED_GRP220 : (Group 220 pm_mrk_br) A marked branch was mispredicted
+event:0X0DC3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP220 : (Group 220 pm_mrk_br) Number of PowerPC Instructions that completed.
+event:0X0DC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP220 : (Group 220 pm_mrk_br) Number of run instructions completed.
+event:0X0DC5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP220 : (Group 220 pm_mrk_br) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 221 pm_mrk_dsource1, Marked data sources
+event:0X0DD0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DMEM_GRP221 : (Group 221 pm_mrk_dsource1) The processor's Data Cache was reloaded with data from memory attached to a distant module due to a marked load.
+event:0X0DD1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DMEM_CYC_GRP221 : (Group 221 pm_mrk_dsource1) Marked ld latency Data Source 1110 (Distant Memory)
+event:0X0DD2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_MOD_GRP221 : (Group 221 pm_mrk_dsource1) Marked data loaded from another L2 on same chip modified
+event:0X0DD3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_MOD_CYC_GRP221 : (Group 221 pm_mrk_dsource1) Marked ld latency Data source 0101 (L2.1 M same chip)
+event:0X0DD4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP221 : (Group 221 pm_mrk_dsource1) Number of run instructions completed.
+event:0X0DD5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP221 : (Group 221 pm_mrk_dsource1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 222 pm_mrk_dsource2, Marked data sources
+event:0X0DE0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_GRP222 : (Group 222 pm_mrk_dsource2) The processor's Data Cache was reloaded from the local L3 due to a marked load.
+event:0X0DE1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_CYC_GRP222 : (Group 222 pm_mrk_dsource2) Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.
+event:0X0DE2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_LMEM_GRP222 : (Group 222 pm_mrk_dsource2) The processor’s Data Cache was reloaded due to a marked load from memory attached to the same module this proccessor is located on.
+event:0X0DE3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3_CYC_GRP222 : (Group 222 pm_mrk_dsource2) Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.
+event:0X0DE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP222 : (Group 222 pm_mrk_dsource2) Number of run instructions completed.
+event:0X0DE5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP222 : (Group 222 pm_mrk_dsource2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 223 pm_mrk_dsource3, Marked data sources
+event:0X0DF0 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L31_MOD_GRP223 : (Group 223 pm_mrk_dsource3) Marked data loaded from another L3 on same chip modified
+event:0X0DF1 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_SHR_CYC_GRP223 : (Group 223 pm_mrk_dsource3) Marked load latency Data source 0100 (L2.1 S)
+event:0X0DF2 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L21_SHR_GRP223 : (Group 223 pm_mrk_dsource3) Marked data loaded from another L2 on same chip shared
+event:0X0DF3 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L31_MOD_CYC_GRP223 : (Group 223 pm_mrk_dsource3) Marked ld latency Data source 0111 (L3.1 M same chip)
+event:0X0DF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP223 : (Group 223 pm_mrk_dsource3) Number of run instructions completed.
+event:0X0DF5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP223 : (Group 223 pm_mrk_dsource3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 224 pm_mrk_dsource4, Marked data sources
+event:0X0E00 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_GRP224 : (Group 224 pm_mrk_dsource4) The processor's Data Cache was reloaded from the local L2 due to a marked load.
+event:0X0E01 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2_CYC_GRP224 : (Group 224 pm_mrk_dsource4) Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.
+event:0X0E02 counters:2 um:zero minimum:1000 name:PM_DATA_FROM_RMEM_GRP224 : (Group 224 pm_mrk_dsource4) The processor’s Data Cache was reloaded from memory attached to a different module than this proccessor is located on.
+event:0X0E03 counters:3 um:zero minimum:1000 name:PM_DATA_FROM_LMEM_GRP224 : (Group 224 pm_mrk_dsource4) The processor’s Data Cache was reloaded from memory attached to the same module this proccessor is located on.
+event:0X0E04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP224 : (Group 224 pm_mrk_dsource4) Number of run instructions completed.
+event:0X0E05 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP224 : (Group 224 pm_mrk_dsource4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 225 pm_mrk_dsource5, Marked data sources
+event:0X0E10 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_MOD_GRP225 : (Group 225 pm_mrk_dsource5) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a remote module due to a marked load.
+event:0X0E11 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_SHR_CYC_GRP225 : (Group 225 pm_mrk_dsource5) Marked ld latency Data Source 1010 (Distant L2.75/L3.75 S)
+event:0X0E12 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_SHR_GRP225 : (Group 225 pm_mrk_dsource5) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a distant module due to a marked load.
+event:0X0E13 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_MOD_CYC_GRP225 : (Group 225 pm_mrk_dsource5) Marked ld latency Data source 1001 (L2.5/L3.5 M same 4 chip node)
+event:0X0E14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP225 : (Group 225 pm_mrk_dsource5) Number of run instructions completed.
+event:0X0E15 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP225 : (Group 225 pm_mrk_dsource5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 226 pm_mrk_dsource6, Marked data sources
+event:0X0E20 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_SHR_GRP226 : (Group 226 pm_mrk_dsource6) The processor's Data Cache was reloaded with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load
+event:0X0E21 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RL2L3_SHR_CYC_GRP226 : (Group 226 pm_mrk_dsource6) Marked load latency Data Source 1000 (Remote L2.5/L3.5 S)
+event:0X0E22 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_GRP226 : (Group 226 pm_mrk_dsource6) The processor’s Data Cache was reloaded due to a marked load from memory attached to a different module than this proccessor is located on.
+event:0X0E23 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_RMEM_CYC_GRP226 : (Group 226 pm_mrk_dsource6) Cycles a marked load waited for data from this level of the storage system. Counting begins when a marked load misses the data cache and ends when the data is reloaded into the data cache. To calculate average latency divide this count by the number of marked misses to the same level.
+event:0X0E24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP226 : (Group 226 pm_mrk_dsource6) Number of run instructions completed.
+event:0X0E25 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP226 : (Group 226 pm_mrk_dsource6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 227 pm_mrk_dsource7, Marked data sources
+event:0X0E30 counters:0 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L31_SHR_GRP227 : (Group 227 pm_mrk_dsource7) Marked data loaded from another L3 on same chip shared
+event:0X0E31 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L31_SHR_CYC_GRP227 : (Group 227 pm_mrk_dsource7) Marked load latency Data source 0110 (L3.1 S)
+event:0X0E32 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP227 : (Group 227 pm_mrk_dsource7) One of the execution units finished a marked instruction. Instructions that finish may not necessary complete
+event:0X0E33 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L2MISS_GRP227 : (Group 227 pm_mrk_dsource7) DL1 was reloaded from beyond L2 due to a marked demand load.
+event:0X0E34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP227 : (Group 227 pm_mrk_dsource7) Number of run instructions completed.
+event:0X0E35 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP227 : (Group 227 pm_mrk_dsource7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 228 pm_mrk_dsource8, Marked data sources
+event:0X0E40 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_EXPOSED_CYC_COUNT_GRP228 : (Group 228 pm_mrk_dsource8) Marked Load exposed Miss (use edge detect to count #)
+event:0X0E41 counters:1 um:zero minimum:1000 name:PM_MRK_DATA_FROM_L3MISS_GRP228 : (Group 228 pm_mrk_dsource8) DL1 was reloaded from beyond L3 due to a marked load.
+event:0X0E42 counters:2 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_MOD_GRP228 : (Group 228 pm_mrk_dsource8) The processor's Data Cache was reloaded with modified (M) data from an L2 or L3 on a distant module due to a marked load.
+event:0X0E43 counters:3 um:zero minimum:1000 name:PM_MRK_DATA_FROM_DL2L3_MOD_CYC_GRP228 : (Group 228 pm_mrk_dsource8) Marked ld latency Data source 1011 (L2.75/L3.75 M different 4 chip node)
+event:0X0E44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP228 : (Group 228 pm_mrk_dsource8) Number of run instructions completed.
+event:0X0E45 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP228 : (Group 228 pm_mrk_dsource8) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 229 pm_mrk_lsu_flush1, Marked LSU Flush
+event:0X0E50 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_ULD_GRP229 : (Group 229 pm_mrk_lsu_flush1) A marked load was flushed because it was unaligned (crossed a 64byte boundary, or 32 byte if it missed the L1)
+event:0X0E51 counters:1 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_UST_GRP229 : (Group 229 pm_mrk_lsu_flush1) A marked store was flushed because it was unaligned
+event:0X0E52 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP229 : (Group 229 pm_mrk_lsu_flush1) Number of PowerPC Instructions that completed.
+event:0X0E53 counters:3 um:zero minimum:10000 name:PM_CYC_GRP229 : (Group 229 pm_mrk_lsu_flush1) Processor Cycles
+event:0X0E54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP229 : (Group 229 pm_mrk_lsu_flush1) Number of run instructions completed.
+event:0X0E55 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP229 : (Group 229 pm_mrk_lsu_flush1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 230 pm_mrk_lsu_flush2, Marked LSU Flush
+event:0X0E60 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP230 : (Group 230 pm_mrk_lsu_flush2) Number of PowerPC Instructions that completed.
+event:0X0E61 counters:1 um:zero minimum:10000 name:PM_CYC_GRP230 : (Group 230 pm_mrk_lsu_flush2) Processor Cycles
+event:0X0E62 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_LRQ_GRP230 : (Group 230 pm_mrk_lsu_flush2) Load Hit Load or Store Hit Load flush. A marked load was flushed because it executed before an older store and they had overlapping data OR two loads executed out of order and they have byte overlap and there was a snoop in between to an overlapped byte.
+event:0X0E63 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_SRQ_GRP230 : (Group 230 pm_mrk_lsu_flush2) Load Hit Store flush. A marked load was flushed because it hits (overlaps) an older store that is already in the SRQ or in the same group. If the real addresses match but the effective addresses do not, an alias condition exists that prevents store forwarding. If the load and store are in the same group the load must be flushed to separate the two instructions.
+event:0X0E64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP230 : (Group 230 pm_mrk_lsu_flush2) Number of run instructions completed.
+event:0X0E65 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP230 : (Group 230 pm_mrk_lsu_flush2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 231 pm_mrk_rejects, Marked rejects
+event:0X0E70 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_LHS_GRP231 : (Group 231 pm_mrk_rejects) The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully
+event:0X0E71 counters:1 um:zero minimum:1000 name:PM_MRK_LSU_FLUSH_GRP231 : (Group 231 pm_mrk_rejects) Marked flush initiated by LSU
+event:0X0E72 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP231 : (Group 231 pm_mrk_rejects) Number of PowerPC Instructions that completed.
+event:0X0E73 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_GRP231 : (Group 231 pm_mrk_rejects) LSU marked reject (up to 2 per cycle)
+event:0X0E74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP231 : (Group 231 pm_mrk_rejects) Number of run instructions completed.
+event:0X0E75 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP231 : (Group 231 pm_mrk_rejects) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 232 pm_mrk_inst, Marked instruction events
+event:0X0E80 counters:0 um:zero minimum:1000 name:PM_MRK_INST_ISSUED_GRP232 : (Group 232 pm_mrk_inst) A marked instruction was issued to an execution unit.
+event:0X0E81 counters:1 um:zero minimum:1000 name:PM_MRK_INST_DISP_GRP232 : (Group 232 pm_mrk_inst) A marked instruction was dispatched
+event:0X0E82 counters:2 um:zero minimum:1000 name:PM_MRK_INST_FIN_GRP232 : (Group 232 pm_mrk_inst) One of the execution units finished a marked instruction. Instructions that finish may not necessary complete
+event:0X0E83 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP232 : (Group 232 pm_mrk_inst) Number of PowerPC Instructions that completed.
+event:0X0E84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP232 : (Group 232 pm_mrk_inst) Number of run instructions completed.
+event:0X0E85 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP232 : (Group 232 pm_mrk_inst) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 233 pm_mrk_st, Marked stores events
+event:0X0E90 counters:0 um:zero minimum:1000 name:PM_MRK_ST_CMPL_GRP233 : (Group 233 pm_mrk_st) A sampled store has completed (data home)
+event:0X0E91 counters:1 um:zero minimum:1000 name:PM_MRK_ST_NEST_GRP233 : (Group 233 pm_mrk_st) A sampled store has been sent to the memory subsystem
+event:0X0E92 counters:2 um:zero minimum:1000 name:PM_MRK_ST_CMPL_INT_GRP233 : (Group 233 pm_mrk_st) A marked store previously sent to the memory subsystem completed (data home) after requiring intervention
+event:0X0E93 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP233 : (Group 233 pm_mrk_st) Number of PowerPC Instructions that completed.
+event:0X0E94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP233 : (Group 233 pm_mrk_st) Number of run instructions completed.
+event:0X0E95 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP233 : (Group 233 pm_mrk_st) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 234 pm_mrk_dtlb_miss1, Marked Data TLB Miss
+event:0X0EA0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Number of PowerPC Instructions that completed.
+event:0X0EA1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
+event:0X0EA2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_64K_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
+event:0X0EA3 counters:3 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16M_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Data TLB references to 16M pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
+event:0X0EA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Number of run instructions completed.
+event:0X0EA5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP234 : (Group 234 pm_mrk_dtlb_miss1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 235 pm_mrk_dtlb_miss2, Marked Data TLB Miss
+event:0X0EB0 counters:0 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_16G_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Data TLB references to 16GB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
+event:0X0EB1 counters:1 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_4K_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Data TLB references to 4KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
+event:0X0EB2 counters:2 um:zero minimum:1000 name:PM_MRK_DTLB_MISS_64K_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Data TLB references to 64KB pages by a marked instruction that missed the TLB. Page size is determined at TLB reload time.
+event:0X0EB3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Number of PowerPC Instructions that completed.
+event:0X0EB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Number of run instructions completed.
+event:0X0EB5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP235 : (Group 235 pm_mrk_dtlb_miss2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 236 pm_mrk_derat_miss1, Marked DERAT Miss events
+event:0X0EC0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP236 : (Group 236 pm_mrk_derat_miss1) Number of PowerPC Instructions that completed.
+event:0X0EC1 counters:1 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_64K_GRP236 : (Group 236 pm_mrk_derat_miss1) A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
+event:0X0EC2 counters:2 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_16M_GRP236 : (Group 236 pm_mrk_derat_miss1) A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
+event:0X0EC3 counters:3 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_16G_GRP236 : (Group 236 pm_mrk_derat_miss1) A marked data request (load or store) missed the ERAT for 16G page and resulted in an ERAT reload.
+event:0X0EC4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP236 : (Group 236 pm_mrk_derat_miss1) Number of run instructions completed.
+event:0X0EC5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP236 : (Group 236 pm_mrk_derat_miss1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 237 pm_mrk_derat_miss2, Marked DERAT Miss events
+event:0X0ED0 counters:0 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_4K_GRP237 : (Group 237 pm_mrk_derat_miss2) A marked data request (load or store) missed the ERAT for 4K page and resulted in an ERAT reload.
+event:0X0ED1 counters:1 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_64K_GRP237 : (Group 237 pm_mrk_derat_miss2) A marked data request (load or store) missed the ERAT for 64K page and resulted in an ERAT reload.
+event:0X0ED2 counters:2 um:zero minimum:1000 name:PM_MRK_DERAT_MISS_16M_GRP237 : (Group 237 pm_mrk_derat_miss2) A marked data request (load or store) missed the ERAT for 16M page and resulted in an ERAT reload.
+event:0X0ED3 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP237 : (Group 237 pm_mrk_derat_miss2) Number of PowerPC Instructions that completed.
+event:0X0ED4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP237 : (Group 237 pm_mrk_derat_miss2) Number of run instructions completed.
+event:0X0ED5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP237 : (Group 237 pm_mrk_derat_miss2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 238 pm_mrk_misc_miss, marked Miss Events
+event:0X0EE0 counters:0 um:zero minimum:1000 name:PM_MRK_LD_MISS_EXPOSED_CYC_GRP238 : (Group 238 pm_mrk_misc_miss) Marked Load exposed Miss
+event:0X0EE1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP238 : (Group 238 pm_mrk_misc_miss) Number of PowerPC Instructions that completed.
+event:0X0EE2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_DERAT_MISS_GRP238 : (Group 238 pm_mrk_misc_miss) Marked DERAT Miss
+event:0X0EE3 counters:3 um:zero minimum:1000 name:PM_MRK_LD_MISS_L1_CYC_GRP238 : (Group 238 pm_mrk_misc_miss) L1 data load miss cycles
+event:0X0EE4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP238 : (Group 238 pm_mrk_misc_miss) Number of run instructions completed.
+event:0X0EE5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP238 : (Group 238 pm_mrk_misc_miss) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 239 pm_mrk_pteg1, Marked PTEG
+event:0X0EF0 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP239 : (Group 239 pm_mrk_pteg1) Number of PowerPC Instructions that completed.
+event:0X0EF1 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DMEM_GRP239 : (Group 239 pm_mrk_pteg1) A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.
+event:0X0EF2 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L21_MOD_GRP239 : (Group 239 pm_mrk_pteg1) Marked PTEG loaded from another L2 on same chip modified
+event:0X0EF3 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L21_SHR_GRP239 : (Group 239 pm_mrk_pteg1) Marked PTEG loaded from another L2 on same chip shared
+event:0X0EF4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP239 : (Group 239 pm_mrk_pteg1) Number of run instructions completed.
+event:0X0EF5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP239 : (Group 239 pm_mrk_pteg1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 240 pm_mrk_pteg2, Marked PTEG
+event:0X0F00 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L2_GRP240 : (Group 240 pm_mrk_pteg2) A Page Table Entry was loaded into the ERAT from the local L2 due to a marked load or store.
+event:0X0F01 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RL2L3_SHR_GRP240 : (Group 240 pm_mrk_pteg2) A Page Table Entry was loaded into the ERAT from memory attached to a different module than this proccessor is located on due to a marked load or store.
+event:0X0F02 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RMEM_GRP240 : (Group 240 pm_mrk_pteg2) A Page Table Entry was loaded into the ERAT. POWER6 does not have a TLB
+event:0X0F03 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP240 : (Group 240 pm_mrk_pteg2) Number of PowerPC Instructions that completed.
+event:0X0F04 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP240 : (Group 240 pm_mrk_pteg2) Number of run instructions completed.
+event:0X0F05 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP240 : (Group 240 pm_mrk_pteg2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 241 pm_mrk_pteg3, Marked PTEG
+event:0X0F10 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP241 : (Group 241 pm_mrk_pteg3) Number of PowerPC Instructions that completed.
+event:0X0F11 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L31_SHR_GRP241 : (Group 241 pm_mrk_pteg3) Marked PTEG loaded from another L3 on same chip shared
+event:0X0F12 counters:2 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L21_MOD_GRP241 : (Group 241 pm_mrk_pteg3) Marked PTEG loaded from another L2 on same chip modified
+event:0X0F13 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_DL2L3_MOD_GRP241 : (Group 241 pm_mrk_pteg3) A Page Table Entry was loaded into the ERAT with modified (M) data from an L2 or L3 on a distant module due to a marked load or store.
+event:0X0F14 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP241 : (Group 241 pm_mrk_pteg3) Number of run instructions completed.
+event:0X0F15 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP241 : (Group 241 pm_mrk_pteg3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 242 pm_mrk_pteg4, Marked PTEG
+event:0X0F20 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L31_MOD_GRP242 : (Group 242 pm_mrk_pteg4) Marked PTEG loaded from another L3 on same chip modified
+event:0X0F21 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L3_GRP242 : (Group 242 pm_mrk_pteg4) A Page Table Entry was loaded into the ERAT from the local L3 due to a marked load or store.
+event:0X0F22 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP242 : (Group 242 pm_mrk_pteg4) Number of PowerPC Instructions that completed.
+event:0X0F23 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L2MISS_GRP242 : (Group 242 pm_mrk_pteg4) A Page Table Entry was loaded into the ERAT but not from the local L2 due to a marked load or store.
+event:0X0F24 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP242 : (Group 242 pm_mrk_pteg4) Number of run instructions completed.
+event:0X0F25 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP242 : (Group 242 pm_mrk_pteg4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 243 pm_mrk_pteg5, Marked PTEG
+event:0X0F30 counters:0 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_RL2L3_MOD_GRP243 : (Group 243 pm_mrk_pteg5) A Page Table Entry was loaded into the ERAT with shared (T or SL) data from an L2 or L3 on a remote module due to a marked load or store.
+event:0X0F31 counters:1 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_L3MISS_GRP243 : (Group 243 pm_mrk_pteg5) A Page Table Entry was loaded into the ERAT from beyond the L3 due to a marked load or store
+event:0X0F32 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP243 : (Group 243 pm_mrk_pteg5) Number of PowerPC Instructions that completed.
+event:0X0F33 counters:3 um:zero minimum:1000 name:PM_MRK_PTEG_FROM_LMEM_GRP243 : (Group 243 pm_mrk_pteg5) A Page Table Entry was loaded into the ERAT from memory attached to the same module this proccessor is located on due to a marked load or store.
+event:0X0F34 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP243 : (Group 243 pm_mrk_pteg5) Number of run instructions completed.
+event:0X0F35 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP243 : (Group 243 pm_mrk_pteg5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 244 pm_mrk_misc1, Marked misc events
+event:0X0F40 counters:0 um:zero minimum:1000 name:PM_MRK_STCX_FAIL_GRP244 : (Group 244 pm_mrk_misc1) A marked stcx (stwcx or stdcx) failed
+event:0X0F41 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP244 : (Group 244 pm_mrk_misc1) Number of PowerPC Instructions that completed.
+event:0X0F42 counters:2 um:zero minimum:1000 name:PM_MRK_IFU_FIN_GRP244 : (Group 244 pm_mrk_misc1) The Instruction Fetch Unit finished a marked instruction.
+event:0X0F43 counters:3 um:zero minimum:1000 name:PM_MRK_INST_TIMEO_GRP244 : (Group 244 pm_mrk_misc1) The number of instructions finished since the last progress indicator from a marked instruction exceeded the threshold. The marked instruction was flushed.
+event:0X0F44 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP244 : (Group 244 pm_mrk_misc1) Number of run instructions completed.
+event:0X0F45 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP244 : (Group 244 pm_mrk_misc1) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 245 pm_mrk_misc2, Marked misc events
+event:0X0F50 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP245 : (Group 245 pm_mrk_misc2) Number of PowerPC Instructions that completed.
+event:0X0F51 counters:1 um:zero minimum:1000 name:PM_MRK_FXU_FIN_GRP245 : (Group 245 pm_mrk_misc2) One of the Fixed Point Units finished a marked instruction. Instructions that finish may not necessary complete.
+event:0X0F52 counters:2 um:zero minimum:1000 name:PM_MRK_IFU_FIN_GRP245 : (Group 245 pm_mrk_misc2) The Instruction Fetch Unit finished a marked instruction.
+event:0X0F53 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP245 : (Group 245 pm_mrk_misc2) One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete
+event:0X0F54 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP245 : (Group 245 pm_mrk_misc2) Number of run instructions completed.
+event:0X0F55 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP245 : (Group 245 pm_mrk_misc2) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 246 pm_mrk_misc3, Marked misc events
+event:0X0F60 counters:0 um:zero minimum:10000 name:PM_INST_CMPL_GRP246 : (Group 246 pm_mrk_misc3) Number of PowerPC Instructions that completed.
+event:0X0F61 counters:1 um:zero minimum:1000 name:PM_MRK_BRU_FIN_GRP246 : (Group 246 pm_mrk_misc3) The branch unit finished a marked instruction. Instructions that finish may not necessary complete.
+event:0X0F62 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_PARTIAL_CDF_GRP246 : (Group 246 pm_mrk_misc3) A partial cacheline was returned from the L3 for a marked load
+event:0X0F63 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP246 : (Group 246 pm_mrk_misc3) One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete
+event:0X0F64 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP246 : (Group 246 pm_mrk_misc3) Number of run instructions completed.
+event:0X0F65 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP246 : (Group 246 pm_mrk_misc3) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 247 pm_mrk_misc4, Marked misc events
+event:0X0F70 counters:0 um:zero minimum:1000 name:PM_MRK_FIN_STALL_CYC_GRP247 : (Group 247 pm_mrk_misc4) Marked instruction Finish Stall cycles (marked finish after NTC)
+event:0X0F71 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP247 : (Group 247 pm_mrk_misc4) Number of PowerPC Instructions that completed.
+event:0X0F72 counters:2 um:zero minimum:1000 name:PM_MRK_VSU_FIN_GRP247 : (Group 247 pm_mrk_misc4) vsu (fpu) marked instr finish
+event:0X0F73 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_IC_MISS_GRP247 : (Group 247 pm_mrk_misc4) A group containing a marked (sampled) instruction experienced an instruction cache miss.
+event:0X0F74 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP247 : (Group 247 pm_mrk_misc4) Number of run instructions completed.
+event:0X0F75 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP247 : (Group 247 pm_mrk_misc4) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 248 pm_mrk_misc5, Marked misc events
+event:0X0F80 counters:0 um:zero minimum:1000 name:PM_MRK_FIN_STALL_CYC_COUNT_GRP248 : (Group 248 pm_mrk_misc5) Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #)
+event:0X0F81 counters:1 um:zero minimum:1000 name:PM_MRK_DFU_FIN_GRP248 : (Group 248 pm_mrk_misc5) The Decimal Floating Point Unit finished a marked instruction.
+event:0X0F82 counters:2 um:zero minimum:1000 name:PM_MRK_STALL_CMPLU_CYC_COUNT_GRP248 : (Group 248 pm_mrk_misc5) Marked Group Completion Stall cycles (use edge detect to count #)
+event:0X0F83 counters:3 um:zero minimum:10000 name:PM_INST_CMPL_GRP248 : (Group 248 pm_mrk_misc5) Number of PowerPC Instructions that completed.
+event:0X0F84 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP248 : (Group 248 pm_mrk_misc5) Number of run instructions completed.
+event:0X0F85 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP248 : (Group 248 pm_mrk_misc5) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 249 pm_mrk_misc6, Marked misc events
+event:0X0F90 counters:0 um:zero minimum:1000 name:PM_GRP_MRK_CYC_GRP249 : (Group 249 pm_mrk_misc6) cycles IDU marked instruction before dispatch
+event:0X0F91 counters:1 um:zero minimum:10000 name:PM_RUN_CYC_GRP249 : (Group 249 pm_mrk_misc6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+event:0X0F92 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP249 : (Group 249 pm_mrk_misc6) Number of PowerPC Instructions that completed.
+event:0X0F93 counters:3 um:zero minimum:1000 name:PM_MRK_GRP_CMPL_GRP249 : (Group 249 pm_mrk_misc6) A group containing a sampled instruction completed. Microcoded instructions that span multiple groups will generate this event once per group.
+event:0X0F94 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP249 : (Group 249 pm_mrk_misc6) Number of run instructions completed.
+event:0X0F95 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP249 : (Group 249 pm_mrk_misc6) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 250 pm_mrk_misc7, Marked misc events
+event:0X0FA0 counters:0 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_LHS_GRP250 : (Group 250 pm_mrk_misc7) The Load Store Unit rejected a marked load instruction that had an address overlap with an older store in the store queue. The store must be committed and de-allocated from the Store Queue before the load can execute successfully
+event:0X0FA1 counters:1 um:zero minimum:10000 name:PM_INST_CMPL_GRP250 : (Group 250 pm_mrk_misc7) Number of PowerPC Instructions that completed.
+event:0X0FA2 counters:2 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_ERAT_MISS_GRP250 : (Group 250 pm_mrk_misc7) LSU marked reject due to ERAT (up to 2 per cycle)
+event:0X0FA3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_REJECT_GRP250 : (Group 250 pm_mrk_misc7) LSU marked reject (up to 2 per cycle)
+event:0X0FA4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP250 : (Group 250 pm_mrk_misc7) Number of run instructions completed.
+event:0X0FA5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP250 : (Group 250 pm_mrk_misc7) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
+
+#Group 251 pm_mrk_misc8, Marked misc events
+event:0X0FB0 counters:0 um:zero minimum:10000 name:PM_CYC_GRP251 : (Group 251 pm_mrk_misc8) Processor Cycles
+event:0X0FB1 counters:1 um:zero minimum:10000 name:PM_CYC_GRP251 : (Group 251 pm_mrk_misc8) Processor Cycles
+event:0X0FB2 counters:2 um:zero minimum:10000 name:PM_INST_CMPL_GRP251 : (Group 251 pm_mrk_misc8) Number of PowerPC Instructions that completed.
+event:0X0FB3 counters:3 um:zero minimum:1000 name:PM_MRK_LSU_FIN_GRP251 : (Group 251 pm_mrk_misc8) One of the Load/Store Units finished a marked instruction. Instructions that finish may not necessary complete
+event:0X0FB4 counters:4 um:zero minimum:1000 name:PM_RUN_INST_CMPL_GRP251 : (Group 251 pm_mrk_misc8) Number of run instructions completed.
+event:0X0FB5 counters:5 um:zero minimum:10000 name:PM_RUN_CYC_GRP251 : (Group 251 pm_mrk_misc8) Processor Cycles gated by the run latch. Operating systems use the run latch to indicate when they are doing useful work. The run latch is typically cleared in the OS idle loop. Gating by the run latch filters out the idle loop.
diff --git a/events/ppc64/power7/unit_masks b/events/ppc64/power7/unit_masks
new file mode 100644
index 0000000..ab55afa
--- /dev/null
+++ b/events/ppc64/power7/unit_masks
@@ -0,0 +1,9 @@
+#
+# Copyright OProfile authors
+# Copyright (c) International Business Machines, 2009.
+# Contributed by Maynard Johnson <maynardj@us.ibm.com>.
+#
+# ppc64 POWER7 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/rtc/events b/events/rtc/events
new file mode 100644
index 0000000..cce44b0
--- /dev/null
+++ b/events/rtc/events
@@ -0,0 +1,3 @@
+# RTC events
+#
+name:RTC_INTERRUPTS event:0xff counters:0 um:zero minimum:2 : RTC interrupts/sec (rounded up to power of two)
diff --git a/events/rtc/unit_masks b/events/rtc/unit_masks
new file mode 100644
index 0000000..6984b62
--- /dev/null
+++ b/events/rtc/unit_masks
@@ -0,0 +1,4 @@
+# RTC possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/x86-64/family10/events b/events/x86-64/family10/events
new file mode 100644
index 0000000..753464d
--- /dev/null
+++ b/events/x86-64/family10/events
@@ -0,0 +1,241 @@
+# AMD Family 10 processor performance events
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2008 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+#
+# Sources: BIOS and Kernel Developer's Guide for AMD Family 10h Processors,
+# Publication# 31116, Revision 3.28, May 28, 2009
+#
+# Software Optimization Guide for AMD Family 10h Processors,
+# Publication# 40546, Revision 3.04, September 2007
+#
+# Revision: 1.3
+#
+# ChangeLog:
+# 1.3: 22 October 2009.
+# - Update from BKDG Rev 3.28 to Rev 3.34 (no change)
+# - Specify that event 4EDh is for Rev D only
+#
+# 1.2: 03 June 2009.
+# - Update from BKDG Rev 3.20 to Rev 3.28
+# - Add Event 4EDh
+# - Modify unitmasks for 4E0h-4E3h
+#
+# 1.1: 06 April 2009.
+# - Add IBS-derived events
+# - Update from BKDG Rev 3.00 to Rev 3.20
+# - Add Events 165h, 1c0h, 1cfh, 1d3h-1d5h
+#
+# Floating point events
+event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
+event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_FPU_EMPTY : The number of cycles in which the PFU is empty
+event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : The number of FPU operations that use the fast flag interface
+event:0x03 counters:0,1,2,3 um:sse_ops minimum:500 name:RETIRED_SSE_OPS : The number of SSE ops or uops retired
+event:0x04 counters:0,1,2,3 um:move_ops minimum:500 name:RETIRED_MOVE_OPS : The number of move uops retired
+event:0x05 counters:0,1,2,3 um:serial_ops minimum:500 name:RETIRED_SERIALIZING_OPS : The number of serializing uops retired.
+event:0x06 counters:0,1,2,3 um:serial_ops_sched minimum:500 name:SERIAL_UOPS_IN_FP_SCHED : Number of cycles a serializing uop is in the FP scheduler
+
+# Load, Store, and TLB events
+event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 Full
+event:0x24 counters:0,1,2,3 um:lock_ops minimum:500 name:LOCKED_OPS : Locked operations
+event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH instructions
+event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID_INSTRUCTIONS : Retired CPUID instructions
+event:0x2a counters:0,1,2,3 um:store_to_load minimum:500 name:CANCELLED_STORE_TO_LOAD : Counts the number of cancelled store to load forward operations
+event:0x2b counters:0,1,2,3 um:zero minimum:500 name:SMIS_RECEIVED : Counts the number of SMIs received by the processor
+
+# Data Cache event
+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
+# Note: unit mask 0x01 counts same events as event select 0x43
+event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE : Data cache refills from L2 or Northbridge
+event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_NORTHBRIDGE : Data cache refills from Northbridge
+event:0x44 counters:0,1,2,3 um:moesi_gh minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
+event:0x45 counters:0,1,2,3 um:l1_dtlb_miss_l2_hit minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB miss and L2 DTLB hit
+event:0x46 counters:0,1,2,3 um:l1_l2_dtlb_miss minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 DTLB and L2 DTLB miss
+event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesses
+event:0x48 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_LATE_CANCEL_ACCESS : Microarchitectural late cancel of an access
+event:0x49 counters:0,1,2,3 um:zero minimum:500 name:MICRO_ARCH_EARLY_CANCEL_ACCESS : Microarchitectural early cancel of an access
+event:0x4a counters:0,1,2,3 um:ecc minimum:500 name:1_BIT_ECC_ERRORS : Single-bit ECC errors recorded by scrubber
+event:0x4b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : The number of prefetch instructions dispatched by the decoder
+event:0x4c counters:0,1,2,3 um:locked_instruction_dcache_miss minimum:500 name:LOCKED_INSTRUCTIONS_DCACHE_MISSES : The number of dta cache misses by locked instructions.
+event:0x4d counters:0,1,2,3 um:l1_dtlb_hit minimum:500 name:L1_DTLB_HIT : L1 DTLB hit
+event:0x52 counters:0,1,2,3 um:soft_prefetch minimum:500 name:INEFFECTIVE_SW_PREFETCHES : Number of software prefetches that did not fetch data outside of processor core
+event:0x54 counters:0,1,2,3 um:zero minimum:500 name:GLOBAL_TLB_FLUSHES : The number of global TLB flushes
+
+# L2 Cache and System Interface events
+event:0x65 counters:0,1,2,3 um:memreqtype minimum:500 name:MEMORY_REQUESTS : Memory requests by type
+event:0x67 counters:0,1,2,3 um:dataprefetch minimum:500 name:DATA_PREFETCHES : Data prefetcher
+event:0x6c counters:0,1,2,3 um:systemreadresponse minimum:500 name:NORTHBRIDGE_READ_RESPONSES : Northbridge read responses by coherency state
+event:0x6d counters:0,1,2,3 um:octword_transfer minimum:500 name:OCTWORD_WRITE_TRANSFERS : Octwords written to system
+event:0x76 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+event:0x7d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 Cache
+event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
+event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback
+event:0x165 counters:0,1,2,3 um:page_size_mismatches minimum:500 name:PAGE_SIZE_MISMATCHES : Page Size Mismatches
+
+# Instruction Cache events
+event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches (RevE)
+event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
+event:0x82 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_L2 : Instruction cache refills from L2
+event:0x83 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM : Instruction cache refills from system
+event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
+event:0x85 counters:0,1,2,3 um:l1_l2_itlb_miss minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
+event:0x86 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE : Pipeline restart due to instruction stream probe
+event:0x87 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction fetch stall
+event:0x88 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_HITS : Return stack hit
+event:0x89 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_OVERFLOWS : Return stack overflow
+event:0x8b counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_VICTIMS : Number of instruction cache lines evicticed to the L2 cache
+event:0x8c counters:0,1,2,3 um:icache_invalidated minimum:500 name:INSTRUCTION_CACHE_INVALIDATED : Instruction cache lines invalidated
+event:0x99 counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS : The number of ITLB reloads requests
+event:0x9a counters:0,1,2,3 um:zero minimum:500 name:ITLB_RELOADS_ABORTED : The number of ITLB reloads aborted
+
+# Execution Unit events
+event:0xc0 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
+event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
+event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
+event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired mispredicted branch instructions
+event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired taken branch instructions
+event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired taken branches mispredicted
+event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers
+event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired branches resyncs (only non-control transfer branches)
+event:0xc8 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS : Retired near returns
+event:0xc9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired near returns mispredicted
+event:0xca counters:0,1,2,3 um:zero minimum:500 name:RETIRED_INDIRECT_BRANCHES_MISPREDICTED : Retired indirect branches mispredicted
+event:0xcb counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_MMX_FP_INSTRUCTIONS : Retired MMX/FP instructions
+event:0xcc counters:0,1,2,3 um:fpu_fastpath minimum:500 name:RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS : Retired FastPath double-op instructions
+event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
+event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
+event:0xcf counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts
+event:0xd0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Nothing to dispatch (decoder empty)
+event:0xd1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch stalls
+event:0xd2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_BRANCH_ABORT : Dispatch stall from branch abort to retire
+event:0xd3 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SERIALIZATION : Dispatch stall for serialization
+event:0xd4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SEGMENT_LOAD : Dispatch stall for segment load
+event:0xd5 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_REORDER_BUFFER_FULL : Dispatch stall for reorder buffer full
+event:0xd6 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_RESERVATION_STATION_FULL : Dispatch stall when reservation stations are full
+event:0xd7 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FPU_FULL : Dispatch stall when FPU is full
+event:0xd8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_LS_FULL : Dispatch stall when LS is full
+event:0xd9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_WAITING_FOR_ALL_QUIET : Dispatch stall when waiting for all to be quiet
+event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch Stall for Far Transfer or Resync to Retire
+event:0xdb counters:0,1,2,3 um:fpu_exceptions minimum:500 name:FPU_EXCEPTIONS : FPU exceptions
+event:0xdc counters:0,1,2,3 um:zero minimum:500 name:DR0_BREAKPOINTS : The number of matches on the address in breakpoint register DR0
+event:0xdd counters:0,1,2,3 um:zero minimum:500 name:DR1_BREAKPOINTS : The number of matches on the address in breakpoint register DR1
+event:0xde counters:0,1,2,3 um:zero minimum:500 name:DR2_BREAKPOINTS : The number of matches on the address in breakpoint register DR2
+event:0xdf counters:0,1,2,3 um:zero minimum:500 name:DR3_BREAKPOINTS : The number of matches on the address in breakpoint register DR3
+event:0x1c0 counters:0,1,2,3 um:retired_x87_fp minimum:500 name:RETIRED_X87_FLOATING_POINT_OPERATIONS : Retired x87 Floating Point Operations (RevC and later)
+event:0x1cf counters:0,1,2,3 um:zero minimum:50000 name:IBS_OPS_TAGGED : IBS Ops Tagged (RevC and later)
+event:0x1d3 counters:0,1,2,3 um:zero minimum:500 name:LFENCE_INSTRUCTIONS_RETIRED : LFENCE Instructions Retired (RevC and later)
+event:0x1d4 counters:0,1,2,3 um:zero minimum:500 name:SFENCE_INSTRUCTIONS_RETIRED : SFENCE Instructions Retired (RevC and later)
+event:0x1d5 counters:0,1,2,3 um:zero minimum:500 name:MFENCE_INSTRUCTIONS_RETIRED : MFENCE Instructions Retired (RevC and later)
+
+# Memory Controler events
+event:0xe0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM accesses
+event:0xe1 counters:0,1,2,3 um:mem_page_overflow minimum:500 name:MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS : Memory controller page table overflows
+event:0xe2 counters:0,1,2,3 um:slot_missed minimum:500 name:MEMORY_CONTROLLER_SLOT_MISSED : Memory controller DRAM command slots missed
+event:0xe3 counters:0,1,2,3 um:turnaround minimum:500 name:MEMORY_CONTROLLER_TURNAROUNDS : Memory controller turnarounds
+event:0xe4 counters:0,1,2,3 um:saturation minimum:500 name:MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION : Memory controller bypass saturation
+event:0xe8 counters:0,1,2,3 um:thermal_status minimum:500 name:THERMAL_STATUS : Thermal status
+event:0xe9 counters:0,1,2,3 um:cpiorequests minimum:500 name:CPU_IO_REQUESTS_TO_MEMORY_IO : CPU/IO Requests to Memory/IO
+event:0xea counters:0,1,2,3 um:cacheblock minimum:500 name:CACHE_BLOCK_COMMANDS : Cache block commands
+event:0xeb counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized commands
+event:0xec counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESPONSES_AND_UPSTREAM_REQUESTS : Probe responses and upstream requests
+event:0xee counters:0,1,2,3 um:gart minimum:500 name:GART_EVENTS : GART events
+event:0x1f0 counters:0,1,2,3 um:mem_control_request minimum:500 name:MEMORY_CONTROLLER_REQUESTS : Sized read/write activity.
+
+# Crossbar events
+event:0x1e0 counters:0,1,2,3 um:cpu_dram_req minimum:500 name:CPU_DRAM_REQUEST_TO_NODE : CPU to DRAM requests to target node
+event:0x1e1 counters:0,1,2,3 um:io_dram_req minimum:500 name:IO_DRAM_REQUEST_TO_NODE : IO to DRAM requests to target node
+event:0x1e2 counters:0,1,2,3 um:cpu_read_lat_0_3 minimum:500 name:CPU_READ_COMMAND_LATENCY_NODE_0_3 : Latency between the local node and remote node
+event:0x1e3 counters:0,1,2,3 um:cpu_read_lat_0_3 minimum:500 name:CPU_READ_COMMAND_REQUEST_NODE_0_3 : Number of requests that a latency measurement is made for Event 0x1E2
+event:0x1e4 counters:0,1,2,3 um:cpu_read_lat_4_7 minimum:500 name:CPU_READ_COMMAND_LATENCY_NODE_4_7 : Latency between the local node and remote node
+event:0x1e5 counters:0,1,2,3 um:cpu_read_lat_4_7 minimum:500 name:CPU_READ_COMMAND_REQUEST_NODE_4_7 : Number of requests that a latency measurement is made for Event 0x1E2
+event:0x1e6 counters:0,1,2,3 um:cpu_comm_lat minimum:500 name:CPU_COMMAND_LATENCY_TARGET : Determine latency between the local node and a remote node.
+event:0x1e7 counters:0,1,2,3 um:cpu_comm_lat minimum:500 name:CPU_REQUEST_TARGET : Number of requests that a latency measurement is made for Event 0x1E6
+
+# Link events
+event:0xf6 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
+event:0xf7 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 1 transmit bandwidth
+event:0xf8 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 2 transmit bandwidth
+event:0x1f9 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 3 transmit bandwidth
+
+# L3 Cache events
+event:0x4e0 counters:0,1,2,3 um:l3_cache minimum:500 name:READ_REQUEST_L3_CACHE : Number of read requests from each core to L3 cache
+event:0x4e1 counters:0,1,2,3 um:l3_cache minimum:500 name:L3_CACHE_MISSES : Number of L3 cache misses from each core
+event:0x4e2 counters:0,1,2,3 um:l3_fill minimum:500 name:L3_FILLS_CAUSED_BY_L2_EVICTIONS : Number of L3 fills caused by L2 evictions per core
+event:0x4e3 counters:0,1,2,3 um:l3_evict minimum:500 name:L3_EVICTIONS : Number of L3 cache line evictions by cache state
+event:0x4ed counters:0,1,2,3 um:non_cancelled_l3_read_requests minimum:500 name:NON_CANCELLED_L3_READ_REQUESTS : Non-cancelled L3 Read Requests (Rev D)
+
+###############################
+# IBS FETCH EVENTS
+###############################
+event:0xf000 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ALL : All IBS fetch samples
+event:0xf001 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_KILLED : IBS fetch killed
+event:0xf002 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ATTEMPTED : IBS fetch attempted
+event:0xf003 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_COMPLETED : IBS fetch completed
+event:0xf004 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ABORTED : IBS fetch aborted
+event:0xf005 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ITLB_HITS : IBS ITLB hit
+event:0xf006 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_HITS : IBS L1 ITLB misses (and L2 ITLB hits)
+event:0xf007 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_L1_ITLB_MISSES_L2_ITLB_MISSES : IBS L1 L2 ITLB miss
+event:0xf008 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ICACHE_MISSES : IBS Instruction cache misses
+event:0xf009 ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_ICACHE_HITS : IBS Instruction cache hit
+event:0xf00A ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_4K_PAGE : IBS 4K page translation
+event:0xf00B ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_2M_PAGE : IBS 2M page translation
+#
+event:0xf00E ext:ibs_fetch um:zero minimum:50000 name:IBS_FETCH_LATENCY : IBS fetch latency
+
+###############################
+# IBS OP EVENTS
+###############################
+event:0xf100 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_ALL : All IBS op samples
+event:0xf101 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_TAG_TO_RETIRE : IBS tag-to-retire cycles
+event:0xf102 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_COMP_TO_RET : IBS completion-to-retire cycles
+event:0xf103 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_BRANCH_RETIRED : IBS branch op
+event:0xf104 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MISPREDICTED_BRANCH : IBS mispredicted branch op
+event:0xf105 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_TAKEN_BRANCH : IBS taken branch op
+event:0xf106 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MISPREDICTED_BRANCH_TAKEN : IBS mispredicted taken branch op
+event:0xf107 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_RETURNS : IBS return op
+event:0xf108 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MISPREDICTED_RETURNS : IBS mispredicted return op
+event:0xf109 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_RESYNC : IBS resync op
+event:0xf200 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_ALL_LOAD_STORE : IBS all load store ops
+event:0xf201 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_LOAD : IBS load ops
+event:0xf202 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_STORE : IBS store ops
+event:0xf203 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_HITS : IBS L1 DTLB hit
+event:0xf204 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_MISS_L2_DTLB_HIT : IBS L1 DTLB misses L2 hits
+event:0xf205 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_L2_DTLB_MISS : IBS L1 and L2 DTLB misses
+event:0xf206 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DATA_CACHE_MISS : IBS data cache misses
+event:0xf207 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DATA_HITS : IBS data cache hits
+event:0xf208 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MISALIGNED_DATA_ACC : IBS misaligned data access
+event:0xf209 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_BANK_CONF_LOAD : IBS bank conflict on load op
+event:0xf20A ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_BANK_CONF_STORE : IBS bank conflict on store op
+event:0xf20B ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_FORWARD : IBS store-to-load forwarded
+event:0xf20C ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_CANCELLED : IBS store-to-load cancelled
+event:0xf20D ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DCUC_MEM_ACC : IBS UC memory access
+event:0xf20E ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DCWC_MEM_ACC : IBS WC memory access
+event:0xf20F ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_LOCKED : IBS locked operation
+event:0xf210 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_MAB_HIT : IBS MAB hit
+event:0xf211 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_4K : IBS L1 DTLB 4K page
+event:0xf212 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_2M : IBS L1 DTLB 2M page
+event:0xf213 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L1_DTLB_1G : IBS L1 DTLB 1G page
+event:0xf215 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L2_DTLB_4K : IBS L2 DTLB 4K page
+event:0xf216 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L2_DTLB_2M : IBS L2 DTLB 2M page
+event:0xf217 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_L2_DTLB_1G : IBS L2 DTLB 1G page
+event:0xf219 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_DC_LOAD_LAT : IBS data cache miss load latency
+event:0xf240 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_ONLY : IBS northbridge local
+event:0xf241 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_ONLY : IBS northbridge remote
+event:0xf242 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_L3 : IBS northbridge local L3
+event:0xf243 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_CACHE : IBS northbridge local core L1 or L2 cache
+event:0xf244 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_CACHE : IBS northbridge local core L1, L2, L3 cache
+event:0xf245 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_DRAM : IBS northbridge local DRAM
+event:0xf246 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_DRAM : IBS northbridge remote DRAM
+event:0xf247 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_OTHER : IBS northbridge local APIC MMIO Config PCI
+event:0xf248 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_OTHER : IBS northbridge remote APIC MMIO Config PCI
+event:0xf249 ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_CACHE_MODIFIED : IBS northbridge cache modified state
+event:0xf24A ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_CACHE_OWNED : IBS northbridge cache owned state
+event:0xf24B ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_LOCAL_CACHE_LAT : IBS northbridge local cache latency
+event:0xf24C ext:ibs_op um:ibs_op minimum:50000 name:IBS_OP_NB_REMOTE_CACHE_LAT : IBS northbridge remote cache latency
diff --git a/events/x86-64/family10/unit_masks b/events/x86-64/family10/unit_masks
new file mode 100644
index 0000000..1eeef18
--- /dev/null
+++ b/events/x86-64/family10/unit_masks
@@ -0,0 +1,374 @@
+#
+# AMD Family 10 processor unit masks
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2008 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+#
+# Sources: BIOS and Kernel Developer's Guide for AMD Family 10h Processors,
+# Publication# 31116, Revision 3.34, September 2009
+#
+# Software Optimization Guide for AMD Family 10h Processors,
+# Publication# 40546, Revision 3.04, September 2007
+#
+# Revision: 1.3
+#
+# ChangeLog:
+# 1.3: 22 October 2009.
+# - Update from BKDG Rev 3.28 to Rev 3.34 (no change)
+# - Modify unitmasks l3_evict
+#
+# 1.2: 03 June 2009.
+# - Update from BKDG Rev 3.20 to Rev 3.28
+# - Add Event 4EDh
+# - Modify unitmasks for 4E0h-4E3h
+#
+# 1.1: 06 April 2009.
+# - Add IBS-derived events
+# - Update from BKDG Rev 3.00 to Rev 3.20
+# - Add Events 165h, 1c0h, 1cfh, 1d3h-1d5h
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:moesi type:bitmask default:0x1f
+ 0x01 (I)nvalid cache state
+ 0x02 (S)hared cache state
+ 0x04 (E)xclusive cache state
+ 0x08 (O)wner cache state
+ 0x10 (M)odified cache state
+ 0x1f All cache states
+name:moess type:bitmask default:0x1e
+ 0x01 Refill from northbridge
+ 0x02 Shared-state line from L2
+ 0x04 Exclusive-state line from L2
+ 0x08 Owner-state line from L2
+ 0x10 Modified-state line from L2
+ 0x1e All cache states except refill from northbridge
+name:fpu_ops type:bitmask default:0x3f
+ 0x01 Add pipe ops excluding load ops and SSE move ops
+ 0x02 Multiply pipe ops excluding load ops and SSE move ops
+ 0x04 Store pipe ops excluding load ops and SSE move ops
+ 0x08 Add pipe load ops and SSE move ops
+ 0x10 Multiply pipe load ops and SSE move ops
+ 0x20 Store pipe load ops and SSE move ops
+ 0x3f All ops
+name:segregload type:bitmask default:0x7f
+ 0x01 ES register
+ 0x02 CS register
+ 0x04 SS register
+ 0x08 DS register
+ 0x10 FS register
+ 0x20 GS register
+ 0x40 HS register
+name:fpu_instr type:bitmask default:0x07
+ 0x01 x87 instructions
+ 0x02 MMX & 3DNow instructions
+ 0x04 SSE instructions (SSE, SSE2, SSE3, and SSE4A)
+name:fpu_fastpath type:bitmask default:0x07
+ 0x01 With low op in position 0
+ 0x02 With low op in position 1
+ 0x04 With low op in position 2
+name:fpu_exceptions type:bitmask default:0x0f
+ 0x01 x87 reclass microfaults
+ 0x02 SSE retype microfaults
+ 0x04 SSE reclass microfaults
+ 0x08 SSE and x87 microtraps
+name:page_access type:bitmask default:0x3f
+ 0x01 DCT0 Page hit
+ 0x02 DCT0 Page miss
+ 0x04 DCT0 Page conflict
+ 0x08 DCT1 Page hit
+ 0x10 DCT1 Page miss
+ 0x20 DCT1 Page Conflict
+name:mem_page_overflow type:bitmask default:0x03
+ 0x01 DCT0 Page Table Overflow
+ 0x02 DCT1 Page Table Overflow
+name:turnaround type:bitmask default:0x3f
+ 0x01 DCT0 DIMM (chip select) turnaround
+ 0x02 DCT0 Read to write turnaround
+ 0x04 DCT0 Write to read turnaround
+ 0x08 DCT1 DIMM (chip select) turnaround
+ 0x10 DCT1 Read to write turnaround
+ 0x20 DCT1 Write to read turnaround
+name:saturation type:bitmask default:0x0f
+ 0x01 Memory controller high priority bypass
+ 0x02 Memory controller medium priority bypass
+ 0x04 DCT0 DCQ bypass
+ 0x08 DCT1 DCQ bypass
+name:slot_missed type:bitmask default:0x03
+ 0x01 DCT0 Command slots missed
+ 0x02 DCT2 Command slots missed
+name:sizecmds type:bitmask default:0x3f
+ 0x01 Non-posted write byte (1-32 bytes)
+ 0x02 Non-posted write DWORD (1-16 DWORDs)
+ 0x04 Posted write byte (1-32 bytes)
+ 0x08 Posted write DWORD (1-16 DWORDs)
+ 0x10 Read byte (4 bytes)
+ 0x20 Read DWORD (1-16 DWORDs)
+name:probe type:bitmask default:0xff
+ 0x01 Probe miss
+ 0x02 Probe hit clean
+ 0x04 Probe hit dirty without memory cancel
+ 0x08 Probe hit dirty with memory cancel
+ 0x10 Upstream display refresh/ISOC reads
+ 0x20 Upstream non-display refresh reads
+ 0x40 Upstream ISOC writes
+ 0x80 Upstream non-ISOC writes
+name:l2_internal type:bitmask default:0x3f
+ 0x01 IC fill
+ 0x02 DC fill
+ 0x04 TLB fill (page table walks)
+ 0x08 Tag snoop request
+ 0x10 Canceled request
+ 0x20 Hardware prefetch from data cache
+name:l2_req_miss type:bitmask default:0x0f
+ 0x01 IC fill
+ 0x02 DC fill (includes possible replays)
+ 0x04 TLB page table walk
+ 0x08 Hardware prefetch from data cache
+name:l2_fill type:bitmask default:0x03
+ 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
+ 0x02 L2 writebacks to system
+name:gart type:bitmask default:0xff
+ 0x01 GART aperture hit on access from CPU
+ 0x02 GART aperture hit on access from I/O
+ 0x04 GART miss
+ 0x08 GART/DEV request hit table walk in progress
+ 0x10 DEV hit
+ 0x20 DEV miss
+ 0x40 DEV error
+ 0x80 GART/DEV multiple table walk in progress
+name:cpiorequests type:bitmask default:0xa2
+ 0xa1 Requests Local I/O to Local I/O
+ 0xa2 Requests Local I/O to Local Memory
+ 0xa3 Requests Local I/O to Local (I/O or Mem)
+ 0xa4 Requests Local CPU to Local I/O
+ 0xa5 Requests Local (CPU or I/O) to Local I/O
+ 0xa8 Requests Local CPU to Local Memory
+ 0xaa Requests Local (CPU or I/O) to Local Memory
+ 0xac Requests Local CPU to Local (I/O or Mem)
+ 0xaf Requests Local (CPU or I/O) to Local (I/O or Mem)
+ 0x91 Requests Local I/O to Remote I/O
+ 0x92 Requests Local I/O to Remote Memory
+ 0x93 Requests Local I/O to Remote (I/O or Mem)
+ 0x94 Requests Local CPU to Remote I/O
+ 0x95 Requests Local (CPU or I/O) to Remote I/O
+ 0x98 Requests Local CPU to Remote Memory
+ 0x9a Requests Local (CPU or I/O) to Remote Memory
+ 0x9c Requests Local CPU to Remote (I/O or Mem)
+ 0x9f Requests Local (CPU or I/O) to Remote (I/O or Mem)
+ 0xb1 Requests Local I/O to Any I/O
+ 0xb2 Requests Local I/O to Any Memory
+ 0xb3 Requests Local I/O to Any (I/O or Mem)
+ 0xb4 Requests Local CPU to Any I/O
+ 0xb5 Requests Local (CPU or I/O) to Any I/O
+ 0xb8 Requests Local CPU to Any Memory
+ 0xba Requests Local (CPU or I/O) to Any Memory
+ 0xbc Requests Local CPU to Any (I/O or Mem)
+ 0xbf Requests Local (CPU or I/O) to Any (I/O or Mem)
+ 0x61 Requests Remote I/O to Local I/O
+ 0x64 Requests Remote CPU to Local I/O
+ 0x65 Requests Remote (CPU or I/O) to Local I/O
+name:cacheblock type:bitmask default:0x3d
+ 0x01 Victim Block (Writeback)
+ 0x04 Read Block (Dcache load miss refill)
+ 0x08 Read Block Shared (Icache refill)
+ 0x10 Read Block Modified (Dcache store miss refill)
+ 0x20 Change-to-Dirty (first store to clean block already in cache)
+name:dataprefetch type:bitmask default:0x03
+ 0x01 Cancelled prefetches
+ 0x02 Prefetch attempts
+name:memreqtype type:bitmask default:0x83
+ 0x01 Requests to non-cacheable (UC) memory
+ 0x02 Requests to write-combining (WC) memory or WC buffer flushes to WB memory
+ 0x80 Streaming store (SS) requests
+name:systemreadresponse type:bitmask default:0x1f
+ 0x01 Exclusive
+ 0x02 Modified
+ 0x04 Shared
+ 0x08 Owned
+ 0x10 Data Error
+name:l1_dtlb_miss_l2_hit type:bitmask default:0x07
+ 0x01 L2 4K TLB hit
+ 0x02 L2 2M TLB hit
+ 0x04 L2 1G TLB hit (RevC)
+name:l1_l2_dtlb_miss type:bitmask default:0x07
+ 0x01 4K TLB reload
+ 0x02 2M TLB reload
+ 0x04 1G TLB reload
+name:ecc type:bitmask default:0x0f
+ 0x01 Scrubber error
+ 0x02 Piggyback scrubber errors
+ 0x04 Load pipe error
+ 0x08 Store write pip error
+name:prefetch type:bitmask default:0x07
+ 0x01 Load (Prefetch, PrefetchT0/T1/T2)
+ 0x02 Store (PrefetchW)
+ 0x04 NTA (PrefetchNTA)
+name:locked_instruction_dcache_miss type:bitmask default:0x02
+ 0x02 Data cache misses by locked instructions
+name:octword_transfer type:bitmask default:0x01
+ 0x01 Octword write transfer
+name:thermal_status type:bitmask default:0x7c
+ 0x04 Number of times the HTC trip point is crossed
+ 0x08 Number of clocks when STC trip point active
+ 0x10 Number of times the STC trip point is crossed
+ 0x20 Number of clocks HTC P-state is inactive
+ 0x40 Number of clocks HTC P-state is active
+name:mem_control_request type:bitmask default:0x78
+ 0x01 Write requests
+ 0x02 Read Requests including Prefetch
+ 0x04 Prefetch Request
+ 0x08 32 Bytes Sized Writes
+ 0x10 64 Bytes Sized Writes
+ 0x20 32 Bytes Sized Reads
+ 0x40 64 Byte Sized Reads
+ 0x80 Read requests sent to the DCT while write requests are pending in the DCQ
+name:httransmit type:bitmask default:0xbf
+ 0x01 Command DWORD sent
+ 0x02 Data DWORD sent
+ 0x04 Buffer release DWORD sent
+ 0x08 Nop DW sent (idle)
+ 0x10 Address DWORD sent
+ 0x20 Per packet CRC sent
+ 0x80 SubLink Mask
+name:lock_ops type:bitmask default:0x0f
+ 0x01 Number of locked instructions executed
+ 0x02 Cycles in speculative phase
+ 0x04 Cycles in non-speculative phase (including cache miss penalty)
+ 0x08 Cache miss penalty in cycles
+name:sse_ops type:bitmask default:0x7f
+ 0x01 Single Precision add/subtract ops
+ 0x02 Single precision multiply ops
+ 0x04 Single precision divide/square root ops
+ 0x08 Double precision add/subtract ops
+ 0x10 Double precision multiply ops
+ 0x20 Double precision divide/square root ops
+ 0x40 OP type: 0=uops 1=FLOPS
+name:move_ops type:bitmask default:0x0f
+ 0x01 Merging low quadword move uops
+ 0x02 Merging high quadword move uops
+ 0x04 All other merging move uops
+ 0x08 All other move uops
+name:serial_ops type:bitmask default:0x0f
+ 0x01 SSE bottom-executing uops retired
+ 0x02 SSE bottom-serializing uops retired
+ 0x04 x87 bottom-executing uops retired
+ 0x08 x87 bottom-serializing uops retired
+name:serial_ops_sched type:bitmask default:0x03
+ 0x01 Number of cycles a bottom-execute uops in FP scheduler
+ 0x02 Number of cycles a bottom-serializing uops in FP scheduler
+name:store_to_load type:bitmask default:0x07
+ 0x01 Address mismatches (starting byte not the same)
+ 0x02 Store is smaller than load
+ 0x04 Misaligned
+name:moesi_gh type:bitmask default:0x1f
+ 0x01 (I)nvalid cache state
+ 0x02 (S)hared cache state
+ 0x04 (E)xclusive cache state
+ 0x08 (O)wner cache state
+ 0x10 (M)odified cache state
+ 0x20 Cache line evicted brought into the cache by PrefetchNTA
+ 0x40 Cache line evicted not brought into the cache by PrefetchNTA
+name:l1_dtlb_hit type:bitmask default:0x07
+ 0x01 L1 4K TLB hit
+ 0x02 L1 2M TLB hit
+ 0x04 L1 1G TLB hit
+name:soft_prefetch type:bitmask default:0x09
+ 0x01 Software prefetch hit in L1
+ 0x08 Software prefetch hit in L2
+name:l1_l2_itlb_miss type:bitmask default:0x03
+ 0x01 Instruction fetches to a 4K page
+ 0x02 Instruction fetches to a 2M page
+name:cpu_dram_req type:bitmask default:0xff
+ 0x01 From local node to node 0
+ 0x02 From local node to node 1
+ 0x04 From local node to node 2
+ 0x08 From local node to node 3
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:io_dram_req type:bitmask default:0xff
+ 0x01 From local node to node 0
+ 0x02 From local node to node 1
+ 0x04 From local node to node 2
+ 0x08 From local node to node 3
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:cpu_read_lat_0_3 type:bitmask default:0xff
+ 0x01 Read block
+ 0x02 Read block shared
+ 0x04 Read block modified
+ 0x08 Change-to-Dirty
+ 0x10 From local node to node 0
+ 0x20 From local node to node 1
+ 0x40 From local node to node 2
+ 0x80 From local node to node 3
+name:cpu_read_lat_4_7 type:bitmask default:0xff
+ 0x01 Read block
+ 0x02 Read block shared
+ 0x04 Read block modified
+ 0x08 Change-to-Dirty
+ 0x10 From local node to node 4
+ 0x20 From local node to node 5
+ 0x40 From local node to node 6
+ 0x80 From local node to node 7
+name:cpu_comm_lat type:bitmask default:0xf7
+ 0x01 Read sized
+ 0x02 Write sized
+ 0x04 Victim block
+ 0x08 Node group select: 0=Nodes 0-3, 1=Nodes 4-7
+ 0x10 From local node to node 0/4
+ 0x20 From local node to node 1/5
+ 0x40 From local node to node 2/6
+ 0x80 From local node to node 3/7
+name:l3_cache type:bitmask default:0xf7
+ 0x01 Read block Exclusive (Data cache read)
+ 0x02 Read block Shared (Instruciton cache read)
+ 0x04 Read block Modify
+ 0x10 Reserved (Must be selected)
+ 0x20 Reserved (Must be selected)
+ 0x40 Reserved (Must be selected)
+ 0x80 Reserved (Must be selected)
+name:l3_fill type:bitmask default:0xff
+ 0x01 Shared
+ 0x02 Exclusive
+ 0x04 Owned
+ 0x08 Modified
+ 0x10 Reserved (Must be selected)
+ 0x20 Reserved (Must be selected)
+ 0x40 Reserved (Must be selected)
+ 0x80 Reserved (Must be selected)
+name:l3_evict type:bitmask default:0x0f
+ 0x01 Shared
+ 0x02 Exclusive
+ 0x04 Owned
+ 0x08 Modified
+name:icache_invalidated type:bitmask default:0x03
+ 0x01 Invalidating probe that did not hit any in-flight instructions
+ 0x02 Invalidating probe that hit one or more in-flight instructions
+name:page_size_mismatches type:bitmask default:0x07
+ 0x01 Guest page size is larger than the host page size
+ 0x02 MTRR mismatch
+ 0x04 Host page size is larger than the guest page size
+name:retired_x87_fp type:bitmask default:0x07
+ 0x01 Add/subtract ops
+ 0x02 Multiply ops
+ 0x04 Divide ops
+name:ibs_op type:bitmask default:0x01
+ 0x00 Using IBS OP cycle count mode
+ 0x01 Using IBS OP dispatch count mode
+ 0x02 Enable IBS OP Memory Access Log
+name:non_cancelled_l3_read_requests type:bitmask default:0xf7
+ 0x01 RbBlk
+ 0x02 RbBlkS
+ 0x04 RbBlkM
+ 0x10 Reserved (Must be selected)
+ 0x20 Reserved (Must be selected)
+ 0x40 Reserved (Must be selected)
+ 0x80 Reserved (Must be selected)
diff --git a/events/x86-64/family11h/events b/events/x86-64/family11h/events
new file mode 100644
index 0000000..98d1dad
--- /dev/null
+++ b/events/x86-64/family11h/events
@@ -0,0 +1,132 @@
+#
+# AMD Athlon(tm)64 and AMD Opteron(tm) processor performance events
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2008 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+# Paul Drongowski <paul.drongowski at amd.com>
+#
+# Source : BIOS and Kernel Developer's Guide for AMD Family 11h Processors,
+# Publication# 41256, Revision 3.00, July 07, 2008
+#
+# Updated on 11 November 2008:
+# Description : Prepare for Oprofile patch submission
+# Signed off : Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+#
+# Updated on 20 February 2008:
+# Description : Added events for AMD Family 11h processors and proofread
+# WRT the latest BKDG
+#
+
+# Floating point events
+event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
+event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles in which the FPU is empty
+event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
+
+# Load, Store, and TLB events
+event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
+event:0x24 counters:0,1,2,3 um:locked_ops minimum:500 name:LOCKED_OPS : Locked operations
+
+# Execution Unit Events
+
+# Data Cache event
+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
+# Event 0x42 with unit mask 0x01 counts same events as event select 0x43
+event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM : Data cache refills from L2 or system
+event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_SYSTEM : Data cache refills from system
+event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
+event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
+event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
+event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesses
+event:0x48 counters:0,1,2,3 um:zero minimum:500 name:MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS : Micro-architectural late cancel of an access
+event:0x49 counters:0,1,2,3 um:zero minimum:500 name:MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS : Micro-architectural early cancel of an access
+event:0x4a counters:0,1,2,3 um:ecc minimum:500 name:SCRUBBER_SINGLE_BIT_ECC_ERRORS : One bit ECC error recorded by scrubber
+event:0x4b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : Prefetch instructions dispatched
+event:0x4c counters:0,1,2,3 um:dcachemisslocked minimum:500 name:DCACHE_MISS_LOCKED_INSTRUCTIONS : DCACHE misses by locked instructions
+
+# L2 Cache and System Interface events
+event:0x65 counters:0,1,2,3 um:memreqtype minimum:500 name:MEMORY_REQUESTS : Memory requests by type
+event:0x67 counters:0,1,2,3 um:dataprefetch minimum:500 name:DATA_PREFETCHES : Data prefetcher
+event:0x6c counters:0,1,2,3 um:systemreadresponse minimum:500 name:SYSTEM_READ_RESPONSES : System read responses by coherency state
+event:0x6d counters:0,1,2,3 um:writtentosystem minimum:500 name:QUADWORD_WRITE_TRANSFERS : Quadwords written to system
+
+event:0x7d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 cache
+event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
+event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback
+
+# Instruction Cache events
+event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches
+event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
+event:0x82 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_L2 : Instruction cache refills from L2
+event:0x83 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM : Instruction cache refills from system
+event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
+event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
+event:0x86 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE : Pipeline restart due to instruction stream probe
+event:0x87 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction fetch stall
+event:0x88 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_HITS : Return stack hits
+event:0x89 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_OVERFLOWS : Return stack overflows
+
+
+event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CFLUSH : Retired CLFLUSH instructions
+event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID : Retired CPUID instructions
+event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+
+# Execution Unit events
+event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
+event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
+event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
+event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired mispredicted branch instructions
+event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired taken branch instructions
+event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired taken branches mispredicted
+event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers
+event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired branches resyncs (only non-control transfer branches)
+event:0xc8 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS : Retired near returns
+event:0xc9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired near returns mispredicted
+event:0xca counters:0,1,2,3 um:zero minimum:500 name:RETIRED_INDIRECT_BRANCHES_MISPREDICTED : Retired indirect branches mispredicted
+event:0xcb counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_MMX_FP_INSTRUCTIONS : Retired MMX/FP instructions
+event:0xcc counters:0,1,2,3 um:fpu_fastpath minimum:500 name:RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS : Retired FastPath double-op instructions
+event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
+event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
+event:0xcf counters:0,1,2,3 um:zero minimum:10 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts
+event:0xd0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Nothing to dispatch (decoder empty)
+event:0xd1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch stalls
+event:0xd2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_BRANCH_ABORT : Dispatch stall from branch abort to retire
+event:0xd3 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SERIALIZATION : Dispatch stall for serialization
+event:0xd4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SEGMENT_LOAD : Dispatch stall for segment load
+event:0xd5 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_REORDER_BUFFER_FULL : Dispatch stall for reorder buffer full
+event:0xd6 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_RESERVATION_STATION_FULL : Dispatch stall when reservation stations are full
+event:0xd7 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FPU_FULL : Dispatch stall when FPU is full
+event:0xd8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_LS_FULL : Dispatch stall when LS is full
+event:0xd9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_WAITING_FOR_ALL_QUIET : Dispatch stall when waiting for all to be quiet
+event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch stall for far transfer or resync to retire
+event:0xdb counters:0,1,2,3 um:fpu_exceptions minimum:1 name:FPU_EXCEPTIONS : FPU exceptions
+event:0xdc counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : Number of breakpoints for DR0
+event:0xdd counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : Number of breakpoints for DR1
+event:0xde counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : Number of breakpoints for DR2
+event:0xdf counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : Number of breakpoints for DR3
+
+# Memory Controller events
+event:0xe0 counters:0,1,2,3 um:dramaccess minimum:500 name:DRAM_ACCESSES : DRAM accesses
+event:0xe1 counters:0,1,2,3 um:dramcontroller minimum:500 name:DRAM_CONTROLLER_PAGE_TABLE_EVENTS : DRAM Controller Page Table Events
+event:0xe3 counters:0,1,2,3 um:turnaround minimum:500 name:MEMORY_CONTROLLER_TURNAROUNDS : Memory controller turnarounds
+event:0xe4 counters:0,1,2,3 um:rbdqueue minimum:500 name:MEMORY_CONTROLLER_RBD_QUEUE_EVENTS : Memory controller RBD queue events
+event:0xe8 counters:0,1,2,3 um:thermalstatus minimum:500 name:THERMAL_STATUS : Thermal status
+event:0xe9 counters:0,1,2,3 um:cpiorequests minimum:500 name:CPU_IO_REQUESTS_TO_MEMORY_IO : CPU/IO requests to memory/IO
+event:0xea counters:0,1,2,3 um:cacheblock minimum:500 name:CACHE_BLOCK_COMMANDS : Cache block commands
+event:0xeb counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized commands
+event:0xec counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESPONSES_AND_UPSTREAM_REQUESTS : Probe responses and upstream requests
+event:0xee counters:0,1,2,3 um:devevents minimum:500 name:DEV_EVENTS : DEV events
+
+
+event:0x1f0 counters:0,1,2,3 um:memory_controller_requests minimum:500 name:MEMORY_CONTROLLER_REQUESTS : Memory controller requests
+event:0x1e9 counters:0,1,2,3 um:sideband_signals_and_special_cycles minimum:500 name:SIDEBAND_SIGNALS_AND_SPECIAL_CYCLES : Sideband Signals and Special Cycles
+event:0x1ea counters:0,1,2,3 um:interrupt_events minimum:500 name:INTERRUPT_EVENTS : Interrupt Events
+
+# Link events
+event:0xf6 counters:0,1,2,3 um:httransmit minimum:500 name:HYPERTRANSPORT_LINK_0_TRANSMIT_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
diff --git a/events/x86-64/family11h/unit_masks b/events/x86-64/family11h/unit_masks
new file mode 100644
index 0000000..91e5d4f
--- /dev/null
+++ b/events/x86-64/family11h/unit_masks
@@ -0,0 +1,220 @@
+#
+# AMD Athlon(tm)64 and AMD Opteron(tm) processor unit masks
+#
+# Copyright OProfile authors
+# Copyright (c) Advanced Micro Devices, 2006-2008
+# Contributed by Ray Bryant <raybry@amd.com>, and others.
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+# Paul Drongowski <paul.drongowski at amd.com>
+#
+# Source : BIOS and Kernel Developer's Guide for AMD Family 11h Processors,
+# Publication# 41256, Revision 3.00, July 07, 2008
+#
+# Updated on 11 November 2008:
+# Description : Prepare for Oprofile patch submission
+# Signed off : Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
+#
+# Updated on 20 February 2008:
+# Description : Added events for AMD Family 11h processors and proofread
+# WRT the latest BKDG
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:moesi type:bitmask default:0x1f
+ 0x01 (I)nvalid cache state
+ 0x02 (S)hared cache state
+ 0x04 (E)xclusive cache state
+ 0x08 (O)wned cache state
+ 0x10 (M)odified cache state
+ 0x1f All cache states
+name:moess type:bitmask default:0x1e
+ 0x01 refill from system
+ 0x02 (S)hared cache state from L2
+ 0x04 (E)xclusive cache state from L2
+ 0x08 (O)wned cache state from L2
+ 0x10 (M)odified cache state from L2
+ 0x1e All cache states except Invalid
+name:fpu_ops type:bitmask default:0x3f
+ 0x01 Add pipe ops
+ 0x02 Multiply pipe
+ 0x04 Store pipe ops
+ 0x08 Add pipe load ops
+ 0x10 Multiply pipe load ops
+ 0x20 Store pipe load ops
+name:segregload type:bitmask default:0x7f
+ 0x01 ES register
+ 0x02 CS register
+ 0x04 SS register
+ 0x08 DS register
+ 0x10 FS register
+ 0x20 GS register
+ 0x40 HS register
+name:ecc type:bitmask default:0x03
+ 0x01 Scrubber error
+ 0x02 Piggyback scrubber errors
+name:prefetch type:bitmask default:0x07
+ 0x01 Load
+ 0x02 Store
+ 0x04 NTA
+name:fpu_instr type:bitmask default:0x0f
+ 0x01 x87 instructions
+ 0x02 MMX & 3DNow instructions
+ 0x04 Packed SSE & SSE2 instructions
+ 0x08 Packed scalar SSE & SSE2 instructions
+name:fpu_fastpath type:bitmask default:0x07
+ 0x01 With low op in position 0
+ 0x02 With low op in position 1
+ 0x04 With low op in position 2
+name:fpu_exceptions type:bitmask default:0x0f
+ 0x01 x87 reclass microfaults
+ 0x02 SSE retype microfaults
+ 0x04 SSE reclass microfaults
+ 0x08 SSE and x87 microtraps
+name:dramaccess type:bitmask default:0xff
+ 0x01 DCT0 Page hit
+ 0x02 DCT0 Page miss
+ 0x04 DCT0 Page conflict
+ 0x08 DCT1 Page hit
+ 0x10 DCT1 Page miss
+ 0x20 DCT1 Page conflict
+ 0x40 Write request
+ 0x80 Read request
+name:dramcontroller type:bitmask default:0x0f
+ 0x01 DCT Page Table Overflow
+ 0x02 Number of stale table entry hits (hit on a page closed too soon)
+ 0x04 Page table idle cycle limit incremented
+ 0x08 Page table idle cycle limit decremented
+name:turnaround type:bitmask default:0x3f
+ 0x01 DCT0 Read to write turnaround
+ 0x02 DCT0 Write to read turnaround
+ 0x04 DCT0 DIMM (chip select) turnaround
+ 0x08 DCT1 Read to write turnaround
+ 0x10 DCT1 Write to read turnaround
+ 0x20 DCT1 DIMM (chip select) turnaround
+name:rbdqueue type:bitmask default:0x04
+ 0x04 F2x[1,0]94[DcqBypassMax] counter reached
+name:sizecmds type:bitmask default:0x3f
+ 0x01 Non-posted write byte (1-32 bytes)
+ 0x02 Non-posted write DWORD (1-16 DWORDs)
+ 0x04 Posted write byte (1-32 bytes)
+ 0x08 Posted write DWORD (1-16 DWORDs)
+ 0x10 Read byte (4 bytes)
+ 0x20 Read DWORD (1-16 DWORDs)
+name:probe type:bitmask default:0x0f
+ 0x01 Probe miss
+ 0x02 Probe hit clean
+ 0x04 Probe hit dirty without memory cancel
+ 0x08 Probe hit dirty with memory cancel
+ 0x10 Upstream display refresh/ISOC reads
+ 0x20 Upstream non-display refresh reads
+ 0x40 Upstream ISOC writes
+ 0x80 Upstream non-ISOC writes
+name:l2_internal type:bitmask default:0x1f
+ 0x01 IC fill
+ 0x02 DC fill
+ 0x04 TLB fill (page table walk)
+ 0x08 Tag snoop request
+ 0x10 Cancelled request
+name:l2_req_miss type:bitmask default:0x07
+ 0x01 IC fill
+ 0x02 DC fill
+ 0x04 TLB page table walk
+name:l2_fill type:bitmask default:0x03
+ 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
+ 0x02 L2 writebacks to system
+name:devevents type:bitmask default:0x70
+ 0x10 DEV hit
+ 0x20 DEV miss
+ 0x40 DEV error
+name:cpiorequests type:bitmask default:0xa2
+ 0xa1 Requests Local I/O to Local I/O
+ 0xa2 Requests Local I/O to Local Memory
+ 0xa3 Requests Local I/O to Local (I/O or Mem)
+ 0xa4 Requests Local CPU to Local I/O
+ 0xa5 Requests Local (CPU or I/O) to Local I/O
+ 0xa8 Requests Local CPU to Local Memory
+ 0xaa Requests Local (CPU or I/O) to Local Memory
+ 0xac Requests Local CPU to Local (I/O or Mem)
+ 0xaf Requests Local (CPU or I/O) to Local (I/O or Mem)
+ 0x91 Requests Local I/O to Remote I/O
+ 0x92 Requests Local I/O to Remote Memory
+ 0x93 Requests Local I/O to Remote (I/O or Mem)
+ 0x94 Requests Local CPU to Remote I/O
+ 0x95 Requests Local (CPU or I/O) to Remote I/O
+ 0x98 Requests Local CPU to Remote Memory
+ 0x9a Requests Local (CPU or I/O) to Remote Memory
+ 0x9c Requests Local CPU to Remote (I/O or Mem)
+ 0x9f Requests Local (CPU or I/O) to Remote (I/O or Mem)
+ 0xb1 Requests Local I/O to Any I/O
+ 0xb2 Requests Local I/O to Any Memory
+ 0xb3 Requests Local I/O to Any (I/O or Mem)
+ 0xb4 Requests Local CPU to Any I/O
+ 0xb5 Requests Local (CPU or I/O) to Any I/O
+ 0xb8 Requests Local CPU to Any Memory
+ 0xba Requests Local (CPU or I/O) to Any Memory
+ 0xbc Requests Local CPU to Any (I/O or Mem)
+ 0xbf Requests Local (CPU or I/O) to Any (I/O or Mem)
+ 0x61 Requests Remote I/O to Local I/O
+ 0x64 Requests Remote CPU to Local I/O
+ 0x65 Requests Remote (CPU or I/O) to Local I/O
+name:cacheblock type:bitmask default:0x3d
+ 0x01 Victim Block (Writeback)
+ 0x04 Read Block (Dcache load miss refill)
+ 0x08 Read Block Shared (Icache refill)
+ 0x10 Read Block Modified (Dcache store miss refill)
+ 0x20 Change to Dirty (first store to clean block already in cache)
+name:dataprefetch type:bitmask default:0x03
+ 0x01 Cancelled prefetches
+ 0x02 Prefetch attempts
+name:memreqtype type:bitmask default:0x83
+ 0x01 Requests to non-cacheable (UC) memory
+ 0x02 Requests to write-combining (WC) memory or WC buffer flushes to WB memory
+ 0x80 Streaming store (SS) requests
+name:systemreadresponse type:bitmask default:0x7
+ 0x01 Exclusive
+ 0x02 Modified
+ 0x04 Shared
+ 0x08 Data Error
+name:writtentosystem type:bitmask default:0x1
+ 0x01 Quadword write transfer
+# BKDG 3.28 does not include unit_mask of 0x01 for "accesses by Locked instructions"
+name:dcachemisslocked type:bitmask default:0x02
+ 0x02 Data cache misses by locked instructions
+name:locked_ops type:bitmask default:0x04
+ 0x01 The number of locked instructions executed
+ 0x02 The number of cycles spent in speculative phase
+ 0x04 The number of cycles spent in non-speculative phase (including cache miss penalty)
+name:thermalstatus type:bitmask default:0x80
+ 0x01 Number of clocks MEMHOT_L is asserted
+ 0x04 Number of times the HTC transitions from inactive to active
+ 0x20 Number of clocks HTC P-state is inactive
+ 0x40 Number of clocks HTC P-state is active
+ 0x80 PROCHOT_L asserted by an external source and P-state change occurred
+name:memory_controller_requests type:bitmask default:0x78
+ 0x08 32 Bytes Sized Writes
+ 0x10 64 Bytes Sized Writes
+ 0x20 32 Bytes Sized Reads
+ 0x40 64 Bytes Sized Reads
+name:sideband_signals_and_special_cycles type:bitmask default:0x1f
+ 0x01 HALT
+ 0x02 STOPGRANT
+ 0x04 SHUTDOWN
+ 0x08 WBINVD
+ 0x10 INVD
+name:interrupt_events type:bitmask default:0xff
+ 0x01 Fixed
+ 0x02 LPA
+ 0x04 SMI
+ 0x08 NMI
+ 0x10 INIT
+ 0x20 STARTUP
+ 0x40 INT
+ 0x80 EOI
+name:httransmit type:bitmask default:0x3f
+ 0x01 Command DWORD sent
+ 0x02 Address DWORD sent
+ 0x04 Data DWORD sent
+ 0x08 Buffer release DWORD sent
+ 0x10 Nop DW sent (idle)
+ 0x20 Per packet CRC sent
diff --git a/events/x86-64/family12h/events b/events/x86-64/family12h/events
new file mode 100644
index 0000000..e576fc1
--- /dev/null
+++ b/events/x86-64/family12h/events
@@ -0,0 +1,23 @@
+# AMD Generic performance events
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2010 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+#
+# Revision: 1.0
+#
+# ChangeLog:
+# 1.0: 30 August 2010.
+# - Initial revision
+#
+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
+event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE : Data cache refills from L2 or Northbridge
+event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_NORTHBRIDGE : Data cache refills from Northbridge
+event:0x76 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+event:0xc0 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
+event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
+event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
+event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired mispredicted branch instructions
diff --git a/events/x86-64/family12h/unit_masks b/events/x86-64/family12h/unit_masks
new file mode 100644
index 0000000..c9d76a8
--- /dev/null
+++ b/events/x86-64/family12h/unit_masks
@@ -0,0 +1,30 @@
+# AMD Generic unit masks
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2010 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+#
+# Revision: 1.0
+#
+# ChangeLog:
+# 1.0: 30 August 2010.
+# - Initial revision
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:moesi type:bitmask default:0x1f
+ 0x01 (I)nvalid cache state
+ 0x02 (S)hared cache state
+ 0x04 (E)xclusive cache state
+ 0x08 (O)wner cache state
+ 0x10 (M)odified cache state
+ 0x1f All cache states
+name:moess type:bitmask default:0x1e
+ 0x01 Refill from northbridge
+ 0x02 Shared-state line from L2
+ 0x04 Exclusive-state line from L2
+ 0x08 Owner-state line from L2
+ 0x10 Modified-state line from L2
+ 0x1e All cache states except refill from northbridge
diff --git a/events/x86-64/family14h/events b/events/x86-64/family14h/events
new file mode 100644
index 0000000..e576fc1
--- /dev/null
+++ b/events/x86-64/family14h/events
@@ -0,0 +1,23 @@
+# AMD Generic performance events
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2010 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+#
+# Revision: 1.0
+#
+# ChangeLog:
+# 1.0: 30 August 2010.
+# - Initial revision
+#
+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
+event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE : Data cache refills from L2 or Northbridge
+event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_NORTHBRIDGE : Data cache refills from Northbridge
+event:0x76 counters:0,1,2,3 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+event:0xc0 counters:0,1,2,3 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
+event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
+event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
+event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired mispredicted branch instructions
diff --git a/events/x86-64/family14h/unit_masks b/events/x86-64/family14h/unit_masks
new file mode 100644
index 0000000..c9d76a8
--- /dev/null
+++ b/events/x86-64/family14h/unit_masks
@@ -0,0 +1,30 @@
+# AMD Generic unit masks
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2010 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+#
+# Revision: 1.0
+#
+# ChangeLog:
+# 1.0: 30 August 2010.
+# - Initial revision
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:moesi type:bitmask default:0x1f
+ 0x01 (I)nvalid cache state
+ 0x02 (S)hared cache state
+ 0x04 (E)xclusive cache state
+ 0x08 (O)wner cache state
+ 0x10 (M)odified cache state
+ 0x1f All cache states
+name:moess type:bitmask default:0x1e
+ 0x01 Refill from northbridge
+ 0x02 Shared-state line from L2
+ 0x04 Exclusive-state line from L2
+ 0x08 Owner-state line from L2
+ 0x10 Modified-state line from L2
+ 0x1e All cache states except refill from northbridge
diff --git a/events/x86-64/family15h/events b/events/x86-64/family15h/events
new file mode 100644
index 0000000..499938d
--- /dev/null
+++ b/events/x86-64/family15h/events
@@ -0,0 +1,16 @@
+# AMD Generic performance events
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2010 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+#
+# Revision: 1.0
+#
+# ChangeLog:
+# 1.0: 30 August 2010.
+# - Initial revision
+#
+event:0x76 counters:0,1,2 um:zero minimum:50000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+event:0xc0 counters:0,1,2,3,4,5 um:zero minimum:50000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
diff --git a/events/x86-64/family15h/unit_masks b/events/x86-64/family15h/unit_masks
new file mode 100644
index 0000000..6a9c06e
--- /dev/null
+++ b/events/x86-64/family15h/unit_masks
@@ -0,0 +1,16 @@
+# AMD Generic unit masks
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2010 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>,
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+#
+# Revision: 1.0
+#
+# ChangeLog:
+# 1.0: 30 August 2010.
+# - Initial revision
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/x86-64/hammer/events b/events/x86-64/hammer/events
new file mode 100644
index 0000000..a86482b
--- /dev/null
+++ b/events/x86-64/hammer/events
@@ -0,0 +1,125 @@
+#
+# AMD Athlon(tm)64 and AMD Opteron(tm) processor unit masks
+#
+# Copyright OProfile authors
+# Copyright (c) 2006-2008 Advanced Micro Devices
+# Contributed by Ray Bryant <raybry at amd.com>
+# Jason Yeh <jason.yeh at amd.com>
+# Suravee Suthikulpanit <suravee.suthikulpanit at amd.com>
+# Paul Drongowski <paul.drongowski at amd.com>
+#
+# Source: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors,
+# Publication# 32559, Revision 3.08, July 2007
+#
+# This file was last updated on 10 January 2008:
+#
+# Sorted by event select value for easier maintenance and to be
+# consistent with events for other AMD processor families.
+#
+# Updated for the latest version of the BKDG.
+#
+# Floating point events
+event:0x00 counters:0,1,2,3 um:fpu_ops minimum:500 name:DISPATCHED_FPU_OPS : Dispatched FPU ops
+event:0x01 counters:0,1,2,3 um:zero minimum:500 name:CYCLES_NO_FPU_OPS_RETIRED : Cycles with no FPU ops retired
+event:0x02 counters:0,1,2,3 um:zero minimum:500 name:DISPATCHED_FPU_OPS_FAST_FLAG : Dispatched FPU ops that use the fast flag interface
+
+# Load, Store, and TLB events
+event:0x20 counters:0,1,2,3 um:segregload minimum:500 name:SEGMENT_REGISTER_LOADS : Segment register loads
+event:0x21 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE : Micro-architectural re-sync caused by self modifying code
+event:0x22 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_PROBE_HIT : Micro-architectural re-sync caused by snoop
+event:0x23 counters:0,1,2,3 um:zero minimum:500 name:LS_BUFFER_2_FULL_CYCLES : Cycles LS Buffer 2 full
+event:0x24 counters:0,1,2,3 um:locked_ops minimum:500 name:LOCKED_OPS : Locked operations
+
+# Execution Unit Events
+event:0x26 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CLFLUSH_INSTRUCTIONS : Retired CLFLUSH instructions
+event:0x27 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_CPUID_INSTRUCTIONS : Retired CPUID instructions
+
+# Data Cache event
+event:0x40 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_ACCESSES : Data cache accesses
+event:0x41 counters:0,1,2,3 um:zero minimum:500 name:DATA_CACHE_MISSES : Data cache misses
+# Event 0x42 with unit mask 0x01 counts same events as event select 0x43
+event:0x42 counters:0,1,2,3 um:moess minimum:500 name:DATA_CACHE_REFILLS_FROM_L2_OR_SYSTEM : Data cache refills from L2 or system
+event:0x43 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_REFILLS_FROM_SYSTEM : Data cache refills from system
+event:0x44 counters:0,1,2,3 um:moesi minimum:500 name:DATA_CACHE_LINES_EVICTED : Data cache lines evicted
+event:0x45 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_MISS_AND_L2_DTLB_HIT : L1 DTLB misses and L2 DTLB hits
+event:0x46 counters:0,1,2,3 um:zero minimum:500 name:L1_DTLB_AND_L2_DTLB_MISS : L1 and L2 DTLB misses
+event:0x47 counters:0,1,2,3 um:zero minimum:500 name:MISALIGNED_ACCESSES : Misaligned Accesses
+event:0x48 counters:0,1,2,3 um:zero minimum:500 name:MICROARCHITECTURAL_LATE_CANCEL_OF_AN_ACCESS : Micro-architectural late cancel of an access
+event:0x49 counters:0,1,2,3 um:zero minimum:500 name:MICROARCHITECTURAL_EARLY_CANCEL_OF_AN_ACCESS : Micro-architectural early cancel of an access
+event:0x4a counters:0,1,2,3 um:ecc minimum:500 name:SCRUBBER_SINGLE_BIT_ECC_ERRORS : One bit ECC error recorded by scrubber
+event:0x4b counters:0,1,2,3 um:prefetch minimum:500 name:PREFETCH_INSTRUCTIONS_DISPATCHED : Prefetch instructions dispatched
+event:0x4c counters:0,1,2,3 um:dcachemisslocked minimum:500 name:DCACHE_MISS_LOCKED_INSTRUCTIONS : DCACHE misses by locked instructions
+
+# L2 Cache and System Interface events
+event:0x65 counters:0,1,2,3 um:memreqtype minimum:500 name:MEMORY_REQUESTS : Memory requests by type
+event:0x67 counters:0,1,2,3 um:dataprefetch minimum:500 name:DATA_PREFETCHES : Data prefetcher
+event:0x6c counters:0,1,2,3 um:systemreadresponse minimum:500 name:SYSTEM_READ_RESPONSES : System read responses by coherency state
+event:0x6d counters:0,1,2,3 um:writtentosystem minimum:500 name:QUADWORD_WRITE_TRANSFERS : Quadwords written to system
+event:0x76 counters:0,1,2,3 um:zero minimum:3000 name:CPU_CLK_UNHALTED : Cycles outside of halt state
+event:0x7d counters:0,1,2,3 um:l2_internal minimum:500 name:REQUESTS_TO_L2 : Requests to L2 cache
+event:0x7e counters:0,1,2,3 um:l2_req_miss minimum:500 name:L2_CACHE_MISS : L2 cache misses
+event:0x7f counters:0,1,2,3 um:l2_fill minimum:500 name:L2_CACHE_FILL_WRITEBACK : L2 fill/writeback
+
+# Instruction Cache events
+event:0x80 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_FETCHES : Instruction cache fetches
+event:0x81 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
+event:0x82 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_L2 : Instruction cache refills from L2
+event:0x83 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM : Instruction cache refills from system
+event:0x84 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_HIT : L1 ITLB miss and L2 ITLB hit
+event:0x85 counters:0,1,2,3 um:zero minimum:500 name:L1_ITLB_MISS_AND_L2_ITLB_MISS : L1 ITLB miss and L2 ITLB miss
+event:0x86 counters:0,1,2,3 um:zero minimum:500 name:PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE : Pipeline restart due to instruction stream probe
+event:0x87 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_FETCH_STALL : Instruction fetch stall
+event:0x88 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_HITS : Return stack hits
+event:0x89 counters:0,1,2,3 um:zero minimum:500 name:RETURN_STACK_OVERFLOWS : Return stack overflows
+
+# Execution Unit events
+event:0xc0 counters:0,1,2,3 um:zero minimum:3000 name:RETIRED_INSTRUCTIONS : Retired instructions (includes exceptions, interrupts, re-syncs)
+event:0xc1 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_UOPS : Retired micro-ops
+event:0xc2 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_INSTRUCTIONS : Retired branches (conditional, unconditional, exceptions, interrupts)
+event:0xc3 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS : Retired mispredicted branch instructions
+event:0xc4 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS : Retired taken branch instructions
+event:0xc5 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED : Retired taken branches mispredicted
+event:0xc6 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_FAR_CONTROL_TRANSFERS : Retired far control transfers
+event:0xc7 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_BRANCH_RESYNCS : Retired branches resyncs (only non-control transfer branches)
+event:0xc8 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS : Retired near returns
+event:0xc9 counters:0,1,2,3 um:zero minimum:500 name:RETIRED_NEAR_RETURNS_MISPREDICTED : Retired near returns mispredicted
+event:0xca counters:0,1,2,3 um:zero minimum:500 name:RETIRED_INDIRECT_BRANCHES_MISPREDICTED : Retired indirect branches mispredicted
+event:0xcb counters:0,1,2,3 um:fpu_instr minimum:500 name:RETIRED_MMX_FP_INSTRUCTIONS : Retired MMX/FP instructions
+event:0xcc counters:0,1,2,3 um:fpu_fastpath minimum:500 name:RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS : Retired FastPath double-op instructions
+event:0xcd counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES : Cycles with interrupts masked (IF=0)
+event:0xce counters:0,1,2,3 um:zero minimum:500 name:INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING : Cycles with interrupts masked while interrupt pending
+event:0xcf counters:0,1,2,3 um:zero minimum:10 name:INTERRUPTS_TAKEN : Number of taken hardware interrupts
+event:0xd0 counters:0,1,2,3 um:zero minimum:500 name:DECODER_EMPTY : Nothing to dispatch (decoder empty)
+event:0xd1 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALLS : Dispatch stalls
+event:0xd2 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_BRANCH_ABORT : Dispatch stall from branch abort to retire
+event:0xd3 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SERIALIZATION : Dispatch stall for serialization
+event:0xd4 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_SEGMENT_LOAD : Dispatch stall for segment load
+event:0xd5 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_REORDER_BUFFER_FULL : Dispatch stall for reorder buffer full
+event:0xd6 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_RESERVATION_STATION_FULL : Dispatch stall when reservation stations are full
+event:0xd7 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FPU_FULL : Dispatch stall when FPU is full
+event:0xd8 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_LS_FULL : Dispatch stall when LS is full
+event:0xd9 counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_WAITING_FOR_ALL_QUIET : Dispatch stall when waiting for all to be quiet
+event:0xda counters:0,1,2,3 um:zero minimum:500 name:DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC : Dispatch stall for far transfer or resync to retire
+event:0xdb counters:0,1,2,3 um:fpu_exceptions minimum:1 name:FPU_EXCEPTIONS : FPU exceptions
+event:0xdc counters:0,1,2,3 um:zero minimum:1 name:DR0_BREAKPOINTS : Number of breakpoints for DR0
+event:0xdd counters:0,1,2,3 um:zero minimum:1 name:DR1_BREAKPOINTS : Number of breakpoints for DR1
+event:0xde counters:0,1,2,3 um:zero minimum:1 name:DR2_BREAKPOINTS : Number of breakpoints for DR2
+event:0xdf counters:0,1,2,3 um:zero minimum:1 name:DR3_BREAKPOINTS : Number of breakpoints for DR3
+
+# Memory Controler events
+event:0xe0 counters:0,1,2,3 um:page_access minimum:500 name:DRAM_ACCESSES : DRAM accesses
+event:0xe1 counters:0,1,2,3 um:zero minimum:500 name:MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS : Memory controller page table overflows
+event:0xe3 counters:0,1,2,3 um:turnaround minimum:500 name:MEMORY_CONTROLLER_TURNAROUNDS : Memory controller turnarounds
+event:0xe4 counters:0,1,2,3 um:saturation minimum:500 name:MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION : Memory controller bypass saturation
+event:0xe5 counters:0,1,2,3 um:sizedblocks minimum:500 name:SIZED_BLOCKS : Sized blocks
+event:0xe8 counters:0,1,2,3 um:thermalecc minimum:500 name:THERMAL_STATUS_AND_DRAM_ECC_ERRORS : Thermal status and ECC errors
+event:0xe9 counters:0,1,2,3 um:cpiorequests minimum:500 name:CPU_IO_REQUESTS_TO_MEMORY_IO : CPU/IO requests to memory/IO (RevE)
+event:0xea counters:0,1,2,3 um:cacheblock minimum:500 name:CACHE_BLOCK_COMMANDS : Cache block commands (RevE)
+event:0xeb counters:0,1,2,3 um:sizecmds minimum:500 name:SIZED_COMMANDS : Sized commands
+event:0xec counters:0,1,2,3 um:probe minimum:500 name:PROBE_RESPONSES_AND_UPSTREAM_REQUESTS : Probe responses and upstream requests
+event:0xee counters:0,1,2,3 um:gart minimum:500 name:GART_EVENTS : GART events
+
+# Link events
+event:0xf6 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_LINK0_BANDWIDTH : HyperTransport(tm) link 0 transmit bandwidth
+event:0xf7 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_LINK1_BANDWIDTH : HyperTransport(tm) link 1 transmit bandwidth
+event:0xf8 counters:0,1,2,3 um:ht minimum:500 name:HYPERTRANSPORT_LINK2_BANDWIDTH : HyperTransport(tm) link 2 transmit bandwidth
diff --git a/events/x86-64/hammer/unit_masks b/events/x86-64/hammer/unit_masks
new file mode 100644
index 0000000..0e8ea66
--- /dev/null
+++ b/events/x86-64/hammer/unit_masks
@@ -0,0 +1,186 @@
+#
+# AMD Athlon(tm)64 and AMD Opteron(tm) processor unit masks
+#
+# Copyright OProfile authors
+# Copyright (c) Advanced Micro Devices, 2006-2008
+# Contributed by Ray Bryant <raybry@amd.com>, and others.
+#
+# Source: BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors,
+# Publication# 32559, Revision 3.08, July 2007
+#
+# This file was last updated on 10 January 2008:
+#
+# Unit mask (writtentosystem) was added for the
+# QUADWORD_WRITE_TRANSFERS event.
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
+name:moesi type:bitmask default:0x1f
+ 0x01 (I)nvalid cache state
+ 0x02 (S)hared cache state
+ 0x04 (E)xclusive cache state
+ 0x08 (O)wned cache state
+ 0x10 (M)odified cache state
+ 0x1f All cache states
+name:moess type:bitmask default:0x1e
+ 0x01 refill from system
+ 0x02 (S)hared cache state from L2
+ 0x04 (E)xclusive cache state from L2
+ 0x08 (O)wned cache state from L2
+ 0x10 (M)odified cache state from L2
+ 0x1e All cache states except Invalid
+name:fpu_ops type:bitmask default:0x3f
+ 0x01 Add pipe ops
+ 0x02 Multiply pipe
+ 0x04 Store pipe ops
+ 0x08 Add pipe load ops
+ 0x10 Multiply pipe load ops
+ 0x20 Store pipe load ops
+name:segregload type:bitmask default:0x7f
+ 0x01 ES register
+ 0x02 CS register
+ 0x04 SS register
+ 0x08 DS register
+ 0x10 FS register
+ 0x20 GS register
+ 0x40 HS register
+name:ecc type:bitmask default:0x03
+ 0x01 Scrubber error
+ 0x02 Piggyback scrubber errors
+name:prefetch type:bitmask default:0x07
+ 0x01 Load
+ 0x02 Store
+ 0x04 NTA
+name:fpu_instr type:bitmask default:0x0f
+ 0x01 x87 instructions
+ 0x02 Combined MMX & 3DNow instructions
+ 0x04 Combined packed SSE & SSE2 instructions
+ 0x08 Combined packed scalar SSE & SSE2 instructions
+name:fpu_fastpath type:bitmask default:0x07
+ 0x01 With low op in position 0
+ 0x02 With low op in position 1
+ 0x04 With low op in position 2
+name:fpu_exceptions type:bitmask default:0x0f
+ 0x01 x87 reclass microfaults
+ 0x02 SSE retype microfaults
+ 0x04 SSE reclass microfaults
+ 0x08 SSE and x87 microtraps
+name:page_access type:bitmask default:0x07
+ 0x01 Page hit
+ 0x02 Page miss
+ 0x04 Page conflict
+name:turnaround type:bitmask default:0x07
+ 0x01 DIMM (chip select) turnaround
+ 0x02 Read to write turnaround
+ 0x04 Write to read turnaround
+name:saturation type:bitmask default:0x0f
+ 0x01 Memory controller high priority bypass
+ 0x02 Memory controller low priority bypass
+ 0x04 DRAM controller interface bypass
+ 0x08 DRAM controller queue bypass
+name:sizecmds type:bitmask default:0x7f
+ 0x01 Non-posted write byte
+ 0x02 Non-posted write dword
+ 0x04 Posted write byte
+ 0x08 Posted write dword
+ 0x10 Read byte (4 bytes)
+ 0x20 Read dword (1-16 dwords)
+ 0x40 Read-modify-write
+name:probe type:bitmask default:0x0f
+ 0x01 Probe miss
+ 0x02 Probe hit clean
+ 0x04 Probe hit dirty without memory cancel
+ 0x08 Probe hit dirty with memory cancel
+ 0x10 Upstream display refresh reads
+ 0x20 Upstream non-display refresh reads
+ 0x40 Upstream writes (RevD and later)
+name:ht type:bitmask default:0x7
+ 0x01 Command sent
+ 0x02 Data sent
+ 0x04 Buffer release sent
+ 0x08 NOP sent
+name:l2_internal type:bitmask default:0x1f
+ 0x01 IC fill
+ 0x02 DC fill
+ 0x04 TLB fill (page table walk)
+ 0x08 Tag snoop request
+ 0x10 Cancelled request
+name:l2_req_miss type:bitmask default:0x07
+ 0x01 IC fill
+ 0x02 DC fill
+ 0x04 TLB page table walk
+name:l2_fill type:bitmask default:0x03
+ 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
+ 0x02 L2 writebacks to system
+name:gart type:bitmask default:0x07
+ 0x01 GART aperture hit on access from CPU
+ 0x02 GART aperture hit on access from I/O
+ 0x04 GART miss
+name:sizedblocks type:bitmask default:0x3c
+ 0x04 32-byte Sized Writes (RevD and later)
+ 0x08 64-byte Sized Writes (RevD and later)
+ 0x10 32-byte Sized Reads (RevD and later)
+ 0x20 64-byte Sized Reads (RevD and later)
+name:cpiorequests type:bitmask default:0xa2
+ 0xa1 Requests Local I/O to Local I/O
+ 0xa2 Requests Local I/O to Local Memory
+ 0xa3 Requests Local I/O to Local (I/O or Mem)
+ 0xa4 Requests Local CPU to Local I/O
+ 0xa5 Requests Local (CPU or I/O) to Local I/O
+ 0xa8 Requests Local CPU to Local Memory
+ 0xaa Requests Local (CPU or I/O) to Local Memory
+ 0xac Requests Local CPU to Local (I/O or Mem)
+ 0xaf Requests Local (CPU or I/O) to Local (I/O or Mem)
+ 0x91 Requests Local I/O to Remote I/O
+ 0x92 Requests Local I/O to Remote Memory
+ 0x93 Requests Local I/O to Remote (I/O or Mem)
+ 0x94 Requests Local CPU to Remote I/O
+ 0x95 Requests Local (CPU or I/O) to Remote I/O
+ 0x98 Requests Local CPU to Remote Memory
+ 0x9a Requests Local (CPU or I/O) to Remote Memory
+ 0x9c Requests Local CPU to Remote (I/O or Mem)
+ 0x9f Requests Local (CPU or I/O) to Remote (I/O or Mem)
+ 0xb1 Requests Local I/O to Any I/O
+ 0xb2 Requests Local I/O to Any Memory
+ 0xb3 Requests Local I/O to Any (I/O or Mem)
+ 0xb4 Requests Local CPU to Any I/O
+ 0xb5 Requests Local (CPU or I/O) to Any I/O
+ 0xb8 Requests Local CPU to Any Memory
+ 0xba Requests Local (CPU or I/O) to Any Memory
+ 0xbc Requests Local CPU to Any (I/O or Mem)
+ 0xbf Requests Local (CPU or I/O) to Any (I/O or Mem)
+ 0x61 Requests Remote I/O to Local I/O
+ 0x64 Requests Remote CPU to Local I/O
+ 0x65 Requests Remote (CPU or I/O) to Local I/O
+name:cacheblock type:bitmask default:0x3d
+ 0x01 Victim Block (Writeback)
+ 0x04 Read Block (Dcache load miss refill)
+ 0x08 Read Block Shared (Icache refill)
+ 0x10 Read Block Modified (Dcache store miss refill)
+ 0x20 Change to Dirty (first store to clean block already in cache)
+name:dataprefetch type:bitmask default:0x03
+ 0x01 Cancelled prefetches
+ 0x02 Prefetch attempts
+name:memreqtype type:bitmask default:0x83
+ 0x01 Requests to non-cacheable (UC) memory
+ 0x02 Requests to write-combining (WC) memory or WC buffer flushes to WB memory
+ 0x80 Streaming store (SS) requests
+name:systemreadresponse type:bitmask default:0x7
+ 0x01 Exclusive
+ 0x02 Modified
+ 0x04 Shared
+name:writtentosystem type:bitmask default:0x1
+ 0x01 Quadword write transfer
+# BKDG 3.28 does not include unit_mask of 0x01 for "accesses by Locked instructions"
+name:dcachemisslocked type:bitmask default:0x02
+ 0x02 Data cache misses by locked instructions
+name:locked_ops type:bitmask default:0x04
+ 0x01 The number of locked instructions executed
+ 0x02 The number of cycles spent in speculative phase
+ 0x04 The number of cycles spent in non-speculative phase (including cache miss penalty)
+name:thermalecc type:bitmask default:0x80
+ 0x01 Number of clocks CPU is active when HTC is active (RevF)
+ 0x02 Number of clocks CPU clock is inactive when HTC is active (RevF)
+ 0x04 Number of clocks when die temperature is higher than the software high temperature threshold (RevF)
+ 0x08 Number of clocks when high temperature threshold was exceeded (RevF)
+ 0x80 Number of correctable and uncorrectable DRAM ECC errors (RevE)