1 files changed, 35 insertions, 0 deletions
diff --git a/src/riscv/mod.rs b/src/riscv/mod.rs
new file mode 100644
index 0000000..62ce98e
--- /dev/null
+++ b/src/riscv/mod.rs
@@ -0,0 +1,35 @@
+//! Implementations for the [RISC-V](https://riscv.org/) architecture.
+//!
+//! *Note*: currently only supports integer versions of the ISA.
+
+use gdbstub::arch::Arch;
+
+pub mod reg;
+
+/// Implements `Arch` for 32-bit RISC-V.
+pub enum Riscv32 {}
+
+/// Implements `Arch` for 64-bit RISC-V.
+pub enum Riscv64 {}
+
+impl Arch for Riscv32 {
+    type Usize = u32;
+    type Registers = reg::RiscvCoreRegs<u32>;
+    type RegId = reg::id::RiscvRegId<u32>;
+    type BreakpointKind = usize;
+
+    fn target_description_xml() -> Option<&'static str> {
+        Some(r#"<target version="1.0"><architecture>riscv</architecture></target>"#)
+    }
+}
+
+impl Arch for Riscv64 {
+    type Usize = u64;
+    type Registers = reg::RiscvCoreRegs<u64>;
+    type RegId = reg::id::RiscvRegId<u64>;
+    type BreakpointKind = usize;
+
+    fn target_description_xml() -> Option<&'static str> {
+        Some(r#"<target version="1.0"><architecture>riscv64</architecture></target>"#)
+    }
+}