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author | Wei Huang <wei@redhat.com> | 2017-11-20 23:49:10 -0500 |
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committer | Wei Huang <wei@redhat.com> | 2017-11-20 23:07:02 -0600 |
commit | 82af7e15583882f6748abe76ba5d8585fe4ae52b (patch) | |
tree | dc568b3df8bec2cb447f42d41a85a5514aa2c6ae | |
parent | 53aadb92f3822085d5c0c2ddf292bb05aabee932 (diff) | |
download | stressapptest-82af7e15583882f6748abe76ba5d8585fe4ae52b.tar.gz |
Add aarch64 support in OS related code
This patch adds OS related support for aarch64. Other than removing
unncessary warnings, it adds two aarch64 specific functions: cache
line flush and gettsc.
Signed-off-by: Wei Huang <wei@redhat.com>
-rw-r--r-- | src/os.h | 14 |
1 files changed, 11 insertions, 3 deletions
@@ -156,6 +156,12 @@ class OsLayer { #elif defined(STRESSAPPTEST_CPU_ARMV7A) // ARMv7a cachelines are 8 words (32 bytes). syscall(__ARM_NR_cacheflush, vaddr, reinterpret_cast<char*>(vaddr) + 32, 0); +#elif defined(STRESSAPPTEST_CPU_AARCH64) + asm volatile("dc cvau, %0" : : "r" (vaddr)); + asm volatile("dsb ish"); + asm volatile("ic ivau, %0" : : "r" (vaddr)); + asm volatile("dsb ish"); + asm volatile("isb"); #else #warning "Unsupported CPU type: Unable to force cache flushes." #endif @@ -186,7 +192,7 @@ class OsLayer { asm volatile("clflush (%0)" : : "r" (*vaddrs++)); } asm volatile("mfence"); -#elif defined(STRESSAPPTEST_CPU_ARMV7A) +#elif defined(STRESSAPPTEST_CPU_ARMV7A) || defined(STRESSAPPTEST_CPU_AARCH64) while (*vaddrs) { FastFlush(*vaddrs++); } @@ -211,7 +217,7 @@ class OsLayer { // instruction. For example, software can use an MFENCE instruction to // insure that previous stores are included in the write-back. asm volatile("clflush (%0)" : : "r" (vaddr)); -#elif defined(STRESSAPPTEST_CPU_ARMV7A) +#elif defined(STRESSAPPTEST_CPU_ARMV7A) || defined(STRESSAPPTEST_CPU_AARCH64) FastFlush(vaddr); #else #warning "Unsupported CPU type: Unable to force cache flushes." @@ -236,7 +242,7 @@ class OsLayer { // instruction. For example, software can use an MFENCE instruction to // insure that previous stores are included in the write-back. asm volatile("mfence"); -#elif defined(STRESSAPPTEST_CPU_ARMV7A) +#elif defined(STRESSAPPTEST_CPU_ARMV7A) || defined(STRESSAPPTEST_CPU_AARCH64) // This is a NOP, FastFlushHint() always does a full flush, so there's // nothing to do for FastFlushSync(). #else @@ -269,6 +275,8 @@ class OsLayer { #elif defined(STRESSAPPTEST_CPU_ARMV7A) #warning "Unsupported CPU type ARMV7A: your timer may not function correctly" tsc = 0; +#elif defined(STRESSAPPTEST_CPU_AARCH64) + __asm __volatile("mrs %0, CNTVCT_EL0" : "=r" (tsc) : : ); #else #warning "Unsupported CPU type: your timer may not function correctly" tsc = 0; |