{ global: Tss2_MU_BYTE_Marshal; Tss2_MU_BYTE_Unmarshal; Tss2_MU_INT8_Marshal; Tss2_MU_INT8_Unmarshal; Tss2_MU_INT16_Marshal; Tss2_MU_INT16_Unmarshal; Tss2_MU_INT32_Marshal; Tss2_MU_INT32_Unmarshal; Tss2_MU_INT64_Marshal; Tss2_MU_INT64_Unmarshal; Tss2_MU_UINT8_Marshal; Tss2_MU_UINT8_Unmarshal; Tss2_MU_UINT16_Marshal; Tss2_MU_UINT16_Unmarshal; Tss2_MU_UINT32_Marshal; Tss2_MU_UINT32_Unmarshal; Tss2_MU_UINT64_Marshal; Tss2_MU_UINT64_Unmarshal; Tss2_MU_TPM2_CC_Marshal; Tss2_MU_TPM2_CC_Unmarshal; Tss2_MU_TPM2_ST_Marshal; Tss2_MU_TPM2_ST_Unmarshal; Tss2_MU_TPMA_ALGORITHM_Marshal; Tss2_MU_TPMA_ALGORITHM_Unmarshal; Tss2_MU_TPMA_CC_Marshal; Tss2_MU_TPMA_CC_Unmarshal; Tss2_MU_TPMA_LOCALITY_Marshal; Tss2_MU_TPMA_LOCALITY_Unmarshal; Tss2_MU_TPMA_NV_Marshal; Tss2_MU_TPMA_NV_Unmarshal; Tss2_MU_TPMA_OBJECT_Marshal; Tss2_MU_TPMA_OBJECT_Unmarshal; Tss2_MU_TPMA_PERMANENT_Marshal; Tss2_MU_TPMA_PERMANENT_Unmarshal; Tss2_MU_TPMA_SESSION_Marshal; Tss2_MU_TPMA_SESSION_Unmarshal; Tss2_MU_TPMA_STARTUP_CLEAR_Marshal; Tss2_MU_TPMA_STARTUP_CLEAR_Unmarshal; Tss2_MU_TPM2B_DIGEST_Marshal; Tss2_MU_TPM2B_DIGEST_Unmarshal; Tss2_MU_TPM2B_NAME_Marshal; Tss2_MU_TPM2B_NAME_Unmarshal; Tss2_MU_TPM2B_MAX_NV_BUFFER_Marshal; Tss2_MU_TPM2B_MAX_NV_BUFFER_Unmarshal; Tss2_MU_TPM2B_SENSITIVE_DATA_Marshal; Tss2_MU_TPM2B_SENSITIVE_DATA_Unmarshal; Tss2_MU_TPM2B_ECC_PARAMETER_Marshal; Tss2_MU_TPM2B_ECC_PARAMETER_Unmarshal; Tss2_MU_TPM2B_PUBLIC_KEY_RSA_Marshal; Tss2_MU_TPM2B_PUBLIC_KEY_RSA_Unmarshal; Tss2_MU_TPM2B_PRIVATE_KEY_RSA_Marshal; Tss2_MU_TPM2B_PRIVATE_KEY_RSA_Unmarshal; Tss2_MU_TPM2B_PRIVATE_Marshal; Tss2_MU_TPM2B_PRIVATE_Unmarshal; Tss2_MU_TPM2B_CONTEXT_SENSITIVE_Marshal; Tss2_MU_TPM2B_CONTEXT_SENSITIVE_Unmarshal; Tss2_MU_TPM2B_CONTEXT_DATA_Marshal; Tss2_MU_TPM2B_CONTEXT_DATA_Unmarshal; Tss2_MU_TPM2B_DATA_Marshal; Tss2_MU_TPM2B_DATA_Unmarshal; Tss2_MU_TPM2B_SYM_KEY_Marshal; Tss2_MU_TPM2B_SYM_KEY_Unmarshal; Tss2_MU_TPM2B_ECC_POINT_Marshal; Tss2_MU_TPM2B_ECC_POINT_Unmarshal; Tss2_MU_TPM2B_NV_PUBLIC_Marshal; Tss2_MU_TPM2B_NV_PUBLIC_Unmarshal; Tss2_MU_TPM2B_SENSITIVE_Marshal; Tss2_MU_TPM2B_SENSITIVE_Unmarshal; Tss2_MU_TPM2B_SENSITIVE_CREATE_Marshal; Tss2_MU_TPM2B_SENSITIVE_CREATE_Unmarshal; Tss2_MU_TPM2B_CREATION_DATA_Marshal; Tss2_MU_TPM2B_CREATION_DATA_Unmarshal; Tss2_MU_TPM2B_PUBLIC_Marshal; Tss2_MU_TPM2B_PUBLIC_Unmarshal; Tss2_MU_TPM2B_ID_OBJECT_Marshal; Tss2_MU_TPM2B_ID_OBJECT_Unmarshal; Tss2_MU_TPM2B_ENCRYPTED_SECRET_Marshal; Tss2_MU_TPM2B_ENCRYPTED_SECRET_Unmarshal; Tss2_MU_TPM2B_ATTEST_Marshal; Tss2_MU_TPM2B_ATTEST_Unmarshal; Tss2_MU_TPM2B_MAX_BUFFER_Marshal; Tss2_MU_TPM2B_MAX_BUFFER_Unmarshal; Tss2_MU_TPM2B_IV_Marshal; Tss2_MU_TPM2B_IV_Unmarshal; Tss2_MU_TPM2B_AUTH_Marshal; Tss2_MU_TPM2B_AUTH_Unmarshal; Tss2_MU_TPM2B_EVENT_Marshal; Tss2_MU_TPM2B_EVENT_Unmarshal; Tss2_MU_TPM2B_NONCE_Marshal; Tss2_MU_TPM2B_NONCE_Unmarshal; Tss2_MU_TPM2B_OPERAND_Marshal; Tss2_MU_TPM2B_OPERAND_Unmarshal; Tss2_MU_TPM2B_TIMEOUT_Marshal; Tss2_MU_TPM2B_TIMEOUT_Unmarshal; Tss2_MU_TPM2B_TEMPLATE_Marshal; Tss2_MU_TPM2B_TEMPLATE_Unmarshal; Tss2_MU_TPMS_CONTEXT_Marshal; Tss2_MU_TPMS_CONTEXT_Unmarshal; Tss2_MU_TPMS_TIME_INFO_Marshal; Tss2_MU_TPMS_TIME_INFO_Unmarshal; Tss2_MU_TPMS_ECC_POINT_Marshal; Tss2_MU_TPMS_ECC_POINT_Unmarshal; Tss2_MU_TPMS_NV_PUBLIC_Marshal; Tss2_MU_TPMS_NV_PUBLIC_Unmarshal; Tss2_MU_TPMS_ALG_PROPERTY_Marshal; Tss2_MU_TPMS_ALG_PROPERTY_Unmarshal; Tss2_MU_TPMS_ALGORITHM_DESCRIPTION_Marshal; Tss2_MU_TPMS_ALGORITHM_DESCRIPTION_Unmarshal; Tss2_MU_TPMS_TAGGED_PROPERTY_Marshal; Tss2_MU_TPMS_TAGGED_PROPERTY_Unmarshal; Tss2_MU_TPMS_CLOCK_INFO_Marshal; Tss2_MU_TPMS_CLOCK_INFO_Unmarshal; Tss2_MU_TPMS_TIME_ATTEST_INFO_Marshal; Tss2_MU_TPMS_TIME_ATTEST_INFO_Unmarshal; Tss2_MU_TPMS_CERTIFY_INFO_Marshal; Tss2_MU_TPMS_CERTIFY_INFO_Unmarshal; Tss2_MU_TPMS_COMMAND_AUDIT_INFO_Marshal; Tss2_MU_TPMS_COMMAND_AUDIT_INFO_Unmarshal; Tss2_MU_TPMS_SESSION_AUDIT_INFO_Marshal; Tss2_MU_TPMS_SESSION_AUDIT_INFO_Unmarshal; Tss2_MU_TPMS_CREATION_INFO_Marshal; Tss2_MU_TPMS_CREATION_INFO_Unmarshal; Tss2_MU_TPMS_NV_CERTIFY_INFO_Marshal; Tss2_MU_TPMS_NV_CERTIFY_INFO_Unmarshal; Tss2_MU_TPMS_AUTH_COMMAND_Marshal; Tss2_MU_TPMS_AUTH_COMMAND_Unmarshal; Tss2_MU_TPMS_AUTH_RESPONSE_Marshal; Tss2_MU_TPMS_AUTH_RESPONSE_Unmarshal; Tss2_MU_TPMS_SENSITIVE_CREATE_Marshal; Tss2_MU_TPMS_SENSITIVE_CREATE_Unmarshal; Tss2_MU_TPMS_SCHEME_HASH_Marshal; Tss2_MU_TPMS_SCHEME_HASH_Unmarshal; Tss2_MU_TPMS_SCHEME_ECDAA_Marshal; Tss2_MU_TPMS_SCHEME_ECDAA_Unmarshal; Tss2_MU_TPMS_SCHEME_XOR_Marshal; Tss2_MU_TPMS_SCHEME_XOR_Unmarshal; Tss2_MU_TPMS_SIGNATURE_RSA_Marshal; Tss2_MU_TPMS_SIGNATURE_RSA_Unmarshal; Tss2_MU_TPMS_SIGNATURE_ECC_Marshal; Tss2_MU_TPMS_SIGNATURE_ECC_Unmarshal; Tss2_MU_TPMS_NV_PIN_COUNTER_PARAMETERS_Marshal; Tss2_MU_TPMS_NV_PIN_COUNTER_PARAMETERS_Unmarshal; Tss2_MU_TPMS_CONTEXT_DATA_Marshal; Tss2_MU_TPMS_CONTEXT_DATA_Unmarshal; Tss2_MU_TPMS_PCR_SELECT_Marshal; Tss2_MU_TPMS_PCR_SELECT_Unmarshal; Tss2_MU_TPMS_PCR_SELECTION_Marshal; Tss2_MU_TPMS_PCR_SELECTION_Unmarshal; Tss2_MU_TPMS_TAGGED_PCR_SELECT_Marshal; Tss2_MU_TPMS_TAGGED_PCR_SELECT_Unmarshal; Tss2_MU_TPMS_QUOTE_INFO_Marshal; Tss2_MU_TPMS_QUOTE_INFO_Unmarshal; Tss2_MU_TPMS_CREATION_DATA_Marshal; Tss2_MU_TPMS_CREATION_DATA_Unmarshal; Tss2_MU_TPMS_ECC_PARMS_Marshal; Tss2_MU_TPMS_ECC_PARMS_Unmarshal; Tss2_MU_TPMS_ATTEST_Marshal; Tss2_MU_TPMS_ATTEST_Unmarshal; Tss2_MU_TPMS_ALGORITHM_DETAIL_ECC_Marshal; Tss2_MU_TPMS_ALGORITHM_DETAIL_ECC_Unmarshal; Tss2_MU_TPMS_CAPABILITY_DATA_Marshal; Tss2_MU_TPMS_CAPABILITY_DATA_Unmarshal; Tss2_MU_TPMS_KEYEDHASH_PARMS_Marshal; Tss2_MU_TPMS_KEYEDHASH_PARMS_Unmarshal; Tss2_MU_TPMS_RSA_PARMS_Marshal; Tss2_MU_TPMS_RSA_PARMS_Unmarshal; Tss2_MU_TPMS_SYMCIPHER_PARMS_Marshal; Tss2_MU_TPMS_SYMCIPHER_PARMS_Unmarshal; Tss2_MU_TPMS_AC_OUTPUT_Marshal; Tss2_MU_TPMS_AC_OUTPUT_Unmarshal; Tss2_MU_TPMS_ID_OBJECT_Marshal; Tss2_MU_TPMS_ID_OBJECT_Unmarshal; Tss2_MU_TPML_CC_Marshal; Tss2_MU_TPML_CC_Unmarshal; Tss2_MU_TPML_CCA_Marshal; Tss2_MU_TPML_CCA_Unmarshal; Tss2_MU_TPML_ALG_Marshal; Tss2_MU_TPML_ALG_Unmarshal; Tss2_MU_TPML_ALG_PROPERTY_Marshal; Tss2_MU_TPML_ALG_PROPERTY_Unmarshal; Tss2_MU_TPML_HANDLE_Marshal; Tss2_MU_TPML_HANDLE_Unmarshal; Tss2_MU_TPML_DIGEST_Marshal; Tss2_MU_TPML_DIGEST_Unmarshal; Tss2_MU_TPML_ECC_CURVE_Marshal; Tss2_MU_TPML_ECC_CURVE_Unmarshal; Tss2_MU_TPML_TAGGED_TPM_PROPERTY_Marshal; Tss2_MU_TPML_TAGGED_TPM_PROPERTY_Unmarshal; Tss2_MU_TPML_TAGGED_PCR_PROPERTY_Marshal; Tss2_MU_TPML_TAGGED_PCR_PROPERTY_Unmarshal; Tss2_MU_TPML_PCR_SELECTION_Marshal; Tss2_MU_TPML_PCR_SELECTION_Unmarshal; Tss2_MU_TPML_DIGEST_VALUES_Marshal; Tss2_MU_TPML_DIGEST_VALUES_Unmarshal; Tss2_MU_TPML_INTEL_PTT_PROPERTY_Marshal; Tss2_MU_TPML_INTEL_PTT_PROPERTY_Unmarshal; Tss2_MU_TPML_AC_CAPABILITIES_Marshal; Tss2_MU_TPML_AC_CAPABILITIES_Unmarshal; Tss2_MU_TPMU_HA_Marshal; Tss2_MU_TPMU_HA_Unmarshal; Tss2_MU_TPMU_ATTEST_Marshal; Tss2_MU_TPMU_ATTEST_Unmarshal; Tss2_MU_TPMU_SYM_KEY_BITS_Marshal; Tss2_MU_TPMU_SYM_KEY_BITS_Unmarshal; Tss2_MU_TPMU_SYM_MODE_Marshal; Tss2_MU_TPMU_SYM_MODE_Unmarshal; Tss2_MU_TPMU_SIG_SCHEME_Marshal; Tss2_MU_TPMU_SIG_SCHEME_Unmarshal; Tss2_MU_TPMU_KDF_SCHEME_Marshal; Tss2_MU_TPMU_KDF_SCHEME_Unmarshal; Tss2_MU_TPMU_ASYM_SCHEME_Marshal; Tss2_MU_TPMU_ASYM_SCHEME_Unmarshal; Tss2_MU_TPMU_SCHEME_KEYEDHASH_Marshal; Tss2_MU_TPMU_SCHEME_KEYEDHASH_Unmarshal; Tss2_MU_TPMU_SIGNATURE_Marshal; Tss2_MU_TPMU_SIGNATURE_Unmarshal; Tss2_MU_TPMU_SENSITIVE_COMPOSITE_Marshal; Tss2_MU_TPMU_SENSITIVE_COMPOSITE_Unmarshal; Tss2_MU_TPMU_CAPABILITIES_Marshal; Tss2_MU_TPMU_CAPABILITIES_Unmarshal; Tss2_MU_TPMU_PUBLIC_PARMS_Marshal; Tss2_MU_TPMU_PUBLIC_PARMS_Unmarshal; Tss2_MU_TPMU_PUBLIC_ID_Marshal; Tss2_MU_TPMU_PUBLIC_ID_Unmarshal; Tss2_MU_TPMU_NAME_Marshal; Tss2_MU_TPMU_NAME_Unmarshal; Tss2_MU_TPMT_HA_Marshal; Tss2_MU_TPMT_HA_Unmarshal; Tss2_MU_TPMT_SYM_DEF_Marshal; Tss2_MU_TPMT_SYM_DEF_Unmarshal; Tss2_MU_TPMT_SYM_DEF_OBJECT_Marshal; Tss2_MU_TPMT_SYM_DEF_OBJECT_Unmarshal; Tss2_MU_TPMT_KEYEDHASH_SCHEME_Marshal; Tss2_MU_TPMT_KEYEDHASH_SCHEME_Unmarshal; Tss2_MU_TPMT_SIG_SCHEME_Marshal; Tss2_MU_TPMT_SIG_SCHEME_Unmarshal; Tss2_MU_TPMT_KDF_SCHEME_Marshal; Tss2_MU_TPMT_KDF_SCHEME_Unmarshal; Tss2_MU_TPMT_ASYM_SCHEME_Marshal; Tss2_MU_TPMT_ASYM_SCHEME_Unmarshal; Tss2_MU_TPMT_RSA_SCHEME_Marshal; Tss2_MU_TPMT_RSA_SCHEME_Unmarshal; Tss2_MU_TPMT_RSA_DECRYPT_Marshal; Tss2_MU_TPMT_RSA_DECRYPT_Unmarshal; Tss2_MU_TPMT_ECC_SCHEME_Marshal; Tss2_MU_TPMT_ECC_SCHEME_Unmarshal; Tss2_MU_TPMT_SIGNATURE_Marshal; Tss2_MU_TPMT_SIGNATURE_Unmarshal; Tss2_MU_TPMT_SENSITIVE_Marshal; Tss2_MU_TPMT_SENSITIVE_Unmarshal; Tss2_MU_TPMT_PUBLIC_Marshal; Tss2_MU_TPMT_PUBLIC_Unmarshal; Tss2_MU_TPMT_PUBLIC_PARMS_Marshal; Tss2_MU_TPMT_PUBLIC_PARMS_Unmarshal; Tss2_MU_TPMT_TK_CREATION_Marshal; Tss2_MU_TPMT_TK_CREATION_Unmarshal; Tss2_MU_TPMT_TK_VERIFIED_Marshal; Tss2_MU_TPMT_TK_VERIFIED_Unmarshal; Tss2_MU_TPMT_TK_AUTH_Marshal; Tss2_MU_TPMT_TK_AUTH_Unmarshal; Tss2_MU_TPMT_TK_HASHCHECK_Marshal; Tss2_MU_TPMT_TK_HASHCHECK_Unmarshal; Tss2_MU_TPMS_EMPTY_Marshal; Tss2_MU_TPMS_EMPTY_Unmarshal; Tss2_MU_TPM2_HANDLE_Marshal; Tss2_MU_TPM2_HANDLE_Unmarshal; Tss2_MU_TPM2_SE_Marshal; Tss2_MU_TPM2_SE_Unmarshal; Tss2_MU_TPM2_NT_Marshal; Tss2_MU_TPM2_NT_Unmarshal; Tss2_MU_TPMI_ALG_HASH_Marshal; Tss2_MU_TPMI_ALG_HASH_Unmarshal; Tss2_MU_TPMI_BYTE_Marshal; Tss2_MU_TPMI_BYTE_Unmarshal; local: *; };