From 7649bf9057f6c247e04160a5fd75aeb66b0abad6 Mon Sep 17 00:00:00 2001 From: Elliott Hughes Date: Fri, 30 Apr 2021 09:36:43 -0700 Subject: Fix ARM assembler to work with clang's as. Trivial changes so that B/H comes *before* the condition code on LDR instructions in the modern syntax, and a more complicated macro fix to reimplement ADRL (which is a pseudo-op that expands to *two* instructions, an idea that isn't supported by LLVM). Bug: http://b/133391830 Test: treehugger Change-Id: Ib655cc020f94a8637a74c9cc3ced754cdf23c629 --- Tremolo/dpen.s | 4 ++-- Tremolo/mdctARM.s | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) (limited to 'Tremolo') diff --git a/Tremolo/dpen.s b/Tremolo/dpen.s index 3ed3b36..cc492cf 100644 --- a/Tremolo/dpen.s +++ b/Tremolo/dpen.s @@ -143,7 +143,7 @@ m1_loop: BLT duff CMP r8, r7 @ if bit==0 (chase+bit==chase) (sets C) - LDRNEB r14,[r6, r7] @ r14= t[chase] + LDRBNE r14,[r6, r7] @ r14= t[chase] MOVEQ r14,#128 ADC r12,r8, r6 @ r12= chase+bit+1+t LDRB r14,[r12,r14,LSR #7] @ r14= t[chase+bit+1+(!bit || t[chase]0x0x80)] @@ -202,7 +202,7 @@ m3_loop: MOV r7, r7, LSL #1 CMP r8, r7 @ if bit==0 (chase+bit==chase) sets C - LDRNEH r14,[r6, r7] @ r14= t[chase] + LDRHNE r14,[r6, r7] @ r14= t[chase] MOVEQ r14,#0x8000 ADC r12,r8, r14,LSR #15 @ r12= 1+((chase+bit)<<1)+(!bit || t[chase]0x0x8000) ADC r12,r12,r14,LSR #15 @ r12= t + (1+chase+bit+(!bit || t[chase]0x0x8000))<<1 diff --git a/Tremolo/mdctARM.s b/Tremolo/mdctARM.s index c403f6c..c16c5e9 100644 --- a/Tremolo/mdctARM.s +++ b/Tremolo/mdctARM.s @@ -55,6 +55,14 @@ .hidden sincos_lookup0 .hidden sincos_lookup1 + @ clang doesn't support ADRL. + @ Workaround based on that at https://bugs.llvm.org/show_bug.cgi?id=24350. + .macro ADRL reg:req, label:req + add \reg, pc, #((\label - .L_adrl_\@) & 0xff00) + add \reg, \reg, #((\label - .L_adrl_\@) - ((\label - .L_adrl_\@) & 0xff00)) + .L_adrl_\@: + .endm + mdct_unroll_prelap: @ r0 = out @ r1 = post -- cgit v1.2.3