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| author | Ben Cheng <bccheng@google.com> | 2013-03-11 13:58:54 -0700 |
|---|---|---|
| committer | Ben Cheng <bccheng@google.com> | 2013-03-11 14:28:14 -0700 |
| commit | 91b8144359fc6c68fecae099d117372f95144842 (patch) | |
| tree | 1cba6d16d66cbd48362c96b38cefab918588bb15 | |
| parent | 917486bb2d1e7a1fd6588eb35e7e4232e3075a93 (diff) | |
| download | valgrind-91b8144359fc6c68fecae099d117372f95144842.tar.gz | |
Add support for ARM mode smmla instructions.
BUG: 8350745
[cherry-picked from internal master]
Change-Id: I6fbd1289ac5fdb53ba6e38f2ea3ff189f6f319b3
| -rw-r--r-- | main/VEX/priv/guest_arm_toIR.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/main/VEX/priv/guest_arm_toIR.c b/main/VEX/priv/guest_arm_toIR.c index 220c50f66..4c5cb9630 100644 --- a/main/VEX/priv/guest_arm_toIR.c +++ b/main/VEX/priv/guest_arm_toIR.c @@ -14602,6 +14602,30 @@ DisResult disInstr_ARM_WRK ( } } + /* ------------------- smmla ------------------ */ + if (INSN(27,20) == BITS8(0,1,1,1,0,1,0,1) + && INSN(15,12) != BITS4(1,1,1,1) + && (INSN(7,4) & BITS4(1,1,0,1)) == BITS4(0,0,0,1)) { + UInt bitR = INSN(5,5); + UInt rD = INSN(19,16); + UInt rA = INSN(15,12); + UInt rM = INSN(11,8); + UInt rN = INSN(3,0); + if (rD != 15 && rM != 15 && rN != 15) { + IRExpr* res + = unop(Iop_64HIto32, + binop(Iop_Add64, + binop(Iop_Add64, + binop(Iop_32HLto64, getIRegA(rA), mkU32(0)), + binop(Iop_MullS32, getIRegA(rN), getIRegA(rM))), + mkU64(bitR ? 0x80000000ULL : 0ULL))); + putIRegA(rD, res, condT, Ijk_Boring); + DIP("smmla%s%s r%u, r%u, r%u, r%u\n", + nCC(INSN_COND), bitR ? "r" : "", rD, rN, rM, rA); + goto decode_success; + } + } + /* ------------------- NOP ------------------ */ if (0x0320F000 == (insn & 0x0FFFFFFF)) { DIP("nop%s\n", nCC(INSN_COND)); |