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| author | Ben Cheng <bccheng@google.com> | 2013-02-14 16:09:57 -0800 |
|---|---|---|
| committer | Ben Cheng <bccheng@google.com> | 2013-03-11 14:31:12 -0700 |
| commit | a552dd29ae5c8ce251cdf43da8f84902bbe0b7c9 (patch) | |
| tree | bf52442362c262e8a254c22c608879a3dff9080e | |
| parent | 14d4abff5b711f14716d6180c6f6ad26c344b726 (diff) | |
| download | valgrind-a552dd29ae5c8ce251cdf43da8f84902bbe0b7c9.tar.gz | |
Add support for ARM SMMLA instruction.
[cherry-picked from internal master]
Change-Id: Ic22af7fc6001b332416363a0b8a51f142f676e48
| -rw-r--r-- | main/VEX/priv/guest_arm_toIR.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/main/VEX/priv/guest_arm_toIR.c b/main/VEX/priv/guest_arm_toIR.c index 4c5cb9630..372c92796 100644 --- a/main/VEX/priv/guest_arm_toIR.c +++ b/main/VEX/priv/guest_arm_toIR.c @@ -18826,6 +18826,30 @@ DisResult disInstr_THUMB_WRK ( } } + /* ------------------- (T1) SMMLA{R} ------------------ */ + if (INSN0(15,7) == BITS9(1,1,1,1,1,0,1,1,0) + && INSN0(6,4) == BITS3(1,0,1) + && INSN1(7,5) == BITS3(0,0,0)) { + UInt bitR = INSN1(4,4); + UInt rA = INSN1(15,12); + UInt rD = INSN1(11,8); + UInt rM = INSN1(3,0); + UInt rN = INSN0(3,0); + if (!isBadRegT(rD) && !isBadRegT(rN) && !isBadRegT(rM) && (rA != 13)) { + IRExpr* res + = unop(Iop_64HIto32, + binop(Iop_Add64, + binop(Iop_Add64, + binop(Iop_32HLto64, getIRegT(rA), mkU32(0)), + binop(Iop_MullS32, getIRegT(rN), getIRegT(rM))), + mkU64(bitR ? 0x80000000ULL : 0ULL))); + putIRegT(rD, res, condT); + DIP("smmla%s r%u, r%u, r%u, r%u\n", + bitR ? "r" : "", rD, rN, rM, rA); + goto decode_success; + } + } + /* ----------------------------------------------------------- */ /* -- VFP (CP 10, CP 11) instructions (in Thumb mode) -- */ /* ----------------------------------------------------------- */ |