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| author | philippe <philippe@a5019735-40e9-0310-863c-91ae7b9d1cf9> | 2012-03-14 21:27:35 +0000 |
|---|---|---|
| committer | philippe <philippe@a5019735-40e9-0310-863c-91ae7b9d1cf9> | 2012-03-14 21:27:35 +0000 |
| commit | ede2d6c0a82a3faed1889fc73f42d3a4cd6352fc (patch) | |
| tree | 5ac7a387192d5b54d6302b89820f145ee7e96484 /coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml | |
| parent | 561b8324821735f82981026232ec649b362ec6e2 (diff) | |
| download | valgrind-ede2d6c0a82a3faed1889fc73f42d3a4cd6352fc.tar.gz | |
(for x86 and amd64): Change the type of the shadow regs for floating point registers
Similar to r12444 (see Log below), but this is doing it for x86 and amd64.
The xmm registers are using uint32 or uint64 for their float
union components. For the i387 80 bits float registers, as there is
no uint80, a struct uint16 + uint64 is defined.
Log:
Change the type of the shadow regs for floating point registers
to be uint64. Previously the value in such a shadow reg would
be interpreted by gdb as a floating point value which would
produce non-sensible output for e.g p/x $f1s1.
This patch covers the power and arm architectures.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12445 a5019735-40e9-0310-863c-91ae7b9d1cf9
Diffstat (limited to 'coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml')
| -rw-r--r-- | coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml b/coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml index 1a368c4ea..a650b1696 100644 --- a/coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml +++ b/coregrind/m_gdbserver/32bit-sse-valgrind-s1.xml @@ -7,15 +7,15 @@ <!DOCTYPE feature SYSTEM "gdb-target.dtd"> <feature name="org.gnu.gdb.i386.sse.valgrind.s1"> - <vector id="v4f" type="ieee_single" count="4"/> - <vector id="v2d" type="ieee_double" count="2"/> + <vector id="v4f_s" type="uint32" count="4"/> + <vector id="v2d_s" type="uint64" count="2"/> <vector id="v16i8" type="int8" count="16"/> <vector id="v8i16" type="int16" count="8"/> <vector id="v4i32" type="int32" count="4"/> <vector id="v2i64" type="int64" count="2"/> - <union id="vec128"> - <field name="v4_float" type="v4f"/> - <field name="v2_double" type="v2d"/> + <union id="vec128_s"> + <field name="v4_float" type="v4f_s"/> + <field name="v2_double" type="v2d_s"/> <field name="v16_int8" type="v16i8"/> <field name="v8_int16" type="v8i16"/> <field name="v4_int32" type="v4i32"/> @@ -39,14 +39,14 @@ <field name="FZ" start="15" end="15"/> </flags> - <reg name="xmm0s1" bitsize="128" type="vec128"/> - <reg name="xmm1s1" bitsize="128" type="vec128"/> - <reg name="xmm2s1" bitsize="128" type="vec128"/> - <reg name="xmm3s1" bitsize="128" type="vec128"/> - <reg name="xmm4s1" bitsize="128" type="vec128"/> - <reg name="xmm5s1" bitsize="128" type="vec128"/> - <reg name="xmm6s1" bitsize="128" type="vec128"/> - <reg name="xmm7s1" bitsize="128" type="vec128"/> + <reg name="xmm0s1" bitsize="128" type="vec128_s"/> + <reg name="xmm1s1" bitsize="128" type="vec128_s"/> + <reg name="xmm2s1" bitsize="128" type="vec128_s"/> + <reg name="xmm3s1" bitsize="128" type="vec128_s"/> + <reg name="xmm4s1" bitsize="128" type="vec128_s"/> + <reg name="xmm5s1" bitsize="128" type="vec128_s"/> + <reg name="xmm6s1" bitsize="128" type="vec128_s"/> + <reg name="xmm7s1" bitsize="128" type="vec128_s"/> <reg name="mxcsrs1" bitsize="32" type="i386_mxcsr" group="vector"/> </feature> |