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authorGert Wollny <gert.wollny@collabora.com>2022-11-08 17:29:48 +0100
committerMarge Bot <emma+marge@anholt.net>2022-11-10 07:03:02 +0000
commit546bf7011765ba5dea9f14f9251e291281e9dc25 (patch)
tree0ac02da54bc51af500b567e05b4abead3542d0be
parent02e204ff0df368b5a3b9812d7a9eda4a794d6841 (diff)
downloadvirglrenderer-546bf7011765ba5dea9f14f9251e291281e9dc25.tar.gz
proxy: Make sure we shift a 64 bit value
The shift parameter is the result of u_bit_scan64, so the shifted value should be 64 bit too. Fixes Coverity IDs: 1527225 "Unintentional integer overflow" 1527204 "Bad bit shift operation" Signed-off-by: Gert Wollny <gert.wollny@collabora.com> Part-of: <https://gitlab.freedesktop.org/virgl/virglrenderer/-/merge_requests/975>
-rw-r--r--src/proxy/proxy_context.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/proxy/proxy_context.c b/src/proxy/proxy_context.c
index f2a035b3..988c13bf 100644
--- a/src/proxy/proxy_context.c
+++ b/src/proxy/proxy_context.c
@@ -152,7 +152,7 @@ proxy_context_retire_fences_internal(struct proxy_context *ctx)
const uint32_t ring_idx = u_bit_scan64(&old_busy_mask);
const uint32_t cur_seqno = proxy_context_load_timeline_seqno(ctx, ring_idx);
if (!proxy_context_retire_timeline_fences_locked(ctx, ring_idx, cur_seqno))
- new_busy_mask |= 1 << ring_idx;
+ new_busy_mask |= 1ull << ring_idx;
}
ctx->timeline_busy_mask = new_busy_mask;
@@ -220,7 +220,7 @@ proxy_context_submit_fence(struct virgl_context *base,
mtx_lock(&ctx->timeline_mutex);
list_addtail(&fence->head, &timeline->fences);
- ctx->timeline_busy_mask |= 1 << ring_idx;
+ ctx->timeline_busy_mask |= 1ull << ring_idx;
if (proxy_renderer.flags & VIRGL_RENDERER_ASYNC_FENCE_CB)
mtx_unlock(&ctx->timeline_mutex);