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| author | Gert Wollny <gert.wollny@collabora.com> | 2022-11-08 13:54:33 +0100 |
|---|---|---|
| committer | Marge Bot <emma+marge@anholt.net> | 2022-11-10 07:03:02 +0000 |
| commit | 6c2feadeea1aad95dfc92f9cfec8f2e00c0a3e67 (patch) | |
| tree | 53c1432b2a3ae0c7c3c09f670ff83b32c23ca231 | |
| parent | 4e3258534d08be84cc8692a0aac0ea9b14f2c1fa (diff) | |
| download | virglrenderer-6c2feadeea1aad95dfc92f9cfec8f2e00c0a3e67.tar.gz | |
mesa/util: Limit scoop of local variable
Otherwise reg2 could theoretically be accesses without initialization.
Fixes Coverity ID: 1527231 "Uninitialized scalar variable"
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/virgl/virglrenderer/-/merge_requests/975>
| -rw-r--r-- | src/mesa/util/u_cpu_detect.c | 39 |
1 files changed, 21 insertions, 18 deletions
diff --git a/src/mesa/util/u_cpu_detect.c b/src/mesa/util/u_cpu_detect.c index 955d087b..d6e51a11 100644 --- a/src/mesa/util/u_cpu_detect.c +++ b/src/mesa/util/u_cpu_detect.c @@ -681,7 +681,6 @@ util_cpu_detect_once(void) #if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64) if (has_cpuid()) { uint32_t regs[4]; - uint32_t regs2[4]; util_cpu_caps.cacheline = 32; @@ -690,6 +689,7 @@ util_cpu_detect_once(void) if (regs[0] >= 0x00000001) { unsigned int cacheline; + uint32_t regs2[4]; cpuid (0x00000001, regs2); @@ -739,6 +739,24 @@ util_cpu_detect_once(void) cacheline = ((regs2[1] >> 8) & 0xFF) * 8; if (cacheline > 0) util_cpu_caps.cacheline = cacheline; + + // check for avx512 + if (((regs2[2] >> 27) & 1) && // OSXSAVE + (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS + ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS + uint32_t regs3[4]; + cpuid_count(0x00000007, 0x00000000, regs3); + util_cpu_caps.has_avx512f = (regs3[1] >> 16) & 1; + util_cpu_caps.has_avx512dq = (regs3[1] >> 17) & 1; + util_cpu_caps.has_avx512ifma = (regs3[1] >> 21) & 1; + util_cpu_caps.has_avx512pf = (regs3[1] >> 26) & 1; + util_cpu_caps.has_avx512er = (regs3[1] >> 27) & 1; + util_cpu_caps.has_avx512cd = (regs3[1] >> 28) & 1; + util_cpu_caps.has_avx512bw = (regs3[1] >> 30) & 1; + util_cpu_caps.has_avx512vl = (regs3[1] >> 31) & 1; + util_cpu_caps.has_avx512vbmi = (regs3[2] >> 1) & 1; + } + } if (util_cpu_caps.has_avx && regs[0] >= 0x00000007) { uint32_t regs7[4]; @@ -746,22 +764,6 @@ util_cpu_detect_once(void) util_cpu_caps.has_avx2 = (regs7[1] >> 5) & 1; } - // check for avx512 - if (((regs2[2] >> 27) & 1) && // OSXSAVE - (xgetbv() & (0x7 << 5)) && // OPMASK: upper-256 enabled by OS - ((xgetbv() & 6) == 6)) { // XMM/YMM enabled by OS - uint32_t regs3[4]; - cpuid_count(0x00000007, 0x00000000, regs3); - util_cpu_caps.has_avx512f = (regs3[1] >> 16) & 1; - util_cpu_caps.has_avx512dq = (regs3[1] >> 17) & 1; - util_cpu_caps.has_avx512ifma = (regs3[1] >> 21) & 1; - util_cpu_caps.has_avx512pf = (regs3[1] >> 26) & 1; - util_cpu_caps.has_avx512er = (regs3[1] >> 27) & 1; - util_cpu_caps.has_avx512cd = (regs3[1] >> 28) & 1; - util_cpu_caps.has_avx512bw = (regs3[1] >> 30) & 1; - util_cpu_caps.has_avx512vl = (regs3[1] >> 31) & 1; - util_cpu_caps.has_avx512vbmi = (regs3[2] >> 1) & 1; - } if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] == 0x49656e69) { /* GenuineIntel */ @@ -771,7 +773,7 @@ util_cpu_detect_once(void) cpuid(0x80000000, regs); if (regs[0] >= 0x80000001) { - + uint32_t regs2[4]; cpuid(0x80000001, regs2); util_cpu_caps.has_mmx |= (regs2[3] >> 23) & 1; @@ -784,6 +786,7 @@ util_cpu_detect_once(void) } if (regs[0] >= 0x80000006) { + uint32_t regs2[4]; /* should we really do this if the clflush size above worked? */ unsigned int cacheline; cpuid(0x80000006, regs2); |