Merge changes from topic "VIXL_UPDATE_11_20" am: c4b1310f4f am: 232c365e75 am: 8654da69be am: 3b80d11845

Original change: https://android-review.googlesource.com/c/platform/external/vixl/+/1492919

Change-Id: I3815defd1f90efea845fc40c186ee463b05b379a

108 files changed, 122864 insertions, 27015 deletions

diff --git a/.gitignore b/.gitignore
index 930e7535..78477d3b 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,5 +4,4 @@
 .sconsign.dblite
 log/
 obj/
-vixl_stats.csv
 tools/.cached_lint_results.pkl
diff --git a/README.md b/README.md
index 01ea26d8..57e94b7d 100644
--- a/README.md
+++ b/README.md
@@ -7,6 +7,7 @@ Contents:
  * Licence
  * Requirements
  * Known limitations
+ * Bug reports
  * Usage
 
 
@@ -43,7 +44,7 @@ To build VIXL the following software is required:
 
  1. Python 2.7
  2. SCons 2.0
- 3. GCC 4.8+ or Clang 3.4+
+ 3. GCC 4.8+ or Clang 4.0+
 
 A 64-bit host machine is required, implementing an LP64 data model. VIXL has
 been tested using GCC on AArch64 Debian, GCC and Clang on amd64 Ubuntu
@@ -54,13 +55,17 @@ software is also required:
 
  1. Git
  2. [Google's `cpplint.py`][cpplint]
- 3. clang-format-3.8
+ 3. clang-format-4.0
+ 4. clang-tidy-4.0
 
 Refer to the 'Usage' section for details.
 
+Note that in Ubuntu 18.04, clang-tidy-4.0 will only work if the clang-4.0
+package is also installed.
 
-Known Limitations for AArch64 code generation
-=============================================
+
+Known Limitations
+=================
 
 VIXL was developed for JavaScript engines so a number of features from A64 were
 deemed unnecessary:
@@ -79,11 +84,6 @@ builds and mostly works for 32-bit x86 platforms, there are a number of
 floating-point operations which do not work correctly, and a number of tests
 fail as a result.
 
-VIXL may not build using Clang 3.7, due to a compiler warning. A workaround is
-to disable conversion of warnings to errors, or to delete the offending
-`return` statement reported and rebuild. This problem will be fixed in the next
-release.
-
 Debug Builds
 ------------
 
@@ -125,6 +125,45 @@ Instructions affected by these limitations:
   `stlxrh`, `stlxr`, `ldaxrb`, `ldaxrh`, `ldaxr`, `stlxp`, `ldaxp`, `stlrb`,
   `stlrh`, `stlr`, `ldarb`, `ldarh`, `ldar`, `clrex`.
 
+Security Considerations
+-----------------------
+
+VIXL allows callers to generate any code they want. The generated code is
+arbitrary, and can therefore call back into any other component in the process.
+As with any self-modifying code, vulnerabilities in the client or in VIXL itself
+could lead to arbitrary code generation.
+
+For performance reasons, VIXL's Assembler only performs debug-mode checking of
+instruction operands (such as immediate field encodability). This can minimise
+code-generation overheads for advanced compilers that already model instructions
+accurately, and might consider the Assembler's checks to be redundant. The
+Assembler should only be used directly where encodability is independently
+checked, and where fine control over all generated code is required.
+
+The MacroAssembler synthesises multiple-instruction sequences to support _some_
+unencodable operand combinations. The MacroAssembler can provide a useful safety
+check in cases where the Assembler's precision is not required; an unexpected
+unencodable operand should result in a macro with the correct behaviour, rather
+than an invalid instruction.
+
+In general, the MacroAssembler handles operands which are likely to vary with
+user-supplied data, but does not usually handle inputs which are likely to be
+easily covered by tests. For example, move-immediate arguments are likely to be
+data-dependent, but register types (e.g. `x` vs `w`) are not.
+
+We recommend that _all_ users use the MacroAssembler, using `ExactAssemblyScope`
+to invoke the Assembler when specific instruction sequences are required. This
+approach is recommended even in cases where a compiler can model the
+instructions precisely, because, subject to the limitations described above, it
+offers an additional layer of protection against logic bugs in instruction
+selection.
+
+Bug reports
+===========
+
+Bug reports may be sent to vixl@arm.com. Please provide any steps required to
+recreate a bug, along with build environment and host system information.
+
 
 Usage
 =====
@@ -151,9 +190,10 @@ It is possible to tell `tools/test.py` to skip the linter stage by passing
 `--nolint`. This removes the dependency on `cpplint.py` and Git. The `--nolint`
 option is implied if the VIXL project is a snapshot (with no `.git` directory).
 
-Additionally, `tools/test.py` tests code formatting using `clang-format-3.8`.
-If you don't have `clang-format-3.8`, disable the test using the
-`--noclang-format` option.
+Additionally, `tools/test.py` tests code formatting using `clang-format-4.0`,
+and performs static analysis using `clang-tidy-4.0`. If you don't have these
+tools, disable the test using `--noclang-format` or `--noclang-tidy`,
+respectively.
 
 Also note that the tests for the tracing features depend upon external `diff`
 and `sed` tools. If these tools are not available in `PATH`, these tests will
diff --git a/SConstruct b/SConstruct
index 8e1b1a73..6c1f5638 100644
--- a/SConstruct
+++ b/SConstruct
@@ -207,6 +207,19 @@ def DefaultVariable(name, help, allowed_values):
   return (name, help, default_value, validator)
 
 
+def SortListVariable(iterator):
+  # Previously this code relied on the order of items in a list
+  # converted from a set. However in Python 3 the order changes each run.
+  # Here we do a custom partial sort to ensure that the build directory
+  # name is stable, the same across Python 2 and 3, and the same as the
+  # old code.
+  result = list(sorted(iterator))
+  result = sorted(result, key=lambda x: x == 't32', reverse=True)
+  result = sorted(result, key=lambda x: x == 'a32', reverse=True)
+  result = sorted(result, key=lambda x: x == 'a64', reverse=True)
+  return result
+
+
 def AliasedListVariable(name, help, default_value, allowed_values, aliasing):
   help = '%s (all|auto|comma-separated list) (any combination from [%s])' % \
          (help, ', '.join(allowed_values))
@@ -222,10 +235,10 @@ def AliasedListVariable(name, help, default_value, allowed_values, aliasing):
     if value == 'auto': return []
     if value == 'all':
       translated = [aliasing[v] for v in allowed_values]
-      return list(set(itertools.chain.from_iterable(translated)))
+      return SortListVariable(itertools.chain.from_iterable(translated))
     # The validator is run later hence the get.
     translated = [aliasing.get(v, v) for v in value.split(',')]
-    return list(set(itertools.chain.from_iterable(translated)))
+    return SortListVariable(itertools.chain.from_iterable(translated))
 
   return (name, help, default_value, validator, converter)
 
@@ -251,8 +264,10 @@ vars.AddVariables(
     DefaultVariable('code_buffer_allocator',
                     'Configure the allocation mechanism in the CodeBuffer',
                     ['malloc', 'mmap']),
-    ('std', 'C++ standard. The standards tested are: %s.' % \
-                                         ', '.join(config.tested_cpp_standards)),
+    ('std',
+     'C++ standard. The standards tested are: %s.' % \
+     ', '.join(config.tested_cpp_standards),
+     config.tested_cpp_standards[0]),
     ('compiler_wrapper', 'Command to prefix to the C and C++ compiler (e.g ccache)', '')
     )
 
@@ -292,9 +307,9 @@ def target_handler(env):
   if Is32BitHost(env):
     # We use list(set(...)) to keep the same order as if it was specify as
     # an option.
-    env['target'] = list(set(['a32', 't32']))
+    env['target'] = SortListVariable(['a32', 't32'])
   else:
-    env['target'] = list(set(['a64', 'a32', 't32']))
+    env['target'] = SortListVariable(['a64', 'a32', 't32'])
 
 
 def target_validator(env):
@@ -381,21 +396,12 @@ def ConfigureEnvironmentForCompiler(env):
   if env['negative_testing'] == 'on' and env['mode'] == 'debug' \
       and compiler >= 'gcc-6':
     env.Append(CPPFLAGS = ['-Wno-terminate'])
-    # The C++11 compatibility warning will also be triggered for this case, as
-    # the behavior of throwing from desctructors has changed.
-    if 'std' in env and env['std'] == 'c++98':
-      env.Append(CPPFLAGS = ['-Wno-c++11-compat'])
-
-  # When compiling with c++98 (the default), allow long long constants.
-  if 'std' not in env or env['std'] == 'c++98':
-    env.Append(CPPFLAGS = ['-Wno-long-long'])
-    env.Append(CPPFLAGS = ['-Wno-variadic-macros'])
-  # When compiling with c++11, suggest missing override keywords on methods.
-  if 'std' in env and env['std'] in ['c++11', 'c++14']:
-    if compiler >= 'gcc-5':
-      env.Append(CPPFLAGS = ['-Wsuggest-override'])
-    elif compiler >= 'clang-3.6':
-      env.Append(CPPFLAGS = ['-Winconsistent-missing-override'])
+
+  # Suggest missing override keywords on methods.
+  if compiler >= 'gcc-5':
+    env.Append(CPPFLAGS = ['-Wsuggest-override'])
+  elif compiler >= 'clang-3.6':
+    env.Append(CPPFLAGS = ['-Winconsistent-missing-override'])
 
 
 def ConfigureEnvironment(env):
@@ -459,11 +465,11 @@ env = Environment(variables = vars,
 # Abort the build if any command line option is unknown or invalid.
 unknown_build_options = vars.UnknownVariables()
 if unknown_build_options:
-  print 'Unknown build options:',  unknown_build_options.keys()
+  print('Unknown build options: ' + str(unknown_build_options.keys()))
   Exit(1)
 
 if env['negative_testing'] == 'on' and env['mode'] != 'debug':
-  print 'negative_testing only works in debug mode'
+  print('negative_testing only works in debug mode')
   Exit(1)
 
 ConfigureEnvironment(env)
diff --git a/doc/aarch64/topics/state-trace.md b/doc/aarch64/topics/state-trace.md
new file mode 100644
index 00000000..4d37af11
--- /dev/null
+++ b/doc/aarch64/topics/state-trace.md
@@ -0,0 +1,231 @@
+AArch64 Simulator state trace
+=============================
+
+The AArch64 Simulator can be configured to produce traces of instruction
+execution, register contents, and memory accesses. The trace is designed to be
+intuitive for human readers, but this document describes the format of the
+trace, so that post-processing tools can confidently parse the output.
+
+In VIXL's own test runner, the trace is controlled by the `--trace*` options.
+Run `test-runner --help` for details.
+
+Basic structure
+---------------
+
+Executed instructions show the address, the encoding of the instruction and the
+disassembly (as produced by VIXL's Disassembler). For example:
+
+    0x00007fbe2a6a9044  d299d200		mov x0, #0xce90
+
+The first field is the address of the instruction, with exactly 16 hexadecimal
+characters and a leading 0x, and is followed by two spaces. The second field is
+the instruction encoding, with exactly eight hexadecimal characters (and no
+leading 0x). This is followed by two _tab_ characters, and the instruction
+disassembly. The following regular expression can be used to capture each field:
+
+    (0x[0-9a-f]{16})  ([0-9a-f]{8})\t\t(.*)
+
+Following each instruction are zero or more lines of state update. Most notably,
+these represent the register state updates and memory accesses that occurred
+during simulation of the instruction. All of these lines begin with a '#'
+character, so that they can be easily identified, and filtered if necessary. For
+example:
+
+    0x00007fd2221c907c  8b82200e		add x14, x0, x2, asr #8
+    #            x14: 0xfffedcba98765432
+    0x00007fd2221c9080  0b81200f		add w15, w0, w1, asr #8
+    #            w15:         0xff89abcd
+
+Note that the Simulator uses these state update lines to describe its initial
+state. As a result, there will be state trace output before the first simulated
+instruction, and parsers need to be tolerant of this.
+
+Note that padding white space is used liberally to keep values vertically
+aligned throughout the trace (as shown with the write to `w15` in the example
+above). Similarly, some compound values are split into parts using the C++14
+literal separator (`'`) character. Refer to the "Memory accesses" section
+(below) for examples.
+
+Ordering
+--------
+
+VIXL guarantees that each instruction is printed before its associated state
+trace.
+
+State trace must be interpreted sequentially, line by line. VIXL avoids updating
+the same register more than once (because it makes the trace hard for humans to
+read), but this can occur in some situations, and should be supported by
+parsers.
+
+The state is intended to be consistent with architectural execution at the start
+of each instruction and at the end of the whole trace, but no such guarantees
+are made about the traced state _between_ instructions. VIXL prioritises
+human-readability when choosing the ordering of state updates.
+
+If simulated registers are modified externally, for example using
+`WriteRegister` from C++ code, their state will (by default) be logged
+immediately. In the full trace, it will appear as though the (runtime) call or
+return instruction modified the state. This is consistent with the guarantees
+above, but it can result in single instructions appearing to generate a large
+number of state updates.
+
+There is no upper limit on the number of state update lines that any one
+instruction can generate.
+
+Whole register trace
+--------------------
+
+The simplest form of state trace has the form "`REG: VALUE`", meaning that
+the register `REG` has the specified value, and any high-order bits in aliased
+registers are set to zero.
+
+    0x00007fd2221c907c  8b82200e		add x14, x0, x2, asr #8
+    #            x14: 0xfffedcba98765432
+
+Note that to correctly track state, parsers need to be aware of architectural
+register aliasing rules. Also, VIXL uses some standard register aliases, such as
+`lr` (`x30`). To avoid misinterpreting a register alias (and thereby potentially
+missing an aliased register update), some tools may need to treat an
+unrecognised register name as an error.
+
+This trace format attempts to represent _architectural_ register writes.
+However, this is not strictly checked or enforced.
+
+`VALUE` is always shown in hexadecimal (raw bits) form, with a leading `0x` and
+enough digits to exactly fill `REG`. `VALUE` may also include annotations (for
+example to show FP arithmetic values) in parentheses. These annotations are for
+the benefit of human readers, and parsers may ignore them.
+
+Note that SVE registers _always_ use the partial register trace format,
+described below, so a plain `z` or `p` register will never be used in a whole
+register trace. This is true even if the vector length is configured to 16
+bytes.
+
+Partial register trace
+----------------------
+
+Sometimes, VIXL needs to show _part_ of a register without implying that the
+rest of the register is zeroed. A partial register value is indicated by a bit
+range in angled brackets after the register name: "`REG<MSB:LSB>: VALUE`".
+This format is used for stores, for example.
+
+SVE register updates are split across multiple lines, and therefore always use
+the partial register trace format. For example (with a 384-bit VL):
+
+    0x00007fb1978da044  04214000		index z0.b, #0, #1
+    #   z0<383:256>: 0x2f2e2d2c2b2a29282726252423222120
+    #   z0<255:128>: 0x1f1e1d1c1b1a19181716151413121110
+    #     z0<127:0>: 0x0f0e0d0c0b0a09080706050403020100
+
+Note that VIXL will omit whole lines where they are unnecessary, for example if
+they have no active (predicated) lanes. Parsers should not assume that every
+part of a register will appear in such cases.
+
+The `VALUE` has the same format as in the whole register trace, except in the
+case of SVE `p` registers (as described below).
+
+SVE `p` registers
+-----------------
+
+For `p` registers, we try to keep the lanes vertically aligned with the
+corresponding parts of the `z` registers that they affect. To do this, we use a
+binary format, with a leading `0b`, and spaces between each digit. For example:
+
+    0x00007f66e539b0b8  04f54607		index z7.d, x16, #-11
+    #     z7<127:0>: 0x00000000000000150000000000000020
+    0x00007f66e539b0bc  25d8e3a7		ptrue p7.d, all
+    #      p7<15:0>: 0b 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
+
+Memory accesses
+---------------
+
+The pattern for a memory access is "`VALUE OP ADDRESS`", where:
+
+- `VALUE` is a hexadecimal value, with visual separators (') between
+  structure components,
+- `OP` is `"->"` for a store, or `"<-"` for a load,
+- `ADDRESS` is the (hexadecimal) address of the access.
+
+Accesses shown in this style are always contiguous, and with little-endian
+semantics. However, a given instruction might have multiple lines of memory
+access trace, particularly if the instruction performs non-contiguous accesses.
+
+In the case of simple accesses, the `VALUE` is shared with register value trace:
+
+    0x00007f3835372058  e400e401		st1b { z1.b }, p1, [x0]
+    #      z1<127:0>: 0xd4d7dadde0e3e6e9eceff2f5f8fbfe01 -> 0x000055d170298e90
+
+Sign-extending loads show the whole resulting register value, with the (smaller)
+access represented on a separate line. This makes the (differing) values in the
+register and in memory unambiguous, without parsers needing to understand the
+instruction set:
+
+    0x00007f47922d0068  79800306		ldrsh x6, [x24]
+    #             x6: 0xffffffffffff8080
+    #                                  ╙─ 0x8080 <- 0x00007fffbc197708
+
+Some instructions access several different memory locations. In these cases,
+each access is given its own line, with the highest lane index first so that
+(for contiguous accesses) the lowest address ends up at the bottom:
+
+    0x00007fa6001e9060  e4217c0a		st2b { z10.b, z11.b }, p7, [x0, x1]
+    #     z10<127:0>: 0x0f0e0d0c0b0a09080706050403020100
+    #     z11<127:0>: 0x1f1e1d1c1b1a19181716151413121110
+    #                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x10'00 -> 0x00007ffe485d2f90
+    #                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x11'01 -> 0x00007ffe485d2f92
+    #                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x12'02 -> 0x00007ffe485d2f94
+    #                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x13'03 -> 0x00007ffe485d2f96
+    #                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x14'04 -> 0x00007ffe485d2f98
+    #                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x15'05 -> 0x00007ffe485d2f9a
+    #                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x16'06 -> 0x00007ffe485d2f9c
+    #                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17'07 -> 0x00007ffe485d2f9e
+    #                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18'08 -> 0x00007ffe485d2fa0
+    #                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19'09 -> 0x00007ffe485d2fa2
+    #                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a'0a -> 0x00007ffe485d2fa4
+    #                    ║ ║ ║ ║ ╙─────────────────────── 0x1b'0b -> 0x00007ffe485d2fa6
+    #                    ║ ║ ║ ╙───────────────────────── 0x1c'0c -> 0x00007ffe485d2fa8
+    #                    ║ ║ ╙─────────────────────────── 0x1d'0d -> 0x00007ffe485d2faa
+    #                    ║ ╙───────────────────────────── 0x1e'0e -> 0x00007ffe485d2fac
+    #                    ╙─────────────────────────────── 0x1f'0f -> 0x00007ffe485d2fae
+
+The line-drawing characters are encoded as UTF-8 (as is this document). There is
+currently no locale handling in VIXL, so this is not configurable. However,
+since these annotations are for the benefit of human readers, parsers can safely
+ignore them, and treat the whole trace as an ASCII byte stream (ignoring 8-bit
+characters). This is useful in situations where UTF-8 handling carries an
+unacceptable performance cost.
+
+In the future, VIXL may offer an option to avoid printing these annotations, so
+that the trace is restricted to single-byte characters.
+
+Floating-point value annotations
+--------------------------------
+
+Some floating-point operations produce register trace that annotates the raw
+values with the corresponding FP arithmetic values. This is for the benefit of
+human readers (and has limited precision). Such annotations follow the `VALUE`
+in parentheses.
+
+Scalar form:
+
+    #             s1:                         0x3f800000 (1.000) <- 0x00007ffdc64d2314
+
+Vector form, updating all S lanes using a load:
+
+    #            v16: 0x1211100f0e0d0c0b0a09080706050403 (4.577e-28, 1.739e-30, 6.598e-33, 2.502e-35)
+    #                          ║       ║       ║       ╙─ 0x06050403 <- 0x00007ffe56fd7863
+    #                          ║       ║       ╙───────── 0x0a090807 <- 0x00007ffe56fd7867
+    #                          ║       ╙───────────────── 0x0e0d0c0b <- 0x00007ffe56fd786b
+    #                          ╙───────────────────────── 0x1211100f <- 0x00007ffe56fd786f
+
+Vector form, updating a single S lane using a load:
+
+    #             v2: 0x03020100040302017ff0f0027f80f000 (..., 1.540e-36, ...)
+    #                                  ╙───────────────── 0x04030201 <- 0x00007ffc7b2e3ca1
+
+Vector form, replicating a single struct load to all S lanes:
+
+    #            v15: 0x100f0e0d100f0e0d100f0e0d100f0e0d (2.821e-29, 2.821e-29, 2.821e-29, 2.821e-29)
+    #            v16: 0x14131211141312111413121114131211 (7.425e-27, 7.425e-27, 7.425e-27, 7.425e-27)
+    #            v17: 0x18171615181716151817161518171615 (1.953e-24, 1.953e-24, 1.953e-24, 1.953e-24)
+    #                          ╙───────╨───────╨───────╨─ 0x18171615'14131211'100f0e0d <- 0x00007ffdd64d847d
diff --git a/examples/aarch32/getting-started.cc b/examples/aarch32/getting-started.cc
index 35fcbf5b..a4ab3f83 100644
--- a/examples/aarch32/getting-started.cc
+++ b/examples/aarch32/getting-started.cc
@@ -60,8 +60,10 @@ int main() {
   uint32_t code_size = masm.GetSizeOfCodeGenerated();
   ExecutableMemory memory(code, code_size);
   // Run the example function.
-  uint32_t (*demo_function)(uint32_t) = memory.GetEntryPoint<uint32_t (*)(
-      uint32_t)>(demo, masm.GetInstructionSetInUse());
+  uint32_t (*demo_function)(uint32_t) =
+      memory
+          .GetEntryPoint<uint32_t (*)(uint32_t)>(demo,
+                                                 masm.GetInstructionSetInUse());
   uint32_t input_value = 0x89abcdef;
   uint32_t output_value = (*demo_function)(input_value);
   printf("native: demo(0x%08x) = 0x%08x\n", input_value, output_value);
diff --git a/examples/aarch64/add2-vectors.cc b/examples/aarch64/add2-vectors.cc
index 2ca109a1..85fc5c71 100644
--- a/examples/aarch64/add2-vectors.cc
+++ b/examples/aarch64/add2-vectors.cc
@@ -38,12 +38,12 @@ using namespace vixl::aarch64;
  * and returns the results in the first vector.
  */
 void GenerateAdd2Vectors(MacroAssembler* masm) {
-  // void add2_vectors(uint8_t *vec*, const uint8_t *vecB, unsigned size)
+  // void add2_vectors(uint8_t *vec_a, const uint8_t *vec_b, unsigned size)
   // Argument locations:
-  //    vecA (pointer) -> x0
-  //    vecB (pointer) -> x1
+  //    vec_a (pointer) -> x0
+  //    vec_b (pointer) -> x1
   //    size (integer) -> w2
-  // Result returned in vecA.
+  // Result returned in vec_a.
 
   Label loop16, loopr, end;
 
@@ -109,48 +109,48 @@ int main(void) {
 
   // Initialize input data for the example function.
   // clang-format: off
-  uint8_t vecA[] = {0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12,
-                    13, 14, 15, 0,  1,  2,  3,  4,  5,  6,  7,  8,  9,
-                    10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20};
-  uint8_t vecB[] = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
-                    29, 30, 31, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
-                    26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36};
+  uint8_t vec_a[] = {0,  1,  2,  3,  4,  5,  6,  7,  8,  9,  10, 11, 12,
+                     13, 14, 15, 0,  1,  2,  3,  4,  5,  6,  7,  8,  9,
+                     10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20};
+  uint8_t vec_b[] = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28,
+                     29, 30, 31, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25,
+                     26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36};
   // clang-format on
-  uint8_t vecC[ARRAY_SIZE(vecA)];
+  uint8_t vec_c[ARRAY_SIZE(vec_a)];
 
   // Check whether the number of elements in both vectors match.
-  VIXL_CHECK(ARRAY_SIZE(vecA) == ARRAY_SIZE(vecB));
+  VIXL_CHECK(ARRAY_SIZE(vec_a) == ARRAY_SIZE(vec_b));
 
   // Compute the result in C.
-  for (unsigned i = 0; i < ARRAY_SIZE(vecA); i++) {
-    vecC[i] = vecA[i] + vecB[i];
+  for (unsigned i = 0; i < ARRAY_SIZE(vec_a); i++) {
+    vec_c[i] = vec_a[i] + vec_b[i];
   }
 
 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
-  uintptr_t vecA_addr = reinterpret_cast<uintptr_t>(vecA);
-  uintptr_t vecB_addr = reinterpret_cast<uintptr_t>(vecB);
+  uintptr_t vec_a_addr = reinterpret_cast<uintptr_t>(vec_a);
+  uintptr_t vec_b_addr = reinterpret_cast<uintptr_t>(vec_b);
 
   // Configure register environment in the simulator.
   Decoder decoder;
   Simulator simulator(&decoder);
-  simulator.WriteXRegister(0, vecA_addr);
-  simulator.WriteXRegister(1, vecB_addr);
-  simulator.WriteXRegister(2, ARRAY_SIZE(vecA));
-  PrintVector(vecA, ARRAY_SIZE(vecA));
+  simulator.WriteXRegister(0, vec_a_addr);
+  simulator.WriteXRegister(1, vec_b_addr);
+  simulator.WriteXRegister(2, ARRAY_SIZE(vec_a));
+  PrintVector(vec_a, ARRAY_SIZE(vec_a));
   printf(" +\n");
-  PrintVector(vecB, ARRAY_SIZE(vecB));
+  PrintVector(vec_b, ARRAY_SIZE(vec_b));
 
   // Run the example function in the simulator.
   simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&add2_vectors));
   printf(" =\n");
-  PrintVector(vecA, ARRAY_SIZE(vecA));
+  PrintVector(vec_a, ARRAY_SIZE(vec_a));
 
   // Check that the computed value in NEON matches the C version.
-  for (unsigned i = 0; i < ARRAY_SIZE(vecA); i++) {
-    VIXL_CHECK(vecC[i] == vecA[i]);
+  for (unsigned i = 0; i < ARRAY_SIZE(vec_a); i++) {
+    VIXL_CHECK(vec_c[i] == vec_a[i]);
   }
 #else
-  USE(vecC);
+  USE(vec_c);
 
   // Placeholder to run test natively.
   printf("Running tests natively is not supported yet.\n");
diff --git a/examples/aarch64/cpu-features.cc b/examples/aarch64/cpu-features.cc
new file mode 100644
index 00000000..74ddc986
--- /dev/null
+++ b/examples/aarch64/cpu-features.cc
@@ -0,0 +1,53 @@
+// Copyright 2020, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "examples.h"
+
+using namespace vixl;
+using namespace vixl::aarch64;
+
+// Demonstrate the use of VIXL's CPU feature detection, printing the features
+// that VIXL detects.
+
+#ifndef TEST_EXAMPLES
+int main() {
+  // Simple native deployments should initialise CPU features using
+  // `InferFromOS()`. If not on an AArch64 host, this returns nothing.
+  std::cout << "==== CPUFeatures::InferFromOS() ====\n";
+  std::cout << CPUFeatures::InferFromOS() << "\n";
+
+  // VIXL assumes support for FP, NEON and CRC32 by default. These features were
+  // implemented before the CPUFeatures mechanism.
+  std::cout << "==== CPUFeatures::AArch64LegacyBaseline() ====\n";
+  std::cout << CPUFeatures::AArch64LegacyBaseline() << "\n";
+
+  // Retrieve a list of all supported CPU features.
+  std::cout << "==== CPUFeatures::All() ====\n";
+  std::cout << CPUFeatures::All() << "\n";
+
+  return 0;
+}
+#endif
diff --git a/examples/aarch64/crc-checksums.cc b/examples/aarch64/crc-checksums.cc
index d997f6d8..38a56419 100644
--- a/examples/aarch64/crc-checksums.cc
+++ b/examples/aarch64/crc-checksums.cc
@@ -68,7 +68,7 @@ void GenerateCrc32(MacroAssembler* masm) {
 
 #ifndef TEST_EXAMPLES
 
-void runExample(const char* msg) {
+void RunExample(const char* msg) {
   MacroAssembler masm;
 
   // Generate the code for the example function.
@@ -96,10 +96,10 @@ void runExample(const char* msg) {
 
 
 int main(void) {
-  runExample("Hello World!");
-  runExample("do");
-  runExample("1");
-  runExample("");
+  RunExample("Hello World!");
+  RunExample("do");
+  RunExample("1");
+  RunExample("");
 
   return 0;
 }
diff --git a/examples/aarch64/disasm.cc b/examples/aarch64/disasm.cc
new file mode 100644
index 00000000..1c580270
--- /dev/null
+++ b/examples/aarch64/disasm.cc
@@ -0,0 +1,134 @@
+// Copyright 2020, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "code-buffer-vixl.h"
+#include "aarch64/decoder-aarch64.h"
+#include "aarch64/disasm-aarch64.h"
+
+// This example is interactive, and isn't tested systematically.
+#ifndef TEST_EXAMPLES
+
+using namespace vixl;
+using namespace vixl::aarch64;
+
+void PrintUsage(char const* name) {
+  printf("Usage: %s [OPTION]... <INSTRUCTION>...\n", name);
+  printf("\n");
+  printf("Disassemble ad-hoc A64 instructions.\n");
+  printf("\n");
+  printf(
+      "Options:\n"
+      "  --start-at <address>\n"
+      "    Start disassembling from <address> Any signed 64-bit value\n"
+      "    accepted by strtoll can be specified. The address is printed\n"
+      "    alongside each instruction, and it is also used to decode\n"
+      "    PC-relative offsets.\n"
+      "\n"
+      "    Defaults to 0.\n"
+      "\n");
+  printf(
+      "<instruction>\n"
+      "  A hexadecimal representation of an A64 instruction. The leading '0x'\n"
+      "  (or '0X') is optional.\n"
+      "\n"
+      "  Multiple instructions can be provided; they will be disassembled as\n"
+      "  if they were read sequentially from memory.\n"
+      "\n");
+  printf("Examples:\n");
+  printf("  $ %s d2824685\n", name);
+  printf("   0x0000000000000000:  d2824685  movz x5, #0x1234\n");
+  printf("\n");
+  printf("  $ %s --start-at -4 0x10fffe85 0xd61f00a0\n", name);
+  printf("  -0x0000000000000004:  10fffe85  adr x5, #-0x30 (addr -0x34)\n");
+  printf("   0x0000000000000000:  d61f00a0  br x5\n");
+}
+
+Instr ParseInstr(char const* arg) {
+  // TODO: Error handling for out-of-range inputs.
+  return (Instr)strtoul(arg, NULL, 16);
+}
+
+int64_t ParseInt64(char const* arg) {
+  // TODO: Error handling for out-of-range inputs.
+  return (int64_t)strtoll(arg, NULL, 0);
+}
+
+int main(int argc, char* argv[]) {
+  for (int i = 1; i < argc; i++) {
+    char const* arg = argv[i];
+    if ((strcmp(arg, "--help") == 0) || (strcmp(arg, "-h") == 0)) {
+      PrintUsage(argv[0]);
+      return 0;
+    }
+  }
+
+  // Assume an address of 0, unless otherwise specified.
+  int64_t start_address = 0;
+  // Allocate space for one instruction per argument.
+  CodeBuffer buffer((argc - 1) * kInstructionSize);
+
+  bool expect_start_at = false;
+  for (int i = 1; i < argc; i++) {
+    char* arg = argv[i];
+    if (expect_start_at) {
+      start_address = ParseInt64(arg);
+      expect_start_at = false;
+    } else if (strcmp(arg, "--start-at") == 0) {
+      expect_start_at = true;
+    } else {
+      // Assume that everything else is an instruction.
+      buffer.Emit(ParseInstr(arg));
+    }
+  }
+  buffer.SetClean();
+
+  if (expect_start_at) {
+    printf("No address given. Use: --start-at <address>\n");
+    return 1;
+  }
+
+  if (buffer.GetSizeInBytes() == 0) {
+    printf("Nothing to disassemble.\n");
+    return 0;
+  }
+
+  // Disassemble the buffer.
+  const Instruction* start = buffer.GetStartAddress<Instruction*>();
+  const Instruction* end = buffer.GetEndAddress<Instruction*>();
+  vixl::aarch64::PrintDisassembler disasm(stdout);
+  disasm.PrintSignedAddresses(true);
+  disasm.MapCodeAddress(start_address, start);
+  disasm.DisassembleBuffer(start, end);
+
+  return 0;
+}
+
+#endif  // TEST_EXAMPLES
diff --git a/examples/aarch64/examples.h b/examples/aarch64/examples.h
index 1292e812..ca1f3cc2 100644
--- a/examples/aarch64/examples.h
+++ b/examples/aarch64/examples.h
@@ -49,9 +49,9 @@ void GenerateFactorialRec(vixl::aarch64::MacroAssembler* masm);
 void GenerateNEONMatrixMultiply(vixl::aarch64::MacroAssembler* masm);
 
 // Generate a function with the following prototype:
-//   void add2_vectors(int8_t *vecA, const int8_t *vecB, unsigned size)
+//   void add2_vectors(int8_t *vec_a, const int8_t *vec_b, unsigned size)
 //
-// Demonstrate how to add two vectors using NEON. The result is stored in vecA.
+// Demonstrate how to add two vectors using NEON. The result is stored in vec_a.
 void GenerateAdd2Vectors(vixl::aarch64::MacroAssembler* masm);
 
 // Generate a function with the following prototype:
@@ -119,4 +119,10 @@ int64_t LiteralExample(int64_t a, int64_t b);
 // Generate a few examples of runtime calls.
 void GenerateRuntimeCallExamples(vixl::aarch64::MacroAssembler* masm);
 
+// Generate a function with the following prototype:
+//    size_t sve_strlen(const char* str);
+//
+// The function implements the standard `strlen` using SVE.
+void GenerateSVEStrlen(vixl::aarch64::MacroAssembler* masm);
+
 #endif  // VIXL_EXAMPLE_EXAMPLES_H_
diff --git a/examples/aarch64/non-const-visitor.h b/examples/aarch64/non-const-visitor.h
index 81c0c9c7..243cc156 100644
--- a/examples/aarch64/non-const-visitor.h
+++ b/examples/aarch64/non-const-visitor.h
@@ -30,109 +30,17 @@
 #include "aarch64/decoder-aarch64.h"
 #include "aarch64/macro-assembler-aarch64.h"
 
-class SwitchAddSubRegisterSources : public vixl::aarch64::DecoderVisitor {
+class SwitchAddSubRegisterSources
+    : public vixl::aarch64::DecoderVisitorWithDefaults {
  public:
   SwitchAddSubRegisterSources()
-      : vixl::aarch64::DecoderVisitor(kNonConstVisitor) {}
+      : vixl::aarch64::DecoderVisitorWithDefaults(kNonConstVisitor) {}
 
   // Our visitor switches the register sources for some add and sub instructions
-  // (not all add and sub instructions). Visitors are listed by the macro
-  // `VISITOR_LIST` in aarch64/decoder-aarch64.h.
+  // (not all add and sub instructions).
 
   virtual void VisitAddSubShifted(const vixl::aarch64::Instruction* instr)
       VIXL_OVERRIDE;
-
-// Define the remaining visitors to do nothing.
-#define UNUSED_VISITOR_LIST(V)          \
-  V(PCRelAddressing)                    \
-  V(AddSubImmediate)                    \
-  V(LogicalImmediate)                   \
-  V(MoveWideImmediate)                  \
-  V(Bitfield)                           \
-  V(Extract)                            \
-  V(UnconditionalBranch)                \
-  V(UnconditionalBranchToRegister)      \
-  V(CompareBranch)                      \
-  V(TestBranch)                         \
-  V(ConditionalBranch)                  \
-  V(System)                             \
-  V(Exception)                          \
-  V(RotateRightIntoFlags)               \
-  V(EvaluateIntoFlags)                  \
-  V(LoadStorePAC)                       \
-  V(LoadStorePairPostIndex)             \
-  V(LoadStorePairOffset)                \
-  V(LoadStorePairPreIndex)              \
-  V(LoadStorePairNonTemporal)           \
-  V(LoadStoreRCpcUnscaledOffset)        \
-  V(LoadLiteral)                        \
-  V(LoadStoreUnscaledOffset)            \
-  V(LoadStorePostIndex)                 \
-  V(LoadStorePreIndex)                  \
-  V(LoadStoreRegisterOffset)            \
-  V(LoadStoreUnsignedOffset)            \
-  V(LoadStoreExclusive)                 \
-  V(AtomicMemory)                       \
-  V(LogicalShifted)                     \
-  V(AddSubExtended)                     \
-  V(AddSubWithCarry)                    \
-  V(ConditionalCompareRegister)         \
-  V(ConditionalCompareImmediate)        \
-  V(ConditionalSelect)                  \
-  V(DataProcessing1Source)              \
-  V(DataProcessing2Source)              \
-  V(DataProcessing3Source)              \
-  V(FPCompare)                          \
-  V(FPConditionalCompare)               \
-  V(FPConditionalSelect)                \
-  V(FPImmediate)                        \
-  V(FPDataProcessing1Source)            \
-  V(FPDataProcessing2Source)            \
-  V(FPDataProcessing3Source)            \
-  V(FPIntegerConvert)                   \
-  V(FPFixedPointConvert)                \
-  V(Crypto2RegSHA)                      \
-  V(Crypto3RegSHA)                      \
-  V(CryptoAES)                          \
-  V(NEON2RegMisc)                       \
-  V(NEON2RegMiscFP16)                   \
-  V(NEON3Different)                     \
-  V(NEON3Same)                          \
-  V(NEON3SameFP16)                      \
-  V(NEONAcrossLanes)                    \
-  V(NEONByIndexedElement)               \
-  V(NEONCopy)                           \
-  V(NEONExtract)                        \
-  V(NEONLoadStoreMultiStruct)           \
-  V(NEONLoadStoreMultiStructPostIndex)  \
-  V(NEONLoadStoreSingleStruct)          \
-  V(NEONLoadStoreSingleStructPostIndex) \
-  V(NEONModifiedImmediate)              \
-  V(NEONScalar2RegMisc)                 \
-  V(NEONScalar2RegMiscFP16)             \
-  V(NEONScalar3Diff)                    \
-  V(NEONScalar3Same)                    \
-  V(NEONScalar3SameFP16)                \
-  V(NEONScalar3SameExtra)               \
-  V(NEON3SameExtra)                     \
-  V(NEONScalarByIndexedElement)         \
-  V(NEONScalarCopy)                     \
-  V(NEONScalarPairwise)                 \
-  V(NEONScalarShiftImmediate)           \
-  V(NEONShiftImmediate)                 \
-  V(NEONTable)                          \
-  V(NEONPerm)                           \
-  V(Reserved)                           \
-  V(Unallocated)                        \
-  V(Unimplemented)
-#define DEFINE_UNUSED_VISITOR(Name)                                  \
-  virtual void Visit##Name(const vixl::aarch64::Instruction* i)      \
-      VIXL_OVERRIDE {                                                \
-    USE(i); /* Prevents compiler warnings about unused variables. */ \
-  }
-  UNUSED_VISITOR_LIST(DEFINE_UNUSED_VISITOR)
-#undef DEFINE_UNUSED_VISITOR
-#undef UNUSED_VISITOR_LIST
 };
 
 
diff --git a/examples/aarch64/sve-strlen.cc b/examples/aarch64/sve-strlen.cc
new file mode 100644
index 00000000..02804d57
--- /dev/null
+++ b/examples/aarch64/sve-strlen.cc
@@ -0,0 +1,117 @@
+// Copyright 2020, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "examples.h"
+
+using namespace vixl;
+using namespace vixl::aarch64;
+
+#define __ masm->
+
+// size_t sve_strlen(const char* str);
+void GenerateSVEStrlen(MacroAssembler* masm) {
+  // We will accumulate the length as we load each chunk.
+  Register len = x1;
+  __ Mov(len, 0);
+
+  // We want to load as much as we can on each iteration, so set up an all-true
+  // predicate for that purpose.
+  PRegister all_true = p0;
+  __ Ptrue(all_true.VnB());
+
+  Label loop;
+  __ Bind(&loop);
+  // FFR is cumulative, so reset it to all-true for each iteration.
+  __ Setffr();
+
+  // Load as many characters as we can from &str[len]. We have to use a NF or FF
+  // load, because we don't know how long the string is. An FF load is a good
+  // choice, because we know that we will see at least a NULL termination, even
+  // for an empty string.
+  __ Ldff1b(z0.VnB(), all_true.Zeroing(), SVEMemOperand(x0, len));
+  // For example, if str = "Test string.", and we load every byte:
+  //   z0.b:      \0 . g n i r t s   t s e T
+
+  // FFR now represents the number of bytes that we actually loaded, so use it
+  // to predicate the data processing instructions.
+  __ Rdffr(p1.VnB());
+
+  // Find the NULL termination (if there is one), and set the flags.
+  __ Cmpeq(p2.VnB(), p1.Zeroing(), z0.VnB(), 0);
+  //   p2.b:       1 0 0 0 0 0 0 0 0 0 0 0 0
+
+  // Activate every lane up to (but not including) the NULL termination. If we
+  // found no NULL termination, this activates every lane, and indicates that we
+  // have to load another vector of characters. Lanes activated in this way
+  // represent string characters that we need to count.
+  __ Brkb(p1.VnB(), p1.Zeroing(), p2.VnB());
+  //   p1.b: 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
+
+  // Count the active lanes, and add them to the length count.
+  __ Incp(len, p1.VnB());
+
+  // Loop until `cmpeq` finds a NULL termination.
+  __ B(sve_none, &loop);
+
+  // Put the length in the AAPCS64 return register.
+  __ Mov(x0, len);
+  __ Ret();
+}
+
+#ifndef TEST_EXAMPLES
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+int main(void) {
+  MacroAssembler masm;
+  Decoder decoder;
+  Simulator simulator(&decoder);
+
+  // We're running on the simulator, so we can assume that SVE is present.
+  masm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+
+  // Generate the code for the example function.
+  Label sve_strlen;
+  masm.Bind(&sve_strlen);
+  GenerateSVEStrlen(&masm);
+  masm.FinalizeCode();
+
+  const char* example_input = "This is a string of exactly 42 characters.";
+  VIXL_ASSERT(strlen(example_input) == 42);
+
+  simulator.ResetState();
+  simulator.WriteXRegister(0, reinterpret_cast<uintptr_t>(example_input));
+  simulator.RunFrom(masm.GetLabelAddress<Instruction*>(&sve_strlen));
+
+  printf("strlen(\"%s\") == %" PRIu64 "\n",
+         example_input,
+         simulator.ReadXRegister(0));
+
+  return 0;
+}
+#else
+// Without the simulator there is nothing to test.
+int main(void) { return 0; }
+#endif  // VIXL_INCLUDE_SIMULATOR_AARCH64
+#endif  // TEST_EXAMPLES
diff --git a/src/aarch32/disasm-aarch32.cc b/src/aarch32/disasm-aarch32.cc
index 9ed3a831..535f60c8 100644
--- a/src/aarch32/disasm-aarch32.cc
+++ b/src/aarch32/disasm-aarch32.cc
@@ -8288,13 +8288,13 @@ void Disassembler::DecodeT32(uint32_t instr) {
                             UnallocatedT32(instr);
                             return;
                           }
-                          unsigned firstcond = (instr >> 20) & 0xf;
+                          unsigned first_cond = (instr >> 20) & 0xf;
                           unsigned mask = (instr >> 16) & 0xf;
-                          bool wasInITBlock = InITBlock();
-                          SetIT(Condition(firstcond), mask);
-                          it(Condition(firstcond), mask);
-                          if (wasInITBlock || (firstcond == 15) ||
-                              ((firstcond == al) &&
+                          bool was_in_it_block = InITBlock();
+                          SetIT(Condition(first_cond), mask);
+                          it(Condition(first_cond), mask);
+                          if (was_in_it_block || (first_cond == 15) ||
+                              ((first_cond == al) &&
                                (BitCount(Uint32(mask)) != 1))) {
                             UnpredictableT32(instr);
                           }
diff --git a/src/aarch32/location-aarch32.h b/src/aarch32/location-aarch32.h
index 9a57f153..512b9c7c 100644
--- a/src/aarch32/location-aarch32.h
+++ b/src/aarch32/location-aarch32.h
@@ -58,7 +58,7 @@ class Location : public LocationBase<int32_t> {
   // with the assembler methods for generating instructions, but will never
   // be handled by the pool manager.
   Location()
-      : LocationBase<int32_t>(kRawLocation, 1 /* dummy size*/),
+      : LocationBase<int32_t>(kRawLocation, 1 /* placeholder size*/),
         referenced_(false) {}
 
   typedef int32_t Offset;
diff --git a/src/aarch32/macro-assembler-aarch32.h b/src/aarch32/macro-assembler-aarch32.h
index d0ff52b3..6d76642f 100644
--- a/src/aarch32/macro-assembler-aarch32.h
+++ b/src/aarch32/macro-assembler-aarch32.h
@@ -268,7 +268,8 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
         generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE),
         pool_end_(NULL) {
 #ifdef VIXL_DEBUG
-    SetAllowMacroInstructions(true);
+    SetAllowMacroInstructions(  // NOLINT(clang-analyzer-optin.cplusplus.VirtualCall)
+        true);
 #else
     USE(allow_macro_instructions_);
 #endif
@@ -283,7 +284,8 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
         generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE),
         pool_end_(NULL) {
 #ifdef VIXL_DEBUG
-    SetAllowMacroInstructions(true);
+    SetAllowMacroInstructions(  // NOLINT(clang-analyzer-optin.cplusplus.VirtualCall)
+        true);
 #endif
   }
   MacroAssembler(byte* buffer, size_t size, InstructionSet isa = kDefaultISA)
@@ -296,7 +298,8 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
         generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE),
         pool_end_(NULL) {
 #ifdef VIXL_DEBUG
-    SetAllowMacroInstructions(true);
+    SetAllowMacroInstructions(  // NOLINT(clang-analyzer-optin.cplusplus.VirtualCall)
+        true);
 #endif
   }
 
diff --git a/src/aarch32/operands-aarch32.h b/src/aarch32/operands-aarch32.h
index 1d18bfd3..2b452958 100644
--- a/src/aarch32/operands-aarch32.h
+++ b/src/aarch32/operands-aarch32.h
@@ -54,28 +54,16 @@ class Operand {
   // This is allowed to be an implicit constructor because Operand is
   // a wrapper class that doesn't normally perform any type conversion.
   Operand(uint32_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        rm_(NoReg),
-        shift_(LSL),
-        amount_(0),
-        rs_(NoReg) {}
+      : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {}
   Operand(int32_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        rm_(NoReg),
-        shift_(LSL),
-        amount_(0),
-        rs_(NoReg) {}
+      : imm_(immediate), rm_(NoReg), shift_(LSL), amount_(0), rs_(NoReg) {}
 
   // rm
   // where rm is the base register
   // This is allowed to be an implicit constructor because Operand is
   // a wrapper class that doesn't normally perform any type conversion.
   Operand(Register rm)  // NOLINT(runtime/explicit)
-      : imm_(0),
-        rm_(rm),
-        shift_(LSL),
-        amount_(0),
-        rs_(NoReg) {
+      : imm_(0), rm_(rm), shift_(LSL), amount_(0), rs_(NoReg) {
     VIXL_ASSERT(rm_.IsValid());
   }
 
@@ -245,22 +233,18 @@ class NeonImmediate {
   // This is allowed to be an implicit constructor because NeonImmediate is
   // a wrapper class that doesn't normally perform any type conversion.
   NeonImmediate(uint32_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        immediate_type_(I32) {}
+      : imm_(immediate), immediate_type_(I32) {}
   NeonImmediate(int immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        immediate_type_(I32) {}
+      : imm_(immediate), immediate_type_(I32) {}
 
   // { #<immediate> }
   // where <immediate> is a 64 bit number
   // This is allowed to be an implicit constructor because NeonImmediate is
   // a wrapper class that doesn't normally perform any type conversion.
   NeonImmediate(int64_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        immediate_type_(I64) {}
+      : imm_(immediate), immediate_type_(I64) {}
   NeonImmediate(uint64_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        immediate_type_(I64) {}
+      : imm_(immediate), immediate_type_(I64) {}
 
   // { #<immediate> }
   // where <immediate> is a non zero floating point number which can be encoded
@@ -268,11 +252,9 @@ class NeonImmediate {
   // This is allowed to be an implicit constructor because NeonImmediate is
   // a wrapper class that doesn't normally perform any type conversion.
   NeonImmediate(float immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        immediate_type_(F32) {}
+      : imm_(immediate), immediate_type_(F32) {}
   NeonImmediate(double immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        immediate_type_(F64) {}
+      : imm_(immediate), immediate_type_(F64) {}
 
   NeonImmediate(const NeonImmediate& src)
       : imm_(src.imm_), immediate_type_(src.immediate_type_) {}
@@ -374,29 +356,21 @@ std::ostream& operator<<(std::ostream& os, const NeonImmediate& operand);
 class NeonOperand {
  public:
   NeonOperand(int32_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        rm_(NoDReg) {}
+      : imm_(immediate), rm_(NoDReg) {}
   NeonOperand(uint32_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        rm_(NoDReg) {}
+      : imm_(immediate), rm_(NoDReg) {}
   NeonOperand(int64_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        rm_(NoDReg) {}
+      : imm_(immediate), rm_(NoDReg) {}
   NeonOperand(uint64_t immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        rm_(NoDReg) {}
+      : imm_(immediate), rm_(NoDReg) {}
   NeonOperand(float immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        rm_(NoDReg) {}
+      : imm_(immediate), rm_(NoDReg) {}
   NeonOperand(double immediate)  // NOLINT(runtime/explicit)
-      : imm_(immediate),
-        rm_(NoDReg) {}
+      : imm_(immediate), rm_(NoDReg) {}
   NeonOperand(const NeonImmediate& imm)  // NOLINT(runtime/explicit)
-      : imm_(imm),
-        rm_(NoDReg) {}
+      : imm_(imm), rm_(NoDReg) {}
   NeonOperand(const VRegister& rm)  // NOLINT(runtime/explicit)
-      : imm_(0),
-        rm_(rm) {
+      : imm_(0), rm_(rm) {
     VIXL_ASSERT(rm_.IsValid());
   }
 
diff --git a/src/aarch64/assembler-aarch64.cc b/src/aarch64/assembler-aarch64.cc
index 9e73ffaa..e98de89b 100644
--- a/src/aarch64/assembler-aarch64.cc
+++ b/src/aarch64/assembler-aarch64.cc
@@ -1044,7 +1044,7 @@ void Assembler::cls(const Register& rd, const Register& rn) {
   V(auti, AUTI)             \
   V(autd, AUTD)
 
-#define DEFINE_ASM_FUNCS(PRE, OP)                                  \
+#define VIXL_DEFINE_ASM_FUNC(PRE, OP)                              \
   void Assembler::PRE##a(const Register& xd, const Register& xn) { \
     VIXL_ASSERT(CPUHas(CPUFeatures::kPAuth));                      \
     VIXL_ASSERT(xd.Is64Bits() && xn.Is64Bits());                   \
@@ -1069,8 +1069,8 @@ void Assembler::cls(const Register& rd, const Register& rn) {
     Emit(SF(xd) | OP##ZB | Rd(xd));                                \
   }
 
-PAUTH_VARIATIONS(DEFINE_ASM_FUNCS)
-#undef DEFINE_ASM_FUNCS
+PAUTH_VARIATIONS(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 void Assembler::pacga(const Register& xd,
                       const Register& xn,
@@ -1141,7 +1141,13 @@ void Assembler::LoadStorePair(const CPURegister& rt,
       addrmodeop = LoadStorePairPostIndexFixed;
     }
   }
-  Emit(addrmodeop | memop);
+
+  Instr emitop = addrmodeop | memop;
+
+  // Only X registers may be specified for ldpsw.
+  VIXL_ASSERT(((emitop & LoadStorePairMask) != LDPSW_x) || rt.IsX());
+
+  Emit(emitop);
 }
 
 
@@ -1381,10 +1387,16 @@ void Assembler::ldr(const CPURegister& rt, int64_t imm19) {
 }
 
 
-void Assembler::prfm(PrefetchOperation op, int64_t imm19) {
+void Assembler::prfm(int op, int64_t imm19) {
   Emit(PRFM_lit | ImmPrefetchOperation(op) | ImmLLiteral(imm19));
 }
 
+void Assembler::prfm(PrefetchOperation op, int64_t imm19) {
+  // Passing unnamed values in 'op' is undefined behaviour in C++.
+  VIXL_ASSERT(IsNamedPrefetchOperation(op));
+  prfm(static_cast<int>(op), imm19);
+}
+
 
 // Exclusive-access instructions.
 void Assembler::stxrb(const Register& rs,
@@ -1635,17 +1647,18 @@ void Assembler::ldlar(const Register& rt, const MemOperand& src) {
   V(casal, CASAL)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP)                                          \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                                     \
   void Assembler::FN(const Register& rs,                                 \
                      const Register& rt,                                 \
                      const MemOperand& src) {                            \
     VIXL_ASSERT(CPUHas(CPUFeatures::kAtomics));                          \
     VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));      \
+    VIXL_ASSERT(AreSameFormat(rs, rt));                                  \
     LoadStoreExclusive op = rt.Is64Bits() ? OP##_x : OP##_w;             \
     Emit(op | Rs(rs) | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister())); \
   }
-COMPARE_AND_SWAP_W_X_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+COMPARE_AND_SWAP_W_X_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 // clang-format off
 #define COMPARE_AND_SWAP_W_LIST(V) \
@@ -1659,7 +1672,7 @@ COMPARE_AND_SWAP_W_X_LIST(DEFINE_ASM_FUNC)
   V(casalh, CASALH)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP)                                          \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                                     \
   void Assembler::FN(const Register& rs,                                 \
                      const Register& rt,                                 \
                      const MemOperand& src) {                            \
@@ -1667,8 +1680,8 @@ COMPARE_AND_SWAP_W_X_LIST(DEFINE_ASM_FUNC)
     VIXL_ASSERT(src.IsImmediateOffset() && (src.GetOffset() == 0));      \
     Emit(OP | Rs(rs) | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister())); \
   }
-COMPARE_AND_SWAP_W_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+COMPARE_AND_SWAP_W_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 // clang-format off
@@ -1679,7 +1692,7 @@ COMPARE_AND_SWAP_W_LIST(DEFINE_ASM_FUNC)
   V(caspal, CASPAL)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP)                                          \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                                     \
   void Assembler::FN(const Register& rs,                                 \
                      const Register& rs1,                                \
                      const Register& rt,                                 \
@@ -1691,11 +1704,12 @@ COMPARE_AND_SWAP_W_LIST(DEFINE_ASM_FUNC)
     VIXL_ASSERT(AreEven(rs, rt));                                        \
     VIXL_ASSERT(AreConsecutive(rs, rs1));                                \
     VIXL_ASSERT(AreConsecutive(rt, rt1));                                \
+    VIXL_ASSERT(AreSameFormat(rs, rs1, rt, rt1));                        \
     LoadStoreExclusive op = rt.Is64Bits() ? OP##_x : OP##_w;             \
     Emit(op | Rs(rs) | Rt(rt) | Rt2_mask | RnSP(src.GetBaseRegister())); \
   }
-COMPARE_AND_SWAP_PAIR_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+COMPARE_AND_SWAP_PAIR_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 // These macros generate all the variations of the atomic memory operations,
 // e.g. ldadd, ldadda, ldaddb, staddl, etc.
@@ -1846,7 +1860,7 @@ void Assembler::ldapursw(const Register& rt, const MemOperand& src) {
   Emit(LDAPURSW | Rt(rt) | base | ImmLS(static_cast<int>(offset)));
 }
 
-void Assembler::prfm(PrefetchOperation op,
+void Assembler::prfm(int op,
                      const MemOperand& address,
                      LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireUnscaledOffset);
@@ -1854,8 +1868,16 @@ void Assembler::prfm(PrefetchOperation op,
   Prefetch(op, address, option);
 }
 
+void Assembler::prfm(PrefetchOperation op,
+                     const MemOperand& address,
+                     LoadStoreScalingOption option) {
+  // Passing unnamed values in 'op' is undefined behaviour in C++.
+  VIXL_ASSERT(IsNamedPrefetchOperation(op));
+  prfm(static_cast<int>(op), address, option);
+}
 
-void Assembler::prfum(PrefetchOperation op,
+
+void Assembler::prfum(int op,
                       const MemOperand& address,
                       LoadStoreScalingOption option) {
   VIXL_ASSERT(option != RequireScaledOffset);
@@ -1863,11 +1885,25 @@ void Assembler::prfum(PrefetchOperation op,
   Prefetch(op, address, option);
 }
 
+void Assembler::prfum(PrefetchOperation op,
+                      const MemOperand& address,
+                      LoadStoreScalingOption option) {
+  // Passing unnamed values in 'op' is undefined behaviour in C++.
+  VIXL_ASSERT(IsNamedPrefetchOperation(op));
+  prfum(static_cast<int>(op), address, option);
+}
 
-void Assembler::prfm(PrefetchOperation op, RawLiteral* literal) {
+
+void Assembler::prfm(int op, RawLiteral* literal) {
   prfm(op, static_cast<int>(LinkAndGetWordOffsetTo(literal)));
 }
 
+void Assembler::prfm(PrefetchOperation op, RawLiteral* literal) {
+  // Passing unnamed values in 'op' is undefined behaviour in C++.
+  VIXL_ASSERT(IsNamedPrefetchOperation(op));
+  prfm(static_cast<int>(op), literal);
+}
+
 
 void Assembler::sys(int op1, int crn, int crm, int op2, const Register& xt) {
   VIXL_ASSERT(xt.Is64Bits());
@@ -1933,6 +1969,7 @@ void Assembler::LoadStoreStructVerify(const VRegister& vt,
   // Assert that addressing mode is either offset (with immediate 0), post
   // index by immediate of the size of the register list, or post index by a
   // value in a core register.
+  VIXL_ASSERT(vt.HasSize() && vt.HasLaneSize());
   if (addr.IsImmediateOffset()) {
     VIXL_ASSERT(addr.GetOffset() == 0);
   } else {
@@ -2290,6 +2327,7 @@ void Assembler::LoadStoreStructSingle(const VRegister& vt,
   // We support vt arguments of the form vt.VxT() or vt.T(), where x is the
   // number of lanes, and T is b, h, s or d.
   unsigned lane_size = vt.GetLaneSizeInBytes();
+  VIXL_ASSERT(lane_size > 0);
   VIXL_ASSERT(lane < (kQRegSizeInBytes / lane_size));
 
   // Lane size is encoded in the opcode field. Lane index is encoded in the Q,
@@ -2424,7 +2462,7 @@ void Assembler::NEON3DifferentHN(const VRegister& vd,
 // clang-format on
 
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)                   \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP, AS)                   \
 void Assembler::FN(const VRegister& vd,               \
                    const VRegister& vn,               \
                    const VRegister& vm) {             \
@@ -2432,8 +2470,8 @@ void Assembler::FN(const VRegister& vd,               \
   VIXL_ASSERT(AS);                                    \
   NEON3DifferentL(vd, vn, vm, OP);                    \
 }
-NEON_3DIFF_LONG_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_3DIFF_LONG_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 // clang-format off
 #define NEON_3DIFF_HN_LIST(V)         \
@@ -2447,7 +2485,7 @@ NEON_3DIFF_LONG_LIST(DEFINE_ASM_FUNC)
   V(rsubhn2, NEON_RSUBHN2, vd.IsQ())
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)          \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP, AS)     \
   void Assembler::FN(const VRegister& vd,    \
                      const VRegister& vn,    \
                      const VRegister& vm) {  \
@@ -2455,8 +2493,8 @@ NEON_3DIFF_LONG_LIST(DEFINE_ASM_FUNC)
     VIXL_ASSERT(AS);                         \
     NEON3DifferentHN(vd, vn, vm, OP);        \
   }
-NEON_3DIFF_HN_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_3DIFF_HN_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 void Assembler::uaddw(const VRegister& vd,
                       const VRegister& vn,
@@ -3104,7 +3142,7 @@ void Assembler::NEONFP16ConvertToInt(const VRegister& vd,
   V(fcvtau, NEON_FCVTAU, FCVTAU)     \
   V(fcvtas, NEON_FCVTAS, FCVTAS)
 
-#define DEFINE_ASM_FUNCS(FN, VEC_OP, SCA_OP)                     \
+#define VIXL_DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP)                 \
   void Assembler::FN(const Register& rd, const VRegister& vn) {  \
     VIXL_ASSERT(CPUHas(CPUFeatures::kFP));                       \
     if (vn.IsH()) VIXL_ASSERT(CPUHas(CPUFeatures::kFPHalf));     \
@@ -3119,8 +3157,8 @@ void Assembler::NEONFP16ConvertToInt(const VRegister& vd,
       NEONFPConvertToInt(vd, vn, VEC_OP);                        \
     }                                                            \
   }
-NEON_FP2REGMISC_FCVT_LIST(DEFINE_ASM_FUNCS)
-#undef DEFINE_ASM_FUNCS
+NEON_FP2REGMISC_FCVT_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 void Assembler::fcvtzs(const Register& rd, const VRegister& vn, int fbits) {
@@ -3308,7 +3346,7 @@ void Assembler::NEON3SameFP16(const VRegister& vd,
   V(frecpe,  NEON_FRECPE,  NEON_FRECPE_scalar,  NEON_FRECPE_H_scalar)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP, SCA_OP_H)                        \
+#define VIXL_DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP, SCA_OP_H)                   \
   void Assembler::FN(const VRegister& vd, const VRegister& vn) {             \
     VIXL_ASSERT(CPUHas(CPUFeatures::kFP));                                   \
     Instr op;                                                                \
@@ -3348,8 +3386,8 @@ void Assembler::NEON3SameFP16(const VRegister& vd,
       NEONFP2RegMisc(vd, vn, op);                                            \
     }                                                                        \
   }
-NEON_FP2REGMISC_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_FP2REGMISC_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 // clang-format off
 #define NEON_FP2REGMISC_V85_LIST(V)       \
@@ -3359,7 +3397,7 @@ NEON_FP2REGMISC_LIST(DEFINE_ASM_FUNC)
   V(frint64z,  NEON_FRINT64Z,  FRINT64Z)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP)                                    \
+#define VIXL_DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP)                               \
   void Assembler::FN(const VRegister& vd, const VRegister& vn) {               \
     VIXL_ASSERT(CPUHas(CPUFeatures::kFP, CPUFeatures::kFrintToFixedSizedInt)); \
     Instr op;                                                                  \
@@ -3373,8 +3411,8 @@ NEON_FP2REGMISC_LIST(DEFINE_ASM_FUNC)
     }                                                                          \
     NEONFP2RegMisc(vd, vn, op);                                                \
   }
-NEON_FP2REGMISC_V85_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_FP2REGMISC_V85_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 void Assembler::NEONFP2RegMiscFP16(const VRegister& vd,
                                    const VRegister& vn,
@@ -3638,7 +3676,7 @@ void Assembler::frecpx(const VRegister& vd, const VRegister& vn) {
   V(uqrshl,   NEON_UQRSHL,   true)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)          \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP, AS)     \
   void Assembler::FN(const VRegister& vd,    \
                      const VRegister& vn,    \
                      const VRegister& vm) {  \
@@ -3646,8 +3684,8 @@ void Assembler::frecpx(const VRegister& vd, const VRegister& vn) {
     VIXL_ASSERT(AS);                         \
     NEON3Same(vd, vn, vm, OP);               \
   }
-NEON_3SAME_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_3SAME_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 // clang-format off
 #define NEON_FP3SAME_OP_LIST(V)                                        \
@@ -3680,7 +3718,7 @@ NEON_3SAME_LIST(DEFINE_ASM_FUNC)
 // TODO: This macro is complicated because it classifies the instructions in the
 // macro list above, and treats each case differently. It could be somewhat
 // simpler if we were to split the macro, at the cost of some duplication.
-#define DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP, SCA_OP_H)                    \
+#define VIXL_DEFINE_ASM_FUNC(FN, VEC_OP, SCA_OP, SCA_OP_H)               \
   void Assembler::FN(const VRegister& vd,                                \
                      const VRegister& vn,                                \
                      const VRegister& vm) {                              \
@@ -3720,8 +3758,8 @@ NEON_3SAME_LIST(DEFINE_ASM_FUNC)
       NEONFP3Same(vd, vn, vm, op);                                       \
     }                                                                    \
   }
-NEON_FP3SAME_OP_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_FP3SAME_OP_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 // clang-format off
@@ -3732,7 +3770,7 @@ NEON_FP3SAME_OP_LIST(DEFINE_ASM_FUNC)
   V(fmlsl2,  NEON_FMLSL2)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, VEC_OP)                         \
+#define VIXL_DEFINE_ASM_FUNC(FN, VEC_OP)                    \
   void Assembler::FN(const VRegister& vd,                   \
                      const VRegister& vn,                   \
                      const VRegister& vm) {                 \
@@ -3744,8 +3782,8 @@ NEON_FP3SAME_OP_LIST(DEFINE_ASM_FUNC)
                 (vd.Is4S() && vn.Is4H() && vm.Is4H()));     \
     Emit(FPFormat(vd) | VEC_OP | Rm(vm) | Rn(vn) | Rd(vd)); \
   }
-NEON_FHM_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_FHM_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 void Assembler::addp(const VRegister& vd, const VRegister& vn) {
@@ -4138,7 +4176,7 @@ void Assembler::udot(const VRegister& vd,
   V(sqrdmulh, NEON_SQRDMULH_byelement, true)          \
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)                     \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP, AS)                     \
   void Assembler::FN(const VRegister& vd,               \
                      const VRegister& vn,               \
                      const VRegister& vm,               \
@@ -4147,8 +4185,8 @@ void Assembler::udot(const VRegister& vd,
     VIXL_ASSERT(AS);                                    \
     NEONByElement(vd, vn, vm, vm_index, OP);            \
   }
-NEON_BYELEMENT_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_BYELEMENT_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 // clang-format off
@@ -4157,7 +4195,7 @@ NEON_BYELEMENT_LIST(DEFINE_ASM_FUNC)
   V(sqrdmlsh, NEON_SQRDMLSH_byelement)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP)                                 \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                            \
   void Assembler::FN(const VRegister& vd,                       \
                      const VRegister& vn,                       \
                      const VRegister& vm,                       \
@@ -4165,8 +4203,8 @@ NEON_BYELEMENT_LIST(DEFINE_ASM_FUNC)
     VIXL_ASSERT(CPUHas(CPUFeatures::kNEON, CPUFeatures::kRDM)); \
     NEONByElement(vd, vn, vm, vm_index, OP);                    \
   }
-NEON_BYELEMENT_RDM_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_BYELEMENT_RDM_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 // clang-format off
@@ -4177,7 +4215,7 @@ NEON_BYELEMENT_RDM_LIST(DEFINE_ASM_FUNC)
   V(fmulx, NEON_FMULX_byelement, NEON_FMULX_H_byelement)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP, OP_H)                                  \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP, OP_H)                             \
   void Assembler::FN(const VRegister& vd,                              \
                      const VRegister& vn,                              \
                      const VRegister& vm,                              \
@@ -4186,8 +4224,8 @@ NEON_BYELEMENT_RDM_LIST(DEFINE_ASM_FUNC)
     if (vd.IsLaneSizeH()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf)); \
     NEONFPByElement(vd, vn, vm, vm_index, OP, OP_H);                   \
   }
-NEON_FPBYELEMENT_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_FPBYELEMENT_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 // clang-format off
@@ -4213,7 +4251,7 @@ NEON_FPBYELEMENT_LIST(DEFINE_ASM_FUNC)
 // clang-format on
 
 
-#define DEFINE_ASM_FUNC(FN, OP, AS)           \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP, AS)      \
   void Assembler::FN(const VRegister& vd,     \
                      const VRegister& vn,     \
                      const VRegister& vm,     \
@@ -4222,8 +4260,8 @@ NEON_FPBYELEMENT_LIST(DEFINE_ASM_FUNC)
     VIXL_ASSERT(AS);                          \
     NEONByElementL(vd, vn, vm, vm_index, OP); \
   }
-NEON_BYELEMENT_LONG_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_BYELEMENT_LONG_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 // clang-format off
@@ -4235,7 +4273,7 @@ NEON_BYELEMENT_LONG_LIST(DEFINE_ASM_FUNC)
 // clang-format on
 
 
-#define DEFINE_ASM_FUNC(FN, OP)                                        \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                                   \
   void Assembler::FN(const VRegister& vd,                              \
                      const VRegister& vn,                              \
                      const VRegister& vm,                              \
@@ -4252,8 +4290,8 @@ NEON_BYELEMENT_LONG_LIST(DEFINE_ASM_FUNC)
     Emit(FPFormat(vd) | OP | Rd(vd) | Rn(vn) | Rm(vm) |                \
          ImmNEONHLM(vm_index, 3));                                     \
   }
-NEON_BYELEMENT_FHM_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_BYELEMENT_FHM_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 void Assembler::suqadd(const VRegister& vd, const VRegister& vn) {
   VIXL_ASSERT(CPUHas(CPUFeatures::kNEON));
@@ -4763,13 +4801,13 @@ void Assembler::NEONAcrossLanes(const VRegister& vd,
   V(uminv,   NEON_UMINV)
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP)                                  \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                             \
   void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
     VIXL_ASSERT(CPUHas(CPUFeatures::kNEON));                     \
     NEONAcrossLanes(vd, vn, OP, 0);                              \
   }
-NEON_ACROSSLANES_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_ACROSSLANES_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 // clang-format off
@@ -4780,15 +4818,15 @@ NEON_ACROSSLANES_LIST(DEFINE_ASM_FUNC)
   V(fminnmv, NEON_FMINNMV, NEON_FMINNMV_H) \
 // clang-format on
 
-#define DEFINE_ASM_FUNC(FN, OP, OP_H)                            \
+#define VIXL_DEFINE_ASM_FUNC(FN, OP, OP_H)                            \
   void Assembler::FN(const VRegister& vd, const VRegister& vn) { \
     VIXL_ASSERT(CPUHas(CPUFeatures::kFP, CPUFeatures::kNEON));   \
     if (vd.Is1H()) VIXL_ASSERT(CPUHas(CPUFeatures::kNEONHalf));  \
     VIXL_ASSERT(vd.Is1S() || vd.Is1H());                         \
     NEONAcrossLanes(vd, vn, OP, OP_H);                           \
   }
-NEON_ACROSSLANES_FP_LIST(DEFINE_ASM_FUNC)
-#undef DEFINE_ASM_FUNC
+NEON_ACROSSLANES_FP_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
 
 
 void Assembler::NEONPerm(const VRegister& vd,
@@ -4870,9 +4908,9 @@ void Assembler::NEONShiftLeftImmediate(const VRegister& vd,
                                        const VRegister& vn,
                                        int shift,
                                        NEONShiftImmediateOp op) {
-  int laneSizeInBits = vn.GetLaneSizeInBits();
-  VIXL_ASSERT((shift >= 0) && (shift < laneSizeInBits));
-  NEONShiftImmediate(vd, vn, op, (laneSizeInBits + shift) << 16);
+  int lane_size_in_bits = vn.GetLaneSizeInBits();
+  VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits));
+  NEONShiftImmediate(vd, vn, op, (lane_size_in_bits + shift) << 16);
 }
 
 
@@ -4880,9 +4918,9 @@ void Assembler::NEONShiftRightImmediate(const VRegister& vd,
                                         const VRegister& vn,
                                         int shift,
                                         NEONShiftImmediateOp op) {
-  int laneSizeInBits = vn.GetLaneSizeInBits();
-  VIXL_ASSERT((shift >= 1) && (shift <= laneSizeInBits));
-  NEONShiftImmediate(vd, vn, op, ((2 * laneSizeInBits) - shift) << 16);
+  int lane_size_in_bits = vn.GetLaneSizeInBits();
+  VIXL_ASSERT((shift >= 1) && (shift <= lane_size_in_bits));
+  NEONShiftImmediate(vd, vn, op, ((2 * lane_size_in_bits) - shift) << 16);
 }
 
 
@@ -4890,9 +4928,9 @@ void Assembler::NEONShiftImmediateL(const VRegister& vd,
                                     const VRegister& vn,
                                     int shift,
                                     NEONShiftImmediateOp op) {
-  int laneSizeInBits = vn.GetLaneSizeInBits();
-  VIXL_ASSERT((shift >= 0) && (shift < laneSizeInBits));
-  int immh_immb = (laneSizeInBits + shift) << 16;
+  int lane_size_in_bits = vn.GetLaneSizeInBits();
+  VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits));
+  int immh_immb = (lane_size_in_bits + shift) << 16;
 
   VIXL_ASSERT((vn.Is8B() && vd.Is8H()) || (vn.Is4H() && vd.Is4S()) ||
               (vn.Is2S() && vd.Is2D()) || (vn.Is16B() && vd.Is8H()) ||
@@ -4908,9 +4946,9 @@ void Assembler::NEONShiftImmediateN(const VRegister& vd,
                                     int shift,
                                     NEONShiftImmediateOp op) {
   Instr q, scalar;
-  int laneSizeInBits = vd.GetLaneSizeInBits();
-  VIXL_ASSERT((shift >= 1) && (shift <= laneSizeInBits));
-  int immh_immb = (2 * laneSizeInBits - shift) << 16;
+  int lane_size_in_bits = vd.GetLaneSizeInBits();
+  VIXL_ASSERT((shift >= 1) && (shift <= lane_size_in_bits));
+  int immh_immb = (2 * lane_size_in_bits - shift) << 16;
 
   if (vn.IsScalar()) {
     VIXL_ASSERT((vd.Is1B() && vn.Is1H()) || (vd.Is1H() && vn.Is1S()) ||
@@ -5271,6 +5309,7 @@ void Assembler::MoveWide(const Register& rd,
   } else {
     // Calculate a new immediate and shift combination to encode the immediate
     // argument.
+    VIXL_ASSERT(shift == -1);
     shift = 0;
     if ((imm & 0xffffffffffff0000) == 0) {
       // Nothing to do.
@@ -5604,7 +5643,7 @@ void Assembler::DataProcExtendedRegister(const Register& rd,
 
 
 Instr Assembler::LoadStoreMemOperand(const MemOperand& addr,
-                                     unsigned access_size,
+                                     unsigned access_size_in_bytes_log2,
                                      LoadStoreScalingOption option) {
   Instr base = RnSP(addr.GetBaseRegister());
   int64_t offset = addr.GetOffset();
@@ -5614,21 +5653,22 @@ Instr Assembler::LoadStoreMemOperand(const MemOperand& addr,
         (option == PreferUnscaledOffset) || (option == RequireUnscaledOffset);
     if (prefer_unscaled && IsImmLSUnscaled(offset)) {
       // Use the unscaled addressing mode.
-      return base | LoadStoreUnscaledOffsetFixed |
-             ImmLS(static_cast<int>(offset));
+      return base | LoadStoreUnscaledOffsetFixed | ImmLS(offset);
     }
 
     if ((option != RequireUnscaledOffset) &&
-        IsImmLSScaled(offset, access_size)) {
+        IsImmLSScaled(offset, access_size_in_bytes_log2)) {
+      // We need `offset` to be positive for the shift to be well-defined.
+      // IsImmLSScaled should check this.
+      VIXL_ASSERT(offset >= 0);
       // Use the scaled addressing mode.
       return base | LoadStoreUnsignedOffsetFixed |
-             ImmLSUnsigned(static_cast<int>(offset) >> access_size);
+             ImmLSUnsigned(offset >> access_size_in_bytes_log2);
     }
 
     if ((option != RequireScaledOffset) && IsImmLSUnscaled(offset)) {
       // Use the unscaled addressing mode.
-      return base | LoadStoreUnscaledOffsetFixed |
-             ImmLS(static_cast<int>(offset));
+      return base | LoadStoreUnscaledOffsetFixed | ImmLS(offset);
     }
   }
 
@@ -5649,17 +5689,17 @@ Instr Assembler::LoadStoreMemOperand(const MemOperand& addr,
 
     // Shifts are encoded in one bit, indicating a left shift by the memory
     // access size.
-    VIXL_ASSERT((shift_amount == 0) || (shift_amount == access_size));
+    VIXL_ASSERT((shift_amount == 0) || (shift_amount == access_size_in_bytes_log2));
     return base | LoadStoreRegisterOffsetFixed | Rm(addr.GetRegisterOffset()) |
            ExtendMode(ext) | ImmShiftLS((shift_amount > 0) ? 1 : 0);
   }
 
   if (addr.IsPreIndex() && IsImmLSUnscaled(offset)) {
-    return base | LoadStorePreIndexFixed | ImmLS(static_cast<int>(offset));
+    return base | LoadStorePreIndexFixed | ImmLS(offset);
   }
 
   if (addr.IsPostIndex() && IsImmLSUnscaled(offset)) {
-    return base | LoadStorePostIndexFixed | ImmLS(static_cast<int>(offset));
+    return base | LoadStorePostIndexFixed | ImmLS(offset);
   }
 
   // If this point is reached, the MemOperand (addr) cannot be encoded.
@@ -5694,7 +5734,7 @@ void Assembler::LoadStorePAC(const Register& xt,
 }
 
 
-void Assembler::Prefetch(PrefetchOperation op,
+void Assembler::Prefetch(int op,
                          const MemOperand& addr,
                          LoadStoreScalingOption option) {
   VIXL_ASSERT(addr.IsRegisterOffset() || addr.IsImmediateOffset());
@@ -5703,6 +5743,14 @@ void Assembler::Prefetch(PrefetchOperation op,
   Emit(PRFM | prfop | LoadStoreMemOperand(addr, kXRegSizeInBytesLog2, option));
 }
 
+void Assembler::Prefetch(PrefetchOperation op,
+                         const MemOperand& addr,
+                         LoadStoreScalingOption option) {
+  // Passing unnamed values in 'op' is undefined behaviour in C++.
+  VIXL_ASSERT(IsNamedPrefetchOperation(op));
+  Prefetch(static_cast<int>(op), addr, option);
+}
+
 
 bool Assembler::IsImmAddSub(int64_t immediate) {
   return IsUint12(immediate) ||
@@ -5788,17 +5836,17 @@ bool Assembler::IsImmFP64(double imm) {
 }
 
 
-bool Assembler::IsImmLSPair(int64_t offset, unsigned access_size) {
-  VIXL_ASSERT(access_size <= kQRegSizeInBytesLog2);
-  return IsMultiple(offset, 1 << access_size) &&
-         IsInt7(offset / (1 << access_size));
+bool Assembler::IsImmLSPair(int64_t offset, unsigned access_size_in_bytes_log2) {
+  VIXL_ASSERT(access_size_in_bytes_log2 <= kQRegSizeInBytesLog2);
+  return IsMultiple(offset, 1 << access_size_in_bytes_log2) &&
+         IsInt7(offset / (1 << access_size_in_bytes_log2));
 }
 
 
-bool Assembler::IsImmLSScaled(int64_t offset, unsigned access_size) {
-  VIXL_ASSERT(access_size <= kQRegSizeInBytesLog2);
-  return IsMultiple(offset, 1 << access_size) &&
-         IsUint12(offset / (1 << access_size));
+bool Assembler::IsImmLSScaled(int64_t offset, unsigned access_size_in_bytes_log2) {
+  VIXL_ASSERT(access_size_in_bytes_log2 <= kQRegSizeInBytesLog2);
+  return IsMultiple(offset, 1 << access_size_in_bytes_log2) &&
+         IsUint12(offset / (1 << access_size_in_bytes_log2));
 }
 
 
@@ -5832,7 +5880,8 @@ bool Assembler::IsImmLogical(uint64_t value,
                              unsigned* n,
                              unsigned* imm_s,
                              unsigned* imm_r) {
-  VIXL_ASSERT((width == kWRegSize) || (width == kXRegSize));
+  VIXL_ASSERT((width == kBRegSize) || (width == kHRegSize) ||
+              (width == kSRegSize) || (width == kDRegSize));
 
   bool negate = false;
 
@@ -5873,16 +5922,18 @@ bool Assembler::IsImmLogical(uint64_t value,
     value = ~value;
   }
 
-  if (width == kWRegSize) {
-    // To handle 32-bit logical immediates, the very easiest thing is to repeat
-    // the input value twice to make a 64-bit word. The correct encoding of that
-    // as a logical immediate will also be the correct encoding of the 32-bit
-    // value.
+  if (width <= kWRegSize) {
+    // To handle 8/16/32-bit logical immediates, the very easiest thing is to repeat
+    // the input value to fill a 64-bit word. The correct encoding of that as a
+    // logical immediate will also be the correct encoding of the value.
 
-    // Avoid making the assumption that the most-significant 32 bits are zero by
+    // Avoid making the assumption that the most-significant 56/48/32 bits are zero by
     // shifting the value left and duplicating it.
-    value <<= kWRegSize;
-    value |= value >> kWRegSize;
+    for (unsigned bits = width; bits <= kWRegSize; bits *= 2) {
+      value <<= bits;
+      uint64_t mask = (UINT64_C(1) << bits) - 1;
+      value |= ((value >> bits) & mask);
+    }
   }
 
   // The basic analysis idea: imagine our input word looks like this.
@@ -6186,152 +6237,5 @@ bool Assembler::CPUHas(SystemRegister sysreg) const {
 }
 
 
-bool AreAliased(const CPURegister& reg1,
-                const CPURegister& reg2,
-                const CPURegister& reg3,
-                const CPURegister& reg4,
-                const CPURegister& reg5,
-                const CPURegister& reg6,
-                const CPURegister& reg7,
-                const CPURegister& reg8) {
-  int number_of_valid_regs = 0;
-  int number_of_valid_fpregs = 0;
-
-  RegList unique_regs = 0;
-  RegList unique_fpregs = 0;
-
-  const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
-
-  for (size_t i = 0; i < ArrayLength(regs); i++) {
-    if (regs[i].IsRegister()) {
-      number_of_valid_regs++;
-      unique_regs |= regs[i].GetBit();
-    } else if (regs[i].IsVRegister()) {
-      number_of_valid_fpregs++;
-      unique_fpregs |= regs[i].GetBit();
-    } else {
-      VIXL_ASSERT(!regs[i].IsValid());
-    }
-  }
-
-  int number_of_unique_regs = CountSetBits(unique_regs);
-  int number_of_unique_fpregs = CountSetBits(unique_fpregs);
-
-  VIXL_ASSERT(number_of_valid_regs >= number_of_unique_regs);
-  VIXL_ASSERT(number_of_valid_fpregs >= number_of_unique_fpregs);
-
-  return (number_of_valid_regs != number_of_unique_regs) ||
-         (number_of_valid_fpregs != number_of_unique_fpregs);
-}
-
-
-bool AreSameSizeAndType(const CPURegister& reg1,
-                        const CPURegister& reg2,
-                        const CPURegister& reg3,
-                        const CPURegister& reg4,
-                        const CPURegister& reg5,
-                        const CPURegister& reg6,
-                        const CPURegister& reg7,
-                        const CPURegister& reg8) {
-  VIXL_ASSERT(reg1.IsValid());
-  bool match = true;
-  match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
-  match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
-  match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
-  match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
-  match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);
-  match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1);
-  match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1);
-  return match;
-}
-
-bool AreEven(const CPURegister& reg1,
-             const CPURegister& reg2,
-             const CPURegister& reg3,
-             const CPURegister& reg4,
-             const CPURegister& reg5,
-             const CPURegister& reg6,
-             const CPURegister& reg7,
-             const CPURegister& reg8) {
-  VIXL_ASSERT(reg1.IsValid());
-  bool even = (reg1.GetCode() % 2) == 0;
-  even &= !reg2.IsValid() || ((reg2.GetCode() % 2) == 0);
-  even &= !reg3.IsValid() || ((reg3.GetCode() % 2) == 0);
-  even &= !reg4.IsValid() || ((reg4.GetCode() % 2) == 0);
-  even &= !reg5.IsValid() || ((reg5.GetCode() % 2) == 0);
-  even &= !reg6.IsValid() || ((reg6.GetCode() % 2) == 0);
-  even &= !reg7.IsValid() || ((reg7.GetCode() % 2) == 0);
-  even &= !reg8.IsValid() || ((reg8.GetCode() % 2) == 0);
-  return even;
-}
-
-
-bool AreConsecutive(const CPURegister& reg1,
-                    const CPURegister& reg2,
-                    const CPURegister& reg3,
-                    const CPURegister& reg4) {
-  VIXL_ASSERT(reg1.IsValid());
-
-  if (!reg2.IsValid()) {
-    return true;
-  } else if (reg2.GetCode() != ((reg1.GetCode() + 1) % kNumberOfRegisters)) {
-    return false;
-  }
-
-  if (!reg3.IsValid()) {
-    return true;
-  } else if (reg3.GetCode() != ((reg2.GetCode() + 1) % kNumberOfRegisters)) {
-    return false;
-  }
-
-  if (!reg4.IsValid()) {
-    return true;
-  } else if (reg4.GetCode() != ((reg3.GetCode() + 1) % kNumberOfRegisters)) {
-    return false;
-  }
-
-  return true;
-}
-
-
-bool AreSameFormat(const VRegister& reg1,
-                   const VRegister& reg2,
-                   const VRegister& reg3,
-                   const VRegister& reg4) {
-  VIXL_ASSERT(reg1.IsValid());
-  bool match = true;
-  match &= !reg2.IsValid() || reg2.IsSameFormat(reg1);
-  match &= !reg3.IsValid() || reg3.IsSameFormat(reg1);
-  match &= !reg4.IsValid() || reg4.IsSameFormat(reg1);
-  return match;
-}
-
-
-bool AreConsecutive(const VRegister& reg1,
-                    const VRegister& reg2,
-                    const VRegister& reg3,
-                    const VRegister& reg4) {
-  VIXL_ASSERT(reg1.IsValid());
-
-  if (!reg2.IsValid()) {
-    return true;
-  } else if (reg2.GetCode() != ((reg1.GetCode() + 1) % kNumberOfVRegisters)) {
-    return false;
-  }
-
-  if (!reg3.IsValid()) {
-    return true;
-  } else if (reg3.GetCode() != ((reg2.GetCode() + 1) % kNumberOfVRegisters)) {
-    return false;
-  }
-
-  if (!reg4.IsValid()) {
-    return true;
-  } else if (reg4.GetCode() != ((reg3.GetCode() + 1) % kNumberOfVRegisters)) {
-    return false;
-  }
-
-  return true;
-}
 }  // namespace aarch64
 }  // namespace vixl
diff --git a/src/aarch64/assembler-aarch64.h b/src/aarch64/assembler-aarch64.h
index 3ccda1a6..f7aafd07 100644
--- a/src/aarch64/assembler-aarch64.h
+++ b/src/aarch64/assembler-aarch64.h
@@ -1089,18 +1089,6 @@ class Assembler : public vixl::internal::AssemblerBase {
   // zero [Armv8.3].
   void pacdza(const Register& xd);
 
-  // Pointer Authentication Code for Data address, using key A, with address in
-  // x17 and modifier in x16 [Armv8.3].
-  void pacda1716();
-
-  // Pointer Authentication Code for Data address, using key A, with address in
-  // LR and modifier in SP [Armv8.3].
-  void pacdasp();
-
-  // Pointer Authentication Code for Data address, using key A, with address in
-  // LR and a modifier of zero [Armv8.3].
-  void pacdaz();
-
   // Pointer Authentication Code for Data address, using key B [Armv8.3].
   void pacdb(const Register& xd, const Register& xn);
 
@@ -1108,18 +1096,6 @@ class Assembler : public vixl::internal::AssemblerBase {
   // zero [Armv8.3].
   void pacdzb(const Register& xd);
 
-  // Pointer Authentication Code for Data address, using key B, with address in
-  // x17 and modifier in x16 [Armv8.3].
-  void pacdb1716();
-
-  // Pointer Authentication Code for Data address, using key B, with address in
-  // LR and modifier in SP [Armv8.3].
-  void pacdbsp();
-
-  // Pointer Authentication Code for Data address, using key B, with address in
-  // LR and a modifier of zero [Armv8.3].
-  void pacdbz();
-
   // Pointer Authentication Code, using Generic key [Armv8.3].
   void pacga(const Register& xd, const Register& xn, const Register& xm);
 
@@ -1167,36 +1143,12 @@ class Assembler : public vixl::internal::AssemblerBase {
   // Authenticate Data address, using key A and a modifier of zero [Armv8.3].
   void autdza(const Register& xd);
 
-  // Authenticate Data address, using key A, with address in x17 and modifier in
-  // x16 [Armv8.3].
-  void autda1716();
-
-  // Authenticate Data address, using key A, with address in LR and modifier in
-  // SP [Armv8.3].
-  void autdasp();
-
-  // Authenticate Data address, using key A, with address in LR and a modifier
-  // of zero [Armv8.3].
-  void autdaz();
-
   // Authenticate Data address, using key B [Armv8.3].
   void autdb(const Register& xd, const Register& xn);
 
   // Authenticate Data address, using key B and a modifier of zero [Armv8.3].
   void autdzb(const Register& xd);
 
-  // Authenticate Data address, using key B, with address in x17 and modifier in
-  // x16 [Armv8.3].
-  void autdb1716();
-
-  // Authenticate Data address, using key B, with address in LR and modifier in
-  // SP [Armv8.3].
-  void autdbsp();
-
-  // Authenticate Data address, using key B, with address in LR and a modifier
-  // of zero [Armv8.3].
-  void autdbz();
-
   // Strip Pointer Authentication Code of Data address [Armv8.3].
   void xpacd(const Register& xd);
 
@@ -2112,6 +2064,22 @@ class Assembler : public vixl::internal::AssemblerBase {
   // Prefetch from pc + imm19 << 2.
   void prfm(PrefetchOperation op, int64_t imm19);
 
+  // Prefetch memory (allowing unallocated hints).
+  void prfm(int op,
+            const MemOperand& addr,
+            LoadStoreScalingOption option = PreferScaledOffset);
+
+  // Prefetch memory (with unscaled offset, allowing unallocated hints).
+  void prfum(int op,
+             const MemOperand& addr,
+             LoadStoreScalingOption option = PreferUnscaledOffset);
+
+  // Prefetch memory in the literal pool (allowing unallocated hints).
+  void prfm(int op, RawLiteral* literal);
+
+  // Prefetch from pc + imm19 << 2 (allowing unallocated hints).
+  void prfm(int op, int64_t imm19);
+
   // Move instructions. The default shift of -1 indicates that the move
   // instruction will calculate an appropriate 16-bit immediate and left shift
   // that is equal to the 64-bit immediate argument. If an explicit left shift
@@ -3618,6 +3586,2240 @@ class Assembler : public vixl::internal::AssemblerBase {
              const VRegister& vm,
              int rot);
 
+  // Scalable Vector Extensions.
+
+  // Absolute value (predicated).
+  void abs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Add vectors (predicated).
+  void add(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Add vectors (unpredicated).
+  void add(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Add immediate (unpredicated).
+  void add(const ZRegister& zd, const ZRegister& zn, int imm8, int shift = -1);
+
+  // Add multiple of predicate register size to scalar register.
+  void addpl(const Register& xd, const Register& xn, int imm6);
+
+  // Add multiple of vector register size to scalar register.
+  void addvl(const Register& xd, const Register& xn, int imm6);
+
+  // Compute vector address.
+  void adr(const ZRegister& zd, const SVEMemOperand& addr);
+
+  // Bitwise AND predicates.
+  void and_(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Bitwise AND vectors (predicated).
+  void and_(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Bitwise AND with immediate (unpredicated).
+  void and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
+
+  // Bitwise AND vectors (unpredicated).
+  void and_(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Bitwise AND predicates.
+  void ands(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Bitwise AND reduction to scalar.
+  void andv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Arithmetic shift right by immediate (predicated).
+  void asr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           int shift);
+
+  // Arithmetic shift right by 64-bit wide elements (predicated).
+  void asr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Arithmetic shift right by immediate (unpredicated).
+  void asr(const ZRegister& zd, const ZRegister& zn, int shift);
+
+  // Arithmetic shift right by 64-bit wide elements (unpredicated).
+  void asr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Arithmetic shift right for divide by immediate (predicated).
+  void asrd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            int shift);
+
+  // Reversed arithmetic shift right by vector (predicated).
+  void asrr(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Bitwise clear predicates.
+  void bic(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm);
+
+  // Bitwise clear vectors (predicated).
+  void bic(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Bitwise clear bits using immediate (unpredicated).
+  void bic(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
+
+  // Bitwise clear vectors (unpredicated).
+  void bic(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Bitwise clear predicates.
+  void bics(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Break after first true condition.
+  void brka(const PRegisterWithLaneSize& pd,
+            const PRegister& pg,
+            const PRegisterWithLaneSize& pn);
+
+  // Break after first true condition.
+  void brkas(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn);
+
+  // Break before first true condition.
+  void brkb(const PRegisterWithLaneSize& pd,
+            const PRegister& pg,
+            const PRegisterWithLaneSize& pn);
+
+  // Break before first true condition.
+  void brkbs(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn);
+
+  // Propagate break to next partition.
+  void brkn(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Propagate break to next partition.
+  void brkns(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn,
+             const PRegisterWithLaneSize& pm);
+
+  // Break after first true condition, propagating from previous partition.
+  void brkpa(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn,
+             const PRegisterWithLaneSize& pm);
+
+  // Break after first true condition, propagating from previous partition.
+  void brkpas(const PRegisterWithLaneSize& pd,
+              const PRegisterZ& pg,
+              const PRegisterWithLaneSize& pn,
+              const PRegisterWithLaneSize& pm);
+
+  // Break before first true condition, propagating from previous partition.
+  void brkpb(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn,
+             const PRegisterWithLaneSize& pm);
+
+  // Break before first true condition, propagating from previous partition.
+  void brkpbs(const PRegisterWithLaneSize& pd,
+              const PRegisterZ& pg,
+              const PRegisterWithLaneSize& pn,
+              const PRegisterWithLaneSize& pm);
+
+  // Conditionally extract element after last to general-purpose register.
+  void clasta(const Register& rd,
+              const PRegister& pg,
+              const Register& rn,
+              const ZRegister& zm);
+
+  // Conditionally extract element after last to SIMD&FP scalar register.
+  void clasta(const VRegister& vd,
+              const PRegister& pg,
+              const VRegister& vn,
+              const ZRegister& zm);
+
+  // Conditionally extract element after last to vector register.
+  void clasta(const ZRegister& zd,
+              const PRegister& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+
+  // Conditionally extract last element to general-purpose register.
+  void clastb(const Register& rd,
+              const PRegister& pg,
+              const Register& rn,
+              const ZRegister& zm);
+
+  // Conditionally extract last element to SIMD&FP scalar register.
+  void clastb(const VRegister& vd,
+              const PRegister& pg,
+              const VRegister& vn,
+              const ZRegister& zm);
+
+  // Conditionally extract last element to vector register.
+  void clastb(const ZRegister& zd,
+              const PRegister& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+
+  // Count leading sign bits (predicated).
+  void cls(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Count leading zero bits (predicated).
+  void clz(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  void cmp(Condition cond,
+           const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Compare vector to 64-bit wide elements.
+  void cmpeq(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmpeq(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             int imm5);
+
+  // Compare vector to 64-bit wide elements.
+  void cmpge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmpge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             int imm5);
+
+  // Compare vector to 64-bit wide elements.
+  void cmpgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmpgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             int imm5);
+
+  // Compare vector to 64-bit wide elements.
+  void cmphi(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmphi(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             unsigned imm7);
+
+  // Compare vector to 64-bit wide elements.
+  void cmphs(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmphs(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             unsigned imm7);
+
+  // Compare vector to 64-bit wide elements.
+  void cmple(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmple(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             int imm5);
+
+  // Compare vector to 64-bit wide elements.
+  void cmplo(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmplo(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             unsigned imm7);
+
+  // Compare vector to 64-bit wide elements.
+  void cmpls(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmpls(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             unsigned imm7);
+
+  // Compare vector to 64-bit wide elements.
+  void cmplt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmplt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             int imm5);
+
+  // Compare vector to 64-bit wide elements.
+  void cmpne(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Compare vector to immediate.
+  void cmpne(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             int imm5);
+
+  // Logically invert boolean condition in vector (predicated).
+  void cnot(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Count non-zero bits (predicated).
+  void cnt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Set scalar to multiple of predicate constraint element count.
+  void cntb(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Set scalar to multiple of predicate constraint element count.
+  void cntd(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Set scalar to multiple of predicate constraint element count.
+  void cnth(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Set scalar to active predicate element count.
+  void cntp(const Register& xd,
+            const PRegister& pg,
+            const PRegisterWithLaneSize& pn);
+
+  // Set scalar to multiple of predicate constraint element count.
+  void cntw(const Register& rd, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Shuffle active elements of vector to the right and fill with zero.
+  void compact(const ZRegister& zd, const PRegister& pg, const ZRegister& zn);
+
+  // Copy signed integer immediate to vector elements (predicated).
+  void cpy(const ZRegister& zd, const PRegister& pg, int imm8, int shift = -1);
+
+  // Copy general-purpose register to vector elements (predicated).
+  void cpy(const ZRegister& zd, const PRegisterM& pg, const Register& rn);
+
+  // Copy SIMD&FP scalar register to vector elements (predicated).
+  void cpy(const ZRegister& zd, const PRegisterM& pg, const VRegister& vn);
+
+  // Compare and terminate loop.
+  void ctermeq(const Register& rn, const Register& rm);
+
+  // Compare and terminate loop.
+  void ctermne(const Register& rn, const Register& rm);
+
+  // Decrement scalar by multiple of predicate constraint element count.
+  void decb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Decrement scalar by multiple of predicate constraint element count.
+  void decd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Decrement vector by multiple of predicate constraint element count.
+  void decd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Decrement scalar by multiple of predicate constraint element count.
+  void dech(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Decrement vector by multiple of predicate constraint element count.
+  void dech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Decrement scalar by active predicate element count.
+  void decp(const Register& rdn, const PRegisterWithLaneSize& pg);
+
+  // Decrement vector by active predicate element count.
+  void decp(const ZRegister& zdn, const PRegister& pg);
+
+  // Decrement scalar by multiple of predicate constraint element count.
+  void decw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Decrement vector by multiple of predicate constraint element count.
+  void decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Broadcast general-purpose register to vector elements (unpredicated).
+  void dup(const ZRegister& zd, const Register& xn);
+
+  // Broadcast indexed element to vector (unpredicated).
+  void dup(const ZRegister& zd, const ZRegister& zn, unsigned index);
+
+  // As for movz/movk/movn, if the default shift of -1 is specified to dup, the
+  // assembler will pick an appropriate immediate and left shift that is
+  // equivalent to the immediate argument. If an explicit left shift is
+  // specified (0 or 8), the immediate must be a signed 8-bit integer.
+
+  // Broadcast signed immediate to vector elements (unpredicated).
+  void dup(const ZRegister& zd, int imm8, int shift = -1);
+
+  // Broadcast logical bitmask immediate to vector (unpredicated).
+  void dupm(const ZRegister& zd, uint64_t imm);
+
+  // Bitwise exclusive OR with inverted immediate (unpredicated).
+  void eon(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
+
+  // Bitwise exclusive OR predicates.
+  void eor(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm);
+
+  // Bitwise exclusive OR vectors (predicated).
+  void eor(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Bitwise exclusive OR with immediate (unpredicated).
+  void eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
+
+  // Bitwise exclusive OR vectors (unpredicated).
+  void eor(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Bitwise exclusive OR predicates.
+  void eors(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Bitwise XOR reduction to scalar.
+  void eorv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Extract vector from pair of vectors.
+  void ext(const ZRegister& zd,
+           const ZRegister& zn,
+           const ZRegister& zm,
+           unsigned offset);
+
+  // Floating-point absolute difference (predicated).
+  void fabd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point absolute value (predicated).
+  void fabs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point absolute compare vectors.
+  void facge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point absolute compare vectors.
+  void facgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point add immediate (predicated).
+  void fadd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm);
+
+  // Floating-point add vector (predicated).
+  void fadd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point add vector (unpredicated).
+  void fadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Floating-point add strictly-ordered reduction, accumulating in scalar.
+  void fadda(const VRegister& vd,
+             const PRegister& pg,
+             const VRegister& vn,
+             const ZRegister& zm);
+
+  // Floating-point add recursive reduction to scalar.
+  void faddv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Floating-point complex add with rotate (predicated).
+  void fcadd(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             int rot);
+
+  // Floating-point compare vector with zero.
+  void fcmeq(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero);
+
+  // Floating-point compare vectors.
+  void fcmeq(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point compare vector with zero.
+  void fcmge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero);
+
+  // Floating-point compare vectors.
+  void fcmge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point compare vector with zero.
+  void fcmgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero);
+
+  // Floating-point compare vectors.
+  void fcmgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point complex multiply-add with rotate (predicated).
+  void fcmla(const ZRegister& zda,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             int rot);
+
+  // Floating-point complex multiply-add by indexed values with rotate.
+  void fcmla(const ZRegister& zda,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             int index,
+             int rot);
+
+  // Floating-point compare vector with zero.
+  void fcmle(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero);
+
+  // Floating-point compare vector with zero.
+  void fcmlt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero);
+
+  // Floating-point compare vector with zero.
+  void fcmne(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero);
+
+  // Floating-point compare vectors.
+  void fcmne(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point compare vectors.
+  void fcmuo(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Copy floating-point immediate to vector elements (predicated).
+  void fcpy(const ZRegister& zd, const PRegisterM& pg, double imm);
+
+  // Copy half-precision floating-point immediate to vector elements
+  // (predicated).
+  void fcpy(const ZRegister& zd, const PRegisterM& pg, Float16 imm) {
+    fcpy(zd, pg, FPToDouble(imm, kIgnoreDefaultNaN));
+  }
+
+  // Floating-point convert precision (predicated).
+  void fcvt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point convert to signed integer, rounding toward zero
+  // (predicated).
+  void fcvtzs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point convert to unsigned integer, rounding toward zero
+  // (predicated).
+  void fcvtzu(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point divide by vector (predicated).
+  void fdiv(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point reversed divide by vector (predicated).
+  void fdivr(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Broadcast floating-point immediate to vector elements.
+  void fdup(const ZRegister& zd, double imm);
+
+  // Broadcast half-precision floating-point immediate to vector elements.
+  void fdup(const ZRegister& zd, Float16 imm) {
+    fdup(zd, FPToDouble(imm, kIgnoreDefaultNaN));
+  }
+
+  // Floating-point exponential accelerator.
+  void fexpa(const ZRegister& zd, const ZRegister& zn);
+
+  // Floating-point fused multiply-add vectors (predicated), writing
+  // multiplicand [Zdn = Za + Zdn * Zm].
+  void fmad(const ZRegister& zdn,
+            const PRegisterM& pg,
+            const ZRegister& zm,
+            const ZRegister& za);
+
+  // Floating-point maximum with immediate (predicated).
+  void fmax(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm);
+
+  // Floating-point maximum (predicated).
+  void fmax(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point maximum number with immediate (predicated).
+  void fmaxnm(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              double imm);
+
+  // Floating-point maximum number (predicated).
+  void fmaxnm(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+
+  // Floating-point maximum number recursive reduction to scalar.
+  void fmaxnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Floating-point maximum recursive reduction to scalar.
+  void fmaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Floating-point minimum with immediate (predicated).
+  void fmin(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm);
+
+  // Floating-point minimum (predicated).
+  void fmin(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point minimum number with immediate (predicated).
+  void fminnm(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              double imm);
+
+  // Floating-point minimum number (predicated).
+  void fminnm(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+
+  // Floating-point minimum number recursive reduction to scalar.
+  void fminnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Floating-point minimum recursive reduction to scalar.
+  void fminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Floating-point fused multiply-add vectors (predicated), writing addend
+  // [Zda = Zda + Zn * Zm].
+  void fmla(const ZRegister& zda,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point fused multiply-add by indexed elements
+  // (Zda = Zda + Zn * Zm[indexed]).
+  void fmla(const ZRegister& zda,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            int index);
+
+  // Floating-point fused multiply-subtract vectors (predicated), writing
+  // addend [Zda = Zda + -Zn * Zm].
+  void fmls(const ZRegister& zda,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point fused multiply-subtract by indexed elements
+  // (Zda = Zda + -Zn * Zm[indexed]).
+  void fmls(const ZRegister& zda,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            int index);
+
+  // Move 8-bit floating-point immediate to vector elements (unpredicated).
+  void fmov(const ZRegister& zd, double imm);
+
+  // Move 8-bit floating-point immediate to vector elements (predicated).
+  void fmov(const ZRegister& zd, const PRegisterM& pg, double imm);
+
+  // Floating-point fused multiply-subtract vectors (predicated), writing
+  // multiplicand [Zdn = Za + -Zdn * Zm].
+  void fmsb(const ZRegister& zdn,
+            const PRegisterM& pg,
+            const ZRegister& zm,
+            const ZRegister& za);
+
+  // Floating-point multiply by immediate (predicated).
+  void fmul(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm);
+
+  // Floating-point multiply vectors (predicated).
+  void fmul(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point multiply by indexed elements.
+  void fmul(const ZRegister& zd,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            unsigned index);
+
+  // Floating-point multiply vectors (unpredicated).
+  void fmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Floating-point multiply-extended vectors (predicated).
+  void fmulx(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point negate (predicated).
+  void fneg(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point negated fused multiply-add vectors (predicated), writing
+  // multiplicand [Zdn = -Za + -Zdn * Zm].
+  void fnmad(const ZRegister& zdn,
+             const PRegisterM& pg,
+             const ZRegister& zm,
+             const ZRegister& za);
+
+  // Floating-point negated fused multiply-add vectors (predicated), writing
+  // addend [Zda = -Zda + -Zn * Zm].
+  void fnmla(const ZRegister& zda,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point negated fused multiply-subtract vectors (predicated),
+  // writing addend [Zda = -Zda + Zn * Zm].
+  void fnmls(const ZRegister& zda,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point negated fused multiply-subtract vectors (predicated),
+  // writing multiplicand [Zdn = -Za + Zdn * Zm].
+  void fnmsb(const ZRegister& zdn,
+             const PRegisterM& pg,
+             const ZRegister& zm,
+             const ZRegister& za);
+
+  // Floating-point reciprocal estimate (unpredicated).
+  void frecpe(const ZRegister& zd, const ZRegister& zn);
+
+  // Floating-point reciprocal step (unpredicated).
+  void frecps(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Floating-point reciprocal exponent (predicated).
+  void frecpx(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point round to integral value (predicated).
+  void frinta(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point round to integral value (predicated).
+  void frinti(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point round to integral value (predicated).
+  void frintm(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point round to integral value (predicated).
+  void frintn(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point round to integral value (predicated).
+  void frintp(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point round to integral value (predicated).
+  void frintx(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point round to integral value (predicated).
+  void frintz(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point reciprocal square root estimate (unpredicated).
+  void frsqrte(const ZRegister& zd, const ZRegister& zn);
+
+  // Floating-point reciprocal square root step (unpredicated).
+  void frsqrts(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Floating-point adjust exponent by vector (predicated).
+  void fscale(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+
+  // Floating-point square root (predicated).
+  void fsqrt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Floating-point subtract immediate (predicated).
+  void fsub(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm);
+
+  // Floating-point subtract vectors (predicated).
+  void fsub(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Floating-point subtract vectors (unpredicated).
+  void fsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Floating-point reversed subtract from immediate (predicated).
+  void fsubr(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             double imm);
+
+  // Floating-point reversed subtract vectors (predicated).
+  void fsubr(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Floating-point trigonometric multiply-add coefficient.
+  void ftmad(const ZRegister& zd,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             int imm3);
+
+  // Floating-point trigonometric starting value.
+  void ftsmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Floating-point trigonometric select coefficient.
+  void ftssel(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Increment scalar by multiple of predicate constraint element count.
+  void incb(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Increment scalar by multiple of predicate constraint element count.
+  void incd(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Increment vector by multiple of predicate constraint element count.
+  void incd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Increment scalar by multiple of predicate constraint element count.
+  void inch(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Increment vector by multiple of predicate constraint element count.
+  void inch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Increment scalar by active predicate element count.
+  void incp(const Register& rdn, const PRegisterWithLaneSize& pg);
+
+  // Increment vector by active predicate element count.
+  void incp(const ZRegister& zdn, const PRegister& pg);
+
+  // Increment scalar by multiple of predicate constraint element count.
+  void incw(const Register& xdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Increment vector by multiple of predicate constraint element count.
+  void incw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Create index starting from and incremented by immediate.
+  void index(const ZRegister& zd, int start, int step);
+
+  // Create index starting from and incremented by general-purpose register.
+  void index(const ZRegister& zd, const Register& rn, const Register& rm);
+
+  // Create index starting from general-purpose register and incremented by
+  // immediate.
+  void index(const ZRegister& zd, const Register& rn, int imm5);
+
+  // Create index starting from immediate and incremented by general-purpose
+  // register.
+  void index(const ZRegister& zd, int imm5, const Register& rm);
+
+  // Insert general-purpose register in shifted vector.
+  void insr(const ZRegister& zdn, const Register& rm);
+
+  // Insert SIMD&FP scalar register in shifted vector.
+  void insr(const ZRegister& zdn, const VRegister& vm);
+
+  // Extract element after last to general-purpose register.
+  void lasta(const Register& rd, const PRegister& pg, const ZRegister& zn);
+
+  // Extract element after last to SIMD&FP scalar register.
+  void lasta(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Extract last element to general-purpose register.
+  void lastb(const Register& rd, const PRegister& pg, const ZRegister& zn);
+
+  // Extract last element to SIMD&FP scalar register.
+  void lastb(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Contiguous/gather load bytes to vector.
+  void ld1b(const ZRegister& zt,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous/gather load halfwords to vector.
+  void ld1h(const ZRegister& zt,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous/gather load words to vector.
+  void ld1w(const ZRegister& zt,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous/gather load doublewords to vector.
+  void ld1d(const ZRegister& zt,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // TODO: Merge other loads into the SVEMemOperand versions.
+
+  // Load and broadcast unsigned byte to vector.
+  void ld1rb(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+
+  // Load and broadcast unsigned halfword to vector.
+  void ld1rh(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+
+  // Load and broadcast unsigned word to vector.
+  void ld1rw(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+
+  // Load and broadcast doubleword to vector.
+  void ld1rd(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+
+  // Contiguous load and replicate sixteen bytes.
+  void ld1rqb(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load and replicate eight halfwords.
+  void ld1rqh(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load and replicate four words.
+  void ld1rqw(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load and replicate two doublewords.
+  void ld1rqd(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Load and broadcast signed byte to vector.
+  void ld1rsb(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Load and broadcast signed halfword to vector.
+  void ld1rsh(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Load and broadcast signed word to vector.
+  void ld1rsw(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous/gather load signed bytes to vector.
+  void ld1sb(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+
+  // Contiguous/gather load signed halfwords to vector.
+  void ld1sh(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+
+  // Contiguous/gather load signed words to vector.
+  void ld1sw(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+
+  // TODO: Merge other loads into the SVEMemOperand versions.
+
+  // Contiguous load two-byte structures to two vectors.
+  void ld2b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load two-halfword structures to two vectors.
+  void ld2h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load two-word structures to two vectors.
+  void ld2w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load two-doubleword structures to two vectors.
+  void ld2d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load three-byte structures to three vectors.
+  void ld3b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load three-halfword structures to three vectors.
+  void ld3h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load three-word structures to three vectors.
+  void ld3w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load three-doubleword structures to three vectors.
+  void ld3d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load four-byte structures to four vectors.
+  void ld4b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load four-halfword structures to four vectors.
+  void ld4h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load four-word structures to four vectors.
+  void ld4w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load four-doubleword structures to four vectors.
+  void ld4d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous load first-fault unsigned bytes to vector.
+  void ldff1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load first-fault unsigned halfwords to vector.
+  void ldff1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load first-fault unsigned words to vector.
+  void ldff1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load first-fault doublewords to vector.
+  void ldff1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load first-fault signed bytes to vector.
+  void ldff1sb(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+
+  // Contiguous load first-fault signed halfwords to vector.
+  void ldff1sh(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+
+  // Contiguous load first-fault signed words to vector.
+  void ldff1sw(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+
+  // Gather load first-fault unsigned bytes to vector.
+  void ldff1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const Register& xn,
+              const ZRegister& zm);
+
+  // Gather load first-fault unsigned bytes to vector (immediate index).
+  void ldff1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const ZRegister& zn,
+              int imm5);
+
+  // Gather load first-fault doublewords to vector (vector index).
+  void ldff1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const Register& xn,
+              const ZRegister& zm);
+
+  // Gather load first-fault doublewords to vector (immediate index).
+  void ldff1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const ZRegister& zn,
+              int imm5);
+
+  // Gather load first-fault unsigned halfwords to vector (vector index).
+  void ldff1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const Register& xn,
+              const ZRegister& zm);
+
+  // Gather load first-fault unsigned halfwords to vector (immediate index).
+  void ldff1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const ZRegister& zn,
+              int imm5);
+
+  // Gather load first-fault signed bytes to vector (vector index).
+  void ldff1sb(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const Register& xn,
+               const ZRegister& zm);
+
+  // Gather load first-fault signed bytes to vector (immediate index).
+  void ldff1sb(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const ZRegister& zn,
+               int imm5);
+
+  // Gather load first-fault signed halfwords to vector (vector index).
+  void ldff1sh(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const Register& xn,
+               const ZRegister& zm);
+
+  // Gather load first-fault signed halfwords to vector (immediate index).
+  void ldff1sh(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const ZRegister& zn,
+               int imm5);
+
+  // Gather load first-fault signed words to vector (vector index).
+  void ldff1sw(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const Register& xn,
+               const ZRegister& zm);
+
+  // Gather load first-fault signed words to vector (immediate index).
+  void ldff1sw(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const ZRegister& zn,
+               int imm5);
+
+  // Gather load first-fault unsigned words to vector (vector index).
+  void ldff1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const Register& xn,
+              const ZRegister& zm);
+
+  // Gather load first-fault unsigned words to vector (immediate index).
+  void ldff1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const ZRegister& zn,
+              int imm5);
+
+  // Contiguous load non-fault unsigned bytes to vector (immediate index).
+  void ldnf1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load non-fault doublewords to vector (immediate index).
+  void ldnf1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load non-fault unsigned halfwords to vector (immediate
+  // index).
+  void ldnf1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load non-fault signed bytes to vector (immediate index).
+  void ldnf1sb(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+
+  // Contiguous load non-fault signed halfwords to vector (immediate index).
+  void ldnf1sh(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+
+  // Contiguous load non-fault signed words to vector (immediate index).
+  void ldnf1sw(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+
+  // Contiguous load non-fault unsigned words to vector (immediate index).
+  void ldnf1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load non-temporal bytes to vector.
+  void ldnt1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load non-temporal halfwords to vector.
+  void ldnt1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load non-temporal words to vector.
+  void ldnt1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous load non-temporal doublewords to vector.
+  void ldnt1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+
+  // Load SVE predicate/vector register.
+  void ldr(const CPURegister& rt, const SVEMemOperand& addr);
+
+  // Logical shift left by immediate (predicated).
+  void lsl(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           int shift);
+
+  // Logical shift left by 64-bit wide elements (predicated).
+  void lsl(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Logical shift left by immediate (unpredicated).
+  void lsl(const ZRegister& zd, const ZRegister& zn, int shift);
+
+  // Logical shift left by 64-bit wide elements (unpredicated).
+  void lsl(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Reversed logical shift left by vector (predicated).
+  void lslr(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Logical shift right by immediate (predicated).
+  void lsr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           int shift);
+
+  // Logical shift right by 64-bit wide elements (predicated).
+  void lsr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Logical shift right by immediate (unpredicated).
+  void lsr(const ZRegister& zd, const ZRegister& zn, int shift);
+
+  // Logical shift right by 64-bit wide elements (unpredicated).
+  void lsr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Reversed logical shift right by vector (predicated).
+  void lsrr(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Bitwise invert predicate.
+  void not_(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn);
+
+  // Bitwise invert predicate, setting the condition flags.
+  void nots(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn);
+
+  // Multiply-add vectors (predicated), writing multiplicand
+  // [Zdn = Za + Zdn * Zm].
+  void mad(const ZRegister& zdn,
+           const PRegisterM& pg,
+           const ZRegister& zm,
+           const ZRegister& za);
+
+  // Multiply-add vectors (predicated), writing addend
+  // [Zda = Zda + Zn * Zm].
+  void mla(const ZRegister& zda,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Multiply-subtract vectors (predicated), writing addend
+  // [Zda = Zda - Zn * Zm].
+  void mls(const ZRegister& zda,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Move predicates (unpredicated)
+  void mov(const PRegister& pd, const PRegister& pn);
+
+  // Move predicates (merging)
+  void mov(const PRegisterWithLaneSize& pd,
+           const PRegisterM& pg,
+           const PRegisterWithLaneSize& pn);
+
+  // Move predicates (zeroing)
+  void mov(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn);
+
+  // Move general-purpose register to vector elements (unpredicated)
+  void mov(const ZRegister& zd, const Register& xn);
+
+  // Move SIMD&FP scalar register to vector elements (unpredicated)
+  void mov(const ZRegister& zd, const VRegister& vn);
+
+  // Move vector register (unpredicated)
+  void mov(const ZRegister& zd, const ZRegister& zn);
+
+  // Move indexed element to vector elements (unpredicated)
+  void mov(const ZRegister& zd, const ZRegister& zn, unsigned index);
+
+  // Move general-purpose register to vector elements (predicated)
+  void mov(const ZRegister& zd, const PRegisterM& pg, const Register& rn);
+
+  // Move SIMD&FP scalar register to vector elements (predicated)
+  void mov(const ZRegister& zd, const PRegisterM& pg, const VRegister& vn);
+
+  // Move vector elements (predicated)
+  void mov(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Move signed integer immediate to vector elements (predicated)
+  void mov(const ZRegister& zd, const PRegister& pg, int imm8, int shift = -1);
+
+  // Move signed immediate to vector elements (unpredicated).
+  void mov(const ZRegister& zd, int imm8, int shift);
+
+  // Move logical bitmask immediate to vector (unpredicated).
+  void mov(const ZRegister& zd, uint64_t imm);
+
+  // Move predicate (unpredicated), setting the condition flags
+  void movs(const PRegister& pd, const PRegister& pn);
+
+  // Move predicates (zeroing), setting the condition flags
+  void movs(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn);
+
+  // Move prefix (predicated).
+  void movprfx(const ZRegister& zd, const PRegister& pg, const ZRegister& zn);
+
+  // Move prefix (unpredicated).
+  void movprfx(const ZRegister& zd, const ZRegister& zn);
+
+  // Multiply-subtract vectors (predicated), writing multiplicand
+  // [Zdn = Za - Zdn * Zm].
+  void msb(const ZRegister& zdn,
+           const PRegisterM& pg,
+           const ZRegister& zm,
+           const ZRegister& za);
+
+  // Multiply vectors (predicated).
+  void mul(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Multiply by immediate (unpredicated).
+  void mul(const ZRegister& zd, const ZRegister& zn, int imm8);
+
+  // Bitwise NAND predicates.
+  void nand(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Bitwise NAND predicates.
+  void nands(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn,
+             const PRegisterWithLaneSize& pm);
+
+  // Negate (predicated).
+  void neg(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Bitwise NOR predicates.
+  void nor(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm);
+
+  // Bitwise NOR predicates.
+  void nors(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Bitwise invert vector (predicated).
+  void not_(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Bitwise OR inverted predicate.
+  void orn(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm);
+
+  // Bitwise OR inverted predicate.
+  void orns(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Bitwise OR with inverted immediate (unpredicated).
+  void orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
+
+  // Bitwise OR predicate.
+  void orr(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm);
+
+  // Bitwise OR vectors (predicated).
+  void orr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Bitwise OR with immediate (unpredicated).
+  void orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm);
+
+  // Bitwise OR vectors (unpredicated).
+  void orr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Bitwise OR predicate.
+  void orrs(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Bitwise OR reduction to scalar.
+  void orv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Set all predicate elements to false.
+  void pfalse(const PRegisterWithLaneSize& pd);
+
+  // Set the first active predicate element to true.
+  void pfirst(const PRegisterWithLaneSize& pd,
+              const PRegister& pg,
+              const PRegisterWithLaneSize& pn);
+
+  // Find next active predicate.
+  void pnext(const PRegisterWithLaneSize& pd,
+             const PRegister& pg,
+             const PRegisterWithLaneSize& pn);
+
+  // Prefetch bytes.
+  void prfb(PrefetchOperation prfop,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Prefetch halfwords.
+  void prfh(PrefetchOperation prfop,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Prefetch words.
+  void prfw(PrefetchOperation prfop,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Prefetch doublewords.
+  void prfd(PrefetchOperation prfop,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Set condition flags for predicate.
+  void ptest(const PRegister& pg, const PRegisterWithLaneSize& pn);
+
+  // Initialise predicate from named constraint.
+  void ptrue(const PRegisterWithLaneSize& pd, int pattern = SVE_ALL);
+
+  // Initialise predicate from named constraint.
+  void ptrues(const PRegisterWithLaneSize& pd, int pattern = SVE_ALL);
+
+  // Unpack and widen half of predicate.
+  void punpkhi(const PRegisterWithLaneSize& pd,
+               const PRegisterWithLaneSize& pn);
+
+  // Unpack and widen half of predicate.
+  void punpklo(const PRegisterWithLaneSize& pd,
+               const PRegisterWithLaneSize& pn);
+
+  // Reverse bits (predicated).
+  void rbit(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Read the first-fault register.
+  void rdffr(const PRegisterWithLaneSize& pd);
+
+  // Return predicate of succesfully loaded elements.
+  void rdffr(const PRegisterWithLaneSize& pd, const PRegisterZ& pg);
+
+  // Return predicate of succesfully loaded elements.
+  void rdffrs(const PRegisterWithLaneSize& pd, const PRegisterZ& pg);
+
+  // Read multiple of vector register size to scalar register.
+  void rdvl(const Register& xd, int imm6);
+
+  // Reverse all elements in a predicate.
+  void rev(const PRegisterWithLaneSize& pd, const PRegisterWithLaneSize& pn);
+
+  // Reverse all elements in a vector (unpredicated).
+  void rev(const ZRegister& zd, const ZRegister& zn);
+
+  // Reverse bytes / halfwords / words within elements (predicated).
+  void revb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Reverse bytes / halfwords / words within elements (predicated).
+  void revh(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Reverse bytes / halfwords / words within elements (predicated).
+  void revw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Signed absolute difference (predicated).
+  void sabd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Signed add reduction to scalar.
+  void saddv(const VRegister& dd, const PRegister& pg, const ZRegister& zn);
+
+  // Signed integer convert to floating-point (predicated).
+  void scvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Signed divide (predicated).
+  void sdiv(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Signed reversed divide (predicated).
+  void sdivr(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Signed dot product by indexed quadtuplet.
+  void sdot(const ZRegister& zda,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            int index);
+
+  // Signed dot product.
+  void sdot(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm);
+
+  // Conditionally select elements from two predicates.
+  void sel(const PRegisterWithLaneSize& pd,
+           const PRegister& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm);
+
+  // Conditionally select elements from two vectors.
+  void sel(const ZRegister& zd,
+           const PRegister& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Initialise the first-fault register to all true.
+  void setffr();
+
+  // Signed maximum vectors (predicated).
+  void smax(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Signed maximum with immediate (unpredicated).
+  void smax(const ZRegister& zd, const ZRegister& zn, int imm8);
+
+  // Signed maximum reduction to scalar.
+  void smaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Signed minimum vectors (predicated).
+  void smin(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Signed minimum with immediate (unpredicated).
+  void smin(const ZRegister& zd, const ZRegister& zn, int imm8);
+
+  // Signed minimum reduction to scalar.
+  void sminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Signed multiply returning high half (predicated).
+  void smulh(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Splice two vectors under predicate control.
+  void splice(const ZRegister& zd,
+              const PRegister& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+
+  // Signed saturating add vectors (unpredicated).
+  void sqadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Signed saturating add immediate (unpredicated).
+  void sqadd(const ZRegister& zd,
+             const ZRegister& zn,
+             int imm8,
+             int shift = -1);
+
+  // Signed saturating decrement scalar by multiple of 8-bit predicate
+  // constraint element count.
+  void sqdecb(const Register& xd,
+              const Register& wn,
+              int pattern,
+              int multiplier);
+
+  // Signed saturating decrement scalar by multiple of 8-bit predicate
+  // constraint element count.
+  void sqdecb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating decrement scalar by multiple of 64-bit predicate
+  // constraint element count.
+  void sqdecd(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1);
+
+  // Signed saturating decrement scalar by multiple of 64-bit predicate
+  // constraint element count.
+  void sqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating decrement vector by multiple of 64-bit predicate
+  // constraint element count.
+  void sqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating decrement scalar by multiple of 16-bit predicate
+  // constraint element count.
+  void sqdech(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1);
+
+  // Signed saturating decrement scalar by multiple of 16-bit predicate
+  // constraint element count.
+  void sqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating decrement vector by multiple of 16-bit predicate
+  // constraint element count.
+  void sqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating decrement scalar by active predicate element count.
+  void sqdecp(const Register& xd,
+              const PRegisterWithLaneSize& pg,
+              const Register& wn);
+
+  // Signed saturating decrement scalar by active predicate element count.
+  void sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg);
+
+  // Signed saturating decrement vector by active predicate element count.
+  void sqdecp(const ZRegister& zdn, const PRegister& pg);
+
+  // Signed saturating decrement scalar by multiple of 32-bit predicate
+  // constraint element count.
+  void sqdecw(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1);
+
+  // Signed saturating decrement scalar by multiple of 32-bit predicate
+  // constraint element count.
+  void sqdecw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating decrement vector by multiple of 32-bit predicate
+  // constraint element count.
+  void sqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating increment scalar by multiple of 8-bit predicate
+  // constraint element count.
+  void sqincb(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1);
+
+  // Signed saturating increment scalar by multiple of 8-bit predicate
+  // constraint element count.
+  void sqincb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating increment scalar by multiple of 64-bit predicate
+  // constraint element count.
+  void sqincd(const Register& xd,
+              const Register& wn,
+              int pattern,
+              int multiplier);
+
+  // Signed saturating increment scalar by multiple of 64-bit predicate
+  // constraint element count.
+  void sqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating increment vector by multiple of 64-bit predicate
+  // constraint element count.
+  void sqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating increment scalar by multiple of 16-bit predicate
+  // constraint element count.
+  void sqinch(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1);
+
+  // Signed saturating increment scalar by multiple of 16-bit predicate
+  // constraint element count.
+  void sqinch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating increment vector by multiple of 16-bit predicate
+  // constraint element count.
+  void sqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating increment scalar by active predicate element count.
+  void sqincp(const Register& xd,
+              const PRegisterWithLaneSize& pg,
+              const Register& wn);
+
+  // Signed saturating increment scalar by active predicate element count.
+  void sqincp(const Register& xdn, const PRegisterWithLaneSize& pg);
+
+  // Signed saturating increment vector by active predicate element count.
+  void sqincp(const ZRegister& zdn, const PRegister& pg);
+
+  // Signed saturating increment scalar by multiple of 32-bit predicate
+  // constraint element count.
+  void sqincw(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1);
+
+  // Signed saturating increment scalar by multiple of 32-bit predicate
+  // constraint element count.
+  void sqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating increment vector by multiple of 32-bit predicate
+  // constraint element count.
+  void sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Signed saturating subtract vectors (unpredicated).
+  void sqsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Signed saturating subtract immediate (unpredicated).
+  void sqsub(const ZRegister& zd,
+             const ZRegister& zn,
+             int imm8,
+             int shift = -1);
+
+  // Contiguous/scatter store bytes from vector.
+  void st1b(const ZRegister& zt,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous/scatter store halfwords from vector.
+  void st1h(const ZRegister& zt,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous/scatter store words from vector.
+  void st1w(const ZRegister& zt,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous/scatter store doublewords from vector.
+  void st1d(const ZRegister& zt,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store two-byte structures from two vectors.
+  void st2b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store two-halfword structures from two vectors.
+  void st2h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store two-word structures from two vectors.
+  void st2w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store two-doubleword structures from two vectors,
+  void st2d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store three-byte structures from three vectors.
+  void st3b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store three-halfword structures from three vectors.
+  void st3h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store three-word structures from three vectors.
+  void st3w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store three-doubleword structures from three vectors.
+  void st3d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store four-byte structures from four vectors.
+  void st4b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store four-halfword structures from four vectors.
+  void st4h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store four-word structures from four vectors.
+  void st4w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store four-doubleword structures from four vectors.
+  void st4d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+
+  // Contiguous store non-temporal bytes from vector.
+  void stnt1b(const ZRegister& zt,
+              const PRegister& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous store non-temporal halfwords from vector.
+  void stnt1h(const ZRegister& zt,
+              const PRegister& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous store non-temporal words from vector.
+  void stnt1w(const ZRegister& zt,
+              const PRegister& pg,
+              const SVEMemOperand& addr);
+
+  // Contiguous store non-temporal doublewords from vector.
+  void stnt1d(const ZRegister& zt,
+              const PRegister& pg,
+              const SVEMemOperand& addr);
+
+  // Store SVE predicate/vector register.
+  void str(const CPURegister& rt, const SVEMemOperand& addr);
+
+  // Subtract vectors (predicated).
+  void sub(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+
+  // Subtract vectors (unpredicated).
+  void sub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Subtract immediate (unpredicated).
+  void sub(const ZRegister& zd, const ZRegister& zn, int imm8, int shift = -1);
+
+  // Reversed subtract vectors (predicated).
+  void subr(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Reversed subtract from immediate (unpredicated).
+  void subr(const ZRegister& zd, const ZRegister& zn, int imm8, int shift = -1);
+
+  // Signed unpack and extend half of vector.
+  void sunpkhi(const ZRegister& zd, const ZRegister& zn);
+
+  // Signed unpack and extend half of vector.
+  void sunpklo(const ZRegister& zd, const ZRegister& zn);
+
+  // Signed byte extend (predicated).
+  void sxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Signed halfword extend (predicated).
+  void sxth(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Signed word extend (predicated).
+  void sxtw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Programmable table lookup/permute using vector of indices into a
+  // vector.
+  void tbl(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Interleave even or odd elements from two predicates.
+  void trn1(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Interleave even or odd elements from two vectors.
+  void trn1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Interleave even or odd elements from two predicates.
+  void trn2(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Interleave even or odd elements from two vectors.
+  void trn2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Unsigned absolute difference (predicated).
+  void uabd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Unsigned add reduction to scalar.
+  void uaddv(const VRegister& dd, const PRegister& pg, const ZRegister& zn);
+
+  // Unsigned integer convert to floating-point (predicated).
+  void ucvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Unsigned divide (predicated).
+  void udiv(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Unsigned reversed divide (predicated).
+  void udivr(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Unsigned dot product by indexed quadtuplet.
+  void udot(const ZRegister& zda,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            int index);
+
+  // Unsigned dot product.
+  void udot(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm);
+
+  // Unsigned maximum vectors (predicated).
+  void umax(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Unsigned maximum with immediate (unpredicated).
+  void umax(const ZRegister& zd, const ZRegister& zn, int imm8);
+
+  // Unsigned maximum reduction to scalar.
+  void umaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Unsigned minimum vectors (predicated).
+  void umin(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+
+  // Unsigned minimum with immediate (unpredicated).
+  void umin(const ZRegister& zd, const ZRegister& zn, int imm8);
+
+  // Unsigned minimum reduction to scalar.
+  void uminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn);
+
+  // Unsigned multiply returning high half (predicated).
+  void umulh(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm);
+
+  // Unsigned saturating add vectors (unpredicated).
+  void uqadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Unsigned saturating add immediate (unpredicated).
+  void uqadd(const ZRegister& zd,
+             const ZRegister& zn,
+             int imm8,
+             int shift = -1);
+
+  // Unsigned saturating decrement scalar by multiple of 8-bit predicate
+  // constraint element count.
+  void uqdecb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating decrement scalar by multiple of 64-bit predicate
+  // constraint element count.
+  void uqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating decrement vector by multiple of 64-bit predicate
+  // constraint element count.
+  void uqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating decrement scalar by multiple of 16-bit predicate
+  // constraint element count.
+  void uqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating decrement vector by multiple of 16-bit predicate
+  // constraint element count.
+  void uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating decrement scalar by active predicate element count.
+  void uqdecp(const Register& rdn, const PRegisterWithLaneSize& pg);
+
+  // Unsigned saturating decrement vector by active predicate element count.
+  void uqdecp(const ZRegister& zdn, const PRegister& pg);
+
+  // Unsigned saturating decrement scalar by multiple of 32-bit predicate
+  // constraint element count.
+  void uqdecw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating decrement vector by multiple of 32-bit predicate
+  // constraint element count.
+  void uqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating increment scalar by multiple of 8-bit predicate
+  // constraint element count.
+  void uqincb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating increment scalar by multiple of 64-bit predicate
+  // constraint element count.
+  void uqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating increment vector by multiple of 64-bit predicate
+  // constraint element count.
+  void uqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating increment scalar by multiple of 16-bit predicate
+  // constraint element count.
+  void uqinch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating increment vector by multiple of 16-bit predicate
+  // constraint element count.
+  void uqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating increment scalar by active predicate element count.
+  void uqincp(const Register& rdn, const PRegisterWithLaneSize& pg);
+
+  // Unsigned saturating increment vector by active predicate element count.
+  void uqincp(const ZRegister& zdn, const PRegister& pg);
+
+  // Unsigned saturating increment scalar by multiple of 32-bit predicate
+  // constraint element count.
+  void uqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating increment vector by multiple of 32-bit predicate
+  // constraint element count.
+  void uqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1);
+
+  // Unsigned saturating subtract vectors (unpredicated).
+  void uqsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Unsigned saturating subtract immediate (unpredicated).
+  void uqsub(const ZRegister& zd,
+             const ZRegister& zn,
+             int imm8,
+             int shift = -1);
+
+  // Unsigned unpack and extend half of vector.
+  void uunpkhi(const ZRegister& zd, const ZRegister& zn);
+
+  // Unsigned unpack and extend half of vector.
+  void uunpklo(const ZRegister& zd, const ZRegister& zn);
+
+  // Unsigned byte extend (predicated).
+  void uxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Unsigned halfword extend (predicated).
+  void uxth(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Unsigned word extend (predicated).
+  void uxtw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
+
+  // Concatenate even or odd elements from two predicates.
+  void uzp1(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Concatenate even or odd elements from two vectors.
+  void uzp1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Concatenate even or odd elements from two predicates.
+  void uzp2(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Concatenate even or odd elements from two vectors.
+  void uzp2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // While incrementing signed scalar less than or equal to scalar.
+  void whilele(const PRegisterWithLaneSize& pd,
+               const Register& rn,
+               const Register& rm);
+
+  // While incrementing unsigned scalar lower than scalar.
+  void whilelo(const PRegisterWithLaneSize& pd,
+               const Register& rn,
+               const Register& rm);
+
+  // While incrementing unsigned scalar lower or same as scalar.
+  void whilels(const PRegisterWithLaneSize& pd,
+               const Register& rn,
+               const Register& rm);
+
+  // While incrementing signed scalar less than scalar.
+  void whilelt(const PRegisterWithLaneSize& pd,
+               const Register& rn,
+               const Register& rm);
+
+  // Write the first-fault register.
+  void wrffr(const PRegisterWithLaneSize& pn);
+
+  // Interleave elements from two half predicates.
+  void zip1(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Interleave elements from two half vectors.
+  void zip1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
+  // Interleave elements from two half predicates.
+  void zip2(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm);
+
+  // Interleave elements from two half vectors.
+  void zip2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
+
   // Emit generic instructions.
 
   // Emit raw instructions into the instruction stream.
@@ -3650,20 +5852,20 @@ class Assembler : public vixl::internal::AssemblerBase {
   // Code generation helpers.
 
   // Register encoding.
-  static Instr Rd(CPURegister rd) {
-    VIXL_ASSERT(rd.GetCode() != kSPRegInternalCode);
-    return rd.GetCode() << Rd_offset;
+  template <int hibit, int lobit>
+  static Instr Rx(CPURegister rx) {
+    VIXL_ASSERT(rx.GetCode() != kSPRegInternalCode);
+    return ImmUnsignedField<hibit, lobit>(rx.GetCode());
   }
 
-  static Instr Rn(CPURegister rn) {
-    VIXL_ASSERT(rn.GetCode() != kSPRegInternalCode);
-    return rn.GetCode() << Rn_offset;
-  }
-
-  static Instr Rm(CPURegister rm) {
-    VIXL_ASSERT(rm.GetCode() != kSPRegInternalCode);
-    return rm.GetCode() << Rm_offset;
+#define CPU_REGISTER_FIELD_NAMES(V) V(d) V(n) V(m) V(a) V(t) V(t2) V(s)
+#define REGISTER_ENCODER(N)                                           \
+  static Instr R##N(CPURegister r##N) {                               \
+    return Rx<R##N##_offset + R##N##_width - 1, R##N##_offset>(r##N); \
   }
+  CPU_REGISTER_FIELD_NAMES(REGISTER_ENCODER)
+#undef REGISTER_ENCODER
+#undef CPU_REGISTER_FIELD_NAMES
 
   static Instr RmNot31(CPURegister rm) {
     VIXL_ASSERT(rm.GetCode() != kSPRegInternalCode);
@@ -3671,26 +5873,6 @@ class Assembler : public vixl::internal::AssemblerBase {
     return Rm(rm);
   }
 
-  static Instr Ra(CPURegister ra) {
-    VIXL_ASSERT(ra.GetCode() != kSPRegInternalCode);
-    return ra.GetCode() << Ra_offset;
-  }
-
-  static Instr Rt(CPURegister rt) {
-    VIXL_ASSERT(rt.GetCode() != kSPRegInternalCode);
-    return rt.GetCode() << Rt_offset;
-  }
-
-  static Instr Rt2(CPURegister rt2) {
-    VIXL_ASSERT(rt2.GetCode() != kSPRegInternalCode);
-    return rt2.GetCode() << Rt2_offset;
-  }
-
-  static Instr Rs(CPURegister rs) {
-    VIXL_ASSERT(rs.GetCode() != kSPRegInternalCode);
-    return rs.GetCode() << Rs_offset;
-  }
-
   // These encoding functions allow the stack pointer to be encoded, and
   // disallow the zero register.
   static Instr RdSP(Register rd) {
@@ -3708,6 +5890,33 @@ class Assembler : public vixl::internal::AssemblerBase {
     return (rm.GetCode() & kRegCodeMask) << Rm_offset;
   }
 
+  static Instr Pd(PRegister pd) {
+    return Rx<Pd_offset + Pd_width - 1, Pd_offset>(pd);
+  }
+
+  static Instr Pm(PRegister pm) {
+    return Rx<Pm_offset + Pm_width - 1, Pm_offset>(pm);
+  }
+
+  static Instr Pn(PRegister pn) {
+    return Rx<Pn_offset + Pn_width - 1, Pn_offset>(pn);
+  }
+
+  static Instr PgLow8(PRegister pg) {
+    // Governing predicates can be merging, zeroing, or unqualified. They should
+    // never have a lane size.
+    VIXL_ASSERT(!pg.HasLaneSize());
+    return Rx<PgLow8_offset + PgLow8_width - 1, PgLow8_offset>(pg);
+  }
+
+  template <int hibit, int lobit>
+  static Instr Pg(PRegister pg) {
+    // Governing predicates can be merging, zeroing, or unqualified. They should
+    // never have a lane size.
+    VIXL_ASSERT(!pg.HasLaneSize());
+    return Rx<hibit, lobit>(pg);
+  }
+
   // Flags encoding.
   static Instr Flags(FlagsUpdate S) {
     if (S == SetFlags) {
@@ -3721,6 +5930,26 @@ class Assembler : public vixl::internal::AssemblerBase {
 
   static Instr Cond(Condition cond) { return cond << Condition_offset; }
 
+  // Generic immediate encoding.
+  template <int hibit, int lobit>
+  static Instr ImmField(int64_t imm) {
+    VIXL_STATIC_ASSERT((hibit >= lobit) && (lobit >= 0));
+    VIXL_STATIC_ASSERT(hibit < (sizeof(Instr) * kBitsPerByte));
+    int fieldsize = hibit - lobit + 1;
+    VIXL_ASSERT(IsIntN(fieldsize, imm));
+    return static_cast<Instr>(TruncateToUintN(fieldsize, imm) << lobit);
+  }
+
+  // For unsigned immediate encoding.
+  // TODO: Handle signed and unsigned immediate in satisfactory way.
+  template <int hibit, int lobit>
+  static Instr ImmUnsignedField(uint64_t imm) {
+    VIXL_STATIC_ASSERT((hibit >= lobit) && (lobit >= 0));
+    VIXL_STATIC_ASSERT(hibit < (sizeof(Instr) * kBitsPerByte));
+    VIXL_ASSERT(IsUintN(hibit - lobit + 1, imm));
+    return static_cast<Instr>(imm << lobit);
+  }
+
   // PC-relative address encoding.
   static Instr ImmPCRelAddress(int64_t imm21) {
     VIXL_ASSERT(IsInt21(imm21));
@@ -3771,11 +6000,60 @@ class Assembler : public vixl::internal::AssemblerBase {
     if (IsUint12(imm)) {  // No shift required.
       imm <<= ImmAddSub_offset;
     } else {
-      imm = ((imm >> 12) << ImmAddSub_offset) | (1 << ShiftAddSub_offset);
+      imm = ((imm >> 12) << ImmAddSub_offset) | (1 << ImmAddSubShift_offset);
     }
     return imm;
   }
 
+  static Instr SVEImmSetBits(unsigned imms, unsigned lane_size) {
+    VIXL_ASSERT(IsUint6(imms));
+    VIXL_ASSERT((lane_size == kDRegSize) || IsUint6(imms + 3));
+    USE(lane_size);
+    return imms << SVEImmSetBits_offset;
+  }
+
+  static Instr SVEImmRotate(unsigned immr, unsigned lane_size) {
+    VIXL_ASSERT(IsUintN(WhichPowerOf2(lane_size), immr));
+    USE(lane_size);
+    return immr << SVEImmRotate_offset;
+  }
+
+  static Instr SVEBitN(unsigned bitn) {
+    VIXL_ASSERT(IsUint1(bitn));
+    return bitn << SVEBitN_offset;
+  }
+
+  static Instr SVEDtype(unsigned msize_in_bytes_log2,
+                        unsigned esize_in_bytes_log2,
+                        bool is_signed,
+                        int dtype_h_lsb = 23,
+                        int dtype_l_lsb = 21) {
+    VIXL_ASSERT(msize_in_bytes_log2 <= kDRegSizeInBytesLog2);
+    VIXL_ASSERT(esize_in_bytes_log2 <= kDRegSizeInBytesLog2);
+    Instr dtype_h = msize_in_bytes_log2;
+    Instr dtype_l = esize_in_bytes_log2;
+    // Signed forms use the encodings where msize would be greater than esize.
+    if (is_signed) {
+      dtype_h = dtype_h ^ 0x3;
+      dtype_l = dtype_l ^ 0x3;
+    }
+    VIXL_ASSERT(IsUint2(dtype_h));
+    VIXL_ASSERT(IsUint2(dtype_l));
+    VIXL_ASSERT((dtype_h > dtype_l) == is_signed);
+
+    return (dtype_h << dtype_h_lsb) | (dtype_l << dtype_l_lsb);
+  }
+
+  static Instr SVEDtypeSplit(unsigned msize_in_bytes_log2,
+                             unsigned esize_in_bytes_log2,
+                             bool is_signed) {
+    return SVEDtype(msize_in_bytes_log2,
+                    esize_in_bytes_log2,
+                    is_signed,
+                    23,
+                    13);
+  }
+
   static Instr ImmS(unsigned imms, unsigned reg_size) {
     VIXL_ASSERT(((reg_size == kXRegSize) && IsUint6(imms)) ||
                 ((reg_size == kWRegSize) && IsUint5(imms)));
@@ -3856,9 +6134,9 @@ class Assembler : public vixl::internal::AssemblerBase {
     return TruncateToUint9(imm9) << ImmLS_offset;
   }
 
-  static Instr ImmLSPair(int64_t imm7, unsigned access_size) {
-    VIXL_ASSERT(IsMultiple(imm7, 1 << access_size));
-    int64_t scaled_imm7 = imm7 / (1 << access_size);
+  static Instr ImmLSPair(int64_t imm7, unsigned access_size_in_bytes_log2) {
+    VIXL_ASSERT(IsMultiple(imm7, 1 << access_size_in_bytes_log2));
+    int64_t scaled_imm7 = imm7 / (1 << access_size_in_bytes_log2);
     VIXL_ASSERT(IsInt7(scaled_imm7));
     return TruncateToUint7(scaled_imm7) << ImmLSPair_offset;
   }
@@ -3990,8 +6268,8 @@ class Assembler : public vixl::internal::AssemblerBase {
                            unsigned* n = NULL,
                            unsigned* imm_s = NULL,
                            unsigned* imm_r = NULL);
-  static bool IsImmLSPair(int64_t offset, unsigned access_size);
-  static bool IsImmLSScaled(int64_t offset, unsigned access_size);
+  static bool IsImmLSPair(int64_t offset, unsigned access_size_in_bytes_log2);
+  static bool IsImmLSScaled(int64_t offset, unsigned access_size_in_bytes_log2);
   static bool IsImmLSUnscaled(int64_t offset);
   static bool IsImmMovn(uint64_t imm, unsigned reg_size);
   static bool IsImmMovz(uint64_t imm, unsigned reg_size);
@@ -4126,6 +6404,30 @@ class Assembler : public vixl::internal::AssemblerBase {
     }
   }
 
+  template <typename T>
+  static Instr SVESize(const T& rd) {
+    VIXL_ASSERT(rd.IsZRegister() || rd.IsPRegister());
+    VIXL_ASSERT(rd.HasLaneSize());
+    switch (rd.GetLaneSizeInBytes()) {
+      case 1:
+        return SVE_B;
+      case 2:
+        return SVE_H;
+      case 4:
+        return SVE_S;
+      case 8:
+        return SVE_D;
+      default:
+        return 0xffffffff;
+    }
+  }
+
+  static Instr ImmSVEPredicateConstraint(int pattern) {
+    VIXL_ASSERT(IsUint5(pattern));
+    return (pattern << ImmSVEPredicateConstraint_offset) &
+           ImmSVEPredicateConstraint_mask;
+  }
+
   static Instr ImmNEONHLM(int index, int num_bits) {
     int h, l, m;
     if (num_bits == 3) {
@@ -4277,9 +6579,93 @@ class Assembler : public vixl::internal::AssemblerBase {
                              const MemOperand& addr,
                              Instr op);
 
+  // Set `is_load` to false in default as it's only used in the
+  // scalar-plus-vector form.
+  Instr SVEMemOperandHelper(unsigned msize_in_bytes_log2,
+                            int num_regs,
+                            const SVEMemOperand& addr,
+                            bool is_load = false);
+
+  // E.g. st1b, st1h, ...
+  // This supports both contiguous and scatter stores.
+  void SVESt1Helper(unsigned msize_in_bytes_log2,
+                    const ZRegister& zt,
+                    const PRegister& pg,
+                    const SVEMemOperand& addr);
+
+  // E.g. ld1b, ld1h, ...
+  // This supports both contiguous and gather loads.
+  void SVELd1Helper(unsigned msize_in_bytes_log2,
+                    const ZRegister& zt,
+                    const PRegisterZ& pg,
+                    const SVEMemOperand& addr,
+                    bool is_signed);
+
+  // E.g. ld1rb, ld1rh, ...
+  void SVELd1BroadcastHelper(unsigned msize_in_bytes_log2,
+                             const ZRegister& zt,
+                             const PRegisterZ& pg,
+                             const SVEMemOperand& addr,
+                             bool is_signed);
+
+  // E.g. ldff1b, ldff1h, ...
+  // This supports both contiguous and gather loads.
+  void SVELdff1Helper(unsigned msize_in_bytes_log2,
+                      const ZRegister& zt,
+                      const PRegisterZ& pg,
+                      const SVEMemOperand& addr,
+                      bool is_signed);
+
+  // Common code for the helpers above.
+  void SVELdSt1Helper(unsigned msize_in_bytes_log2,
+                      const ZRegister& zt,
+                      const PRegister& pg,
+                      const SVEMemOperand& addr,
+                      bool is_signed,
+                      Instr op);
+
+  // Common code for the helpers above.
+  void SVEScatterGatherHelper(unsigned msize_in_bytes_log2,
+                              const ZRegister& zt,
+                              const PRegister& pg,
+                              const SVEMemOperand& addr,
+                              bool is_load,
+                              bool is_signed,
+                              bool is_first_fault);
+
+  // E.g. st2b, st3h, ...
+  void SVESt234Helper(int num_regs,
+                      const ZRegister& zt1,
+                      const PRegister& pg,
+                      const SVEMemOperand& addr);
+
+  // E.g. ld2b, ld3h, ...
+  void SVELd234Helper(int num_regs,
+                      const ZRegister& zt1,
+                      const PRegisterZ& pg,
+                      const SVEMemOperand& addr);
+
+  // Common code for the helpers above.
+  void SVELdSt234Helper(int num_regs,
+                        const ZRegister& zt1,
+                        const PRegister& pg,
+                        const SVEMemOperand& addr,
+                        Instr op);
+
+  // E.g. ld1qb, ld1qh, ldnt1b, ...
+  void SVELd1St1ScaImmHelper(const ZRegister& zt,
+                             const PRegister& pg,
+                             const SVEMemOperand& addr,
+                             Instr regoffset_op,
+                             Instr immoffset_op,
+                             int imm_divisor = 1);
+
   void Prefetch(PrefetchOperation op,
                 const MemOperand& addr,
                 LoadStoreScalingOption option = PreferScaledOffset);
+  void Prefetch(int op,
+                const MemOperand& addr,
+                LoadStoreScalingOption option = PreferScaledOffset);
 
   // TODO(all): The third parameter should be passed by reference but gcc 4.8.2
   // reports a bogus uninitialised warning then.
@@ -4287,6 +6673,9 @@ class Assembler : public vixl::internal::AssemblerBase {
                const Register& rn,
                const Operand operand,
                LogicalOp op);
+
+  void SVELogicalImmediate(const ZRegister& zd, uint64_t imm, Instr op);
+
   void LogicalImmediate(const Register& rd,
                         const Register& rn,
                         unsigned n,
@@ -4306,6 +6695,92 @@ class Assembler : public vixl::internal::AssemblerBase {
                        FlagsUpdate S,
                        AddSubWithCarryOp op);
 
+  void CompareVectors(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm,
+                      SVEIntCompareVectorsOp op);
+
+  void CompareVectors(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      int imm,
+                      SVEIntCompareSignedImmOp op);
+
+  void CompareVectors(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      unsigned imm,
+                      SVEIntCompareUnsignedImmOp op);
+
+  void SVEIntAddSubtractImmUnpredicatedHelper(
+      SVEIntAddSubtractImm_UnpredicatedOp op,
+      const ZRegister& zd,
+      int imm8,
+      int shift);
+
+  void SVEElementCountToRegisterHelper(Instr op,
+                                       const Register& rd,
+                                       int pattern,
+                                       int multiplier);
+
+  Instr EncodeSVEShiftImmediate(Shift shift_op,
+                                int shift,
+                                int lane_size_in_bits);
+
+  void SVEBitwiseShiftImmediate(const ZRegister& zd,
+                                const ZRegister& zn,
+                                Instr encoded_imm,
+                                SVEBitwiseShiftUnpredicatedOp op);
+
+  void SVEBitwiseShiftImmediatePred(const ZRegister& zdn,
+                                    const PRegisterM& pg,
+                                    Instr encoded_imm,
+                                    SVEBitwiseShiftByImm_PredicatedOp op);
+
+  Instr SVEFPMulIndexHelper(unsigned lane_size_in_bytes_log2,
+                            const ZRegister& zm,
+                            int index,
+                            Instr op_h,
+                            Instr op_s,
+                            Instr op_d);
+
+
+  void SVEContiguousPrefetchScalarPlusScalarHelper(PrefetchOperation prfop,
+                                                   const PRegister& pg,
+                                                   const SVEMemOperand& addr,
+                                                   int prefetch_size);
+
+  void SVEContiguousPrefetchScalarPlusVectorHelper(PrefetchOperation prfop,
+                                                   const PRegister& pg,
+                                                   const SVEMemOperand& addr,
+                                                   int prefetch_size);
+
+  void SVEGatherPrefetchVectorPlusImmediateHelper(PrefetchOperation prfop,
+                                                  const PRegister& pg,
+                                                  const SVEMemOperand& addr,
+                                                  int prefetch_size);
+
+  void SVEGatherPrefetchScalarPlusImmediateHelper(PrefetchOperation prfop,
+                                                  const PRegister& pg,
+                                                  const SVEMemOperand& addr,
+                                                  int prefetch_size);
+
+  void SVEPrefetchHelper(PrefetchOperation prfop,
+                         const PRegister& pg,
+                         const SVEMemOperand& addr,
+                         int prefetch_size);
+
+  static Instr SVEImmPrefetchOperation(PrefetchOperation prfop) {
+    // SVE only supports PLD and PST, not PLI.
+    VIXL_ASSERT(((prfop >= PLDL1KEEP) && (prfop <= PLDL3STRM)) ||
+                ((prfop >= PSTL1KEEP) && (prfop <= PSTL3STRM)));
+    // Check that we can simply map bits.
+    VIXL_STATIC_ASSERT(PLDL1KEEP == 0b00000);
+    VIXL_STATIC_ASSERT(PSTL1KEEP == 0b10000);
+    // Remaining operations map directly.
+    return ((prfop & 0b10000) >> 1) | (prfop & 0b00111);
+  }
 
   // Functions for emulating operands not directly supported by the instruction
   // set.
@@ -4507,12 +6982,16 @@ class Assembler : public vixl::internal::AssemblerBase {
                            NEONShiftImmediateOp op);
   void NEONXtn(const VRegister& vd, const VRegister& vn, NEON2RegMiscOp vop);
 
+  // If *shift is -1, find values of *imm8 and *shift such that IsInt8(*imm8)
+  // and *shift is either 0 or 8. Otherwise, leave the values unchanged.
+  void ResolveSVEImm8Shift(int* imm8, int* shift);
+
   Instr LoadStoreStructAddrModeField(const MemOperand& addr);
 
   // Encode the specified MemOperand for the specified access size and scaling
   // preference.
   Instr LoadStoreMemOperand(const MemOperand& addr,
-                            unsigned access_size,
+                            unsigned access_size_in_bytes_log2,
                             LoadStoreScalingOption option);
 
   // Link the current (not-yet-emitted) instruction to the specified label, then
diff --git a/src/aarch64/assembler-sve-aarch64.cc b/src/aarch64/assembler-sve-aarch64.cc
new file mode 100644
index 00000000..f7cf8b21
--- /dev/null
+++ b/src/aarch64/assembler-sve-aarch64.cc
@@ -0,0 +1,6489 @@
+// Copyright 2019, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "assembler-aarch64.h"
+
+namespace vixl {
+namespace aarch64 {
+
+void Assembler::ResolveSVEImm8Shift(int* imm8, int* shift) {
+  if (*shift < 0) {
+    VIXL_ASSERT(*shift == -1);
+    // Derive the shift amount from the immediate.
+    if (IsInt8(*imm8)) {
+      *shift = 0;
+    } else if ((*imm8 % 256) == 0) {
+      *imm8 /= 256;
+      *shift = 8;
+    }
+  }
+
+  VIXL_ASSERT(IsInt8(*imm8));
+  VIXL_ASSERT((*shift == 0) || (*shift == 8));
+}
+
+// SVEAddressGeneration.
+
+void Assembler::adr(const ZRegister& zd, const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsVectorPlusVector());
+  VIXL_ASSERT(
+      AreSameLaneSize(zd, addr.GetVectorBase(), addr.GetVectorOffset()));
+
+  int lane_size = zd.GetLaneSizeInBits();
+  VIXL_ASSERT((lane_size == kSRegSize) || (lane_size == kDRegSize));
+
+  int shift_amount = addr.GetShiftAmount();
+  VIXL_ASSERT((shift_amount >= 0) && (shift_amount <= 3));
+
+  Instr op = 0xffffffff;
+  Instr msz = shift_amount << 10;
+  SVEOffsetModifier mod = addr.GetOffsetModifier();
+  switch (mod) {
+    case SVE_UXTW:
+      VIXL_ASSERT(lane_size == kDRegSize);
+      op = ADR_z_az_d_u32_scaled;
+      break;
+    case SVE_SXTW:
+      VIXL_ASSERT(lane_size == kDRegSize);
+      op = ADR_z_az_d_s32_scaled;
+      break;
+    case SVE_LSL:
+    case NO_SVE_OFFSET_MODIFIER:
+      op = (lane_size == kSRegSize) ? ADR_z_az_s_same_scaled
+                                    : ADR_z_az_d_same_scaled;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+  }
+  Emit(op | msz | Rd(zd) | Rn(addr.GetVectorBase()) |
+       Rm(addr.GetVectorOffset()));
+}
+
+void Assembler::SVELogicalImmediate(const ZRegister& zdn,
+                                    uint64_t imm,
+                                    Instr op) {
+  unsigned bit_n, imm_s, imm_r;
+  unsigned lane_size = zdn.GetLaneSizeInBits();
+  // Check that the immediate can be encoded in the instruction.
+  if (IsImmLogical(imm, lane_size, &bit_n, &imm_s, &imm_r)) {
+    Emit(op | Rd(zdn) | SVEBitN(bit_n) | SVEImmRotate(imm_r, lane_size) |
+         SVEImmSetBits(imm_s, lane_size));
+  } else {
+    VIXL_UNREACHABLE();
+  }
+}
+
+void Assembler::and_(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  SVELogicalImmediate(zd, imm, AND_z_zi);
+}
+
+void Assembler::dupm(const ZRegister& zd, uint64_t imm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  // DUPM_z_i is an SVEBroadcastBitmaskImmOp, but its encoding and constraints
+  // are similar enough to SVEBitwiseLogicalWithImm_UnpredicatedOp, that we can
+  // use the logical immediate encoder to get the correct behaviour.
+  SVELogicalImmediate(zd, imm, DUPM_z_i);
+}
+
+void Assembler::eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  SVELogicalImmediate(zd, imm, EOR_z_zi);
+}
+
+void Assembler::orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  SVELogicalImmediate(zd, imm, ORR_z_zi);
+}
+
+// SVEBitwiseLogicalUnpredicated.
+void Assembler::and_(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.IsLaneSizeD());
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+  Emit(AND_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::bic(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.IsLaneSizeD());
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+  Emit(BIC_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::eor(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.IsLaneSizeD());
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+  Emit(EOR_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::orr(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.IsLaneSizeD());
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+  Emit(ORR_z_zz | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+// SVEBitwiseShiftPredicated.
+
+void Assembler::SVEBitwiseShiftImmediatePred(
+    const ZRegister& zdn,
+    const PRegisterM& pg,
+    Instr encoded_imm_and_tsz,
+    SVEBitwiseShiftByImm_PredicatedOp op) {
+  Instr tszl_and_imm = ExtractUnsignedBitfield32(4, 0, encoded_imm_and_tsz)
+                       << 5;
+  Instr tszh = ExtractUnsignedBitfield32(6, 5, encoded_imm_and_tsz) << 22;
+  Emit(op | tszh | tszl_and_imm | PgLow8(pg) | Rd(zdn));
+}
+
+void Assembler::asr(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    int shift) {
+  // ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
+  //  0000 0100 ..00 0000 100. .... .... ....
+  //  tszh<23:22> | opc<19:18> = 00 | L<17> = 0 | U<16> = 0 | Pg<12:10> |
+  //  tszl<9:8> | imm3<7:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  Instr encoded_imm =
+      EncodeSVEShiftImmediate(ASR, shift, zd.GetLaneSizeInBits());
+  SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, ASR_z_p_zi);
+}
+
+void Assembler::asr(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // ASR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
+  //  0000 0100 ..01 1000 100. .... .... ....
+  //  size<23:22> | R<18> = 0 | L<17> = 0 | U<16> = 0 | Pg<12:10> | Zm<9:5> |
+  //  Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
+              ((zm.GetLaneSizeInBytes() == kDRegSizeInBytes) &&
+               (zd.GetLaneSizeInBytes() != kDRegSizeInBytes)));
+  Instr op = ASR_z_p_zw;
+  if (AreSameLaneSize(zd, zn, zm)) {
+    op = ASR_z_p_zz;
+  }
+  Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::asrd(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     int shift) {
+  // ASRD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
+  //  0000 0100 ..00 0100 100. .... .... ....
+  //  tszh<23:22> | opc<19:18> = 01 | L<17> = 0 | U<16> = 0 | Pg<12:10> |
+  //  tszl<9:8> | imm3<7:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+
+  Instr encoded_imm =
+      EncodeSVEShiftImmediate(ASR, shift, zd.GetLaneSizeInBits());
+  SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, ASRD_z_p_zi);
+}
+
+void Assembler::asrr(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // ASRR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0100 100. .... .... ....
+  //  size<23:22> | R<18> = 1 | L<17> = 0 | U<16> = 0 | Pg<12:10> | Zm<9:5> |
+  //  Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(ASRR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::lsl(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    int shift) {
+  // LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
+  //  0000 0100 ..00 0011 100. .... .... ....
+  //  tszh<23:22> | opc<19:18> = 00 | L<17> = 1 | U<16> = 1 | Pg<12:10> |
+  //  tszl<9:8> | imm3<7:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+
+  Instr encoded_imm =
+      EncodeSVEShiftImmediate(LSL, shift, zd.GetLaneSizeInBits());
+  SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, LSL_z_p_zi);
+}
+
+void Assembler::lsl(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // LSL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
+  //  0000 0100 ..01 1011 100. .... .... ....
+  //  size<23:22> | R<18> = 0 | L<17> = 1 | U<16> = 1 | Pg<12:10> | Zm<9:5> |
+  //  Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
+              ((zm.GetLaneSizeInBytes() == kDRegSizeInBytes) &&
+               (zd.GetLaneSizeInBytes() != kDRegSizeInBytes)));
+  Instr op = LSL_z_p_zw;
+  if (AreSameLaneSize(zd, zn, zm)) {
+    op = LSL_z_p_zz;
+  }
+  Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::lslr(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // LSLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0111 100. .... .... ....
+  //  size<23:22> | R<18> = 1 | L<17> = 1 | U<16> = 1 | Pg<12:10> | Zm<9:5> |
+  //  Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(LSLR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::lsr(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    int shift) {
+  // LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
+  //  0000 0100 ..00 0001 100. .... .... ....
+  //  tszh<23:22> | opc<19:18> = 00 | L<17> = 0 | U<16> = 1 | Pg<12:10> |
+  //  tszl<9:8> | imm3<7:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+
+  Instr encoded_imm =
+      EncodeSVEShiftImmediate(LSR, shift, zd.GetLaneSizeInBits());
+  SVEBitwiseShiftImmediatePred(zd, pg, encoded_imm, LSR_z_p_zi);
+}
+
+void Assembler::lsr(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // LSR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
+  //  0000 0100 ..01 1001 100. .... .... ....
+  //  size<23:22> | R<18> = 0 | L<17> = 0 | U<16> = 1 | Pg<12:10> | Zm<9:5> |
+  //  Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm) ||
+              ((zm.GetLaneSizeInBytes() == kDRegSizeInBytes) &&
+               (zd.GetLaneSizeInBytes() != kDRegSizeInBytes)));
+  Instr op = LSR_z_p_zw;
+  if (AreSameLaneSize(zd, zn, zm)) {
+    op = LSR_z_p_zz;
+  }
+  Emit(op | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::lsrr(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // LSRR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0101 100. .... .... ....
+  //  size<23:22> | R<18> = 1 | L<17> = 0 | U<16> = 1 | Pg<12:10> | Zm<9:5> |
+  //  Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(LSRR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+// SVEBitwiseShiftUnpredicated.
+
+Instr Assembler::EncodeSVEShiftImmediate(Shift shift_op,
+                                         int shift,
+                                         int lane_size_in_bits) {
+  if (shift_op == LSL) {
+    VIXL_ASSERT((shift >= 0) && (shift < lane_size_in_bits));
+    return lane_size_in_bits + shift;
+  }
+
+  VIXL_ASSERT((shift_op == ASR) || (shift_op == LSR));
+  VIXL_ASSERT((shift > 0) && (shift <= lane_size_in_bits));
+  return (2 * lane_size_in_bits) - shift;
+}
+
+void Assembler::SVEBitwiseShiftImmediate(const ZRegister& zd,
+                                         const ZRegister& zn,
+                                         Instr encoded_imm_and_tsz,
+                                         SVEBitwiseShiftUnpredicatedOp op) {
+  Instr tszl_and_imm = ExtractUnsignedBitfield32(4, 0, encoded_imm_and_tsz)
+                       << 16;
+  Instr tszh = ExtractUnsignedBitfield32(6, 5, encoded_imm_and_tsz) << 22;
+  Emit(op | tszh | tszl_and_imm | Rd(zd) | Rn(zn));
+}
+
+void Assembler::asr(const ZRegister& zd, const ZRegister& zn, int shift) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  Instr encoded_imm =
+      EncodeSVEShiftImmediate(ASR, shift, zd.GetLaneSizeInBits());
+  SVEBitwiseShiftImmediate(zd, zn, encoded_imm, ASR_z_zi);
+}
+
+void Assembler::asr(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kDRegSizeInBytes);
+
+  Emit(ASR_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::lsl(const ZRegister& zd, const ZRegister& zn, int shift) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  Instr encoded_imm =
+      EncodeSVEShiftImmediate(LSL, shift, zd.GetLaneSizeInBits());
+  SVEBitwiseShiftImmediate(zd, zn, encoded_imm, LSL_z_zi);
+}
+
+void Assembler::lsl(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kDRegSizeInBytes);
+
+  Emit(LSL_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::lsr(const ZRegister& zd, const ZRegister& zn, int shift) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  Instr encoded_imm =
+      EncodeSVEShiftImmediate(LSR, shift, zd.GetLaneSizeInBits());
+  SVEBitwiseShiftImmediate(zd, zn, encoded_imm, LSR_z_zi);
+}
+
+void Assembler::lsr(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kDRegSizeInBytes);
+
+  Emit(LSR_z_zw | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+// SVEElementCount.
+
+#define VIXL_SVE_INC_DEC_LIST(V) \
+  V(cntb, CNTB_r_s)              \
+  V(cnth, CNTH_r_s)              \
+  V(cntw, CNTW_r_s)              \
+  V(cntd, CNTD_r_s)              \
+  V(decb, DECB_r_rs)             \
+  V(dech, DECH_r_rs)             \
+  V(decw, DECW_r_rs)             \
+  V(decd, DECD_r_rs)             \
+  V(incb, INCB_r_rs)             \
+  V(inch, INCH_r_rs)             \
+  V(incw, INCW_r_rs)             \
+  V(incd, INCD_r_rs)             \
+  V(sqdecb, SQDECB_r_rs_x)       \
+  V(sqdech, SQDECH_r_rs_x)       \
+  V(sqdecw, SQDECW_r_rs_x)       \
+  V(sqdecd, SQDECD_r_rs_x)       \
+  V(sqincb, SQINCB_r_rs_x)       \
+  V(sqinch, SQINCH_r_rs_x)       \
+  V(sqincw, SQINCW_r_rs_x)       \
+  V(sqincd, SQINCD_r_rs_x)
+
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                                     \
+  void Assembler::FN(const Register& rdn, int pattern, int multiplier) { \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                              \
+    VIXL_ASSERT(rdn.IsX());                                              \
+    Emit(OP | Rd(rdn) | ImmSVEPredicateConstraint(pattern) |             \
+         ImmUnsignedField<19, 16>(multiplier - 1));                      \
+  }
+VIXL_SVE_INC_DEC_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
+
+#define VIXL_SVE_UQINC_UQDEC_LIST(V)                      \
+  V(uqdecb, (rdn.IsX() ? UQDECB_r_rs_x : UQDECB_r_rs_uw)) \
+  V(uqdech, (rdn.IsX() ? UQDECH_r_rs_x : UQDECH_r_rs_uw)) \
+  V(uqdecw, (rdn.IsX() ? UQDECW_r_rs_x : UQDECW_r_rs_uw)) \
+  V(uqdecd, (rdn.IsX() ? UQDECD_r_rs_x : UQDECD_r_rs_uw)) \
+  V(uqincb, (rdn.IsX() ? UQINCB_r_rs_x : UQINCB_r_rs_uw)) \
+  V(uqinch, (rdn.IsX() ? UQINCH_r_rs_x : UQINCH_r_rs_uw)) \
+  V(uqincw, (rdn.IsX() ? UQINCW_r_rs_x : UQINCW_r_rs_uw)) \
+  V(uqincd, (rdn.IsX() ? UQINCD_r_rs_x : UQINCD_r_rs_uw))
+
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                                     \
+  void Assembler::FN(const Register& rdn, int pattern, int multiplier) { \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                              \
+    Emit(OP | Rd(rdn) | ImmSVEPredicateConstraint(pattern) |             \
+         ImmUnsignedField<19, 16>(multiplier - 1));                      \
+  }
+VIXL_SVE_UQINC_UQDEC_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
+
+#define VIXL_SVE_SQX_INC_DEC_LIST(V) \
+  V(sqdecb, SQDECB)                  \
+  V(sqdech, SQDECH)                  \
+  V(sqdecw, SQDECW)                  \
+  V(sqdecd, SQDECD)                  \
+  V(sqincb, SQINCB)                  \
+  V(sqinch, SQINCH)                  \
+  V(sqincw, SQINCW)                  \
+  V(sqincd, SQINCD)
+
+#define VIXL_DEFINE_ASM_FUNC(FN, OP)                                  \
+  void Assembler::FN(const Register& xd,                              \
+                     const Register& wn,                              \
+                     int pattern,                                     \
+                     int multiplier) {                                \
+    USE(wn);                                                          \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                           \
+    VIXL_ASSERT(wn.IsW() && xd.Is(wn.X()));                           \
+    Emit(OP##_r_rs_sx | Rd(xd) | ImmSVEPredicateConstraint(pattern) | \
+         ImmUnsignedField<19, 16>(multiplier - 1));                   \
+  }
+VIXL_SVE_SQX_INC_DEC_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
+
+#define VIXL_SVE_INC_DEC_VEC_LIST(V) \
+  V(dech, DEC, H)                    \
+  V(decw, DEC, W)                    \
+  V(decd, DEC, D)                    \
+  V(inch, INC, H)                    \
+  V(incw, INC, W)                    \
+  V(incd, INC, D)                    \
+  V(sqdech, SQDEC, H)                \
+  V(sqdecw, SQDEC, W)                \
+  V(sqdecd, SQDEC, D)                \
+  V(sqinch, SQINC, H)                \
+  V(sqincw, SQINC, W)                \
+  V(sqincd, SQINC, D)                \
+  V(uqdech, UQDEC, H)                \
+  V(uqdecw, UQDEC, W)                \
+  V(uqdecd, UQDEC, D)                \
+  V(uqinch, UQINC, H)                \
+  V(uqincw, UQINC, W)                \
+  V(uqincd, UQINC, D)
+
+#define VIXL_DEFINE_ASM_FUNC(FN, OP, T)                                   \
+  void Assembler::FN(const ZRegister& zdn, int pattern, int multiplier) { \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                               \
+    VIXL_ASSERT(zdn.GetLaneSizeInBytes() == k##T##RegSizeInBytes);        \
+    Emit(OP##T##_z_zs | Rd(zdn) | ImmSVEPredicateConstraint(pattern) |    \
+         ImmUnsignedField<19, 16>(multiplier - 1));                       \
+  }
+VIXL_SVE_INC_DEC_VEC_LIST(VIXL_DEFINE_ASM_FUNC)
+#undef VIXL_DEFINE_ASM_FUNC
+
+// SVEFPAccumulatingReduction.
+
+void Assembler::fadda(const VRegister& vd,
+                      const PRegister& pg,
+                      const VRegister& vn,
+                      const ZRegister& zm) {
+  // FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
+  //  0110 0101 ..01 1000 001. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | Pg<12:10> | Zm<9:5> | Vdn<4:0>
+
+  USE(vn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.Is(vn));
+  VIXL_ASSERT(vd.IsScalar());
+  VIXL_ASSERT(zm.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(AreSameLaneSize(zm, vd));
+
+  Emit(FADDA_v_p_z | SVESize(zm) | Rd(vd) | PgLow8(pg) | Rn(zm));
+}
+
+// SVEFPArithmetic_Predicated.
+
+void Assembler::fabd(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 1000 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 1000 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FABD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fadd(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     double imm) {
+  // FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
+  //  0110 0101 ..01 1000 100. ..00 00.. ....
+  //  size<23:22> | opc<18:16> = 000 | Pg<12:10> | i1<5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT((imm == 0.5) || (imm == 1.0));
+
+  Instr i1 = (imm == 1.0) ? (1 << 5) : 0;
+  Emit(FADD_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
+}
+
+void Assembler::fadd(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 0000 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 0000 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FADD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fdiv(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 1101 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 1101 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FDIV_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fdivr(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 1100 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 1100 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FDIVR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fmax(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     double imm) {
+  // FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
+  //  0110 0101 ..01 1110 100. ..00 00.. ....
+  //  size<23:22> | opc<18:16> = 110 | Pg<12:10> | i1<5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(((imm == 0.0) && (copysign(1.0, imm) == 1.0)) || (imm == 1.0));
+
+  Instr i1 = (imm == 1.0) ? (1 << 5) : 0;
+  Emit(FMAX_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
+}
+
+void Assembler::fmax(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 0110 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 0110 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMAX_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fmaxnm(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn,
+                       double imm) {
+  // FMAXNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
+  //  0110 0101 ..01 1100 100. ..00 00.. ....
+  //  size<23:22> | opc<18:16> = 100 | Pg<12:10> | i1<5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(((imm == 0.0) && (copysign(1.0, imm) == 1.0)) || (imm == 1.0));
+
+  Instr i1 = (imm == 1.0) ? (1 << 5) : 0;
+  Emit(FMAXNM_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
+}
+
+void Assembler::fmaxnm(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // FMAXNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 0100 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 0100 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMAXNM_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fmin(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     double imm) {
+  // FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
+  //  0110 0101 ..01 1111 100. ..00 00.. ....
+  //  size<23:22> | opc<18:16> = 111 | Pg<12:10> | i1<5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(((imm == 0.0) && (copysign(1.0, imm) == 1.0)) || (imm == 1.0));
+
+  Instr i1 = (imm == 1.0) ? (1 << 5) : 0;
+  Emit(FMIN_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
+}
+
+void Assembler::fmin(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 0111 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 0111 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMIN_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fminnm(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn,
+                       double imm) {
+  // FMINNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
+  //  0110 0101 ..01 1101 100. ..00 00.. ....
+  //  size<23:22> | opc<18:16> = 101 | Pg<12:10> | i1<5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(((imm == 0.0) && (copysign(1.0, imm) == 1.0)) || (imm == 1.0));
+
+  Instr i1 = (imm == 1.0) ? (1 << 5) : 0;
+  Emit(FMINNM_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
+}
+
+void Assembler::fminnm(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // FMINNM <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 0101 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 0101 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMINNM_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fmul(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     double imm) {
+  // FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
+  //  0110 0101 ..01 1010 100. ..00 00.. ....
+  //  size<23:22> | opc<18:16> = 010 | Pg<12:10> | i1<5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT((imm == 0.5) || (imm == 2.0));
+
+  Instr i1 = (imm == 2.0) ? (1 << 5) : 0;
+  Emit(FMUL_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
+}
+
+void Assembler::fmul(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 0010 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 0010 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMUL_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fmulx(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FMULX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 1010 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 1010 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMULX_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fscale(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // FSCALE <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 1001 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 1001 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FSCALE_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fsub(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     double imm) {
+  // FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
+  //  0110 0101 ..01 1001 100. ..00 00.. ....
+  //  size<23:22> | opc<18:16> = 001 | Pg<12:10> | i1<5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT((imm == 0.5) || (imm == 1.0));
+
+  Instr i1 = (imm == 1.0) ? (1 << 5) : 0;
+  Emit(FSUB_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
+}
+
+void Assembler::fsub(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 0001 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 0001 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FSUB_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::fsubr(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      double imm) {
+  // FSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
+  //  0110 0101 ..01 1011 100. ..00 00.. ....
+  //  size<23:22> | opc<18:16> = 011 | Pg<12:10> | i1<5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT((imm == 0.5) || (imm == 1.0));
+
+  Instr i1 = (imm == 1.0) ? (1 << 5) : 0;
+  Emit(FSUBR_z_p_zs | SVESize(zd) | Rd(zd) | PgLow8(pg) | i1);
+}
+
+void Assembler::fsubr(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FSUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0110 0101 ..00 0011 100. .... .... ....
+  //  size<23:22> | opc<19:16> = 0011 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FSUBR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::ftmad(const ZRegister& zd,
+                      const ZRegister& zn,
+                      const ZRegister& zm,
+                      int imm3) {
+  // FTMAD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm>
+  //  0110 0101 ..01 0... 1000 00.. .... ....
+  //  size<23:22> | imm3<18:16> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FTMAD_z_zzi | SVESize(zd) | Rd(zd) | Rn(zm) |
+       ImmUnsignedField<18, 16>(imm3));
+}
+
+// SVEFPArithmeticUnpredicated.
+
+void Assembler::fadd(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 0000 00.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 000 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fmul(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 0000 10.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 010 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMUL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::frecps(const ZRegister& zd,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // FRECPS <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 0001 10.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 110 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRECPS_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::frsqrts(const ZRegister& zd,
+                        const ZRegister& zn,
+                        const ZRegister& zm) {
+  // FRSQRTS <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 0001 11.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 111 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRSQRTS_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fsub(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 0000 01.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 001 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::ftsmul(const ZRegister& zd,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // FTSMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 0000 11.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 011 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FTSMUL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+// SVEFPCompareVectors.
+
+void Assembler::facge(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FACGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 110. .... ...1 ....
+  //  size<23:22> | Zm<20:16> | op<15> = 1 | o2<13> = 0 | Pg<12:10> | Zn<9:5> |
+  //  o3<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FACGE_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::facgt(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FACGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 111. .... ...1 ....
+  //  size<23:22> | Zm<20:16> | op<15> = 1 | o2<13> = 1 | Pg<12:10> | Zn<9:5> |
+  //  o3<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FACGT_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fcmeq(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FCMEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 011. .... ...0 ....
+  //  size<23:22> | Zm<20:16> | op<15> = 0 | o2<13> = 1 | Pg<12:10> | Zn<9:5> |
+  //  o3<4> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FCMEQ_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fcmge(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FCMGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 010. .... ...0 ....
+  //  size<23:22> | Zm<20:16> | op<15> = 0 | o2<13> = 0 | Pg<12:10> | Zn<9:5> |
+  //  o3<4> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FCMGE_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fcmgt(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 010. .... ...1 ....
+  //  size<23:22> | Zm<20:16> | op<15> = 0 | o2<13> = 0 | Pg<12:10> | Zn<9:5> |
+  //  o3<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FCMGT_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fcmne(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FCMNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 011. .... ...1 ....
+  //  size<23:22> | Zm<20:16> | op<15> = 0 | o2<13> = 1 | Pg<12:10> | Zn<9:5> |
+  //  o3<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FCMNE_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fcmuo(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FCMUO <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..0. .... 110. .... ...0 ....
+  //  size<23:22> | Zm<20:16> | op<15> = 1 | o2<13> = 0 | Pg<12:10> | Zn<9:5> |
+  //  o3<4> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FCMUO_p_p_zz | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+// SVEFPCompareWithZero.
+
+void Assembler::fcmeq(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      double zero) {
+  // FCMEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
+  //  0110 0101 ..01 0010 001. .... ...0 ....
+  //  size<23:22> | eq<17> = 1 | lt<16> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
+
+  Emit(FCMEQ_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fcmge(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      double zero) {
+  // FCMGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
+  //  0110 0101 ..01 0000 001. .... ...0 ....
+  //  size<23:22> | eq<17> = 0 | lt<16> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
+
+  Emit(FCMGE_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fcmgt(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      double zero) {
+  // FCMGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
+  //  0110 0101 ..01 0000 001. .... ...1 ....
+  //  size<23:22> | eq<17> = 0 | lt<16> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 1 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
+
+  Emit(FCMGT_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fcmle(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      double zero) {
+  // FCMLE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
+  //  0110 0101 ..01 0001 001. .... ...1 ....
+  //  size<23:22> | eq<17> = 0 | lt<16> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 1 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
+
+  Emit(FCMLE_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fcmlt(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      double zero) {
+  // FCMLT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
+  //  0110 0101 ..01 0001 001. .... ...0 ....
+  //  size<23:22> | eq<17> = 0 | lt<16> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
+
+  Emit(FCMLT_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fcmne(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      double zero) {
+  // FCMNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
+  //  0110 0101 ..01 0011 001. .... ...0 ....
+  //  size<23:22> | eq<17> = 1 | lt<16> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(zero == 0.0);
+  USE(zero);
+
+  Emit(FCMNE_p_p_z0 | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn));
+}
+
+// SVEFPComplexAddition.
+
+void Assembler::fcadd(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm,
+                      int rot) {
+  // FCADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const>
+  //  0110 0100 ..00 000. 100. .... .... ....
+  //  size<23:22> | rot<16> | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT((rot == 90) || (rot == 270));
+
+  Instr rotate_bit = (rot == 90) ? 0 : (1 << 16);
+  Emit(FCADD_z_p_zz | rotate_bit | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+// SVEFPComplexMulAdd.
+
+void Assembler::fcmla(const ZRegister& zda,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm,
+                      int rot) {
+  // FCMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>
+  //  0110 0100 ..0. .... 0... .... .... ....
+  //  size<23:22> | Zm<20:16> | rot<14:13> | Pg<12:10> | Zn<9:5> | Zda<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT((rot == 0) || (rot == 90) || (rot == 180) || (rot == 270));
+
+  Instr rotate_bit = (rot / 90) << 13;
+  Emit(FCMLA_z_p_zzz | rotate_bit | SVESize(zda) | Rd(zda) | PgLow8(pg) |
+       Rn(zn) | Rm(zm));
+}
+
+// SVEFPComplexMulAddIndex.
+
+void Assembler::fcmla(const ZRegister& zda,
+                      const ZRegister& zn,
+                      const ZRegister& zm,
+                      int index,
+                      int rot) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+  VIXL_ASSERT((rot == 0) || (rot == 90) || (rot == 180) || (rot == 270));
+  VIXL_ASSERT(index >= 0);
+
+  int lane_size = zda.GetLaneSizeInBytes();
+
+  Instr zm_and_idx = 0;
+  Instr op = FCMLA_z_zzzi_h;
+  if (lane_size == kHRegSizeInBytes) {
+    // Zm<18:16> | i2<20:19>
+    VIXL_ASSERT((zm.GetCode() <= 7) && (index <= 3));
+    zm_and_idx = (index << 19) | Rx<18, 16>(zm);
+  } else {
+    // Zm<19:16> | i1<20>
+    VIXL_ASSERT(lane_size == kSRegSizeInBytes);
+    VIXL_ASSERT((zm.GetCode() <= 15) && (index <= 1));
+    zm_and_idx = (index << 20) | Rx<19, 16>(zm);
+    op = FCMLA_z_zzzi_s;
+  }
+
+  Instr rotate_bit = (rot / 90) << 10;
+  Emit(op | zm_and_idx | rotate_bit | Rd(zda) | Rn(zn));
+}
+
+// SVEFPFastReduction.
+
+void Assembler::faddv(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  // FADDV <V><d>, <Pg>, <Zn>.<T>
+  //  0110 0101 ..00 0000 001. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | Pg<12:10> | Zn<9:5> | Vd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(AreSameLaneSize(zn, vd));
+
+  Emit(FADDV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fmaxnmv(const VRegister& vd,
+                        const PRegister& pg,
+                        const ZRegister& zn) {
+  // FMAXNMV <V><d>, <Pg>, <Zn>.<T>
+  //  0110 0101 ..00 0100 001. .... .... ....
+  //  size<23:22> | opc<18:16> = 100 | Pg<12:10> | Zn<9:5> | Vd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(AreSameLaneSize(zn, vd));
+
+  Emit(FMAXNMV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fmaxv(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  // FMAXV <V><d>, <Pg>, <Zn>.<T>
+  //  0110 0101 ..00 0110 001. .... .... ....
+  //  size<23:22> | opc<18:16> = 110 | Pg<12:10> | Zn<9:5> | Vd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(AreSameLaneSize(zn, vd));
+
+  Emit(FMAXV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fminnmv(const VRegister& vd,
+                        const PRegister& pg,
+                        const ZRegister& zn) {
+  // FMINNMV <V><d>, <Pg>, <Zn>.<T>
+  //  0110 0101 ..00 0101 001. .... .... ....
+  //  size<23:22> | opc<18:16> = 101 | Pg<12:10> | Zn<9:5> | Vd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(AreSameLaneSize(zn, vd));
+
+  Emit(FMINNMV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fminv(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  // FMINV <V><d>, <Pg>, <Zn>.<T>
+  //  0110 0101 ..00 0111 001. .... .... ....
+  //  size<23:22> | opc<18:16> = 111 | Pg<12:10> | Zn<9:5> | Vd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(AreSameLaneSize(zn, vd));
+
+  Emit(FMINV_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+// SVEFPMulAdd.
+
+void Assembler::fmad(const ZRegister& zdn,
+                     const PRegisterM& pg,
+                     const ZRegister& zm,
+                     const ZRegister& za) {
+  // FMAD <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
+  //  0110 0101 ..1. .... 100. .... .... ....
+  //  size<23:22> | Za<20:16> | opc<14:13> = 00 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMAD_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rn(zm) | Rm(za));
+}
+
+void Assembler::fmla(const ZRegister& zda,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..1. .... 000. .... .... ....
+  //  size<23:22> | Zm<20:16> | opc<14:13> = 00 | Pg<12:10> | Zn<9:5> | Zda<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMLA_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fmls(const ZRegister& zda,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // FMLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..1. .... 001. .... .... ....
+  //  size<23:22> | Zm<20:16> | opc<14:13> = 01 | Pg<12:10> | Zn<9:5> | Zda<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMLS_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fmsb(const ZRegister& zdn,
+                     const PRegisterM& pg,
+                     const ZRegister& zm,
+                     const ZRegister& za) {
+  // FMSB <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
+  //  0110 0101 ..1. .... 101. .... .... ....
+  //  size<23:22> | Za<20:16> | opc<14:13> = 01 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FMSB_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rn(zm) | Rm(za));
+}
+
+void Assembler::fnmad(const ZRegister& zdn,
+                      const PRegisterM& pg,
+                      const ZRegister& zm,
+                      const ZRegister& za) {
+  // FNMAD <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
+  //  0110 0101 ..1. .... 110. .... .... ....
+  //  size<23:22> | Za<20:16> | opc<14:13> = 10 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FNMAD_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rn(zm) | Rm(za));
+}
+
+void Assembler::fnmla(const ZRegister& zda,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FNMLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..1. .... 010. .... .... ....
+  //  size<23:22> | Zm<20:16> | opc<14:13> = 10 | Pg<12:10> | Zn<9:5> | Zda<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FNMLA_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fnmls(const ZRegister& zda,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // FNMLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
+  //  0110 0101 ..1. .... 011. .... .... ....
+  //  size<23:22> | Zm<20:16> | opc<14:13> = 11 | Pg<12:10> | Zn<9:5> | Zda<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FNMLS_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::fnmsb(const ZRegister& zdn,
+                      const PRegisterM& pg,
+                      const ZRegister& zm,
+                      const ZRegister& za) {
+  // FNMSB <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
+  //  0110 0101 ..1. .... 111. .... .... ....
+  //  size<23:22> | Za<20:16> | opc<14:13> = 11 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FNMSB_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rn(zm) | Rm(za));
+}
+
+Instr Assembler::SVEFPMulIndexHelper(unsigned lane_size_in_bytes_log2,
+                                     const ZRegister& zm,
+                                     int index,
+                                     Instr op_h,
+                                     Instr op_s,
+                                     Instr op_d) {
+  Instr size = lane_size_in_bytes_log2 << SVESize_offset;
+  Instr zm_with_index = Rm(zm);
+  Instr op = 0xffffffff;
+  // Allowable register number and lane index depends on the lane size.
+  switch (lane_size_in_bytes_log2) {
+    case kHRegSizeInBytesLog2:
+      VIXL_ASSERT(zm.GetCode() <= 7);
+      VIXL_ASSERT(IsUint3(index));
+      // For H-sized lanes, size is encoded as 0b0x, where x is used as the top
+      // bit of the index. So, if index is less than four, the top bit of index
+      // is zero, and therefore size is 0b00. Otherwise, it's 0b01, the usual
+      // encoding for H-sized lanes.
+      if (index < 4) size = 0;
+      // Top two bits of "zm" encode the index.
+      zm_with_index |= (index & 3) << (Rm_offset + 3);
+      op = op_h;
+      break;
+    case kSRegSizeInBytesLog2:
+      VIXL_ASSERT(zm.GetCode() <= 7);
+      VIXL_ASSERT(IsUint2(index));
+      // Top two bits of "zm" encode the index.
+      zm_with_index |= (index & 3) << (Rm_offset + 3);
+      op = op_s;
+      break;
+    case kDRegSizeInBytesLog2:
+      VIXL_ASSERT(zm.GetCode() <= 15);
+      VIXL_ASSERT(IsUint1(index));
+      // Top bit of "zm" encodes the index.
+      zm_with_index |= (index & 1) << (Rm_offset + 4);
+      op = op_d;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+  }
+  return op | zm_with_index | size;
+}
+
+// SVEFPMulAddIndex.
+
+void Assembler::fmla(const ZRegister& zda,
+                     const ZRegister& zn,
+                     const ZRegister& zm,
+                     int index) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+
+  // The encoding of opcode, index, Zm, and size are synthesized in this
+  // variable.
+  Instr synthesized_op = SVEFPMulIndexHelper(zda.GetLaneSizeInBytesLog2(),
+                                             zm,
+                                             index,
+                                             FMLA_z_zzzi_h,
+                                             FMLA_z_zzzi_s,
+                                             FMLA_z_zzzi_d);
+
+  Emit(synthesized_op | Rd(zda) | Rn(zn));
+}
+
+void Assembler::fmls(const ZRegister& zda,
+                     const ZRegister& zn,
+                     const ZRegister& zm,
+                     int index) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+
+  // The encoding of opcode, index, Zm, and size are synthesized in this
+  // variable.
+  Instr synthesized_op = SVEFPMulIndexHelper(zda.GetLaneSizeInBytesLog2(),
+                                             zm,
+                                             index,
+                                             FMLS_z_zzzi_h,
+                                             FMLS_z_zzzi_s,
+                                             FMLS_z_zzzi_d);
+
+  Emit(synthesized_op | Rd(zda) | Rn(zn));
+}
+
+// SVEFPMulIndex.
+
+// This prototype maps to 3 instruction encodings:
+void Assembler::fmul(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm,
+                     unsigned index) {
+  // FMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T>[<imm>]
+  //  0110 0100 ..1. .... 0010 00.. .... ....
+  //  size<23:22> | opc<20:16> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  // The encoding of opcode, index, Zm, and size are synthesized in this
+  // variable.
+  Instr synthesized_op = SVEFPMulIndexHelper(zd.GetLaneSizeInBytesLog2(),
+                                             zm,
+                                             index,
+                                             FMUL_z_zzi_h,
+                                             FMUL_z_zzi_s,
+                                             FMUL_z_zzi_d);
+
+  Emit(synthesized_op | Rd(zd) | Rn(zn));
+}
+
+// SVEFPUnaryOpPredicated.
+
+void Assembler::fcvt(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Instr op = 0xffffffff;
+  switch (zn.GetLaneSizeInBytes()) {
+    case kHRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kSRegSizeInBytes:
+          op = FCVT_z_p_z_h2s;
+          break;
+        case kDRegSizeInBytes:
+          op = FCVT_z_p_z_h2d;
+          break;
+      }
+      break;
+    case kSRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = FCVT_z_p_z_s2h;
+          break;
+        case kDRegSizeInBytes:
+          op = FCVT_z_p_z_s2d;
+          break;
+      }
+      break;
+    case kDRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = FCVT_z_p_z_d2h;
+          break;
+        case kSRegSizeInBytes:
+          op = FCVT_z_p_z_d2s;
+          break;
+      }
+      break;
+  }
+  VIXL_ASSERT(op != 0xffffffff);
+
+  Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fcvtzs(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  Instr op = 0xffffffff;
+  switch (zn.GetLaneSizeInBytes()) {
+    case kHRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = FCVTZS_z_p_z_fp162h;
+          break;
+        case kSRegSizeInBytes:
+          op = FCVTZS_z_p_z_fp162w;
+          break;
+        case kDRegSizeInBytes:
+          op = FCVTZS_z_p_z_fp162x;
+          break;
+      }
+      break;
+    case kSRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kSRegSizeInBytes:
+          op = FCVTZS_z_p_z_s2w;
+          break;
+        case kDRegSizeInBytes:
+          op = FCVTZS_z_p_z_s2x;
+          break;
+      }
+      break;
+    case kDRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kSRegSizeInBytes:
+          op = FCVTZS_z_p_z_d2w;
+          break;
+        case kDRegSizeInBytes:
+          op = FCVTZS_z_p_z_d2x;
+          break;
+      }
+      break;
+  }
+  VIXL_ASSERT(op != 0xffffffff);
+
+  Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fcvtzu(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  Instr op = 0xffffffff;
+  switch (zn.GetLaneSizeInBytes()) {
+    case kHRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = FCVTZU_z_p_z_fp162h;
+          break;
+        case kSRegSizeInBytes:
+          op = FCVTZU_z_p_z_fp162w;
+          break;
+        case kDRegSizeInBytes:
+          op = FCVTZU_z_p_z_fp162x;
+          break;
+      }
+      break;
+    case kSRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kSRegSizeInBytes:
+          op = FCVTZU_z_p_z_s2w;
+          break;
+        case kDRegSizeInBytes:
+          op = FCVTZU_z_p_z_s2x;
+          break;
+      }
+      break;
+    case kDRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kSRegSizeInBytes:
+          op = FCVTZU_z_p_z_d2w;
+          break;
+        case kDRegSizeInBytes:
+          op = FCVTZU_z_p_z_d2x;
+          break;
+      }
+      break;
+  }
+  VIXL_ASSERT(op != 0xffffffff);
+
+  Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::frecpx(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  // FRECPX <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0110 0101 ..00 1100 101. .... .... ....
+  //  size<23:22> | opc<17:16> = 00 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRECPX_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::frinta(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRINTA_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::frinti(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRINTI_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::frintm(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRINTM_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::frintn(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRINTN_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::frintp(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRINTP_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::frintx(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRINTX_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::frintz(const ZRegister& zd,
+                       const PRegisterM& pg,
+                       const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRINTZ_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fsqrt(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn) {
+  // FSQRT <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0110 0101 ..00 1101 101. .... .... ....
+  //  size<23:22> | opc<17:16> = 01 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FSQRT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::scvtf(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  Instr op = 0xffffffff;
+  switch (zn.GetLaneSizeInBytes()) {
+    case kHRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = SCVTF_z_p_z_h2fp16;
+          break;
+      }
+      break;
+    case kSRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = SCVTF_z_p_z_w2fp16;
+          break;
+        case kSRegSizeInBytes:
+          op = SCVTF_z_p_z_w2s;
+          break;
+        case kDRegSizeInBytes:
+          op = SCVTF_z_p_z_w2d;
+          break;
+      }
+      break;
+    case kDRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = SCVTF_z_p_z_x2fp16;
+          break;
+        case kSRegSizeInBytes:
+          op = SCVTF_z_p_z_x2s;
+          break;
+        case kDRegSizeInBytes:
+          op = SCVTF_z_p_z_x2d;
+          break;
+      }
+      break;
+  }
+  VIXL_ASSERT(op != 0xffffffff);
+
+  Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::ucvtf(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  Instr op = 0xffffffff;
+  switch (zn.GetLaneSizeInBytes()) {
+    case kHRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = UCVTF_z_p_z_h2fp16;
+          break;
+      }
+      break;
+    case kSRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = UCVTF_z_p_z_w2fp16;
+          break;
+        case kSRegSizeInBytes:
+          op = UCVTF_z_p_z_w2s;
+          break;
+        case kDRegSizeInBytes:
+          op = UCVTF_z_p_z_w2d;
+          break;
+      }
+      break;
+    case kDRegSizeInBytes:
+      switch (zd.GetLaneSizeInBytes()) {
+        case kHRegSizeInBytes:
+          op = UCVTF_z_p_z_x2fp16;
+          break;
+        case kSRegSizeInBytes:
+          op = UCVTF_z_p_z_x2s;
+          break;
+        case kDRegSizeInBytes:
+          op = UCVTF_z_p_z_x2d;
+          break;
+      }
+      break;
+  }
+  VIXL_ASSERT(op != 0xffffffff);
+
+  Emit(op | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+// SVEFPUnaryOpUnpredicated.
+
+void Assembler::frecpe(const ZRegister& zd, const ZRegister& zn) {
+  // FRECPE <Zd>.<T>, <Zn>.<T>
+  //  0110 0101 ..00 1110 0011 00.. .... ....
+  //  size<23:22> | opc<18:16> = 110 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRECPE_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
+}
+
+void Assembler::frsqrte(const ZRegister& zd, const ZRegister& zn) {
+  // FRSQRTE <Zd>.<T>, <Zn>.<T>
+  //  0110 0101 ..00 1111 0011 00.. .... ....
+  //  size<23:22> | opc<18:16> = 111 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FRSQRTE_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
+}
+
+// SVEIncDecByPredicateCount.
+
+void Assembler::decp(const Register& rdn, const PRegisterWithLaneSize& pg) {
+  // DECP <Xdn>, <Pg>.<T>
+  //  0010 0101 ..10 1101 1000 100. .... ....
+  //  size<23:22> | op<17> = 0 | D<16> = 1 | opc2<10:9> = 00 | Pg<8:5> |
+  //  Rdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(rdn.IsX());
+
+  Emit(DECP_r_p_r | SVESize(pg) | Rd(rdn) | Rx<8, 5>(pg));
+}
+
+void Assembler::decp(const ZRegister& zdn, const PRegister& pg) {
+  // DECP <Zdn>.<T>, <Pg>
+  //  0010 0101 ..10 1101 1000 000. .... ....
+  //  size<23:22> | op<17> = 0 | D<16> = 1 | opc2<10:9> = 00 | Pg<8:5> |
+  //  Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(pg.IsUnqualified());
+
+  Emit(DECP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
+}
+
+void Assembler::incp(const Register& rdn, const PRegisterWithLaneSize& pg) {
+  // INCP <Xdn>, <Pg>.<T>
+  //  0010 0101 ..10 1100 1000 100. .... ....
+  //  size<23:22> | op<17> = 0 | D<16> = 0 | opc2<10:9> = 00 | Pg<8:5> |
+  //  Rdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(rdn.IsX());
+
+  Emit(INCP_r_p_r | SVESize(pg) | Rd(rdn) | Rx<8, 5>(pg));
+}
+
+void Assembler::incp(const ZRegister& zdn, const PRegister& pg) {
+  // INCP <Zdn>.<T>, <Pg>
+  //  0010 0101 ..10 1100 1000 000. .... ....
+  //  size<23:22> | op<17> = 0 | D<16> = 0 | opc2<10:9> = 00 | Pg<8:5> |
+  //  Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(pg.IsUnqualified());
+
+  Emit(INCP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
+}
+
+void Assembler::sqdecp(const Register& xd,
+                       const PRegisterWithLaneSize& pg,
+                       const Register& wn) {
+  // SQDECP <Xdn>, <Pg>.<T>, <Wdn>
+  //  0010 0101 ..10 1010 1000 100. .... ....
+  //  size<23:22> | D<17> = 1 | U<16> = 0 | sf<10> = 0 | op<9> = 0 | Pg<8:5> |
+  //  Rdn<4:0>
+
+  USE(wn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(xd.IsX() && wn.IsW() && xd.Aliases(wn));
+
+  Emit(SQDECP_r_p_r_sx | SVESize(pg) | Rd(xd) | Rx<8, 5>(pg));
+}
+
+void Assembler::sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg) {
+  // SQDECP <Xdn>, <Pg>.<T>
+  //  0010 0101 ..10 1010 1000 110. .... ....
+  //  size<23:22> | D<17> = 1 | U<16> = 0 | sf<10> = 1 | op<9> = 0 | Pg<8:5> |
+  //  Rdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(xdn.IsX());
+
+  Emit(SQDECP_r_p_r_x | SVESize(pg) | Rd(xdn) | Rx<8, 5>(pg));
+}
+
+void Assembler::sqdecp(const ZRegister& zdn, const PRegister& pg) {
+  // SQDECP <Zdn>.<T>, <Pg>
+  //  0010 0101 ..10 1010 1000 000. .... ....
+  //  size<23:22> | D<17> = 1 | U<16> = 0 | opc<10:9> = 00 | Pg<8:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(pg.IsUnqualified());
+
+  Emit(SQDECP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
+}
+
+void Assembler::sqincp(const Register& xd,
+                       const PRegisterWithLaneSize& pg,
+                       const Register& wn) {
+  // SQINCP <Xdn>, <Pg>.<T>, <Wdn>
+  //  0010 0101 ..10 1000 1000 100. .... ....
+  //  size<23:22> | D<17> = 0 | U<16> = 0 | sf<10> = 0 | op<9> = 0 | Pg<8:5> |
+  //  Rdn<4:0>
+
+  USE(wn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(xd.IsX() && wn.IsW() && xd.Aliases(wn));
+
+  Emit(SQINCP_r_p_r_sx | SVESize(pg) | Rd(xd) | Rx<8, 5>(pg));
+}
+
+void Assembler::sqincp(const Register& xdn, const PRegisterWithLaneSize& pg) {
+  // SQINCP <Xdn>, <Pg>.<T>
+  //  0010 0101 ..10 1000 1000 110. .... ....
+  //  size<23:22> | D<17> = 0 | U<16> = 0 | sf<10> = 1 | op<9> = 0 | Pg<8:5> |
+  //  Rdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(xdn.IsX());
+
+  Emit(SQINCP_r_p_r_x | SVESize(pg) | Rd(xdn) | Rx<8, 5>(pg));
+}
+
+void Assembler::sqincp(const ZRegister& zdn, const PRegister& pg) {
+  // SQINCP <Zdn>.<T>, <Pg>
+  //  0010 0101 ..10 1000 1000 000. .... ....
+  //  size<23:22> | D<17> = 0 | U<16> = 0 | opc<10:9> = 00 | Pg<8:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(pg.IsUnqualified());
+
+  Emit(SQINCP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
+}
+
+void Assembler::uqdecp(const Register& rdn, const PRegisterWithLaneSize& pg) {
+  // UQDECP <Wdn>, <Pg>.<T>
+  // UQDECP <Xdn>, <Pg>.<T>
+  //  0010 0101 ..10 1011 1000 10.. .... ....
+  //  size<23:22> | D<17> = 1 | U<16> = 1 | sf<10> | op<9> = 0 | Pg<8:5> |
+  //  Rdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Instr op = rdn.IsX() ? UQDECP_r_p_r_x : UQDECP_r_p_r_uw;
+  Emit(op | SVESize(pg) | Rd(rdn) | Rx<8, 5>(pg));
+}
+
+void Assembler::uqdecp(const ZRegister& zdn, const PRegister& pg) {
+  // UQDECP <Zdn>.<T>, <Pg>
+  //  0010 0101 ..10 1011 1000 000. .... ....
+  //  size<23:22> | D<17> = 1 | U<16> = 1 | opc<10:9> = 00 | Pg<8:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(pg.IsUnqualified());
+
+  Emit(UQDECP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
+}
+
+void Assembler::uqincp(const Register& rdn, const PRegisterWithLaneSize& pg) {
+  // UQINCP <Wdn>, <Pg>.<T>
+  //  0010 0101 ..10 1001 1000 100. .... ....
+  //  size<23:22> | D<17> = 0 | U<16> = 1 | sf<10> = 0 | op<9> = 0 | Pg<8:5> |
+  //  Rdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Instr op = rdn.IsX() ? UQINCP_r_p_r_x : UQINCP_r_p_r_uw;
+  Emit(op | SVESize(pg) | Rd(rdn) | Rx<8, 5>(pg));
+}
+
+void Assembler::uqincp(const ZRegister& zdn, const PRegister& pg) {
+  // UQINCP <Zdn>.<T>, <Pg>
+  //  0010 0101 ..10 1001 1000 000. .... ....
+  //  size<23:22> | D<17> = 0 | U<16> = 1 | opc<10:9> = 00 | Pg<8:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zdn.GetLaneSizeInBytes() != kBRegSizeInBytes);
+  VIXL_ASSERT(pg.IsUnqualified());
+
+  Emit(UQINCP_z_p_z | SVESize(zdn) | Rd(zdn) | Pg<8, 5>(pg));
+}
+
+// SVEIndexGeneration.
+
+void Assembler::index(const ZRegister& zd, int start, int step) {
+  // INDEX <Zd>.<T>, #<imm1>, #<imm2>
+  //  0000 0100 ..1. .... 0100 00.. .... ....
+  //  size<23:22> | step<20:16> | start<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(INDEX_z_ii | SVESize(zd) | ImmField<20, 16>(step) |
+       ImmField<9, 5>(start) | Rd(zd));
+}
+
+void Assembler::index(const ZRegister& zd,
+                      const Register& rn,
+                      const Register& rm) {
+  // INDEX <Zd>.<T>, <R><n>, <R><m>
+  //  0000 0100 ..1. .... 0100 11.. .... ....
+  //  size<23:22> | Rm<20:16> | Rn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(static_cast<unsigned>(rn.GetSizeInBits()) >=
+              zd.GetLaneSizeInBits());
+  VIXL_ASSERT(static_cast<unsigned>(rm.GetSizeInBits()) >=
+              zd.GetLaneSizeInBits());
+
+  Emit(INDEX_z_rr | SVESize(zd) | Rd(zd) | Rn(rn) | Rm(rm));
+}
+
+void Assembler::index(const ZRegister& zd, const Register& rn, int imm5) {
+  // INDEX <Zd>.<T>, <R><n>, #<imm>
+  //  0000 0100 ..1. .... 0100 01.. .... ....
+  //  size<23:22> | imm5<20:16> | Rn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(static_cast<unsigned>(rn.GetSizeInBits()) >=
+              zd.GetLaneSizeInBits());
+
+  Emit(INDEX_z_ri | SVESize(zd) | Rd(zd) | Rn(rn) | ImmField<20, 16>(imm5));
+}
+
+void Assembler::index(const ZRegister& zd, int imm5, const Register& rm) {
+  // INDEX <Zd>.<T>, #<imm>, <R><m>
+  //  0000 0100 ..1. .... 0100 10.. .... ....
+  //  size<23:22> | Rm<20:16> | imm5<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(static_cast<unsigned>(rm.GetSizeInBits()) >=
+              zd.GetLaneSizeInBits());
+
+  Emit(INDEX_z_ir | SVESize(zd) | Rd(zd) | ImmField<9, 5>(imm5) | Rm(rm));
+}
+
+// SVEIntArithmeticUnpredicated.
+
+void Assembler::add(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // ADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..1. .... 0000 00.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 000 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(ADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::sqadd(const ZRegister& zd,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // SQADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..1. .... 0001 00.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 100 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(SQADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::sqsub(const ZRegister& zd,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // SQSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..1. .... 0001 10.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 110 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(SQSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::sub(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // SUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..1. .... 0000 01.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 001 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(SUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::uqadd(const ZRegister& zd,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // UQADD <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..1. .... 0001 01.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 101 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(UQADD_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::uqsub(const ZRegister& zd,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // UQSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..1. .... 0001 11.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 111 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(UQSUB_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+// SVEIntBinaryArithmeticPredicated.
+
+void Assembler::add(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // ADD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 0000 000. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(ADD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::and_(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 1010 000. .... .... ....
+  //  size<23:22> | opc<18:16> = 010 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(AND_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::bic(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // BIC <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 1011 000. .... .... ....
+  //  size<23:22> | opc<18:16> = 011 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(BIC_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::eor(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // EOR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 1001 000. .... .... ....
+  //  size<23:22> | opc<18:16> = 001 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(EOR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::mul(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // MUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0000 000. .... .... ....
+  //  size<23:22> | H<17> = 0 | U<16> = 0 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(MUL_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::orr(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 1000 000. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(ORR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::sabd(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // SABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 1100 000. .... .... ....
+  //  size<23:22> | opc<18:17> = 10 | U<16> = 0 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(SABD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::sdiv(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0100 000. .... .... ....
+  //  size<23:22> | R<17> = 0 | U<16> = 0 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+  VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
+
+  Emit(SDIV_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::sdivr(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // SDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0110 000. .... .... ....
+  //  size<23:22> | R<17> = 1 | U<16> = 0 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+  VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
+
+  Emit(SDIVR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::smax(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 1000 000. .... .... ....
+  //  size<23:22> | opc<18:17> = 00 | U<16> = 0 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(SMAX_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::smin(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // SMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 1010 000. .... .... ....
+  //  size<23:22> | opc<18:17> = 01 | U<16> = 0 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(SMIN_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::smulh(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // SMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0010 000. .... .... ....
+  //  size<23:22> | H<17> = 1 | U<16> = 0 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(SMULH_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::sub(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // SUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 0001 000. .... .... ....
+  //  size<23:22> | opc<18:16> = 001 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(SUB_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::subr(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // SUBR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 0011 000. .... .... ....
+  //  size<23:22> | opc<18:16> = 011 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(SUBR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::uabd(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // UABD <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 1101 000. .... .... ....
+  //  size<23:22> | opc<18:17> = 10 | U<16> = 1 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(UABD_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::udiv(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // UDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0101 000. .... .... ....
+  //  size<23:22> | R<17> = 0 | U<16> = 1 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+  VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
+
+  Emit(UDIV_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::udivr(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // UDIVR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0111 000. .... .... ....
+  //  size<23:22> | R<17> = 1 | U<16> = 1 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+  VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
+
+  Emit(UDIVR_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::umax(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // UMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 1001 000. .... .... ....
+  //  size<23:22> | opc<18:17> = 00 | U<16> = 1 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(UMAX_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::umin(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..00 1011 000. .... .... ....
+  //  size<23:22> | opc<18:17> = 01 | U<16> = 1 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(UMIN_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::umulh(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  // UMULH <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0100 ..01 0011 000. .... .... ....
+  //  size<23:22> | H<17> = 1 | U<16> = 1 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(UMULH_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+// SVEIntCompareScalars.
+
+void Assembler::ctermeq(const Register& rn, const Register& rm) {
+  // CTERMEQ <R><n>, <R><m>
+  //  0010 0101 1.1. .... 0010 00.. ...0 0000
+  //  op<23> = 1 | sz<22> | Rm<20:16> | Rn<9:5> | ne<4> = 0
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameSizeAndType(rn, rm));
+  const Instr sz = rn.Is64Bits() ? 0x00400000 : 0x00000000;
+
+  Emit(CTERMEQ_rr | sz | Rn(rn) | Rm(rm));
+}
+
+void Assembler::ctermne(const Register& rn, const Register& rm) {
+  // CTERMNE <R><n>, <R><m>
+  //  0010 0101 1.1. .... 0010 00.. ...1 0000
+  //  op<23> = 1 | sz<22> | Rm<20:16> | Rn<9:5> | ne<4> = 1
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameSizeAndType(rn, rm));
+  const Instr sz = rn.Is64Bits() ? 0x00400000 : 0x00000000;
+
+  Emit(CTERMNE_rr | sz | Rn(rn) | Rm(rm));
+}
+
+void Assembler::whilele(const PRegisterWithLaneSize& pd,
+                        const Register& rn,
+                        const Register& rm) {
+  // WHILELE <Pd>.<T>, <R><n>, <R><m>
+  //  0010 0101 ..1. .... 000. 01.. ...1 ....
+  //  size<23:22> | Rm<20:16> | sf<12> | U<11> = 0 | lt<10> = 1 | Rn<9:5> |
+  //  eq<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameSizeAndType(rn, rm));
+  const Instr sf = rn.Is64Bits() ? 0x00001000 : 0x00000000;
+
+  Emit(WHILELE_p_p_rr | SVESize(pd) | sf | Pd(pd) | Rn(rn) | Rm(rm));
+}
+
+void Assembler::whilelo(const PRegisterWithLaneSize& pd,
+                        const Register& rn,
+                        const Register& rm) {
+  // WHILELO <Pd>.<T>, <R><n>, <R><m>
+  //  0010 0101 ..1. .... 000. 11.. ...0 ....
+  //  size<23:22> | Rm<20:16> | sf<12> | U<11> = 1 | lt<10> = 1 | Rn<9:5> |
+  //  eq<4> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameSizeAndType(rn, rm));
+  const Instr sf = rn.Is64Bits() ? 0x00001000 : 0x00000000;
+
+  Emit(WHILELO_p_p_rr | SVESize(pd) | sf | Pd(pd) | Rn(rn) | Rm(rm));
+}
+
+void Assembler::whilels(const PRegisterWithLaneSize& pd,
+                        const Register& rn,
+                        const Register& rm) {
+  // WHILELS <Pd>.<T>, <R><n>, <R><m>
+  //  0010 0101 ..1. .... 000. 11.. ...1 ....
+  //  size<23:22> | Rm<20:16> | sf<12> | U<11> = 1 | lt<10> = 1 | Rn<9:5> |
+  //  eq<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameSizeAndType(rn, rm));
+  const Instr sf = rn.Is64Bits() ? 0x00001000 : 0x00000000;
+
+  Emit(WHILELS_p_p_rr | SVESize(pd) | sf | Pd(pd) | Rn(rn) | Rm(rm));
+}
+
+void Assembler::whilelt(const PRegisterWithLaneSize& pd,
+                        const Register& rn,
+                        const Register& rm) {
+  // WHILELT <Pd>.<T>, <R><n>, <R><m>
+  //  0010 0101 ..1. .... 000. 01.. ...0 ....
+  //  size<23:22> | Rm<20:16> | sf<12> | U<11> = 0 | lt<10> = 1 | Rn<9:5> |
+  //  eq<4> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameSizeAndType(rn, rm));
+  const Instr sf = rn.Is64Bits() ? 0x00001000 : 0x00000000;
+
+  Emit(WHILELT_p_p_rr | SVESize(pd) | sf | Pd(pd) | Rn(rn) | Rm(rm));
+}
+
+void Assembler::CompareVectors(const PRegisterWithLaneSize& pd,
+                               const PRegisterZ& pg,
+                               const ZRegister& zn,
+                               const ZRegister& zm,
+                               SVEIntCompareVectorsOp op) {
+  Emit(op | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::CompareVectors(const PRegisterWithLaneSize& pd,
+                               const PRegisterZ& pg,
+                               const ZRegister& zn,
+                               int imm,
+                               SVEIntCompareSignedImmOp op) {
+  Emit(op | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm));
+}
+
+void Assembler::CompareVectors(const PRegisterWithLaneSize& pd,
+                               const PRegisterZ& pg,
+                               const ZRegister& zn,
+                               unsigned imm,
+                               SVEIntCompareUnsignedImmOp op) {
+  Emit(op | SVESize(zn) | Pd(pd) | PgLow8(pg) | Rn(zn) |
+       ImmUnsignedField<20, 14>(imm));
+}
+
+void Assembler::cmp(Condition cond,
+                    const PRegisterWithLaneSize& pd,
+                    const PRegisterZ& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  switch (cond) {
+    case eq:
+      cmpeq(pd, pg, zn, zm);
+      break;
+    case ge:
+      cmpge(pd, pg, zn, zm);
+      break;
+    case gt:
+      cmpgt(pd, pg, zn, zm);
+      break;
+    case le:
+      cmple(pd, pg, zn, zm);
+      break;
+    case lt:
+      cmplt(pd, pg, zn, zm);
+      break;
+    case ne:
+      cmpne(pd, pg, zn, zm);
+      break;
+    case hi:
+      cmphi(pd, pg, zn, zm);
+      break;
+    case hs:
+      cmphs(pd, pg, zn, zm);
+      break;
+    case lo:
+      cmplo(pd, pg, zn, zm);
+      break;
+    case ls:
+      cmpls(pd, pg, zn, zm);
+      break;
+    default:
+      VIXL_UNREACHABLE();
+  }
+}
+
+// SVEIntCompareSignedImm.
+
+void Assembler::cmpeq(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      int imm5) {
+  // CMPEQ <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0101 ..0. .... 100. .... ...0 ....
+  //  size<23:22> | imm5<20:16> | op<15> = 1 | o2<13> = 0 | Pg<12:10> | Zn<9:5>
+  //  | ne<4> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm5, CMPEQ_p_p_zi);
+}
+
+void Assembler::cmpge(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      int imm5) {
+  // CMPGE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0101 ..0. .... 000. .... ...0 ....
+  //  size<23:22> | imm5<20:16> | op<15> = 0 | o2<13> = 0 | Pg<12:10> | Zn<9:5>
+  //  | ne<4> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm5, CMPGE_p_p_zi);
+}
+
+void Assembler::cmpgt(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      int imm5) {
+  // CMPGT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0101 ..0. .... 000. .... ...1 ....
+  //  size<23:22> | imm5<20:16> | op<15> = 0 | o2<13> = 0 | Pg<12:10> | Zn<9:5>
+  //  | ne<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm5, CMPGT_p_p_zi);
+}
+
+void Assembler::cmple(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      int imm5) {
+  // CMPLE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0101 ..0. .... 001. .... ...1 ....
+  //  size<23:22> | imm5<20:16> | op<15> = 0 | o2<13> = 1 | Pg<12:10> | Zn<9:5>
+  //  | ne<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm5, CMPLE_p_p_zi);
+}
+
+void Assembler::cmplt(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      int imm5) {
+  // CMPLT <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0101 ..0. .... 001. .... ...0 ....
+  //  size<23:22> | imm5<20:16> | op<15> = 0 | o2<13> = 1 | Pg<12:10> | Zn<9:5>
+  //  | ne<4> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm5, CMPLT_p_p_zi);
+}
+
+void Assembler::cmpne(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      int imm5) {
+  // CMPNE <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0101 ..0. .... 100. .... ...1 ....
+  //  size<23:22> | imm5<20:16> | op<15> = 1 | o2<13> = 0 | Pg<12:10> | Zn<9:5>
+  //  | ne<4> = 1 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm5, CMPNE_p_p_zi);
+}
+
+// SVEIntCompareUnsignedImm.
+
+void Assembler::cmphi(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      unsigned imm7) {
+  // CMPHI <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0100 ..1. .... ..0. .... ...1 ....
+  //  size<23:22> | imm7<20:14> | lt<13> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 1 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm7, CMPHI_p_p_zi);
+}
+
+void Assembler::cmphs(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      unsigned imm7) {
+  // CMPHS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0100 ..1. .... ..0. .... ...0 ....
+  //  size<23:22> | imm7<20:14> | lt<13> = 0 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm7, CMPHS_p_p_zi);
+}
+
+void Assembler::cmplo(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      unsigned imm7) {
+  // CMPLO <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0100 ..1. .... ..1. .... ...0 ....
+  //  size<23:22> | imm7<20:14> | lt<13> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 0 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm7, CMPLO_p_p_zi);
+}
+
+void Assembler::cmpls(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      unsigned imm7) {
+  // CMPLS <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
+  //  0010 0100 ..1. .... ..1. .... ...1 ....
+  //  size<23:22> | imm7<20:14> | lt<13> = 1 | Pg<12:10> | Zn<9:5> | ne<4> = 1 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+
+  CompareVectors(pd, pg, zn, imm7, CMPLS_p_p_zi);
+}
+
+// SVEIntCompareVectors.
+
+// This prototype maps to 2 instruction encodings:
+//  CMPEQ_p_p_zw
+//  CMPEQ_p_p_zz
+void Assembler::cmpeq(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  SVEIntCompareVectorsOp op = CMPEQ_p_p_zz;
+  if (!AreSameLaneSize(zn, zm)) {
+    VIXL_ASSERT(zm.IsLaneSizeD());
+    op = CMPEQ_p_p_zw;
+  }
+  CompareVectors(pd, pg, zn, zm, op);
+}
+
+// This prototype maps to 2 instruction encodings:
+//  CMPGE_p_p_zw
+//  CMPGE_p_p_zz
+void Assembler::cmpge(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  SVEIntCompareVectorsOp op = CMPGE_p_p_zz;
+  if (!AreSameLaneSize(zn, zm)) {
+    VIXL_ASSERT(zm.IsLaneSizeD());
+    op = CMPGE_p_p_zw;
+  }
+  CompareVectors(pd, pg, zn, zm, op);
+}
+
+// This prototype maps to 2 instruction encodings:
+//  CMPGT_p_p_zw
+//  CMPGT_p_p_zz
+void Assembler::cmpgt(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  SVEIntCompareVectorsOp op = CMPGT_p_p_zz;
+  if (!AreSameLaneSize(zn, zm)) {
+    VIXL_ASSERT(zm.IsLaneSizeD());
+    op = CMPGT_p_p_zw;
+  }
+  CompareVectors(pd, pg, zn, zm, op);
+}
+
+// This prototype maps to 2 instruction encodings:
+//  CMPHI_p_p_zw
+//  CMPHI_p_p_zz
+void Assembler::cmphi(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  SVEIntCompareVectorsOp op = CMPHI_p_p_zz;
+  if (!AreSameLaneSize(zn, zm)) {
+    VIXL_ASSERT(zm.IsLaneSizeD());
+    op = CMPHI_p_p_zw;
+  }
+  CompareVectors(pd, pg, zn, zm, op);
+}
+
+// This prototype maps to 2 instruction encodings:
+//  CMPHS_p_p_zw
+//  CMPHS_p_p_zz
+void Assembler::cmphs(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  SVEIntCompareVectorsOp op = CMPHS_p_p_zz;
+  if (!AreSameLaneSize(zn, zm)) {
+    VIXL_ASSERT(zm.IsLaneSizeD());
+    op = CMPHS_p_p_zw;
+  }
+  CompareVectors(pd, pg, zn, zm, op);
+}
+
+void Assembler::cmple(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  if (AreSameLaneSize(zn, zm)) {
+    cmpge(pd, pg, zm, zn);
+    return;
+  }
+  VIXL_ASSERT(zm.IsLaneSizeD());
+  VIXL_ASSERT(!zn.IsLaneSizeD());
+
+  CompareVectors(pd, pg, zn, zm, CMPLE_p_p_zw);
+}
+
+void Assembler::cmplo(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  if (AreSameLaneSize(zn, zm)) {
+    cmphi(pd, pg, zm, zn);
+    return;
+  }
+  VIXL_ASSERT(zm.IsLaneSizeD());
+  VIXL_ASSERT(!zn.IsLaneSizeD());
+
+  CompareVectors(pd, pg, zn, zm, CMPLO_p_p_zw);
+}
+
+void Assembler::cmpls(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  if (AreSameLaneSize(zn, zm)) {
+    cmphs(pd, pg, zm, zn);
+    return;
+  }
+  VIXL_ASSERT(zm.IsLaneSizeD());
+  VIXL_ASSERT(!zn.IsLaneSizeD());
+
+  CompareVectors(pd, pg, zn, zm, CMPLS_p_p_zw);
+}
+
+void Assembler::cmplt(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  if (AreSameLaneSize(zn, zm)) {
+    cmpgt(pd, pg, zm, zn);
+    return;
+  }
+  VIXL_ASSERT(zm.IsLaneSizeD());
+  VIXL_ASSERT(!zn.IsLaneSizeD());
+
+  CompareVectors(pd, pg, zn, zm, CMPLT_p_p_zw);
+}
+
+// This prototype maps to 2 instruction encodings:
+//  CMPNE_p_p_zw
+//  CMPNE_p_p_zz
+void Assembler::cmpne(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const ZRegister& zn,
+                      const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, zn));
+  SVEIntCompareVectorsOp op = CMPNE_p_p_zz;
+  if (!AreSameLaneSize(zn, zm)) {
+    VIXL_ASSERT(zm.IsLaneSizeD());
+    op = CMPNE_p_p_zw;
+  }
+  CompareVectors(pd, pg, zn, zm, op);
+}
+
+// SVEIntMiscUnpredicated.
+
+void Assembler::fexpa(const ZRegister& zd, const ZRegister& zn) {
+  // FEXPA <Zd>.<T>, <Zn>.<T>
+  //  0000 0100 ..10 0000 1011 10.. .... ....
+  //  size<23:22> | opc<20:16> = 00000 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FEXPA_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
+}
+
+void Assembler::ftssel(const ZRegister& zd,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // FTSSEL <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..1. .... 1011 00.. .... ....
+  //  size<23:22> | Zm<20:16> | op<10> = 0 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FTSSEL_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::movprfx(const ZRegister& zd, const ZRegister& zn) {
+  // MOVPRFX <Zd>, <Zn>
+  //  0000 0100 0010 0000 1011 11.. .... ....
+  //  opc<23:22> = 00 | opc2<20:16> = 00000 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(MOVPRFX_z_z | Rd(zd) | Rn(zn));
+}
+
+// SVEIntMulAddPredicated.
+
+void Assembler::mad(const ZRegister& zdn,
+                    const PRegisterM& pg,
+                    const ZRegister& zm,
+                    const ZRegister& za) {
+  // MAD <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
+  //  0000 0100 ..0. .... 110. .... .... ....
+  //  size<23:22> | Zm<20:16> | op<13> = 0 | Pg<12:10> | Za<9:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
+
+  Emit(MAD_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rm(zm) | Rn(za));
+}
+
+void Assembler::mla(const ZRegister& zda,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // MLA <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..0. .... 010. .... .... ....
+  //  size<23:22> | Zm<20:16> | op<13> = 0 | Pg<12:10> | Zn<9:5> | Zda<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+
+  Emit(MLA_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::mls(const ZRegister& zda,
+                    const PRegisterM& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // MLS <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
+  //  0000 0100 ..0. .... 011. .... .... ....
+  //  size<23:22> | Zm<20:16> | op<13> = 1 | Pg<12:10> | Zn<9:5> | Zda<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zda, zn, zm));
+
+  Emit(MLS_z_p_zzz | SVESize(zda) | Rd(zda) | PgLow8(pg) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::msb(const ZRegister& zdn,
+                    const PRegisterM& pg,
+                    const ZRegister& zm,
+                    const ZRegister& za) {
+  // MSB <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
+  //  0000 0100 ..0. .... 111. .... .... ....
+  //  size<23:22> | Zm<20:16> | op<13> = 1 | Pg<12:10> | Za<9:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zdn, zm, za));
+
+  Emit(MSB_z_p_zzz | SVESize(zdn) | Rd(zdn) | PgLow8(pg) | Rm(zm) | Rn(za));
+}
+
+// SVEIntMulAddUnpredicated.
+
+void Assembler::sdot(const ZRegister& zda,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zda.IsLaneSizeS() || zda.IsLaneSizeD());
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
+  VIXL_ASSERT(AreSameLaneSize(zm, zn));
+
+  Emit(SDOT_z_zzz | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::udot(const ZRegister& zda,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zda.IsLaneSizeS() || zda.IsLaneSizeD());
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
+  VIXL_ASSERT(AreSameLaneSize(zm, zn));
+
+  Emit(UDOT_z_zzz | SVESize(zda) | Rd(zda) | Rn(zn) | Rm(zm));
+}
+
+// SVEIntReduction.
+
+void Assembler::andv(const VRegister& vd,
+                     const PRegister& pg,
+                     const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(ANDV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::eorv(const VRegister& vd,
+                     const PRegister& pg,
+                     const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(EORV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::movprfx(const ZRegister& zd,
+                        const PRegister& pg,
+                        const ZRegister& zn) {
+  // MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>
+  //  0000 0100 ..01 000. 001. .... .... ....
+  //  size<23:22> | opc<18:17> = 00 | M<16> | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(pg.IsMerging() || pg.IsZeroing());
+  VIXL_ASSERT(!pg.HasLaneSize());
+
+  Instr m = pg.IsMerging() ? 0x00010000 : 0x00000000;
+  Emit(MOVPRFX_z_p_z | SVESize(zd) | m | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::orv(const VRegister& vd,
+                    const PRegister& pg,
+                    const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(ORV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::saddv(const VRegister& dd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zn.GetLaneSizeInBytes() != kDRegSizeInBytes);
+
+  Emit(SADDV_r_p_z | SVESize(zn) | Rd(dd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::smaxv(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(SMAXV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::sminv(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(SMINV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::uaddv(const VRegister& dd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(UADDV_r_p_z | SVESize(zn) | Rd(dd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::umaxv(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(UMAXV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::uminv(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(UMINV_r_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+// SVEIntUnaryArithmeticPredicated.
+
+void Assembler::abs(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn) {
+  // ABS <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 0110 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 110 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(ABS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::cls(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn) {
+  // CLS <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 1000 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(CLS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::clz(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn) {
+  // CLZ <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 1001 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 001 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(CLZ_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::cnot(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // CNOT <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 1011 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 011 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(CNOT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::cnt(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn) {
+  // CNT <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 1010 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 010 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(CNT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fabs(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // FABS <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 1100 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 100 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FABS_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::fneg(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // FNEG <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 1101 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 101 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Emit(FNEG_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::neg(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn) {
+  // NEG <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 0111 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 111 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(NEG_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::not_(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // NOT <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 1110 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 110 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(NOT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::sxtb(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // SXTB <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 0000 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() > kBRegSizeInBytes);
+
+  Emit(SXTB_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::sxth(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // SXTH <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 0010 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 010 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() > kHRegSizeInBytes);
+
+  Emit(SXTH_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::sxtw(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // SXTW <Zd>.D, <Pg>/M, <Zn>.D
+  //  0000 0100 ..01 0100 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 100 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() > kSRegSizeInBytes);
+
+  Emit(SXTW_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::uxtb(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // UXTB <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 0001 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 001 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() > kBRegSizeInBytes);
+
+  Emit(UXTB_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::uxth(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // UXTH <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0100 ..01 0011 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 011 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() > kHRegSizeInBytes);
+
+  Emit(UXTH_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::uxtw(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // UXTW <Zd>.D, <Pg>/M, <Zn>.D
+  //  0000 0100 ..01 0101 101. .... .... ....
+  //  size<23:22> | opc<18:16> = 101 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() > kSRegSizeInBytes);
+
+  Emit(UXTW_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+// SVEIntWideImmPredicated.
+
+void Assembler::cpy(const ZRegister& zd,
+                    const PRegister& pg,
+                    int imm8,
+                    int shift) {
+  // CPY <Zd>.<T>, <Pg>/<ZM>, #<imm>{, <shift>}
+  //  0000 0101 ..01 .... 0... .... .... ....
+  //  size<23:22> | Pg<19:16> | M<14> | sh<13> | imm8<12:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pg.IsMerging() || pg.IsZeroing());
+
+  ResolveSVEImm8Shift(&imm8, &shift);
+
+  Instr sh = (shift > 0) ? (1 << 13) : 0;
+  Instr m = pg.IsMerging() ? (1 << 14) : 0;
+  Emit(CPY_z_p_i | m | sh | SVESize(zd) | Rd(zd) | Pg<19, 16>(pg) |
+       ImmField<12, 5>(imm8));
+}
+
+void Assembler::fcpy(const ZRegister& zd, const PRegisterM& pg, double imm) {
+  // FCPY <Zd>.<T>, <Pg>/M, #<const>
+  //  0000 0101 ..01 .... 110. .... .... ....
+  //  size<23:22> | Pg<19:16> | imm8<12:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Instr imm_field = ImmUnsignedField<12, 5>(FP64ToImm8(imm));
+  Emit(FCPY_z_p_i | SVESize(zd) | Rd(zd) | Pg<19, 16>(pg) | imm_field);
+}
+
+// SVEIntAddSubtractImmUnpredicated.
+
+void Assembler::SVEIntAddSubtractImmUnpredicatedHelper(
+    SVEIntAddSubtractImm_UnpredicatedOp op,
+    const ZRegister& zd,
+    int imm8,
+    int shift) {
+  if (shift < 0) {
+    VIXL_ASSERT(shift == -1);
+    // Derive the shift amount from the immediate.
+    if (IsUint8(imm8)) {
+      shift = 0;
+    } else if (IsUint16(imm8) && ((imm8 % 256) == 0)) {
+      imm8 /= 256;
+      shift = 8;
+    }
+  }
+
+  VIXL_ASSERT(IsUint8(imm8));
+  VIXL_ASSERT((shift == 0) || (shift == 8));
+
+  Instr shift_bit = (shift > 0) ? (1 << 13) : 0;
+  Emit(op | SVESize(zd) | Rd(zd) | shift_bit | ImmUnsignedField<12, 5>(imm8));
+}
+
+void Assembler::add(const ZRegister& zd,
+                    const ZRegister& zn,
+                    int imm8,
+                    int shift) {
+  // ADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
+  //  0010 0101 ..10 0000 11.. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | sh<13> | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  SVEIntAddSubtractImmUnpredicatedHelper(ADD_z_zi, zd, imm8, shift);
+}
+
+void Assembler::dup(const ZRegister& zd, int imm8, int shift) {
+  // DUP <Zd>.<T>, #<imm>{, <shift>}
+  //  0010 0101 ..11 1000 11.. .... .... ....
+  //  size<23:22> | opc<18:17> = 00 | sh<13> | imm8<12:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  ResolveSVEImm8Shift(&imm8, &shift);
+  VIXL_ASSERT((shift < 8) || !zd.IsLaneSizeB());
+
+  Instr shift_bit = (shift > 0) ? (1 << 13) : 0;
+  Emit(DUP_z_i | SVESize(zd) | Rd(zd) | shift_bit | ImmField<12, 5>(imm8));
+}
+
+void Assembler::fdup(const ZRegister& zd, double imm) {
+  // FDUP <Zd>.<T>, #<const>
+  //  0010 0101 ..11 1001 110. .... .... ....
+  //  size<23:22> | opc<18:17> = 00 | o2<13> = 0 | imm8<12:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() != kBRegSizeInBytes);
+
+  Instr encoded_imm = FP64ToImm8(imm) << 5;
+  Emit(FDUP_z_i | SVESize(zd) | encoded_imm | Rd(zd));
+}
+
+void Assembler::mul(const ZRegister& zd, const ZRegister& zn, int imm8) {
+  // MUL <Zdn>.<T>, <Zdn>.<T>, #<imm>
+  //  0010 0101 ..11 0000 110. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | o2<13> = 0 | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(MUL_z_zi | SVESize(zd) | Rd(zd) | ImmField<12, 5>(imm8));
+}
+
+void Assembler::smax(const ZRegister& zd, const ZRegister& zn, int imm8) {
+  // SMAX <Zdn>.<T>, <Zdn>.<T>, #<imm>
+  //  0010 0101 ..10 1000 110. .... .... ....
+  //  size<23:22> | opc<18:16> = 000 | o2<13> = 0 | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(SMAX_z_zi | SVESize(zd) | Rd(zd) | ImmField<12, 5>(imm8));
+}
+
+void Assembler::smin(const ZRegister& zd, const ZRegister& zn, int imm8) {
+  // SMIN <Zdn>.<T>, <Zdn>.<T>, #<imm>
+  //  0010 0101 ..10 1010 110. .... .... ....
+  //  size<23:22> | opc<18:16> = 010 | o2<13> = 0 | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(SMIN_z_zi | SVESize(zd) | Rd(zd) | ImmField<12, 5>(imm8));
+}
+
+void Assembler::sqadd(const ZRegister& zd,
+                      const ZRegister& zn,
+                      int imm8,
+                      int shift) {
+  // SQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
+  //  0010 0101 ..10 0100 11.. .... .... ....
+  //  size<23:22> | opc<18:16> = 100 | sh<13> | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  SVEIntAddSubtractImmUnpredicatedHelper(SQADD_z_zi, zd, imm8, shift);
+}
+
+void Assembler::sqsub(const ZRegister& zd,
+                      const ZRegister& zn,
+                      int imm8,
+                      int shift) {
+  // SQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
+  //  0010 0101 ..10 0110 11.. .... .... ....
+  //  size<23:22> | opc<18:16> = 110 | sh<13> | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  SVEIntAddSubtractImmUnpredicatedHelper(SQSUB_z_zi, zd, imm8, shift);
+}
+
+void Assembler::sub(const ZRegister& zd,
+                    const ZRegister& zn,
+                    int imm8,
+                    int shift) {
+  // SUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
+  //  0010 0101 ..10 0001 11.. .... .... ....
+  //  size<23:22> | opc<18:16> = 001 | sh<13> | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  SVEIntAddSubtractImmUnpredicatedHelper(SUB_z_zi, zd, imm8, shift);
+}
+
+void Assembler::subr(const ZRegister& zd,
+                     const ZRegister& zn,
+                     int imm8,
+                     int shift) {
+  // SUBR <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
+  //  0010 0101 ..10 0011 11.. .... .... ....
+  //  size<23:22> | opc<18:16> = 011 | sh<13> | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  SVEIntAddSubtractImmUnpredicatedHelper(SUBR_z_zi, zd, imm8, shift);
+}
+
+void Assembler::umax(const ZRegister& zd, const ZRegister& zn, int imm8) {
+  // UMAX <Zdn>.<T>, <Zdn>.<T>, #<imm>
+  //  0010 0101 ..10 1001 110. .... .... ....
+  //  size<23:22> | opc<18:16> = 001 | o2<13> = 0 | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(UMAX_z_zi | SVESize(zd) | Rd(zd) | ImmUnsignedField<12, 5>(imm8));
+}
+
+void Assembler::umin(const ZRegister& zd, const ZRegister& zn, int imm8) {
+  // UMIN <Zdn>.<T>, <Zdn>.<T>, #<imm>
+  //  0010 0101 ..10 1011 110. .... .... ....
+  //  size<23:22> | opc<18:16> = 011 | o2<13> = 0 | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(UMIN_z_zi | SVESize(zd) | Rd(zd) | ImmUnsignedField<12, 5>(imm8));
+}
+
+void Assembler::uqadd(const ZRegister& zd,
+                      const ZRegister& zn,
+                      int imm8,
+                      int shift) {
+  // UQADD <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
+  //  0010 0101 ..10 0101 11.. .... .... ....
+  //  size<23:22> | opc<18:16> = 101 | sh<13> | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  SVEIntAddSubtractImmUnpredicatedHelper(UQADD_z_zi, zd, imm8, shift);
+}
+
+void Assembler::uqsub(const ZRegister& zd,
+                      const ZRegister& zn,
+                      int imm8,
+                      int shift) {
+  // UQSUB <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
+  //  0010 0101 ..10 0111 11.. .... .... ....
+  //  size<23:22> | opc<18:16> = 111 | sh<13> | imm8<12:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  SVEIntAddSubtractImmUnpredicatedHelper(UQSUB_z_zi, zd, imm8, shift);
+}
+
+// SVEMemLoad.
+
+void Assembler::SVELdSt1Helper(unsigned msize_in_bytes_log2,
+                               const ZRegister& zt,
+                               const PRegister& pg,
+                               const SVEMemOperand& addr,
+                               bool is_signed,
+                               Instr op) {
+  VIXL_ASSERT(addr.IsContiguous());
+
+  Instr mem_op = SVEMemOperandHelper(msize_in_bytes_log2, 1, addr);
+  Instr dtype =
+      SVEDtype(msize_in_bytes_log2, zt.GetLaneSizeInBytesLog2(), is_signed);
+  Emit(op | mem_op | dtype | Rt(zt) | PgLow8(pg));
+}
+
+void Assembler::SVELdSt234Helper(int num_regs,
+                                 const ZRegister& zt1,
+                                 const PRegister& pg,
+                                 const SVEMemOperand& addr,
+                                 Instr op) {
+  VIXL_ASSERT((num_regs >= 2) && (num_regs <= 4));
+
+  unsigned msize_in_bytes_log2 = zt1.GetLaneSizeInBytesLog2();
+  Instr num = (num_regs - 1) << 21;
+  Instr msz = msize_in_bytes_log2 << 23;
+  Instr mem_op = SVEMemOperandHelper(msize_in_bytes_log2, num_regs, addr);
+  Emit(op | mem_op | msz | num | Rt(zt1) | PgLow8(pg));
+}
+
+void Assembler::SVELd1Helper(unsigned msize_in_bytes_log2,
+                             const ZRegister& zt,
+                             const PRegisterZ& pg,
+                             const SVEMemOperand& addr,
+                             bool is_signed) {
+  VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() >= msize_in_bytes_log2);
+  if (is_signed) {
+    // Sign-extension is only possible when the vector elements are larger than
+    // the elements in memory.
+    VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() != msize_in_bytes_log2);
+  }
+
+  if (addr.IsScatterGather()) {
+    bool is_load = true;
+    bool is_ff = false;
+    SVEScatterGatherHelper(msize_in_bytes_log2,
+                           zt,
+                           pg,
+                           addr,
+                           is_load,
+                           is_signed,
+                           is_ff);
+    return;
+  }
+
+  Instr op = 0xffffffff;
+  if (addr.IsScalarPlusImmediate()) {
+    op = SVEContiguousLoad_ScalarPlusImmFixed;
+  } else if (addr.IsScalarPlusScalar()) {
+    // Rm must not be xzr.
+    VIXL_ASSERT(!addr.GetScalarOffset().IsZero());
+    op = SVEContiguousLoad_ScalarPlusScalarFixed;
+  } else {
+    VIXL_UNIMPLEMENTED();
+  }
+  SVELdSt1Helper(msize_in_bytes_log2, zt, pg, addr, is_signed, op);
+}
+
+void Assembler::SVELdff1Helper(unsigned msize_in_bytes_log2,
+                               const ZRegister& zt,
+                               const PRegisterZ& pg,
+                               const SVEMemOperand& addr,
+                               bool is_signed) {
+  VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() >= msize_in_bytes_log2);
+  if (is_signed) {
+    // Sign-extension is only possible when the vector elements are larger than
+    // the elements in memory.
+    VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() != msize_in_bytes_log2);
+  }
+
+  if (addr.IsScatterGather()) {
+    bool is_load = true;
+    bool is_ff = true;
+    SVEScatterGatherHelper(msize_in_bytes_log2,
+                           zt,
+                           pg,
+                           addr,
+                           is_load,
+                           is_signed,
+                           is_ff);
+    return;
+  }
+
+  if (addr.IsPlainScalar()) {
+    // SVEMemOperand(x0) is treated as a scalar-plus-immediate form ([x0, #0]).
+    // In these instructions, we want to treat it as [x0, xzr].
+    SVEMemOperand addr_scalar_plus_scalar(addr.GetScalarBase(), xzr);
+    // Guard against infinite recursion.
+    VIXL_ASSERT(!addr_scalar_plus_scalar.IsPlainScalar());
+    SVELdff1Helper(msize_in_bytes_log2,
+                   zt,
+                   pg,
+                   addr_scalar_plus_scalar,
+                   is_signed);
+    return;
+  }
+
+  Instr op = 0xffffffff;
+  if (addr.IsScalarPlusScalar()) {
+    op = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed;
+  } else {
+    VIXL_UNIMPLEMENTED();
+  }
+  SVELdSt1Helper(msize_in_bytes_log2, zt, pg, addr, is_signed, op);
+}
+
+void Assembler::SVEScatterGatherHelper(unsigned msize_in_bytes_log2,
+                                       const ZRegister& zt,
+                                       const PRegister& pg,
+                                       const SVEMemOperand& addr,
+                                       bool is_load,
+                                       bool is_signed,
+                                       bool is_first_fault) {
+  VIXL_ASSERT(addr.IsScatterGather());
+  VIXL_ASSERT(zt.IsLaneSizeS() || zt.IsLaneSizeD());
+  VIXL_ASSERT(is_load || !is_first_fault);
+  VIXL_ASSERT(is_load || !is_signed);
+
+  Instr op = 0xffffffff;
+  if (addr.IsVectorPlusImmediate()) {
+    VIXL_ASSERT(AreSameLaneSize(zt, addr.GetVectorBase()));
+    if (is_load) {
+      if (zt.IsLaneSizeS()) {
+        op = SVE32BitGatherLoad_VectorPlusImmFixed;
+      } else {
+        op = SVE64BitGatherLoad_VectorPlusImmFixed;
+      }
+    } else {
+      if (zt.IsLaneSizeS()) {
+        op = SVE32BitScatterStore_VectorPlusImmFixed;
+      } else {
+        op = SVE64BitScatterStore_VectorPlusImmFixed;
+      }
+    }
+  } else {
+    VIXL_ASSERT(addr.IsScalarPlusVector());
+    VIXL_ASSERT(AreSameLaneSize(zt, addr.GetVectorOffset()));
+    SVEOffsetModifier mod = addr.GetOffsetModifier();
+    if (zt.IsLaneSizeS()) {
+      VIXL_ASSERT((mod == SVE_UXTW) || (mod == SVE_SXTW));
+      unsigned shift_amount = addr.GetShiftAmount();
+      if (shift_amount == 0) {
+        if (is_load) {
+          op = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed;
+        } else {
+          op = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed;
+        }
+      } else if (shift_amount == 1) {
+        VIXL_ASSERT(msize_in_bytes_log2 == kHRegSizeInBytesLog2);
+        if (is_load) {
+          op = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed;
+        } else {
+          op = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed;
+        }
+      } else {
+        VIXL_ASSERT(shift_amount == 2);
+        VIXL_ASSERT(msize_in_bytes_log2 == kSRegSizeInBytesLog2);
+        if (is_load) {
+          op = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed;
+        } else {
+          op = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed;
+        }
+      }
+    } else if (zt.IsLaneSizeD()) {
+      switch (mod) {
+        case NO_SVE_OFFSET_MODIFIER:
+          if (is_load) {
+            op = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed;
+          } else {
+            op = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed;
+          }
+          break;
+        case SVE_LSL:
+          if (is_load) {
+            op = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed;
+          } else {
+            op = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed;
+          }
+          break;
+        case SVE_UXTW:
+        case SVE_SXTW: {
+          unsigned shift_amount = addr.GetShiftAmount();
+          if (shift_amount == 0) {
+            if (is_load) {
+              op =
+                  SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed;
+            } else {
+              op =
+                  SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed;
+            }
+          } else {
+            VIXL_ASSERT(shift_amount == msize_in_bytes_log2);
+            if (is_load) {
+              op = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed;
+            } else {
+              op =
+                  SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed;
+            }
+          }
+          break;
+        }
+        default:
+          VIXL_UNIMPLEMENTED();
+      }
+    }
+  }
+
+  Instr mem_op = SVEMemOperandHelper(msize_in_bytes_log2, 1, addr, is_load);
+  Instr msz = ImmUnsignedField<24, 23>(msize_in_bytes_log2);
+  Instr u = (!is_load || is_signed) ? 0 : (1 << 14);
+  Instr ff = is_first_fault ? (1 << 13) : 0;
+  Emit(op | mem_op | msz | u | ff | Rt(zt) | PgLow8(pg));
+}
+
+void Assembler::SVELd234Helper(int num_regs,
+                               const ZRegister& zt1,
+                               const PRegisterZ& pg,
+                               const SVEMemOperand& addr) {
+  if (addr.IsScalarPlusScalar()) {
+    // Rm must not be xzr.
+    VIXL_ASSERT(!addr.GetScalarOffset().IsZero());
+  }
+
+  Instr op;
+  if (addr.IsScalarPlusImmediate()) {
+    op = SVELoadMultipleStructures_ScalarPlusImmFixed;
+  } else if (addr.IsScalarPlusScalar()) {
+    op = SVELoadMultipleStructures_ScalarPlusScalarFixed;
+  } else {
+    // These instructions don't support any other addressing modes.
+    VIXL_ABORT();
+  }
+  SVELdSt234Helper(num_regs, zt1, pg, addr, op);
+}
+
+// SVEMemContiguousLoad.
+
+#define VIXL_DEFINE_LD1(MSZ, LANE_SIZE)                                  \
+  void Assembler::ld1##MSZ(const ZRegister& zt,                          \
+                           const PRegisterZ& pg,                         \
+                           const SVEMemOperand& addr) {                  \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                              \
+    SVELd1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr, false); \
+  }
+#define VIXL_DEFINE_LD2(MSZ, LANE_SIZE)                 \
+  void Assembler::ld2##MSZ(const ZRegister& zt1,        \
+                           const ZRegister& zt2,        \
+                           const PRegisterZ& pg,        \
+                           const SVEMemOperand& addr) { \
+    USE(zt2);                                           \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));             \
+    VIXL_ASSERT(AreConsecutive(zt1, zt2));              \
+    VIXL_ASSERT(AreSameFormat(zt1, zt2));               \
+    VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE());           \
+    SVELd234Helper(2, zt1, pg, addr);                   \
+  }
+#define VIXL_DEFINE_LD3(MSZ, LANE_SIZE)                 \
+  void Assembler::ld3##MSZ(const ZRegister& zt1,        \
+                           const ZRegister& zt2,        \
+                           const ZRegister& zt3,        \
+                           const PRegisterZ& pg,        \
+                           const SVEMemOperand& addr) { \
+    USE(zt2, zt3);                                      \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));             \
+    VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3));         \
+    VIXL_ASSERT(AreSameFormat(zt1, zt2, zt3));          \
+    VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE());           \
+    SVELd234Helper(3, zt1, pg, addr);                   \
+  }
+#define VIXL_DEFINE_LD4(MSZ, LANE_SIZE)                 \
+  void Assembler::ld4##MSZ(const ZRegister& zt1,        \
+                           const ZRegister& zt2,        \
+                           const ZRegister& zt3,        \
+                           const ZRegister& zt4,        \
+                           const PRegisterZ& pg,        \
+                           const SVEMemOperand& addr) { \
+    USE(zt2, zt3, zt4);                                 \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));             \
+    VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3, zt4));    \
+    VIXL_ASSERT(AreSameFormat(zt1, zt2, zt3, zt4));     \
+    VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE());           \
+    SVELd234Helper(4, zt1, pg, addr);                   \
+  }
+
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_LD1)
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_LD2)
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_LD3)
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_LD4)
+
+#define VIXL_DEFINE_LD1S(MSZ, LANE_SIZE)                                \
+  void Assembler::ld1s##MSZ(const ZRegister& zt,                        \
+                            const PRegisterZ& pg,                       \
+                            const SVEMemOperand& addr) {                \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                             \
+    SVELd1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr, true); \
+  }
+VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST(VIXL_DEFINE_LD1S)
+
+// SVEMem32BitGatherAndUnsizedContiguous.
+
+void Assembler::SVELd1BroadcastHelper(unsigned msize_in_bytes_log2,
+                                      const ZRegister& zt,
+                                      const PRegisterZ& pg,
+                                      const SVEMemOperand& addr,
+                                      bool is_signed) {
+  VIXL_ASSERT(addr.IsScalarPlusImmediate());
+  VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() >= msize_in_bytes_log2);
+  if (is_signed) {
+    // Sign-extension is only possible when the vector elements are larger than
+    // the elements in memory.
+    VIXL_ASSERT(zt.GetLaneSizeInBytesLog2() != msize_in_bytes_log2);
+  }
+
+  int64_t imm = addr.GetImmediateOffset();
+  int divisor = 1 << msize_in_bytes_log2;
+  VIXL_ASSERT(imm % divisor == 0);
+  Instr dtype = SVEDtypeSplit(msize_in_bytes_log2,
+                              zt.GetLaneSizeInBytesLog2(),
+                              is_signed);
+
+  Emit(SVELoadAndBroadcastElementFixed | dtype | RnSP(addr.GetScalarBase()) |
+       ImmUnsignedField<21, 16>(imm / divisor) | Rt(zt) | PgLow8(pg));
+}
+
+// This prototype maps to 4 instruction encodings:
+//  LD1RB_z_p_bi_u16
+//  LD1RB_z_p_bi_u32
+//  LD1RB_z_p_bi_u64
+//  LD1RB_z_p_bi_u8
+void Assembler::ld1rb(const ZRegister& zt,
+                      const PRegisterZ& pg,
+                      const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  SVELd1BroadcastHelper(kBRegSizeInBytesLog2, zt, pg, addr, false);
+}
+
+// This prototype maps to 3 instruction encodings:
+//  LD1RH_z_p_bi_u16
+//  LD1RH_z_p_bi_u32
+//  LD1RH_z_p_bi_u64
+void Assembler::ld1rh(const ZRegister& zt,
+                      const PRegisterZ& pg,
+                      const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  SVELd1BroadcastHelper(kHRegSizeInBytesLog2, zt, pg, addr, false);
+}
+
+// This prototype maps to 2 instruction encodings:
+//  LD1RW_z_p_bi_u32
+//  LD1RW_z_p_bi_u64
+void Assembler::ld1rw(const ZRegister& zt,
+                      const PRegisterZ& pg,
+                      const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  SVELd1BroadcastHelper(kSRegSizeInBytesLog2, zt, pg, addr, false);
+}
+
+void Assembler::ld1rd(const ZRegister& zt,
+                      const PRegisterZ& pg,
+                      const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  SVELd1BroadcastHelper(kDRegSizeInBytesLog2, zt, pg, addr, false);
+}
+
+// This prototype maps to 3 instruction encodings:
+//  LD1RSB_z_p_bi_s16
+//  LD1RSB_z_p_bi_s32
+//  LD1RSB_z_p_bi_s64
+void Assembler::ld1rsb(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  SVELd1BroadcastHelper(kBRegSizeInBytesLog2, zt, pg, addr, true);
+}
+
+// This prototype maps to 2 instruction encodings:
+//  LD1RSH_z_p_bi_s32
+//  LD1RSH_z_p_bi_s64
+void Assembler::ld1rsh(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  SVELd1BroadcastHelper(kHRegSizeInBytesLog2, zt, pg, addr, true);
+}
+
+void Assembler::ld1rsw(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  SVELd1BroadcastHelper(kWRegSizeInBytesLog2, zt, pg, addr, true);
+}
+
+void Assembler::ldr(const CPURegister& rt, const SVEMemOperand& addr) {
+  // LDR <Pt/Zt>, [<Xn|SP>{, #<imm>, MUL VL}]
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(rt.IsPRegister() || rt.IsZRegister());
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+  int64_t imm9 = addr.GetImmediateOffset();
+  VIXL_ASSERT(IsInt9(imm9));
+  Instr imm9l = ExtractUnsignedBitfield32(2, 0, imm9) << 10;
+  Instr imm9h = ExtractUnsignedBitfield32(8, 3, imm9) << 16;
+
+  Instr op = LDR_z_bi;
+  if (rt.IsPRegister()) {
+    op = LDR_p_bi;
+  }
+  Emit(op | Rt(rt) | RnSP(addr.GetScalarBase()) | imm9h | imm9l);
+}
+
+// SVEMem64BitGather.
+
+// This prototype maps to 3 instruction encodings:
+//  LDFF1B_z_p_bz_d_64_unscaled
+//  LDFF1B_z_p_bz_d_x32_unscaled
+void Assembler::ldff1b(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const Register& xn,
+                       const ZRegister& zm) {
+  // LDFF1B { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
+  //  1100 0100 010. .... 111. .... .... ....
+  //  msz<24:23> = 00 | Zm<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> | Rn<9:5>
+  //  | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1B_z_p_bz_d_64_unscaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
+}
+
+// This prototype maps to 2 instruction encodings:
+//  LDFF1B_z_p_ai_d
+//  LDFF1B_z_p_ai_s
+void Assembler::ldff1b(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const ZRegister& zn,
+                       int imm5) {
+  // LDFF1B { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
+  //  1100 0100 001. .... 111. .... .... ....
+  //  msz<24:23> = 00 | imm5<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> |
+  //  Zn<9:5> | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1B_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
+}
+
+// This prototype maps to 4 instruction encodings:
+//  LDFF1D_z_p_bz_d_64_scaled
+//  LDFF1D_z_p_bz_d_64_unscaled
+//  LDFF1D_z_p_bz_d_x32_scaled
+//  LDFF1D_z_p_bz_d_x32_unscaled
+void Assembler::ldff1d(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const Register& xn,
+                       const ZRegister& zm) {
+  // LDFF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
+  //  1100 0101 111. .... 111. .... .... ....
+  //  msz<24:23> = 11 | Zm<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> | Rn<9:5>
+  //  | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1D_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
+}
+
+void Assembler::ldff1d(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const ZRegister& zn,
+                       int imm5) {
+  // LDFF1D { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
+  //  1100 0101 101. .... 111. .... .... ....
+  //  msz<24:23> = 11 | imm5<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> |
+  //  Zn<9:5> | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1D_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
+}
+
+// This prototype maps to 6 instruction encodings:
+//  LDFF1H_z_p_bz_d_64_scaled
+//  LDFF1H_z_p_bz_d_64_unscaled
+//  LDFF1H_z_p_bz_d_x32_scaled
+//  LDFF1H_z_p_bz_d_x32_unscaled
+void Assembler::ldff1h(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const Register& xn,
+                       const ZRegister& zm) {
+  // LDFF1H { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
+  //  1100 0100 111. .... 111. .... .... ....
+  //  msz<24:23> = 01 | Zm<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> | Rn<9:5>
+  //  | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1H_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
+}
+
+// This prototype maps to 2 instruction encodings:
+//  LDFF1H_z_p_ai_d
+//  LDFF1H_z_p_ai_s
+void Assembler::ldff1h(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const ZRegister& zn,
+                       int imm5) {
+  // LDFF1H { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
+  //  1100 0100 101. .... 111. .... .... ....
+  //  msz<24:23> = 01 | imm5<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> |
+  //  Zn<9:5> | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1H_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
+}
+
+// This prototype maps to 3 instruction encodings:
+//  LDFF1SB_z_p_bz_d_64_unscaled
+//  LDFF1SB_z_p_bz_d_x32_unscaled
+void Assembler::ldff1sb(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const Register& xn,
+                        const ZRegister& zm) {
+  // LDFF1SB { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
+  //  1100 0100 010. .... 101. .... .... ....
+  //  msz<24:23> = 00 | Zm<20:16> | U<14> = 0 | ff<13> = 1 | Pg<12:10> | Rn<9:5>
+  //  | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1SB_z_p_bz_d_64_unscaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
+}
+
+// This prototype maps to 2 instruction encodings:
+//  LDFF1SB_z_p_ai_d
+//  LDFF1SB_z_p_ai_s
+void Assembler::ldff1sb(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const ZRegister& zn,
+                        int imm5) {
+  // LDFF1SB { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
+  //  1100 0100 001. .... 101. .... .... ....
+  //  msz<24:23> = 00 | imm5<20:16> | U<14> = 0 | ff<13> = 1 | Pg<12:10> |
+  //  Zn<9:5> | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1SB_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
+       ImmField<20, 16>(imm5));
+}
+
+// This prototype maps to 6 instruction encodings:
+//  LDFF1SH_z_p_bz_d_64_scaled
+//  LDFF1SH_z_p_bz_d_64_unscaled
+//  LDFF1SH_z_p_bz_d_x32_scaled
+//  LDFF1SH_z_p_bz_d_x32_unscaled
+void Assembler::ldff1sh(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const Register& xn,
+                        const ZRegister& zm) {
+  // LDFF1SH { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
+  //  1100 0100 111. .... 101. .... .... ....
+  //  msz<24:23> = 01 | Zm<20:16> | U<14> = 0 | ff<13> = 1 | Pg<12:10> | Rn<9:5>
+  //  | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1SH_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
+}
+
+// This prototype maps to 2 instruction encodings:
+//  LDFF1SH_z_p_ai_d
+//  LDFF1SH_z_p_ai_s
+void Assembler::ldff1sh(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const ZRegister& zn,
+                        int imm5) {
+  // LDFF1SH { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
+  //  1100 0100 101. .... 101. .... .... ....
+  //  msz<24:23> = 01 | imm5<20:16> | U<14> = 0 | ff<13> = 1 | Pg<12:10> |
+  //  Zn<9:5> | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1SH_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
+       ImmField<20, 16>(imm5));
+}
+
+// This prototype maps to 4 instruction encodings:
+//  LDFF1SW_z_p_bz_d_64_scaled
+//  LDFF1SW_z_p_bz_d_64_unscaled
+//  LDFF1SW_z_p_bz_d_x32_scaled
+//  LDFF1SW_z_p_bz_d_x32_unscaled
+void Assembler::ldff1sw(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const Register& xn,
+                        const ZRegister& zm) {
+  // LDFF1SW { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
+  //  1100 0101 011. .... 101. .... .... ....
+  //  msz<24:23> = 10 | Zm<20:16> | U<14> = 0 | ff<13> = 1 | Pg<12:10> | Rn<9:5>
+  //  | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1SW_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
+}
+
+void Assembler::ldff1sw(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const ZRegister& zn,
+                        int imm5) {
+  // LDFF1SW { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
+  //  1100 0101 001. .... 101. .... .... ....
+  //  msz<24:23> = 10 | imm5<20:16> | U<14> = 0 | ff<13> = 1 | Pg<12:10> |
+  //  Zn<9:5> | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1SW_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) |
+       ImmField<20, 16>(imm5));
+}
+
+// This prototype maps to 6 instruction encodings:
+//  LDFF1W_z_p_bz_d_64_scaled
+//  LDFF1W_z_p_bz_d_64_unscaled
+//  LDFF1W_z_p_bz_d_x32_scaled
+//  LDFF1W_z_p_bz_d_x32_unscaled
+void Assembler::ldff1w(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const Register& xn,
+                       const ZRegister& zm) {
+  // LDFF1W { <Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
+  //  1100 0101 011. .... 111. .... .... ....
+  //  msz<24:23> = 10 | Zm<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> | Rn<9:5>
+  //  | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1W_z_p_bz_d_64_scaled | Rt(zt) | PgLow8(pg) | RnSP(xn) | Rm(zm));
+}
+
+// This prototype maps to 2 instruction encodings:
+//  LDFF1W_z_p_ai_d
+//  LDFF1W_z_p_ai_s
+void Assembler::ldff1w(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const ZRegister& zn,
+                       int imm5) {
+  // LDFF1W { <Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
+  //  1100 0101 001. .... 111. .... .... ....
+  //  msz<24:23> = 10 | imm5<20:16> | U<14> = 1 | ff<13> = 1 | Pg<12:10> |
+  //  Zn<9:5> | Zt<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LDFF1W_z_p_ai_d | Rt(zt) | PgLow8(pg) | Rn(zn) | ImmField<20, 16>(imm5));
+}
+
+void Assembler::SVEGatherPrefetchVectorPlusImmediateHelper(
+    PrefetchOperation prfop,
+    const PRegister& pg,
+    const SVEMemOperand& addr,
+    int prefetch_size) {
+  VIXL_ASSERT(addr.IsVectorPlusImmediate());
+  ZRegister zn = addr.GetVectorBase();
+  VIXL_ASSERT(zn.IsLaneSizeS() || zn.IsLaneSizeD());
+
+  Instr op = 0xffffffff;
+  switch (prefetch_size) {
+    case kBRegSize:
+      op = zn.IsLaneSizeS() ? static_cast<Instr>(PRFB_i_p_ai_s)
+                            : static_cast<Instr>(PRFB_i_p_ai_d);
+      break;
+    case kHRegSize:
+      op = zn.IsLaneSizeS() ? static_cast<Instr>(PRFH_i_p_ai_s)
+                            : static_cast<Instr>(PRFH_i_p_ai_d);
+      break;
+    case kSRegSize:
+      op = zn.IsLaneSizeS() ? static_cast<Instr>(PRFW_i_p_ai_s)
+                            : static_cast<Instr>(PRFW_i_p_ai_d);
+      break;
+    case kDRegSize:
+      op = zn.IsLaneSizeS() ? static_cast<Instr>(PRFD_i_p_ai_s)
+                            : static_cast<Instr>(PRFD_i_p_ai_d);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  int64_t imm5 = addr.GetImmediateOffset();
+  Emit(op | SVEImmPrefetchOperation(prfop) | PgLow8(pg) | Rn(zn) |
+       ImmUnsignedField<20, 16>(imm5));
+}
+
+void Assembler::SVEGatherPrefetchScalarPlusImmediateHelper(
+    PrefetchOperation prfop,
+    const PRegister& pg,
+    const SVEMemOperand& addr,
+    int prefetch_size) {
+  VIXL_ASSERT(addr.IsScalarPlusImmediate());
+  int64_t imm6 = addr.GetImmediateOffset();
+
+  Instr op = 0xffffffff;
+  switch (prefetch_size) {
+    case kBRegSize:
+      op = PRFB_i_p_bi_s;
+      break;
+    case kHRegSize:
+      op = PRFH_i_p_bi_s;
+      break;
+    case kSRegSize:
+      op = PRFW_i_p_bi_s;
+      break;
+    case kDRegSize:
+      op = PRFD_i_p_bi_s;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  Emit(op | SVEImmPrefetchOperation(prfop) | PgLow8(pg) |
+       RnSP(addr.GetScalarBase()) | ImmField<21, 16>(imm6));
+}
+
+void Assembler::SVEContiguousPrefetchScalarPlusScalarHelper(
+    PrefetchOperation prfop,
+    const PRegister& pg,
+    const SVEMemOperand& addr,
+    int prefetch_size) {
+  VIXL_ASSERT(addr.IsScalarPlusScalar());
+  Instr op = 0xffffffff;
+
+  switch (prefetch_size) {
+    case kBRegSize:
+      VIXL_ASSERT(addr.GetOffsetModifier() == NO_SVE_OFFSET_MODIFIER);
+      op = PRFB_i_p_br_s;
+      break;
+    case kHRegSize:
+      VIXL_ASSERT(addr.GetOffsetModifier() == SVE_LSL);
+      VIXL_ASSERT(addr.GetShiftAmount() == kHRegSizeInBytesLog2);
+      op = PRFH_i_p_br_s;
+      break;
+    case kSRegSize:
+      VIXL_ASSERT(addr.GetOffsetModifier() == SVE_LSL);
+      VIXL_ASSERT(addr.GetShiftAmount() == kSRegSizeInBytesLog2);
+      op = PRFW_i_p_br_s;
+      break;
+    case kDRegSize:
+      VIXL_ASSERT(addr.GetOffsetModifier() == SVE_LSL);
+      VIXL_ASSERT(addr.GetShiftAmount() == kDRegSizeInBytesLog2);
+      op = PRFD_i_p_br_s;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  VIXL_ASSERT(!addr.GetScalarOffset().IsZero());
+  Emit(op | SVEImmPrefetchOperation(prfop) | PgLow8(pg) |
+       RnSP(addr.GetScalarBase()) | Rm(addr.GetScalarOffset()));
+}
+
+void Assembler::SVEContiguousPrefetchScalarPlusVectorHelper(
+    PrefetchOperation prfop,
+    const PRegister& pg,
+    const SVEMemOperand& addr,
+    int prefetch_size) {
+  VIXL_ASSERT(addr.IsScalarPlusVector());
+  ZRegister zm = addr.GetVectorOffset();
+  SVEOffsetModifier mod = addr.GetOffsetModifier();
+
+  // All prefetch scalar-plus-vector addressing modes use a shift corresponding
+  // to the element size.
+  switch (prefetch_size) {
+    case kBRegSize:
+      VIXL_ASSERT(addr.GetShiftAmount() == kBRegSizeInBytesLog2);
+      break;
+    case kHRegSize:
+      VIXL_ASSERT(addr.GetShiftAmount() == kHRegSizeInBytesLog2);
+      break;
+    case kSRegSize:
+      VIXL_ASSERT(addr.GetShiftAmount() == kSRegSizeInBytesLog2);
+      break;
+    case kDRegSize:
+      VIXL_ASSERT(addr.GetShiftAmount() == kDRegSizeInBytesLog2);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  Instr sx = 0;
+  Instr op = 0xffffffff;
+  if ((mod == NO_SVE_OFFSET_MODIFIER) || (mod == SVE_LSL)) {
+    VIXL_ASSERT(zm.IsLaneSizeD());
+
+    switch (prefetch_size) {
+      case kBRegSize:
+        VIXL_ASSERT(mod == NO_SVE_OFFSET_MODIFIER);
+        op = PRFB_i_p_bz_d_64_scaled;
+        break;
+      case kHRegSize:
+        VIXL_ASSERT(mod == SVE_LSL);
+        op = PRFH_i_p_bz_d_64_scaled;
+        break;
+      case kSRegSize:
+        VIXL_ASSERT(mod == SVE_LSL);
+        op = PRFW_i_p_bz_d_64_scaled;
+        break;
+      case kDRegSize:
+        VIXL_ASSERT(mod == SVE_LSL);
+        op = PRFD_i_p_bz_d_64_scaled;
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  } else {
+    VIXL_ASSERT((mod == SVE_SXTW) || (mod == SVE_UXTW));
+    VIXL_ASSERT(zm.IsLaneSizeS() || zm.IsLaneSizeD());
+
+    switch (prefetch_size) {
+      case kBRegSize:
+        op = zm.IsLaneSizeS() ? static_cast<Instr>(PRFB_i_p_bz_s_x32_scaled)
+                              : static_cast<Instr>(PRFB_i_p_bz_d_x32_scaled);
+        break;
+      case kHRegSize:
+        op = zm.IsLaneSizeS() ? static_cast<Instr>(PRFH_i_p_bz_s_x32_scaled)
+                              : static_cast<Instr>(PRFH_i_p_bz_d_x32_scaled);
+        break;
+      case kSRegSize:
+        op = zm.IsLaneSizeS() ? static_cast<Instr>(PRFW_i_p_bz_s_x32_scaled)
+                              : static_cast<Instr>(PRFW_i_p_bz_d_x32_scaled);
+        break;
+      case kDRegSize:
+        op = zm.IsLaneSizeS() ? static_cast<Instr>(PRFD_i_p_bz_s_x32_scaled)
+                              : static_cast<Instr>(PRFD_i_p_bz_d_x32_scaled);
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+
+    if (mod == SVE_SXTW) {
+      sx = 1 << 22;
+    }
+  }
+
+  Emit(op | SVEImmPrefetchOperation(prfop) | PgLow8(pg) | sx |
+       RnSP(addr.GetScalarBase()) | Rm(zm));
+}
+
+void Assembler::SVEPrefetchHelper(PrefetchOperation prfop,
+                                  const PRegister& pg,
+                                  const SVEMemOperand& addr,
+                                  int prefetch_size) {
+  if (addr.IsVectorPlusImmediate()) {
+    // For example:
+    //   [z0.s, #0]
+    SVEGatherPrefetchVectorPlusImmediateHelper(prfop, pg, addr, prefetch_size);
+
+  } else if (addr.IsScalarPlusImmediate()) {
+    // For example:
+    //   [x0, #42, mul vl]
+    SVEGatherPrefetchScalarPlusImmediateHelper(prfop, pg, addr, prefetch_size);
+
+  } else if (addr.IsScalarPlusVector()) {
+    // For example:
+    //   [x0, z0.s, sxtw]
+    SVEContiguousPrefetchScalarPlusVectorHelper(prfop, pg, addr, prefetch_size);
+
+  } else if (addr.IsScalarPlusScalar()) {
+    // For example:
+    //   [x0, x1]
+    SVEContiguousPrefetchScalarPlusScalarHelper(prfop, pg, addr, prefetch_size);
+
+  } else {
+    VIXL_UNIMPLEMENTED();
+  }
+}
+
+void Assembler::prfb(PrefetchOperation prfop,
+                     const PRegister& pg,
+                     const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  SVEPrefetchHelper(prfop, pg, addr, kBRegSize);
+}
+
+void Assembler::prfd(PrefetchOperation prfop,
+                     const PRegister& pg,
+                     const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  SVEPrefetchHelper(prfop, pg, addr, kDRegSize);
+}
+
+void Assembler::prfh(PrefetchOperation prfop,
+                     const PRegister& pg,
+                     const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  SVEPrefetchHelper(prfop, pg, addr, kHRegSize);
+}
+
+void Assembler::prfw(PrefetchOperation prfop,
+                     const PRegister& pg,
+                     const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  SVEPrefetchHelper(prfop, pg, addr, kSRegSize);
+}
+
+void Assembler::SVELd1St1ScaImmHelper(const ZRegister& zt,
+                                      const PRegister& pg,
+                                      const SVEMemOperand& addr,
+                                      Instr regoffset_op,
+                                      Instr immoffset_op,
+                                      int imm_divisor) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsScalarPlusScalar() || addr.IsScalarPlusImmediate());
+
+  Instr op;
+  if (addr.IsScalarPlusScalar()) {
+    op = regoffset_op | Rm(addr.GetScalarOffset());
+  } else {
+    int64_t imm = addr.GetImmediateOffset();
+    VIXL_ASSERT(((imm % imm_divisor) == 0) && IsInt4(imm / imm_divisor));
+    op = immoffset_op | ImmField<19, 16>(imm / imm_divisor);
+  }
+  Emit(op | Rt(zt) | PgLow8(pg) | RnSP(addr.GetScalarBase()));
+}
+
+void Assembler::ld1rqb(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsScalarPlusImmediate() || addr.IsEquivalentToLSL(0));
+  VIXL_ASSERT(zt.IsLaneSizeB());
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        LD1RQB_z_p_br_contiguous,
+                        LD1RQB_z_p_bi_u8,
+                        16);
+}
+
+void Assembler::ld1rqd(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsScalarPlusImmediate() || addr.IsEquivalentToLSL(3));
+  VIXL_ASSERT(zt.IsLaneSizeD());
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        LD1RQD_z_p_br_contiguous,
+                        LD1RQD_z_p_bi_u64,
+                        16);
+}
+
+void Assembler::ld1rqh(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsScalarPlusImmediate() || addr.IsEquivalentToLSL(1));
+  VIXL_ASSERT(zt.IsLaneSizeH());
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        LD1RQH_z_p_br_contiguous,
+                        LD1RQH_z_p_bi_u16,
+                        16);
+}
+
+void Assembler::ld1rqw(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsScalarPlusImmediate() || addr.IsEquivalentToLSL(2));
+  VIXL_ASSERT(zt.IsLaneSizeS());
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        LD1RQW_z_p_br_contiguous,
+                        LD1RQW_z_p_bi_u32,
+                        16);
+}
+
+#define VIXL_DEFINE_LDFF1(MSZ, LANE_SIZE)                                  \
+  void Assembler::ldff1##MSZ(const ZRegister& zt,                          \
+                             const PRegisterZ& pg,                         \
+                             const SVEMemOperand& addr) {                  \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                                \
+    SVELdff1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr, false); \
+  }
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_LDFF1)
+
+#define VIXL_DEFINE_LDFF1S(MSZ, LANE_SIZE)                                \
+  void Assembler::ldff1s##MSZ(const ZRegister& zt,                        \
+                              const PRegisterZ& pg,                       \
+                              const SVEMemOperand& addr) {                \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                               \
+    SVELdff1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr, true); \
+  }
+VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST(VIXL_DEFINE_LDFF1S)
+
+void Assembler::ldnf1b(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsPlainRegister() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+
+  SVELdSt1Helper(0,
+                 zt,
+                 pg,
+                 addr,
+                 /* is_signed = */ false,
+                 SVEContiguousNonFaultLoad_ScalarPlusImmFixed);
+}
+
+void Assembler::ldnf1d(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsPlainRegister() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+
+  SVELdSt1Helper(3,
+                 zt,
+                 pg,
+                 addr,
+                 /* is_signed = */ false,
+                 SVEContiguousNonFaultLoad_ScalarPlusImmFixed);
+}
+
+void Assembler::ldnf1h(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsPlainRegister() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+
+  SVELdSt1Helper(1,
+                 zt,
+                 pg,
+                 addr,
+                 /* is_signed = */ false,
+                 SVEContiguousNonFaultLoad_ScalarPlusImmFixed);
+}
+
+void Assembler::ldnf1sb(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsPlainRegister() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+
+  SVELdSt1Helper(0,
+                 zt,
+                 pg,
+                 addr,
+                 /* is_signed = */ true,
+                 SVEContiguousNonFaultLoad_ScalarPlusImmFixed);
+}
+
+void Assembler::ldnf1sh(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsPlainRegister() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+
+  SVELdSt1Helper(1,
+                 zt,
+                 pg,
+                 addr,
+                 /* is_signed = */ true,
+                 SVEContiguousNonFaultLoad_ScalarPlusImmFixed);
+}
+
+void Assembler::ldnf1sw(const ZRegister& zt,
+                        const PRegisterZ& pg,
+                        const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsPlainRegister() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+
+  SVELdSt1Helper(2,
+                 zt,
+                 pg,
+                 addr,
+                 /* is_signed = */ true,
+                 SVEContiguousNonFaultLoad_ScalarPlusImmFixed);
+}
+
+void Assembler::ldnf1w(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(addr.IsPlainRegister() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+
+  SVELdSt1Helper(2,
+                 zt,
+                 pg,
+                 addr,
+                 /* is_signed = */ false,
+                 SVEContiguousNonFaultLoad_ScalarPlusImmFixed);
+}
+
+void Assembler::ldnt1b(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() && addr.IsMulVl()) ||
+              (addr.IsScalarPlusScalar() && addr.IsEquivalentToLSL(0)));
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        LDNT1B_z_p_br_contiguous,
+                        LDNT1B_z_p_bi_contiguous);
+}
+
+void Assembler::ldnt1d(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() && addr.IsMulVl()) ||
+              (addr.IsScalarPlusScalar() && addr.IsEquivalentToLSL(3)));
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        LDNT1D_z_p_br_contiguous,
+                        LDNT1D_z_p_bi_contiguous);
+}
+
+void Assembler::ldnt1h(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() && addr.IsMulVl()) ||
+              (addr.IsScalarPlusScalar() && addr.IsEquivalentToLSL(1)));
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        LDNT1H_z_p_br_contiguous,
+                        LDNT1H_z_p_bi_contiguous);
+}
+
+void Assembler::ldnt1w(const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() && addr.IsMulVl()) ||
+              (addr.IsScalarPlusScalar() && addr.IsEquivalentToLSL(2)));
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        LDNT1W_z_p_br_contiguous,
+                        LDNT1W_z_p_bi_contiguous);
+}
+
+Instr Assembler::SVEMemOperandHelper(unsigned msize_in_bytes_log2,
+                                     int num_regs,
+                                     const SVEMemOperand& addr,
+                                     bool is_load) {
+  VIXL_ASSERT((num_regs >= 1) && (num_regs <= 4));
+
+  Instr op = 0xfffffff;
+  if (addr.IsScalarPlusImmediate()) {
+    VIXL_ASSERT((addr.GetImmediateOffset() == 0) || addr.IsMulVl());
+    int64_t imm = addr.GetImmediateOffset();
+    VIXL_ASSERT((imm % num_regs) == 0);
+    op = RnSP(addr.GetScalarBase()) | ImmField<19, 16>(imm / num_regs);
+
+  } else if (addr.IsScalarPlusScalar()) {
+    VIXL_ASSERT(addr.GetScalarOffset().IsZero() ||
+                addr.IsEquivalentToLSL(msize_in_bytes_log2));
+    op = RnSP(addr.GetScalarBase()) | Rm(addr.GetScalarOffset());
+
+  } else if (addr.IsVectorPlusImmediate()) {
+    ZRegister zn = addr.GetVectorBase();
+    uint64_t imm = addr.GetImmediateOffset();
+    VIXL_ASSERT(num_regs == 1);
+    VIXL_ASSERT(zn.IsLaneSizeS() || zn.IsLaneSizeD());
+    VIXL_ASSERT(IsMultiple(imm, (1 << msize_in_bytes_log2)));
+    op = Rn(zn) | ImmUnsignedField<20, 16>(imm >> msize_in_bytes_log2);
+
+  } else if (addr.IsScalarPlusVector()) {
+    // We have to support several different addressing modes. Some instructions
+    // support a subset of these, but the SVEMemOperand encoding is consistent.
+    Register xn = addr.GetScalarBase();
+    ZRegister zm = addr.GetVectorOffset();
+    SVEOffsetModifier mod = addr.GetOffsetModifier();
+    Instr modifier_bit = 1 << (is_load ? 22 : 14);
+    Instr xs = (mod == SVE_SXTW) ? modifier_bit : 0;
+    VIXL_ASSERT(num_regs == 1);
+
+    if (mod == SVE_LSL) {
+      // 64-bit scaled offset:            [<Xn|SP>, <Zm>.D, LSL #<shift>]
+      VIXL_ASSERT(zm.IsLaneSizeD());
+      VIXL_ASSERT(addr.GetShiftAmount() == msize_in_bytes_log2);
+    } else if (mod == NO_SVE_OFFSET_MODIFIER) {
+      // 64-bit unscaled offset:          [<Xn|SP>, <Zm>.D]
+      VIXL_ASSERT(zm.IsLaneSizeD());
+      VIXL_ASSERT(addr.GetShiftAmount() == 0);
+    } else {
+      // 32-bit scaled offset:            [<Xn|SP>, <Zm>.S, <mod> #<shift>]
+      // 32-bit unscaled offset:          [<Xn|SP>, <Zm>.S, <mod>]
+      // 32-bit unpacked scaled offset:   [<Xn|SP>, <Zm>.D, <mod> #<shift>]
+      // 32-bit unpacked unscaled offset: [<Xn|SP>, <Zm>.D, <mod>]
+      VIXL_ASSERT(zm.IsLaneSizeS() || zm.IsLaneSizeD());
+      VIXL_ASSERT((mod == SVE_SXTW) || (mod == SVE_UXTW));
+      VIXL_ASSERT((addr.GetShiftAmount() == 0) ||
+                  (addr.GetShiftAmount() == msize_in_bytes_log2));
+    }
+
+    // The form itself is encoded in the instruction opcode.
+    op = RnSP(xn) | Rm(zm) | xs;
+  } else {
+    VIXL_UNIMPLEMENTED();
+  }
+
+  return op;
+}
+
+// SVEMemStore.
+
+void Assembler::SVESt1Helper(unsigned msize_in_bytes_log2,
+                             const ZRegister& zt,
+                             const PRegister& pg,
+                             const SVEMemOperand& addr) {
+  if (addr.IsScalarPlusScalar()) {
+    // Rm must not be xzr.
+    VIXL_ASSERT(!addr.GetScalarOffset().IsZero());
+  }
+
+  if (addr.IsScatterGather()) {
+    bool is_load = false;
+    bool is_signed = false;
+    bool is_ff = false;
+    SVEScatterGatherHelper(msize_in_bytes_log2,
+                           zt,
+                           pg,
+                           addr,
+                           is_load,
+                           is_signed,
+                           is_ff);
+    return;
+  }
+
+  Instr op;
+  if (addr.IsScalarPlusImmediate()) {
+    op = SVEContiguousStore_ScalarPlusImmFixed;
+  } else if (addr.IsScalarPlusScalar()) {
+    op = SVEContiguousStore_ScalarPlusScalarFixed;
+  } else {
+    VIXL_UNIMPLEMENTED();
+    op = 0xffffffff;
+  }
+  SVELdSt1Helper(msize_in_bytes_log2, zt, pg, addr, false, op);
+}
+
+void Assembler::SVESt234Helper(int num_regs,
+                               const ZRegister& zt1,
+                               const PRegister& pg,
+                               const SVEMemOperand& addr) {
+  if (addr.IsScalarPlusScalar()) {
+    // Rm must not be xzr.
+    VIXL_ASSERT(!addr.GetScalarOffset().IsZero());
+  }
+
+  Instr op;
+  if (addr.IsScalarPlusImmediate()) {
+    op = SVEStoreMultipleStructures_ScalarPlusImmFixed;
+  } else if (addr.IsScalarPlusScalar()) {
+    op = SVEStoreMultipleStructures_ScalarPlusScalarFixed;
+  } else {
+    // These instructions don't support any other addressing modes.
+    VIXL_ABORT();
+  }
+  SVELdSt234Helper(num_regs, zt1, pg, addr, op);
+}
+
+#define VIXL_DEFINE_ST1(MSZ, LANE_SIZE)                           \
+  void Assembler::st1##MSZ(const ZRegister& zt,                   \
+                           const PRegister& pg,                   \
+                           const SVEMemOperand& addr) {           \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));                       \
+    SVESt1Helper(k##LANE_SIZE##RegSizeInBytesLog2, zt, pg, addr); \
+  }
+#define VIXL_DEFINE_ST2(MSZ, LANE_SIZE)                 \
+  void Assembler::st2##MSZ(const ZRegister& zt1,        \
+                           const ZRegister& zt2,        \
+                           const PRegister& pg,         \
+                           const SVEMemOperand& addr) { \
+    USE(zt2);                                           \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));             \
+    VIXL_ASSERT(AreConsecutive(zt1, zt2));              \
+    VIXL_ASSERT(AreSameFormat(zt1, zt2));               \
+    VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE());           \
+    SVESt234Helper(2, zt1, pg, addr);                   \
+  }
+#define VIXL_DEFINE_ST3(MSZ, LANE_SIZE)                 \
+  void Assembler::st3##MSZ(const ZRegister& zt1,        \
+                           const ZRegister& zt2,        \
+                           const ZRegister& zt3,        \
+                           const PRegister& pg,         \
+                           const SVEMemOperand& addr) { \
+    USE(zt2, zt3);                                      \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));             \
+    VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3));         \
+    VIXL_ASSERT(AreSameFormat(zt1, zt2, zt3));          \
+    VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE());           \
+    SVESt234Helper(3, zt1, pg, addr);                   \
+  }
+#define VIXL_DEFINE_ST4(MSZ, LANE_SIZE)                 \
+  void Assembler::st4##MSZ(const ZRegister& zt1,        \
+                           const ZRegister& zt2,        \
+                           const ZRegister& zt3,        \
+                           const ZRegister& zt4,        \
+                           const PRegister& pg,         \
+                           const SVEMemOperand& addr) { \
+    USE(zt2, zt3, zt4);                                 \
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));             \
+    VIXL_ASSERT(AreConsecutive(zt1, zt2, zt3, zt4));    \
+    VIXL_ASSERT(AreSameFormat(zt1, zt2, zt3, zt4));     \
+    VIXL_ASSERT(zt1.IsLaneSize##LANE_SIZE());           \
+    SVESt234Helper(4, zt1, pg, addr);                   \
+  }
+
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_ST1)
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_ST2)
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_ST3)
+VIXL_SVE_LOAD_STORE_VARIANT_LIST(VIXL_DEFINE_ST4)
+
+void Assembler::stnt1b(const ZRegister& zt,
+                       const PRegister& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() && addr.IsMulVl()) ||
+              (addr.IsScalarPlusScalar() && addr.IsEquivalentToLSL(0)));
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        STNT1B_z_p_br_contiguous,
+                        STNT1B_z_p_bi_contiguous);
+}
+
+void Assembler::stnt1d(const ZRegister& zt,
+                       const PRegister& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() && addr.IsMulVl()) ||
+              (addr.IsScalarPlusScalar() && addr.IsEquivalentToLSL(3)));
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        STNT1D_z_p_br_contiguous,
+                        STNT1D_z_p_bi_contiguous);
+}
+
+void Assembler::stnt1h(const ZRegister& zt,
+                       const PRegister& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() && addr.IsMulVl()) ||
+              (addr.IsScalarPlusScalar() && addr.IsEquivalentToLSL(1)));
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        STNT1H_z_p_br_contiguous,
+                        STNT1H_z_p_bi_contiguous);
+}
+
+void Assembler::stnt1w(const ZRegister& zt,
+                       const PRegister& pg,
+                       const SVEMemOperand& addr) {
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() && addr.IsMulVl()) ||
+              (addr.IsScalarPlusScalar() && addr.IsEquivalentToLSL(2)));
+  SVELd1St1ScaImmHelper(zt,
+                        pg,
+                        addr,
+                        STNT1W_z_p_br_contiguous,
+                        STNT1W_z_p_bi_contiguous);
+}
+
+void Assembler::str(const CPURegister& rt, const SVEMemOperand& addr) {
+  // STR <Pt/Zt>, [<Xn|SP>{, #<imm>, MUL VL}]
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(rt.IsPRegister() || rt.IsZRegister());
+  VIXL_ASSERT(addr.IsPlainScalar() ||
+              (addr.IsScalarPlusImmediate() &&
+               (addr.GetOffsetModifier() == SVE_MUL_VL)));
+  int64_t imm9 = addr.GetImmediateOffset();
+  VIXL_ASSERT(IsInt9(imm9));
+  Instr imm9l = ExtractUnsignedBitfield32(2, 0, imm9) << 10;
+  Instr imm9h = ExtractUnsignedBitfield32(8, 3, imm9) << 16;
+
+  Instr op = STR_z_bi;
+  if (rt.IsPRegister()) {
+    op = STR_p_bi;
+  }
+  Emit(op | Rt(rt) | RnSP(addr.GetScalarBase()) | imm9h | imm9l);
+}
+
+// SVEMulIndex.
+
+void Assembler::sdot(const ZRegister& zda,
+                     const ZRegister& zn,
+                     const ZRegister& zm,
+                     int index) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+
+  Instr op = 0xffffffff;
+  switch (zda.GetLaneSizeInBits()) {
+    case kSRegSize:
+      VIXL_ASSERT(IsUint2(index));
+      op = SDOT_z_zzzi_s | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn);
+      break;
+    case kDRegSize:
+      VIXL_ASSERT(IsUint1(index));
+      op = SDOT_z_zzzi_d | Rx<19, 16>(zm) | (index << 20) | Rd(zda) | Rn(zn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  Emit(op);
+}
+
+void Assembler::udot(const ZRegister& zda,
+                     const ZRegister& zn,
+                     const ZRegister& zm,
+                     int index) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zda.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 4));
+  VIXL_ASSERT(AreSameLaneSize(zn, zm));
+
+  Instr op = 0xffffffff;
+  switch (zda.GetLaneSizeInBits()) {
+    case kSRegSize:
+      VIXL_ASSERT(IsUint2(index));
+      op = UDOT_z_zzzi_s | Rx<18, 16>(zm) | (index << 19) | Rd(zda) | Rn(zn);
+      break;
+    case kDRegSize:
+      VIXL_ASSERT(IsUint1(index));
+      op = UDOT_z_zzzi_d | Rx<19, 16>(zm) | (index << 20) | Rd(zda) | Rn(zn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  Emit(op);
+}
+
+// SVEPartitionBreak.
+
+void Assembler::brka(const PRegisterWithLaneSize& pd,
+                     const PRegister& pg,
+                     const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pg.IsMerging() || pg.IsZeroing());
+  VIXL_ASSERT(pd.IsLaneSizeB() && pn.IsLaneSizeB());
+
+  Instr m = pg.IsMerging() ? 0x00000010 : 0x00000000;
+  Emit(BRKA_p_p_p | Pd(pd) | Pg<13, 10>(pg) | m | Pn(pn));
+}
+
+void Assembler::brkas(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pd.IsLaneSizeB() && pn.IsLaneSizeB());
+
+  Emit(BRKAS_p_p_p_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn));
+}
+
+void Assembler::brkb(const PRegisterWithLaneSize& pd,
+                     const PRegister& pg,
+                     const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pg.IsMerging() || pg.IsZeroing());
+  VIXL_ASSERT(pd.IsLaneSizeB() && pn.IsLaneSizeB());
+
+  Instr m = pg.IsMerging() ? 0x00000010 : 0x00000000;
+  Emit(BRKB_p_p_p | Pd(pd) | Pg<13, 10>(pg) | m | Pn(pn));
+}
+
+void Assembler::brkbs(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pd.IsLaneSizeB() && pn.IsLaneSizeB());
+
+  Emit(BRKBS_p_p_p_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn));
+}
+
+void Assembler::brkn(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  USE(pm);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pd.IsLaneSizeB() && pn.IsLaneSizeB());
+  VIXL_ASSERT(pd.Is(pm));
+
+  Emit(BRKN_p_p_pp | Pd(pd) | Pg<13, 10>(pg) | Pn(pn));
+}
+
+void Assembler::brkns(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const PRegisterWithLaneSize& pn,
+                      const PRegisterWithLaneSize& pm) {
+  USE(pm);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pd.IsLaneSizeB() && pn.IsLaneSizeB());
+  VIXL_ASSERT(pd.Is(pm));
+
+  Emit(BRKNS_p_p_pp | Pd(pd) | Pg<13, 10>(pg) | Pn(pn));
+}
+
+// SVEPermutePredicate.
+
+void Assembler::punpkhi(const PRegisterWithLaneSize& pd,
+                        const PRegisterWithLaneSize& pn) {
+  // PUNPKHI <Pd>.H, <Pn>.B
+  //  0000 0101 0011 0001 0100 000. ...0 ....
+  //  H<16> = 1 | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pd.IsLaneSizeH());
+  VIXL_ASSERT(pn.IsLaneSizeB());
+
+  Emit(PUNPKHI_p_p | Pd(pd) | Pn(pn));
+}
+
+void Assembler::punpklo(const PRegisterWithLaneSize& pd,
+                        const PRegisterWithLaneSize& pn) {
+  // PUNPKLO <Pd>.H, <Pn>.B
+  //  0000 0101 0011 0000 0100 000. ...0 ....
+  //  H<16> = 0 | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pd.IsLaneSizeH());
+  VIXL_ASSERT(pn.IsLaneSizeB());
+
+  Emit(PUNPKLO_p_p | Pd(pd) | Pn(pn));
+}
+
+void Assembler::rev(const PRegisterWithLaneSize& pd,
+                    const PRegisterWithLaneSize& pn) {
+  // REV <Pd>.<T>, <Pn>.<T>
+  //  0000 0101 ..11 0100 0100 000. ...0 ....
+  //  size<23:22> | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, pn));
+
+  Emit(REV_p_p | SVESize(pd) | Pd(pd) | Rx<8, 5>(pn));
+}
+
+void Assembler::trn1(const PRegisterWithLaneSize& pd,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  // TRN1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
+  //  0000 0101 ..10 .... 0101 000. ...0 ....
+  //  size<23:22> | Pm<19:16> | opc<12:11> = 10 | H<10> = 0 | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, pn, pm));
+
+  Emit(TRN1_p_pp | SVESize(pd) | Pd(pd) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::trn2(const PRegisterWithLaneSize& pd,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  // TRN2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
+  //  0000 0101 ..10 .... 0101 010. ...0 ....
+  //  size<23:22> | Pm<19:16> | opc<12:11> = 10 | H<10> = 1 | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, pn, pm));
+
+  Emit(TRN2_p_pp | SVESize(pd) | Pd(pd) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::uzp1(const PRegisterWithLaneSize& pd,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  // UZP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
+  //  0000 0101 ..10 .... 0100 100. ...0 ....
+  //  size<23:22> | Pm<19:16> | opc<12:11> = 01 | H<10> = 0 | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, pn, pm));
+
+  Emit(UZP1_p_pp | SVESize(pd) | Pd(pd) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::uzp2(const PRegisterWithLaneSize& pd,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  // UZP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
+  //  0000 0101 ..10 .... 0100 110. ...0 ....
+  //  size<23:22> | Pm<19:16> | opc<12:11> = 01 | H<10> = 1 | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, pn, pm));
+
+  Emit(UZP2_p_pp | SVESize(pd) | Pd(pd) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::zip1(const PRegisterWithLaneSize& pd,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  // ZIP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
+  //  0000 0101 ..10 .... 0100 000. ...0 ....
+  //  size<23:22> | Pm<19:16> | opc<12:11> = 00 | H<10> = 0 | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, pn, pm));
+
+  Emit(ZIP1_p_pp | SVESize(pd) | Pd(pd) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::zip2(const PRegisterWithLaneSize& pd,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  // ZIP2 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
+  //  0000 0101 ..10 .... 0100 010. ...0 ....
+  //  size<23:22> | Pm<19:16> | opc<12:11> = 00 | H<10> = 1 | Pn<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(pd, pn, pm));
+
+  Emit(ZIP2_p_pp | SVESize(pd) | Pd(pd) | Pn(pn) | Pm(pm));
+}
+
+// SVEPermuteVectorExtract.
+
+void Assembler::ext(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm,
+                    unsigned offset) {
+  // EXT <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>
+  //  0000 0101 001. .... 000. .... .... ....
+  //  imm8h<20:16> | imm8l<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(IsUint8(offset));
+
+  int imm8h = ExtractUnsignedBitfield32(7, 3, offset);
+  int imm8l = ExtractUnsignedBitfield32(2, 0, offset);
+  Emit(EXT_z_zi_des | Rd(zd) | Rn(zm) | ImmUnsignedField<20, 16>(imm8h) |
+       ImmUnsignedField<12, 10>(imm8l));
+}
+
+// SVEPermuteVectorInterleaving.
+
+void Assembler::trn1(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // TRN1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0101 ..1. .... 0111 00.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 100 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(TRN1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::trn2(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // TRN2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0101 ..1. .... 0111 01.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 101 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(TRN2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::uzp1(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // UZP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0101 ..1. .... 0110 10.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 010 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(UZP1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::uzp2(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // UZP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0101 ..1. .... 0110 11.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 011 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(UZP2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::zip1(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // ZIP1 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0101 ..1. .... 0110 00.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 000 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(ZIP1_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::zip2(const ZRegister& zd,
+                     const ZRegister& zn,
+                     const ZRegister& zm) {
+  // ZIP2 <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
+  //  0000 0101 ..1. .... 0110 01.. .... ....
+  //  size<23:22> | Zm<20:16> | opc<12:10> = 001 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(ZIP2_z_zz | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+// SVEPermuteVectorPredicated.
+
+void Assembler::clasta(const Register& rd,
+                       const PRegister& pg,
+                       const Register& rn,
+                       const ZRegister& zm) {
+  // CLASTA <R><dn>, <Pg>, <R><dn>, <Zm>.<T>
+  //  0000 0101 ..11 0000 101. .... .... ....
+  //  size<23:22> | B<16> = 0 | Pg<12:10> | Zm<9:5> | Rdn<4:0>
+
+  USE(rn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(rd.Is(rn));
+
+  Emit(CLASTA_r_p_z | SVESize(zm) | Rd(rd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::clasta(const VRegister& vd,
+                       const PRegister& pg,
+                       const VRegister& vn,
+                       const ZRegister& zm) {
+  // CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
+  //  0000 0101 ..10 1010 100. .... .... ....
+  //  size<23:22> | B<16> = 0 | Pg<12:10> | Zm<9:5> | Vdn<4:0>
+
+  USE(vn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.Is(vn));
+  VIXL_ASSERT(vd.IsScalar());
+  VIXL_ASSERT(AreSameLaneSize(vd, zm));
+
+  Emit(CLASTA_v_p_z | SVESize(zm) | Rd(vd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::clasta(const ZRegister& zd,
+                       const PRegister& pg,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // CLASTA <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0101 ..10 1000 100. .... .... ....
+  //  size<23:22> | B<16> = 0 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(CLASTA_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::clastb(const Register& rd,
+                       const PRegister& pg,
+                       const Register& rn,
+                       const ZRegister& zm) {
+  // CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T>
+  //  0000 0101 ..11 0001 101. .... .... ....
+  //  size<23:22> | B<16> = 1 | Pg<12:10> | Zm<9:5> | Rdn<4:0>
+
+  USE(rn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(rd.Is(rn));
+
+  Emit(CLASTB_r_p_z | SVESize(zm) | Rd(rd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::clastb(const VRegister& vd,
+                       const PRegister& pg,
+                       const VRegister& vn,
+                       const ZRegister& zm) {
+  // CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
+  //  0000 0101 ..10 1011 100. .... .... ....
+  //  size<23:22> | B<16> = 1 | Pg<12:10> | Zm<9:5> | Vdn<4:0>
+
+  USE(vn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.Is(vn));
+  VIXL_ASSERT(vd.IsScalar());
+  VIXL_ASSERT(AreSameLaneSize(vd, zm));
+
+  Emit(CLASTB_v_p_z | SVESize(zm) | Rd(vd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::clastb(const ZRegister& zd,
+                       const PRegister& pg,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // CLASTB <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0101 ..10 1001 100. .... .... ....
+  //  size<23:22> | B<16> = 1 | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(CLASTB_z_p_zz | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+void Assembler::compact(const ZRegister& zd,
+                        const PRegister& pg,
+                        const ZRegister& zn) {
+  // COMPACT <Zd>.<T>, <Pg>, <Zn>.<T>
+  //  0000 0101 1.10 0001 100. .... .... ....
+  //  sz<22> | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT((zd.GetLaneSizeInBits() == kSRegSize) ||
+              (zd.GetLaneSizeInBits() == kDRegSize));
+
+  Instr sz = (zd.GetLaneSizeInBits() == kDRegSize) ? (1 << 22) : 0;
+  Emit(COMPACT_z_p_z | sz | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::cpy(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const Register& rn) {
+  // CPY <Zd>.<T>, <Pg>/M, <R><n|SP>
+  //  0000 0101 ..10 1000 101. .... .... ....
+  //  size<23:22> | Pg<12:10> | Rn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(static_cast<unsigned>(rn.GetSizeInBits()) >=
+              zd.GetLaneSizeInBits());
+
+  Emit(CPY_z_p_r | SVESize(zd) | Rd(zd) | PgLow8(pg) | RnSP(rn));
+}
+
+void Assembler::cpy(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const VRegister& vn) {
+  // CPY <Zd>.<T>, <Pg>/M, <V><n>
+  //  0000 0101 ..10 0000 100. .... .... ....
+  //  size<23:22> | Pg<12:10> | Vn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vn.IsScalar());
+  VIXL_ASSERT(static_cast<unsigned>(vn.GetSizeInBits()) ==
+              zd.GetLaneSizeInBits());
+
+  Emit(CPY_z_p_v | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(vn));
+}
+
+void Assembler::lasta(const Register& rd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  // LASTA <R><d>, <Pg>, <Zn>.<T>
+  //  0000 0101 ..10 0000 101. .... .... ....
+  //  size<23:22> | B<16> = 0 | Pg<12:10> | Zn<9:5> | Rd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LASTA_r_p_z | SVESize(zn) | Rd(rd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::lasta(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  // LASTA <V><d>, <Pg>, <Zn>.<T>
+  //  0000 0101 ..10 0010 100. .... .... ....
+  //  size<23:22> | B<16> = 0 | Pg<12:10> | Zn<9:5> | Vd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(LASTA_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::lastb(const Register& rd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  // LASTB <R><d>, <Pg>, <Zn>.<T>
+  //  0000 0101 ..10 0001 101. .... .... ....
+  //  size<23:22> | B<16> = 1 | Pg<12:10> | Zn<9:5> | Rd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(LASTB_r_p_z | SVESize(zn) | Rd(rd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::lastb(const VRegister& vd,
+                      const PRegister& pg,
+                      const ZRegister& zn) {
+  // LASTB <V><d>, <Pg>, <Zn>.<T>
+  //  0000 0101 ..10 0011 100. .... .... ....
+  //  size<23:22> | B<16> = 1 | Pg<12:10> | Zn<9:5> | Vd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vd.IsScalar());
+
+  Emit(LASTB_v_p_z | SVESize(zn) | Rd(vd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::rbit(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0101 ..10 0111 100. .... .... ....
+  //  size<23:22> | opc<17:16> = 11 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+
+  Emit(RBIT_z_p_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::revb(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // REVB <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0101 ..10 0100 100. .... .... ....
+  //  size<23:22> | opc<17:16> = 00 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.IsLaneSizeH() || zd.IsLaneSizeS() || zd.IsLaneSizeD());
+
+  Emit(REVB_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::revh(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // REVH <Zd>.<T>, <Pg>/M, <Zn>.<T>
+  //  0000 0101 ..10 0101 100. .... .... ....
+  //  size<23:22> | opc<17:16> = 01 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.IsLaneSizeS() || zd.IsLaneSizeD());
+
+  Emit(REVH_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::revw(const ZRegister& zd,
+                     const PRegisterM& pg,
+                     const ZRegister& zn) {
+  // REVW <Zd>.D, <Pg>/M, <Zn>.D
+  //  0000 0101 ..10 0110 100. .... .... ....
+  //  size<23:22> | opc<17:16> = 10 | Pg<12:10> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  VIXL_ASSERT(zd.IsLaneSizeD());
+
+  Emit(REVW_z_z | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zn));
+}
+
+void Assembler::splice(const ZRegister& zd,
+                       const PRegister& pg,
+                       const ZRegister& zn,
+                       const ZRegister& zm) {
+  // SPLICE <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>
+  //  0000 0101 ..10 1100 100. .... .... ....
+  //  size<23:22> | Pg<12:10> | Zm<9:5> | Zdn<4:0>
+
+  USE(zn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.Is(zn));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(SPLICE_z_p_zz_des | SVESize(zd) | Rd(zd) | PgLow8(pg) | Rn(zm));
+}
+
+// SVEPermuteVectorUnpredicated.
+
+void Assembler::dup(const ZRegister& zd, const Register& xn) {
+  // DUP <Zd>.<T>, <R><n|SP>
+  //  0000 0101 ..10 0000 0011 10.. .... ....
+  //  size<23:22> | Rn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(DUP_z_r | SVESize(zd) | Rd(zd) | RnSP(xn));
+}
+
+void Assembler::dup(const ZRegister& zd, const ZRegister& zn, unsigned index) {
+  // DUP <Zd>.<T>, <Zn>.<T>[<imm>]
+  //  0000 0101 ..1. .... 0010 00.. .... ....
+  //  imm2<23:22> | tsz<20:16> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(zd, zn));
+  VIXL_ASSERT((index * zd.GetLaneSizeInBits()) < 512);
+  int n = zd.GetLaneSizeInBytesLog2();
+  unsigned imm_7 = (index << (n + 1)) | (1 << n);
+  VIXL_ASSERT(IsUint7(imm_7));
+  unsigned imm_2 = ExtractUnsignedBitfield32(6, 5, imm_7);
+  unsigned tsz_5 = ExtractUnsignedBitfield32(4, 0, imm_7);
+
+  Emit(DUP_z_zi | ImmUnsignedField<23, 22>(imm_2) |
+       ImmUnsignedField<20, 16>(tsz_5) | Rd(zd) | Rn(zn));
+}
+
+void Assembler::insr(const ZRegister& zdn, const Register& rm) {
+  // INSR <Zdn>.<T>, <R><m>
+  //  0000 0101 ..10 0100 0011 10.. .... ....
+  //  size<23:22> | Rm<9:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(INSR_z_r | SVESize(zdn) | Rd(zdn) | Rn(rm));
+}
+
+void Assembler::insr(const ZRegister& zdn, const VRegister& vm) {
+  // INSR <Zdn>.<T>, <V><m>
+  //  0000 0101 ..11 0100 0011 10.. .... ....
+  //  size<23:22> | Vm<9:5> | Zdn<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(vm.IsScalar());
+
+  Emit(INSR_z_v | SVESize(zdn) | Rd(zdn) | Rn(vm));
+}
+
+void Assembler::rev(const ZRegister& zd, const ZRegister& zn) {
+  // REV <Zd>.<T>, <Zn>.<T>
+  //  0000 0101 ..11 1000 0011 10.. .... ....
+  //  size<23:22> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(zd, zn));
+
+  Emit(REV_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
+}
+
+void Assembler::sunpkhi(const ZRegister& zd, const ZRegister& zn) {
+  // SUNPKHI <Zd>.<T>, <Zn>.<Tb>
+  //  0000 0101 ..11 0001 0011 10.. .... ....
+  //  size<23:22> | U<17> = 0 | H<16> = 1 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
+  VIXL_ASSERT(!zd.IsLaneSizeB());
+
+  Emit(SUNPKHI_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
+}
+
+void Assembler::sunpklo(const ZRegister& zd, const ZRegister& zn) {
+  // SUNPKLO <Zd>.<T>, <Zn>.<Tb>
+  //  0000 0101 ..11 0000 0011 10.. .... ....
+  //  size<23:22> | U<17> = 0 | H<16> = 0 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
+  VIXL_ASSERT(!zd.IsLaneSizeB());
+
+  Emit(SUNPKLO_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
+}
+
+void Assembler::tbl(const ZRegister& zd,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  // TBL <Zd>.<T>, { <Zn>.<T> }, <Zm>.<T>
+  //  0000 0101 ..1. .... 0011 00.. .... ....
+  //  size<23:22> | Zm<20:16> | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(zd, zn, zm));
+
+  Emit(TBL_z_zz_1 | SVESize(zd) | Rd(zd) | Rn(zn) | Rm(zm));
+}
+
+void Assembler::uunpkhi(const ZRegister& zd, const ZRegister& zn) {
+  // UUNPKHI <Zd>.<T>, <Zn>.<Tb>
+  //  0000 0101 ..11 0011 0011 10.. .... ....
+  //  size<23:22> | U<17> = 1 | H<16> = 1 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
+  VIXL_ASSERT(!zd.IsLaneSizeB());
+
+  Emit(UUNPKHI_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
+}
+
+void Assembler::uunpklo(const ZRegister& zd, const ZRegister& zn) {
+  // UUNPKLO <Zd>.<T>, <Zn>.<Tb>
+  //  0000 0101 ..11 0010 0011 10.. .... ....
+  //  size<23:22> | U<17> = 1 | H<16> = 0 | Zn<9:5> | Zd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(zd.GetLaneSizeInBytes() == (zn.GetLaneSizeInBytes() * 2));
+  VIXL_ASSERT(!zd.IsLaneSizeB());
+
+  Emit(UUNPKLO_z_z | SVESize(zd) | Rd(zd) | Rn(zn));
+}
+
+// SVEPredicateCount.
+
+void Assembler::cntp(const Register& xd,
+                     const PRegister& pg,
+                     const PRegisterWithLaneSize& pn) {
+  // CNTP <Xd>, <Pg>, <Pn>.<T>
+  //  0010 0101 ..10 0000 10.. ..0. .... ....
+  //  size<23:22> | opc<18:16> = 000 | Pg<13:10> | o2<9> = 0 | Pn<8:5> | Rd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(xd.IsX());
+  VIXL_ASSERT(pg.IsUnqualified());
+  if (pg.HasLaneSize()) VIXL_ASSERT(AreSameFormat(pg, pn));
+
+  Emit(CNTP_r_p_p | SVESize(pn) | Rd(xd) | Pg<13, 10>(pg) | Pn(pn));
+}
+
+// SVEPredicateLogicalOp.
+void Assembler::and_(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(AND_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::ands(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(ANDS_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::bic(const PRegisterWithLaneSize& pd,
+                    const PRegisterZ& pg,
+                    const PRegisterWithLaneSize& pn,
+                    const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(BIC_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::bics(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(BICS_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::eor(const PRegisterWithLaneSize& pd,
+                    const PRegisterZ& pg,
+                    const PRegisterWithLaneSize& pn,
+                    const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(EOR_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::eors(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(EORS_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::nand(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(NAND_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::nands(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const PRegisterWithLaneSize& pn,
+                      const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(NANDS_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::nor(const PRegisterWithLaneSize& pd,
+                    const PRegisterZ& pg,
+                    const PRegisterWithLaneSize& pn,
+                    const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(NOR_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::nors(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(NORS_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::orn(const PRegisterWithLaneSize& pd,
+                    const PRegisterZ& pg,
+                    const PRegisterWithLaneSize& pn,
+                    const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(ORN_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::orns(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(ORNS_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::orr(const PRegisterWithLaneSize& pd,
+                    const PRegisterZ& pg,
+                    const PRegisterWithLaneSize& pn,
+                    const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(ORR_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::orrs(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn,
+                     const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameFormat(pd, pn, pm));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  Emit(ORRS_p_p_pp_z | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::sel(const PRegisterWithLaneSize& pd,
+                    const PRegister& pg,
+                    const PRegisterWithLaneSize& pn,
+                    const PRegisterWithLaneSize& pm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  Emit(SEL_p_p_pp | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+// SVEPredicateMisc.
+
+void Assembler::pfalse(const PRegisterWithLaneSize& pd) {
+  // PFALSE <Pd>.B
+  //  0010 0101 0001 1000 1110 0100 0000 ....
+  //  op<23> = 0 | S<22> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  // Ignore the lane size, since it makes no difference to the operation.
+
+  Emit(PFALSE_p | Pd(pd));
+}
+
+void Assembler::pfirst(const PRegisterWithLaneSize& pd,
+                       const PRegister& pg,
+                       const PRegisterWithLaneSize& pn) {
+  // PFIRST <Pdn>.B, <Pg>, <Pdn>.B
+  //  0010 0101 0101 1000 1100 000. ...0 ....
+  //  op<23> = 0 | S<22> = 1 | Pg<8:5> | Pdn<3:0>
+
+  USE(pn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pd.Is(pn));
+  VIXL_ASSERT(pd.IsLaneSizeB());
+
+  Emit(PFIRST_p_p_p | Pd(pd) | Pg<8, 5>(pg));
+}
+
+void Assembler::pnext(const PRegisterWithLaneSize& pd,
+                      const PRegister& pg,
+                      const PRegisterWithLaneSize& pn) {
+  // PNEXT <Pdn>.<T>, <Pg>, <Pdn>.<T>
+  //  0010 0101 ..01 1001 1100 010. ...0 ....
+  //  size<23:22> | Pg<8:5> | Pdn<3:0>
+
+  USE(pn);
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pd.Is(pn));
+
+  Emit(PNEXT_p_p_p | SVESize(pd) | Pd(pd) | Pg<8, 5>(pg));
+}
+
+void Assembler::ptest(const PRegister& pg, const PRegisterWithLaneSize& pn) {
+  // PTEST <Pg>, <Pn>.B
+  //  0010 0101 0101 0000 11.. ..0. ...0 0000
+  //  op<23> = 0 | S<22> = 1 | Pg<13:10> | Pn<8:5> | opc2<3:0> = 0000
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(pn.IsLaneSizeB());
+
+  Emit(PTEST_p_p | Pg<13, 10>(pg) | Rx<8, 5>(pn));
+}
+
+void Assembler::ptrue(const PRegisterWithLaneSize& pd, int pattern) {
+  // PTRUE <Pd>.<T>{, <pattern>}
+  //  0010 0101 ..01 1000 1110 00.. ...0 ....
+  //  size<23:22> | S<16> = 0 | pattern<9:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(PTRUE_p_s | SVESize(pd) | Pd(pd) | ImmSVEPredicateConstraint(pattern));
+}
+
+void Assembler::ptrues(const PRegisterWithLaneSize& pd, int pattern) {
+  // PTRUES <Pd>.<T>{, <pattern>}
+  //  0010 0101 ..01 1001 1110 00.. ...0 ....
+  //  size<23:22> | S<16> = 1 | pattern<9:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(PTRUES_p_s | SVESize(pd) | Pd(pd) | ImmSVEPredicateConstraint(pattern));
+}
+
+void Assembler::rdffr(const PRegisterWithLaneSize& pd) {
+  // RDFFR <Pd>.B
+  //  0010 0101 0001 1001 1111 0000 0000 ....
+  //  op<23> = 0 | S<22> = 0 | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(RDFFR_p_f | Pd(pd));
+}
+
+void Assembler::rdffr(const PRegisterWithLaneSize& pd, const PRegisterZ& pg) {
+  // RDFFR <Pd>.B, <Pg>/Z
+  //  0010 0101 0001 1000 1111 000. ...0 ....
+  //  op<23> = 0 | S<22> = 0 | Pg<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(RDFFR_p_p_f | Pd(pd) | Pg<8, 5>(pg));
+}
+
+void Assembler::rdffrs(const PRegisterWithLaneSize& pd, const PRegisterZ& pg) {
+  // RDFFRS <Pd>.B, <Pg>/Z
+  //  0010 0101 0101 1000 1111 000. ...0 ....
+  //  op<23> = 0 | S<22> = 1 | Pg<8:5> | Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(RDFFRS_p_p_f | Pd(pd) | Pg<8, 5>(pg));
+}
+
+// SVEPropagateBreak.
+
+void Assembler::brkpa(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const PRegisterWithLaneSize& pn,
+                      const PRegisterWithLaneSize& pm) {
+  // BRKPA <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
+  //  0010 0101 0000 .... 11.. ..0. ...0 ....
+  //  op<23> = 0 | S<22> = 0 | Pm<19:16> | Pg<13:10> | Pn<8:5> | B<4> = 0 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(BRKPA_p_p_pp | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::brkpas(const PRegisterWithLaneSize& pd,
+                       const PRegisterZ& pg,
+                       const PRegisterWithLaneSize& pn,
+                       const PRegisterWithLaneSize& pm) {
+  // BRKPAS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
+  //  0010 0101 0100 .... 11.. ..0. ...0 ....
+  //  op<23> = 0 | S<22> = 1 | Pm<19:16> | Pg<13:10> | Pn<8:5> | B<4> = 0 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(BRKPAS_p_p_pp | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::brkpb(const PRegisterWithLaneSize& pd,
+                      const PRegisterZ& pg,
+                      const PRegisterWithLaneSize& pn,
+                      const PRegisterWithLaneSize& pm) {
+  // BRKPB <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
+  //  0010 0101 0000 .... 11.. ..0. ...1 ....
+  //  op<23> = 0 | S<22> = 0 | Pm<19:16> | Pg<13:10> | Pn<8:5> | B<4> = 1 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(BRKPB_p_p_pp | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+void Assembler::brkpbs(const PRegisterWithLaneSize& pd,
+                       const PRegisterZ& pg,
+                       const PRegisterWithLaneSize& pn,
+                       const PRegisterWithLaneSize& pm) {
+  // BRKPBS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
+  //  0010 0101 0100 .... 11.. ..0. ...1 ....
+  //  op<23> = 0 | S<22> = 1 | Pm<19:16> | Pg<13:10> | Pn<8:5> | B<4> = 1 |
+  //  Pd<3:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(BRKPBS_p_p_pp | Pd(pd) | Pg<13, 10>(pg) | Pn(pn) | Pm(pm));
+}
+
+// SVEStackFrameAdjustment.
+
+void Assembler::addpl(const Register& xd, const Register& xn, int imm6) {
+  // ADDPL <Xd|SP>, <Xn|SP>, #<imm>
+  //  0000 0100 011. .... 0101 0... .... ....
+  //  op<22> = 1 | Rn<20:16> | imm6<10:5> | Rd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(xd.IsX());
+  VIXL_ASSERT(xn.IsX());
+
+  Emit(ADDPL_r_ri | RdSP(xd) | RmSP(xn) | ImmField<10, 5>(imm6));
+}
+
+void Assembler::addvl(const Register& xd, const Register& xn, int imm6) {
+  // ADDVL <Xd|SP>, <Xn|SP>, #<imm>
+  //  0000 0100 001. .... 0101 0... .... ....
+  //  op<22> = 0 | Rn<20:16> | imm6<10:5> | Rd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(xd.IsX());
+  VIXL_ASSERT(xn.IsX());
+
+  Emit(ADDVL_r_ri | RdSP(xd) | RmSP(xn) | ImmField<10, 5>(imm6));
+}
+
+// SVEStackFrameSize.
+
+void Assembler::rdvl(const Register& xd, int imm6) {
+  // RDVL <Xd>, #<imm>
+  //  0000 0100 1011 1111 0101 0... .... ....
+  //  op<22> = 0 | opc2<20:16> = 11111 | imm6<10:5> | Rd<4:0>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(xd.IsX());
+
+  Emit(RDVL_r_i | Rd(xd) | ImmField<10, 5>(imm6));
+}
+
+// SVEVectorSelect.
+
+void Assembler::sel(const ZRegister& zd,
+                    const PRegister& pg,
+                    const ZRegister& zn,
+                    const ZRegister& zm) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+
+  Emit(SEL_z_p_zz | SVESize(zd) | Rd(zd) | Pg<13, 10>(pg) | Rn(zn) | Rm(zm));
+}
+
+// SVEWriteFFR.
+
+void Assembler::setffr() {
+  // SETFFR
+  //  0010 0101 0010 1100 1001 0000 0000 0000
+  //  opc<23:22> = 00
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(SETFFR_f);
+}
+
+void Assembler::wrffr(const PRegisterWithLaneSize& pn) {
+  // WRFFR <Pn>.B
+  //  0010 0101 0010 1000 1001 000. ...0 0000
+  //  opc<23:22> = 00 | Pn<8:5>
+
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+
+  Emit(WRFFR_f_p | Rx<8, 5>(pn));
+}
+
+// Aliases.
+
+void Assembler::bic(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+  and_(zd, zn, ~imm);
+}
+
+void Assembler::eon(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+  eor(zd, zn, ~imm);
+}
+
+void Assembler::orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+  orr(zd, zn, ~imm);
+}
+
+
+void Assembler::fmov(const ZRegister& zd, const PRegisterM& pg, double imm) {
+  if (IsPositiveZero(imm)) {
+    cpy(zd, pg, 0);
+  } else {
+    fcpy(zd, pg, imm);
+  }
+}
+
+void Assembler::fmov(const ZRegister& zd, double imm) {
+  if (IsPositiveZero(imm)) {
+    dup(zd, imm);
+  } else {
+    fdup(zd, imm);
+  }
+}
+
+void Assembler::mov(const PRegister& pd, const PRegister& pn) {
+  // If the inputs carry a lane size, they must match.
+  VIXL_ASSERT((!pd.HasLaneSize() && !pn.HasLaneSize()) ||
+              AreSameLaneSize(pd, pn));
+  orr(pd.VnB(), pn.Zeroing(), pn.VnB(), pn.VnB());
+}
+
+void Assembler::mov(const PRegisterWithLaneSize& pd,
+                    const PRegisterM& pg,
+                    const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  sel(pd, pg, pn, pd);
+}
+
+void Assembler::mov(const PRegisterWithLaneSize& pd,
+                    const PRegisterZ& pg,
+                    const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  and_(pd, pg, pn, pn);
+}
+
+void Assembler::mov(const ZRegister& zd,
+                    const PRegister& pg,
+                    int imm8,
+                    int shift) {
+  VIXL_ASSERT(pg.IsMerging() || pg.IsZeroing());
+  cpy(zd, pg, imm8, shift);
+}
+
+void Assembler::mov(const ZRegister& zd, const Register& xn) { dup(zd, xn); }
+
+void Assembler::mov(const ZRegister& zd, const VRegister& vn) {
+  VIXL_ASSERT(vn.IsScalar());
+  VIXL_ASSERT(AreSameLaneSize(zd, vn));
+  dup(zd, vn.Z().WithSameLaneSizeAs(vn), 0);
+}
+
+void Assembler::mov(const ZRegister& zd, const ZRegister& zn) {
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  orr(zd.VnD(), zn.VnD(), zn.VnD());
+}
+
+void Assembler::mov(const ZRegister& zd, const ZRegister& zn, unsigned index) {
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  dup(zd, zn, index);
+}
+
+void Assembler::mov(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const Register& rn) {
+  cpy(zd, pg, rn);
+}
+
+void Assembler::mov(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const VRegister& vn) {
+  VIXL_ASSERT(vn.IsScalar());
+  VIXL_ASSERT(AreSameLaneSize(zd, vn));
+  cpy(zd, pg, vn);
+}
+
+void Assembler::mov(const ZRegister& zd,
+                    const PRegisterM& pg,
+                    const ZRegister& zn) {
+  VIXL_ASSERT(AreSameLaneSize(zd, zn));
+  sel(zd, pg, zn, zd);
+}
+
+void Assembler::mov(const ZRegister& zd, uint64_t imm) {
+  // Mov is an alias of dupm for certain values of imm. Whilst this matters in
+  // the disassembler, for the assembler, we don't distinguish between the
+  // two mnemonics, and simply call dupm.
+  dupm(zd, imm);
+}
+
+void Assembler::mov(const ZRegister& zd, int imm8, int shift) {
+  dup(zd, imm8, shift);
+}
+
+void Assembler::movs(const PRegister& pd, const PRegister& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  orrs(pd.VnB(), pn.Zeroing(), pn.VnB(), pn.VnB());
+}
+
+void Assembler::movs(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  ands(pd, pg, pn, pn);
+}
+
+void Assembler::not_(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  eor(pd, pg, pn, pg.VnB());
+}
+
+void Assembler::nots(const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+  eors(pd, pg, pn, pg.VnB());
+}
+
+}  // namespace aarch64
+}  // namespace vixl
diff --git a/src/aarch64/constants-aarch64.h b/src/aarch64/constants-aarch64.h
index 36f5568d..d17c8894 100644
--- a/src/aarch64/constants-aarch64.h
+++ b/src/aarch64/constants-aarch64.h
@@ -34,6 +34,8 @@ namespace aarch64 {
 
 const unsigned kNumberOfRegisters = 32;
 const unsigned kNumberOfVRegisters = 32;
+const unsigned kNumberOfZRegisters = kNumberOfVRegisters;
+const unsigned kNumberOfPRegisters = 16;
 // Callee saved registers are x21-x30(lr).
 const int kNumberOfCalleeSavedRegisters = 10;
 const int kFirstCalleeSavedRegisterIndex = 21;
@@ -41,14 +43,34 @@ const int kFirstCalleeSavedRegisterIndex = 21;
 // still caller-saved.
 const int kNumberOfCalleeSavedFPRegisters = 8;
 const int kFirstCalleeSavedFPRegisterIndex = 8;
+// All predicated instructions accept at least p0-p7 as the governing predicate.
+const unsigned kNumberOfGoverningPRegisters = 8;
 
 // clang-format off
+#define AARCH64_P_REGISTER_CODE_LIST(R)                                        \
+  R(0)  R(1)  R(2)  R(3)  R(4)  R(5)  R(6)  R(7)                               \
+  R(8)  R(9)  R(10) R(11) R(12) R(13) R(14) R(15)
+
 #define AARCH64_REGISTER_CODE_LIST(R)                                          \
   R(0)  R(1)  R(2)  R(3)  R(4)  R(5)  R(6)  R(7)                               \
   R(8)  R(9)  R(10) R(11) R(12) R(13) R(14) R(15)                              \
   R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23)                              \
   R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31)
 
+// SVE loads and stores use "w" instead of "s" for word-sized accesses, so the
+// mapping from the load/store variant to constants like k*RegSize is irregular.
+#define VIXL_SVE_LOAD_STORE_VARIANT_LIST(V) \
+  V(b, B)                            \
+  V(h, H)                            \
+  V(w, S)                            \
+  V(d, D)
+
+// Sign-extending loads don't have double-word variants.
+#define VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST(V) \
+  V(b, B)                            \
+  V(h, H)                            \
+  V(w, S)
+
 #define INSTRUCTION_FIELDS_LIST(V_)                                          \
 /* Register fields */                                                        \
 V_(Rd, 4, 0, ExtractBits)         /* Destination register.                */ \
@@ -59,6 +81,11 @@ V_(Ra, 14, 10, ExtractBits)       /* Third source register.               */ \
 V_(Rt, 4, 0, ExtractBits)         /* Load/store register.                 */ \
 V_(Rt2, 14, 10, ExtractBits)      /* Load/store second register.          */ \
 V_(Rs, 20, 16, ExtractBits)       /* Exclusive access status.             */ \
+V_(Pt, 3, 0, ExtractBits)         /* Load/store register (p0-p7).         */ \
+V_(Pd, 3, 0, ExtractBits)         /* SVE destination predicate register.  */ \
+V_(Pn, 8, 5, ExtractBits)         /* SVE first source predicate register. */ \
+V_(Pm, 19, 16, ExtractBits)       /* SVE second source predicate register.*/ \
+V_(PgLow8, 12, 10, ExtractBits)   /* Governing predicate (p0-p7).         */ \
                                                                              \
 /* Common bits */                                                            \
 V_(SixtyFourBits, 31, 31, ExtractBits)                                       \
@@ -74,7 +101,7 @@ V_(ImmDPShift, 15, 10, ExtractBits)                                          \
                                                                              \
 /* Add/subtract immediate */                                                 \
 V_(ImmAddSub, 21, 10, ExtractBits)                                           \
-V_(ShiftAddSub, 23, 22, ExtractBits)                                         \
+V_(ImmAddSubShift, 22, 22, ExtractBits)                                      \
                                                                              \
 /* Add/substract extend */                                                   \
 V_(ImmExtendShift, 12, 10, ExtractBits)                                      \
@@ -177,7 +204,23 @@ V_(NEONCmode, 15, 12, ExtractBits)                                           \
 /* NEON Shift Immediate fields */                                            \
 V_(ImmNEONImmhImmb, 22, 16, ExtractBits)                                     \
 V_(ImmNEONImmh, 22, 19, ExtractBits)                                         \
-V_(ImmNEONImmb, 18, 16, ExtractBits)
+V_(ImmNEONImmb, 18, 16, ExtractBits)                                         \
+                                                                             \
+/* SVE generic fields */                                                     \
+V_(SVESize, 23, 22, ExtractBits)                                             \
+V_(ImmSVEVLScale, 10, 5, ExtractSignedBits)                                  \
+V_(ImmSVEIntWideSigned, 12, 5, ExtractSignedBits)                            \
+V_(ImmSVEIntWideUnsigned, 12, 5, ExtractBits)                                \
+V_(ImmSVEPredicateConstraint, 9, 5, ExtractBits)                             \
+                                                                             \
+/* SVE Bitwise Immediate bitfield */                                         \
+V_(SVEBitN, 17, 17, ExtractBits)                                             \
+V_(SVEImmRotate, 16, 11, ExtractBits)                                        \
+V_(SVEImmSetBits, 10, 5, ExtractBits)                                        \
+                                                                             \
+V_(SVEImmPrefetchOperation, 3, 0, ExtractBits)                               \
+V_(SVEPrefetchHint, 3, 3, ExtractBits)
+
 // clang-format on
 
 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \
@@ -235,7 +278,22 @@ enum Condition {
 
   // Aliases.
   hs = cs,  // C set            Unsigned higher or same.
-  lo = cc   // C clear          Unsigned lower.
+  lo = cc,  // C clear          Unsigned lower.
+
+  // Floating-point additional condition code.
+  uo,       // Unordered comparison.
+
+  // SVE predicate condition aliases.
+  sve_none  = eq,  // No active elements were true.
+  sve_any   = ne,  // An active element was true.
+  sve_nlast = cs,  // The last element was not true.
+  sve_last  = cc,  // The last element was true.
+  sve_first = mi,  // The first element was true.
+  sve_nfrst = pl,  // The first element was not true.
+  sve_pmore = hi,  // An active element was true but not the last element.
+  sve_plast = ls,  // The last active element was true or no active elements were true.
+  sve_tcont = ge,  // CTERM termination condition not deleted.
+  sve_tstop = lt   // CTERM termination condition deleted.
 };
 
 inline Condition InvertCondition(Condition cond) {
@@ -279,7 +337,12 @@ enum StatusFlags {
   FPEqualFlag       = ZCFlag,
   FPLessThanFlag    = NFlag,
   FPGreaterThanFlag = CFlag,
-  FPUnorderedFlag   = CVFlag
+  FPUnorderedFlag   = CVFlag,
+
+  // SVE condition flags.
+  SVEFirstFlag   = NFlag,
+  SVENoneFlag    = ZFlag,
+  SVENotLastFlag = CFlag
 };
 
 enum Shift {
@@ -303,6 +366,17 @@ enum Extend {
   SXTX      = 7
 };
 
+enum SVEOffsetModifier {
+  NO_SVE_OFFSET_MODIFIER,
+  // Multiply (each element of) the offset by either the vector or predicate
+  // length, according to the context.
+  SVE_MUL_VL,
+  // Shift or extend modifiers (as in `Shift` or `Extend`).
+  SVE_LSL,
+  SVE_UXTW,
+  SVE_SXTW
+};
+
 enum SystemHint {
   NOP    = 0,
   YIELD  = 1,
@@ -353,6 +427,9 @@ enum PrefetchOperation {
   PLDL3KEEP = 0x04,
   PLDL3STRM = 0x05,
 
+  PrfUnallocated06 = 0x06,
+  PrfUnallocated07 = 0x07,
+
   PLIL1KEEP = 0x08,
   PLIL1STRM = 0x09,
   PLIL2KEEP = 0x0a,
@@ -360,14 +437,34 @@ enum PrefetchOperation {
   PLIL3KEEP = 0x0c,
   PLIL3STRM = 0x0d,
 
+  PrfUnallocated0e = 0x0e,
+  PrfUnallocated0f = 0x0f,
+
   PSTL1KEEP = 0x10,
   PSTL1STRM = 0x11,
   PSTL2KEEP = 0x12,
   PSTL2STRM = 0x13,
   PSTL3KEEP = 0x14,
-  PSTL3STRM = 0x15
+  PSTL3STRM = 0x15,
+
+  PrfUnallocated16 = 0x16,
+  PrfUnallocated17 = 0x17,
+  PrfUnallocated18 = 0x18,
+  PrfUnallocated19 = 0x19,
+  PrfUnallocated1a = 0x1a,
+  PrfUnallocated1b = 0x1b,
+  PrfUnallocated1c = 0x1c,
+  PrfUnallocated1d = 0x1d,
+  PrfUnallocated1e = 0x1e,
+  PrfUnallocated1f = 0x1f,
 };
 
+constexpr bool IsNamedPrefetchOperation(int op) {
+  return ((op >= PLDL1KEEP) && (op <= PLDL3STRM)) ||
+      ((op >= PLIL1KEEP) && (op <= PLIL3STRM)) ||
+      ((op >= PSTL1KEEP) && (op <= PSTL3STRM));
+}
+
 enum BType {
   // Set when executing any instruction on a guarded page, except those cases
   // listed below.
@@ -429,6 +526,36 @@ enum DataCacheOp {
   ZVA = CacheOpEncoder<3, 7, 4, 1>::value
 };
 
+// Some SVE instructions support a predicate constraint pattern. This is
+// interpreted as a VL-dependent value, and is typically used to initialise
+// predicates, or to otherwise limit the number of processed elements.
+enum SVEPredicateConstraint {
+  // Select 2^N elements, for the largest possible N.
+  SVE_POW2 = 0x0,
+  // Each VL<N> selects exactly N elements if possible, or zero if N is greater
+  // than the number of elements. Note that the encoding values for VL<N> are
+  // not linearly related to N.
+  SVE_VL1 = 0x1,
+  SVE_VL2 = 0x2,
+  SVE_VL3 = 0x3,
+  SVE_VL4 = 0x4,
+  SVE_VL5 = 0x5,
+  SVE_VL6 = 0x6,
+  SVE_VL7 = 0x7,
+  SVE_VL8 = 0x8,
+  SVE_VL16 = 0x9,
+  SVE_VL32 = 0xa,
+  SVE_VL64 = 0xb,
+  SVE_VL128 = 0xc,
+  SVE_VL256 = 0xd,
+  // Each MUL<N> selects the largest multiple of N elements that the vector
+  // length supports. Note that for D-sized lanes, this can be zero.
+  SVE_MUL4 = 0x1d,
+  SVE_MUL3 = 0x1e,
+  // Select all elements.
+  SVE_ALL = 0x1f
+};
+
 // Instruction enumerations.
 //
 // These are the masks that define a class of instructions, and the list of
@@ -503,6 +630,14 @@ enum NEONScalarFormatField {
   NEON_D                    = 0x00C00000
 };
 
+enum SVESizeField {
+  SVESizeFieldMask = 0x00C00000,
+  SVE_B            = 0x00000000,
+  SVE_H            = 0x00400000,
+  SVE_S            = 0x00800000,
+  SVE_D            = 0x00C00000
+};
+
 // PC relative addressing.
 enum PCRelAddressingOp {
   PCRelAddressingFixed = 0x10000000,
@@ -531,8 +666,8 @@ enum AddSubOp {
 
 enum AddSubImmediateOp {
   AddSubImmediateFixed = 0x11000000,
-  AddSubImmediateFMask = 0x1F000000,
-  AddSubImmediateMask  = 0xFF000000,
+  AddSubImmediateFMask = 0x1F800000,
+  AddSubImmediateMask  = 0xFF800000,
   #define ADD_SUB_IMMEDIATE(A)           \
   A##_w_imm = AddSubImmediateFixed | A,  \
   A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits
@@ -2660,11 +2795,1626 @@ enum NEONScalarShiftImmediateOp {
   NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm
 };
 
+enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp {
+  SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed = 0x84A00000,
+  SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000,
+  SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000,
+  LD1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed,
+  LDFF1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00002000,
+  LD1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
+  LDFF1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
+};
+
+enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp {
+  SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed = 0x85200000,
+  SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000,
+  SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000,
+  LD1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
+  LDFF1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
+};
+
+enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp {
+  SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed = 0x84000000,
+  SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE208000,
+  SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask = 0xFFA0E000,
+  LD1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed,
+  LDFF1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00002000,
+  LD1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00004000,
+  LDFF1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00006000,
+  LD1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000,
+  LDFF1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00802000,
+  LD1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00804000,
+  LDFF1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00806000,
+  LD1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01004000,
+  LDFF1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01006000
+};
+
+enum SVE32BitGatherLoad_VectorPlusImmOp {
+  SVE32BitGatherLoad_VectorPlusImmFixed = 0x84208000,
+  SVE32BitGatherLoad_VectorPlusImmFMask = 0xFE608000,
+  SVE32BitGatherLoad_VectorPlusImmMask = 0xFFE0E000,
+  LD1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed,
+  LDFF1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00002000,
+  LD1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00004000,
+  LDFF1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00006000,
+  LD1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00800000,
+  LDFF1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00802000,
+  LD1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00804000,
+  LDFF1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00806000,
+  LD1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01004000,
+  LDFF1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01006000
+};
+
+enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp {
+  SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed = 0x84200000,
+  SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08010,
+  SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E010,
+  PRFB_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed,
+  PRFH_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00002000,
+  PRFW_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00004000,
+  PRFD_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00006000
+};
+
+enum SVE32BitGatherPrefetch_VectorPlusImmOp {
+  SVE32BitGatherPrefetch_VectorPlusImmFixed = 0x8400E000,
+  SVE32BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010,
+  SVE32BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010,
+  PRFB_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed,
+  PRFH_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x00800000,
+  PRFW_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01000000,
+  PRFD_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01800000
+};
+
+enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp {
+  SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed = 0xE4608000,
+  SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFMask = 0xFE60A000,
+  SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask = 0xFFE0A000,
+  ST1H_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x00800000,
+  ST1W_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x01000000
+};
+
+enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp {
+  SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed = 0xE4408000,
+  SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE60A000,
+  SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask = 0xFFE0A000,
+  ST1B_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed,
+  ST1H_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000,
+  ST1W_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x01000000
+};
+
+enum SVE32BitScatterStore_VectorPlusImmOp {
+  SVE32BitScatterStore_VectorPlusImmFixed = 0xE460A000,
+  SVE32BitScatterStore_VectorPlusImmFMask = 0xFE60E000,
+  SVE32BitScatterStore_VectorPlusImmMask = 0xFFE0E000,
+  ST1B_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed,
+  ST1H_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x00800000,
+  ST1W_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x01000000
+};
+
+enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp {
+  SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed = 0xC4200000,
+  SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFMask = 0xFE208000,
+  SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask = 0xFFA0E000,
+  LD1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00800000,
+  LDFF1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00802000,
+  LD1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00804000,
+  LDFF1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00806000,
+  LD1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01000000,
+  LDFF1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01002000,
+  LD1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01004000,
+  LDFF1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01006000,
+  LD1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01804000,
+  LDFF1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01806000
+};
+
+enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp {
+  SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000,
+  SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFMask = 0xFE608000,
+  SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000,
+  LD1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00800000,
+  LDFF1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00802000,
+  LD1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00804000,
+  LDFF1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00806000,
+  LD1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01000000,
+  LDFF1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01002000,
+  LD1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01004000,
+  LDFF1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01006000,
+  LD1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01804000,
+  LDFF1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01806000
+};
+
+enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp {
+  SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed = 0xC4408000,
+  SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE608000,
+  SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000,
+  LD1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed,
+  LDFF1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00002000,
+  LD1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00004000,
+  LDFF1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00006000,
+  LD1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000,
+  LDFF1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00802000,
+  LD1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00804000,
+  LDFF1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00806000,
+  LD1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000,
+  LDFF1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01002000,
+  LD1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01004000,
+  LDFF1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01006000,
+  LD1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01804000,
+  LDFF1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01806000
+};
+
+enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
+  SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xC4000000,
+  SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE208000,
+  SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFA0E000,
+  LD1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed,
+  LDFF1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00002000,
+  LD1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00004000,
+  LDFF1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00006000,
+  LD1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000,
+  LDFF1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00802000,
+  LD1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00804000,
+  LDFF1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00806000,
+  LD1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000,
+  LDFF1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01002000,
+  LD1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01004000,
+  LDFF1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01006000,
+  LD1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01804000,
+  LDFF1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01806000
+};
+
+enum SVE64BitGatherLoad_VectorPlusImmOp {
+  SVE64BitGatherLoad_VectorPlusImmFixed = 0xC4208000,
+  SVE64BitGatherLoad_VectorPlusImmFMask = 0xFE608000,
+  SVE64BitGatherLoad_VectorPlusImmMask = 0xFFE0E000,
+  LD1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed,
+  LDFF1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00002000,
+  LD1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00004000,
+  LDFF1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00006000,
+  LD1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00800000,
+  LDFF1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00802000,
+  LD1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00804000,
+  LDFF1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00806000,
+  LD1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01000000,
+  LDFF1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01002000,
+  LD1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01004000,
+  LDFF1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01006000,
+  LD1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01804000,
+  LDFF1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01806000
+};
+
+enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp {
+  SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000,
+  SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFMask = 0xFFE08010,
+  SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E010,
+  PRFB_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed,
+  PRFH_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00002000,
+  PRFW_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00004000,
+  PRFD_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00006000
+};
+
+enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp {
+  SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xC4200000,
+  SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFFA08010,
+  SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFA0E010,
+  PRFB_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed,
+  PRFH_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00002000,
+  PRFW_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00004000,
+  PRFD_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00006000
+};
+
+enum SVE64BitGatherPrefetch_VectorPlusImmOp {
+  SVE64BitGatherPrefetch_VectorPlusImmFixed = 0xC400E000,
+  SVE64BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010,
+  SVE64BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010,
+  PRFB_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed,
+  PRFH_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x00800000,
+  PRFW_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01000000,
+  PRFD_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01800000
+};
+
+enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp {
+  SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed = 0xE420A000,
+  SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFMask = 0xFE60E000,
+  SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000,
+  ST1H_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x00800000,
+  ST1W_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01000000,
+  ST1D_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01800000
+};
+
+enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp {
+  SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed = 0xE400A000,
+  SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE60E000,
+  SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000,
+  ST1B_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed,
+  ST1H_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000,
+  ST1W_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000,
+  ST1D_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01800000
+};
+
+enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp {
+  SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xE4208000,
+  SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFE60A000,
+  SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFE0A000,
+  ST1H_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00800000,
+  ST1W_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01000000,
+  ST1D_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01800000
+};
+
+enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp {
+  SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xE4008000,
+  SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE60A000,
+  SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFE0A000,
+  ST1B_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed,
+  ST1H_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000,
+  ST1W_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000,
+  ST1D_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01800000
+};
+
+enum SVE64BitScatterStore_VectorPlusImmOp {
+  SVE64BitScatterStore_VectorPlusImmFixed = 0xE440A000,
+  SVE64BitScatterStore_VectorPlusImmFMask = 0xFE60E000,
+  SVE64BitScatterStore_VectorPlusImmMask = 0xFFE0E000,
+  ST1B_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed,
+  ST1H_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x00800000,
+  ST1W_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01000000,
+  ST1D_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01800000
+};
+
+enum SVEAddressGenerationOp {
+  SVEAddressGenerationFixed = 0x0420A000,
+  SVEAddressGenerationFMask = 0xFF20F000,
+  SVEAddressGenerationMask = 0xFFE0F000,
+  ADR_z_az_d_s32_scaled = SVEAddressGenerationFixed,
+  ADR_z_az_d_u32_scaled = SVEAddressGenerationFixed | 0x00400000,
+  ADR_z_az_s_same_scaled = SVEAddressGenerationFixed | 0x00800000,
+  ADR_z_az_d_same_scaled = SVEAddressGenerationFixed | 0x00C00000
+};
+
+enum SVEBitwiseLogicalUnpredicatedOp {
+  SVEBitwiseLogicalUnpredicatedFixed = 0x04202000,
+  SVEBitwiseLogicalUnpredicatedFMask = 0xFF20E000,
+  SVEBitwiseLogicalUnpredicatedMask = 0xFFE0FC00,
+  AND_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00001000,
+  ORR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00401000,
+  EOR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00801000,
+  BIC_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00C01000
+};
+
+enum SVEBitwiseLogicalWithImm_UnpredicatedOp {
+  SVEBitwiseLogicalWithImm_UnpredicatedFixed = 0x05000000,
+  SVEBitwiseLogicalWithImm_UnpredicatedFMask = 0xFF3C0000,
+  SVEBitwiseLogicalWithImm_UnpredicatedMask = 0xFFFC0000,
+  ORR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed,
+  EOR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00400000,
+  AND_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00800000
+};
+
+enum SVEBitwiseLogical_PredicatedOp {
+  SVEBitwiseLogical_PredicatedFixed = 0x04180000,
+  SVEBitwiseLogical_PredicatedFMask = 0xFF38E000,
+  SVEBitwiseLogical_PredicatedMask = 0xFF3FE000,
+  ORR_z_p_zz = SVEBitwiseLogical_PredicatedFixed,
+  EOR_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00010000,
+  AND_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00020000,
+  BIC_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00030000
+};
+
+enum SVEBitwiseShiftByImm_PredicatedOp {
+  SVEBitwiseShiftByImm_PredicatedFixed = 0x04008000,
+  SVEBitwiseShiftByImm_PredicatedFMask = 0xFF30E000,
+  SVEBitwiseShiftByImm_PredicatedMask = 0xFF3FE000,
+  ASR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed,
+  LSR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00010000,
+  LSL_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00030000,
+  ASRD_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00040000
+};
+
+enum SVEBitwiseShiftByVector_PredicatedOp {
+  SVEBitwiseShiftByVector_PredicatedFixed = 0x04108000,
+  SVEBitwiseShiftByVector_PredicatedFMask = 0xFF38E000,
+  SVEBitwiseShiftByVector_PredicatedMask = 0xFF3FE000,
+  ASR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed,
+  LSR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00010000,
+  LSL_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00030000,
+  ASRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00040000,
+  LSRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00050000,
+  LSLR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00070000
+};
+
+enum SVEBitwiseShiftByWideElements_PredicatedOp {
+  SVEBitwiseShiftByWideElements_PredicatedFixed = 0x04188000,
+  SVEBitwiseShiftByWideElements_PredicatedFMask = 0xFF38E000,
+  SVEBitwiseShiftByWideElements_PredicatedMask = 0xFF3FE000,
+  ASR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed,
+  LSR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00010000,
+  LSL_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00030000
+};
+
+enum SVEBitwiseShiftUnpredicatedOp {
+  SVEBitwiseShiftUnpredicatedFixed = 0x04208000,
+  SVEBitwiseShiftUnpredicatedFMask = 0xFF20E000,
+  SVEBitwiseShiftUnpredicatedMask = 0xFF20FC00,
+  ASR_z_zw = SVEBitwiseShiftUnpredicatedFixed,
+  LSR_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000400,
+  LSL_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000C00,
+  ASR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001000,
+  LSR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001400,
+  LSL_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001C00
+};
+
+enum SVEBroadcastBitmaskImmOp {
+  SVEBroadcastBitmaskImmFixed = 0x05C00000,
+  SVEBroadcastBitmaskImmFMask = 0xFFFC0000,
+  SVEBroadcastBitmaskImmMask = 0xFFFC0000,
+  DUPM_z_i = SVEBroadcastBitmaskImmFixed
+};
+
+enum SVEBroadcastFPImm_UnpredicatedOp {
+  SVEBroadcastFPImm_UnpredicatedFixed = 0x2539C000,
+  SVEBroadcastFPImm_UnpredicatedFMask = 0xFF39C000,
+  SVEBroadcastFPImm_UnpredicatedMask = 0xFF3FE000,
+  FDUP_z_i = SVEBroadcastFPImm_UnpredicatedFixed
+};
+
+enum SVEBroadcastGeneralRegisterOp {
+  SVEBroadcastGeneralRegisterFixed = 0x05203800,
+  SVEBroadcastGeneralRegisterFMask = 0xFF3FFC00,
+  SVEBroadcastGeneralRegisterMask = 0xFF3FFC00,
+  DUP_z_r = SVEBroadcastGeneralRegisterFixed
+};
+
+enum SVEBroadcastIndexElementOp {
+  SVEBroadcastIndexElementFixed = 0x05202000,
+  SVEBroadcastIndexElementFMask = 0xFF20FC00,
+  SVEBroadcastIndexElementMask = 0xFF20FC00,
+  DUP_z_zi = SVEBroadcastIndexElementFixed
+};
+
+enum SVEBroadcastIntImm_UnpredicatedOp {
+  SVEBroadcastIntImm_UnpredicatedFixed = 0x2538C000,
+  SVEBroadcastIntImm_UnpredicatedFMask = 0xFF39C000,
+  SVEBroadcastIntImm_UnpredicatedMask = 0xFF3FC000,
+  DUP_z_i = SVEBroadcastIntImm_UnpredicatedFixed
+};
+
+enum SVECompressActiveElementsOp {
+  SVECompressActiveElementsFixed = 0x05A18000,
+  SVECompressActiveElementsFMask = 0xFFBFE000,
+  SVECompressActiveElementsMask = 0xFFBFE000,
+  COMPACT_z_p_z = SVECompressActiveElementsFixed
+};
+
+enum SVEConditionallyBroadcastElementToVectorOp {
+  SVEConditionallyBroadcastElementToVectorFixed = 0x05288000,
+  SVEConditionallyBroadcastElementToVectorFMask = 0xFF3EE000,
+  SVEConditionallyBroadcastElementToVectorMask = 0xFF3FE000,
+  CLASTA_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed,
+  CLASTB_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed | 0x00010000
+};
+
+enum SVEConditionallyExtractElementToGeneralRegisterOp {
+  SVEConditionallyExtractElementToGeneralRegisterFixed = 0x0530A000,
+  SVEConditionallyExtractElementToGeneralRegisterFMask = 0xFF3EE000,
+  SVEConditionallyExtractElementToGeneralRegisterMask = 0xFF3FE000,
+  CLASTA_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed,
+  CLASTB_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed | 0x00010000
+};
+
+enum SVEConditionallyExtractElementToSIMDFPScalarOp {
+  SVEConditionallyExtractElementToSIMDFPScalarFixed = 0x052A8000,
+  SVEConditionallyExtractElementToSIMDFPScalarFMask = 0xFF3EE000,
+  SVEConditionallyExtractElementToSIMDFPScalarMask = 0xFF3FE000,
+  CLASTA_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed,
+  CLASTB_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed | 0x00010000
+};
+
+enum SVEConditionallyTerminateScalarsOp {
+  SVEConditionallyTerminateScalarsFixed = 0x25202000,
+  SVEConditionallyTerminateScalarsFMask = 0xFF20FC0F,
+  SVEConditionallyTerminateScalarsMask = 0xFFA0FC1F,
+  CTERMEQ_rr = SVEConditionallyTerminateScalarsFixed | 0x00800000,
+  CTERMNE_rr = SVEConditionallyTerminateScalarsFixed | 0x00800010
+};
+
+enum SVEConstructivePrefix_UnpredicatedOp {
+  SVEConstructivePrefix_UnpredicatedFixed = 0x0420BC00,
+  SVEConstructivePrefix_UnpredicatedFMask = 0xFF20FC00,
+  SVEConstructivePrefix_UnpredicatedMask = 0xFFFFFC00,
+  MOVPRFX_z_z = SVEConstructivePrefix_UnpredicatedFixed
+};
+
+enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp {
+  SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed = 0xA4006000,
+  SVEContiguousFirstFaultLoad_ScalarPlusScalarFMask = 0xFE00E000,
+  SVEContiguousFirstFaultLoad_ScalarPlusScalarMask = 0xFFE0E000,
+  LDFF1B_z_p_br_u8 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed,
+  LDFF1B_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00200000,
+  LDFF1B_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00400000,
+  LDFF1B_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00600000,
+  LDFF1SW_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00800000,
+  LDFF1H_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00A00000,
+  LDFF1H_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00C00000,
+  LDFF1H_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00E00000,
+  LDFF1SH_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01000000,
+  LDFF1SH_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01200000,
+  LDFF1W_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01400000,
+  LDFF1W_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01600000,
+  LDFF1SB_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01800000,
+  LDFF1SB_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01A00000,
+  LDFF1SB_z_p_br_s16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01C00000,
+  LDFF1D_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01E00000
+};
+
+enum SVEContiguousLoad_ScalarPlusImmOp {
+  SVEContiguousLoad_ScalarPlusImmFixed = 0xA400A000,
+  SVEContiguousLoad_ScalarPlusImmFMask = 0xFE10E000,
+  SVEContiguousLoad_ScalarPlusImmMask = 0xFFF0E000,
+  LD1B_z_p_bi_u8 = SVEContiguousLoad_ScalarPlusImmFixed,
+  LD1B_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00200000,
+  LD1B_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00400000,
+  LD1B_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00600000,
+  LD1SW_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00800000,
+  LD1H_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00A00000,
+  LD1H_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00C00000,
+  LD1H_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00E00000,
+  LD1SH_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01000000,
+  LD1SH_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01200000,
+  LD1W_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01400000,
+  LD1W_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01600000,
+  LD1SB_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01800000,
+  LD1SB_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01A00000,
+  LD1SB_z_p_bi_s16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01C00000,
+  LD1D_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01E00000
+};
+
+enum SVEContiguousLoad_ScalarPlusScalarOp {
+  SVEContiguousLoad_ScalarPlusScalarFixed = 0xA4004000,
+  SVEContiguousLoad_ScalarPlusScalarFMask = 0xFE00E000,
+  SVEContiguousLoad_ScalarPlusScalarMask = 0xFFE0E000,
+  LD1B_z_p_br_u8 = SVEContiguousLoad_ScalarPlusScalarFixed,
+  LD1B_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00200000,
+  LD1B_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00400000,
+  LD1B_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00600000,
+  LD1SW_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00800000,
+  LD1H_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00A00000,
+  LD1H_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00C00000,
+  LD1H_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00E00000,
+  LD1SH_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01000000,
+  LD1SH_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01200000,
+  LD1W_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01400000,
+  LD1W_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01600000,
+  LD1SB_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01800000,
+  LD1SB_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01A00000,
+  LD1SB_z_p_br_s16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01C00000,
+  LD1D_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01E00000
+};
+
+enum SVEContiguousNonFaultLoad_ScalarPlusImmOp {
+  SVEContiguousNonFaultLoad_ScalarPlusImmFixed = 0xA410A000,
+  SVEContiguousNonFaultLoad_ScalarPlusImmFMask = 0xFE10E000,
+  SVEContiguousNonFaultLoad_ScalarPlusImmMask = 0xFFF0E000,
+  LDNF1B_z_p_bi_u8 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed,
+  LDNF1B_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00200000,
+  LDNF1B_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00400000,
+  LDNF1B_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00600000,
+  LDNF1SW_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00800000,
+  LDNF1H_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00A00000,
+  LDNF1H_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00C00000,
+  LDNF1H_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00E00000,
+  LDNF1SH_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01000000,
+  LDNF1SH_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01200000,
+  LDNF1W_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01400000,
+  LDNF1W_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01600000,
+  LDNF1SB_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01800000,
+  LDNF1SB_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01A00000,
+  LDNF1SB_z_p_bi_s16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01C00000,
+  LDNF1D_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01E00000
+};
+
+enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp {
+  SVEContiguousNonTemporalLoad_ScalarPlusImmFixed = 0xA400E000,
+  SVEContiguousNonTemporalLoad_ScalarPlusImmFMask = 0xFE70E000,
+  SVEContiguousNonTemporalLoad_ScalarPlusImmMask = 0xFFF0E000,
+  LDNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed,
+  LDNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x00800000,
+  LDNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01000000,
+  LDNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01800000
+};
+
+enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp {
+  SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed = 0xA400C000,
+  SVEContiguousNonTemporalLoad_ScalarPlusScalarFMask = 0xFE60E000,
+  SVEContiguousNonTemporalLoad_ScalarPlusScalarMask = 0xFFE0E000,
+  LDNT1B_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed,
+  LDNT1H_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x00800000,
+  LDNT1W_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01000000,
+  LDNT1D_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01800000
+};
+
+enum SVEContiguousNonTemporalStore_ScalarPlusImmOp {
+  SVEContiguousNonTemporalStore_ScalarPlusImmFixed = 0xE410E000,
+  SVEContiguousNonTemporalStore_ScalarPlusImmFMask = 0xFE70E000,
+  SVEContiguousNonTemporalStore_ScalarPlusImmMask = 0xFFF0E000,
+  STNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed,
+  STNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x00800000,
+  STNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01000000,
+  STNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01800000
+};
+
+enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp {
+  SVEContiguousNonTemporalStore_ScalarPlusScalarFixed = 0xE4006000,
+  SVEContiguousNonTemporalStore_ScalarPlusScalarFMask = 0xFE60E000,
+  SVEContiguousNonTemporalStore_ScalarPlusScalarMask = 0xFFE0E000,
+  STNT1B_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed,
+  STNT1H_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x00800000,
+  STNT1W_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01000000,
+  STNT1D_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01800000
+};
+
+enum SVEContiguousPrefetch_ScalarPlusImmOp {
+  SVEContiguousPrefetch_ScalarPlusImmFixed = 0x85C00000,
+  SVEContiguousPrefetch_ScalarPlusImmFMask = 0xFFC08010,
+  SVEContiguousPrefetch_ScalarPlusImmMask = 0xFFC0E010,
+  PRFB_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed,
+  PRFH_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00002000,
+  PRFW_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00004000,
+  PRFD_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00006000
+};
+
+enum SVEContiguousPrefetch_ScalarPlusScalarOp {
+  SVEContiguousPrefetch_ScalarPlusScalarFixed = 0x8400C000,
+  SVEContiguousPrefetch_ScalarPlusScalarFMask = 0xFE60E010,
+  SVEContiguousPrefetch_ScalarPlusScalarMask = 0xFFE0E010,
+  PRFB_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed,
+  PRFH_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x00800000,
+  PRFW_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01000000,
+  PRFD_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01800000
+};
+
+enum SVEContiguousStore_ScalarPlusImmOp {
+  SVEContiguousStore_ScalarPlusImmFixed = 0xE400E000,
+  SVEContiguousStore_ScalarPlusImmFMask = 0xFE10E000,
+  SVEContiguousStore_ScalarPlusImmMask = 0xFF90E000,
+  ST1B_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed,
+  ST1H_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x00800000,
+  ST1W_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01000000,
+  ST1D_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01800000
+};
+
+enum SVEContiguousStore_ScalarPlusScalarOp {
+  SVEContiguousStore_ScalarPlusScalarFixed = 0xE4004000,
+  SVEContiguousStore_ScalarPlusScalarFMask = 0xFE00E000,
+  SVEContiguousStore_ScalarPlusScalarMask = 0xFF80E000,
+  ST1B_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed,
+  ST1H_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x00800000,
+  ST1W_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01000000,
+  ST1D_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01800000
+};
+
+enum SVECopyFPImm_PredicatedOp {
+  SVECopyFPImm_PredicatedFixed = 0x0510C000,
+  SVECopyFPImm_PredicatedFMask = 0xFF30E000,
+  SVECopyFPImm_PredicatedMask = 0xFF30E000,
+  FCPY_z_p_i = SVECopyFPImm_PredicatedFixed
+};
+
+enum SVECopyGeneralRegisterToVector_PredicatedOp {
+  SVECopyGeneralRegisterToVector_PredicatedFixed = 0x0528A000,
+  SVECopyGeneralRegisterToVector_PredicatedFMask = 0xFF3FE000,
+  SVECopyGeneralRegisterToVector_PredicatedMask = 0xFF3FE000,
+  CPY_z_p_r = SVECopyGeneralRegisterToVector_PredicatedFixed
+};
+
+enum SVECopyIntImm_PredicatedOp {
+  SVECopyIntImm_PredicatedFixed = 0x05100000,
+  SVECopyIntImm_PredicatedFMask = 0xFF308000,
+  SVECopyIntImm_PredicatedMask = 0xFF308000,
+  CPY_z_p_i = SVECopyIntImm_PredicatedFixed
+};
+
+enum SVECopySIMDFPScalarRegisterToVector_PredicatedOp {
+  SVECopySIMDFPScalarRegisterToVector_PredicatedFixed = 0x05208000,
+  SVECopySIMDFPScalarRegisterToVector_PredicatedFMask = 0xFF3FE000,
+  SVECopySIMDFPScalarRegisterToVector_PredicatedMask = 0xFF3FE000,
+  CPY_z_p_v = SVECopySIMDFPScalarRegisterToVector_PredicatedFixed
+};
+
+enum SVEElementCountOp {
+  SVEElementCountFixed = 0x0420E000,
+  SVEElementCountFMask = 0xFF30F800,
+  SVEElementCountMask = 0xFFF0FC00,
+  CNTB_r_s = SVEElementCountFixed,
+  CNTH_r_s = SVEElementCountFixed | 0x00400000,
+  CNTW_r_s = SVEElementCountFixed | 0x00800000,
+  CNTD_r_s = SVEElementCountFixed | 0x00C00000
+};
+
+enum SVEExtractElementToGeneralRegisterOp {
+  SVEExtractElementToGeneralRegisterFixed = 0x0520A000,
+  SVEExtractElementToGeneralRegisterFMask = 0xFF3EE000,
+  SVEExtractElementToGeneralRegisterMask = 0xFF3FE000,
+  LASTA_r_p_z = SVEExtractElementToGeneralRegisterFixed,
+  LASTB_r_p_z = SVEExtractElementToGeneralRegisterFixed | 0x00010000
+};
+
+enum SVEExtractElementToSIMDFPScalarRegisterOp {
+  SVEExtractElementToSIMDFPScalarRegisterFixed = 0x05228000,
+  SVEExtractElementToSIMDFPScalarRegisterFMask = 0xFF3EE000,
+  SVEExtractElementToSIMDFPScalarRegisterMask = 0xFF3FE000,
+  LASTA_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed,
+  LASTB_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed | 0x00010000
+};
+
+enum SVEFFRInitialiseOp {
+  SVEFFRInitialiseFixed = 0x252C9000,
+  SVEFFRInitialiseFMask = 0xFF3FFFFF,
+  SVEFFRInitialiseMask = 0xFFFFFFFF,
+  SETFFR_f = SVEFFRInitialiseFixed
+};
+
+enum SVEFFRWriteFromPredicateOp {
+  SVEFFRWriteFromPredicateFixed = 0x25289000,
+  SVEFFRWriteFromPredicateFMask = 0xFF3FFE1F,
+  SVEFFRWriteFromPredicateMask = 0xFFFFFE1F,
+  WRFFR_f_p = SVEFFRWriteFromPredicateFixed
+};
+
+enum SVEFPAccumulatingReductionOp {
+  SVEFPAccumulatingReductionFixed = 0x65182000,
+  SVEFPAccumulatingReductionFMask = 0xFF38E000,
+  SVEFPAccumulatingReductionMask = 0xFF3FE000,
+  FADDA_v_p_z = SVEFPAccumulatingReductionFixed
+};
+
+enum SVEFPArithmeticUnpredicatedOp {
+  SVEFPArithmeticUnpredicatedFixed = 0x65000000,
+  SVEFPArithmeticUnpredicatedFMask = 0xFF20E000,
+  SVEFPArithmeticUnpredicatedMask = 0xFF20FC00,
+  FADD_z_zz = SVEFPArithmeticUnpredicatedFixed,
+  FSUB_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000400,
+  FMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000800,
+  FTSMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000C00,
+  FRECPS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001800,
+  FRSQRTS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001C00
+};
+
+enum SVEFPArithmeticWithImm_PredicatedOp {
+  SVEFPArithmeticWithImm_PredicatedFixed = 0x65188000,
+  SVEFPArithmeticWithImm_PredicatedFMask = 0xFF38E3C0,
+  SVEFPArithmeticWithImm_PredicatedMask = 0xFF3FE3C0,
+  FADD_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed,
+  FSUB_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00010000,
+  FMUL_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00020000,
+  FSUBR_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00030000,
+  FMAXNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00040000,
+  FMINNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00050000,
+  FMAX_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00060000,
+  FMIN_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00070000
+};
+
+enum SVEFPArithmetic_PredicatedOp {
+  SVEFPArithmetic_PredicatedFixed = 0x65008000,
+  SVEFPArithmetic_PredicatedFMask = 0xFF30E000,
+  SVEFPArithmetic_PredicatedMask = 0xFF3FE000,
+  FADD_z_p_zz = SVEFPArithmetic_PredicatedFixed,
+  FSUB_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00010000,
+  FMUL_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00020000,
+  FSUBR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00030000,
+  FMAXNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00040000,
+  FMINNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00050000,
+  FMAX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00060000,
+  FMIN_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00070000,
+  FABD_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00080000,
+  FSCALE_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00090000,
+  FMULX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000A0000,
+  FDIVR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000C0000,
+  FDIV_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000D0000
+};
+
+enum SVEFPCompareVectorsOp {
+  SVEFPCompareVectorsFixed = 0x65004000,
+  SVEFPCompareVectorsFMask = 0xFF204000,
+  SVEFPCompareVectorsMask = 0xFF20E010,
+  FCMGE_p_p_zz = SVEFPCompareVectorsFixed,
+  FCMGT_p_p_zz = SVEFPCompareVectorsFixed | 0x00000010,
+  FCMEQ_p_p_zz = SVEFPCompareVectorsFixed | 0x00002000,
+  FCMNE_p_p_zz = SVEFPCompareVectorsFixed | 0x00002010,
+  FCMUO_p_p_zz = SVEFPCompareVectorsFixed | 0x00008000,
+  FACGE_p_p_zz = SVEFPCompareVectorsFixed | 0x00008010,
+  FACGT_p_p_zz = SVEFPCompareVectorsFixed | 0x0000A010
+};
+
+enum SVEFPCompareWithZeroOp {
+  SVEFPCompareWithZeroFixed = 0x65102000,
+  SVEFPCompareWithZeroFMask = 0xFF38E000,
+  SVEFPCompareWithZeroMask = 0xFF3FE010,
+  FCMGE_p_p_z0 = SVEFPCompareWithZeroFixed,
+  FCMGT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00000010,
+  FCMLT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010000,
+  FCMLE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010010,
+  FCMEQ_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00020000,
+  FCMNE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00030000
+};
+
+enum SVEFPComplexAdditionOp {
+  SVEFPComplexAdditionFixed = 0x64008000,
+  SVEFPComplexAdditionFMask = 0xFF3EE000,
+  SVEFPComplexAdditionMask = 0xFF3EE000,
+  FCADD_z_p_zz = SVEFPComplexAdditionFixed
+};
+
+enum SVEFPComplexMulAddOp {
+  SVEFPComplexMulAddFixed = 0x64000000,
+  SVEFPComplexMulAddFMask = 0xFF208000,
+  SVEFPComplexMulAddMask = 0xFF208000,
+  FCMLA_z_p_zzz = SVEFPComplexMulAddFixed
+};
+
+enum SVEFPComplexMulAddIndexOp {
+  SVEFPComplexMulAddIndexFixed = 0x64201000,
+  SVEFPComplexMulAddIndexFMask = 0xFF20F000,
+  SVEFPComplexMulAddIndexMask = 0xFFE0F000,
+  FCMLA_z_zzzi_h = SVEFPComplexMulAddIndexFixed | 0x00800000,
+  FCMLA_z_zzzi_s = SVEFPComplexMulAddIndexFixed | 0x00C00000
+};
+
+enum SVEFPConvertPrecisionOp {
+  SVEFPConvertPrecisionFixed = 0x6508A000,
+  SVEFPConvertPrecisionFMask = 0xFF3CE000,
+  SVEFPConvertPrecisionMask = 0xFFFFE000,
+  FCVT_z_p_z_s2h = SVEFPConvertPrecisionFixed | 0x00800000,
+  FCVT_z_p_z_h2s = SVEFPConvertPrecisionFixed | 0x00810000,
+  FCVT_z_p_z_d2h = SVEFPConvertPrecisionFixed | 0x00C00000,
+  FCVT_z_p_z_h2d = SVEFPConvertPrecisionFixed | 0x00C10000,
+  FCVT_z_p_z_d2s = SVEFPConvertPrecisionFixed | 0x00C20000,
+  FCVT_z_p_z_s2d = SVEFPConvertPrecisionFixed | 0x00C30000
+};
+
+enum SVEFPConvertToIntOp {
+  SVEFPConvertToIntFixed = 0x6518A000,
+  SVEFPConvertToIntFMask = 0xFF38E000,
+  SVEFPConvertToIntMask = 0xFFFFE000,
+  FCVTZS_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00420000,
+  FCVTZU_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00430000,
+  FCVTZS_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00440000,
+  FCVTZU_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00450000,
+  FCVTZS_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00460000,
+  FCVTZU_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00470000,
+  FCVTZS_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00840000,
+  FCVTZU_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00850000,
+  FCVTZS_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C00000,
+  FCVTZU_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C10000,
+  FCVTZS_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C40000,
+  FCVTZU_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C50000,
+  FCVTZS_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C60000,
+  FCVTZU_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C70000
+};
+
+enum SVEFPExponentialAcceleratorOp {
+  SVEFPExponentialAcceleratorFixed = 0x0420B800,
+  SVEFPExponentialAcceleratorFMask = 0xFF20FC00,
+  SVEFPExponentialAcceleratorMask = 0xFF3FFC00,
+  FEXPA_z_z = SVEFPExponentialAcceleratorFixed
+};
+
+enum SVEFPFastReductionOp {
+  SVEFPFastReductionFixed = 0x65002000,
+  SVEFPFastReductionFMask = 0xFF38E000,
+  SVEFPFastReductionMask = 0xFF3FE000,
+  FADDV_v_p_z = SVEFPFastReductionFixed,
+  FMAXNMV_v_p_z = SVEFPFastReductionFixed | 0x00040000,
+  FMINNMV_v_p_z = SVEFPFastReductionFixed | 0x00050000,
+  FMAXV_v_p_z = SVEFPFastReductionFixed | 0x00060000,
+  FMINV_v_p_z = SVEFPFastReductionFixed | 0x00070000
+};
+
+enum SVEFPMulAddOp {
+  SVEFPMulAddFixed = 0x65200000,
+  SVEFPMulAddFMask = 0xFF200000,
+  SVEFPMulAddMask = 0xFF20E000,
+  FMLA_z_p_zzz = SVEFPMulAddFixed,
+  FMLS_z_p_zzz = SVEFPMulAddFixed | 0x00002000,
+  FNMLA_z_p_zzz = SVEFPMulAddFixed | 0x00004000,
+  FNMLS_z_p_zzz = SVEFPMulAddFixed | 0x00006000,
+  FMAD_z_p_zzz = SVEFPMulAddFixed | 0x00008000,
+  FMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000A000,
+  FNMAD_z_p_zzz = SVEFPMulAddFixed | 0x0000C000,
+  FNMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000E000
+};
+
+enum SVEFPMulAddIndexOp {
+  SVEFPMulAddIndexFixed = 0x64200000,
+  SVEFPMulAddIndexFMask = 0xFF20F800,
+  SVEFPMulAddIndexMask = 0xFFE0FC00,
+  FMLA_z_zzzi_h = SVEFPMulAddIndexFixed,
+  FMLA_z_zzzi_h_i3h = FMLA_z_zzzi_h | 0x00400000,
+  FMLS_z_zzzi_h = SVEFPMulAddIndexFixed | 0x00000400,
+  FMLS_z_zzzi_h_i3h = FMLS_z_zzzi_h | 0x00400000,
+  FMLA_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800000,
+  FMLS_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800400,
+  FMLA_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00000,
+  FMLS_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00400
+};
+
+enum SVEFPMulIndexOp {
+  SVEFPMulIndexFixed = 0x64202000,
+  SVEFPMulIndexFMask = 0xFF20FC00,
+  SVEFPMulIndexMask = 0xFFE0FC00,
+  FMUL_z_zzi_h = SVEFPMulIndexFixed,
+  FMUL_z_zzi_h_i3h = FMUL_z_zzi_h | 0x00400000,
+  FMUL_z_zzi_s = SVEFPMulIndexFixed | 0x00800000,
+  FMUL_z_zzi_d = SVEFPMulIndexFixed | 0x00C00000
+};
+
+enum SVEFPRoundToIntegralValueOp {
+  SVEFPRoundToIntegralValueFixed = 0x6500A000,
+  SVEFPRoundToIntegralValueFMask = 0xFF38E000,
+  SVEFPRoundToIntegralValueMask = 0xFF3FE000,
+  FRINTN_z_p_z = SVEFPRoundToIntegralValueFixed,
+  FRINTP_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00010000,
+  FRINTM_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00020000,
+  FRINTZ_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00030000,
+  FRINTA_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00040000,
+  FRINTX_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00060000,
+  FRINTI_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00070000
+};
+
+enum SVEFPTrigMulAddCoefficientOp {
+  SVEFPTrigMulAddCoefficientFixed = 0x65108000,
+  SVEFPTrigMulAddCoefficientFMask = 0xFF38FC00,
+  SVEFPTrigMulAddCoefficientMask = 0xFF38FC00,
+  FTMAD_z_zzi = SVEFPTrigMulAddCoefficientFixed
+};
+
+enum SVEFPTrigSelectCoefficientOp {
+  SVEFPTrigSelectCoefficientFixed = 0x0420B000,
+  SVEFPTrigSelectCoefficientFMask = 0xFF20F800,
+  SVEFPTrigSelectCoefficientMask = 0xFF20FC00,
+  FTSSEL_z_zz = SVEFPTrigSelectCoefficientFixed
+};
+
+enum SVEFPUnaryOpOp {
+  SVEFPUnaryOpFixed = 0x650CA000,
+  SVEFPUnaryOpFMask = 0xFF3CE000,
+  SVEFPUnaryOpMask = 0xFF3FE000,
+  FRECPX_z_p_z = SVEFPUnaryOpFixed,
+  FSQRT_z_p_z = SVEFPUnaryOpFixed | 0x00010000
+};
+
+enum SVEFPUnaryOpUnpredicatedOp {
+  SVEFPUnaryOpUnpredicatedFixed = 0x65083000,
+  SVEFPUnaryOpUnpredicatedFMask = 0xFF38F000,
+  SVEFPUnaryOpUnpredicatedMask = 0xFF3FFC00,
+  FRECPE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00060000,
+  FRSQRTE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00070000
+};
+
+enum SVEIncDecByPredicateCountOp {
+  SVEIncDecByPredicateCountFixed = 0x25288000,
+  SVEIncDecByPredicateCountFMask = 0xFF38F000,
+  SVEIncDecByPredicateCountMask = 0xFF3FFE00,
+  SQINCP_z_p_z = SVEIncDecByPredicateCountFixed,
+  SQINCP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00000800,
+  SQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00000C00,
+  UQINCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00010000,
+  UQINCP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00010800,
+  UQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00010C00,
+  SQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00020000,
+  SQDECP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00020800,
+  SQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00020C00,
+  UQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00030000,
+  UQDECP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00030800,
+  UQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00030C00,
+  INCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00040000,
+  INCP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00040800,
+  DECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00050000,
+  DECP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00050800
+};
+
+enum SVEIncDecRegisterByElementCountOp {
+  SVEIncDecRegisterByElementCountFixed = 0x0430E000,
+  SVEIncDecRegisterByElementCountFMask = 0xFF30F800,
+  SVEIncDecRegisterByElementCountMask = 0xFFF0FC00,
+  INCB_r_rs = SVEIncDecRegisterByElementCountFixed,
+  DECB_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00000400,
+  INCH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400000,
+  DECH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400400,
+  INCW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800000,
+  DECW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800400,
+  INCD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00000,
+  DECD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00400
+};
+
+enum SVEIncDecVectorByElementCountOp {
+  SVEIncDecVectorByElementCountFixed = 0x0430C000,
+  SVEIncDecVectorByElementCountFMask = 0xFF30F800,
+  SVEIncDecVectorByElementCountMask = 0xFFF0FC00,
+  INCH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400000,
+  DECH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400400,
+  INCW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800000,
+  DECW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800400,
+  INCD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00000,
+  DECD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00400
+};
+
+enum SVEIndexGenerationOp {
+  SVEIndexGenerationFixed = 0x04204000,
+  SVEIndexGenerationFMask = 0xFF20F000,
+  SVEIndexGenerationMask = 0xFF20FC00,
+  INDEX_z_ii = SVEIndexGenerationFixed,
+  INDEX_z_ri = SVEIndexGenerationFixed | 0x00000400,
+  INDEX_z_ir = SVEIndexGenerationFixed | 0x00000800,
+  INDEX_z_rr = SVEIndexGenerationFixed | 0x00000C00
+};
+
+enum SVEInsertGeneralRegisterOp {
+  SVEInsertGeneralRegisterFixed = 0x05243800,
+  SVEInsertGeneralRegisterFMask = 0xFF3FFC00,
+  SVEInsertGeneralRegisterMask = 0xFF3FFC00,
+  INSR_z_r = SVEInsertGeneralRegisterFixed
+};
+
+enum SVEInsertSIMDFPScalarRegisterOp {
+  SVEInsertSIMDFPScalarRegisterFixed = 0x05343800,
+  SVEInsertSIMDFPScalarRegisterFMask = 0xFF3FFC00,
+  SVEInsertSIMDFPScalarRegisterMask = 0xFF3FFC00,
+  INSR_z_v = SVEInsertSIMDFPScalarRegisterFixed
+};
+
+enum SVEIntAddSubtractImm_UnpredicatedOp {
+  SVEIntAddSubtractImm_UnpredicatedFixed = 0x2520C000,
+  SVEIntAddSubtractImm_UnpredicatedFMask = 0xFF38C000,
+  SVEIntAddSubtractImm_UnpredicatedMask = 0xFF3FC000,
+  ADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed,
+  SUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00010000,
+  SUBR_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00030000,
+  SQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00040000,
+  UQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00050000,
+  SQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00060000,
+  UQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00070000
+};
+
+enum SVEIntAddSubtractVectors_PredicatedOp {
+  SVEIntAddSubtractVectors_PredicatedFixed = 0x04000000,
+  SVEIntAddSubtractVectors_PredicatedFMask = 0xFF38E000,
+  SVEIntAddSubtractVectors_PredicatedMask = 0xFF3FE000,
+  ADD_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed,
+  SUB_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00010000,
+  SUBR_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00030000
+};
+
+enum SVEIntArithmeticUnpredicatedOp {
+  SVEIntArithmeticUnpredicatedFixed = 0x04200000,
+  SVEIntArithmeticUnpredicatedFMask = 0xFF20E000,
+  SVEIntArithmeticUnpredicatedMask = 0xFF20FC00,
+  ADD_z_zz = SVEIntArithmeticUnpredicatedFixed,
+  SUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00000400,
+  SQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001000,
+  UQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001400,
+  SQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001800,
+  UQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001C00
+};
+
+enum SVEIntCompareScalarCountAndLimitOp {
+  SVEIntCompareScalarCountAndLimitFixed = 0x25200000,
+  SVEIntCompareScalarCountAndLimitFMask = 0xFF20E000,
+  SVEIntCompareScalarCountAndLimitMask = 0xFF20EC10,
+  WHILELT_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000400,
+  WHILELE_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000410,
+  WHILELO_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C00,
+  WHILELS_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C10
+};
+
+enum SVEIntCompareSignedImmOp {
+  SVEIntCompareSignedImmFixed = 0x25000000,
+  SVEIntCompareSignedImmFMask = 0xFF204000,
+  SVEIntCompareSignedImmMask = 0xFF20E010,
+  CMPGE_p_p_zi = SVEIntCompareSignedImmFixed,
+  CMPGT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00000010,
+  CMPLT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002000,
+  CMPLE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002010,
+  CMPEQ_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008000,
+  CMPNE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008010
+};
+
+enum SVEIntCompareUnsignedImmOp {
+  SVEIntCompareUnsignedImmFixed = 0x24200000,
+  SVEIntCompareUnsignedImmFMask = 0xFF200000,
+  SVEIntCompareUnsignedImmMask = 0xFF202010,
+  CMPHS_p_p_zi = SVEIntCompareUnsignedImmFixed,
+  CMPHI_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00000010,
+  CMPLO_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002000,
+  CMPLS_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002010
+};
+
+enum SVEIntCompareVectorsOp {
+  SVEIntCompareVectorsFixed = 0x24000000,
+  SVEIntCompareVectorsFMask = 0xFF200000,
+  SVEIntCompareVectorsMask = 0xFF20E010,
+  CMPHS_p_p_zz = SVEIntCompareVectorsFixed,
+  CMPHI_p_p_zz = SVEIntCompareVectorsFixed | 0x00000010,
+  CMPEQ_p_p_zw = SVEIntCompareVectorsFixed | 0x00002000,
+  CMPNE_p_p_zw = SVEIntCompareVectorsFixed | 0x00002010,
+  CMPGE_p_p_zw = SVEIntCompareVectorsFixed | 0x00004000,
+  CMPGT_p_p_zw = SVEIntCompareVectorsFixed | 0x00004010,
+  CMPLT_p_p_zw = SVEIntCompareVectorsFixed | 0x00006000,
+  CMPLE_p_p_zw = SVEIntCompareVectorsFixed | 0x00006010,
+  CMPGE_p_p_zz = SVEIntCompareVectorsFixed | 0x00008000,
+  CMPGT_p_p_zz = SVEIntCompareVectorsFixed | 0x00008010,
+  CMPEQ_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A000,
+  CMPNE_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A010,
+  CMPHS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C000,
+  CMPHI_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C010,
+  CMPLO_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E000,
+  CMPLS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E010
+};
+
+enum SVEIntConvertToFPOp {
+  SVEIntConvertToFPFixed = 0x6510A000,
+  SVEIntConvertToFPFMask = 0xFF38E000,
+  SVEIntConvertToFPMask = 0xFFFFE000,
+  SCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00420000,
+  UCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00430000,
+  SCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00440000,
+  UCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00450000,
+  SCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00460000,
+  UCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00470000,
+  SCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00840000,
+  UCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00850000,
+  SCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C00000,
+  UCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C10000,
+  SCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C40000,
+  UCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C50000,
+  SCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C60000,
+  UCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C70000
+};
+
+enum SVEIntDivideVectors_PredicatedOp {
+  SVEIntDivideVectors_PredicatedFixed = 0x04140000,
+  SVEIntDivideVectors_PredicatedFMask = 0xFF3CE000,
+  SVEIntDivideVectors_PredicatedMask = 0xFF3FE000,
+  SDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed,
+  UDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00010000,
+  SDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00020000,
+  UDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00030000
+};
+
+enum SVEIntMinMaxDifference_PredicatedOp {
+  SVEIntMinMaxDifference_PredicatedFixed = 0x04080000,
+  SVEIntMinMaxDifference_PredicatedFMask = 0xFF38E000,
+  SVEIntMinMaxDifference_PredicatedMask = 0xFF3FE000,
+  SMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed,
+  UMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00010000,
+  SMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00020000,
+  UMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00030000,
+  SABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00040000,
+  UABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00050000
+};
+
+enum SVEIntMinMaxImm_UnpredicatedOp {
+  SVEIntMinMaxImm_UnpredicatedFixed = 0x2528C000,
+  SVEIntMinMaxImm_UnpredicatedFMask = 0xFF38C000,
+  SVEIntMinMaxImm_UnpredicatedMask = 0xFF3FE000,
+  SMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed,
+  UMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00010000,
+  SMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00020000,
+  UMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00030000
+};
+
+enum SVEIntMulAddPredicatedOp {
+  SVEIntMulAddPredicatedFixed = 0x04004000,
+  SVEIntMulAddPredicatedFMask = 0xFF204000,
+  SVEIntMulAddPredicatedMask = 0xFF20E000,
+  MLA_z_p_zzz = SVEIntMulAddPredicatedFixed,
+  MLS_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00002000,
+  MAD_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00008000,
+  MSB_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x0000A000
+};
+
+enum SVEIntMulAddUnpredicatedOp {
+  SVEIntMulAddUnpredicatedFixed = 0x44000000,
+  SVEIntMulAddUnpredicatedFMask = 0xFF208000,
+  SVEIntMulAddUnpredicatedMask = 0xFF20FC00,
+  SDOT_z_zzz = SVEIntMulAddUnpredicatedFixed,
+  UDOT_z_zzz = SVEIntMulAddUnpredicatedFixed | 0x00000400
+};
+
+enum SVEIntMulImm_UnpredicatedOp {
+  SVEIntMulImm_UnpredicatedFixed = 0x2530C000,
+  SVEIntMulImm_UnpredicatedFMask = 0xFF38C000,
+  SVEIntMulImm_UnpredicatedMask = 0xFF3FE000,
+  MUL_z_zi = SVEIntMulImm_UnpredicatedFixed
+};
+
+enum SVEIntMulVectors_PredicatedOp {
+  SVEIntMulVectors_PredicatedFixed = 0x04100000,
+  SVEIntMulVectors_PredicatedFMask = 0xFF3CE000,
+  SVEIntMulVectors_PredicatedMask = 0xFF3FE000,
+  MUL_z_p_zz = SVEIntMulVectors_PredicatedFixed,
+  SMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00020000,
+  UMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00030000
+};
+
+enum SVEMovprfxOp {
+  SVEMovprfxFixed = 0x04002000,
+  SVEMovprfxFMask = 0xFF20E000,
+  SVEMovprfxMask = 0xFF3EE000,
+  MOVPRFX_z_p_z = SVEMovprfxFixed | 0x00100000
+};
+
+enum SVEIntReductionOp {
+  SVEIntReductionFixed = 0x04002000,
+  SVEIntReductionFMask = 0xFF20E000,
+  SVEIntReductionMask = 0xFF3FE000,
+  SADDV_r_p_z = SVEIntReductionFixed,
+  UADDV_r_p_z = SVEIntReductionFixed | 0x00010000,
+  SMAXV_r_p_z = SVEIntReductionFixed | 0x00080000,
+  UMAXV_r_p_z = SVEIntReductionFixed | 0x00090000,
+  SMINV_r_p_z = SVEIntReductionFixed | 0x000A0000,
+  UMINV_r_p_z = SVEIntReductionFixed | 0x000B0000
+};
+
+enum SVEIntReductionLogicalOp {
+  SVEIntReductionLogicalFixed = 0x04182000,
+  SVEIntReductionLogicalFMask = 0xFF38E000,
+  SVEIntReductionLogicalMask = 0xFF3FE000,
+  ORV_r_p_z = SVEIntReductionLogicalFixed | 0x00180000,
+  EORV_r_p_z = SVEIntReductionLogicalFixed | 0x00190000,
+  ANDV_r_p_z = SVEIntReductionLogicalFixed | 0x001A0000
+};
+
+enum SVEIntUnaryArithmeticPredicatedOp {
+  SVEIntUnaryArithmeticPredicatedFixed = 0x0400A000,
+  SVEIntUnaryArithmeticPredicatedFMask = 0xFF20E000,
+  SVEIntUnaryArithmeticPredicatedMask = 0xFF3FE000,
+  SXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00100000,
+  UXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00110000,
+  SXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00120000,
+  UXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00130000,
+  SXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00140000,
+  UXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00150000,
+  ABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00160000,
+  NEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00170000,
+  CLS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00180000,
+  CLZ_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00190000,
+  CNT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001A0000,
+  CNOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001B0000,
+  FABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001C0000,
+  FNEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001D0000,
+  NOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001E0000
+};
+
+enum SVELoadAndBroadcastElementOp {
+  SVELoadAndBroadcastElementFixed = 0x84408000,
+  SVELoadAndBroadcastElementFMask = 0xFE408000,
+  SVELoadAndBroadcastElementMask = 0xFFC0E000,
+  LD1RB_z_p_bi_u8 = SVELoadAndBroadcastElementFixed,
+  LD1RB_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00002000,
+  LD1RB_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00004000,
+  LD1RB_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00006000,
+  LD1RSW_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x00800000,
+  LD1RH_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00802000,
+  LD1RH_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00804000,
+  LD1RH_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00806000,
+  LD1RSH_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01000000,
+  LD1RSH_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01002000,
+  LD1RW_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x01004000,
+  LD1RW_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01006000,
+  LD1RSB_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01800000,
+  LD1RSB_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01802000,
+  LD1RSB_z_p_bi_s16 = SVELoadAndBroadcastElementFixed | 0x01804000,
+  LD1RD_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01806000
+};
+
+enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp {
+  SVELoadAndBroadcastQuadword_ScalarPlusImmFixed = 0xA4002000,
+  SVELoadAndBroadcastQuadword_ScalarPlusImmFMask = 0xFE10E000,
+  SVELoadAndBroadcastQuadword_ScalarPlusImmMask = 0xFFF0E000,
+  LD1RQB_z_p_bi_u8 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed,
+  LD1RQH_z_p_bi_u16 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x00800000,
+  LD1RQW_z_p_bi_u32 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01000000,
+  LD1RQD_z_p_bi_u64 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01800000
+};
+
+enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp {
+  SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed = 0xA4000000,
+  SVELoadAndBroadcastQuadword_ScalarPlusScalarFMask = 0xFE00E000,
+  SVELoadAndBroadcastQuadword_ScalarPlusScalarMask = 0xFFE0E000,
+  LD1RQB_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed,
+  LD1RQH_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x00800000,
+  LD1RQW_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01000000,
+  LD1RQD_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01800000
+};
+
+enum SVELoadMultipleStructures_ScalarPlusImmOp {
+  SVELoadMultipleStructures_ScalarPlusImmFixed = 0xA400E000,
+  SVELoadMultipleStructures_ScalarPlusImmFMask = 0xFE10E000,
+  SVELoadMultipleStructures_ScalarPlusImmMask = 0xFFF0E000,
+  LD2B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00200000,
+  LD3B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00400000,
+  LD4B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00600000,
+  LD2H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00A00000,
+  LD3H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00C00000,
+  LD4H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00E00000,
+  LD2W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01200000,
+  LD3W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01400000,
+  LD4W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01600000,
+  LD2D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01A00000,
+  LD3D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01C00000,
+  LD4D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01E00000
+};
+
+enum SVELoadMultipleStructures_ScalarPlusScalarOp {
+  SVELoadMultipleStructures_ScalarPlusScalarFixed = 0xA400C000,
+  SVELoadMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000,
+  SVELoadMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000,
+  LD2B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00200000,
+  LD3B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00400000,
+  LD4B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00600000,
+  LD2H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00A00000,
+  LD3H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00C00000,
+  LD4H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00E00000,
+  LD2W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01200000,
+  LD3W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01400000,
+  LD4W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01600000,
+  LD2D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01A00000,
+  LD3D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01C00000,
+  LD4D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01E00000
+};
+
+enum SVELoadPredicateRegisterOp {
+  SVELoadPredicateRegisterFixed = 0x85800000,
+  SVELoadPredicateRegisterFMask = 0xFFC0E010,
+  SVELoadPredicateRegisterMask = 0xFFC0E010,
+  LDR_p_bi = SVELoadPredicateRegisterFixed
+};
+
+enum SVELoadVectorRegisterOp {
+  SVELoadVectorRegisterFixed = 0x85804000,
+  SVELoadVectorRegisterFMask = 0xFFC0E000,
+  SVELoadVectorRegisterMask = 0xFFC0E000,
+  LDR_z_bi = SVELoadVectorRegisterFixed
+};
+
+enum SVEMulIndexOp {
+  SVEMulIndexFixed = 0x44200000,
+  SVEMulIndexFMask = 0xFF200000,
+  SVEMulIndexMask = 0xFFE0FC00,
+  SDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800000,
+  UDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800400,
+  SDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00000,
+  UDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00400
+};
+
+enum SVEPartitionBreakConditionOp {
+  SVEPartitionBreakConditionFixed = 0x25104000,
+  SVEPartitionBreakConditionFMask = 0xFF3FC200,
+  SVEPartitionBreakConditionMask = 0xFFFFC200,
+  BRKA_p_p_p = SVEPartitionBreakConditionFixed,
+  BRKAS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00400000,
+  BRKB_p_p_p = SVEPartitionBreakConditionFixed | 0x00800000,
+  BRKBS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00C00000
+};
+
+enum SVEPermutePredicateElementsOp {
+  SVEPermutePredicateElementsFixed = 0x05204000,
+  SVEPermutePredicateElementsFMask = 0xFF30E210,
+  SVEPermutePredicateElementsMask = 0xFF30FE10,
+  ZIP1_p_pp = SVEPermutePredicateElementsFixed,
+  ZIP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000400,
+  UZP1_p_pp = SVEPermutePredicateElementsFixed | 0x00000800,
+  UZP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000C00,
+  TRN1_p_pp = SVEPermutePredicateElementsFixed | 0x00001000,
+  TRN2_p_pp = SVEPermutePredicateElementsFixed | 0x00001400
+};
+
+enum SVEPermuteVectorExtractOp {
+  SVEPermuteVectorExtractFixed = 0x05200000,
+  SVEPermuteVectorExtractFMask = 0xFF20E000,
+  SVEPermuteVectorExtractMask = 0xFFE0E000,
+  EXT_z_zi_des = SVEPermuteVectorExtractFixed
+};
+
+enum SVEPermuteVectorInterleavingOp {
+  SVEPermuteVectorInterleavingFixed = 0x05206000,
+  SVEPermuteVectorInterleavingFMask = 0xFF20E000,
+  SVEPermuteVectorInterleavingMask = 0xFF20FC00,
+  ZIP1_z_zz = SVEPermuteVectorInterleavingFixed,
+  ZIP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000400,
+  UZP1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000800,
+  UZP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000C00,
+  TRN1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001000,
+  TRN2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001400
+};
+
+enum SVEPredicateCountOp {
+  SVEPredicateCountFixed = 0x25208000,
+  SVEPredicateCountFMask = 0xFF38C000,
+  SVEPredicateCountMask = 0xFF3FC200,
+  CNTP_r_p_p = SVEPredicateCountFixed
+};
+
+enum SVEPredicateFirstActiveOp {
+  SVEPredicateFirstActiveFixed = 0x2518C000,
+  SVEPredicateFirstActiveFMask = 0xFF3FFE10,
+  SVEPredicateFirstActiveMask = 0xFFFFFE10,
+  PFIRST_p_p_p = SVEPredicateFirstActiveFixed | 0x00400000
+};
+
+enum SVEPredicateInitializeOp {
+  SVEPredicateInitializeFixed = 0x2518E000,
+  SVEPredicateInitializeFMask = 0xFF3EFC10,
+  SVEPredicateInitializeMask = 0xFF3FFC10,
+  SVEPredicateInitializeSetFlagsBit = 0x00010000,
+  PTRUE_p_s = SVEPredicateInitializeFixed | 0x00000000,
+  PTRUES_p_s = SVEPredicateInitializeFixed | SVEPredicateInitializeSetFlagsBit
+};
+
+enum SVEPredicateLogicalOp {
+  SVEPredicateLogicalFixed = 0x25004000,
+  SVEPredicateLogicalFMask = 0xFF30C000,
+  SVEPredicateLogicalMask = 0xFFF0C210,
+  SVEPredicateLogicalSetFlagsBit = 0x00400000,
+  AND_p_p_pp_z = SVEPredicateLogicalFixed,
+  ANDS_p_p_pp_z = AND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
+  BIC_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000010,
+  BICS_p_p_pp_z = BIC_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
+  EOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000200,
+  EORS_p_p_pp_z = EOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
+  ORR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800000,
+  ORRS_p_p_pp_z = ORR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
+  ORN_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800010,
+  ORNS_p_p_pp_z = ORN_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
+  NAND_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800210,
+  NANDS_p_p_pp_z = NAND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
+  NOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800200,
+  NORS_p_p_pp_z = NOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit,
+  SEL_p_p_pp = SVEPredicateLogicalFixed | 0x00000210
+};
+
+enum SVEPredicateNextActiveOp {
+  SVEPredicateNextActiveFixed = 0x2519C400,
+  SVEPredicateNextActiveFMask = 0xFF3FFE10,
+  SVEPredicateNextActiveMask = 0xFF3FFE10,
+  PNEXT_p_p_p = SVEPredicateNextActiveFixed
+};
+
+enum SVEPredicateReadFromFFR_PredicatedOp {
+  SVEPredicateReadFromFFR_PredicatedFixed = 0x2518F000,
+  SVEPredicateReadFromFFR_PredicatedFMask = 0xFF3FFE10,
+  SVEPredicateReadFromFFR_PredicatedMask = 0xFFFFFE10,
+  RDFFR_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed,
+  RDFFRS_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed | 0x00400000
+};
+
+enum SVEPredicateReadFromFFR_UnpredicatedOp {
+  SVEPredicateReadFromFFR_UnpredicatedFixed = 0x2519F000,
+  SVEPredicateReadFromFFR_UnpredicatedFMask = 0xFF3FFFF0,
+  SVEPredicateReadFromFFR_UnpredicatedMask = 0xFFFFFFF0,
+  RDFFR_p_f = SVEPredicateReadFromFFR_UnpredicatedFixed
+};
+
+enum SVEPredicateTestOp {
+  SVEPredicateTestFixed = 0x2510C000,
+  SVEPredicateTestFMask = 0xFF3FC210,
+  SVEPredicateTestMask = 0xFFFFC21F,
+  PTEST_p_p = SVEPredicateTestFixed | 0x00400000
+};
+
+enum SVEPredicateZeroOp {
+  SVEPredicateZeroFixed = 0x2518E400,
+  SVEPredicateZeroFMask = 0xFF3FFFF0,
+  SVEPredicateZeroMask = 0xFFFFFFF0,
+  PFALSE_p = SVEPredicateZeroFixed
+};
+
+enum SVEPropagateBreakOp {
+  SVEPropagateBreakFixed = 0x2500C000,
+  SVEPropagateBreakFMask = 0xFF30C000,
+  SVEPropagateBreakMask = 0xFFF0C210,
+  BRKPA_p_p_pp = SVEPropagateBreakFixed,
+  BRKPB_p_p_pp = SVEPropagateBreakFixed | 0x00000010,
+  BRKPAS_p_p_pp = SVEPropagateBreakFixed | 0x00400000,
+  BRKPBS_p_p_pp = SVEPropagateBreakFixed | 0x00400010
+};
+
+enum SVEPropagateBreakToNextPartitionOp {
+  SVEPropagateBreakToNextPartitionFixed = 0x25184000,
+  SVEPropagateBreakToNextPartitionFMask = 0xFFBFC210,
+  SVEPropagateBreakToNextPartitionMask = 0xFFFFC210,
+  BRKN_p_p_pp = SVEPropagateBreakToNextPartitionFixed,
+  BRKNS_p_p_pp = SVEPropagateBreakToNextPartitionFixed | 0x00400000
+};
+
+enum SVEReversePredicateElementsOp {
+  SVEReversePredicateElementsFixed = 0x05344000,
+  SVEReversePredicateElementsFMask = 0xFF3FFE10,
+  SVEReversePredicateElementsMask = 0xFF3FFE10,
+  REV_p_p = SVEReversePredicateElementsFixed
+};
+
+enum SVEReverseVectorElementsOp {
+  SVEReverseVectorElementsFixed = 0x05383800,
+  SVEReverseVectorElementsFMask = 0xFF3FFC00,
+  SVEReverseVectorElementsMask = 0xFF3FFC00,
+  REV_z_z = SVEReverseVectorElementsFixed
+};
+
+enum SVEReverseWithinElementsOp {
+  SVEReverseWithinElementsFixed = 0x05248000,
+  SVEReverseWithinElementsFMask = 0xFF3CE000,
+  SVEReverseWithinElementsMask = 0xFF3FE000,
+  REVB_z_z = SVEReverseWithinElementsFixed,
+  REVH_z_z = SVEReverseWithinElementsFixed | 0x00010000,
+  REVW_z_z = SVEReverseWithinElementsFixed | 0x00020000,
+  RBIT_z_p_z = SVEReverseWithinElementsFixed | 0x00030000
+};
+
+enum SVESaturatingIncDecRegisterByElementCountOp {
+  SVESaturatingIncDecRegisterByElementCountFixed = 0x0420F000,
+  SVESaturatingIncDecRegisterByElementCountFMask = 0xFF20F000,
+  SVESaturatingIncDecRegisterByElementCountMask = 0xFFF0FC00,
+  SQINCB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed,
+  UQINCB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000400,
+  SQDECB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000800,
+  UQDECB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000C00,
+  SQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100000,
+  UQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100400,
+  SQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100800,
+  UQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100C00,
+  SQINCH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400000,
+  UQINCH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400400,
+  SQDECH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400800,
+  UQDECH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400C00,
+  SQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500000,
+  UQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500400,
+  SQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500800,
+  UQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500C00,
+  SQINCW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800000,
+  UQINCW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800400,
+  SQDECW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800800,
+  UQDECW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800C00,
+  SQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900000,
+  UQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900400,
+  SQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900800,
+  UQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900C00,
+  SQINCD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00000,
+  UQINCD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00400,
+  SQDECD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00800,
+  UQDECD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00C00,
+  SQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00000,
+  UQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00400,
+  SQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00800,
+  UQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00C00
+};
+
+enum SVESaturatingIncDecVectorByElementCountOp {
+  SVESaturatingIncDecVectorByElementCountFixed = 0x0420C000,
+  SVESaturatingIncDecVectorByElementCountFMask = 0xFF30F000,
+  SVESaturatingIncDecVectorByElementCountMask = 0xFFF0FC00,
+  SQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400000,
+  UQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400400,
+  SQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400800,
+  UQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400C00,
+  SQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800000,
+  UQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800400,
+  SQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800800,
+  UQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800C00,
+  SQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00000,
+  UQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00400,
+  SQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00800,
+  UQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00C00
+};
+
+enum SVEStackFrameAdjustmentOp {
+  SVEStackFrameAdjustmentFixed = 0x04205000,
+  SVEStackFrameAdjustmentFMask = 0xFFA0F800,
+  SVEStackFrameAdjustmentMask = 0xFFE0F800,
+  ADDVL_r_ri = SVEStackFrameAdjustmentFixed,
+  ADDPL_r_ri = SVEStackFrameAdjustmentFixed | 0x00400000
+};
+
+enum SVEStackFrameSizeOp {
+  SVEStackFrameSizeFixed = 0x04BF5000,
+  SVEStackFrameSizeFMask = 0xFFFFF800,
+  SVEStackFrameSizeMask = 0xFFFFF800,
+  RDVL_r_i = SVEStackFrameSizeFixed
+};
+
+enum SVEStoreMultipleStructures_ScalarPlusImmOp {
+  SVEStoreMultipleStructures_ScalarPlusImmFixed = 0xE410E000,
+  SVEStoreMultipleStructures_ScalarPlusImmFMask = 0xFE10E000,
+  SVEStoreMultipleStructures_ScalarPlusImmMask = 0xFFF0E000,
+  ST2B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00200000,
+  ST3B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00400000,
+  ST4B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00600000,
+  ST2H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00A00000,
+  ST3H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00C00000,
+  ST4H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00E00000,
+  ST2W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01200000,
+  ST3W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01400000,
+  ST4W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01600000,
+  ST2D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01A00000,
+  ST3D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01C00000,
+  ST4D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01E00000
+};
+
+enum SVEStoreMultipleStructures_ScalarPlusScalarOp {
+  SVEStoreMultipleStructures_ScalarPlusScalarFixed = 0xE4006000,
+  SVEStoreMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000,
+  SVEStoreMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000,
+  ST2B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00200000,
+  ST3B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00400000,
+  ST4B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00600000,
+  ST2H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00A00000,
+  ST3H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00C00000,
+  ST4H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00E00000,
+  ST2W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01200000,
+  ST3W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01400000,
+  ST4W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01600000,
+  ST2D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01A00000,
+  ST3D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01C00000,
+  ST4D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01E00000
+};
+
+enum SVEStorePredicateRegisterOp {
+  SVEStorePredicateRegisterFixed = 0xE5800000,
+  SVEStorePredicateRegisterFMask = 0xFFC0E010,
+  SVEStorePredicateRegisterMask = 0xFFC0E010,
+  STR_p_bi = SVEStorePredicateRegisterFixed
+};
+
+enum SVEStoreVectorRegisterOp {
+  SVEStoreVectorRegisterFixed = 0xE5804000,
+  SVEStoreVectorRegisterFMask = 0xFFC0E000,
+  SVEStoreVectorRegisterMask = 0xFFC0E000,
+  STR_z_bi = SVEStoreVectorRegisterFixed
+};
+
+enum SVETableLookupOp {
+  SVETableLookupFixed = 0x05203000,
+  SVETableLookupFMask = 0xFF20FC00,
+  SVETableLookupMask = 0xFF20FC00,
+  TBL_z_zz_1 = SVETableLookupFixed
+};
+
+enum SVEUnpackPredicateElementsOp {
+  SVEUnpackPredicateElementsFixed = 0x05304000,
+  SVEUnpackPredicateElementsFMask = 0xFFFEFE10,
+  SVEUnpackPredicateElementsMask = 0xFFFFFE10,
+  PUNPKLO_p_p = SVEUnpackPredicateElementsFixed,
+  PUNPKHI_p_p = SVEUnpackPredicateElementsFixed | 0x00010000
+};
+
+enum SVEUnpackVectorElementsOp {
+  SVEUnpackVectorElementsFixed = 0x05303800,
+  SVEUnpackVectorElementsFMask = 0xFF3CFC00,
+  SVEUnpackVectorElementsMask = 0xFF3FFC00,
+  SUNPKLO_z_z = SVEUnpackVectorElementsFixed,
+  SUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00010000,
+  UUNPKLO_z_z = SVEUnpackVectorElementsFixed | 0x00020000,
+  UUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00030000
+};
+
+enum SVEVectorSelectOp {
+  SVEVectorSelectFixed = 0x0520C000,
+  SVEVectorSelectFMask = 0xFF20C000,
+  SVEVectorSelectMask = 0xFF20C000,
+  SEL_z_p_zz = SVEVectorSelectFixed
+};
+
+enum SVEVectorSplice_DestructiveOp {
+  SVEVectorSplice_DestructiveFixed = 0x052C8000,
+  SVEVectorSplice_DestructiveFMask = 0xFF3FE000,
+  SVEVectorSplice_DestructiveMask = 0xFF3FE000,
+  SPLICE_z_p_zz_des = SVEVectorSplice_DestructiveFixed
+};
+
 enum ReservedOp {
   ReservedFixed = 0x00000000,
   ReservedFMask = 0x1E000000,
   ReservedMask = 0xFFFF0000,
-
   UDF = ReservedFixed | 0x00000000
 };
 
diff --git a/src/aarch64/cpu-aarch64.cc b/src/aarch64/cpu-aarch64.cc
index f5e4fca5..a31e010d 100644
--- a/src/aarch64/cpu-aarch64.cc
+++ b/src/aarch64/cpu-aarch64.cc
@@ -39,10 +39,15 @@ namespace aarch64 {
 
 const IDRegister::Field AA64PFR0::kFP(16, Field::kSigned);
 const IDRegister::Field AA64PFR0::kAdvSIMD(20, Field::kSigned);
+const IDRegister::Field AA64PFR0::kRAS(28);
 const IDRegister::Field AA64PFR0::kSVE(32);
 const IDRegister::Field AA64PFR0::kDIT(48);
+const IDRegister::Field AA64PFR0::kCSV2(56);
+const IDRegister::Field AA64PFR0::kCSV3(60);
 
 const IDRegister::Field AA64PFR1::kBT(0);
+const IDRegister::Field AA64PFR1::kSSBS(4);
+const IDRegister::Field AA64PFR1::kMTE(8);
 
 const IDRegister::Field AA64ISAR0::kAES(4);
 const IDRegister::Field AA64ISAR0::kSHA1(8);
@@ -56,6 +61,7 @@ const IDRegister::Field AA64ISAR0::kSM4(40);
 const IDRegister::Field AA64ISAR0::kDP(44);
 const IDRegister::Field AA64ISAR0::kFHM(48);
 const IDRegister::Field AA64ISAR0::kTS(52);
+const IDRegister::Field AA64ISAR0::kRNDR(60);
 
 const IDRegister::Field AA64ISAR1::kDPB(0);
 const IDRegister::Field AA64ISAR1::kAPA(4);
@@ -68,23 +74,41 @@ const IDRegister::Field AA64ISAR1::kGPI(28);
 const IDRegister::Field AA64ISAR1::kFRINTTS(32);
 const IDRegister::Field AA64ISAR1::kSB(36);
 const IDRegister::Field AA64ISAR1::kSPECRES(40);
+const IDRegister::Field AA64ISAR1::kBF16(44);
+const IDRegister::Field AA64ISAR1::kDGH(48);
+const IDRegister::Field AA64ISAR1::kI8MM(52);
 
 const IDRegister::Field AA64MMFR1::kLO(16);
 
+const IDRegister::Field AA64MMFR2::kAT(32);
+
+const IDRegister::Field AA64ZFR0::kBF16(20);
+const IDRegister::Field AA64ZFR0::kI8MM(44);
+const IDRegister::Field AA64ZFR0::kF32MM(52);
+const IDRegister::Field AA64ZFR0::kF64MM(56);
+
 CPUFeatures AA64PFR0::GetCPUFeatures() const {
   CPUFeatures f;
   if (Get(kFP) >= 0) f.Combine(CPUFeatures::kFP);
   if (Get(kFP) >= 1) f.Combine(CPUFeatures::kFPHalf);
   if (Get(kAdvSIMD) >= 0) f.Combine(CPUFeatures::kNEON);
   if (Get(kAdvSIMD) >= 1) f.Combine(CPUFeatures::kNEONHalf);
+  if (Get(kRAS) >= 1) f.Combine(CPUFeatures::kRAS);
   if (Get(kSVE) >= 1) f.Combine(CPUFeatures::kSVE);
   if (Get(kDIT) >= 1) f.Combine(CPUFeatures::kDIT);
+  if (Get(kCSV2) >= 1) f.Combine(CPUFeatures::kCSV2);
+  if (Get(kCSV2) >= 2) f.Combine(CPUFeatures::kSCXTNUM);
+  if (Get(kCSV3) >= 1) f.Combine(CPUFeatures::kCSV3);
   return f;
 }
 
 CPUFeatures AA64PFR1::GetCPUFeatures() const {
   CPUFeatures f;
   if (Get(kBT) >= 1) f.Combine(CPUFeatures::kBTI);
+  if (Get(kSSBS) >= 1) f.Combine(CPUFeatures::kSSBS);
+  if (Get(kSSBS) >= 2) f.Combine(CPUFeatures::kSSBSControl);
+  if (Get(kMTE) >= 1) f.Combine(CPUFeatures::kMTEInstructions);
+  if (Get(kMTE) >= 2) f.Combine(CPUFeatures::kMTE);
   return f;
 }
 
@@ -105,20 +129,38 @@ CPUFeatures AA64ISAR0::GetCPUFeatures() const {
   if (Get(kFHM) >= 1) f.Combine(CPUFeatures::kFHM);
   if (Get(kTS) >= 1) f.Combine(CPUFeatures::kFlagM);
   if (Get(kTS) >= 2) f.Combine(CPUFeatures::kAXFlag);
+  if (Get(kRNDR) >= 1) f.Combine(CPUFeatures::kRNG);
   return f;
 }
 
 CPUFeatures AA64ISAR1::GetCPUFeatures() const {
   CPUFeatures f;
   if (Get(kDPB) >= 1) f.Combine(CPUFeatures::kDCPoP);
+  if (Get(kDPB) >= 2) f.Combine(CPUFeatures::kDCCVADP);
   if (Get(kJSCVT) >= 1) f.Combine(CPUFeatures::kJSCVT);
   if (Get(kFCMA) >= 1) f.Combine(CPUFeatures::kFcma);
   if (Get(kLRCPC) >= 1) f.Combine(CPUFeatures::kRCpc);
   if (Get(kLRCPC) >= 2) f.Combine(CPUFeatures::kRCpcImm);
   if (Get(kFRINTTS) >= 1) f.Combine(CPUFeatures::kFrintToFixedSizedInt);
+  if (Get(kSB) >= 1) f.Combine(CPUFeatures::kSB);
+  if (Get(kSPECRES) >= 1) f.Combine(CPUFeatures::kSPECRES);
+  if (Get(kBF16) >= 1) f.Combine(CPUFeatures::kBF16);
+  if (Get(kDGH) >= 1) f.Combine(CPUFeatures::kDGH);
+  if (Get(kI8MM) >= 1) f.Combine(CPUFeatures::kI8MM);
+
+  // Only one of these fields should be non-zero, but they have the same
+  // encodings, so merge the logic.
+  int apx = std::max(Get(kAPI), Get(kAPA));
+  if (apx >= 1) {
+    f.Combine(CPUFeatures::kPAuth);
+    // APA (rather than API) indicates QARMA.
+    if (Get(kAPA) >= 1) f.Combine(CPUFeatures::kPAuthQARMA);
+    if (apx == 0b0010) f.Combine(CPUFeatures::kPAuthEnhancedPAC);
+    if (apx >= 0b0011) f.Combine(CPUFeatures::kPAuthEnhancedPAC2);
+    if (apx >= 0b0100) f.Combine(CPUFeatures::kPAuthFPAC);
+    if (apx >= 0b0101) f.Combine(CPUFeatures::kPAuthFPACCombined);
+  }
 
-  if (Get(kAPI) >= 1) f.Combine(CPUFeatures::kPAuth);
-  if (Get(kAPA) >= 1) f.Combine(CPUFeatures::kPAuth, CPUFeatures::kPAuthQARMA);
   if (Get(kGPI) >= 1) f.Combine(CPUFeatures::kPAuthGeneric);
   if (Get(kGPA) >= 1) {
     f.Combine(CPUFeatures::kPAuthGeneric, CPUFeatures::kPAuthGenericQARMA);
@@ -132,6 +174,23 @@ CPUFeatures AA64MMFR1::GetCPUFeatures() const {
   return f;
 }
 
+CPUFeatures AA64MMFR2::GetCPUFeatures() const {
+  CPUFeatures f;
+  if (Get(kAT) >= 1) f.Combine(CPUFeatures::kUSCAT);
+  return f;
+}
+
+CPUFeatures AA64ZFR0::GetCPUFeatures() const {
+  // This register is only available with SVE, but reads-as-zero in its absence,
+  // so it's always safe to read it.
+  CPUFeatures f;
+  if (Get(kF64MM) >= 1) f.Combine(CPUFeatures::kSVEF64MM);
+  if (Get(kF32MM) >= 1) f.Combine(CPUFeatures::kSVEF32MM);
+  if (Get(kI8MM) >= 1) f.Combine(CPUFeatures::kSVEI8MM);
+  if (Get(kBF16) >= 1) f.Combine(CPUFeatures::kSVEBF16);
+  return f;
+}
+
 int IDRegister::Get(IDRegister::Field field) const {
   int msb = field.GetMsb();
   int lsb = field.GetLsb();
@@ -149,7 +208,8 @@ int IDRegister::Get(IDRegister::Field field) const {
 
 CPUFeatures CPU::InferCPUFeaturesFromIDRegisters() {
   CPUFeatures f;
-#define VIXL_COMBINE_ID_REG(NAME) f.Combine(Read##NAME().GetCPUFeatures());
+#define VIXL_COMBINE_ID_REG(NAME, MRS_ARG) \
+  f.Combine(Read##NAME().GetCPUFeatures());
   VIXL_AARCH64_ID_REG_LIST(VIXL_COMBINE_ID_REG)
 #undef VIXL_COMBINE_ID_REG
   return f;
@@ -163,49 +223,73 @@ CPUFeatures CPU::InferCPUFeaturesFromOS(
   // Map each set bit onto a feature. Ideally, we'd use HWCAP_* macros rather
   // than explicit bits, but explicit bits allow us to identify features that
   // the toolchain doesn't know about.
-  static const CPUFeatures::Feature kFeatureBits[] = {
-      // Bits 0-7
-      CPUFeatures::kFP,
-      CPUFeatures::kNEON,
-      CPUFeatures::kNone,  // "EVTSTRM", which VIXL doesn't track.
-      CPUFeatures::kAES,
-      CPUFeatures::kPmull1Q,
-      CPUFeatures::kSHA1,
-      CPUFeatures::kSHA2,
-      CPUFeatures::kCRC32,
-      // Bits 8-15
-      CPUFeatures::kAtomics,
-      CPUFeatures::kFPHalf,
-      CPUFeatures::kNEONHalf,
-      CPUFeatures::kIDRegisterEmulation,
-      CPUFeatures::kRDM,
-      CPUFeatures::kJSCVT,
-      CPUFeatures::kFcma,
-      CPUFeatures::kRCpc,
-      // Bits 16-23
-      CPUFeatures::kDCPoP,
-      CPUFeatures::kSHA3,
-      CPUFeatures::kSM3,
-      CPUFeatures::kSM4,
-      CPUFeatures::kDotProduct,
-      CPUFeatures::kSHA512,
-      CPUFeatures::kSVE,
-      CPUFeatures::kFHM,
-      // Bits 24-27
-      CPUFeatures::kDIT,
-      CPUFeatures::kUSCAT,
-      CPUFeatures::kRCpcImm,
-      CPUFeatures::kFlagM
-      // Bits 28-31 are unassigned.
-  };
-  static const size_t kFeatureBitCount =
-      sizeof(kFeatureBits) / sizeof(kFeatureBits[0]);
-
-  unsigned long auxv = getauxval(AT_HWCAP);  // NOLINT(runtime/int)
-
-  VIXL_STATIC_ASSERT(kFeatureBitCount < (sizeof(auxv) * kBitsPerByte));
-  for (size_t i = 0; i < kFeatureBitCount; i++) {
-    if (auxv & (1UL << i)) features.Combine(kFeatureBits[i]);
+  static const CPUFeatures::Feature kFeatureBits[] =
+      {// Bits 0-7
+       CPUFeatures::kFP,
+       CPUFeatures::kNEON,
+       CPUFeatures::kNone,  // "EVTSTRM", which VIXL doesn't track.
+       CPUFeatures::kAES,
+       CPUFeatures::kPmull1Q,
+       CPUFeatures::kSHA1,
+       CPUFeatures::kSHA2,
+       CPUFeatures::kCRC32,
+       // Bits 8-15
+       CPUFeatures::kAtomics,
+       CPUFeatures::kFPHalf,
+       CPUFeatures::kNEONHalf,
+       CPUFeatures::kIDRegisterEmulation,
+       CPUFeatures::kRDM,
+       CPUFeatures::kJSCVT,
+       CPUFeatures::kFcma,
+       CPUFeatures::kRCpc,
+       // Bits 16-23
+       CPUFeatures::kDCPoP,
+       CPUFeatures::kSHA3,
+       CPUFeatures::kSM3,
+       CPUFeatures::kSM4,
+       CPUFeatures::kDotProduct,
+       CPUFeatures::kSHA512,
+       CPUFeatures::kSVE,
+       CPUFeatures::kFHM,
+       // Bits 24-31
+       CPUFeatures::kDIT,
+       CPUFeatures::kUSCAT,
+       CPUFeatures::kRCpcImm,
+       CPUFeatures::kFlagM,
+       CPUFeatures::kSSBSControl,
+       CPUFeatures::kSB,
+       CPUFeatures::kPAuth,
+       CPUFeatures::kPAuthGeneric,
+       // Bits 32-39
+       CPUFeatures::kDCCVADP,
+       CPUFeatures::kNone,  // "sve2"
+       CPUFeatures::kNone,  // "sveaes"
+       CPUFeatures::kNone,  // "svepmull"
+       CPUFeatures::kNone,  // "svebitperm"
+       CPUFeatures::kNone,  // "svesha3"
+       CPUFeatures::kNone,  // "svesm4"
+       CPUFeatures::kFrintToFixedSizedInt,
+       // Bits 40-47
+       CPUFeatures::kSVEI8MM,
+       CPUFeatures::kSVEF32MM,
+       CPUFeatures::kSVEF64MM,
+       CPUFeatures::kSVEBF16,
+       CPUFeatures::kI8MM,
+       CPUFeatures::kBF16,
+       CPUFeatures::kDGH,
+       CPUFeatures::kRNG,
+       // Bits 48+
+       CPUFeatures::kBTI};
+
+  uint64_t hwcap_low32 = getauxval(AT_HWCAP);
+  uint64_t hwcap_high32 = getauxval(AT_HWCAP2);
+  VIXL_ASSERT(IsUint32(hwcap_low32));
+  VIXL_ASSERT(IsUint32(hwcap_high32));
+  uint64_t hwcap = hwcap_low32 | (hwcap_high32 << 32);
+
+  VIXL_STATIC_ASSERT(ArrayLength(kFeatureBits) < 64);
+  for (size_t i = 0; i < ArrayLength(kFeatureBits); i++) {
+    if (hwcap & (UINT64_C(1) << i)) features.Combine(kFeatureBits[i]);
   }
 #endif  // VIXL_USE_LINUX_HWCAP
 
@@ -218,17 +302,17 @@ CPUFeatures CPU::InferCPUFeaturesFromOS(
 
 
 #ifdef __aarch64__
-#define VIXL_READ_ID_REG(NAME)                         \
-  NAME CPU::Read##NAME() {                             \
-    uint64_t value = 0;                                \
-    __asm__("mrs %0, ID_" #NAME "_EL1" : "=r"(value)); \
-    return NAME(value);                                \
+#define VIXL_READ_ID_REG(NAME, MRS_ARG)        \
+  NAME CPU::Read##NAME() {                     \
+    uint64_t value = 0;                        \
+    __asm__("mrs %0, " MRS_ARG : "=r"(value)); \
+    return NAME(value);                        \
   }
 #else  // __aarch64__
-#define VIXL_READ_ID_REG(NAME)                                        \
-  NAME CPU::Read##NAME() {                                            \
-    /* TODO: Use VIXL_UNREACHABLE once it works in release builds. */ \
-    VIXL_ABORT();                                                     \
+#define VIXL_READ_ID_REG(NAME, MRS_ARG) \
+  NAME CPU::Read##NAME() {              \
+    VIXL_UNREACHABLE();                 \
+    return NAME(0);                     \
   }
 #endif  // __aarch64__
 
@@ -282,6 +366,27 @@ uint32_t CPU::GetCacheType() {
 }
 
 
+// Query the SVE vector length. This requires CPUFeatures::kSVE.
+int CPU::ReadSVEVectorLengthInBits() {
+#ifdef __aarch64__
+  uint64_t vl;
+  // To support compilers that don't understand `rdvl`, encode the value
+  // directly and move it manually.
+  __asm__(
+      "   .word 0x04bf5100\n"  // rdvl x0, #8
+      "   mov %[vl], x0\n"
+      : [vl] "=r"(vl)
+      :
+      : "x0");
+  VIXL_ASSERT(vl <= INT_MAX);
+  return static_cast<int>(vl);
+#else
+  VIXL_UNREACHABLE();
+  return 0;
+#endif
+}
+
+
 void CPU::EnsureIAndDCacheCoherency(void *address, size_t length) {
 #ifdef __aarch64__
   // Implement the cache synchronisation for all targets where AArch64 is the
diff --git a/src/aarch64/cpu-aarch64.h b/src/aarch64/cpu-aarch64.h
index d2b2ee87..2bf1e60f 100644
--- a/src/aarch64/cpu-aarch64.h
+++ b/src/aarch64/cpu-aarch64.h
@@ -56,7 +56,11 @@ class IDRegister {
    public:
     enum Type { kUnsigned, kSigned };
 
-    explicit Field(int lsb, Type type = kUnsigned) : lsb_(lsb), type_(type) {}
+    // This needs to be constexpr so that fields have "constant initialisation".
+    // This avoids initialisation order problems when these values are used to
+    // (dynamically) initialise static variables, etc.
+    explicit constexpr Field(int lsb, Type type = kUnsigned)
+        : lsb_(lsb), type_(type) {}
 
     static const int kMaxWidthInBits = 4;
 
@@ -92,8 +96,11 @@ class AA64PFR0 : public IDRegister {
  private:
   static const Field kFP;
   static const Field kAdvSIMD;
+  static const Field kRAS;
   static const Field kSVE;
   static const Field kDIT;
+  static const Field kCSV2;
+  static const Field kCSV3;
 };
 
 class AA64PFR1 : public IDRegister {
@@ -104,6 +111,8 @@ class AA64PFR1 : public IDRegister {
 
  private:
   static const Field kBT;
+  static const Field kSSBS;
+  static const Field kMTE;
 };
 
 class AA64ISAR0 : public IDRegister {
@@ -125,6 +134,7 @@ class AA64ISAR0 : public IDRegister {
   static const Field kDP;
   static const Field kFHM;
   static const Field kTS;
+  static const Field kRNDR;
 };
 
 class AA64ISAR1 : public IDRegister {
@@ -145,6 +155,9 @@ class AA64ISAR1 : public IDRegister {
   static const Field kFRINTTS;
   static const Field kSB;
   static const Field kSPECRES;
+  static const Field kBF16;
+  static const Field kDGH;
+  static const Field kI8MM;
 };
 
 class AA64MMFR1 : public IDRegister {
@@ -157,6 +170,29 @@ class AA64MMFR1 : public IDRegister {
   static const Field kLO;
 };
 
+class AA64MMFR2 : public IDRegister {
+ public:
+  explicit AA64MMFR2(uint64_t value) : IDRegister(value) {}
+
+  CPUFeatures GetCPUFeatures() const;
+
+ private:
+  static const Field kAT;
+};
+
+class AA64ZFR0 : public IDRegister {
+ public:
+  explicit AA64ZFR0(uint64_t value) : IDRegister(value) {}
+
+  CPUFeatures GetCPUFeatures() const;
+
+ private:
+  static const Field kBF16;
+  static const Field kI8MM;
+  static const Field kF32MM;
+  static const Field kF64MM;
+};
+
 class CPU {
  public:
   // Initialise CPU support.
@@ -184,6 +220,9 @@ class CPU {
       CPUFeatures::QueryIDRegistersOption option =
           CPUFeatures::kQueryIDRegistersIfAvailable);
 
+  // Query the SVE vector length. This requires CPUFeatures::kSVE.
+  static int ReadSVEVectorLengthInBits();
+
   // Handle tagged pointers.
   template <typename T>
   static T SetPointerTag(T pointer, uint64_t tag) {
@@ -211,14 +250,18 @@ class CPU {
   }
 
  private:
-#define VIXL_AARCH64_ID_REG_LIST(V) \
-  V(AA64PFR0)                       \
-  V(AA64PFR1)                       \
-  V(AA64ISAR0)                      \
-  V(AA64ISAR1)                      \
-  V(AA64MMFR1)
-
-#define VIXL_READ_ID_REG(NAME) static NAME Read##NAME();
+#define VIXL_AARCH64_ID_REG_LIST(V)                                           \
+  V(AA64PFR0, "ID_AA64PFR0_EL1")                                              \
+  V(AA64PFR1, "ID_AA64PFR1_EL1")                                              \
+  V(AA64ISAR0, "ID_AA64ISAR0_EL1")                                            \
+  V(AA64ISAR1, "ID_AA64ISAR1_EL1")                                            \
+  V(AA64MMFR1, "ID_AA64MMFR1_EL1")                                            \
+  /* These registers are RES0 in the baseline Arm8.0. We can always safely */ \
+  /* read them, but some compilers don't accept the symbolic names. */        \
+  V(AA64MMFR2, "S3_0_C0_C7_2")                                                \
+  V(AA64ZFR0, "S3_0_C0_C4_4")
+
+#define VIXL_READ_ID_REG(NAME, MRS_ARG) static NAME Read##NAME();
   // On native AArch64 platforms, read the named CPU ID registers. These require
   // CPUFeatures::kIDRegisterEmulation, and should not be called on non-AArch64
   // platforms.
diff --git a/src/aarch64/cpu-features-auditor-aarch64.cc b/src/aarch64/cpu-features-auditor-aarch64.cc
index 474803a1..abe63d39 100644
--- a/src/aarch64/cpu-features-auditor-aarch64.cc
+++ b/src/aarch64/cpu-features-auditor-aarch64.cc
@@ -870,7 +870,6 @@ void CPUFeaturesAuditor::VisitNEONModifiedImmediate(const Instruction* instr) {
     scope.Record(CPUFeatures::kFP);
     if (instr->ExtractBit(11)) scope.Record(CPUFeatures::kNEONHalf);
   }
-  USE(instr);
 }
 
 void CPUFeaturesAuditor::VisitNEONPerm(const Instruction* instr) {
@@ -1068,6 +1067,165 @@ void CPUFeaturesAuditor::VisitPCRelAddressing(const Instruction* instr) {
   USE(instr);
 }
 
+// Most SVE visitors require only SVE.
+#define VIXL_SIMPLE_SVE_VISITOR_LIST(V)                          \
+  V(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets)           \
+  V(SVE32BitGatherLoad_VectorPlusImm)                            \
+  V(SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets)    \
+  V(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets)        \
+  V(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets)         \
+  V(SVE32BitGatherPrefetch_VectorPlusImm)                        \
+  V(SVE32BitScatterStore_ScalarPlus32BitScaledOffsets)           \
+  V(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets)         \
+  V(SVE32BitScatterStore_VectorPlusImm)                          \
+  V(SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets)     \
+  V(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsets)             \
+  V(SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets)           \
+  V(SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets)   \
+  V(SVE64BitGatherLoad_VectorPlusImm)                            \
+  V(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets)         \
+  V(SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets) \
+  V(SVE64BitGatherPrefetch_VectorPlusImm)                        \
+  V(SVE64BitScatterStore_ScalarPlus64BitScaledOffsets)           \
+  V(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets)         \
+  V(SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets)   \
+  V(SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets) \
+  V(SVE64BitScatterStore_VectorPlusImm)                          \
+  V(SVEAddressGeneration)                                        \
+  V(SVEBitwiseLogicalUnpredicated)                               \
+  V(SVEBitwiseShiftUnpredicated)                                 \
+  V(SVEFFRInitialise)                                            \
+  V(SVEFFRWriteFromPredicate)                                    \
+  V(SVEFPAccumulatingReduction)                                  \
+  V(SVEFPArithmeticUnpredicated)                                 \
+  V(SVEFPCompareVectors)                                         \
+  V(SVEFPCompareWithZero)                                        \
+  V(SVEFPComplexAddition)                                        \
+  V(SVEFPComplexMulAdd)                                          \
+  V(SVEFPComplexMulAddIndex)                                     \
+  V(SVEFPFastReduction)                                          \
+  V(SVEFPMulIndex)                                               \
+  V(SVEFPMulAdd)                                                 \
+  V(SVEFPMulAddIndex)                                            \
+  V(SVEFPUnaryOpUnpredicated)                                    \
+  V(SVEIncDecByPredicateCount)                                   \
+  V(SVEIndexGeneration)                                          \
+  V(SVEIntArithmeticUnpredicated)                                \
+  V(SVEIntCompareSignedImm)                                      \
+  V(SVEIntCompareUnsignedImm)                                    \
+  V(SVEIntCompareVectors)                                        \
+  V(SVEIntMulAddPredicated)                                      \
+  V(SVEIntMulAddUnpredicated)                                    \
+  V(SVEIntReduction)                                             \
+  V(SVEIntUnaryArithmeticPredicated)                             \
+  V(SVEMovprfx)                                                  \
+  V(SVEMulIndex)                                                 \
+  V(SVEPermuteVectorExtract)                                     \
+  V(SVEPermuteVectorInterleaving)                                \
+  V(SVEPredicateCount)                                           \
+  V(SVEPredicateLogical)                                         \
+  V(SVEPropagateBreak)                                           \
+  V(SVEStackFrameAdjustment)                                     \
+  V(SVEStackFrameSize)                                           \
+  V(SVEVectorSelect)                                             \
+  V(SVEBitwiseLogical_Predicated)                                \
+  V(SVEBitwiseLogicalWithImm_Unpredicated)                       \
+  V(SVEBitwiseShiftByImm_Predicated)                             \
+  V(SVEBitwiseShiftByVector_Predicated)                          \
+  V(SVEBitwiseShiftByWideElements_Predicated)                    \
+  V(SVEBroadcastBitmaskImm)                                      \
+  V(SVEBroadcastFPImm_Unpredicated)                              \
+  V(SVEBroadcastGeneralRegister)                                 \
+  V(SVEBroadcastIndexElement)                                    \
+  V(SVEBroadcastIntImm_Unpredicated)                             \
+  V(SVECompressActiveElements)                                   \
+  V(SVEConditionallyBroadcastElementToVector)                    \
+  V(SVEConditionallyExtractElementToSIMDFPScalar)                \
+  V(SVEConditionallyExtractElementToGeneralRegister)             \
+  V(SVEConditionallyTerminateScalars)                            \
+  V(SVEConstructivePrefix_Unpredicated)                          \
+  V(SVEContiguousFirstFaultLoad_ScalarPlusScalar)                \
+  V(SVEContiguousLoad_ScalarPlusImm)                             \
+  V(SVEContiguousLoad_ScalarPlusScalar)                          \
+  V(SVEContiguousNonFaultLoad_ScalarPlusImm)                     \
+  V(SVEContiguousNonTemporalLoad_ScalarPlusImm)                  \
+  V(SVEContiguousNonTemporalLoad_ScalarPlusScalar)               \
+  V(SVEContiguousNonTemporalStore_ScalarPlusImm)                 \
+  V(SVEContiguousNonTemporalStore_ScalarPlusScalar)              \
+  V(SVEContiguousPrefetch_ScalarPlusImm)                         \
+  V(SVEContiguousPrefetch_ScalarPlusScalar)                      \
+  V(SVEContiguousStore_ScalarPlusImm)                            \
+  V(SVEContiguousStore_ScalarPlusScalar)                         \
+  V(SVECopySIMDFPScalarRegisterToVector_Predicated)              \
+  V(SVECopyFPImm_Predicated)                                     \
+  V(SVECopyGeneralRegisterToVector_Predicated)                   \
+  V(SVECopyIntImm_Predicated)                                    \
+  V(SVEElementCount)                                             \
+  V(SVEExtractElementToSIMDFPScalarRegister)                     \
+  V(SVEExtractElementToGeneralRegister)                          \
+  V(SVEFPArithmetic_Predicated)                                  \
+  V(SVEFPArithmeticWithImm_Predicated)                           \
+  V(SVEFPConvertPrecision)                                       \
+  V(SVEFPConvertToInt)                                           \
+  V(SVEFPExponentialAccelerator)                                 \
+  V(SVEFPRoundToIntegralValue)                                   \
+  V(SVEFPTrigMulAddCoefficient)                                  \
+  V(SVEFPTrigSelectCoefficient)                                  \
+  V(SVEFPUnaryOp)                                                \
+  V(SVEIncDecRegisterByElementCount)                             \
+  V(SVEIncDecVectorByElementCount)                               \
+  V(SVEInsertSIMDFPScalarRegister)                               \
+  V(SVEInsertGeneralRegister)                                    \
+  V(SVEIntAddSubtractImm_Unpredicated)                           \
+  V(SVEIntAddSubtractVectors_Predicated)                         \
+  V(SVEIntCompareScalarCountAndLimit)                            \
+  V(SVEIntConvertToFP)                                           \
+  V(SVEIntDivideVectors_Predicated)                              \
+  V(SVEIntMinMaxImm_Unpredicated)                                \
+  V(SVEIntMinMaxDifference_Predicated)                           \
+  V(SVEIntMulImm_Unpredicated)                                   \
+  V(SVEIntMulVectors_Predicated)                                 \
+  V(SVELoadAndBroadcastElement)                                  \
+  V(SVELoadAndBroadcastQuadword_ScalarPlusImm)                   \
+  V(SVELoadAndBroadcastQuadword_ScalarPlusScalar)                \
+  V(SVELoadMultipleStructures_ScalarPlusImm)                     \
+  V(SVELoadMultipleStructures_ScalarPlusScalar)                  \
+  V(SVELoadPredicateRegister)                                    \
+  V(SVELoadVectorRegister)                                       \
+  V(SVEPartitionBreakCondition)                                  \
+  V(SVEPermutePredicateElements)                                 \
+  V(SVEPredicateFirstActive)                                     \
+  V(SVEPredicateInitialize)                                      \
+  V(SVEPredicateNextActive)                                      \
+  V(SVEPredicateReadFromFFR_Predicated)                          \
+  V(SVEPredicateReadFromFFR_Unpredicated)                        \
+  V(SVEPredicateTest)                                            \
+  V(SVEPredicateZero)                                            \
+  V(SVEPropagateBreakToNextPartition)                            \
+  V(SVEReversePredicateElements)                                 \
+  V(SVEReverseVectorElements)                                    \
+  V(SVEReverseWithinElements)                                    \
+  V(SVESaturatingIncDecRegisterByElementCount)                   \
+  V(SVESaturatingIncDecVectorByElementCount)                     \
+  V(SVEStoreMultipleStructures_ScalarPlusImm)                    \
+  V(SVEStoreMultipleStructures_ScalarPlusScalar)                 \
+  V(SVEStorePredicateRegister)                                   \
+  V(SVEStoreVectorRegister)                                      \
+  V(SVETableLookup)                                              \
+  V(SVEUnpackPredicateElements)                                  \
+  V(SVEUnpackVectorElements)                                     \
+  V(SVEVectorSplice_Destructive)
+
+#define VIXL_DEFINE_SIMPLE_SVE_VISITOR(NAME)                       \
+  void CPUFeaturesAuditor::Visit##NAME(const Instruction* instr) { \
+    RecordInstructionFeaturesScope scope(this);                    \
+    scope.Record(CPUFeatures::kSVE);                               \
+    USE(instr);                                                    \
+  }
+VIXL_SIMPLE_SVE_VISITOR_LIST(VIXL_DEFINE_SIMPLE_SVE_VISITOR)
+#undef VIXL_DEFINE_SIMPLE_SVE_VISITOR
+#undef VIXL_SIMPLE_SVE_VISITOR_LIST
+
 void CPUFeaturesAuditor::VisitSystem(const Instruction* instr) {
   RecordInstructionFeaturesScope scope(this);
   if (instr->Mask(SystemHintFMask) == SystemHintFixed) {
diff --git a/src/aarch64/decoder-aarch64.cc b/src/aarch64/decoder-aarch64.cc
index ce1f33fb..c6859bbc 100644
--- a/src/aarch64/decoder-aarch64.cc
+++ b/src/aarch64/decoder-aarch64.cc
@@ -182,22 +182,45 @@ BitExtractFn DecodeNode::GetBitExtractFunction(uint32_t mask) {
   case M:                                          \
     bit_extract_fn = &Instruction::ExtractBits<M>; \
     break;
+    INSTANTIATE_TEMPLATE(0x000001e0);
+    INSTANTIATE_TEMPLATE(0x00000400);
     INSTANTIATE_TEMPLATE(0x00000800);
     INSTANTIATE_TEMPLATE(0x00000c00);
+    INSTANTIATE_TEMPLATE(0x00001000);
+    INSTANTIATE_TEMPLATE(0x00001800);
     INSTANTIATE_TEMPLATE(0x00001c00);
     INSTANTIATE_TEMPLATE(0x00004000);
     INSTANTIATE_TEMPLATE(0x00008000);
     INSTANTIATE_TEMPLATE(0x0000f000);
     INSTANTIATE_TEMPLATE(0x0000fc00);
+    INSTANTIATE_TEMPLATE(0x00060010);
+    INSTANTIATE_TEMPLATE(0x00093e00);
+    INSTANTIATE_TEMPLATE(0x000c1000);
+    INSTANTIATE_TEMPLATE(0x00100000);
+    INSTANTIATE_TEMPLATE(0x00101800);
+    INSTANTIATE_TEMPLATE(0x00140000);
+    INSTANTIATE_TEMPLATE(0x00180000);
+    INSTANTIATE_TEMPLATE(0x00181000);
+    INSTANTIATE_TEMPLATE(0x00190000);
+    INSTANTIATE_TEMPLATE(0x00191400);
+    INSTANTIATE_TEMPLATE(0x001c0000);
+    INSTANTIATE_TEMPLATE(0x001c1800);
     INSTANTIATE_TEMPLATE(0x001f0000);
     INSTANTIATE_TEMPLATE(0x0020fc00);
     INSTANTIATE_TEMPLATE(0x0038f000);
     INSTANTIATE_TEMPLATE(0x00400000);
+    INSTANTIATE_TEMPLATE(0x00400010);
     INSTANTIATE_TEMPLATE(0x0040f000);
+    INSTANTIATE_TEMPLATE(0x00500000);
     INSTANTIATE_TEMPLATE(0x00800000);
+    INSTANTIATE_TEMPLATE(0x00800010);
+    INSTANTIATE_TEMPLATE(0x00801800);
+    INSTANTIATE_TEMPLATE(0x009f0000);
     INSTANTIATE_TEMPLATE(0x00c00000);
+    INSTANTIATE_TEMPLATE(0x00c00010);
     INSTANTIATE_TEMPLATE(0x00cf8000);
     INSTANTIATE_TEMPLATE(0x00db0000);
+    INSTANTIATE_TEMPLATE(0x00dc0000);
     INSTANTIATE_TEMPLATE(0x00e00003);
     INSTANTIATE_TEMPLATE(0x00f80400);
     INSTANTIATE_TEMPLATE(0x01e00000);
@@ -233,6 +256,7 @@ BitExtractFn DecodeNode::GetBitExtractFunction(uint32_t mask) {
     INSTANTIATE_TEMPLATE(0xc4400000);
     INSTANTIATE_TEMPLATE(0xc4c00000);
     INSTANTIATE_TEMPLATE(0xe0400000);
+    INSTANTIATE_TEMPLATE(0xe120e000);
     INSTANTIATE_TEMPLATE(0xe3c00000);
     INSTANTIATE_TEMPLATE(0xf1200000);
 #undef INSTANTIATE_TEMPLATE
@@ -259,20 +283,44 @@ BitExtractFn DecodeNode::GetBitExtractFunction(uint32_t mask, uint32_t value) {
     instantiated = true;                                \
   }
   INSTANTIATE_TEMPLATE(0x0000001c, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00000210, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x000003c0, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00001c00, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00001c0f, 0x00000000);
   INSTANTIATE_TEMPLATE(0x00003000, 0x00000000);
   INSTANTIATE_TEMPLATE(0x00007800, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x0000e000, 0x0000a000);
   INSTANTIATE_TEMPLATE(0x0000f000, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00030400, 0x00000000);
   INSTANTIATE_TEMPLATE(0x0003801f, 0x0000000d);
+  INSTANTIATE_TEMPLATE(0x00060210, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00060810, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00060a10, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00060bf0, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00061e10, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00061e10, 0x00000400);
+  INSTANTIATE_TEMPLATE(0x00070200, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x000b1e10, 0x00000000);
   INSTANTIATE_TEMPLATE(0x000f0000, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00130e1f, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00130fff, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00180000, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00180000, 0x00100000);
+  INSTANTIATE_TEMPLATE(0x001e0000, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x001f0000, 0x00000000);
   INSTANTIATE_TEMPLATE(0x001f0000, 0x001f0000);
   INSTANTIATE_TEMPLATE(0x0038e000, 0x00000000);
   INSTANTIATE_TEMPLATE(0x0039e000, 0x00002000);
   INSTANTIATE_TEMPLATE(0x003ae000, 0x00002000);
   INSTANTIATE_TEMPLATE(0x003ce000, 0x00042000);
+  INSTANTIATE_TEMPLATE(0x005f0000, 0x001f0000);
   INSTANTIATE_TEMPLATE(0x00780000, 0x00000000);
+  INSTANTIATE_TEMPLATE(0x00870210, 0x00000000);
   INSTANTIATE_TEMPLATE(0x00c00000, 0x00000000);
   INSTANTIATE_TEMPLATE(0x00c00000, 0x00800000);
   INSTANTIATE_TEMPLATE(0x00c00000, 0x00c00000);
+  INSTANTIATE_TEMPLATE(0x00c00010, 0x00800000);
+  INSTANTIATE_TEMPLATE(0x00ca1e10, 0x00000000);
   INSTANTIATE_TEMPLATE(0x01000010, 0x00000000);
   INSTANTIATE_TEMPLATE(0x20000800, 0x00000000);
   INSTANTIATE_TEMPLATE(0x20008000, 0x00000000);
@@ -312,14 +360,16 @@ BitExtractFn DecodeNode::GetBitExtractFunction(uint32_t mask, uint32_t value) {
 bool DecodeNode::TryCompileOptimisedDecodeTable(Decoder* decoder) {
   // EitherOr optimisation: if there are only one or two patterns in the table,
   // try to optimise the node to exploit that.
-  if ((pattern_table_.size() == 2) && (GetSampledBitsCount() > 1)) {
+  size_t table_size = pattern_table_.size();
+  if ((table_size <= 2) && (GetSampledBitsCount() > 1)) {
     // TODO: support 'x' in this optimisation by dropping the sampled bit
     // positions before making the mask/value.
     if ((strchr(pattern_table_[0].pattern, 'x') == NULL) &&
-        (strcmp(pattern_table_[1].pattern, "otherwise") == 0)) {
+        ((table_size == 1) ||
+         (strcmp(pattern_table_[1].pattern, "otherwise") == 0))) {
       // A pattern table consisting of a fixed pattern with no x's, and an
-      // "otherwise" case. Optimise this into an instruction mask and value
-      // test.
+      // "otherwise" or absent case. Optimise this into an instruction mask and
+      // value test.
       uint32_t single_decode_mask = 0;
       uint32_t single_decode_value = 0;
       std::vector<uint8_t> bits = GetSampledBits();
@@ -332,7 +382,6 @@ bool DecodeNode::TryCompileOptimisedDecodeTable(Decoder* decoder) {
           single_decode_value |= 1U << bits[i];
         }
       }
-
       BitExtractFn bit_extract_fn =
           GetBitExtractFunction(single_decode_mask, single_decode_value);
 
@@ -342,7 +391,9 @@ bool DecodeNode::TryCompileOptimisedDecodeTable(Decoder* decoder) {
 
       // Set DecodeNode for when the instruction after masking doesn't match the
       // value.
-      CompileNodeForBits(decoder, pattern_table_[1].handler, 0);
+      const char* doesnt_match_handler =
+          (table_size == 1) ? "VisitUnallocated" : pattern_table_[1].handler;
+      CompileNodeForBits(decoder, doesnt_match_handler, 0);
 
       // Set DecodeNode for when it does match.
       CompileNodeForBits(decoder, pattern_table_[0].handler, 1);
diff --git a/src/aarch64/decoder-aarch64.h b/src/aarch64/decoder-aarch64.h
index c0f47c36..38540195 100644
--- a/src/aarch64/decoder-aarch64.h
+++ b/src/aarch64/decoder-aarch64.h
@@ -38,99 +38,239 @@
 
 // List macro containing all visitors needed by the decoder class.
 
-#define VISITOR_LIST_THAT_RETURN(V)     \
-  V(AddSubExtended)                     \
-  V(AddSubImmediate)                    \
-  V(AddSubShifted)                      \
-  V(AddSubWithCarry)                    \
-  V(AtomicMemory)                       \
-  V(Bitfield)                           \
-  V(CompareBranch)                      \
-  V(ConditionalBranch)                  \
-  V(ConditionalCompareImmediate)        \
-  V(ConditionalCompareRegister)         \
-  V(ConditionalSelect)                  \
-  V(Crypto2RegSHA)                      \
-  V(Crypto3RegSHA)                      \
-  V(CryptoAES)                          \
-  V(DataProcessing1Source)              \
-  V(DataProcessing2Source)              \
-  V(DataProcessing3Source)              \
-  V(Exception)                          \
-  V(Extract)                            \
-  V(EvaluateIntoFlags)                  \
-  V(FPCompare)                          \
-  V(FPConditionalCompare)               \
-  V(FPConditionalSelect)                \
-  V(FPDataProcessing1Source)            \
-  V(FPDataProcessing2Source)            \
-  V(FPDataProcessing3Source)            \
-  V(FPFixedPointConvert)                \
-  V(FPImmediate)                        \
-  V(FPIntegerConvert)                   \
-  V(LoadLiteral)                        \
-  V(LoadStoreExclusive)                 \
-  V(LoadStorePAC)                       \
-  V(LoadStorePairNonTemporal)           \
-  V(LoadStorePairOffset)                \
-  V(LoadStorePairPostIndex)             \
-  V(LoadStorePairPreIndex)              \
-  V(LoadStorePostIndex)                 \
-  V(LoadStorePreIndex)                  \
-  V(LoadStoreRCpcUnscaledOffset)        \
-  V(LoadStoreRegisterOffset)            \
-  V(LoadStoreUnscaledOffset)            \
-  V(LoadStoreUnsignedOffset)            \
-  V(LogicalImmediate)                   \
-  V(LogicalShifted)                     \
-  V(MoveWideImmediate)                  \
-  V(NEON2RegMisc)                       \
-  V(NEON2RegMiscFP16)                   \
-  V(NEON3Different)                     \
-  V(NEON3Same)                          \
-  V(NEON3SameExtra)                     \
-  V(NEON3SameFP16)                      \
-  V(NEONAcrossLanes)                    \
-  V(NEONByIndexedElement)               \
-  V(NEONCopy)                           \
-  V(NEONExtract)                        \
-  V(NEONLoadStoreMultiStruct)           \
-  V(NEONLoadStoreMultiStructPostIndex)  \
-  V(NEONLoadStoreSingleStruct)          \
-  V(NEONLoadStoreSingleStructPostIndex) \
-  V(NEONModifiedImmediate)              \
-  V(NEONPerm)                           \
-  V(NEONScalar2RegMisc)                 \
-  V(NEONScalar2RegMiscFP16)             \
-  V(NEONScalar3Diff)                    \
-  V(NEONScalar3Same)                    \
-  V(NEONScalar3SameExtra)               \
-  V(NEONScalar3SameFP16)                \
-  V(NEONScalarByIndexedElement)         \
-  V(NEONScalarCopy)                     \
-  V(NEONScalarPairwise)                 \
-  V(NEONScalarShiftImmediate)           \
-  V(NEONShiftImmediate)                 \
-  V(NEONTable)                          \
-  V(PCRelAddressing)                    \
-  V(RotateRightIntoFlags)               \
-  V(System)                             \
-  V(TestBranch)                         \
-  V(UnconditionalBranch)                \
-  V(UnconditionalBranchToRegister)
-
-// TODO: We shouldn't expose debug-only behaviour like this. Instead, we should
-// use release-mode aborts where appropriate, and merge thse into a single
-// no-return list.
-#define VISITOR_LIST_THAT_DONT_RETURN_IN_DEBUG_MODE(V) \
-  V(Unallocated)                                       \
+#define VISITOR_LIST_THAT_RETURN(V)                              \
+  V(AddSubExtended)                                              \
+  V(AddSubImmediate)                                             \
+  V(AddSubShifted)                                               \
+  V(AddSubWithCarry)                                             \
+  V(AtomicMemory)                                                \
+  V(Bitfield)                                                    \
+  V(CompareBranch)                                               \
+  V(ConditionalBranch)                                           \
+  V(ConditionalCompareImmediate)                                 \
+  V(ConditionalCompareRegister)                                  \
+  V(ConditionalSelect)                                           \
+  V(Crypto2RegSHA)                                               \
+  V(Crypto3RegSHA)                                               \
+  V(CryptoAES)                                                   \
+  V(DataProcessing1Source)                                       \
+  V(DataProcessing2Source)                                       \
+  V(DataProcessing3Source)                                       \
+  V(EvaluateIntoFlags)                                           \
+  V(Exception)                                                   \
+  V(Extract)                                                     \
+  V(FPCompare)                                                   \
+  V(FPConditionalCompare)                                        \
+  V(FPConditionalSelect)                                         \
+  V(FPDataProcessing1Source)                                     \
+  V(FPDataProcessing2Source)                                     \
+  V(FPDataProcessing3Source)                                     \
+  V(FPFixedPointConvert)                                         \
+  V(FPImmediate)                                                 \
+  V(FPIntegerConvert)                                            \
+  V(LoadLiteral)                                                 \
+  V(LoadStoreExclusive)                                          \
+  V(LoadStorePAC)                                                \
+  V(LoadStorePairNonTemporal)                                    \
+  V(LoadStorePairOffset)                                         \
+  V(LoadStorePairPostIndex)                                      \
+  V(LoadStorePairPreIndex)                                       \
+  V(LoadStorePostIndex)                                          \
+  V(LoadStorePreIndex)                                           \
+  V(LoadStoreRCpcUnscaledOffset)                                 \
+  V(LoadStoreRegisterOffset)                                     \
+  V(LoadStoreUnscaledOffset)                                     \
+  V(LoadStoreUnsignedOffset)                                     \
+  V(LogicalImmediate)                                            \
+  V(LogicalShifted)                                              \
+  V(MoveWideImmediate)                                           \
+  V(NEON2RegMisc)                                                \
+  V(NEON2RegMiscFP16)                                            \
+  V(NEON3Different)                                              \
+  V(NEON3Same)                                                   \
+  V(NEON3SameExtra)                                              \
+  V(NEON3SameFP16)                                               \
+  V(NEONAcrossLanes)                                             \
+  V(NEONByIndexedElement)                                        \
+  V(NEONCopy)                                                    \
+  V(NEONExtract)                                                 \
+  V(NEONLoadStoreMultiStruct)                                    \
+  V(NEONLoadStoreMultiStructPostIndex)                           \
+  V(NEONLoadStoreSingleStruct)                                   \
+  V(NEONLoadStoreSingleStructPostIndex)                          \
+  V(NEONModifiedImmediate)                                       \
+  V(NEONPerm)                                                    \
+  V(NEONScalar2RegMisc)                                          \
+  V(NEONScalar2RegMiscFP16)                                      \
+  V(NEONScalar3Diff)                                             \
+  V(NEONScalar3Same)                                             \
+  V(NEONScalar3SameExtra)                                        \
+  V(NEONScalar3SameFP16)                                         \
+  V(NEONScalarByIndexedElement)                                  \
+  V(NEONScalarCopy)                                              \
+  V(NEONScalarPairwise)                                          \
+  V(NEONScalarShiftImmediate)                                    \
+  V(NEONShiftImmediate)                                          \
+  V(NEONTable)                                                   \
+  V(PCRelAddressing)                                             \
+  V(RotateRightIntoFlags)                                        \
+  V(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets)           \
+  V(SVE32BitGatherLoad_VectorPlusImm)                            \
+  V(SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets)    \
+  V(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets)        \
+  V(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets)         \
+  V(SVE32BitGatherPrefetch_VectorPlusImm)                        \
+  V(SVE32BitScatterStore_ScalarPlus32BitScaledOffsets)           \
+  V(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets)         \
+  V(SVE32BitScatterStore_VectorPlusImm)                          \
+  V(SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets)     \
+  V(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsets)             \
+  V(SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets)           \
+  V(SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets)   \
+  V(SVE64BitGatherLoad_VectorPlusImm)                            \
+  V(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets)         \
+  V(SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets) \
+  V(SVE64BitGatherPrefetch_VectorPlusImm)                        \
+  V(SVE64BitScatterStore_ScalarPlus64BitScaledOffsets)           \
+  V(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets)         \
+  V(SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets)   \
+  V(SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets) \
+  V(SVE64BitScatterStore_VectorPlusImm)                          \
+  V(SVEAddressGeneration)                                        \
+  V(SVEBitwiseLogicalUnpredicated)                               \
+  V(SVEBitwiseShiftUnpredicated)                                 \
+  V(SVEFFRInitialise)                                            \
+  V(SVEFFRWriteFromPredicate)                                    \
+  V(SVEFPAccumulatingReduction)                                  \
+  V(SVEFPArithmeticUnpredicated)                                 \
+  V(SVEFPCompareVectors)                                         \
+  V(SVEFPCompareWithZero)                                        \
+  V(SVEFPComplexAddition)                                        \
+  V(SVEFPComplexMulAdd)                                          \
+  V(SVEFPComplexMulAddIndex)                                     \
+  V(SVEFPFastReduction)                                          \
+  V(SVEFPMulIndex)                                               \
+  V(SVEFPMulAdd)                                                 \
+  V(SVEFPMulAddIndex)                                            \
+  V(SVEFPUnaryOpUnpredicated)                                    \
+  V(SVEIncDecByPredicateCount)                                   \
+  V(SVEIndexGeneration)                                          \
+  V(SVEIntArithmeticUnpredicated)                                \
+  V(SVEIntCompareSignedImm)                                      \
+  V(SVEIntCompareUnsignedImm)                                    \
+  V(SVEIntCompareVectors)                                        \
+  V(SVEIntMulAddPredicated)                                      \
+  V(SVEIntMulAddUnpredicated)                                    \
+  V(SVEIntReduction)                                             \
+  V(SVEIntUnaryArithmeticPredicated)                             \
+  V(SVEMovprfx)                                                  \
+  V(SVEMulIndex)                                                 \
+  V(SVEPermuteVectorExtract)                                     \
+  V(SVEPermuteVectorInterleaving)                                \
+  V(SVEPredicateCount)                                           \
+  V(SVEPredicateLogical)                                         \
+  V(SVEPropagateBreak)                                           \
+  V(SVEStackFrameAdjustment)                                     \
+  V(SVEStackFrameSize)                                           \
+  V(SVEVectorSelect)                                             \
+  V(SVEBitwiseLogical_Predicated)                                \
+  V(SVEBitwiseLogicalWithImm_Unpredicated)                       \
+  V(SVEBitwiseShiftByImm_Predicated)                             \
+  V(SVEBitwiseShiftByVector_Predicated)                          \
+  V(SVEBitwiseShiftByWideElements_Predicated)                    \
+  V(SVEBroadcastBitmaskImm)                                      \
+  V(SVEBroadcastFPImm_Unpredicated)                              \
+  V(SVEBroadcastGeneralRegister)                                 \
+  V(SVEBroadcastIndexElement)                                    \
+  V(SVEBroadcastIntImm_Unpredicated)                             \
+  V(SVECompressActiveElements)                                   \
+  V(SVEConditionallyBroadcastElementToVector)                    \
+  V(SVEConditionallyExtractElementToSIMDFPScalar)                \
+  V(SVEConditionallyExtractElementToGeneralRegister)             \
+  V(SVEConditionallyTerminateScalars)                            \
+  V(SVEConstructivePrefix_Unpredicated)                          \
+  V(SVEContiguousFirstFaultLoad_ScalarPlusScalar)                \
+  V(SVEContiguousLoad_ScalarPlusImm)                             \
+  V(SVEContiguousLoad_ScalarPlusScalar)                          \
+  V(SVEContiguousNonFaultLoad_ScalarPlusImm)                     \
+  V(SVEContiguousNonTemporalLoad_ScalarPlusImm)                  \
+  V(SVEContiguousNonTemporalLoad_ScalarPlusScalar)               \
+  V(SVEContiguousNonTemporalStore_ScalarPlusImm)                 \
+  V(SVEContiguousNonTemporalStore_ScalarPlusScalar)              \
+  V(SVEContiguousPrefetch_ScalarPlusImm)                         \
+  V(SVEContiguousPrefetch_ScalarPlusScalar)                      \
+  V(SVEContiguousStore_ScalarPlusImm)                            \
+  V(SVEContiguousStore_ScalarPlusScalar)                         \
+  V(SVECopySIMDFPScalarRegisterToVector_Predicated)              \
+  V(SVECopyFPImm_Predicated)                                     \
+  V(SVECopyGeneralRegisterToVector_Predicated)                   \
+  V(SVECopyIntImm_Predicated)                                    \
+  V(SVEElementCount)                                             \
+  V(SVEExtractElementToSIMDFPScalarRegister)                     \
+  V(SVEExtractElementToGeneralRegister)                          \
+  V(SVEFPArithmetic_Predicated)                                  \
+  V(SVEFPArithmeticWithImm_Predicated)                           \
+  V(SVEFPConvertPrecision)                                       \
+  V(SVEFPConvertToInt)                                           \
+  V(SVEFPExponentialAccelerator)                                 \
+  V(SVEFPRoundToIntegralValue)                                   \
+  V(SVEFPTrigMulAddCoefficient)                                  \
+  V(SVEFPTrigSelectCoefficient)                                  \
+  V(SVEFPUnaryOp)                                                \
+  V(SVEIncDecRegisterByElementCount)                             \
+  V(SVEIncDecVectorByElementCount)                               \
+  V(SVEInsertSIMDFPScalarRegister)                               \
+  V(SVEInsertGeneralRegister)                                    \
+  V(SVEIntAddSubtractImm_Unpredicated)                           \
+  V(SVEIntAddSubtractVectors_Predicated)                         \
+  V(SVEIntCompareScalarCountAndLimit)                            \
+  V(SVEIntConvertToFP)                                           \
+  V(SVEIntDivideVectors_Predicated)                              \
+  V(SVEIntMinMaxImm_Unpredicated)                                \
+  V(SVEIntMinMaxDifference_Predicated)                           \
+  V(SVEIntMulImm_Unpredicated)                                   \
+  V(SVEIntMulVectors_Predicated)                                 \
+  V(SVELoadAndBroadcastElement)                                  \
+  V(SVELoadAndBroadcastQuadword_ScalarPlusImm)                   \
+  V(SVELoadAndBroadcastQuadword_ScalarPlusScalar)                \
+  V(SVELoadMultipleStructures_ScalarPlusImm)                     \
+  V(SVELoadMultipleStructures_ScalarPlusScalar)                  \
+  V(SVELoadPredicateRegister)                                    \
+  V(SVELoadVectorRegister)                                       \
+  V(SVEPartitionBreakCondition)                                  \
+  V(SVEPermutePredicateElements)                                 \
+  V(SVEPredicateFirstActive)                                     \
+  V(SVEPredicateInitialize)                                      \
+  V(SVEPredicateNextActive)                                      \
+  V(SVEPredicateReadFromFFR_Predicated)                          \
+  V(SVEPredicateReadFromFFR_Unpredicated)                        \
+  V(SVEPredicateTest)                                            \
+  V(SVEPredicateZero)                                            \
+  V(SVEPropagateBreakToNextPartition)                            \
+  V(SVEReversePredicateElements)                                 \
+  V(SVEReverseVectorElements)                                    \
+  V(SVEReverseWithinElements)                                    \
+  V(SVESaturatingIncDecRegisterByElementCount)                   \
+  V(SVESaturatingIncDecVectorByElementCount)                     \
+  V(SVEStoreMultipleStructures_ScalarPlusImm)                    \
+  V(SVEStoreMultipleStructures_ScalarPlusScalar)                 \
+  V(SVEStorePredicateRegister)                                   \
+  V(SVEStoreVectorRegister)                                      \
+  V(SVETableLookup)                                              \
+  V(SVEUnpackPredicateElements)                                  \
+  V(SVEUnpackVectorElements)                                     \
+  V(SVEVectorSplice_Destructive)                                 \
+  V(System)                                                      \
+  V(TestBranch)                                                  \
+  V(Unallocated)                                                 \
+  V(UnconditionalBranch)                                         \
+  V(UnconditionalBranchToRegister)                               \
   V(Unimplemented)
 
 #define VISITOR_LIST_THAT_DONT_RETURN(V) V(Reserved)
 
-#define VISITOR_LIST(V)                          \
-  VISITOR_LIST_THAT_RETURN(V)                    \
-  VISITOR_LIST_THAT_DONT_RETURN_IN_DEBUG_MODE(V) \
+#define VISITOR_LIST(V)       \
+  VISITOR_LIST_THAT_RETURN(V) \
   VISITOR_LIST_THAT_DONT_RETURN(V)
 
 namespace vixl {
@@ -138,6 +278,12 @@ namespace aarch64 {
 
 // The Visitor interface. Disassembler and simulator (and other tools)
 // must provide implementations for all of these functions.
+//
+// Note that this class must change in breaking ways with even minor additions
+// to VIXL, and so its API should be considered unstable. User classes that
+// inherit from this one should be expected to break even on minor version
+// updates. If this is a problem, consider using DecoderVisitorWithDefaults
+// instead.
 class DecoderVisitor {
  public:
   enum VisitorConstness { kConstVisitor, kNonConstVisitor };
@@ -160,6 +306,25 @@ class DecoderVisitor {
   const VisitorConstness constness_;
 };
 
+// As above, but a default (no-op) implementation for each visitor is provided.
+// This is useful for derived class that only care about specific visitors.
+//
+// A minor version update may add a visitor, but will never remove one, so it is
+// safe (and recommended) to use `override` in derived classes.
+class DecoderVisitorWithDefaults : public DecoderVisitor {
+ public:
+  explicit DecoderVisitorWithDefaults(
+      VisitorConstness constness = kConstVisitor)
+      : DecoderVisitor(constness) {}
+
+  virtual ~DecoderVisitorWithDefaults() {}
+
+#define DECLARE(A) \
+  virtual void Visit##A(const Instruction* instr) VIXL_OVERRIDE { USE(instr); }
+  VISITOR_LIST(DECLARE)
+#undef DECLARE
+};
+
 class DecodeNode;
 class CompiledDecodeNode;
 
@@ -257,7 +422,7 @@ class Decoder {
 };
 
 const int kMaxDecodeSampledBits = 16;
-const int kMaxDecodeMappings = 22;
+const int kMaxDecodeMappings = 100;
 typedef void (Decoder::*DecodeFnPtr)(const Instruction*);
 typedef uint32_t (Instruction::*BitExtractFn)(void) const;
 
diff --git a/src/aarch64/decoder-constants-aarch64.h b/src/aarch64/decoder-constants-aarch64.h
index def27fa1..53f283bb 100644
--- a/src/aarch64/decoder-constants-aarch64.h
+++ b/src/aarch64/decoder-constants-aarch64.h
@@ -39,6 +39,7 @@ static const DecodeMapping kDecodeMapping[] = {
   { "Root",
     {28, 27, 26, 25},
     { {"0000", "DecodeReserved"},
+      {"0010", "DecodeSVE"},
       {"100x", "DecodeDataProcessingImmediate"},
       {"101x", "DecodeBranchesExceptionAndSystem"},
       {"x1x0", "DecodeLoadsAndStores"},
@@ -124,6 +125,720 @@ static const DecodeMapping kDecodeMapping[] = {
     },
   },
 
+  { "DecodeSVE",
+    {31, 30, 29, 24, 21, 15, 14, 13},
+    { {"00000x1x", "VisitSVEIntMulAddPredicated"},
+      {"00000000", "DecodeSVE00000000"},
+      {"00000001", "DecodeSVE00000001"},
+      {"00000100", "DecodeSVE00000100"},
+      {"00000101", "VisitSVEIntUnaryArithmeticPredicated"},
+      {"00001000", "VisitSVEIntArithmeticUnpredicated"},
+      {"00001001", "VisitSVEBitwiseLogicalUnpredicated"},
+      {"00001010", "DecodeSVE00001010"},
+      {"00001100", "VisitSVEBitwiseShiftUnpredicated"},
+      {"00001101", "DecodeSVE00001101"},
+      {"00001110", "DecodeSVE00001110"},
+      {"00001111", "DecodeSVE00001111"},
+      {"000100xx", "DecodeSVE000100xx"},
+      {"0001010x", "DecodeSVE0001010x"},
+      {"00010110", "DecodeSVE00010110"},
+      {"00010111", "DecodeSVE00010111"},
+      {"00011000", "VisitSVEPermuteVectorExtract"},
+      {"00011001", "DecodeSVE00011001"},
+      {"00011010", "DecodeSVE00011010"},
+      {"00011011", "VisitSVEPermuteVectorInterleaving"},
+      {"00011100", "DecodeSVE00011100"},
+      {"00011101", "DecodeSVE00011101"},
+      {"0001111x", "VisitSVEVectorSelect"},
+      {"00100xxx", "VisitSVEIntCompareVectors"},
+      {"00101xxx", "VisitSVEIntCompareUnsignedImm"},
+      {"00110x0x", "VisitSVEIntCompareSignedImm"},
+      {"0011001x", "DecodeSVE0011001x"},
+      {"00110110", "DecodeSVE00110110"},
+      {"00110111", "DecodeSVE00110111"},
+      {"00111000", "VisitSVEIntCompareScalarCountAndLimit"},
+      {"00111001", "UnallocSVEConditionallyTerminateScalars"},
+      {"00111100", "DecodeSVE00111100"},
+      {"00111101", "UnallocSVEPredicateCount"},
+      {"0011111x", "DecodeSVE0011111x"},
+      {"010000xx", "VisitSVEIntMulAddUnpredicated"},
+      {"01001xxx", "VisitSVEMulIndex"},
+      {"011000xx", "VisitSVEFPComplexMulAdd"},
+      {"01100100", "UnallocSVEFPComplexAddition"},
+      {"01101000", "DecodeSVE01101000"},
+      {"01101001", "UnallocSVEFPMulIndex"},
+      {"01110x1x", "VisitSVEFPCompareVectors"},
+      {"01110000", "VisitSVEFPArithmeticUnpredicated"},
+      {"01110001", "DecodeSVE01110001"},
+      {"01110100", "DecodeSVE01110100"},
+      {"01110101", "DecodeSVE01110101"},
+      {"01111xxx", "VisitSVEFPMulAdd"},
+      {"100x010x", "UnallocSVELoadAndBroadcastElement"},
+      {"100x0110", "DecodeSVE100x0110"},
+      {"100x0111", "DecodeSVE100x0111"},
+      {"100x11xx", "DecodeSVE100x11xx"},
+      {"100000xx", "VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets"},
+      {"100010xx", "DecodeSVE100010xx"},
+      {"100100x1", "DecodeSVE100100x1"},
+      {"10010000", "DecodeSVE10010000"},
+      {"10010010", "DecodeSVE10010010"},
+      {"100110x1", "DecodeSVE100110x1"},
+      {"10011000", "DecodeSVE10011000"},
+      {"10011010", "DecodeSVE10011010"},
+      {"101xx000", "VisitSVELoadAndBroadcastQuadword_ScalarPlusScalar"},
+      {"101xx001", "UnallocSVELoadAndBroadcastQuadword_ScalarPlusImm"},
+      {"101xx010", "VisitSVEContiguousLoad_ScalarPlusScalar"},
+      {"101xx011", "VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar"},
+      {"101xx101", "DecodeSVE101xx101"},
+      {"101x0110", "DecodeSVE101x0110"},
+      {"101x0111", "DecodeSVE101x0111"},
+      {"101x1110", "VisitSVELoadMultipleStructures_ScalarPlusScalar"},
+      {"101x1111", "DecodeSVE101x1111"},
+      {"110x00xx", "VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets"},
+      {"110x0111", "DecodeSVE110x0111"},
+      {"1100010x", "UnallocSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+      {"11000110", "UnallocSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+      {"110010xx", "DecodeSVE110010xx"},
+      {"110011xx", "DecodeSVE110011xx"},
+      {"1101010x", "UnallocSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+      {"11010110", "UnallocSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+      {"110110xx", "VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets"},
+      {"110111xx", "DecodeSVE110111xx"},
+      {"111x0011", "DecodeSVE111x0011"},
+      {"111x01x0", "DecodeSVE111x01x0"},
+      {"111x0101", "DecodeSVE111x0101"},
+      {"111x0111", "DecodeSVE111x0111"},
+      {"111x1011", "VisitSVEStoreMultipleStructures_ScalarPlusScalar"},
+      {"111x11x0", "DecodeSVE111x11x0"},
+      {"111x1101", "DecodeSVE111x1101"},
+      {"111x1111", "DecodeSVE111x1111"},
+      {"1110x010", "VisitSVEContiguousStore_ScalarPlusScalar"},
+      {"1111x000", "UnallocSVEStorePredicateRegister"},
+      {"1111x010", "DecodeSVE1111x010"},
+    },
+  },
+
+  { "DecodeSVE00000000",
+    {20, 19, 18},
+    { {"00x", "VisitSVEIntAddSubtractVectors_Predicated"},
+      {"01x", "VisitSVEIntMinMaxDifference_Predicated"},
+      {"100", "VisitSVEIntMulVectors_Predicated"},
+      {"101", "VisitSVEIntDivideVectors_Predicated"},
+      {"11x", "VisitSVEBitwiseLogical_Predicated"},
+    },
+  },
+
+  { "DecodeSVE00000100",
+    {20, 19},
+    { {"0x", "VisitSVEBitwiseShiftByImm_Predicated"},
+      {"10", "VisitSVEBitwiseShiftByVector_Predicated"},
+      {"11", "VisitSVEBitwiseShiftByWideElements_Predicated"},
+    },
+  },
+
+  { "DecodeSVE00001010",
+    {23, 12, 11},
+    { {"x0x", "VisitSVEIndexGeneration"},
+      {"010", "VisitSVEStackFrameAdjustment"},
+      {"110", "UnallocSVEStackFrameSize"},
+    },
+  },
+
+  { "UnallocSVEStackFrameSize",
+    {22, 20, 19, 18, 17, 16},
+    { {"011111", "VisitSVEStackFrameSize"},
+    },
+  },
+
+  { "DecodeSVE00001101",
+    {12, 11, 10},
+    { {"0xx", "VisitSVEAddressGeneration"},
+      {"10x", "VisitSVEFPTrigSelectCoefficient"},
+      {"110", "VisitSVEFPExponentialAccelerator"},
+      {"111", "VisitSVEConstructivePrefix_Unpredicated"},
+    },
+  },
+
+  { "DecodeSVE00001110",
+    {20, 12, 11},
+    { {"00x", "VisitSVESaturatingIncDecVectorByElementCount"},
+      {"100", "VisitSVEIncDecVectorByElementCount"},
+    },
+  },
+
+  { "DecodeSVE00001111",
+    {20, 12, 11},
+    { {"x1x", "VisitSVESaturatingIncDecRegisterByElementCount"},
+      {"000", "VisitSVEElementCount"},
+      {"100", "VisitSVEIncDecRegisterByElementCount"},
+    },
+  },
+
+  { "DecodeSVE000100xx",
+    {23, 22, 20, 19, 18},
+    { {"xx1xx", "VisitSVECopyIntImm_Predicated"},
+      {"0x000", "VisitSVEBitwiseLogicalWithImm_Unpredicated"},
+      {"10000", "VisitSVEBitwiseLogicalWithImm_Unpredicated"},
+      {"11000", "VisitSVEBroadcastBitmaskImm"},
+    },
+  },
+
+  { "DecodeSVE0001010x",
+    {23, 22, 20, 19, 18},
+    { {"0x000", "VisitSVEBitwiseLogicalWithImm_Unpredicated"},
+      {"10000", "VisitSVEBitwiseLogicalWithImm_Unpredicated"},
+      {"11000", "VisitSVEBroadcastBitmaskImm"},
+    },
+  },
+
+  { "DecodeSVE00010110",
+    {23, 22, 20, 19, 18},
+    { {"xx1xx", "VisitSVECopyFPImm_Predicated"},
+      {"0x000", "VisitSVEBitwiseLogicalWithImm_Unpredicated"},
+      {"10000", "VisitSVEBitwiseLogicalWithImm_Unpredicated"},
+      {"11000", "VisitSVEBroadcastBitmaskImm"},
+    },
+  },
+
+  { "DecodeSVE00010111",
+    {23, 22, 20, 19, 18},
+    { {"0x000", "VisitSVEBitwiseLogicalWithImm_Unpredicated"},
+      {"10000", "VisitSVEBitwiseLogicalWithImm_Unpredicated"},
+      {"11000", "VisitSVEBroadcastBitmaskImm"},
+    },
+  },
+
+  { "UnallocSVEBroadcastIndexElement",
+    {10},
+    { {"0", "VisitSVEBroadcastIndexElement"},
+    },
+  },
+
+  { "UnallocSVETableLookup",
+    {10},
+    { {"0", "VisitSVETableLookup"},
+    },
+  },
+
+  { "UnallocSVEBroadcastGeneralRegister",
+    {17, 16, 10},
+    { {"000", "VisitSVEBroadcastGeneralRegister"},
+    },
+  },
+
+  { "UnallocSVEInsertGeneralRegister",
+    {17, 16, 10},
+    { {"000", "VisitSVEInsertGeneralRegister"},
+    },
+  },
+
+  { "UnallocSVEUnpackVectorElements",
+    {10},
+    { {"0", "VisitSVEUnpackVectorElements"},
+    },
+  },
+
+  { "UnallocSVEInsertSIMDFPScalarRegister",
+    {17, 16, 10},
+    { {"000", "VisitSVEInsertSIMDFPScalarRegister"},
+    },
+  },
+
+  { "UnallocSVEReverseVectorElements",
+    {17, 16, 10},
+    { {"000", "VisitSVEReverseVectorElements"},
+    },
+  },
+
+  { "DecodeSVE00011001",
+    {20, 19, 18, 12, 11},
+    { {"xxx00", "UnallocSVEBroadcastIndexElement"},
+      {"xxx10", "UnallocSVETableLookup"},
+      {"00011", "UnallocSVEBroadcastGeneralRegister"},
+      {"00111", "UnallocSVEInsertGeneralRegister"},
+      {"10011", "UnallocSVEUnpackVectorElements"},
+      {"10111", "UnallocSVEInsertSIMDFPScalarRegister"},
+      {"11011", "UnallocSVEReverseVectorElements"},
+    },
+  },
+
+  { "UnallocSVEPermutePredicateElements",
+    {9, 4},
+    { {"00", "VisitSVEPermutePredicateElements"},
+    },
+  },
+
+  { "UnallocSVEUnpackPredicateElements",
+    {23, 22, 19, 17, 12, 11, 10, 9, 4},
+    { {"000000000", "VisitSVEUnpackPredicateElements"},
+    },
+  },
+
+  { "UnallocSVEReversePredicateElements",
+    {19, 17, 16, 12, 11, 10, 9, 4},
+    { {"00000000", "VisitSVEReversePredicateElements"},
+    },
+  },
+
+  { "DecodeSVE00011010",
+    {20, 18},
+    { {"0x", "UnallocSVEPermutePredicateElements"},
+      {"10", "UnallocSVEUnpackPredicateElements"},
+      {"11", "UnallocSVEReversePredicateElements"},
+    },
+  },
+
+  { "DecodeSVE00011100",
+    {23, 20, 19, 18, 17, 16},
+    { {"x00000", "VisitSVECopySIMDFPScalarRegisterToVector_Predicated"},
+      {"x0001x", "VisitSVEExtractElementToSIMDFPScalarRegister"},
+      {"x001xx", "VisitSVEReverseWithinElements"},
+      {"x0100x", "VisitSVEConditionallyBroadcastElementToVector"},
+      {"x0101x", "VisitSVEConditionallyExtractElementToSIMDFPScalar"},
+      {"x01100", "VisitSVEVectorSplice_Destructive"},
+      {"100001", "VisitSVECompressActiveElements"},
+    },
+  },
+
+  { "DecodeSVE00011101",
+    {20, 19, 18, 17, 16},
+    { {"0000x", "VisitSVEExtractElementToGeneralRegister"},
+      {"01000", "VisitSVECopyGeneralRegisterToVector_Predicated"},
+      {"1000x", "VisitSVEConditionallyExtractElementToGeneralRegister"},
+    },
+  },
+
+  { "UnallocSVEPartitionBreakCondition",
+    {18, 17, 16, 9},
+    { {"0000", "VisitSVEPartitionBreakCondition"},
+    },
+  },
+
+  { "UnallocSVEPropagateBreakToNextPartition",
+    {23, 18, 17, 16, 9, 4},
+    { {"000000", "VisitSVEPropagateBreakToNextPartition"},
+    },
+  },
+
+  { "DecodeSVE0011001x",
+    {20, 19},
+    { {"0x", "VisitSVEPredicateLogical"},
+      {"10", "UnallocSVEPartitionBreakCondition"},
+      {"11", "UnallocSVEPropagateBreakToNextPartition"},
+    },
+  },
+
+  { "UnallocSVEPredicateTest",
+    {18, 17, 9, 4},
+    { {"0000", "VisitSVEPredicateTest"},
+    },
+  },
+
+  { "UnallocSVEPredicateFirstActive",
+    {18, 17, 12, 11, 10, 9, 4},
+    { {"0000000", "VisitSVEPredicateFirstActive"},
+    },
+  },
+
+  { "UnallocSVEPredicateNextActive",
+    {18, 17, 12, 11, 10, 9, 4},
+    { {"0000100", "VisitSVEPredicateNextActive"},
+    },
+  },
+
+  { "DecodeSVE00110110",
+    {20, 19, 16},
+    { {"0xx", "VisitSVEPropagateBreak"},
+      {"100", "UnallocSVEPredicateTest"},
+      {"110", "UnallocSVEPredicateFirstActive"},
+      {"111", "UnallocSVEPredicateNextActive"},
+    },
+  },
+
+  { "UnallocSVEPredicateTest",
+    {18, 17, 9, 4},
+    { {"0000", "VisitSVEPredicateTest"},
+    },
+  },
+
+  { "UnallocSVEPredicateInitialize",
+    {18, 17, 11, 4},
+    { {"0000", "VisitSVEPredicateInitialize"},
+    },
+  },
+
+  { "UnallocSVEPredicateZero",
+    {18, 17, 11, 9, 8, 7, 6, 5, 4},
+    { {"000000000", "VisitSVEPredicateZero"},
+    },
+  },
+
+  { "UnallocSVEPredicateReadFromFFR_Predicated",
+    {18, 17, 11, 9, 4},
+    { {"00000", "VisitSVEPredicateReadFromFFR_Predicated"},
+    },
+  },
+
+  { "UnallocSVEPredicateReadFromFFR_Unpredicated",
+    {18, 17, 11, 9, 8, 7, 6, 5, 4},
+    { {"000000000", "VisitSVEPredicateReadFromFFR_Unpredicated"},
+    },
+  },
+
+  { "DecodeSVE00110111",
+    {20, 19, 16, 12, 10},
+    { {"0xxxx", "VisitSVEPropagateBreak"},
+      {"100xx", "UnallocSVEPredicateTest"},
+      {"11x00", "UnallocSVEPredicateInitialize"},
+      {"11001", "UnallocSVEPredicateZero"},
+      {"11010", "UnallocSVEPredicateReadFromFFR_Predicated"},
+      {"11110", "UnallocSVEPredicateReadFromFFR_Unpredicated"},
+    },
+  },
+
+  { "UnallocSVEConditionallyTerminateScalars",
+    {12, 11, 10, 3, 2, 1, 0},
+    { {"0000000", "VisitSVEConditionallyTerminateScalars"},
+    },
+  },
+
+  { "UnallocSVEPredicateCount_2",
+    {20},
+    { {"0", "VisitSVEPredicateCount"},
+    },
+  },
+
+  { "UnallocSVEIncDecByPredicateCount",
+    {20},
+    { {"0", "VisitSVEIncDecByPredicateCount"},
+    },
+  },
+
+  { "UnallocSVEFFRWriteFromPredicate",
+    {20, 17, 16, 11, 10, 9, 4, 3, 2, 1, 0},
+    { {"00000000000", "VisitSVEFFRWriteFromPredicate"},
+    },
+  },
+
+  { "UnallocSVEFFRInitialise",
+    {20, 17, 16, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0},
+    { {"000000000000000", "VisitSVEFFRInitialise"},
+    },
+  },
+
+  { "DecodeSVE00111100",
+    {19, 18, 12},
+    { {"0xx", "UnallocSVEPredicateCount_2"},
+      {"1x0", "UnallocSVEIncDecByPredicateCount"},
+      {"101", "UnallocSVEFFRWriteFromPredicate"},
+      {"111", "UnallocSVEFFRInitialise"},
+    },
+  },
+
+  { "UnallocSVEPredicateCount",
+    {20, 19},
+    { {"00", "VisitSVEPredicateCount"},
+    },
+  },
+
+  { "DecodeSVE0011111x",
+    {20, 19, 16},
+    { {"00x", "VisitSVEIntAddSubtractImm_Unpredicated"},
+      {"01x", "VisitSVEIntMinMaxImm_Unpredicated"},
+      {"10x", "VisitSVEIntMulImm_Unpredicated"},
+      {"110", "VisitSVEBroadcastIntImm_Unpredicated"},
+      {"111", "VisitSVEBroadcastFPImm_Unpredicated"},
+    },
+  },
+
+  { "UnallocSVEFPComplexAddition",
+    {20, 19, 18, 17},
+    { {"0000", "VisitSVEFPComplexAddition"},
+    },
+  },
+
+  { "DecodeSVE01101000",
+    {12, 11},
+    { {"00", "VisitSVEFPMulAddIndex"},
+      {"1x", "VisitSVEFPComplexMulAddIndex"},
+    },
+  },
+
+  { "UnallocSVEFPMulIndex",
+    {12, 11, 10},
+    { {"000", "VisitSVEFPMulIndex"},
+    },
+  },
+
+  { "DecodeSVE01110001",
+    {20, 19, 12},
+    { {"00x", "VisitSVEFPFastReduction"},
+      {"011", "VisitSVEFPUnaryOpUnpredicated"},
+      {"10x", "VisitSVEFPCompareWithZero"},
+      {"11x", "VisitSVEFPAccumulatingReduction"},
+    },
+  },
+
+  { "UnallocSVEFPTrigMulAddCoefficient",
+    {12, 11, 10},
+    { {"000", "VisitSVEFPTrigMulAddCoefficient"},
+    },
+  },
+
+  { "UnallocSVEFPArithmeticWithImm_Predicated",
+    {9, 8, 7, 6},
+    { {"0000", "VisitSVEFPArithmeticWithImm_Predicated"},
+    },
+  },
+
+  { "DecodeSVE01110100",
+    {20, 19},
+    { {"0x", "VisitSVEFPArithmetic_Predicated"},
+      {"10", "UnallocSVEFPTrigMulAddCoefficient"},
+      {"11", "UnallocSVEFPArithmeticWithImm_Predicated"},
+    },
+  },
+
+  { "DecodeSVE01110101",
+    {20, 19, 18},
+    { {"00x", "VisitSVEFPRoundToIntegralValue"},
+      {"010", "VisitSVEFPConvertPrecision"},
+      {"011", "VisitSVEFPUnaryOp"},
+      {"10x", "VisitSVEIntConvertToFP"},
+      {"11x", "VisitSVEFPConvertToInt"},
+    },
+  },
+
+  { "UnallocSVELoadAndBroadcastElement",
+    {22},
+    { {"1", "VisitSVELoadAndBroadcastElement"},
+    },
+  },
+
+  { "DecodeSVE100x0110",
+    {22, 4},
+    { {"00", "VisitSVEContiguousPrefetch_ScalarPlusScalar"},
+      {"1x", "VisitSVELoadAndBroadcastElement"},
+    },
+  },
+
+  { "DecodeSVE100x0111",
+    {22, 4},
+    { {"00", "VisitSVE32BitGatherPrefetch_VectorPlusImm"},
+      {"1x", "VisitSVELoadAndBroadcastElement"},
+    },
+  },
+
+  { "DecodeSVE100x11xx",
+    {22},
+    { {"0", "VisitSVE32BitGatherLoad_VectorPlusImm"},
+      {"1", "VisitSVELoadAndBroadcastElement"},
+    },
+  },
+
+  { "DecodeSVE100010xx",
+    {23, 4},
+    { {"00", "VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets"},
+      {"1x", "VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets"},
+    },
+  },
+
+  { "DecodeSVE100100x1",
+    {23, 22, 4},
+    { {"0xx", "VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets"},
+      {"110", "VisitSVEContiguousPrefetch_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE10010000",
+    {23, 22, 4},
+    { {"0xx", "VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets"},
+      {"100", "VisitSVELoadPredicateRegister"},
+      {"110", "VisitSVEContiguousPrefetch_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE10010010",
+    {23, 22, 4},
+    { {"0xx", "VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets"},
+      {"10x", "VisitSVELoadVectorRegister"},
+      {"110", "VisitSVEContiguousPrefetch_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE100110x1",
+    {23, 22, 4},
+    { {"0xx", "VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets"},
+      {"110", "VisitSVEContiguousPrefetch_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE10011000",
+    {23, 22, 4},
+    { {"0xx", "VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets"},
+      {"100", "VisitSVELoadPredicateRegister"},
+      {"110", "VisitSVEContiguousPrefetch_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE10011010",
+    {23, 22, 4},
+    { {"0xx", "VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets"},
+      {"10x", "VisitSVELoadVectorRegister"},
+      {"110", "VisitSVEContiguousPrefetch_ScalarPlusImm"},
+    },
+  },
+
+  { "UnallocSVELoadAndBroadcastQuadword_ScalarPlusImm",
+    {20},
+    { {"0", "VisitSVELoadAndBroadcastQuadword_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE101xx101",
+    {20},
+    { {"0", "VisitSVEContiguousLoad_ScalarPlusImm"},
+      {"1", "VisitSVEContiguousNonFaultLoad_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE101x0110",
+    {22},
+    { {"0", "VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar"},
+      {"1", "VisitSVELoadMultipleStructures_ScalarPlusScalar"},
+    },
+  },
+
+  { "DecodeSVE101x0111",
+    {22, 20},
+    { {"00", "VisitSVEContiguousNonTemporalLoad_ScalarPlusImm"},
+      {"10", "VisitSVELoadMultipleStructures_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE101x1111",
+    {22, 20},
+    { {"x0", "VisitSVELoadMultipleStructures_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE110x0111",
+    {22, 4},
+    { {"00", "VisitSVE64BitGatherPrefetch_VectorPlusImm"},
+      {"1x", "VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+    },
+  },
+
+  { "UnallocSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets",
+    {22},
+    { {"1", "VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+    },
+  },
+
+  { "UnallocSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets",
+    {22},
+    { {"1", "VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+    },
+  },
+
+  { "DecodeSVE110010xx",
+    {23, 4},
+    { {"00", "VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets"},
+      {"1x", "VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets"},
+    },
+  },
+
+  { "DecodeSVE110011xx",
+    {23, 22, 4},
+    { {"x0x", "VisitSVE64BitGatherLoad_VectorPlusImm"},
+      {"010", "VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets"},
+      {"11x", "VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets"},
+    },
+  },
+
+  { "UnallocSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets",
+    {22},
+    { {"1", "VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+    },
+  },
+
+  { "UnallocSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets",
+    {22},
+    { {"1", "VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets"},
+    },
+  },
+
+  { "DecodeSVE110111xx",
+    {22},
+    { {"0", "VisitSVE64BitGatherLoad_VectorPlusImm"},
+      {"1", "VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets"},
+    },
+  },
+
+  { "DecodeSVE111x0011",
+    {22},
+    { {"0", "VisitSVEContiguousNonTemporalStore_ScalarPlusScalar"},
+      {"1", "VisitSVEStoreMultipleStructures_ScalarPlusScalar"},
+    },
+  },
+
+  { "DecodeSVE111x01x0",
+    {22},
+    { {"0", "VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets"},
+      {"1", "VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets"},
+    },
+  },
+
+  { "DecodeSVE111x0101",
+    {22},
+    { {"0", "VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets"},
+      {"1", "VisitSVE64BitScatterStore_VectorPlusImm"},
+    },
+  },
+
+  { "DecodeSVE111x0111",
+    {22, 20},
+    { {"x0", "VisitSVEContiguousStore_ScalarPlusImm"},
+      {"01", "VisitSVEContiguousNonTemporalStore_ScalarPlusImm"},
+      {"11", "VisitSVEStoreMultipleStructures_ScalarPlusImm"},
+    },
+  },
+
+  { "DecodeSVE111x11x0",
+    {22},
+    { {"0", "VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets"},
+      {"1", "VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets"},
+    },
+  },
+
+  { "DecodeSVE111x1101",
+    {22},
+    { {"0", "VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets"},
+      {"1", "VisitSVE32BitScatterStore_VectorPlusImm"},
+    },
+  },
+
+  { "DecodeSVE111x1111",
+    {22, 20},
+    { {"x0", "VisitSVEContiguousStore_ScalarPlusImm"},
+      {"x1", "VisitSVEStoreMultipleStructures_ScalarPlusImm"},
+    },
+  },
+
+  { "UnallocSVEStorePredicateRegister",
+    {23, 22, 4},
+    { {"100", "VisitSVEStorePredicateRegister"},
+    },
+  },
+
+  { "DecodeSVE1111x010",
+    {23, 22},
+    { {"0x", "VisitSVEContiguousStore_ScalarPlusScalar"},
+      {"10", "VisitSVEStoreVectorRegister"},
+      {"11", "VisitSVEContiguousStore_ScalarPlusScalar"},
+    },
+  },
+
   { "DecodeNEONScalarAnd3SHA",
     {29, 23, 22, 15, 14, 11, 10},
     { {"0xx0x00", "VisitCrypto3RegSHA"},
@@ -1388,6 +2103,28 @@ static const DecodeMapping kDecodeMapping[] = {
       {"otherwise", "VisitUnconditionalBranchToRegister"},
     },
   },
+
+  { "DecodeSVE101xxxxx",
+    {15, 14, 13},
+    { {"101", "DecodeSVE101xx101"},
+      {"010", "VisitSVEContiguousLoad_ScalarPlusScalar"},
+      {"otherwise", "VisitSVEMemContiguousLoad"},
+    },
+  },
+
+  { "DecodeSVE101xx101",
+    {20},
+    { {"0", "VisitSVEContiguousLoad_ScalarPlusImm"},
+      {"1", "VisitSVEMemContiguousLoad"},
+    },
+  },
+
+  { "DecodeSVE00000001",
+    {20, 19},
+    { {"10", "VisitSVEMovprfx"},
+      {"otherwise", "VisitSVEIntReduction"},
+    },
+  },
 };
 // clang-format on
 
diff --git a/src/aarch64/disasm-aarch64.cc b/src/aarch64/disasm-aarch64.cc
index 7d6fa148..83ce3174 100644
--- a/src/aarch64/disasm-aarch64.cc
+++ b/src/aarch64/disasm-aarch64.cc
@@ -24,6 +24,7 @@
 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+#include <bitset>
 #include <cstdlib>
 #include <sstream>
 
@@ -956,7 +957,7 @@ void Disassembler::VisitTestBranch(const Instruction *instr) {
   // disassembled as Wt, otherwise Xt. As the top bit of the immediate is
   // encoded in bit 31 of the instruction, we can reuse the Rt form, which
   // uses bit 31 (normally "sf") to choose the register size.
-  const char *form = "'Rt, 'IS, 'TImmTest";
+  const char *form = "'Rt, 'It, 'TImmTest";
 
   switch (instr->Mask(TestBranchMask)) {
     case TBZ:
@@ -1086,7 +1087,7 @@ void Disassembler::VisitLoadStoreUnsignedOffset(const Instruction *instr) {
 #undef LS_UNSIGNEDOFFSET
     case PRFM_unsigned:
       mnemonic = "prfm";
-      form = "'PrefOp, ['Xns'ILU]";
+      form = "'prefOp, ['Xns'ILU]";
   }
   Format(instr, mnemonic, form);
 }
@@ -1165,7 +1166,7 @@ void Disassembler::VisitLoadStoreRegisterOffset(const Instruction *instr) {
 #undef LS_REGISTEROFFSET
     case PRFM_reg:
       mnemonic = "prfm";
-      form = "'PrefOp, ['Xns, 'Offsetreg]";
+      form = "'prefOp, ['Xns, 'Offsetreg]";
   }
   Format(instr, mnemonic, form);
 }
@@ -1180,7 +1181,7 @@ void Disassembler::VisitLoadStoreUnscaledOffset(const Instruction *instr) {
   const char *form_s = "'St, ['Xns'ILS]";
   const char *form_d = "'Dt, ['Xns'ILS]";
   const char *form_q = "'Qt, ['Xns'ILS]";
-  const char *form_prefetch = "'PrefOp, ['Xns'ILS]";
+  const char *form_prefetch = "'prefOp, ['Xns'ILS]";
 
   switch (instr->Mask(LoadStoreUnscaledOffsetMask)) {
     case STURB_w:
@@ -1303,7 +1304,7 @@ void Disassembler::VisitLoadLiteral(const Instruction *instr) {
     }
     case PRFM_lit: {
       mnemonic = "prfm";
-      form = "'PrefOp, 'ILLiteral 'LValue";
+      form = "'prefOp, 'ILLiteral 'LValue";
       break;
     }
     default:
@@ -1486,14 +1487,14 @@ void Disassembler::VisitLoadStorePairNonTemporal(const Instruction *instr) {
   V(CASAH,    "casah",  "'Ws, 'Wt")                   \
   V(CASLH,    "caslh",  "'Ws, 'Wt")                   \
   V(CASALH,   "casalh", "'Ws, 'Wt")                   \
-  V(CASP_w,   "casp",   "'Ws, 'W(s+1), 'Wt, 'W(t+1)") \
-  V(CASP_x,   "casp",   "'Xs, 'X(s+1), 'Xt, 'X(t+1)") \
-  V(CASPA_w,  "caspa",  "'Ws, 'W(s+1), 'Wt, 'W(t+1)") \
-  V(CASPA_x,  "caspa",  "'Xs, 'X(s+1), 'Xt, 'X(t+1)") \
-  V(CASPL_w,  "caspl",  "'Ws, 'W(s+1), 'Wt, 'W(t+1)") \
-  V(CASPL_x,  "caspl",  "'Xs, 'X(s+1), 'Xt, 'X(t+1)") \
-  V(CASPAL_w, "caspal", "'Ws, 'W(s+1), 'Wt, 'W(t+1)") \
-  V(CASPAL_x, "caspal", "'Xs, 'X(s+1), 'Xt, 'X(t+1)")
+  V(CASP_w,   "casp",   "'Ws, 'Ws+, 'Wt, 'Wt+")       \
+  V(CASP_x,   "casp",   "'Xs, 'Xs+, 'Xt, 'Xt+")       \
+  V(CASPA_w,  "caspa",  "'Ws, 'Ws+, 'Wt, 'Wt+")       \
+  V(CASPA_x,  "caspa",  "'Xs, 'Xs+, 'Xt, 'Xt+")       \
+  V(CASPL_w,  "caspl",  "'Ws, 'Ws+, 'Wt, 'Wt+")       \
+  V(CASPL_x,  "caspl",  "'Xs, 'Xs+, 'Xt, 'Xt+")       \
+  V(CASPAL_w, "caspal", "'Ws, 'Ws+, 'Wt, 'Wt+")       \
+  V(CASPAL_x, "caspal", "'Xs, 'Xs+, 'Xt, 'Xt+")
 // clang-format on
 
 
@@ -1898,15 +1899,15 @@ void Disassembler::VisitFPImmediate(const Instruction *instr) {
   switch (instr->Mask(FPImmediateMask)) {
     case FMOV_h_imm:
       mnemonic = "fmov";
-      form = "'Hd, 'IFPHalf";
+      form = "'Hd, 'IFP";
       break;
     case FMOV_s_imm:
       mnemonic = "fmov";
-      form = "'Sd, 'IFPSingle";
+      form = "'Sd, 'IFP";
       break;
     case FMOV_d_imm:
       mnemonic = "fmov";
-      form = "'Dd, 'IFPDouble";
+      form = "'Dd, 'IFP";
       break;
     default:
       VIXL_UNREACHABLE();
@@ -3409,7 +3410,7 @@ void Disassembler::VisitNEONCopy(const Instruction *instr) {
   } else if (instr->Mask(NEONCopySmovMask) == NEON_SMOV) {
     mnemonic = "smov";
     nfd.SetFormatMap(0, nfd.TriangularScalarFormatMap());
-    form = "'Rdq, 'Vn.%s['IVInsIndex1]";
+    form = "'R30d, 'Vn.%s['IVInsIndex1]";
   } else if (instr->Mask(NEONCopyDupElementMask) == NEON_DUP_ELEMENT) {
     mnemonic = "dup";
     form = "'Vd.%s, 'Vn.%s['IVInsIndex1]";
@@ -4006,19 +4007,16 @@ void Disassembler::VisitNEONModifiedImmediate(const Instruction *instr) {
           }
         } else {  // cmode<0> == '1'
           mnemonic = "fmov";
+          form = "'Vt.%s, 'IFPNeon";
           if (half_enc == 1) {
-            form = "'Vt.%s, 'IVMIImmFPHalf";
             nfd.SetFormatMap(0, &map_h);
           } else if (op == 0) {
-            form = "'Vt.%s, 'IVMIImmFPSingle";
             nfd.SetFormatMap(0, &map_s);
+          } else if (q == 1) {
+            form = "'Vt.2d, 'IFPNeon";
           } else {
-            if (q == 1) {
-              form = "'Vt.2d, 'IVMIImmFPDouble";
-            } else {
-              mnemonic = "unallocated";
-              form = "(NEONModifiedImmediate)";
-            }
+            mnemonic = "unallocated";
+            form = "(NEONModifiedImmediate)";
           }
         }
       }
@@ -4926,6 +4924,4582 @@ void Disassembler::VisitNEONPerm(const Instruction *instr) {
   Format(instr, mnemonic, nfd.Substitute(form));
 }
 
+void Disassembler::
+    VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets(
+        const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw #1]";
+
+  switch (instr->Mask(
+      SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask)) {
+    case LD1H_z_p_bz_s_x32_scaled:
+      mnemonic = "ld1h";
+      break;
+    case LD1SH_z_p_bz_s_x32_scaled:
+      mnemonic = "ld1sh";
+      break;
+    case LDFF1H_z_p_bz_s_x32_scaled:
+      mnemonic = "ldff1h";
+      break;
+    case LDFF1SH_z_p_bz_s_x32_scaled:
+      mnemonic = "ldff1sh";
+      break;
+    default:
+      form = "(SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw #2]";
+
+  switch (
+      instr->Mask(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask)) {
+    case LD1W_z_p_bz_s_x32_scaled:
+      mnemonic = "ld1w";
+      break;
+    case LDFF1W_z_p_bz_s_x32_scaled:
+      mnemonic = "ldff1w";
+      break;
+    default:
+      form = "(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets(
+    const Instruction *instr) {
+  const char *form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Zm.s, '?22:suxtw]";
+
+  const char *mnemonic = "unimplemented";
+  switch (instr->Mask(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask)) {
+    case LD1B_z_p_bz_s_x32_unscaled:
+      mnemonic = "ld1b";
+      break;
+    case LD1H_z_p_bz_s_x32_unscaled:
+      mnemonic = "ld1h";
+      break;
+    case LD1SB_z_p_bz_s_x32_unscaled:
+      mnemonic = "ld1sb";
+      break;
+    case LD1SH_z_p_bz_s_x32_unscaled:
+      mnemonic = "ld1sh";
+      break;
+    case LD1W_z_p_bz_s_x32_unscaled:
+      mnemonic = "ld1w";
+      break;
+    case LDFF1B_z_p_bz_s_x32_unscaled:
+      mnemonic = "ldff1b";
+      break;
+    case LDFF1H_z_p_bz_s_x32_unscaled:
+      mnemonic = "ldff1h";
+      break;
+    case LDFF1SB_z_p_bz_s_x32_unscaled:
+      mnemonic = "ldff1sb";
+      break;
+    case LDFF1SH_z_p_bz_s_x32_unscaled:
+      mnemonic = "ldff1sh";
+      break;
+    case LDFF1W_z_p_bz_s_x32_unscaled:
+      mnemonic = "ldff1w";
+      break;
+    default:
+      form = "(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE32BitGatherLoad_VectorPlusImm(
+    const Instruction *instr) {
+  const char *form = "{'Zt.s}, 'Pgl/z, ['Zn.s]";
+  const char *form_imm_b = "{'Zt.s}, 'Pgl/z, ['Zn.s, #'u2016]";
+  const char *form_imm_h = "{'Zt.s}, 'Pgl/z, ['Zn.s, #'u2016*2]";
+  const char *form_imm_w = "{'Zt.s}, 'Pgl/z, ['Zn.s, #'u2016*4]";
+  const char *form_imm;
+
+  const char *mnemonic = "unimplemented";
+  switch (instr->Mask(SVE32BitGatherLoad_VectorPlusImmMask)) {
+    case LD1B_z_p_ai_s:
+      mnemonic = "ld1b";
+      form_imm = form_imm_b;
+      break;
+    case LD1H_z_p_ai_s:
+      mnemonic = "ld1h";
+      form_imm = form_imm_h;
+      break;
+    case LD1SB_z_p_ai_s:
+      mnemonic = "ld1sb";
+      form_imm = form_imm_b;
+      break;
+    case LD1SH_z_p_ai_s:
+      mnemonic = "ld1sh";
+      form_imm = form_imm_h;
+      break;
+    case LD1W_z_p_ai_s:
+      mnemonic = "ld1w";
+      form_imm = form_imm_w;
+      break;
+    case LDFF1B_z_p_ai_s:
+      mnemonic = "ldff1b";
+      form_imm = form_imm_b;
+      break;
+    case LDFF1H_z_p_ai_s:
+      mnemonic = "ldff1h";
+      form_imm = form_imm_h;
+      break;
+    case LDFF1SB_z_p_ai_s:
+      mnemonic = "ldff1sb";
+      form_imm = form_imm_b;
+      break;
+    case LDFF1SH_z_p_ai_s:
+      mnemonic = "ldff1sh";
+      form_imm = form_imm_h;
+      break;
+    case LDFF1W_z_p_ai_s:
+      mnemonic = "ldff1w";
+      form_imm = form_imm_w;
+      break;
+    default:
+      form = "(SVE32BitGatherLoad_VectorPlusImm)";
+      form_imm = form;
+      break;
+  }
+  if (instr->ExtractBits(20, 16) != 0) form = form_imm;
+
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.s, '?22:suxtw";
+  const char *suffix = NULL;
+
+  switch (
+      instr->Mask(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask)) {
+    case PRFB_i_p_bz_s_x32_scaled:
+      mnemonic = "prfb";
+      suffix = "]";
+      break;
+    case PRFD_i_p_bz_s_x32_scaled:
+      mnemonic = "prfd";
+      suffix = " #3]";
+      break;
+    case PRFH_i_p_bz_s_x32_scaled:
+      mnemonic = "prfh";
+      suffix = " #1]";
+      break;
+    case PRFW_i_p_bz_s_x32_scaled:
+      mnemonic = "prfw";
+      suffix = " #2]";
+      break;
+    default:
+      form = "(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVE32BitGatherPrefetch_VectorPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = (instr->ExtractBits(20, 16) != 0)
+                         ? "'prefSVEOp, 'Pgl, ['Zn.s, #'u2016]"
+                         : "'prefSVEOp, 'Pgl, ['Zn.s]";
+
+  switch (instr->Mask(SVE32BitGatherPrefetch_VectorPlusImmMask)) {
+    case PRFB_i_p_ai_s:
+      mnemonic = "prfb";
+      break;
+    case PRFD_i_p_ai_s:
+      mnemonic = "prfd";
+      break;
+    case PRFH_i_p_ai_s:
+      mnemonic = "prfh";
+      break;
+    case PRFW_i_p_ai_s:
+      mnemonic = "prfw";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.s}, 'Pgl, ['Xns, 'Zm.s, '?14:suxtw #'u2423]";
+
+  switch (instr->Mask(SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask)) {
+    case ST1H_z_p_bz_s_x32_scaled:
+      mnemonic = "st1h";
+      break;
+    case ST1W_z_p_bz_s_x32_scaled:
+      mnemonic = "st1w";
+      break;
+    default:
+      form = "(SVE32BitScatterStore_ScalarPlus32BitScaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.s}, 'Pgl, ['Xns, 'Zm.s, '?14:suxtw]";
+
+  switch (
+      instr->Mask(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask)) {
+    case ST1B_z_p_bz_s_x32_unscaled:
+      mnemonic = "st1b";
+      break;
+    case ST1H_z_p_bz_s_x32_unscaled:
+      mnemonic = "st1h";
+      break;
+    case ST1W_z_p_bz_s_x32_unscaled:
+      mnemonic = "st1w";
+      break;
+    default:
+      form = "(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE32BitScatterStore_VectorPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.s}, 'Pgl, ['Zn.s";
+  const char *suffix = NULL;
+
+  bool is_zero = instr->ExtractBits(20, 16) == 0;
+
+  switch (instr->Mask(SVE32BitScatterStore_VectorPlusImmMask)) {
+    case ST1B_z_p_ai_s:
+      mnemonic = "st1b";
+      suffix = is_zero ? "]" : ", #'u2016]";
+      break;
+    case ST1H_z_p_ai_s:
+      mnemonic = "st1h";
+      suffix = is_zero ? "]" : ", #'u2016*2]";
+      break;
+    case ST1W_z_p_ai_s:
+      mnemonic = "st1w";
+      suffix = is_zero ? "]" : ", #'u2016*4]";
+      break;
+    default:
+      form = "(SVE32BitScatterStore_VectorPlusImm)";
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, '?22:suxtw #'u2423]";
+
+  switch (instr->Mask(
+      SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask)) {
+    case LD1D_z_p_bz_d_x32_scaled:
+      mnemonic = "ld1d";
+      break;
+    case LD1H_z_p_bz_d_x32_scaled:
+      mnemonic = "ld1h";
+      break;
+    case LD1SH_z_p_bz_d_x32_scaled:
+      mnemonic = "ld1sh";
+      break;
+    case LD1SW_z_p_bz_d_x32_scaled:
+      mnemonic = "ld1sw";
+      break;
+    case LD1W_z_p_bz_d_x32_scaled:
+      mnemonic = "ld1w";
+      break;
+    case LDFF1D_z_p_bz_d_x32_scaled:
+      mnemonic = "ldff1d";
+      break;
+    case LDFF1H_z_p_bz_d_x32_scaled:
+      mnemonic = "ldff1h";
+      break;
+    case LDFF1SH_z_p_bz_d_x32_scaled:
+      mnemonic = "ldff1sh";
+      break;
+    case LDFF1SW_z_p_bz_d_x32_scaled:
+      mnemonic = "ldff1sw";
+      break;
+    case LDFF1W_z_p_bz_d_x32_scaled:
+      mnemonic = "ldff1w";
+      break;
+    default:
+      form = "(SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, lsl #'u2423]";
+
+  switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask)) {
+    case LD1D_z_p_bz_d_64_scaled:
+      mnemonic = "ld1d";
+      break;
+    case LD1H_z_p_bz_d_64_scaled:
+      mnemonic = "ld1h";
+      break;
+    case LD1SH_z_p_bz_d_64_scaled:
+      mnemonic = "ld1sh";
+      break;
+    case LD1SW_z_p_bz_d_64_scaled:
+      mnemonic = "ld1sw";
+      break;
+    case LD1W_z_p_bz_d_64_scaled:
+      mnemonic = "ld1w";
+      break;
+    case LDFF1D_z_p_bz_d_64_scaled:
+      mnemonic = "ldff1d";
+      break;
+    case LDFF1H_z_p_bz_d_64_scaled:
+      mnemonic = "ldff1h";
+      break;
+    case LDFF1SH_z_p_bz_d_64_scaled:
+      mnemonic = "ldff1sh";
+      break;
+    case LDFF1SW_z_p_bz_d_64_scaled:
+      mnemonic = "ldff1sw";
+      break;
+    case LDFF1W_z_p_bz_d_64_scaled:
+      mnemonic = "ldff1w";
+      break;
+    default:
+      form = "(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d]";
+
+  switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask)) {
+    case LD1B_z_p_bz_d_64_unscaled:
+      mnemonic = "ld1b";
+      break;
+    case LD1D_z_p_bz_d_64_unscaled:
+      mnemonic = "ld1d";
+      break;
+    case LD1H_z_p_bz_d_64_unscaled:
+      mnemonic = "ld1h";
+      break;
+    case LD1SB_z_p_bz_d_64_unscaled:
+      mnemonic = "ld1sb";
+      break;
+    case LD1SH_z_p_bz_d_64_unscaled:
+      mnemonic = "ld1sh";
+      break;
+    case LD1SW_z_p_bz_d_64_unscaled:
+      mnemonic = "ld1sw";
+      break;
+    case LD1W_z_p_bz_d_64_unscaled:
+      mnemonic = "ld1w";
+      break;
+    case LDFF1B_z_p_bz_d_64_unscaled:
+      mnemonic = "ldff1b";
+      break;
+    case LDFF1D_z_p_bz_d_64_unscaled:
+      mnemonic = "ldff1d";
+      break;
+    case LDFF1H_z_p_bz_d_64_unscaled:
+      mnemonic = "ldff1h";
+      break;
+    case LDFF1SB_z_p_bz_d_64_unscaled:
+      mnemonic = "ldff1sb";
+      break;
+    case LDFF1SH_z_p_bz_d_64_unscaled:
+      mnemonic = "ldff1sh";
+      break;
+    case LDFF1SW_z_p_bz_d_64_unscaled:
+      mnemonic = "ldff1sw";
+      break;
+    case LDFF1W_z_p_bz_d_64_unscaled:
+      mnemonic = "ldff1w";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::
+    VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets(
+        const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Zm.d, '?22:suxtw]";
+
+  switch (instr->Mask(
+      SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask)) {
+    case LD1B_z_p_bz_d_x32_unscaled:
+      mnemonic = "ld1b";
+      break;
+    case LD1D_z_p_bz_d_x32_unscaled:
+      mnemonic = "ld1d";
+      break;
+    case LD1H_z_p_bz_d_x32_unscaled:
+      mnemonic = "ld1h";
+      break;
+    case LD1SB_z_p_bz_d_x32_unscaled:
+      mnemonic = "ld1sb";
+      break;
+    case LD1SH_z_p_bz_d_x32_unscaled:
+      mnemonic = "ld1sh";
+      break;
+    case LD1SW_z_p_bz_d_x32_unscaled:
+      mnemonic = "ld1sw";
+      break;
+    case LD1W_z_p_bz_d_x32_unscaled:
+      mnemonic = "ld1w";
+      break;
+    case LDFF1B_z_p_bz_d_x32_unscaled:
+      mnemonic = "ldff1b";
+      break;
+    case LDFF1D_z_p_bz_d_x32_unscaled:
+      mnemonic = "ldff1d";
+      break;
+    case LDFF1H_z_p_bz_d_x32_unscaled:
+      mnemonic = "ldff1h";
+      break;
+    case LDFF1SB_z_p_bz_d_x32_unscaled:
+      mnemonic = "ldff1sb";
+      break;
+    case LDFF1SH_z_p_bz_d_x32_unscaled:
+      mnemonic = "ldff1sh";
+      break;
+    case LDFF1SW_z_p_bz_d_x32_unscaled:
+      mnemonic = "ldff1sw";
+      break;
+    case LDFF1W_z_p_bz_d_x32_unscaled:
+      mnemonic = "ldff1w";
+      break;
+    default:
+      form = "(SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE64BitGatherLoad_VectorPlusImm(
+    const Instruction *instr) {
+  const char *form = "{'Zt.d}, 'Pgl/z, ['Zn.d]";
+  const char *form_imm[4] = {"{'Zt.d}, 'Pgl/z, ['Zn.d, #'u2016]",
+                             "{'Zt.d}, 'Pgl/z, ['Zn.d, #'u2016*2]",
+                             "{'Zt.d}, 'Pgl/z, ['Zn.d, #'u2016*4]",
+                             "{'Zt.d}, 'Pgl/z, ['Zn.d, #'u2016*8]"};
+
+  if (instr->ExtractBits(20, 16) != 0) {
+    unsigned msz = instr->ExtractBits(24, 23);
+    bool sign_extend = instr->ExtractBit(14) == 0;
+    if ((msz == kDRegSizeInBytesLog2) && sign_extend) {
+      form = "(SVE64BitGatherLoad_VectorPlusImm)";
+    } else {
+      VIXL_ASSERT(msz < ArrayLength(form_imm));
+      form = form_imm[msz];
+    }
+  }
+
+  const char *mnemonic = "unimplemented";
+  switch (instr->Mask(SVE64BitGatherLoad_VectorPlusImmMask)) {
+    case LD1B_z_p_ai_d:
+      mnemonic = "ld1b";
+      break;
+    case LD1D_z_p_ai_d:
+      mnemonic = "ld1d";
+      break;
+    case LD1H_z_p_ai_d:
+      mnemonic = "ld1h";
+      break;
+    case LD1SB_z_p_ai_d:
+      mnemonic = "ld1sb";
+      break;
+    case LD1SH_z_p_ai_d:
+      mnemonic = "ld1sh";
+      break;
+    case LD1SW_z_p_ai_d:
+      mnemonic = "ld1sw";
+      break;
+    case LD1W_z_p_ai_d:
+      mnemonic = "ld1w";
+      break;
+    case LDFF1B_z_p_ai_d:
+      mnemonic = "ldff1b";
+      break;
+    case LDFF1D_z_p_ai_d:
+      mnemonic = "ldff1d";
+      break;
+    case LDFF1H_z_p_ai_d:
+      mnemonic = "ldff1h";
+      break;
+    case LDFF1SB_z_p_ai_d:
+      mnemonic = "ldff1sb";
+      break;
+    case LDFF1SH_z_p_ai_d:
+      mnemonic = "ldff1sh";
+      break;
+    case LDFF1SW_z_p_ai_d:
+      mnemonic = "ldff1sw";
+      break;
+    case LDFF1W_z_p_ai_d:
+      mnemonic = "ldff1w";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets)";
+
+  switch (
+      instr->Mask(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask)) {
+    case PRFB_i_p_bz_d_64_scaled:
+      mnemonic = "prfb";
+      form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d]";
+      break;
+    case PRFD_i_p_bz_d_64_scaled:
+      mnemonic = "prfd";
+      form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, lsl #3]";
+      break;
+    case PRFH_i_p_bz_d_64_scaled:
+      mnemonic = "prfh";
+      form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, lsl #1]";
+      break;
+    case PRFW_i_p_bz_d_64_scaled:
+      mnemonic = "prfw";
+      form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, lsl #2]";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::
+    VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets(
+        const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'prefSVEOp, 'Pgl, ['Xns, 'Zm.d, '?22:suxtw";
+  const char *suffix = NULL;
+
+  switch (instr->Mask(
+      SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask)) {
+    case PRFB_i_p_bz_d_x32_scaled:
+      mnemonic = "prfb";
+      suffix = " ]";
+      break;
+    case PRFD_i_p_bz_d_x32_scaled:
+      mnemonic = "prfd";
+      suffix = " #3]";
+      break;
+    case PRFH_i_p_bz_d_x32_scaled:
+      mnemonic = "prfh";
+      suffix = " #1]";
+      break;
+    case PRFW_i_p_bz_d_x32_scaled:
+      mnemonic = "prfw";
+      suffix = " #2]";
+      break;
+    default:
+      form = "(SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVE64BitGatherPrefetch_VectorPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = (instr->ExtractBits(20, 16) != 0)
+                         ? "'prefSVEOp, 'Pgl, ['Zn.d, #'u2016]"
+                         : "'prefSVEOp, 'Pgl, ['Zn.d]";
+
+  switch (instr->Mask(SVE64BitGatherPrefetch_VectorPlusImmMask)) {
+    case PRFB_i_p_ai_d:
+      mnemonic = "prfb";
+      break;
+    case PRFD_i_p_ai_d:
+      mnemonic = "prfd";
+      break;
+    case PRFH_i_p_ai_d:
+      mnemonic = "prfh";
+      break;
+    case PRFW_i_p_ai_d:
+      mnemonic = "prfw";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, lsl #'u2423]";
+
+  switch (instr->Mask(SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask)) {
+    case ST1D_z_p_bz_d_64_scaled:
+      mnemonic = "st1d";
+      break;
+    case ST1H_z_p_bz_d_64_scaled:
+      mnemonic = "st1h";
+      break;
+    case ST1W_z_p_bz_d_64_scaled:
+      mnemonic = "st1w";
+      break;
+    default:
+      form = "(SVE64BitScatterStore_ScalarPlus64BitScaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d]";
+
+  switch (
+      instr->Mask(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask)) {
+    case ST1B_z_p_bz_d_64_unscaled:
+      mnemonic = "st1b";
+      break;
+    case ST1D_z_p_bz_d_64_unscaled:
+      mnemonic = "st1d";
+      break;
+    case ST1H_z_p_bz_d_64_unscaled:
+      mnemonic = "st1h";
+      break;
+    case ST1W_z_p_bz_d_64_unscaled:
+      mnemonic = "st1w";
+      break;
+    default:
+      form = "(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffset)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::
+    VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets(
+        const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, '?14:suxtw #'u2423]";
+
+  switch (instr->Mask(
+      SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask)) {
+    case ST1D_z_p_bz_d_x32_scaled:
+      mnemonic = "st1d";
+      break;
+    case ST1H_z_p_bz_d_x32_scaled:
+      mnemonic = "st1h";
+      break;
+    case ST1W_z_p_bz_d_x32_scaled:
+      mnemonic = "st1w";
+      break;
+    default:
+      form = "(SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::
+    VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets(
+        const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl, ['Xns, 'Zm.d, '?14:suxtw]";
+
+  switch (instr->Mask(
+      SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask)) {
+    case ST1B_z_p_bz_d_x32_unscaled:
+      mnemonic = "st1b";
+      break;
+    case ST1D_z_p_bz_d_x32_unscaled:
+      mnemonic = "st1d";
+      break;
+    case ST1H_z_p_bz_d_x32_unscaled:
+      mnemonic = "st1h";
+      break;
+    case ST1W_z_p_bz_d_x32_unscaled:
+      mnemonic = "st1w";
+      break;
+    default:
+      form = "(SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVE64BitScatterStore_VectorPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.d}, 'Pgl, ['Zn.d";
+  const char *suffix = NULL;
+
+  bool is_zero = instr->ExtractBits(20, 16) == 0;
+
+  switch (instr->Mask(SVE64BitScatterStore_VectorPlusImmMask)) {
+    case ST1B_z_p_ai_d:
+      mnemonic = "st1b";
+      suffix = is_zero ? "]" : ", #'u2016]";
+      break;
+    case ST1D_z_p_ai_d:
+      mnemonic = "st1d";
+      suffix = is_zero ? "]" : ", #'u2016*8]";
+      break;
+    case ST1H_z_p_ai_d:
+      mnemonic = "st1h";
+      suffix = is_zero ? "]" : ", #'u2016*2]";
+      break;
+    case ST1W_z_p_ai_d:
+      mnemonic = "st1w";
+      suffix = is_zero ? "]" : ", #'u2016*4]";
+      break;
+    default:
+      form = "(SVE64BitScatterStore_VectorPlusImm)";
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEBitwiseLogicalWithImm_Unpredicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'tl, 'Zd.'tl, 'ITriSvel";
+
+  if (instr->GetSVEImmLogical() == 0) {
+    // The immediate encoded in the instruction is not in the expected format.
+    Format(instr, "unallocated", "(SVEBitwiseImm)");
+    return;
+  }
+
+  switch (instr->Mask(SVEBitwiseLogicalWithImm_UnpredicatedMask)) {
+    case AND_z_zi:
+      mnemonic = "and";
+      break;
+    case EOR_z_zi:
+      mnemonic = "eor";
+      break;
+    case ORR_z_zi:
+      mnemonic = "orr";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBitwiseLogical_Predicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEBitwiseLogical_PredicatedMask)) {
+    case AND_z_p_zz:
+      mnemonic = "and";
+      break;
+    case BIC_z_p_zz:
+      mnemonic = "bic";
+      break;
+    case EOR_z_p_zz:
+      mnemonic = "eor";
+      break;
+    case ORR_z_p_zz:
+      mnemonic = "orr";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBitwiseShiftByImm_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'tszp, 'Pgl/m, 'Zd.'tszp, 'ITriSveq";
+  unsigned tsize = (instr->ExtractBits(23, 22) << 2) | instr->ExtractBits(9, 8);
+
+  if (tsize == 0) {
+    form = "(SVEBitwiseShiftByImm_Predicated)";
+  } else {
+    switch (instr->Mask(SVEBitwiseShiftByImm_PredicatedMask)) {
+      case ASRD_z_p_zi:
+        mnemonic = "asrd";
+        break;
+      case ASR_z_p_zi:
+        mnemonic = "asr";
+        break;
+      case LSL_z_p_zi:
+        mnemonic = "lsl";
+        form = "'Zd.'tszp, p'u1210/m, 'Zd.'tszp, 'ITriSvep";
+        break;
+      case LSR_z_p_zi:
+        mnemonic = "lsr";
+        break;
+      default:
+        break;
+    }
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBitwiseShiftByVector_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEBitwiseShiftByVector_PredicatedMask)) {
+    case ASRR_z_p_zz:
+      mnemonic = "asrr";
+      break;
+    case ASR_z_p_zz:
+      mnemonic = "asr";
+      break;
+    case LSLR_z_p_zz:
+      mnemonic = "lslr";
+      break;
+    case LSL_z_p_zz:
+      mnemonic = "lsl";
+      break;
+    case LSRR_z_p_zz:
+      mnemonic = "lsrr";
+      break;
+    case LSR_z_p_zz:
+      mnemonic = "lsr";
+      break;
+    default:
+      form = "(SVEBitwiseShiftByVector_Predicated)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBitwiseShiftByWideElements_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.d";
+
+  if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
+    form = "(SVEBitwiseShiftByWideElements_Predicated)";
+  } else {
+    switch (instr->Mask(SVEBitwiseShiftByWideElements_PredicatedMask)) {
+      case ASR_z_p_zw:
+        mnemonic = "asr";
+        break;
+      case LSL_z_p_zw:
+        mnemonic = "lsl";
+        break;
+      case LSR_z_p_zw:
+        mnemonic = "lsr";
+        break;
+      default:
+        form = "(SVEBitwiseShiftByWideElements_Predicated)";
+        break;
+    }
+  }
+  Format(instr, mnemonic, form);
+}
+
+static bool SVEMoveMaskPreferred(uint64_t value, int lane_bytes_log2) {
+  VIXL_ASSERT(IsUintN(8 << lane_bytes_log2, value));
+
+  // Duplicate lane-sized value across double word.
+  switch (lane_bytes_log2) {
+    case 0:
+      value *= 0x0101010101010101;
+      break;
+    case 1:
+      value *= 0x0001000100010001;
+      break;
+    case 2:
+      value *= 0x0000000100000001;
+      break;
+    case 3:  // Nothing to do
+      break;
+    default:
+      VIXL_UNREACHABLE();
+  }
+
+  if ((value & 0xff) == 0) {
+    // Check for 16-bit patterns. Set least-significant 16 bits, to make tests
+    // easier; we already checked least-significant byte is zero above.
+    uint64_t generic_value = value | 0xffff;
+
+    // Check 0x00000000_0000pq00 or 0xffffffff_ffffpq00.
+    if ((generic_value == 0xffff) || (generic_value == UINT64_MAX)) {
+      return false;
+    }
+
+    // Check 0x0000pq00_0000pq00 or 0xffffpq00_ffffpq00.
+    uint64_t rotvalue = RotateRight(value, 32, 64);
+    if (value == rotvalue) {
+      generic_value &= 0xffffffff;
+      if ((generic_value == 0xffff) || (generic_value == UINT32_MAX)) {
+        return false;
+      }
+    }
+
+    // Check 0xpq00pq00_pq00pq00.
+    rotvalue = RotateRight(value, 16, 64);
+    if (value == rotvalue) {
+      return false;
+    }
+  } else {
+    // Check for 8-bit patterns. Set least-significant byte, to make tests
+    // easier.
+    uint64_t generic_value = value | 0xff;
+
+    // Check 0x00000000_000000pq or 0xffffffff_ffffffpq.
+    if ((generic_value == 0xff) || (generic_value == UINT64_MAX)) {
+      return false;
+    }
+
+    // Check 0x000000pq_000000pq or 0xffffffpq_ffffffpq.
+    uint64_t rotvalue = RotateRight(value, 32, 64);
+    if (value == rotvalue) {
+      generic_value &= 0xffffffff;
+      if ((generic_value == 0xff) || (generic_value == UINT32_MAX)) {
+        return false;
+      }
+    }
+
+    // Check 0x00pq00pq_00pq00pq or 0xffpqffpq_ffpqffpq.
+    rotvalue = RotateRight(value, 16, 64);
+    if (value == rotvalue) {
+      generic_value &= 0xffff;
+      if ((generic_value == 0xff) || (generic_value == UINT16_MAX)) {
+        return false;
+      }
+    }
+
+    // Check 0xpqpqpqpq_pqpqpqpq.
+    rotvalue = RotateRight(value, 8, 64);
+    if (value == rotvalue) {
+      return false;
+    }
+  }
+  return true;
+}
+
+void Disassembler::VisitSVEBroadcastBitmaskImm(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEBroadcastBitmaskImm)";
+
+  switch (instr->Mask(SVEBroadcastBitmaskImmMask)) {
+    case DUPM_z_i: {
+      uint64_t imm = instr->GetSVEImmLogical();
+      if (imm != 0) {
+        int lane_size = instr->GetSVEBitwiseImmLaneSizeInBytesLog2();
+        mnemonic = SVEMoveMaskPreferred(imm, lane_size) ? "mov" : "dupm";
+        form = "'Zd.'tl, 'ITriSvel";
+      }
+      break;
+    }
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBroadcastFPImm_Unpredicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEBroadcastFPImm_Unpredicated)";
+
+  switch (instr->Mask(SVEBroadcastFPImm_UnpredicatedMask)) {
+    case FDUP_z_i:
+      // The preferred disassembly for fdup is "fmov".
+      mnemonic = "fmov";
+      form = "'Zd.'t, 'IFPSve";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBroadcastGeneralRegister(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEBroadcastGeneralRegister)";
+
+  switch (instr->Mask(SVEBroadcastGeneralRegisterMask)) {
+    case DUP_z_r:
+      // The preferred disassembly for dup is "mov".
+      mnemonic = "mov";
+      if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
+        form = "'Zd.'t, 'Xns";
+      } else {
+        form = "'Zd.'t, 'Wns";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBroadcastIndexElement(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEBroadcastIndexElement)";
+
+  switch (instr->Mask(SVEBroadcastIndexElementMask)) {
+    case DUP_z_zi: {
+      // The tsz field must not be zero.
+      int tsz = instr->ExtractBits(20, 16);
+      if (tsz != 0) {
+        // The preferred disassembly for dup is "mov".
+        mnemonic = "mov";
+        int imm2 = instr->ExtractBits(23, 22);
+        if ((CountSetBits(imm2) + CountSetBits(tsz)) == 1) {
+          // If imm2:tsz has one set bit, the index is zero. This is
+          // disassembled as a mov from a b/h/s/d/q scalar register.
+          form = "'Zd.'tszx, 'tszx'u0905";
+        } else {
+          form = "'Zd.'tszx, 'Zn.'tszx['IVInsSVEIndex]";
+        }
+      }
+      break;
+    }
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBroadcastIntImm_Unpredicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEBroadcastIntImm_Unpredicated)";
+
+  switch (instr->Mask(SVEBroadcastIntImm_UnpredicatedMask)) {
+    case DUP_z_i:
+      // The encoding of byte-sized lanes with lsl #8 is undefined.
+      if ((instr->GetSVEVectorFormat() == kFormatVnB) &&
+          (instr->ExtractBit(13) == 1))
+        break;
+
+      // The preferred disassembly for dup is "mov".
+      mnemonic = "mov";
+      form = (instr->ExtractBit(13) == 0) ? "'Zd.'t, #'s1205"
+                                          : "'Zd.'t, #'s1205, lsl #8";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVECompressActiveElements(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVECompressActiveElements)";
+
+  switch (instr->Mask(SVECompressActiveElementsMask)) {
+    case COMPACT_z_p_z:
+      // The top bit of size is always set for compact, so 't can only be
+      // substituted with types S and D.
+      VIXL_ASSERT(instr->ExtractBit(23) == 1);
+      mnemonic = "compact";
+      form = "'Zd.'t, 'Pgl, 'Zn.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEConditionallyBroadcastElementToVector(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl, 'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEConditionallyBroadcastElementToVectorMask)) {
+    case CLASTA_z_p_zz:
+      mnemonic = "clasta";
+      break;
+    case CLASTB_z_p_zz:
+      mnemonic = "clastb";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEConditionallyExtractElementToGeneralRegister(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Wd, 'Pgl, 'Wd, 'Zn.'t";
+
+  if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
+    form = "'Xd, p'u1210, 'Xd, 'Zn.'t";
+  }
+
+  switch (instr->Mask(SVEConditionallyExtractElementToGeneralRegisterMask)) {
+    case CLASTA_r_p_z:
+      mnemonic = "clasta";
+      break;
+    case CLASTB_r_p_z:
+      mnemonic = "clastb";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEConditionallyExtractElementToSIMDFPScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'t'u0400, 'Pgl, 't'u0400, 'Zn.'t";
+
+  switch (instr->Mask(SVEConditionallyExtractElementToSIMDFPScalarMask)) {
+    case CLASTA_v_p_z:
+      mnemonic = "clasta";
+      break;
+    case CLASTB_v_p_z:
+      mnemonic = "clastb";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEConditionallyTerminateScalars(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = (instr->ExtractBit(22) == 0) ? "'Wn, 'Wm" : "'Xn, 'Xm";
+
+  switch (instr->Mask(SVEConditionallyTerminateScalarsMask)) {
+    case CTERMEQ_rr:
+      mnemonic = "ctermeq";
+      break;
+    case CTERMNE_rr:
+      mnemonic = "ctermne";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEConstructivePrefix_Unpredicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEConstructivePrefix_Unpredicated)";
+
+  switch (instr->Mask(SVEConstructivePrefix_UnpredicatedMask)) {
+    case MOVPRFX_z_z:
+      mnemonic = "movprfx";
+      form = "'Zd, 'Zn";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+
+  bool rm_is_zr = instr->GetRm() == kZeroRegCode;
+
+  const char *form = "{'Zt.'tlss}, 'Pgl/z, ['Xns";
+  const char *suffix = NULL;
+
+  switch (instr->Mask(SVEContiguousFirstFaultLoad_ScalarPlusScalarMask)) {
+    case LDFF1B_z_p_br_u16:
+    case LDFF1B_z_p_br_u32:
+    case LDFF1B_z_p_br_u64:
+    case LDFF1B_z_p_br_u8:
+      mnemonic = "ldff1b";
+      suffix = rm_is_zr ? "]" : ", 'Xm]";
+      break;
+    case LDFF1D_z_p_br_u64:
+      mnemonic = "ldff1d";
+      suffix = rm_is_zr ? "]" : ", 'Xm, lsl #3]";
+      break;
+    case LDFF1H_z_p_br_u16:
+    case LDFF1H_z_p_br_u32:
+    case LDFF1H_z_p_br_u64:
+      mnemonic = "ldff1h";
+      suffix = rm_is_zr ? "]" : ", 'Xm, lsl #1]";
+      break;
+    case LDFF1SB_z_p_br_s16:
+    case LDFF1SB_z_p_br_s32:
+    case LDFF1SB_z_p_br_s64:
+      mnemonic = "ldff1sb";
+      suffix = rm_is_zr ? "]" : ", 'Xm]";
+      break;
+    case LDFF1SH_z_p_br_s32:
+    case LDFF1SH_z_p_br_s64:
+      mnemonic = "ldff1sh";
+      suffix = rm_is_zr ? "]" : ", 'Xm, lsl #1]";
+      break;
+    case LDFF1SW_z_p_br_s64:
+      mnemonic = "ldff1sw";
+      suffix = rm_is_zr ? "]" : ", 'Xm, lsl #2]";
+      break;
+    case LDFF1W_z_p_br_u32:
+    case LDFF1W_z_p_br_u64:
+      mnemonic = "ldff1w";
+      suffix = rm_is_zr ? "]" : ", 'Xm, lsl #2]";
+      break;
+    default:
+      form = "(SVEContiguousFirstFaultLoad_ScalarPlusScalar)";
+      break;
+  }
+
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEContiguousNonFaultLoad_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.'tlss}, 'Pgl/z, ['Xns";
+  const char *suffix =
+      (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
+
+  switch (instr->Mask(SVEContiguousNonFaultLoad_ScalarPlusImmMask)) {
+    case LDNF1B_z_p_bi_u16:
+    case LDNF1B_z_p_bi_u32:
+    case LDNF1B_z_p_bi_u64:
+    case LDNF1B_z_p_bi_u8:
+      mnemonic = "ldnf1b";
+      break;
+    case LDNF1D_z_p_bi_u64:
+      mnemonic = "ldnf1d";
+      break;
+    case LDNF1H_z_p_bi_u16:
+    case LDNF1H_z_p_bi_u32:
+    case LDNF1H_z_p_bi_u64:
+      mnemonic = "ldnf1h";
+      break;
+    case LDNF1SB_z_p_bi_s16:
+    case LDNF1SB_z_p_bi_s32:
+    case LDNF1SB_z_p_bi_s64:
+      mnemonic = "ldnf1sb";
+      break;
+    case LDNF1SH_z_p_bi_s32:
+    case LDNF1SH_z_p_bi_s64:
+      mnemonic = "ldnf1sh";
+      break;
+    case LDNF1SW_z_p_bi_s64:
+      mnemonic = "ldnf1sw";
+      break;
+    case LDNF1W_z_p_bi_u32:
+    case LDNF1W_z_p_bi_u64:
+      mnemonic = "ldnf1w";
+      break;
+    default:
+      form = "(SVEContiguousNonFaultLoad_ScalarPlusImm)";
+      suffix = NULL;
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEContiguousNonTemporalLoad_ScalarPlusImm)";
+
+  const char *suffix =
+      (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
+  switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusImmMask)) {
+    case LDNT1B_z_p_bi_contiguous:
+      mnemonic = "ldnt1b";
+      form = "{'Zt.b}, 'Pgl/z, ['Xns";
+      break;
+    case LDNT1D_z_p_bi_contiguous:
+      mnemonic = "ldnt1d";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      break;
+    case LDNT1H_z_p_bi_contiguous:
+      mnemonic = "ldnt1h";
+      form = "{'Zt.h}, 'Pgl/z, ['Xns";
+      break;
+    case LDNT1W_z_p_bi_contiguous:
+      mnemonic = "ldnt1w";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns";
+      break;
+    default:
+      suffix = NULL;
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEContiguousNonTemporalLoad_ScalarPlusScalar)";
+
+  switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusScalarMask)) {
+    case LDNT1B_z_p_br_contiguous:
+      mnemonic = "ldnt1b";
+      form = "{'Zt.b}, 'Pgl/z, ['Xns, 'Rm]";
+      break;
+    case LDNT1D_z_p_br_contiguous:
+      mnemonic = "ldnt1d";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Rm, lsl #3]";
+      break;
+    case LDNT1H_z_p_br_contiguous:
+      mnemonic = "ldnt1h";
+      form = "{'Zt.h}, 'Pgl/z, ['Xns, 'Rm, lsl #1]";
+      break;
+    case LDNT1W_z_p_br_contiguous:
+      mnemonic = "ldnt1w";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Rm, lsl #2]";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEContiguousNonTemporalStore_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEContiguousNonTemporalStore_ScalarPlusImm)";
+
+  const char *suffix =
+      (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
+  switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusImmMask)) {
+    case STNT1B_z_p_bi_contiguous:
+      mnemonic = "stnt1b";
+      form = "{'Zt.b}, 'Pgl, ['Xns";
+      break;
+    case STNT1D_z_p_bi_contiguous:
+      mnemonic = "stnt1d";
+      form = "{'Zt.d}, 'Pgl, ['Xns";
+      break;
+    case STNT1H_z_p_bi_contiguous:
+      mnemonic = "stnt1h";
+      form = "{'Zt.h}, 'Pgl, ['Xns";
+      break;
+    case STNT1W_z_p_bi_contiguous:
+      mnemonic = "stnt1w";
+      form = "{'Zt.s}, 'Pgl, ['Xns";
+      break;
+    default:
+      suffix = NULL;
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEContiguousNonTemporalStore_ScalarPlusScalar)";
+
+  switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusScalarMask)) {
+    case STNT1B_z_p_br_contiguous:
+      mnemonic = "stnt1b";
+      form = "{'Zt.b}, 'Pgl, ['Xns, 'Rm]";
+      break;
+    case STNT1D_z_p_br_contiguous:
+      mnemonic = "stnt1d";
+      form = "{'Zt.d}, 'Pgl, ['Xns, 'Rm, lsl #3]";
+      break;
+    case STNT1H_z_p_br_contiguous:
+      mnemonic = "stnt1h";
+      form = "{'Zt.h}, 'Pgl, ['Xns, 'Rm, lsl #1]";
+      break;
+    case STNT1W_z_p_br_contiguous:
+      mnemonic = "stnt1w";
+      form = "{'Zt.s}, 'Pgl, ['Xns, 'Rm, lsl #2]";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEContiguousPrefetch_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = (instr->ExtractBits(21, 16) != 0)
+                         ? "'prefSVEOp, 'Pgl, ['Xns, #'s2116, mul vl]"
+                         : "'prefSVEOp, 'Pgl, ['Xns]";
+
+  switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusImmMask)) {
+    case PRFB_i_p_bi_s:
+      mnemonic = "prfb";
+      break;
+    case PRFD_i_p_bi_s:
+      mnemonic = "prfd";
+      break;
+    case PRFH_i_p_bi_s:
+      mnemonic = "prfh";
+      break;
+    case PRFW_i_p_bi_s:
+      mnemonic = "prfw";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEContiguousPrefetch_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEContiguousPrefetch_ScalarPlusScalar)";
+
+  if (instr->GetRm() != kZeroRegCode) {
+    switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusScalarMask)) {
+      case PRFB_i_p_br_s:
+        mnemonic = "prfb";
+        form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm]";
+        break;
+      case PRFD_i_p_br_s:
+        mnemonic = "prfd";
+        form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #3]";
+        break;
+      case PRFH_i_p_br_s:
+        mnemonic = "prfh";
+        form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #1]";
+        break;
+      case PRFW_i_p_br_s:
+        mnemonic = "prfw";
+        form = "'prefSVEOp, 'Pgl, ['Xns, 'Rm, lsl #2]";
+        break;
+      default:
+        break;
+    }
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEContiguousStore_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+
+  // The 'size' field isn't in the usual place here.
+  const char *form = "{'Zt.'tls}, 'Pgl, ['Xns, #'s1916, mul vl]";
+  if (instr->ExtractBits(19, 16) == 0) {
+    form = "{'Zt.'tls}, 'Pgl, ['Xns]";
+  }
+
+  switch (instr->Mask(SVEContiguousStore_ScalarPlusImmMask)) {
+    case ST1B_z_p_bi:
+      mnemonic = "st1b";
+      break;
+    case ST1D_z_p_bi:
+      mnemonic = "st1d";
+      break;
+    case ST1H_z_p_bi:
+      mnemonic = "st1h";
+      break;
+    case ST1W_z_p_bi:
+      mnemonic = "st1w";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEContiguousStore_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+
+  // The 'size' field isn't in the usual place here.
+  const char *form = "{'Zt.'tls}, 'Pgl, ['Xns, 'Xm'NSveS]";
+
+  switch (instr->Mask(SVEContiguousStore_ScalarPlusScalarMask)) {
+    case ST1B_z_p_br:
+      mnemonic = "st1b";
+      break;
+    case ST1D_z_p_br:
+      mnemonic = "st1d";
+      break;
+    case ST1H_z_p_br:
+      mnemonic = "st1h";
+      break;
+    case ST1W_z_p_br:
+      mnemonic = "st1w";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVECopyFPImm_Predicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVECopyFPImm_Predicated)";
+
+  switch (instr->Mask(SVECopyFPImm_PredicatedMask)) {
+    case FCPY_z_p_i:
+      // The preferred disassembly for fcpy is "fmov".
+      mnemonic = "fmov";
+      form = "'Zd.'t, 'Pm/m, 'IFPSve";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVECopyGeneralRegisterToVector_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVECopyGeneralRegisterToVector_Predicated)";
+
+  switch (instr->Mask(SVECopyGeneralRegisterToVector_PredicatedMask)) {
+    case CPY_z_p_r:
+      // The preferred disassembly for cpy is "mov".
+      mnemonic = "mov";
+      form = "'Zd.'t, 'Pgl/m, 'Wns";
+      if (instr->GetSVESize() == kXRegSizeInBytesLog2) {
+        form = "'Zd.'t, 'Pgl/m, 'Xns";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVECopyIntImm_Predicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVECopyIntImm_Predicated)";
+  const char *suffix = NULL;
+
+  switch (instr->Mask(SVECopyIntImm_PredicatedMask)) {
+    case CPY_z_p_i: {
+      // The preferred disassembly for cpy is "mov".
+      mnemonic = "mov";
+      form = "'Zd.'t, 'Pm/'?14:mz, #'s1205";
+      if (instr->ExtractBit(13) != 0) suffix = ", lsl #8";
+      break;
+    }
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVECopySIMDFPScalarRegisterToVector_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVECopySIMDFPScalarRegisterToVector_Predicated)";
+
+  switch (instr->Mask(SVECopySIMDFPScalarRegisterToVector_PredicatedMask)) {
+    case CPY_z_p_v:
+      // The preferred disassembly for cpy is "mov".
+      mnemonic = "mov";
+      form = "'Zd.'t, 'Pgl/m, 'Vnv";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEExtractElementToGeneralRegister(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Wd, 'Pgl, 'Zn.'t";
+
+  if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
+    form = "'Xd, p'u1210, 'Zn.'t";
+  }
+
+  switch (instr->Mask(SVEExtractElementToGeneralRegisterMask)) {
+    case LASTA_r_p_z:
+      mnemonic = "lasta";
+      break;
+    case LASTB_r_p_z:
+      mnemonic = "lastb";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEExtractElementToSIMDFPScalarRegister(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'t'u0400, 'Pgl, 'Zn.'t";
+
+  switch (instr->Mask(SVEExtractElementToSIMDFPScalarRegisterMask)) {
+    case LASTA_v_p_z:
+      mnemonic = "lasta";
+      break;
+    case LASTB_v_p_z:
+      mnemonic = "lastb";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFFRInitialise(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFFRInitialise)";
+
+  switch (instr->Mask(SVEFFRInitialiseMask)) {
+    case SETFFR_f:
+      mnemonic = "setffr";
+      form = " ";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFFRWriteFromPredicate(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFFRWriteFromPredicate)";
+
+  switch (instr->Mask(SVEFFRWriteFromPredicateMask)) {
+    case WRFFR_f_p:
+      mnemonic = "wrffr";
+      form = "'Pn.b";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPArithmeticWithImm_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form00 = "'Zd.'t, 'Pgl/m, 'Zd.'t, #0.0";
+  const char *form05 = "'Zd.'t, 'Pgl/m, 'Zd.'t, #0.5";
+  const char *form10 = "'Zd.'t, 'Pgl/m, 'Zd.'t, #1.0";
+  const char *form20 = "'Zd.'t, 'Pgl/m, 'Zd.'t, #2.0";
+  int i1 = instr->ExtractBit(5);
+  const char *form = i1 ? form10 : form00;
+
+  switch (instr->Mask(SVEFPArithmeticWithImm_PredicatedMask)) {
+    case FADD_z_p_zs:
+      mnemonic = "fadd";
+      form = i1 ? form10 : form05;
+      break;
+    case FMAXNM_z_p_zs:
+      mnemonic = "fmaxnm";
+      break;
+    case FMAX_z_p_zs:
+      mnemonic = "fmax";
+      break;
+    case FMINNM_z_p_zs:
+      mnemonic = "fminnm";
+      break;
+    case FMIN_z_p_zs:
+      mnemonic = "fmin";
+      break;
+    case FMUL_z_p_zs:
+      mnemonic = "fmul";
+      form = i1 ? form20 : form05;
+      break;
+    case FSUBR_z_p_zs:
+      mnemonic = "fsubr";
+      form = i1 ? form10 : form05;
+      break;
+    case FSUB_z_p_zs:
+      mnemonic = "fsub";
+      form = i1 ? form10 : form05;
+      break;
+    default:
+      form = "(SVEFPArithmeticWithImm_Predicated)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPArithmetic_Predicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEFPArithmetic_PredicatedMask)) {
+    case FABD_z_p_zz:
+      mnemonic = "fabd";
+      break;
+    case FADD_z_p_zz:
+      mnemonic = "fadd";
+      break;
+    case FDIVR_z_p_zz:
+      mnemonic = "fdivr";
+      break;
+    case FDIV_z_p_zz:
+      mnemonic = "fdiv";
+      break;
+    case FMAXNM_z_p_zz:
+      mnemonic = "fmaxnm";
+      break;
+    case FMAX_z_p_zz:
+      mnemonic = "fmax";
+      break;
+    case FMINNM_z_p_zz:
+      mnemonic = "fminnm";
+      break;
+    case FMIN_z_p_zz:
+      mnemonic = "fmin";
+      break;
+    case FMULX_z_p_zz:
+      mnemonic = "fmulx";
+      break;
+    case FMUL_z_p_zz:
+      mnemonic = "fmul";
+      break;
+    case FSCALE_z_p_zz:
+      mnemonic = "fscale";
+      break;
+    case FSUBR_z_p_zz:
+      mnemonic = "fsubr";
+      break;
+    case FSUB_z_p_zz:
+      mnemonic = "fsub";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPConvertPrecision(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPConvertPrecision)";
+
+  switch (instr->Mask(SVEFPConvertPrecisionMask)) {
+    case FCVT_z_p_z_d2h:
+      mnemonic = "fcvt";
+      form = "'Zd.h, 'Pgl/m, 'Zn.d";
+      break;
+    case FCVT_z_p_z_d2s:
+      mnemonic = "fcvt";
+      form = "'Zd.s, 'Pgl/m, 'Zn.d";
+      break;
+    case FCVT_z_p_z_h2d:
+      mnemonic = "fcvt";
+      form = "'Zd.d, 'Pgl/m, 'Zn.h";
+      break;
+    case FCVT_z_p_z_h2s:
+      mnemonic = "fcvt";
+      form = "'Zd.s, 'Pgl/m, 'Zn.h";
+      break;
+    case FCVT_z_p_z_s2d:
+      mnemonic = "fcvt";
+      form = "'Zd.d, 'Pgl/m, 'Zn.s";
+      break;
+    case FCVT_z_p_z_s2h:
+      mnemonic = "fcvt";
+      form = "'Zd.h, 'Pgl/m, 'Zn.s";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPConvertToInt(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPConvertToInt)";
+
+  switch (instr->Mask(SVEFPConvertToIntMask)) {
+    case FCVTZS_z_p_z_d2w:
+      mnemonic = "fcvtzs";
+      form = "'Zd.s, 'Pgl/m, 'Zn.d";
+      break;
+    case FCVTZS_z_p_z_d2x:
+      mnemonic = "fcvtzs";
+      form = "'Zd.d, 'Pgl/m, 'Zn.d";
+      break;
+    case FCVTZS_z_p_z_fp162h:
+      mnemonic = "fcvtzs";
+      form = "'Zd.h, 'Pgl/m, 'Zn.h";
+      break;
+    case FCVTZS_z_p_z_fp162w:
+      mnemonic = "fcvtzs";
+      form = "'Zd.s, 'Pgl/m, 'Zn.h";
+      break;
+    case FCVTZS_z_p_z_fp162x:
+      mnemonic = "fcvtzs";
+      form = "'Zd.d, 'Pgl/m, 'Zn.h";
+      break;
+    case FCVTZS_z_p_z_s2w:
+      mnemonic = "fcvtzs";
+      form = "'Zd.s, 'Pgl/m, 'Zn.s";
+      break;
+    case FCVTZS_z_p_z_s2x:
+      mnemonic = "fcvtzs";
+      form = "'Zd.d, 'Pgl/m, 'Zn.s";
+      break;
+    case FCVTZU_z_p_z_d2w:
+      mnemonic = "fcvtzu";
+      form = "'Zd.s, 'Pgl/m, 'Zn.d";
+      break;
+    case FCVTZU_z_p_z_d2x:
+      mnemonic = "fcvtzu";
+      form = "'Zd.d, 'Pgl/m, 'Zn.d";
+      break;
+    case FCVTZU_z_p_z_fp162h:
+      mnemonic = "fcvtzu";
+      form = "'Zd.h, 'Pgl/m, 'Zn.h";
+      break;
+    case FCVTZU_z_p_z_fp162w:
+      mnemonic = "fcvtzu";
+      form = "'Zd.s, 'Pgl/m, 'Zn.h";
+      break;
+    case FCVTZU_z_p_z_fp162x:
+      mnemonic = "fcvtzu";
+      form = "'Zd.d, 'Pgl/m, 'Zn.h";
+      break;
+    case FCVTZU_z_p_z_s2w:
+      mnemonic = "fcvtzu";
+      form = "'Zd.s, 'Pgl/m, 'Zn.s";
+      break;
+    case FCVTZU_z_p_z_s2x:
+      mnemonic = "fcvtzu";
+      form = "'Zd.d, 'Pgl/m, 'Zn.s";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPExponentialAccelerator(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPExponentialAccelerator)";
+
+  unsigned size = instr->GetSVESize();
+  switch (instr->Mask(SVEFPExponentialAcceleratorMask)) {
+    case FEXPA_z_z:
+      if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
+          (size == kDRegSizeInBytesLog2)) {
+        mnemonic = "fexpa";
+        form = "'Zd.'t, 'Zn.'t";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPRoundToIntegralValue(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t";
+
+  switch (instr->Mask(SVEFPRoundToIntegralValueMask)) {
+    case FRINTA_z_p_z:
+      mnemonic = "frinta";
+      break;
+    case FRINTI_z_p_z:
+      mnemonic = "frinti";
+      break;
+    case FRINTM_z_p_z:
+      mnemonic = "frintm";
+      break;
+    case FRINTN_z_p_z:
+      mnemonic = "frintn";
+      break;
+    case FRINTP_z_p_z:
+      mnemonic = "frintp";
+      break;
+    case FRINTX_z_p_z:
+      mnemonic = "frintx";
+      break;
+    case FRINTZ_z_p_z:
+      mnemonic = "frintz";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPTrigMulAddCoefficient(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPTrigMulAddCoefficient)";
+
+  unsigned size = instr->GetSVESize();
+  switch (instr->Mask(SVEFPTrigMulAddCoefficientMask)) {
+    case FTMAD_z_zzi:
+      if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
+          (size == kDRegSizeInBytesLog2)) {
+        mnemonic = "ftmad";
+        form = "'Zd.'t, 'Zd.'t, 'Zn.'t, #'u1816";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPTrigSelectCoefficient(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPTrigSelectCoefficient)";
+
+  unsigned size = instr->GetSVESize();
+  switch (instr->Mask(SVEFPTrigSelectCoefficientMask)) {
+    case FTSSEL_z_zz:
+      if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
+          (size == kDRegSizeInBytesLog2)) {
+        mnemonic = "ftssel";
+        form = "'Zd.'t, 'Zn.'t, 'Zm.'t";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPUnaryOp(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t";
+
+  if (instr->GetSVESize() == kBRegSizeInBytesLog2) {
+    form = "(SVEFPUnaryOp)";
+  } else {
+    switch (instr->Mask(SVEFPUnaryOpMask)) {
+      case FRECPX_z_p_z:
+        mnemonic = "frecpx";
+        break;
+      case FSQRT_z_p_z:
+        mnemonic = "fsqrt";
+        break;
+      default:
+        form = "(SVEFPUnaryOp)";
+        break;
+    }
+  }
+  Format(instr, mnemonic, form);
+}
+
+static const char *IncDecFormHelper(const Instruction *instr,
+                                    const char *reg_pat_mul_form,
+                                    const char *reg_pat_form,
+                                    const char *reg_form) {
+  if (instr->ExtractBits(19, 16) == 0) {
+    if (instr->ExtractBits(9, 5) == SVE_ALL) {
+      // Use the register only form if the multiplier is one (encoded as zero)
+      // and the pattern is SVE_ALL.
+      return reg_form;
+    }
+    // Use the register and pattern form if the multiplier is one.
+    return reg_pat_form;
+  }
+  return reg_pat_mul_form;
+}
+
+void Disassembler::VisitSVEIncDecRegisterByElementCount(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form =
+      IncDecFormHelper(instr, "'Xd, 'Ipc, mul #'u1916+1", "'Xd, 'Ipc", "'Xd");
+
+  switch (instr->Mask(SVEIncDecRegisterByElementCountMask)) {
+    case DECB_r_rs:
+      mnemonic = "decb";
+      break;
+    case DECD_r_rs:
+      mnemonic = "decd";
+      break;
+    case DECH_r_rs:
+      mnemonic = "dech";
+      break;
+    case DECW_r_rs:
+      mnemonic = "decw";
+      break;
+    case INCB_r_rs:
+      mnemonic = "incb";
+      break;
+    case INCD_r_rs:
+      mnemonic = "incd";
+      break;
+    case INCH_r_rs:
+      mnemonic = "inch";
+      break;
+    case INCW_r_rs:
+      mnemonic = "incw";
+      break;
+    default:
+      form = "(SVEIncDecRegisterByElementCount)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIncDecVectorByElementCount(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = IncDecFormHelper(instr,
+                                      "'Zd.'t, 'Ipc, mul #'u1916+1",
+                                      "'Zd.'t, 'Ipc",
+                                      "'Zd.'t");
+
+  switch (instr->Mask(SVEIncDecVectorByElementCountMask)) {
+    case DECD_z_zs:
+      mnemonic = "decd";
+      break;
+    case DECH_z_zs:
+      mnemonic = "dech";
+      break;
+    case DECW_z_zs:
+      mnemonic = "decw";
+      break;
+    case INCD_z_zs:
+      mnemonic = "incd";
+      break;
+    case INCH_z_zs:
+      mnemonic = "inch";
+      break;
+    case INCW_z_zs:
+      mnemonic = "incw";
+      break;
+    default:
+      form = "(SVEIncDecVectorByElementCount)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEInsertGeneralRegister(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEInsertGeneralRegister)";
+
+  switch (instr->Mask(SVEInsertGeneralRegisterMask)) {
+    case INSR_z_r:
+      mnemonic = "insr";
+      if (instr->GetSVESize() == kDRegSizeInBytesLog2) {
+        form = "'Zd.'t, 'Xn";
+      } else {
+        form = "'Zd.'t, 'Wn";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEInsertSIMDFPScalarRegister(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEInsertSIMDFPScalarRegister)";
+
+  switch (instr->Mask(SVEInsertSIMDFPScalarRegisterMask)) {
+    case INSR_z_v:
+      mnemonic = "insr";
+      form = "'Zd.'t, 'Vnv";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntAddSubtractImm_Unpredicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = (instr->ExtractBit(13) == 0)
+                         ? "'Zd.'t, 'Zd.'t, #'u1205"
+                         : "'Zd.'t, 'Zd.'t, #'u1205, lsl #8";
+
+  switch (instr->Mask(SVEIntAddSubtractImm_UnpredicatedMask)) {
+    case ADD_z_zi:
+      mnemonic = "add";
+      break;
+    case SQADD_z_zi:
+      mnemonic = "sqadd";
+      break;
+    case SQSUB_z_zi:
+      mnemonic = "sqsub";
+      break;
+    case SUBR_z_zi:
+      mnemonic = "subr";
+      break;
+    case SUB_z_zi:
+      mnemonic = "sub";
+      break;
+    case UQADD_z_zi:
+      mnemonic = "uqadd";
+      break;
+    case UQSUB_z_zi:
+      mnemonic = "uqsub";
+      break;
+    default:
+      form = "(SVEIntAddSubtractImm_Unpredicated)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntAddSubtractVectors_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEIntAddSubtractVectors_PredicatedMask)) {
+    case ADD_z_p_zz:
+      mnemonic = "add";
+      break;
+    case SUBR_z_p_zz:
+      mnemonic = "subr";
+      break;
+    case SUB_z_p_zz:
+      mnemonic = "sub";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntCompareScalarCountAndLimit(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form =
+      (instr->ExtractBit(12) == 0) ? "'Pd.'t, 'Wn, 'Wm" : "'Pd.'t, 'Xn, 'Xm";
+
+  switch (instr->Mask(SVEIntCompareScalarCountAndLimitMask)) {
+    case WHILELE_p_p_rr:
+      mnemonic = "whilele";
+      break;
+    case WHILELO_p_p_rr:
+      mnemonic = "whilelo";
+      break;
+    case WHILELS_p_p_rr:
+      mnemonic = "whilels";
+      break;
+    case WHILELT_p_p_rr:
+      mnemonic = "whilelt";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntConvertToFP(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEIntConvertToFP)";
+
+  switch (instr->Mask(SVEIntConvertToFPMask)) {
+    case SCVTF_z_p_z_h2fp16:
+      mnemonic = "scvtf";
+      form = "'Zd.h, 'Pgl/m, 'Zn.h";
+      break;
+    case SCVTF_z_p_z_w2d:
+      mnemonic = "scvtf";
+      form = "'Zd.d, 'Pgl/m, 'Zn.s";
+      break;
+    case SCVTF_z_p_z_w2fp16:
+      mnemonic = "scvtf";
+      form = "'Zd.h, 'Pgl/m, 'Zn.s";
+      break;
+    case SCVTF_z_p_z_w2s:
+      mnemonic = "scvtf";
+      form = "'Zd.s, 'Pgl/m, 'Zn.s";
+      break;
+    case SCVTF_z_p_z_x2d:
+      mnemonic = "scvtf";
+      form = "'Zd.d, 'Pgl/m, 'Zn.d";
+      break;
+    case SCVTF_z_p_z_x2fp16:
+      mnemonic = "scvtf";
+      form = "'Zd.h, 'Pgl/m, 'Zn.d";
+      break;
+    case SCVTF_z_p_z_x2s:
+      mnemonic = "scvtf";
+      form = "'Zd.s, 'Pgl/m, 'Zn.d";
+      break;
+    case UCVTF_z_p_z_h2fp16:
+      mnemonic = "ucvtf";
+      form = "'Zd.h, 'Pgl/m, 'Zn.h";
+      break;
+    case UCVTF_z_p_z_w2d:
+      mnemonic = "ucvtf";
+      form = "'Zd.d, 'Pgl/m, 'Zn.s";
+      break;
+    case UCVTF_z_p_z_w2fp16:
+      mnemonic = "ucvtf";
+      form = "'Zd.h, 'Pgl/m, 'Zn.s";
+      break;
+    case UCVTF_z_p_z_w2s:
+      mnemonic = "ucvtf";
+      form = "'Zd.s, 'Pgl/m, 'Zn.s";
+      break;
+    case UCVTF_z_p_z_x2d:
+      mnemonic = "ucvtf";
+      form = "'Zd.d, 'Pgl/m, 'Zn.d";
+      break;
+    case UCVTF_z_p_z_x2fp16:
+      mnemonic = "ucvtf";
+      form = "'Zd.h, 'Pgl/m, 'Zn.d";
+      break;
+    case UCVTF_z_p_z_x2s:
+      mnemonic = "ucvtf";
+      form = "'Zd.s, 'Pgl/m, 'Zn.d";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntDivideVectors_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEIntDivideVectors_PredicatedMask)) {
+    case SDIVR_z_p_zz:
+      mnemonic = "sdivr";
+      break;
+    case SDIV_z_p_zz:
+      mnemonic = "sdiv";
+      break;
+    case UDIVR_z_p_zz:
+      mnemonic = "udivr";
+      break;
+    case UDIV_z_p_zz:
+      mnemonic = "udiv";
+      break;
+    default:
+      break;
+  }
+
+  switch (instr->Mask(SVEIntDivideVectors_PredicatedMask)) {
+    case SDIVR_z_p_zz:
+    case SDIV_z_p_zz:
+    case UDIVR_z_p_zz:
+    case UDIV_z_p_zz:
+      switch (instr->GetSVESize()) {
+        case kBRegSizeInBytesLog2:
+        case kHRegSizeInBytesLog2:
+          mnemonic = "unimplemented";
+          form = "(SVEIntBinaryArithmeticPredicated)";
+          break;
+        case kSRegSizeInBytesLog2:
+        case kDRegSizeInBytesLog2:
+          // The default form works for these instructions.
+          break;
+        default:
+          // GetSVESize() should never return other values.
+          VIXL_UNREACHABLE();
+          break;
+      }
+  }
+
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntMinMaxDifference_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEIntMinMaxDifference_PredicatedMask)) {
+    case SABD_z_p_zz:
+      mnemonic = "sabd";
+      break;
+    case SMAX_z_p_zz:
+      mnemonic = "smax";
+      break;
+    case SMIN_z_p_zz:
+      mnemonic = "smin";
+      break;
+    case UABD_z_p_zz:
+      mnemonic = "uabd";
+      break;
+    case UMAX_z_p_zz:
+      mnemonic = "umax";
+      break;
+    case UMIN_z_p_zz:
+      mnemonic = "umin";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntMinMaxImm_Unpredicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Zd.'t, #'u1205";
+
+  switch (instr->Mask(SVEIntMinMaxImm_UnpredicatedMask)) {
+    case SMAX_z_zi:
+      mnemonic = "smax";
+      form = "'Zd.'t, 'Zd.'t, #'s1205";
+      break;
+    case SMIN_z_zi:
+      mnemonic = "smin";
+      form = "'Zd.'t, 'Zd.'t, #'s1205";
+      break;
+    case UMAX_z_zi:
+      mnemonic = "umax";
+      break;
+    case UMIN_z_zi:
+      mnemonic = "umin";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntMulImm_Unpredicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEIntMulImm_Unpredicated)";
+
+  switch (instr->Mask(SVEIntMulImm_UnpredicatedMask)) {
+    case MUL_z_zi:
+      mnemonic = "mul";
+      form = "'Zd.'t, 'Zd.'t, #'s1205";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntMulVectors_Predicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEIntMulVectors_PredicatedMask)) {
+    case MUL_z_p_zz:
+      mnemonic = "mul";
+      break;
+    case SMULH_z_p_zz:
+      mnemonic = "smulh";
+      break;
+    case UMULH_z_p_zz:
+      mnemonic = "umulh";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVELoadAndBroadcastElement(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVELoadAndBroadcastElement)";
+  const char *suffix_b = ", #'u2116]";
+  const char *suffix_h = ", #'u2116*2]";
+  const char *suffix_w = ", #'u2116*4]";
+  const char *suffix_d = ", #'u2116*8]";
+  const char *suffix = NULL;
+
+  switch (instr->Mask(SVELoadAndBroadcastElementMask)) {
+    case LD1RB_z_p_bi_u16:
+      mnemonic = "ld1rb";
+      form = "{'Zt.h}, 'Pgl/z, ['Xns";
+      suffix = suffix_b;
+      break;
+    case LD1RB_z_p_bi_u32:
+      mnemonic = "ld1rb";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns";
+      suffix = suffix_b;
+      break;
+    case LD1RB_z_p_bi_u64:
+      mnemonic = "ld1rb";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      suffix = suffix_b;
+      break;
+    case LD1RB_z_p_bi_u8:
+      mnemonic = "ld1rb";
+      form = "{'Zt.b}, 'Pgl/z, ['Xns";
+      suffix = suffix_b;
+      break;
+    case LD1RD_z_p_bi_u64:
+      mnemonic = "ld1rd";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      suffix = suffix_d;
+      break;
+    case LD1RH_z_p_bi_u16:
+      mnemonic = "ld1rh";
+      form = "{'Zt.h}, 'Pgl/z, ['Xns";
+      suffix = suffix_h;
+      break;
+    case LD1RH_z_p_bi_u32:
+      mnemonic = "ld1rh";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns";
+      suffix = suffix_h;
+      break;
+    case LD1RH_z_p_bi_u64:
+      mnemonic = "ld1rh";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      suffix = suffix_h;
+      break;
+    case LD1RSB_z_p_bi_s16:
+      mnemonic = "ld1rsb";
+      form = "{'Zt.h}, 'Pgl/z, ['Xns";
+      suffix = suffix_b;
+      break;
+    case LD1RSB_z_p_bi_s32:
+      mnemonic = "ld1rsb";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns";
+      suffix = suffix_b;
+      break;
+    case LD1RSB_z_p_bi_s64:
+      mnemonic = "ld1rsb";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      suffix = suffix_b;
+      break;
+    case LD1RSH_z_p_bi_s32:
+      mnemonic = "ld1rsh";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns";
+      suffix = suffix_h;
+      break;
+    case LD1RSH_z_p_bi_s64:
+      mnemonic = "ld1rsh";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      suffix = suffix_h;
+      break;
+    case LD1RSW_z_p_bi_s64:
+      mnemonic = "ld1rsw";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      suffix = suffix_w;
+      break;
+    case LD1RW_z_p_bi_u32:
+      mnemonic = "ld1rw";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns";
+      suffix = suffix_w;
+      break;
+    case LD1RW_z_p_bi_u64:
+      mnemonic = "ld1rw";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      suffix = suffix_w;
+      break;
+    default:
+      break;
+  }
+
+  // Hide curly brackets if immediate is zero.
+  if (instr->ExtractBits(21, 16) == 0) {
+    suffix = "]";
+  }
+
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVELoadAndBroadcastQuadword_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVELoadAndBroadcastQuadword_ScalarPlusImm)";
+
+  const char *suffix =
+      (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916*16]";
+
+  switch (instr->Mask(SVELoadAndBroadcastQuadword_ScalarPlusImmMask)) {
+    case LD1RQB_z_p_bi_u8:
+      mnemonic = "ld1rqb";
+      form = "{'Zt.b}, 'Pgl/z, ['Xns";
+      break;
+    case LD1RQD_z_p_bi_u64:
+      mnemonic = "ld1rqd";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns";
+      break;
+    case LD1RQH_z_p_bi_u16:
+      mnemonic = "ld1rqh";
+      form = "{'Zt.h}, 'Pgl/z, ['Xns";
+      break;
+    case LD1RQW_z_p_bi_u32:
+      mnemonic = "ld1rqw";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns";
+      break;
+    default:
+      suffix = NULL;
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVELoadAndBroadcastQuadword_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVELoadAndBroadcastQuadword_ScalarPlusScalar)";
+
+  switch (instr->Mask(SVELoadAndBroadcastQuadword_ScalarPlusScalarMask)) {
+    case LD1RQB_z_p_br_contiguous:
+      mnemonic = "ld1rqb";
+      form = "{'Zt.b}, 'Pgl/z, ['Xns, 'Rm]";
+      break;
+    case LD1RQD_z_p_br_contiguous:
+      mnemonic = "ld1rqd";
+      form = "{'Zt.d}, 'Pgl/z, ['Xns, 'Rm, lsl #3]";
+      break;
+    case LD1RQH_z_p_br_contiguous:
+      mnemonic = "ld1rqh";
+      form = "{'Zt.h}, 'Pgl/z, ['Xns, 'Rm, lsl #1]";
+      break;
+    case LD1RQW_z_p_br_contiguous:
+      mnemonic = "ld1rqw";
+      form = "{'Zt.s}, 'Pgl/z, ['Xns, 'Rm, lsl #2]";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVELoadMultipleStructures_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVELoadMultipleStructures_ScalarPlusImm)";
+
+  const char *form_2 = "{'Zt.'tmsz, 'Zt2.'tmsz}, 'Pgl/z, ['Xns'ISveSvl]";
+  const char *form_3 =
+      "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}, 'Pgl/z, ['Xns'ISveSvl]";
+  const char *form_4 =
+      "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}, "
+      "'Pgl/z, ['Xns'ISveSvl]";
+
+  switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusImmMask)) {
+    case LD2B_z_p_bi_contiguous:
+      mnemonic = "ld2b";
+      form = form_2;
+      break;
+    case LD2D_z_p_bi_contiguous:
+      mnemonic = "ld2d";
+      form = form_2;
+      break;
+    case LD2H_z_p_bi_contiguous:
+      mnemonic = "ld2h";
+      form = form_2;
+      break;
+    case LD2W_z_p_bi_contiguous:
+      mnemonic = "ld2w";
+      form = form_2;
+      break;
+    case LD3B_z_p_bi_contiguous:
+      mnemonic = "ld3b";
+      form = form_3;
+      break;
+    case LD3D_z_p_bi_contiguous:
+      mnemonic = "ld3d";
+      form = form_3;
+      break;
+    case LD3H_z_p_bi_contiguous:
+      mnemonic = "ld3h";
+      form = form_3;
+      break;
+    case LD3W_z_p_bi_contiguous:
+      mnemonic = "ld3w";
+      form = form_3;
+      break;
+    case LD4B_z_p_bi_contiguous:
+      mnemonic = "ld4b";
+      form = form_4;
+      break;
+    case LD4D_z_p_bi_contiguous:
+      mnemonic = "ld4d";
+      form = form_4;
+      break;
+    case LD4H_z_p_bi_contiguous:
+      mnemonic = "ld4h";
+      form = form_4;
+      break;
+    case LD4W_z_p_bi_contiguous:
+      mnemonic = "ld4w";
+      form = form_4;
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVELoadMultipleStructures_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVELoadMultipleStructures_ScalarPlusScalar)";
+
+  const char *form_2 = "{'Zt.'tmsz, 'Zt2.'tmsz}, 'Pgl/z, ['Xns, 'Xm'NSveS]";
+  const char *form_3 =
+      "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}, 'Pgl/z, ['Xns, 'Xm'NSveS]";
+  const char *form_4 =
+      "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}, "
+      "'Pgl/z, ['Xns, 'Xm'NSveS]";
+
+  switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusScalarMask)) {
+    case LD2B_z_p_br_contiguous:
+      mnemonic = "ld2b";
+      form = form_2;
+      break;
+    case LD2D_z_p_br_contiguous:
+      mnemonic = "ld2d";
+      form = form_2;
+      break;
+    case LD2H_z_p_br_contiguous:
+      mnemonic = "ld2h";
+      form = form_2;
+      break;
+    case LD2W_z_p_br_contiguous:
+      mnemonic = "ld2w";
+      form = form_2;
+      break;
+    case LD3B_z_p_br_contiguous:
+      mnemonic = "ld3b";
+      form = form_3;
+      break;
+    case LD3D_z_p_br_contiguous:
+      mnemonic = "ld3d";
+      form = form_3;
+      break;
+    case LD3H_z_p_br_contiguous:
+      mnemonic = "ld3h";
+      form = form_3;
+      break;
+    case LD3W_z_p_br_contiguous:
+      mnemonic = "ld3w";
+      form = form_3;
+      break;
+    case LD4B_z_p_br_contiguous:
+      mnemonic = "ld4b";
+      form = form_4;
+      break;
+    case LD4D_z_p_br_contiguous:
+      mnemonic = "ld4d";
+      form = form_4;
+      break;
+    case LD4H_z_p_br_contiguous:
+      mnemonic = "ld4h";
+      form = form_4;
+      break;
+    case LD4W_z_p_br_contiguous:
+      mnemonic = "ld4w";
+      form = form_4;
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVELoadPredicateRegister(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVELoadPredicateRegister)";
+
+  switch (instr->Mask(SVELoadPredicateRegisterMask)) {
+    case LDR_p_bi:
+      mnemonic = "ldr";
+      if (instr->Mask(0x003f1c00) == 0) {
+        form = "'Pd, ['Xns]";
+      } else {
+        form = "'Pd, ['Xns, #'s2116:1210, mul vl]";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVELoadVectorRegister(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVELoadVectorRegister)";
+
+  switch (instr->Mask(SVELoadVectorRegisterMask)) {
+    case LDR_z_bi:
+      mnemonic = "ldr";
+      if (instr->Mask(0x003f1c00) == 0) {
+        form = "'Zd, ['Xns]";
+      } else {
+        form = "'Zt, ['Xns, #'s2116:1210, mul vl]";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPartitionBreakCondition(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.b, p'u1310/'?04:mz, 'Pn.b";
+
+  switch (instr->Mask(SVEPartitionBreakConditionMask)) {
+    case BRKAS_p_p_p_z:
+      mnemonic = "brkas";
+      break;
+    case BRKA_p_p_p:
+      mnemonic = "brka";
+      break;
+    case BRKBS_p_p_p_z:
+      mnemonic = "brkbs";
+      break;
+    case BRKB_p_p_p:
+      mnemonic = "brkb";
+      break;
+    default:
+      form = "(SVEPartitionBreakCondition)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPermutePredicateElements(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.'t, 'Pn.'t, 'Pm.'t";
+
+  switch (instr->Mask(SVEPermutePredicateElementsMask)) {
+    case TRN1_p_pp:
+      mnemonic = "trn1";
+      break;
+    case TRN2_p_pp:
+      mnemonic = "trn2";
+      break;
+    case UZP1_p_pp:
+      mnemonic = "uzp1";
+      break;
+    case UZP2_p_pp:
+      mnemonic = "uzp2";
+      break;
+    case ZIP1_p_pp:
+      mnemonic = "zip1";
+      break;
+    case ZIP2_p_pp:
+      mnemonic = "zip2";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPredicateFirstActive(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEPredicateFirstActive)";
+
+  switch (instr->Mask(SVEPredicateFirstActiveMask)) {
+    case PFIRST_p_p_p:
+      mnemonic = "pfirst";
+      form = "'Pd.b, 'Pn, 'Pd.b";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPredicateReadFromFFR_Unpredicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEPredicateReadFromFFR_Unpredicated)";
+
+  switch (instr->Mask(SVEPredicateReadFromFFR_UnpredicatedMask)) {
+    case RDFFR_p_f:
+      mnemonic = "rdffr";
+      form = "'Pd.b";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPredicateTest(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEPredicateTest)";
+
+  switch (instr->Mask(SVEPredicateTestMask)) {
+    case PTEST_p_p:
+      mnemonic = "ptest";
+      form = "p'u1310, 'Pn.b";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPredicateZero(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEPredicateZero)";
+
+  switch (instr->Mask(SVEPredicateZeroMask)) {
+    case PFALSE_p:
+      mnemonic = "pfalse";
+      form = "'Pd.b";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPropagateBreakToNextPartition(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.b, p'u1310/z, 'Pn.b, 'Pd.b";
+
+  switch (instr->Mask(SVEPropagateBreakToNextPartitionMask)) {
+    case BRKNS_p_p_pp:
+      mnemonic = "brkns";
+      break;
+    case BRKN_p_p_pp:
+      mnemonic = "brkn";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEReversePredicateElements(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEReversePredicateElements)";
+
+  switch (instr->Mask(SVEReversePredicateElementsMask)) {
+    case REV_p_p:
+      mnemonic = "rev";
+      form = "'Pd.'t, 'Pn.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEReverseVectorElements(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEReverseVectorElements)";
+
+  switch (instr->Mask(SVEReverseVectorElementsMask)) {
+    case REV_z_z:
+      mnemonic = "rev";
+      form = "'Zd.'t, 'Zn.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEReverseWithinElements(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t";
+
+  unsigned size = instr->GetSVESize();
+  switch (instr->Mask(SVEReverseWithinElementsMask)) {
+    case RBIT_z_p_z:
+      mnemonic = "rbit";
+      break;
+    case REVB_z_z:
+      if ((size == kHRegSizeInBytesLog2) || (size == kSRegSizeInBytesLog2) ||
+          (size == kDRegSizeInBytesLog2)) {
+        mnemonic = "revb";
+      } else {
+        form = "(SVEReverseWithinElements)";
+      }
+      break;
+    case REVH_z_z:
+      if ((size == kSRegSizeInBytesLog2) || (size == kDRegSizeInBytesLog2)) {
+        mnemonic = "revh";
+      } else {
+        form = "(SVEReverseWithinElements)";
+      }
+      break;
+    case REVW_z_z:
+      if (size == kDRegSizeInBytesLog2) {
+        mnemonic = "revw";
+      } else {
+        form = "(SVEReverseWithinElements)";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVESaturatingIncDecRegisterByElementCount(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = IncDecFormHelper(instr,
+                                      "'R20d, 'Ipc, mul #'u1916+1",
+                                      "'R20d, 'Ipc",
+                                      "'R20d");
+  const char *form_sx = IncDecFormHelper(instr,
+                                         "'Xd, 'Wd, 'Ipc, mul #'u1916+1",
+                                         "'Xd, 'Wd, 'Ipc",
+                                         "'Xd, 'Wd");
+
+  switch (instr->Mask(SVESaturatingIncDecRegisterByElementCountMask)) {
+    case SQDECB_r_rs_sx:
+      mnemonic = "sqdecb";
+      form = form_sx;
+      break;
+    case SQDECD_r_rs_sx:
+      mnemonic = "sqdecd";
+      form = form_sx;
+      break;
+    case SQDECH_r_rs_sx:
+      mnemonic = "sqdech";
+      form = form_sx;
+      break;
+    case SQDECW_r_rs_sx:
+      mnemonic = "sqdecw";
+      form = form_sx;
+      break;
+    case SQINCB_r_rs_sx:
+      mnemonic = "sqincb";
+      form = form_sx;
+      break;
+    case SQINCD_r_rs_sx:
+      mnemonic = "sqincd";
+      form = form_sx;
+      break;
+    case SQINCH_r_rs_sx:
+      mnemonic = "sqinch";
+      form = form_sx;
+      break;
+    case SQINCW_r_rs_sx:
+      mnemonic = "sqincw";
+      form = form_sx;
+      break;
+    case SQDECB_r_rs_x:
+      mnemonic = "sqdecb";
+      break;
+    case SQDECD_r_rs_x:
+      mnemonic = "sqdecd";
+      break;
+    case SQDECH_r_rs_x:
+      mnemonic = "sqdech";
+      break;
+    case SQDECW_r_rs_x:
+      mnemonic = "sqdecw";
+      break;
+    case SQINCB_r_rs_x:
+      mnemonic = "sqincb";
+      break;
+    case SQINCD_r_rs_x:
+      mnemonic = "sqincd";
+      break;
+    case SQINCH_r_rs_x:
+      mnemonic = "sqinch";
+      break;
+    case SQINCW_r_rs_x:
+      mnemonic = "sqincw";
+      break;
+    case UQDECB_r_rs_uw:
+    case UQDECB_r_rs_x:
+      mnemonic = "uqdecb";
+      break;
+    case UQDECD_r_rs_uw:
+    case UQDECD_r_rs_x:
+      mnemonic = "uqdecd";
+      break;
+    case UQDECH_r_rs_uw:
+    case UQDECH_r_rs_x:
+      mnemonic = "uqdech";
+      break;
+    case UQDECW_r_rs_uw:
+    case UQDECW_r_rs_x:
+      mnemonic = "uqdecw";
+      break;
+    case UQINCB_r_rs_uw:
+    case UQINCB_r_rs_x:
+      mnemonic = "uqincb";
+      break;
+    case UQINCD_r_rs_uw:
+    case UQINCD_r_rs_x:
+      mnemonic = "uqincd";
+      break;
+    case UQINCH_r_rs_uw:
+    case UQINCH_r_rs_x:
+      mnemonic = "uqinch";
+      break;
+    case UQINCW_r_rs_uw:
+    case UQINCW_r_rs_x:
+      mnemonic = "uqincw";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVESaturatingIncDecVectorByElementCount(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = IncDecFormHelper(instr,
+                                      "'Zd.'t, 'Ipc, mul #'u1916+1",
+                                      "'Zd.'t, 'Ipc",
+                                      "'Zd.'t");
+
+  switch (instr->Mask(SVESaturatingIncDecVectorByElementCountMask)) {
+    case SQDECD_z_zs:
+      mnemonic = "sqdecd";
+      break;
+    case SQDECH_z_zs:
+      mnemonic = "sqdech";
+      break;
+    case SQDECW_z_zs:
+      mnemonic = "sqdecw";
+      break;
+    case SQINCD_z_zs:
+      mnemonic = "sqincd";
+      break;
+    case SQINCH_z_zs:
+      mnemonic = "sqinch";
+      break;
+    case SQINCW_z_zs:
+      mnemonic = "sqincw";
+      break;
+    case UQDECD_z_zs:
+      mnemonic = "uqdecd";
+      break;
+    case UQDECH_z_zs:
+      mnemonic = "uqdech";
+      break;
+    case UQDECW_z_zs:
+      mnemonic = "uqdecw";
+      break;
+    case UQINCD_z_zs:
+      mnemonic = "uqincd";
+      break;
+    case UQINCH_z_zs:
+      mnemonic = "uqinch";
+      break;
+    case UQINCW_z_zs:
+      mnemonic = "uqincw";
+      break;
+    default:
+      form = "(SVEElementCount)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEStoreMultipleStructures_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEStoreMultipleStructures_ScalarPlusImm)";
+
+  const char *form_2 = "{'Zt.'tmsz, 'Zt2.'tmsz}, 'Pgl, ['Xns'ISveSvl]";
+  const char *form_3 =
+      "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}, 'Pgl, ['Xns'ISveSvl]";
+  const char *form_4 =
+      "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}, "
+      "'Pgl, ['Xns'ISveSvl]";
+
+  switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusImmMask)) {
+    case ST2B_z_p_bi_contiguous:
+      mnemonic = "st2b";
+      form = form_2;
+      break;
+    case ST2H_z_p_bi_contiguous:
+      mnemonic = "st2h";
+      form = form_2;
+      break;
+    case ST2W_z_p_bi_contiguous:
+      mnemonic = "st2w";
+      form = form_2;
+      break;
+    case ST2D_z_p_bi_contiguous:
+      mnemonic = "st2d";
+      form = form_2;
+      break;
+    case ST3B_z_p_bi_contiguous:
+      mnemonic = "st3b";
+      form = form_3;
+      break;
+    case ST3H_z_p_bi_contiguous:
+      mnemonic = "st3h";
+      form = form_3;
+      break;
+    case ST3W_z_p_bi_contiguous:
+      mnemonic = "st3w";
+      form = form_3;
+      break;
+    case ST3D_z_p_bi_contiguous:
+      mnemonic = "st3d";
+      form = form_3;
+      break;
+    case ST4B_z_p_bi_contiguous:
+      mnemonic = "st4b";
+      form = form_4;
+      break;
+    case ST4H_z_p_bi_contiguous:
+      mnemonic = "st4h";
+      form = form_4;
+      break;
+    case ST4W_z_p_bi_contiguous:
+      mnemonic = "st4w";
+      form = form_4;
+      break;
+    case ST4D_z_p_bi_contiguous:
+      mnemonic = "st4d";
+      form = form_4;
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEStoreMultipleStructures_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEStoreMultipleStructures_ScalarPlusScalar)";
+
+  const char *form_2 = "{'Zt.'tmsz, 'Zt2.'tmsz}, 'Pgl, ['Xns, 'Xm'NSveS]";
+  const char *form_3 =
+      "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz}, 'Pgl, ['Xns, 'Xm'NSveS]";
+  const char *form_4 =
+      "{'Zt.'tmsz, 'Zt2.'tmsz, 'Zt3.'tmsz, 'Zt4.'tmsz}, "
+      "'Pgl, ['Xns, 'Xm'NSveS]";
+
+  switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusScalarMask)) {
+    case ST2B_z_p_br_contiguous:
+      mnemonic = "st2b";
+      form = form_2;
+      break;
+    case ST2D_z_p_br_contiguous:
+      mnemonic = "st2d";
+      form = form_2;
+      break;
+    case ST2H_z_p_br_contiguous:
+      mnemonic = "st2h";
+      form = form_2;
+      break;
+    case ST2W_z_p_br_contiguous:
+      mnemonic = "st2w";
+      form = form_2;
+      break;
+    case ST3B_z_p_br_contiguous:
+      mnemonic = "st3b";
+      form = form_3;
+      break;
+    case ST3D_z_p_br_contiguous:
+      mnemonic = "st3d";
+      form = form_3;
+      break;
+    case ST3H_z_p_br_contiguous:
+      mnemonic = "st3h";
+      form = form_3;
+      break;
+    case ST3W_z_p_br_contiguous:
+      mnemonic = "st3w";
+      form = form_3;
+      break;
+    case ST4B_z_p_br_contiguous:
+      mnemonic = "st4b";
+      form = form_4;
+      break;
+    case ST4D_z_p_br_contiguous:
+      mnemonic = "st4d";
+      form = form_4;
+      break;
+    case ST4H_z_p_br_contiguous:
+      mnemonic = "st4h";
+      form = form_4;
+      break;
+    case ST4W_z_p_br_contiguous:
+      mnemonic = "st4w";
+      form = form_4;
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEStorePredicateRegister(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEStorePredicateRegister)";
+
+  switch (instr->Mask(SVEStorePredicateRegisterMask)) {
+    case STR_p_bi:
+      mnemonic = "str";
+      if (instr->Mask(0x003f1c00) == 0) {
+        form = "'Pd, ['Xns]";
+      } else {
+        form = "'Pd, ['Xns, #'s2116:1210, mul vl]";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEStoreVectorRegister(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEStoreVectorRegister)";
+
+  switch (instr->Mask(SVEStoreVectorRegisterMask)) {
+    case STR_z_bi:
+      mnemonic = "str";
+      if (instr->Mask(0x003f1c00) == 0) {
+        form = "'Zd, ['Xns]";
+      } else {
+        form = "'Zt, ['Xns, #'s2116:1210, mul vl]";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVETableLookup(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVETableLookup)";
+
+  switch (instr->Mask(SVETableLookupMask)) {
+    case TBL_z_zz_1:
+      mnemonic = "tbl";
+      form = "'Zd.'t, {'Zn.'t}, 'Zm.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEUnpackPredicateElements(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.h, 'Pn.b";
+
+  switch (instr->Mask(SVEUnpackPredicateElementsMask)) {
+    case PUNPKHI_p_p:
+      mnemonic = "punpkhi";
+      break;
+    case PUNPKLO_p_p:
+      mnemonic = "punpklo";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEUnpackVectorElements(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Zn.'th";
+
+  if (instr->GetSVESize() == 0) {
+    // The lowest lane size of the destination vector is H-sized lane.
+    Format(instr, "unallocated", "(SVEUnpackVectorElements)");
+    return;
+  }
+
+  switch (instr->Mask(SVEUnpackVectorElementsMask)) {
+    case SUNPKHI_z_z:
+      mnemonic = "sunpkhi";
+      break;
+    case SUNPKLO_z_z:
+      mnemonic = "sunpklo";
+      break;
+    case UUNPKHI_z_z:
+      mnemonic = "uunpkhi";
+      break;
+    case UUNPKLO_z_z:
+      mnemonic = "uunpklo";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEVectorSplice_Destructive(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEVectorSplice_Destructive)";
+
+  switch (instr->Mask(SVEVectorSplice_DestructiveMask)) {
+    case SPLICE_z_p_zz_des:
+      mnemonic = "splice";
+      form = "'Zd.'t, 'Pgl, 'Zd.'t, 'Zn.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEAddressGeneration(const Instruction *instr) {
+  const char *mnemonic = "adr";
+  const char *form = "'Zd.d, ['Zn.d, 'Zm.d";
+  const char *suffix = NULL;
+
+  bool msz_is_zero = (instr->ExtractBits(11, 10) == 0);
+
+  switch (instr->Mask(SVEAddressGenerationMask)) {
+    case ADR_z_az_d_s32_scaled:
+      suffix = msz_is_zero ? ", sxtw]" : ", sxtw #'u1110]";
+      break;
+    case ADR_z_az_d_u32_scaled:
+      suffix = msz_is_zero ? ", uxtw]" : ", uxtw #'u1110]";
+      break;
+    case ADR_z_az_s_same_scaled:
+    case ADR_z_az_d_same_scaled:
+      form = "'Zd.'t, ['Zn.'t, 'Zm.'t";
+      suffix = msz_is_zero ? "]" : ", lsl #'u1110]";
+      break;
+    default:
+      mnemonic = "unimplemented";
+      form = "(SVEAddressGeneration)";
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEBitwiseLogicalUnpredicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.d, 'Zn.d, 'Zm.d";
+
+  switch (instr->Mask(SVEBitwiseLogicalUnpredicatedMask)) {
+    case AND_z_zz:
+      mnemonic = "and";
+      break;
+    case BIC_z_zz:
+      mnemonic = "bic";
+      break;
+    case EOR_z_zz:
+      mnemonic = "eor";
+      break;
+    case ORR_z_zz:
+      mnemonic = "orr";
+      if (instr->GetRn() == instr->GetRm()) {
+        mnemonic = "mov";
+        form = "'Zd.d, 'Zn.d";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEBitwiseShiftUnpredicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEBitwiseShiftUnpredicated)";
+  unsigned tsize =
+      (instr->ExtractBits(23, 22) << 2) | instr->ExtractBits(20, 19);
+  unsigned lane_size = instr->GetSVESize();
+
+  switch (instr->Mask(SVEBitwiseShiftUnpredicatedMask)) {
+    case ASR_z_zi:
+      if (tsize != 0) {
+        // The tsz field must not be zero.
+        mnemonic = "asr";
+        form = "'Zd.'tszs, 'Zn.'tszs, 'ITriSves";
+      }
+      break;
+    case ASR_z_zw:
+      if (lane_size <= kSRegSizeInBytesLog2) {
+        mnemonic = "asr";
+        form = "'Zd.'t, 'Zn.'t, 'Zm.d";
+      }
+      break;
+    case LSL_z_zi:
+      if (tsize != 0) {
+        // The tsz field must not be zero.
+        mnemonic = "lsl";
+        form = "'Zd.'tszs, 'Zn.'tszs, 'ITriSver";
+      }
+      break;
+    case LSL_z_zw:
+      if (lane_size <= kSRegSizeInBytesLog2) {
+        mnemonic = "lsl";
+        form = "'Zd.'t, 'Zn.'t, 'Zm.d";
+      }
+      break;
+    case LSR_z_zi:
+      if (tsize != 0) {
+        // The tsz field must not be zero.
+        mnemonic = "lsr";
+        form = "'Zd.'tszs, 'Zn.'tszs, 'ITriSves";
+      }
+      break;
+    case LSR_z_zw:
+      if (lane_size <= kSRegSizeInBytesLog2) {
+        mnemonic = "lsr";
+        form = "'Zd.'t, 'Zn.'t, 'Zm.d";
+      }
+      break;
+    default:
+      break;
+  }
+
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEElementCount(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form =
+      IncDecFormHelper(instr, "'Xd, 'Ipc, mul #'u1916+1", "'Xd, 'Ipc", "'Xd");
+
+  switch (instr->Mask(SVEElementCountMask)) {
+    case CNTB_r_s:
+      mnemonic = "cntb";
+      break;
+    case CNTD_r_s:
+      mnemonic = "cntd";
+      break;
+    case CNTH_r_s:
+      mnemonic = "cnth";
+      break;
+    case CNTW_r_s:
+      mnemonic = "cntw";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPAccumulatingReduction(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPAccumulatingReduction)";
+
+  switch (instr->Mask(SVEFPAccumulatingReductionMask)) {
+    case FADDA_v_p_z:
+      mnemonic = "fadda";
+      form = "'t'u0400, 'Pgl, 't'u0400, 'Zn.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPArithmeticUnpredicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Zn.'t, 'Zm.'t";
+
+  switch (instr->Mask(SVEFPArithmeticUnpredicatedMask)) {
+    case FADD_z_zz:
+      mnemonic = "fadd";
+      break;
+    case FMUL_z_zz:
+      mnemonic = "fmul";
+      break;
+    case FRECPS_z_zz:
+      mnemonic = "frecps";
+      break;
+    case FRSQRTS_z_zz:
+      mnemonic = "frsqrts";
+      break;
+    case FSUB_z_zz:
+      mnemonic = "fsub";
+      break;
+    case FTSMUL_z_zz:
+      mnemonic = "ftsmul";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPCompareVectors(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
+
+  switch (instr->Mask(SVEFPCompareVectorsMask)) {
+    case FACGE_p_p_zz:
+      mnemonic = "facge";
+      break;
+    case FACGT_p_p_zz:
+      mnemonic = "facgt";
+      break;
+    case FCMEQ_p_p_zz:
+      mnemonic = "fcmeq";
+      break;
+    case FCMGE_p_p_zz:
+      mnemonic = "fcmge";
+      break;
+    case FCMGT_p_p_zz:
+      mnemonic = "fcmgt";
+      break;
+    case FCMNE_p_p_zz:
+      mnemonic = "fcmne";
+      break;
+    case FCMUO_p_p_zz:
+      mnemonic = "fcmuo";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPCompareWithZero(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, #0.0";
+
+  switch (instr->Mask(SVEFPCompareWithZeroMask)) {
+    case FCMEQ_p_p_z0:
+      mnemonic = "fcmeq";
+      break;
+    case FCMGE_p_p_z0:
+      mnemonic = "fcmge";
+      break;
+    case FCMGT_p_p_z0:
+      mnemonic = "fcmgt";
+      break;
+    case FCMLE_p_p_z0:
+      mnemonic = "fcmle";
+      break;
+    case FCMLT_p_p_z0:
+      mnemonic = "fcmlt";
+      break;
+    case FCMNE_p_p_z0:
+      mnemonic = "fcmne";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPComplexAddition(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPComplexAddition)";
+
+  switch (instr->Mask(SVEFPComplexAdditionMask)) {
+    case FCADD_z_p_zz:
+      mnemonic = "fcadd";
+      if (instr->ExtractBit(16) == 0) {
+        form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t, #90";
+      } else {
+        form = "'Zd.'t, 'Pgl/m, 'Zd.'t, 'Zn.'t, #270";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPComplexMulAdd(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPComplexMulAdd)";
+  const char *suffix = NULL;
+
+  const char *fcmla_constants[] = {"0", "90", "180", "270"};
+
+  switch (instr->Mask(SVEFPComplexMulAddMask)) {
+    case FCMLA_z_p_zzz:
+      mnemonic = "fcmla";
+      form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t, #";
+      suffix = fcmla_constants[instr->ExtractBits(14, 13)];
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEFPComplexMulAddIndex(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPComplexMulAddIndex)";
+
+  const char *fcmla_constants[] = {"0", "90", "180", "270"};
+  const char *suffix = fcmla_constants[instr->ExtractBits(11, 10)];
+
+  switch (instr->Mask(SVEFPComplexMulAddIndexMask)) {
+    case FCMLA_z_zzzi_h:
+      mnemonic = "fcmla";
+      form = "'Zd.h, 'Zn.h, z'u1816.h['u2019], #";
+      break;
+    case FCMLA_z_zzzi_s:
+      mnemonic = "fcmla";
+      form = "'Zd.s, 'Zn.s, z'u1916.s['u2020], #";
+      break;
+    default:
+      suffix = NULL;
+      break;
+  }
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEFPFastReduction(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'t'u0400, 'Pgl, 'Zn.'t";
+
+  switch (instr->Mask(SVEFPFastReductionMask)) {
+    case FADDV_v_p_z:
+      mnemonic = "faddv";
+      break;
+    case FMAXNMV_v_p_z:
+      mnemonic = "fmaxnmv";
+      break;
+    case FMAXV_v_p_z:
+      mnemonic = "fmaxv";
+      break;
+    case FMINNMV_v_p_z:
+      mnemonic = "fminnmv";
+      break;
+    case FMINV_v_p_z:
+      mnemonic = "fminv";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPMulIndex(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPMulIndex)";
+
+  switch (instr->Mask(SVEFPMulIndexMask)) {
+    case FMUL_z_zzi_d:
+      mnemonic = "fmul";
+      form = "'Zd.d, 'Zn.d, z'u1916.d['u2020]";
+      break;
+    case FMUL_z_zzi_h:
+    case FMUL_z_zzi_h_i3h:
+      mnemonic = "fmul";
+      form = "'Zd.h, 'Zn.h, z'u1816.h['u2222:2019]";
+      break;
+    case FMUL_z_zzi_s:
+      mnemonic = "fmul";
+      form = "'Zd.s, 'Zn.s, z'u1816.s['u2019]";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPMulAdd(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t";
+
+  switch (instr->Mask(SVEFPMulAddMask)) {
+    case FMAD_z_p_zzz:
+      mnemonic = "fmad";
+      break;
+    case FMLA_z_p_zzz:
+      mnemonic = "fmla";
+      break;
+    case FMLS_z_p_zzz:
+      mnemonic = "fmls";
+      break;
+    case FMSB_z_p_zzz:
+      mnemonic = "fmsb";
+      break;
+    case FNMAD_z_p_zzz:
+      mnemonic = "fnmad";
+      break;
+    case FNMLA_z_p_zzz:
+      mnemonic = "fnmla";
+      break;
+    case FNMLS_z_p_zzz:
+      mnemonic = "fnmls";
+      break;
+    case FNMSB_z_p_zzz:
+      mnemonic = "fnmsb";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPMulAddIndex(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEFPMulAddIndex)";
+
+  switch (instr->Mask(SVEFPMulAddIndexMask)) {
+    case FMLA_z_zzzi_d:
+      mnemonic = "fmla";
+      form = "'Zd.d, 'Zn.d, z'u1916.d['u2020]";
+      break;
+    case FMLA_z_zzzi_s:
+      mnemonic = "fmla";
+      form = "'Zd.s, 'Zn.s, z'u1816.s['u2019]";
+      break;
+    case FMLS_z_zzzi_d:
+      mnemonic = "fmls";
+      form = "'Zd.d, 'Zn.d, z'u1916.d['u2020]";
+      break;
+    case FMLS_z_zzzi_s:
+      mnemonic = "fmls";
+      form = "'Zd.s, 'Zn.s, z'u1816.s['u2019]";
+      break;
+    case FMLA_z_zzzi_h:
+    case FMLA_z_zzzi_h_i3h:
+      mnemonic = "fmla";
+      form = "'Zd.h, 'Zn.h, z'u1816.h['u2222:2019]";
+      break;
+    case FMLS_z_zzzi_h:
+    case FMLS_z_zzzi_h_i3h:
+      mnemonic = "fmls";
+      form = "'Zd.h, 'Zn.h, z'u1816.h['u2222:2019]";
+      break;
+    default:
+      break;
+  }
+
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEFPUnaryOpUnpredicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Zn.'t";
+
+  switch (instr->Mask(SVEFPUnaryOpUnpredicatedMask)) {
+    case FRECPE_z_z:
+      mnemonic = "frecpe";
+      break;
+    case FRSQRTE_z_z:
+      mnemonic = "frsqrte";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIncDecByPredicateCount(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEIncDecByPredicateCount)";
+
+  switch (instr->Mask(SVEIncDecByPredicateCountMask)) {
+    case DECP_r_p_r:
+    case DECP_z_p_z:
+      mnemonic = "decp";
+      break;
+    case INCP_r_p_r:
+    case INCP_z_p_z:
+      mnemonic = "incp";
+      break;
+    case SQDECP_r_p_r_sx:
+    case SQDECP_r_p_r_x:
+    case SQDECP_z_p_z:
+      mnemonic = "sqdecp";
+      break;
+    case SQINCP_r_p_r_sx:
+    case SQINCP_r_p_r_x:
+    case SQINCP_z_p_z:
+      mnemonic = "sqincp";
+      break;
+    case UQDECP_r_p_r_uw:
+    case UQDECP_r_p_r_x:
+    case UQDECP_z_p_z:
+      mnemonic = "uqdecp";
+      break;
+    case UQINCP_r_p_r_uw:
+    case UQINCP_r_p_r_x:
+    case UQINCP_z_p_z:
+      mnemonic = "uqincp";
+      break;
+    default:
+      break;
+  }
+
+  switch (instr->Mask(SVEIncDecByPredicateCountMask)) {
+    // <Xdn>, <Pg>.<T>
+    case DECP_r_p_r:
+    case INCP_r_p_r:
+      form = "'Xd, 'Pn.'t";
+      break;
+    // <Zdn>.<T>, <Pg>
+    case DECP_z_p_z:
+    case INCP_z_p_z:
+    case SQDECP_z_p_z:
+    case SQINCP_z_p_z:
+    case UQDECP_z_p_z:
+    case UQINCP_z_p_z:
+      form = "'Zd.'t, 'Pn";
+      break;
+    // <Xdn>, <Pg>.<T>, <Wdn>
+    case SQDECP_r_p_r_sx:
+    case SQINCP_r_p_r_sx:
+      form = "'Xd, 'Pn.'t, 'Wd";
+      break;
+    // <Xdn>, <Pg>.<T>
+    case SQDECP_r_p_r_x:
+    case SQINCP_r_p_r_x:
+    case UQDECP_r_p_r_x:
+    case UQINCP_r_p_r_x:
+      form = "'Xd, 'Pn.'t";
+      break;
+    // <Wdn>, <Pg>.<T>
+    case UQDECP_r_p_r_uw:
+    case UQINCP_r_p_r_uw:
+      form = "'Wd, 'Pn.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIndexGeneration(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEIndexGeneration)";
+
+  bool w_inputs =
+      static_cast<unsigned>(instr->GetSVESize()) <= kWRegSizeInBytesLog2;
+
+  switch (instr->Mask(SVEIndexGenerationMask)) {
+    case INDEX_z_ii:
+      mnemonic = "index";
+      form = "'Zd.'t, #'s0905, #'s2016";
+      break;
+    case INDEX_z_ir:
+      mnemonic = "index";
+      form = w_inputs ? "'Zd.'t, #'s0905, 'Wm" : "'Zd.'t, #'s0905, 'Xm";
+      break;
+    case INDEX_z_ri:
+      mnemonic = "index";
+      form = w_inputs ? "'Zd.'t, 'Wn, #'s2016" : "'Zd.'t, 'Xn, #'s2016";
+      break;
+    case INDEX_z_rr:
+      mnemonic = "index";
+      form = w_inputs ? "'Zd.'t, 'Wn, 'Wm" : "'Zd.'t, 'Xn, 'Xm";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntArithmeticUnpredicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Zn.'t, 'Zm.'t";
+
+  switch (instr->Mask(SVEIntArithmeticUnpredicatedMask)) {
+    case ADD_z_zz:
+      mnemonic = "add";
+      break;
+    case SQADD_z_zz:
+      mnemonic = "sqadd";
+      break;
+    case SQSUB_z_zz:
+      mnemonic = "sqsub";
+      break;
+    case SUB_z_zz:
+      mnemonic = "sub";
+      break;
+    case UQADD_z_zz:
+      mnemonic = "uqadd";
+      break;
+    case UQSUB_z_zz:
+      mnemonic = "uqsub";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntCompareSignedImm(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, #'s2016";
+
+  switch (instr->Mask(SVEIntCompareSignedImmMask)) {
+    case CMPEQ_p_p_zi:
+      mnemonic = "cmpeq";
+      break;
+    case CMPGE_p_p_zi:
+      mnemonic = "cmpge";
+      break;
+    case CMPGT_p_p_zi:
+      mnemonic = "cmpgt";
+      break;
+    case CMPLE_p_p_zi:
+      mnemonic = "cmple";
+      break;
+    case CMPLT_p_p_zi:
+      mnemonic = "cmplt";
+      break;
+    case CMPNE_p_p_zi:
+      mnemonic = "cmpne";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntCompareUnsignedImm(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, #'u2014";
+
+  switch (instr->Mask(SVEIntCompareUnsignedImmMask)) {
+    case CMPHI_p_p_zi:
+      mnemonic = "cmphi";
+      break;
+    case CMPHS_p_p_zi:
+      mnemonic = "cmphs";
+      break;
+    case CMPLO_p_p_zi:
+      mnemonic = "cmplo";
+      break;
+    case CMPLS_p_p_zi:
+      mnemonic = "cmpls";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntCompareVectors(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.d";
+
+  switch (instr->Mask(SVEIntCompareVectorsMask)) {
+    case CMPEQ_p_p_zw:
+      mnemonic = "cmpeq";
+      break;
+    case CMPEQ_p_p_zz:
+      mnemonic = "cmpeq";
+      form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
+      break;
+    case CMPGE_p_p_zw:
+      mnemonic = "cmpge";
+      break;
+    case CMPGE_p_p_zz:
+      mnemonic = "cmpge";
+      form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
+      break;
+    case CMPGT_p_p_zw:
+      mnemonic = "cmpgt";
+      break;
+    case CMPGT_p_p_zz:
+      mnemonic = "cmpgt";
+      form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
+      break;
+    case CMPHI_p_p_zw:
+      mnemonic = "cmphi";
+      break;
+    case CMPHI_p_p_zz:
+      mnemonic = "cmphi";
+      form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
+      break;
+    case CMPHS_p_p_zw:
+      mnemonic = "cmphs";
+      break;
+    case CMPHS_p_p_zz:
+      mnemonic = "cmphs";
+      form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
+      break;
+    case CMPLE_p_p_zw:
+      mnemonic = "cmple";
+      break;
+    case CMPLO_p_p_zw:
+      mnemonic = "cmplo";
+      break;
+    case CMPLS_p_p_zw:
+      mnemonic = "cmpls";
+      break;
+    case CMPLT_p_p_zw:
+      mnemonic = "cmplt";
+      break;
+    case CMPNE_p_p_zw:
+      mnemonic = "cmpne";
+      break;
+    case CMPNE_p_p_zz:
+      mnemonic = "cmpne";
+      form = "'Pd.'t, 'Pgl/z, 'Zn.'t, 'Zm.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntMulAddPredicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEIntMulAddPredicated)";
+
+  switch (instr->Mask(SVEIntMulAddPredicatedMask)) {
+    case MAD_z_p_zzz:
+      mnemonic = "mad";
+      form = "'Zd.'t, 'Pgl/m, 'Zm.'t, 'Zn.'t";
+      break;
+    case MLA_z_p_zzz:
+      mnemonic = "mla";
+      form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t";
+      break;
+    case MLS_z_p_zzz:
+      mnemonic = "mls";
+      form = "'Zd.'t, 'Pgl/m, 'Zn.'t, 'Zm.'t";
+      break;
+    case MSB_z_p_zzz:
+      mnemonic = "msb";
+      form = "'Zd.'t, 'Pgl/m, 'Zm.'t, 'Zn.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntMulAddUnpredicated(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEIntMulAddUnpredicated)";
+
+  if (static_cast<unsigned>(instr->GetSVESize()) >= kSRegSizeInBytesLog2) {
+    form = "'Zd.'t, 'Zn.'tq, 'Zm.'tq";
+    switch (instr->Mask(SVEIntMulAddUnpredicatedMask)) {
+      case SDOT_z_zzz:
+        mnemonic = "sdot";
+        break;
+      case UDOT_z_zzz:
+        mnemonic = "udot";
+        break;
+      default:
+        break;
+    }
+  }
+
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEMovprfx(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEMovprfx)";
+
+  if (instr->Mask(SVEMovprfxMask) == MOVPRFX_z_p_z) {
+    mnemonic = "movprfx";
+    form = "'Zd.'t, 'Pgl/'?16:mz, 'Zn.'t";
+  }
+
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntReduction(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Vdv, 'Pgl, 'Zn.'t";
+
+  if (instr->Mask(SVEIntReductionLogicalFMask) == SVEIntReductionLogicalFixed) {
+    switch (instr->Mask(SVEIntReductionLogicalMask)) {
+      case ANDV_r_p_z:
+        mnemonic = "andv";
+        break;
+      case EORV_r_p_z:
+        mnemonic = "eorv";
+        break;
+      case ORV_r_p_z:
+        mnemonic = "orv";
+        break;
+      default:
+        break;
+    }
+  } else {
+    switch (instr->Mask(SVEIntReductionMask)) {
+      case SADDV_r_p_z:
+        mnemonic = "saddv";
+        form = "'Dd, 'Pgl, 'Zn.'t";
+        break;
+      case SMAXV_r_p_z:
+        mnemonic = "smaxv";
+        break;
+      case SMINV_r_p_z:
+        mnemonic = "sminv";
+        break;
+      case UADDV_r_p_z:
+        mnemonic = "uaddv";
+        form = "'Dd, 'Pgl, 'Zn.'t";
+        break;
+      case UMAXV_r_p_z:
+        mnemonic = "umaxv";
+        break;
+      case UMINV_r_p_z:
+        mnemonic = "uminv";
+        break;
+      default:
+        break;
+    }
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEIntUnaryArithmeticPredicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Pgl/m, 'Zn.'t";
+
+  switch (instr->Mask(SVEIntUnaryArithmeticPredicatedMask)) {
+    case ABS_z_p_z:
+      mnemonic = "abs";
+      break;
+    case CLS_z_p_z:
+      mnemonic = "cls";
+      break;
+    case CLZ_z_p_z:
+      mnemonic = "clz";
+      break;
+    case CNOT_z_p_z:
+      mnemonic = "cnot";
+      break;
+    case CNT_z_p_z:
+      mnemonic = "cnt";
+      break;
+    case FABS_z_p_z:
+      mnemonic = "fabs";
+      break;
+    case FNEG_z_p_z:
+      mnemonic = "fneg";
+      break;
+    case NEG_z_p_z:
+      mnemonic = "neg";
+      break;
+    case NOT_z_p_z:
+      mnemonic = "not";
+      break;
+    case SXTB_z_p_z:
+      mnemonic = "sxtb";
+      break;
+    case SXTH_z_p_z:
+      mnemonic = "sxth";
+      break;
+    case SXTW_z_p_z:
+      mnemonic = "sxtw";
+      break;
+    case UXTB_z_p_z:
+      mnemonic = "uxtb";
+      break;
+    case UXTH_z_p_z:
+      mnemonic = "uxth";
+      break;
+    case UXTW_z_p_z:
+      mnemonic = "uxtw";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEMulIndex(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEMulIndex)";
+
+  switch (instr->Mask(SVEMulIndexMask)) {
+    case SDOT_z_zzzi_d:
+      mnemonic = "sdot";
+      form = "'Zd.d, 'Zn.h, z'u1916.h['u2020]";
+      break;
+    case SDOT_z_zzzi_s:
+      mnemonic = "sdot";
+      form = "'Zd.s, 'Zn.b, z'u1816.b['u2019]";
+      break;
+    case UDOT_z_zzzi_d:
+      mnemonic = "udot";
+      form = "'Zd.d, 'Zn.h, z'u1916.h['u2020]";
+      break;
+    case UDOT_z_zzzi_s:
+      mnemonic = "udot";
+      form = "'Zd.s, 'Zn.b, z'u1816.b['u2019]";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPermuteVectorExtract(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEPermuteVectorExtract)";
+
+  switch (instr->Mask(SVEPermuteVectorExtractMask)) {
+    case EXT_z_zi_des:
+      mnemonic = "ext";
+      form = "'Zd.b, 'Zd.b, 'Zn.b, #'u2016:1210";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPermuteVectorInterleaving(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Zd.'t, 'Zn.'t, 'Zm.'t";
+
+  switch (instr->Mask(SVEPermuteVectorInterleavingMask)) {
+    case TRN1_z_zz:
+      mnemonic = "trn1";
+      break;
+    case TRN2_z_zz:
+      mnemonic = "trn2";
+      break;
+    case UZP1_z_zz:
+      mnemonic = "uzp1";
+      break;
+    case UZP2_z_zz:
+      mnemonic = "uzp2";
+      break;
+    case ZIP1_z_zz:
+      mnemonic = "zip1";
+      break;
+    case ZIP2_z_zz:
+      mnemonic = "zip2";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPredicateCount(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEPredicateCount)";
+
+  switch (instr->Mask(SVEPredicateCountMask)) {
+    case CNTP_r_p_p:
+      mnemonic = "cntp";
+      form = "'Xd, p'u1310, 'Pn.'t";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPredicateLogical(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.b, p'u1310/z, 'Pn.b, 'Pm.b";
+
+  int pd = instr->GetPd();
+  int pn = instr->GetPn();
+  int pm = instr->GetPm();
+  int pg = instr->ExtractBits(13, 10);
+
+  switch (instr->Mask(SVEPredicateLogicalMask)) {
+    case ANDS_p_p_pp_z:
+      mnemonic = "ands";
+      if (pn == pm) {
+        mnemonic = "movs";
+        form = "'Pd.b, p'u1310/z, 'Pn.b";
+      }
+      break;
+    case AND_p_p_pp_z:
+      mnemonic = "and";
+      if (pn == pm) {
+        mnemonic = "mov";
+        form = "'Pd.b, p'u1310/z, 'Pn.b";
+      }
+      break;
+    case BICS_p_p_pp_z:
+      mnemonic = "bics";
+      break;
+    case BIC_p_p_pp_z:
+      mnemonic = "bic";
+      break;
+    case EORS_p_p_pp_z:
+      mnemonic = "eors";
+      if (pm == pg) {
+        mnemonic = "nots";
+        form = "'Pd.b, 'Pm/z, 'Pn.b";
+      }
+      break;
+    case EOR_p_p_pp_z:
+      mnemonic = "eor";
+      if (pm == pg) {
+        mnemonic = "not";
+        form = "'Pd.b, 'Pm/z, 'Pn.b";
+      }
+      break;
+    case NANDS_p_p_pp_z:
+      mnemonic = "nands";
+      break;
+    case NAND_p_p_pp_z:
+      mnemonic = "nand";
+      break;
+    case NORS_p_p_pp_z:
+      mnemonic = "nors";
+      break;
+    case NOR_p_p_pp_z:
+      mnemonic = "nor";
+      break;
+    case ORNS_p_p_pp_z:
+      mnemonic = "orns";
+      break;
+    case ORN_p_p_pp_z:
+      mnemonic = "orn";
+      break;
+    case ORRS_p_p_pp_z:
+      mnemonic = "orrs";
+      if ((pn == pm) && (pn == pg)) {
+        mnemonic = "movs";
+        form = "'Pd.b, 'Pn.b";
+      }
+      break;
+    case ORR_p_p_pp_z:
+      mnemonic = "orr";
+      if ((pn == pm) && (pn == pg)) {
+        mnemonic = "mov";
+        form = "'Pd.b, 'Pn.b";
+      }
+      break;
+    case SEL_p_p_pp:
+      if (pd == pm) {
+        mnemonic = "mov";
+        form = "'Pd.b, p'u1310/m, 'Pn.b";
+      } else {
+        mnemonic = "sel";
+        form = "'Pd.b, p'u1310, 'Pn.b, 'Pm.b";
+      }
+      break;
+    default:
+      form = "(SVEPredicateLogical)";
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPredicateInitialize(const Instruction *instr) {
+  // This group only contains PTRUE{S}, and there are no unallocated encodings.
+  VIXL_STATIC_ASSERT(
+      SVEPredicateInitializeMask ==
+      (SVEPredicateInitializeFMask | SVEPredicateInitializeSetFlagsBit));
+  VIXL_ASSERT((instr->Mask(SVEPredicateInitializeMask) == PTRUE_p_s) ||
+              (instr->Mask(SVEPredicateInitializeMask) == PTRUES_p_s));
+
+  const char *mnemonic = instr->ExtractBit(16) ? "ptrues" : "ptrue";
+  const char *form = "'Pd.'t, 'Ipc";
+  // Omit the pattern if it is the default ('ALL').
+  if (instr->ExtractBits(9, 5) == SVE_ALL) form = "'Pd.'t";
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPredicateNextActive(const Instruction *instr) {
+  // This group only contains PNEXT, and there are no unallocated encodings.
+  VIXL_STATIC_ASSERT(SVEPredicateNextActiveFMask == SVEPredicateNextActiveMask);
+  VIXL_ASSERT(instr->Mask(SVEPredicateNextActiveMask) == PNEXT_p_p_p);
+
+  Format(instr, "pnext", "'Pd.'t, 'Pn, 'Pd.'t");
+}
+
+void Disassembler::VisitSVEPredicateReadFromFFR_Predicated(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEPredicateReadFromFFR_Predicated)";
+  switch (instr->Mask(SVEPredicateReadFromFFR_PredicatedMask)) {
+    case RDFFR_p_p_f:
+    case RDFFRS_p_p_f:
+      mnemonic = instr->ExtractBit(22) ? "rdffrs" : "rdffr";
+      form = "'Pd.b, 'Pn/z";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEPropagateBreak(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Pd.b, p'u1310/z, 'Pn.b, 'Pm.b";
+
+  switch (instr->Mask(SVEPropagateBreakMask)) {
+    case BRKPAS_p_p_pp:
+      mnemonic = "brkpas";
+      break;
+    case BRKPA_p_p_pp:
+      mnemonic = "brkpa";
+      break;
+    case BRKPBS_p_p_pp:
+      mnemonic = "brkpbs";
+      break;
+    case BRKPB_p_p_pp:
+      mnemonic = "brkpb";
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEStackFrameAdjustment(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "'Xds, 'Xms, #'s1005";
+
+  switch (instr->Mask(SVEStackFrameAdjustmentMask)) {
+    case ADDPL_r_ri:
+      mnemonic = "addpl";
+      break;
+    case ADDVL_r_ri:
+      mnemonic = "addvl";
+      break;
+    default:
+      form = "(SVEStackFrameAdjustment)";
+      break;
+  }
+
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEStackFrameSize(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEStackFrameSize)";
+
+  switch (instr->Mask(SVEStackFrameSizeMask)) {
+    case RDVL_r_i:
+      mnemonic = "rdvl";
+      form = "'Xd, #'s1005";
+      break;
+    default:
+      break;
+  }
+
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEVectorSelect(const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "(SVEVectorSelect)";
+
+  switch (instr->Mask(SVEVectorSelectMask)) {
+    case SEL_z_p_zz:
+      if (instr->GetRd() == instr->GetRm()) {
+        mnemonic = "mov";
+        form = "'Zd.'t, p'u1310/m, 'Zn.'t";
+      } else {
+        mnemonic = "sel";
+        form = "'Zd.'t, p'u1310, 'Zn.'t, 'Zm.'t";
+      }
+      break;
+    default:
+      break;
+  }
+  Format(instr, mnemonic, form);
+}
+
+void Disassembler::VisitSVEContiguousLoad_ScalarPlusImm(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.'tlss}, 'Pgl/z, ['Xns";
+  const char *suffix =
+      (instr->ExtractBits(19, 16) == 0) ? "]" : ", #'s1916, mul vl]";
+
+  switch (instr->Mask(SVEContiguousLoad_ScalarPlusImmMask)) {
+    case LD1B_z_p_bi_u16:
+    case LD1B_z_p_bi_u32:
+    case LD1B_z_p_bi_u64:
+    case LD1B_z_p_bi_u8:
+      mnemonic = "ld1b";
+      break;
+    case LD1D_z_p_bi_u64:
+      mnemonic = "ld1d";
+      break;
+    case LD1H_z_p_bi_u16:
+    case LD1H_z_p_bi_u32:
+    case LD1H_z_p_bi_u64:
+      mnemonic = "ld1h";
+      break;
+    case LD1SB_z_p_bi_s16:
+    case LD1SB_z_p_bi_s32:
+    case LD1SB_z_p_bi_s64:
+      mnemonic = "ld1sb";
+      break;
+    case LD1SH_z_p_bi_s32:
+    case LD1SH_z_p_bi_s64:
+      mnemonic = "ld1sh";
+      break;
+    case LD1SW_z_p_bi_s64:
+      mnemonic = "ld1sw";
+      break;
+    case LD1W_z_p_bi_u32:
+    case LD1W_z_p_bi_u64:
+      mnemonic = "ld1w";
+      break;
+    default:
+      form = "(SVEContiguousLoad_ScalarPlusImm)";
+      suffix = NULL;
+      break;
+  }
+
+  Format(instr, mnemonic, form, suffix);
+}
+
+void Disassembler::VisitSVEContiguousLoad_ScalarPlusScalar(
+    const Instruction *instr) {
+  const char *mnemonic = "unimplemented";
+  const char *form = "{'Zt.'tlss}, 'Pgl/z, ['Xns, 'Xm";
+  const char *suffix = NULL;
+
+  switch (instr->Mask(SVEContiguousLoad_ScalarPlusScalarMask)) {
+    case LD1B_z_p_br_u16:
+    case LD1B_z_p_br_u32:
+    case LD1B_z_p_br_u64:
+    case LD1B_z_p_br_u8:
+      mnemonic = "ld1b";
+      suffix = "]";
+      break;
+    case LD1D_z_p_br_u64:
+      mnemonic = "ld1d";
+      suffix = ", lsl #'u2423]";
+      break;
+    case LD1H_z_p_br_u16:
+    case LD1H_z_p_br_u32:
+    case LD1H_z_p_br_u64:
+      mnemonic = "ld1h";
+      suffix = ", lsl #'u2423]";
+      break;
+    case LD1SB_z_p_br_s16:
+    case LD1SB_z_p_br_s32:
+    case LD1SB_z_p_br_s64:
+      mnemonic = "ld1sb";
+      suffix = "]";
+      break;
+    case LD1SH_z_p_br_s32:
+    case LD1SH_z_p_br_s64:
+      mnemonic = "ld1sh";
+      suffix = ", lsl #1]";
+      break;
+    case LD1SW_z_p_br_s64:
+      mnemonic = "ld1sw";
+      suffix = ", lsl #2]";
+      break;
+    case LD1W_z_p_br_u32:
+    case LD1W_z_p_br_u64:
+      mnemonic = "ld1w";
+      suffix = ", lsl #'u2423]";
+      break;
+    default:
+      form = "(SVEContiguousLoad_ScalarPlusScalar)";
+      suffix = NULL;
+      break;
+  }
+
+  Format(instr, mnemonic, form, suffix);
+}
 
 void Disassembler::VisitReserved(const Instruction *instr) {
   // UDF is the only instruction in this group, and the Decoder is precise.
@@ -5059,14 +9633,18 @@ int64_t Disassembler::CodeRelativeAddress(const void *addr) {
 
 void Disassembler::Format(const Instruction *instr,
                           const char *mnemonic,
-                          const char *format) {
+                          const char *format0,
+                          const char *format1) {
   VIXL_ASSERT(mnemonic != NULL);
   ResetOutput();
   Substitute(instr, mnemonic);
-  if (format != NULL) {
+  if (format0 != NULL) {
     VIXL_ASSERT(buffer_pos_ < buffer_size_);
     buffer_[buffer_pos_++] = ' ';
-    Substitute(instr, format);
+    Substitute(instr, format0);
+    if (format1 != NULL) {
+      Substitute(instr, format1);
+    }
   }
   VIXL_ASSERT(buffer_pos_ < buffer_size_);
   buffer_[buffer_pos_] = 0;
@@ -5091,10 +9669,11 @@ void Disassembler::Substitute(const Instruction *instr, const char *string) {
 int Disassembler::SubstituteField(const Instruction *instr,
                                   const char *format) {
   switch (format[0]) {
-    // NB. The remaining substitution prefix characters are: GJKUZ.
-    case 'R':  // Register. X or W, selected by sf bit.
+    // NB. The remaining substitution prefix upper-case characters are: JU.
+    case 'R':  // Register. X or W, selected by sf (or alternative) bit.
     case 'F':  // FP register. S or D, selected by type field.
     case 'V':  // Vector register, V, vector format.
+    case 'Z':  // Scalable vector register.
     case 'W':
     case 'X':
     case 'B':
@@ -5103,14 +9682,14 @@ int Disassembler::SubstituteField(const Instruction *instr,
     case 'D':
     case 'Q':
       return SubstituteRegisterField(instr, format);
+    case 'P':
+      return SubstitutePredicateRegisterField(instr, format);
     case 'I':
       return SubstituteImmediateField(instr, format);
     case 'L':
       return SubstituteLiteralField(instr, format);
     case 'N':
       return SubstituteShiftField(instr, format);
-    case 'P':
-      return SubstitutePrefetchField(instr, format);
     case 'C':
       return SubstituteConditionField(instr, format);
     case 'E':
@@ -5127,6 +9706,15 @@ int Disassembler::SubstituteField(const Instruction *instr,
       return SubstituteCrField(instr, format);
     case 'G':
       return SubstituteSysOpField(instr, format);
+    case 'p':
+      return SubstitutePrefetchField(instr, format);
+    case 'u':
+    case 's':
+      return SubstituteIntField(instr, format);
+    case 't':
+      return SubstituteSVESize(instr, format);
+    case '?':
+      return SubstituteTernary(instr, format);
     default: {
       VIXL_UNREACHABLE();
       return 1;
@@ -5134,55 +9722,20 @@ int Disassembler::SubstituteField(const Instruction *instr,
   }
 }
 
+std::pair<unsigned, unsigned> Disassembler::GetRegNumForField(
+    const Instruction *instr, char reg_prefix, const char *field) {
+  unsigned reg_num = UINT_MAX;
+  unsigned field_len = 1;
 
-int Disassembler::SubstituteRegisterField(const Instruction *instr,
-                                          const char *format) {
-  char reg_prefix = format[0];
-  unsigned reg_num = 0;
-  unsigned field_len = 2;
-
-  switch (format[1]) {
+  switch (field[0]) {
     case 'd':
       reg_num = instr->GetRd();
-      if (format[2] == 'q') {
-        reg_prefix = instr->GetNEONQ() ? 'X' : 'W';
-        field_len = 3;
-      }
       break;
     case 'n':
       reg_num = instr->GetRn();
       break;
     case 'm':
       reg_num = instr->GetRm();
-      switch (format[2]) {
-        // Handle registers tagged with b (bytes), z (instruction), or
-        // r (registers), used for address updates in
-        // NEON load/store instructions.
-        case 'r':
-        case 'b':
-        case 'z': {
-          field_len = 3;
-          char *eimm;
-          int imm = static_cast<int>(strtol(&format[3], &eimm, 10));
-          field_len += eimm - &format[3];
-          if (reg_num == 31) {
-            switch (format[2]) {
-              case 'z':
-                imm *= (1 << instr->GetNEONLSSize());
-                break;
-              case 'r':
-                imm *= (instr->GetNEONQ() == 0) ? kDRegSizeInBytes
-                                                : kQRegSizeInBytes;
-                break;
-              case 'b':
-                break;
-            }
-            AppendToOutput("#%d", imm);
-            return field_len;
-          }
-          break;
-        }
-      }
       break;
     case 'e':
       // This is register Rm, but using a 4-bit specifier. Used in NEON
@@ -5197,72 +9750,121 @@ int Disassembler::SubstituteRegisterField(const Instruction *instr,
       break;
     case 't':
       reg_num = instr->GetRt();
-      if (format[0] == 'V') {
-        if ((format[2] >= '2') && (format[2] <= '4')) {
-          // Handle consecutive vector register specifiers Vt2, Vt3 and Vt4.
-          reg_num = (reg_num + format[2] - '1') % 32;
-          field_len = 3;
-        }
-      } else {
-        if (format[2] == '2') {
-          // Handle register specifier Rt2.
-          reg_num = instr->GetRt2();
-          field_len = 3;
-        }
-      }
       break;
-    case '(': {
-      switch (format[2]) {
-        case 's':
-          reg_num = instr->GetRs();
-          break;
-        case 't':
-          reg_num = instr->GetRt();
-          break;
-        default:
-          VIXL_UNREACHABLE();
-      }
+    default:
+      VIXL_UNREACHABLE();
+  }
 
-      VIXL_ASSERT(format[3] == '+');
-      int i = 4;
-      int addition = 0;
-      while (format[i] != ')') {
-        VIXL_ASSERT((format[i] >= '0') && (format[i] <= '9'));
-        addition *= 10;
-        addition += format[i] - '0';
-        ++i;
+  switch (field[1]) {
+    case '2':
+    case '3':
+    case '4':
+      if ((reg_prefix == 'V') || (reg_prefix == 'Z')) {  // Vt2/3/4, Zt2/3/4
+        VIXL_ASSERT(field[0] == 't');
+        reg_num = (reg_num + field[1] - '1') % 32;
+        field_len++;
+      } else {
+        VIXL_ASSERT((field[0] == 't') && (field[1] == '2'));
+        reg_num = instr->GetRt2();
+        field_len++;
       }
-      reg_num += addition;
-      field_len = i + 1;
       break;
+    case '+':  // Rt+, Rs+ (ie. Rt + 1, Rs + 1)
+      VIXL_ASSERT((reg_prefix == 'W') || (reg_prefix == 'X'));
+      VIXL_ASSERT((field[0] == 's') || (field[0] == 't'));
+      reg_num++;
+      field_len++;
+      break;
+    case 's':  // Core registers that are (w)sp rather than zr.
+      VIXL_ASSERT((reg_prefix == 'W') || (reg_prefix == 'X'));
+      reg_num = (reg_num == kZeroRegCode) ? kSPRegInternalCode : reg_num;
+      field_len++;
+      break;
+  }
+
+  VIXL_ASSERT(reg_num != UINT_MAX);
+  return std::make_pair(reg_num, field_len);
+}
+
+int Disassembler::SubstituteRegisterField(const Instruction *instr,
+                                          const char *format) {
+  unsigned field_len = 1;  // Initially, count only the first character.
+
+  // The first character of the register format field, eg R, X, S, etc.
+  char reg_prefix = format[0];
+
+  // Pointer to the character after the prefix. This may be one of the standard
+  // symbols representing a register encoding, or a two digit bit position,
+  // handled by the following code.
+  const char *reg_field = &format[1];
+
+  if (reg_prefix == 'R') {
+    bool is_x = instr->GetSixtyFourBits();
+    if (strspn(reg_field, "0123456789") == 2) {  // r20d, r31n, etc.
+      // Core W or X registers where the type is determined by a specified bit
+      // position, eg. 'R20d, 'R05n. This is like the 'Rd syntax, where bit 31
+      // is implicitly used to select between W and X.
+      int bitpos = ((reg_field[0] - '0') * 10) + (reg_field[1] - '0');
+      VIXL_ASSERT(bitpos <= 31);
+      is_x = (instr->ExtractBit(bitpos) == 1);
+      reg_field = &format[3];
+      field_len += 2;
     }
-    default:
-      VIXL_UNREACHABLE();
+    reg_prefix = is_x ? 'X' : 'W';
   }
 
-  // Increase field length for registers tagged as stack.
-  if (format[1] != '(' && format[2] == 's') {
-    field_len = 3;
+  std::pair<unsigned, unsigned> rn =
+      GetRegNumForField(instr, reg_prefix, reg_field);
+  unsigned reg_num = rn.first;
+  field_len += rn.second;
+
+  if (reg_field[0] == 'm') {
+    switch (reg_field[1]) {
+      // Handle registers tagged with b (bytes), z (instruction), or
+      // r (registers), used for address updates in NEON load/store
+      // instructions.
+      case 'r':
+      case 'b':
+      case 'z': {
+        VIXL_ASSERT(reg_prefix == 'X');
+        field_len = 3;
+        char *eimm;
+        int imm = static_cast<int>(strtol(&reg_field[2], &eimm, 10));
+        field_len += eimm - &reg_field[2];
+        if (reg_num == 31) {
+          switch (reg_field[1]) {
+            case 'z':
+              imm *= (1 << instr->GetNEONLSSize());
+              break;
+            case 'r':
+              imm *= (instr->GetNEONQ() == 0) ? kDRegSizeInBytes
+                                              : kQRegSizeInBytes;
+              break;
+            case 'b':
+              break;
+          }
+          AppendToOutput("#%d", imm);
+          return field_len;
+        }
+        break;
+      }
+    }
   }
 
   CPURegister::RegisterType reg_type = CPURegister::kRegister;
   unsigned reg_size = kXRegSize;
 
-  switch (reg_prefix) {
-    case 'R':
-      reg_prefix = instr->GetSixtyFourBits() ? 'X' : 'W';
-      break;
-    case 'F':
-      switch (instr->GetFPType()) {
-        case 3:
-          reg_prefix = 'H';
-          break;
-        case 0:
-          reg_prefix = 'S';
-          break;
-        default:
-          reg_prefix = 'D';
-      }
+  if (reg_prefix == 'F') {
+    switch (instr->GetFPType()) {
+      case 3:
+        reg_prefix = 'H';
+        break;
+      case 0:
+        reg_prefix = 'S';
+        break;
+      default:
+        reg_prefix = 'D';
+    }
   }
 
   switch (reg_prefix) {
@@ -5295,22 +9897,51 @@ int Disassembler::SubstituteRegisterField(const Instruction *instr,
       reg_size = kQRegSize;
       break;
     case 'V':
+      if (reg_field[1] == 'v') {
+        reg_type = CPURegister::kVRegister;
+        reg_size = 1 << (instr->GetSVESize() + 3);
+        field_len++;
+        break;
+      }
       AppendToOutput("v%d", reg_num);
       return field_len;
+    case 'Z':
+      AppendToOutput("z%d", reg_num);
+      return field_len;
     default:
       VIXL_UNREACHABLE();
   }
 
-  if ((reg_type == CPURegister::kRegister) && (reg_num == kZeroRegCode) &&
-      (format[2] == 's')) {
-    reg_num = kSPRegInternalCode;
-  }
-
   AppendRegisterNameToOutput(instr, CPURegister(reg_num, reg_size, reg_type));
 
   return field_len;
 }
 
+int Disassembler::SubstitutePredicateRegisterField(const Instruction *instr,
+                                                   const char *format) {
+  VIXL_ASSERT(format[0] == 'P');
+  switch (format[1]) {
+    // This field only supports P register that are always encoded in the same
+    // position.
+    case 'd':
+    case 't':
+      AppendToOutput("p%u", instr->GetPt());
+      break;
+    case 'n':
+      AppendToOutput("p%u", instr->GetPn());
+      break;
+    case 'm':
+      AppendToOutput("p%u", instr->GetPm());
+      break;
+    case 'g':
+      VIXL_ASSERT(format[2] == 'l');
+      AppendToOutput("p%u", instr->GetPgLow8());
+      return 3;
+    default:
+      VIXL_UNREACHABLE();
+  }
+  return 2;
+}
 
 int Disassembler::SubstituteImmediateField(const Instruction *instr,
                                            const char *format) {
@@ -5391,36 +10022,92 @@ int Disassembler::SubstituteImmediateField(const Instruction *instr,
       return 6;
     }
     case 'A': {  // IAddSub.
-      VIXL_ASSERT(instr->GetShiftAddSub() <= 1);
-      int64_t imm = instr->GetImmAddSub() << (12 * instr->GetShiftAddSub());
+      int64_t imm = instr->GetImmAddSub() << (12 * instr->GetImmAddSubShift());
       AppendToOutput("#0x%" PRIx64 " (%" PRId64 ")", imm, imm);
       return 7;
     }
-    case 'F': {                // IFPHalf, IFPSingle, IFPDouble, or IFPFBits.
-      if (format[3] == 'F') {  // IFPFbits.
-        AppendToOutput("#%" PRId32, 64 - instr->GetFPScale());
-        return 8;
-      } else {
-        AppendToOutput("#0x%" PRIx32 " (%.4f)",
-                       instr->GetImmFP(),
-                       format[3] == 'H'
-                           ? FPToFloat(instr->GetImmFP16(), kIgnoreDefaultNaN)
-                           : (format[3] == 'S') ? instr->GetImmFP32()
-                                                : instr->GetImmFP64());
-        if (format[3] == 'H') {
-          return 7;
-        } else {
-          return 9;
-        }
+    case 'F': {  // IFP, IFPNeon, IFPSve or IFPFBits.
+      int imm8 = 0;
+      int len = strlen("IFP");
+      switch (format[3]) {
+        case 'F':
+          VIXL_ASSERT(strncmp(format, "IFPFBits", strlen("IFPFBits")) == 0);
+          AppendToOutput("#%" PRId32, 64 - instr->GetFPScale());
+          return strlen("IFPFBits");
+        case 'N':
+          VIXL_ASSERT(strncmp(format, "IFPNeon", strlen("IFPNeon")) == 0);
+          imm8 = instr->GetImmNEONabcdefgh();
+          len += strlen("Neon");
+          break;
+        case 'S':
+          VIXL_ASSERT(strncmp(format, "IFPSve", strlen("IFPSve")) == 0);
+          imm8 = instr->ExtractBits(12, 5);
+          len += strlen("Sve");
+          break;
+        default:
+          VIXL_ASSERT(strncmp(format, "IFP", strlen("IFP")) == 0);
+          imm8 = instr->GetImmFP();
+          break;
       }
+      AppendToOutput("#0x%" PRIx32 " (%.4f)",
+                     imm8,
+                     Instruction::Imm8ToFP32(imm8));
+      return len;
     }
     case 'H': {  // IH - ImmHint
       AppendToOutput("#%" PRId32, instr->GetImmHint());
       return 2;
     }
     case 'T': {  // ITri - Immediate Triangular Encoded.
-      AppendToOutput("#0x%" PRIx64, instr->GetImmLogical());
-      return 4;
+      if (format[4] == 'S') {
+        VIXL_ASSERT((format[5] == 'v') && (format[6] == 'e'));
+        switch (format[7]) {
+          case 'l':
+            // SVE logical immediate encoding.
+            AppendToOutput("#0x%" PRIx64, instr->GetSVEImmLogical());
+            return 8;
+          case 'p': {
+            // SVE predicated shift immediate encoding, lsl.
+            std::pair<int, int> shift_and_lane_size =
+                instr->GetSVEImmShiftAndLaneSizeLog2(
+                    /* is_predicated = */ true);
+            int lane_bits = 8 << shift_and_lane_size.second;
+            AppendToOutput("#%" PRId32, lane_bits - shift_and_lane_size.first);
+            return 8;
+          }
+          case 'q': {
+            // SVE predicated shift immediate encoding, asr and lsr.
+            std::pair<int, int> shift_and_lane_size =
+                instr->GetSVEImmShiftAndLaneSizeLog2(
+                    /* is_predicated = */ true);
+            AppendToOutput("#%" PRId32, shift_and_lane_size.first);
+            return 8;
+          }
+          case 'r': {
+            // SVE unpredicated shift immediate encoding, lsl.
+            std::pair<int, int> shift_and_lane_size =
+                instr->GetSVEImmShiftAndLaneSizeLog2(
+                    /* is_predicated = */ false);
+            int lane_bits = 8 << shift_and_lane_size.second;
+            AppendToOutput("#%" PRId32, lane_bits - shift_and_lane_size.first);
+            return 8;
+          }
+          case 's': {
+            // SVE unpredicated shift immediate encoding, asr and lsr.
+            std::pair<int, int> shift_and_lane_size =
+                instr->GetSVEImmShiftAndLaneSizeLog2(
+                    /* is_predicated = */ false);
+            AppendToOutput("#%" PRId32, shift_and_lane_size.first);
+            return 8;
+          }
+          default:
+            VIXL_UNREACHABLE();
+            return 0;
+        }
+      } else {
+        AppendToOutput("#0x%" PRIx64, instr->GetImmLogical());
+        return 4;
+      }
     }
     case 'N': {  // INzcv.
       int nzcv = (instr->GetNzcv() << Flags_offset);
@@ -5442,12 +10129,21 @@ int Disassembler::SubstituteImmediateField(const Instruction *instr,
       AppendToOutput("#%" PRId32, instr->GetImmS());
       return 8;
     }
-    case 'S': {  // IS - Test and branch bit.
+    case 't': {  // It - Test and branch bit.
       AppendToOutput("#%" PRId32,
                      (instr->GetImmTestBranchBit5() << 5) |
                          instr->GetImmTestBranchBit40());
       return 2;
     }
+    case 'S': {  // ISveSvl - SVE 'mul vl' immediate for structured ld/st.
+      VIXL_ASSERT(strncmp(format, "ISveSvl", 7) == 0);
+      int imm = instr->ExtractSignedBits(19, 16);
+      if (imm != 0) {
+        int reg_count = instr->ExtractBits(22, 21) + 1;
+        AppendToOutput(", #%d, mul vl", imm * reg_count);
+      }
+      return 7;
+    }
     case 's': {  // Is - Shift (immediate).
       switch (format[2]) {
         case '1': {  // Is1 - SSHR.
@@ -5539,6 +10235,13 @@ int Disassembler::SubstituteImmediateField(const Instruction *instr,
               }
             }
             return 0;
+          } else if (strncmp(format,
+                             "IVInsSVEIndex",
+                             strlen("IVInsSVEIndex")) == 0) {
+            std::pair<int, int> index_and_lane_size =
+                instr->GetSVEPermuteIndexAndLaneSizeLog2();
+            AppendToOutput("%d", index_and_lane_size.first);
+            return strlen("IVInsSVEIndex");
           }
           VIXL_FALLTHROUGH();
         }
@@ -5547,27 +10250,7 @@ int Disassembler::SubstituteImmediateField(const Instruction *instr,
           return 9;
         }
         case 'M': {  // Modified Immediate cases.
-          if (strncmp(format, "IVMIImmFPHalf", strlen("IVMIImmFPHalf")) == 0) {
-            AppendToOutput("#0x%" PRIx32 " (%.4f)",
-                           instr->GetImmNEONabcdefgh(),
-                           FPToFloat(instr->GetImmNEONFP16(),
-                                     kIgnoreDefaultNaN));
-            return strlen("IVMIImmFPHalf");
-          } else if (strncmp(format,
-                             "IVMIImmFPSingle",
-                             strlen("IVMIImmFPSingle")) == 0) {
-            AppendToOutput("#0x%" PRIx32 " (%.4f)",
-                           instr->GetImmNEONabcdefgh(),
-                           instr->GetImmNEONFP32());
-            return strlen("IVMIImmFPSingle");
-          } else if (strncmp(format,
-                             "IVMIImmFPDouble",
-                             strlen("IVMIImmFPDouble")) == 0) {
-            AppendToOutput("#0x%" PRIx32 " (%.4f)",
-                           instr->GetImmNEONabcdefgh(),
-                           instr->GetImmNEONFP64());
-            return strlen("IVMIImmFPDouble");
-          } else if (strncmp(format, "IVMIImm8", strlen("IVMIImm8")) == 0) {
+          if (strncmp(format, "IVMIImm8", strlen("IVMIImm8")) == 0) {
             uint64_t imm8 = instr->GetImmNEONabcdefgh();
             AppendToOutput("#0x%" PRIx64, imm8);
             return strlen("IVMIImm8");
@@ -5647,6 +10330,48 @@ int Disassembler::SubstituteImmediateField(const Instruction *instr,
         }
       }
     }
+    case 'p': {  // Ipc - SVE predicate constraint specifier.
+      VIXL_ASSERT(format[2] == 'c');
+      unsigned pattern = instr->GetImmSVEPredicateConstraint();
+      switch (pattern) {
+        // VL1-VL8 are encoded directly.
+        case SVE_VL1:
+        case SVE_VL2:
+        case SVE_VL3:
+        case SVE_VL4:
+        case SVE_VL5:
+        case SVE_VL6:
+        case SVE_VL7:
+        case SVE_VL8:
+          AppendToOutput("vl%u", pattern);
+          break;
+        // VL16-VL256 are encoded as log2(N) + c.
+        case SVE_VL16:
+        case SVE_VL32:
+        case SVE_VL64:
+        case SVE_VL128:
+        case SVE_VL256:
+          AppendToOutput("vl%u", 16 << (pattern - SVE_VL16));
+          break;
+        // Special cases.
+        case SVE_POW2:
+          AppendToOutput("pow2");
+          break;
+        case SVE_MUL4:
+          AppendToOutput("mul4");
+          break;
+        case SVE_MUL3:
+          AppendToOutput("mul3");
+          break;
+        case SVE_ALL:
+          AppendToOutput("all");
+          break;
+        default:
+          AppendToOutput("#0x%x", pattern);
+          break;
+      }
+      return 3;
+    }
     default: {
       VIXL_UNIMPLEMENTED();
       return 0;
@@ -5736,11 +10461,11 @@ int Disassembler::SubstituteShiftField(const Instruction *instr,
   VIXL_ASSERT(instr->GetShiftDP() <= 0x3);
 
   switch (format[1]) {
-    case 'D': {  // HDP.
+    case 'D': {  // NDP.
       VIXL_ASSERT(instr->GetShiftDP() != ROR);
       VIXL_FALLTHROUGH();
     }
-    case 'L': {  // HLo.
+    case 'L': {  // NLo.
       if (instr->GetImmDPShift() != 0) {
         const char *shift_type[] = {"lsl", "lsr", "asr", "ror"};
         AppendToOutput(", %s #%" PRId32,
@@ -5749,6 +10474,14 @@ int Disassembler::SubstituteShiftField(const Instruction *instr,
       }
       return 3;
     }
+    case 'S': {  // NSveS (SVE structured load/store indexing shift).
+      VIXL_ASSERT(strncmp(format, "NSveS", 5) == 0);
+      int msz = instr->ExtractBits(24, 23);
+      if (msz > 0) {
+        AppendToOutput(", lsl #%d", msz);
+      }
+      return 5;
+    }
     default:
       VIXL_UNIMPLEMENTED();
       return 0;
@@ -5919,30 +10652,43 @@ int Disassembler::SubstituteLSRegOffsetField(const Instruction *instr,
 
 int Disassembler::SubstitutePrefetchField(const Instruction *instr,
                                           const char *format) {
-  VIXL_ASSERT(format[0] == 'P');
+  VIXL_ASSERT(format[0] == 'p');
   USE(format);
 
-  static const char *hints[] = {"ld", "li", "st"};
+  bool is_sve =
+      (strncmp(format, "prefSVEOp", strlen("prefSVEOp")) == 0) ? true : false;
+  int placeholder_length = is_sve ? 9 : 6;
   static const char *stream_options[] = {"keep", "strm"};
 
-  unsigned hint = instr->GetPrefetchHint();
+  auto get_hints = [](bool is_sve) -> std::vector<std::string> {
+    static const std::vector<std::string> sve_hints = {"ld", "st"};
+    static const std::vector<std::string> core_hints = {"ld", "li", "st"};
+    return (is_sve) ? sve_hints : core_hints;
+  };
+
+  std::vector<std::string> hints = get_hints(is_sve);
+  unsigned hint =
+      is_sve ? instr->GetSVEPrefetchHint() : instr->GetPrefetchHint();
   unsigned target = instr->GetPrefetchTarget() + 1;
   unsigned stream = instr->GetPrefetchStream();
 
-  if ((hint >= ArrayLength(hints)) || (target > 3)) {
+  if ((hint >= hints.size()) || (target > 3)) {
     // Unallocated prefetch operations.
-    int prefetch_mode = instr->GetImmPrefetchOperation();
-    AppendToOutput("#0b%c%c%c%c%c",
-                   (prefetch_mode & (1 << 4)) ? '1' : '0',
-                   (prefetch_mode & (1 << 3)) ? '1' : '0',
-                   (prefetch_mode & (1 << 2)) ? '1' : '0',
-                   (prefetch_mode & (1 << 1)) ? '1' : '0',
-                   (prefetch_mode & (1 << 0)) ? '1' : '0');
+    if (is_sve) {
+      std::bitset<4> prefetch_mode(instr->GetSVEImmPrefetchOperation());
+      AppendToOutput("#0b%s", prefetch_mode.to_string().c_str());
+    } else {
+      std::bitset<5> prefetch_mode(instr->GetImmPrefetchOperation());
+      AppendToOutput("#0b%s", prefetch_mode.to_string().c_str());
+    }
   } else {
     VIXL_ASSERT(stream < ArrayLength(stream_options));
-    AppendToOutput("p%sl%d%s", hints[hint], target, stream_options[stream]);
+    AppendToOutput("p%sl%d%s",
+                   hints[hint].c_str(),
+                   target,
+                   stream_options[stream]);
   }
-  return 6;
+  return placeholder_length;
 }
 
 int Disassembler::SubstituteBarrierField(const Instruction *instr,
@@ -5997,6 +10743,159 @@ int Disassembler::SubstituteCrField(const Instruction *instr,
   return 2;
 }
 
+int Disassembler::SubstituteIntField(const Instruction *instr,
+                                     const char *format) {
+  VIXL_ASSERT((format[0] == 'u') || (format[0] == 's'));
+
+  // A generic signed or unsigned int field uses a placeholder of the form
+  // 'sAABB and 'uAABB respectively where AA and BB are two digit bit positions
+  // between 00 and 31, and AA >= BB. The placeholder is substituted with the
+  // decimal integer represented by the bits in the instruction between
+  // positions AA and BB inclusive.
+  //
+  // In addition, split fields can be represented using 'sAABB:CCDD, where CCDD
+  // become the least-significant bits of the result, and bit AA is the sign bit
+  // (if 's is used).
+  int32_t bits = 0;
+  int width = 0;
+  const char *c = format;
+  do {
+    c++;  // Skip the 'u', 's' or ':'.
+    VIXL_ASSERT(strspn(c, "0123456789") == 4);
+    int msb = ((c[0] - '0') * 10) + (c[1] - '0');
+    int lsb = ((c[2] - '0') * 10) + (c[3] - '0');
+    c += 4;  // Skip the characters we just read.
+    int chunk_width = msb - lsb + 1;
+    VIXL_ASSERT((chunk_width > 0) && (chunk_width < 32));
+    bits = (bits << chunk_width) | (instr->ExtractBits(msb, lsb));
+    width += chunk_width;
+  } while (*c == ':');
+  VIXL_ASSERT(IsUintN(width, bits));
+
+  if (format[0] == 's') {
+    bits = ExtractSignedBitfield32(width - 1, 0, bits);
+  }
+
+  if (*c == '+') {
+    // A "+n" trailing the format specifier indicates the extracted value should
+    // be incremented by n. This is for cases where the encoding is zero-based,
+    // but range of values is not, eg. values [1, 16] encoded as [0, 15]
+    char *new_c;
+    uint64_t value = strtoul(c + 1, &new_c, 10);
+    c = new_c;
+    VIXL_ASSERT(IsInt32(value));
+    bits += value;
+  } else if (*c == '*') {
+    // Similarly, a "*n" trailing the format specifier indicates the extracted
+    // value should be multiplied by n. This is for cases where the encoded
+    // immediate is scaled, for example by access size.
+    char *new_c;
+    uint64_t value = strtoul(c + 1, &new_c, 10);
+    c = new_c;
+    VIXL_ASSERT(IsInt32(value));
+    bits *= value;
+  }
+
+  AppendToOutput("%d", bits);
+
+  return static_cast<int>(c - format);
+}
+
+int Disassembler::SubstituteSVESize(const Instruction *instr,
+                                    const char *format) {
+  USE(format);
+  VIXL_ASSERT(format[0] == 't');
+
+  static const char sizes[] = {'b', 'h', 's', 'd', 'q'};
+  // TODO: only the most common case for <size> is supported at the moment,
+  // and even then, the RESERVED values are handled as if they're not
+  // reserved.
+  unsigned size_in_bytes_log2 = instr->GetSVESize();
+  int placeholder_length = 1;
+  switch (format[1]) {
+    case 'l':
+      placeholder_length++;
+      if (format[2] == 's') {
+        // 'tls: Loads and stores
+        size_in_bytes_log2 = instr->ExtractBits(22, 21);
+        placeholder_length++;
+        if (format[3] == 's') {
+          // Sign extension load.
+          unsigned msize = instr->ExtractBits(24, 23);
+          if (msize > size_in_bytes_log2) size_in_bytes_log2 ^= 0x3;
+          placeholder_length++;
+        }
+      } else {
+        // 'tl: Logical operations
+        size_in_bytes_log2 = instr->GetSVEBitwiseImmLaneSizeInBytesLog2();
+      }
+      break;
+    case 'm':  // 'tmsz
+      VIXL_ASSERT(strncmp(format, "tmsz", 4) == 0);
+      placeholder_length += 3;
+      size_in_bytes_log2 = instr->ExtractBits(24, 23);
+      break;
+    case 's':
+      if (format[2] == 'z') {
+        VIXL_ASSERT((format[3] == 'x') || (format[3] == 's') ||
+                    (format[3] == 'p'));
+        if (format[3] == 'x') {
+          // 'tszx: Indexes.
+          std::pair<int, int> index_and_lane_size =
+              instr->GetSVEPermuteIndexAndLaneSizeLog2();
+          size_in_bytes_log2 = index_and_lane_size.second;
+        } else if (format[3] == 'p') {
+          // 'tszp: Predicated shifts.
+          std::pair<int, int> shift_and_lane_size =
+              instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ true);
+          size_in_bytes_log2 = shift_and_lane_size.second;
+        } else {
+          // 'tszs: Unpredicated shifts.
+          std::pair<int, int> shift_and_lane_size =
+              instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
+          size_in_bytes_log2 = shift_and_lane_size.second;
+        }
+        placeholder_length += 3;  // skip `sz[x|s]`
+      }
+      break;
+    case 'h':
+      // Half size of the lane size field.
+      size_in_bytes_log2 -= 1;
+      placeholder_length++;
+      break;
+    case 'q':
+      // Quarter size of the lane size field.
+      size_in_bytes_log2 -= 2;
+      placeholder_length++;
+      break;
+    default:
+      break;
+  }
+
+  VIXL_ASSERT(size_in_bytes_log2 < ArrayLength(sizes));
+  AppendToOutput("%c", sizes[size_in_bytes_log2]);
+
+  return placeholder_length;
+}
+
+int Disassembler::SubstituteTernary(const Instruction *instr,
+                                    const char *format) {
+  VIXL_ASSERT((format[0] == '?') && (format[3] == ':'));
+
+  // The ternary substitution of the format "'?bb:TF" is replaced by a single
+  // character, either T or F, depending on the value of the bit at position
+  // bb in the instruction. For example, "'?31:xw" is substituted with "x" if
+  // bit 31 is true, and "w" otherwise.
+  VIXL_ASSERT(strspn(&format[1], "0123456789") == 2);
+  char *c;
+  uint64_t value = strtoul(&format[1], &c, 10);
+  VIXL_ASSERT(value < (kInstructionSize * kBitsPerByte));
+  VIXL_ASSERT((*c == ':') && (strlen(c) >= 3));  // Minimum of ":TF"
+  c++;
+  AppendToOutput("%c", c[1 - instr->ExtractBit(static_cast<int>(value))]);
+  return 6;
+}
+
 void Disassembler::ResetOutput() {
   buffer_pos_ = 0;
   buffer_[buffer_pos_] = 0;
@@ -6040,9 +10939,28 @@ void PrintDisassembler::DisassembleBuffer(const Instruction *start,
 
 
 void PrintDisassembler::ProcessOutput(const Instruction *instr) {
+  int64_t address = CodeRelativeAddress(instr);
+
+  uint64_t abs_address;
+  const char *sign;
+  if (signed_addresses_) {
+    if (address < 0) {
+      sign = "-";
+      abs_address = -static_cast<uint64_t>(address);
+    } else {
+      // Leave a leading space, to maintain alignment.
+      sign = " ";
+      abs_address = address;
+    }
+  } else {
+    sign = "";
+    abs_address = address;
+  }
+
   int bytes_printed = fprintf(stream_,
-                              "0x%016" PRIx64 "  %08" PRIx32 "\t\t%s",
-                              reinterpret_cast<uint64_t>(instr),
+                              "%s0x%016" PRIx64 "  %08" PRIx32 "\t\t%s",
+                              sign,
+                              abs_address,
                               instr->GetInstructionBits(),
                               GetOutput());
   if (cpu_features_auditor_ != NULL) {
diff --git a/src/aarch64/disasm-aarch64.h b/src/aarch64/disasm-aarch64.h
index c650bee9..176fb790 100644
--- a/src/aarch64/disasm-aarch64.h
+++ b/src/aarch64/disasm-aarch64.h
@@ -27,6 +27,8 @@
 #ifndef VIXL_AARCH64_DISASM_AARCH64_H
 #define VIXL_AARCH64_DISASM_AARCH64_H
 
+#include <utility>
+
 #include "../globals-vixl.h"
 #include "../utils-vixl.h"
 
@@ -112,10 +114,13 @@ class Disassembler : public DecoderVisitor {
  private:
   void Format(const Instruction* instr,
               const char* mnemonic,
-              const char* format);
+              const char* format0,
+              const char* format1 = NULL);
   void Substitute(const Instruction* instr, const char* string);
   int SubstituteField(const Instruction* instr, const char* format);
   int SubstituteRegisterField(const Instruction* instr, const char* format);
+  int SubstitutePredicateRegisterField(const Instruction* instr,
+                                       const char* format);
   int SubstituteImmediateField(const Instruction* instr, const char* format);
   int SubstituteLiteralField(const Instruction* instr, const char* format);
   int SubstituteBitfieldImmediateField(const Instruction* instr,
@@ -130,6 +135,14 @@ class Disassembler : public DecoderVisitor {
   int SubstituteBarrierField(const Instruction* instr, const char* format);
   int SubstituteSysOpField(const Instruction* instr, const char* format);
   int SubstituteCrField(const Instruction* instr, const char* format);
+  int SubstituteIntField(const Instruction* instr, const char* format);
+  int SubstituteSVESize(const Instruction* instr, const char* format);
+  int SubstituteTernary(const Instruction* instr, const char* format);
+
+  std::pair<unsigned, unsigned> GetRegNumForField(const Instruction* instr,
+                                                  char reg_prefix,
+                                                  const char* field);
+
   bool RdIsZROrSP(const Instruction* instr) const {
     return (instr->GetRd() == kZeroRegCode);
   }
@@ -173,6 +186,7 @@ class PrintDisassembler : public Disassembler {
       : cpu_features_auditor_(NULL),
         cpu_features_prefix_("// Needs: "),
         cpu_features_suffix_(""),
+        signed_addresses_(false),
         stream_(stream) {}
 
   // Convenience helpers for quick disassembly, without having to manually
@@ -201,12 +215,23 @@ class PrintDisassembler : public Disassembler {
     cpu_features_suffix_ = suffix;
   }
 
+  // By default, addresses are printed as simple, unsigned 64-bit hex values.
+  //
+  // With `PrintSignedAddresses(true)`:
+  //  - negative addresses are printed as "-0x1234...",
+  //  - positive addresses have a leading space, like " 0x1234...", to maintain
+  //    alignment.
+  //
+  // This is most useful in combination with Disassembler::MapCodeAddress(...).
+  void PrintSignedAddresses(bool s) { signed_addresses_ = s; }
+
  protected:
   virtual void ProcessOutput(const Instruction* instr) VIXL_OVERRIDE;
 
   CPUFeaturesAuditor* cpu_features_auditor_;
   const char* cpu_features_prefix_;
   const char* cpu_features_suffix_;
+  bool signed_addresses_;
 
  private:
   FILE* stream_;
diff --git a/src/aarch64/instructions-aarch64.cc b/src/aarch64/instructions-aarch64.cc
index a99a0459..b3e28384 100644
--- a/src/aarch64/instructions-aarch64.cc
+++ b/src/aarch64/instructions-aarch64.cc
@@ -35,7 +35,8 @@ static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
                                     unsigned width) {
   VIXL_ASSERT((width == 2) || (width == 4) || (width == 8) || (width == 16) ||
               (width == 32));
-  VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
+  VIXL_ASSERT((reg_size == kBRegSize) || (reg_size == kHRegSize) ||
+              (reg_size == kSRegSize) || (reg_size == kDRegSize));
   uint64_t result = value & ((UINT64_C(1) << width) - 1);
   for (unsigned i = width; i < reg_size; i *= 2) {
     result |= (result << i);
@@ -43,6 +44,503 @@ static uint64_t RepeatBitsAcrossReg(unsigned reg_size,
   return result;
 }
 
+bool Instruction::CanTakeSVEMovprfx(const Instruction* movprfx) const {
+  bool movprfx_is_predicated = movprfx->Mask(SVEMovprfxMask) == MOVPRFX_z_p_z;
+  bool movprfx_is_unpredicated =
+      movprfx->Mask(SVEConstructivePrefix_UnpredicatedMask) == MOVPRFX_z_z;
+  VIXL_ASSERT(movprfx_is_predicated != movprfx_is_unpredicated);
+
+  int movprfx_zd = movprfx->GetRd();
+  int movprfx_pg = movprfx_is_predicated ? movprfx->GetPgLow8() : -1;
+  VectorFormat movprfx_vform =
+      movprfx_is_predicated ? movprfx->GetSVEVectorFormat() : kFormatUndefined;
+
+  bool pg_matches_low8 = movprfx_pg == GetPgLow8();
+  bool vform_matches = movprfx_vform == GetSVEVectorFormat();
+  bool zd_matches = movprfx_zd == GetRd();
+  bool zd_matches_zm = movprfx_zd == GetRm();
+  bool zd_matches_zn = movprfx_zd == GetRn();
+
+  switch (Mask(SVEBitwiseLogicalWithImm_UnpredicatedMask)) {
+    case AND_z_zi:
+    case EOR_z_zi:
+    case ORR_z_zi:
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEBitwiseLogical_PredicatedMask)) {
+    case AND_z_p_zz:
+    case BIC_z_p_zz:
+    case EOR_z_p_zz:
+    case ORR_z_p_zz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEBitwiseShiftByImm_PredicatedMask)) {
+    case ASRD_z_p_zi:
+    case ASR_z_p_zi:
+    case LSL_z_p_zi:
+    case LSR_z_p_zi:
+      if (movprfx_is_predicated) {
+        if (!pg_matches_low8) return false;
+        unsigned tsz = ExtractBits<0x00c00300>();
+        VectorFormat instr_vform =
+            SVEFormatFromLaneSizeInBytesLog2(HighestSetBitPosition(tsz));
+        if (movprfx_vform != instr_vform) return false;
+      }
+      return zd_matches;
+  }
+  switch (Mask(SVEBitwiseShiftByVector_PredicatedMask)) {
+    case ASRR_z_p_zz:
+    case ASR_z_p_zz:
+    case LSLR_z_p_zz:
+    case LSL_z_p_zz:
+    case LSRR_z_p_zz:
+    case LSR_z_p_zz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEBitwiseShiftByWideElements_PredicatedMask)) {
+    case ASR_z_p_zw:
+    case LSL_z_p_zw:
+    case LSR_z_p_zw:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEConditionallyBroadcastElementToVectorMask)) {
+    case CLASTA_z_p_zz:
+    case CLASTB_z_p_zz:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVECopyFPImm_PredicatedMask)) {
+    case FCPY_z_p_i:
+      if (movprfx_is_predicated) {
+        if (!vform_matches) return false;
+        if (movprfx_pg != GetRx<19, 16>()) return false;
+      }
+      return zd_matches;
+  }
+  switch (Mask(SVECopyGeneralRegisterToVector_PredicatedMask)) {
+    case CPY_z_p_r:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches;
+  }
+  switch (Mask(SVECopyIntImm_PredicatedMask)) {
+    case CPY_z_p_i:
+      if (movprfx_is_predicated) {
+        if (!vform_matches) return false;
+        if (movprfx_pg != GetRx<19, 16>()) return false;
+      }
+      // Only the merging form can take movprfx.
+      if (ExtractBit(14) == 0) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVECopySIMDFPScalarRegisterToVector_PredicatedMask)) {
+    case CPY_z_p_v:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEFPArithmeticWithImm_PredicatedMask)) {
+    case FADD_z_p_zs:
+    case FMAXNM_z_p_zs:
+    case FMAX_z_p_zs:
+    case FMINNM_z_p_zs:
+    case FMIN_z_p_zs:
+    case FMUL_z_p_zs:
+    case FSUBR_z_p_zs:
+    case FSUB_z_p_zs:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches;
+  }
+  switch (Mask(SVEFPArithmetic_PredicatedMask)) {
+    case FABD_z_p_zz:
+    case FADD_z_p_zz:
+    case FDIVR_z_p_zz:
+    case FDIV_z_p_zz:
+    case FMAXNM_z_p_zz:
+    case FMAX_z_p_zz:
+    case FMINNM_z_p_zz:
+    case FMIN_z_p_zz:
+    case FMULX_z_p_zz:
+    case FMUL_z_p_zz:
+    case FSCALE_z_p_zz:
+    case FSUBR_z_p_zz:
+    case FSUB_z_p_zz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEFPComplexAdditionMask)) {
+    case FCADD_z_p_zz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEFPComplexMulAddIndexMask)) {
+    case FCMLA_z_zzzi_h:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<18, 16>()) return false;
+      return movprfx_is_unpredicated && zd_matches && !zd_matches_zn;
+    case FCMLA_z_zzzi_s:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<19, 16>()) return false;
+      return movprfx_is_unpredicated && zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEFPComplexMulAddMask)) {
+    case FCMLA_z_p_zzz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zm && !zd_matches_zn;
+  }
+  switch (Mask(SVEFPConvertPrecisionMask)) {
+    case FCVT_z_p_z_d2h:
+    case FCVT_z_p_z_d2s:
+    case FCVT_z_p_z_h2d:
+    case FCVT_z_p_z_h2s:
+    case FCVT_z_p_z_s2d:
+    case FCVT_z_p_z_s2h:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEFPConvertToIntMask)) {
+    case FCVTZS_z_p_z_d2w:
+    case FCVTZS_z_p_z_d2x:
+    case FCVTZS_z_p_z_fp162h:
+    case FCVTZS_z_p_z_fp162w:
+    case FCVTZS_z_p_z_fp162x:
+    case FCVTZS_z_p_z_s2w:
+    case FCVTZS_z_p_z_s2x:
+    case FCVTZU_z_p_z_d2w:
+    case FCVTZU_z_p_z_d2x:
+    case FCVTZU_z_p_z_fp162h:
+    case FCVTZU_z_p_z_fp162w:
+    case FCVTZU_z_p_z_fp162x:
+    case FCVTZU_z_p_z_s2w:
+    case FCVTZU_z_p_z_s2x:
+      if (movprfx_is_predicated) {
+        if (!pg_matches_low8) return false;
+        // The movprfx element size must match the instruction's maximum encoded
+        // element size. We have to partially decode the opc and opc2 fields to
+        // find this.
+        unsigned opc = ExtractBits(23, 22);
+        unsigned opc2 = ExtractBits(18, 17);
+        VectorFormat instr_vform =
+            SVEFormatFromLaneSizeInBytesLog2(std::max(opc, opc2));
+        if (movprfx_vform != instr_vform) return false;
+      }
+      return zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEFPMulAddIndexMask)) {
+    case FMLA_z_zzzi_h:
+    case FMLA_z_zzzi_h_i3h:
+    case FMLA_z_zzzi_s:
+    case FMLS_z_zzzi_h:
+    case FMLS_z_zzzi_h_i3h:
+    case FMLS_z_zzzi_s:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<18, 16>()) return false;
+      return movprfx_is_unpredicated && zd_matches && !zd_matches_zn;
+    case FMLA_z_zzzi_d:
+    case FMLS_z_zzzi_d:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<19, 16>()) return false;
+      return movprfx_is_unpredicated && zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEFPMulAddMask)) {
+    case FMAD_z_p_zzz:
+    case FMSB_z_p_zzz:
+    case FNMAD_z_p_zzz:
+    case FNMSB_z_p_zzz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<20, 16>()) return false;
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+    case FMLA_z_p_zzz:
+    case FMLS_z_p_zzz:
+    case FNMLA_z_p_zzz:
+    case FNMLS_z_p_zzz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zm && !zd_matches_zn;
+  }
+  switch (Mask(SVEFPRoundToIntegralValueMask)) {
+    case FRINTA_z_p_z:
+    case FRINTI_z_p_z:
+    case FRINTM_z_p_z:
+    case FRINTN_z_p_z:
+    case FRINTP_z_p_z:
+    case FRINTX_z_p_z:
+    case FRINTZ_z_p_z:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEFPTrigMulAddCoefficientMask)) {
+    case FTMAD_z_zzi:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEFPUnaryOpMask)) {
+    case FRECPX_z_p_z:
+    case FSQRT_z_p_z:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEIncDecByPredicateCountMask)) {
+    case DECP_z_p_z:
+    case INCP_z_p_z:
+    case SQDECP_z_p_z:
+    case SQINCP_z_p_z:
+    case UQDECP_z_p_z:
+    case UQINCP_z_p_z:
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEIncDecVectorByElementCountMask)) {
+    case DECD_z_zs:
+    case DECH_z_zs:
+    case DECW_z_zs:
+    case INCD_z_zs:
+    case INCH_z_zs:
+    case INCW_z_zs:
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEInsertGeneralRegisterMask)) {
+    case INSR_z_r:
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEInsertSIMDFPScalarRegisterMask)) {
+    case INSR_z_v:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEIntAddSubtractImm_UnpredicatedMask)) {
+    case ADD_z_zi:
+    case SQADD_z_zi:
+    case SQSUB_z_zi:
+    case SUBR_z_zi:
+    case SUB_z_zi:
+    case UQADD_z_zi:
+    case UQSUB_z_zi:
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEIntAddSubtractVectors_PredicatedMask)) {
+    case ADD_z_p_zz:
+    case SUBR_z_p_zz:
+    case SUB_z_p_zz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEIntConvertToFPMask)) {
+    case SCVTF_z_p_z_h2fp16:
+    case SCVTF_z_p_z_w2d:
+    case SCVTF_z_p_z_w2fp16:
+    case SCVTF_z_p_z_w2s:
+    case SCVTF_z_p_z_x2d:
+    case SCVTF_z_p_z_x2fp16:
+    case SCVTF_z_p_z_x2s:
+    case UCVTF_z_p_z_h2fp16:
+    case UCVTF_z_p_z_w2d:
+    case UCVTF_z_p_z_w2fp16:
+    case UCVTF_z_p_z_w2s:
+    case UCVTF_z_p_z_x2d:
+    case UCVTF_z_p_z_x2fp16:
+    case UCVTF_z_p_z_x2s:
+      if (movprfx_is_predicated) {
+        if (!pg_matches_low8) return false;
+        // The movprfx element size must match the instruction's maximum encoded
+        // element size. We have to partially decode the opc and opc2 fields to
+        // find this.
+        unsigned opc = ExtractBits(23, 22);
+        unsigned opc2 = ExtractBits(18, 17);
+        VectorFormat instr_vform =
+            SVEFormatFromLaneSizeInBytesLog2(std::max(opc, opc2));
+        if (movprfx_vform != instr_vform) return false;
+      }
+      return zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEIntDivideVectors_PredicatedMask)) {
+    case SDIVR_z_p_zz:
+    case SDIV_z_p_zz:
+    case UDIVR_z_p_zz:
+    case UDIV_z_p_zz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEIntMinMaxDifference_PredicatedMask)) {
+    case SABD_z_p_zz:
+    case SMAX_z_p_zz:
+    case SMIN_z_p_zz:
+    case UABD_z_p_zz:
+    case UMAX_z_p_zz:
+    case UMIN_z_p_zz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEIntMinMaxImm_UnpredicatedMask)) {
+    case SMAX_z_zi:
+    case SMIN_z_zi:
+    case UMAX_z_zi:
+    case UMIN_z_zi:
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEIntMulAddPredicatedMask)) {
+    case MAD_z_p_zzz:
+    case MSB_z_p_zzz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches && !zd_matches_zm;
+    case MLA_z_p_zzz:
+    case MLS_z_p_zzz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zm && !zd_matches_zn;
+  }
+  switch (Mask(SVEIntMulAddUnpredicatedMask)) {
+    case SDOT_z_zzz:
+    case UDOT_z_zzz:
+      return movprfx_is_unpredicated && zd_matches && !zd_matches_zm &&
+             !zd_matches_zn;
+  }
+  switch (Mask(SVEIntMulImm_UnpredicatedMask)) {
+    case MUL_z_zi:
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEIntMulVectors_PredicatedMask)) {
+    case MUL_z_p_zz:
+    case SMULH_z_p_zz:
+    case UMULH_z_p_zz:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return zd_matches;
+  }
+  switch (Mask(SVEIntUnaryArithmeticPredicatedMask)) {
+    case ABS_z_p_z:
+    case CLS_z_p_z:
+    case CLZ_z_p_z:
+    case CNOT_z_p_z:
+    case CNT_z_p_z:
+    case FABS_z_p_z:
+    case FNEG_z_p_z:
+    case NEG_z_p_z:
+    case NOT_z_p_z:
+    case SXTB_z_p_z:
+    case SXTH_z_p_z:
+    case SXTW_z_p_z:
+    case UXTB_z_p_z:
+    case UXTH_z_p_z:
+    case UXTW_z_p_z:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEMulIndexMask)) {
+    case SDOT_z_zzzi_s:
+    case UDOT_z_zzzi_s:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<18, 16>()) return false;
+      return movprfx_is_unpredicated && zd_matches && !zd_matches_zn;
+    case SDOT_z_zzzi_d:
+    case UDOT_z_zzzi_d:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<19, 16>()) return false;
+      return movprfx_is_unpredicated && zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVEPermuteVectorExtractMask)) {
+    case EXT_z_zi_des:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEReverseWithinElementsMask)) {
+    case RBIT_z_p_z:
+    case REVB_z_z:
+    case REVH_z_z:
+    case REVW_z_z:
+      if (movprfx_is_predicated && !(pg_matches_low8 && vform_matches)) {
+        return false;
+      }
+      return zd_matches && !zd_matches_zn;
+  }
+  switch (Mask(SVESaturatingIncDecVectorByElementCountMask)) {
+    case SQDECD_z_zs:
+    case SQDECH_z_zs:
+    case SQDECW_z_zs:
+    case SQINCD_z_zs:
+    case SQINCH_z_zs:
+    case SQINCW_z_zs:
+    case UQDECD_z_zs:
+    case UQDECH_z_zs:
+    case UQDECW_z_zs:
+    case UQINCD_z_zs:
+    case UQINCH_z_zs:
+    case UQINCW_z_zs:
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  switch (Mask(SVEVectorSplice_DestructiveMask)) {
+    case SPLICE_z_p_zz_des:
+      // The movprfx's `zd` must not alias any other inputs.
+      if (movprfx_zd == GetRx<9, 5>()) return false;
+      return movprfx_is_unpredicated && zd_matches;
+  }
+  return false;
+}  // NOLINT(readability/fn_size)
 
 bool Instruction::IsLoad() const {
   if (Mask(LoadStoreAnyFMask) != LoadStoreAnyFixed) {
@@ -103,6 +601,16 @@ bool Instruction::IsStore() const {
 }
 
 
+std::pair<int, int> Instruction::GetSVEPermuteIndexAndLaneSizeLog2() const {
+  uint32_t imm_2 = ExtractBits<0x00C00000>();
+  uint32_t tsz_5 = ExtractBits<0x001F0000>();
+  uint32_t imm_7 = (imm_2 << 5) | tsz_5;
+  int lane_size_in_byte_log_2 = std::min(CountTrailingZeros(tsz_5), 5);
+  int index = ExtractUnsignedBitfield32(6, lane_size_in_byte_log_2 + 1, imm_7);
+  return std::make_pair(index, lane_size_in_byte_log_2);
+}
+
+
 // Logical immediates can't encode zero, so a return value of zero is used to
 // indicate a failure case. Specifically, where the constraints on imm_s are
 // not met.
@@ -111,7 +619,108 @@ uint64_t Instruction::GetImmLogical() const {
   int32_t n = GetBitN();
   int32_t imm_s = GetImmSetBits();
   int32_t imm_r = GetImmRotate();
+  return DecodeImmBitMask(n, imm_s, imm_r, reg_size);
+}
+
+// Logical immediates can't encode zero, so a return value of zero is used to
+// indicate a failure case. Specifically, where the constraints on imm_s are
+// not met.
+uint64_t Instruction::GetSVEImmLogical() const {
+  int n = GetSVEBitN();
+  int imm_s = GetSVEImmSetBits();
+  int imm_r = GetSVEImmRotate();
+  int lane_size_in_bytes_log2 = GetSVEBitwiseImmLaneSizeInBytesLog2();
+  switch (lane_size_in_bytes_log2) {
+    case kDRegSizeInBytesLog2:
+    case kSRegSizeInBytesLog2:
+    case kHRegSizeInBytesLog2:
+    case kBRegSizeInBytesLog2: {
+      int lane_size_in_bits = 1 << (lane_size_in_bytes_log2 + 3);
+      return DecodeImmBitMask(n, imm_s, imm_r, lane_size_in_bits);
+    }
+    default:
+      return 0;
+  }
+}
 
+std::pair<int, int> Instruction::GetSVEImmShiftAndLaneSizeLog2(
+    bool is_predicated) const {
+  Instr tsize =
+      is_predicated ? ExtractBits<0x00C00300>() : ExtractBits<0x00D80000>();
+  Instr imm_3 =
+      is_predicated ? ExtractBits<0x000000E0>() : ExtractBits<0x00070000>();
+  if (tsize == 0) {
+    // The bit field `tsize` means undefined if it is zero, so return a
+    // convenience value kWMinInt to indicate a failure case.
+    return std::make_pair(kWMinInt, kWMinInt);
+  }
+
+  int lane_size_in_bytes_log_2 = 32 - CountLeadingZeros(tsize, 32) - 1;
+  int esize = (1 << lane_size_in_bytes_log_2) * kBitsPerByte;
+  int shift = (2 * esize) - ((tsize << 3) | imm_3);
+  return std::make_pair(shift, lane_size_in_bytes_log_2);
+}
+
+int Instruction::GetSVEMsizeFromDtype(bool is_signed, int dtype_h_lsb) const {
+  Instr dtype_h = ExtractBits(dtype_h_lsb + 1, dtype_h_lsb);
+  if (is_signed) {
+    dtype_h = dtype_h ^ 0x3;
+  }
+  return dtype_h;
+}
+
+int Instruction::GetSVEEsizeFromDtype(bool is_signed, int dtype_l_lsb) const {
+  Instr dtype_l = ExtractBits(dtype_l_lsb + 1, dtype_l_lsb);
+  if (is_signed) {
+    dtype_l = dtype_l ^ 0x3;
+  }
+  return dtype_l;
+}
+
+int Instruction::GetSVEBitwiseImmLaneSizeInBytesLog2() const {
+  int n = GetSVEBitN();
+  int imm_s = GetSVEImmSetBits();
+  unsigned type_bitset =
+      (n << SVEImmSetBits_width) | (~imm_s & GetUintMask(SVEImmSetBits_width));
+
+  // An lane size is constructed from the n and imm_s bits according to
+  // the following table:
+  //
+  // N   imms   size
+  // 0  0xxxxx   32
+  // 0  10xxxx   16
+  // 0  110xxx    8
+  // 0  1110xx    8
+  // 0  11110x    8
+  // 1  xxxxxx   64
+
+  if (type_bitset == 0) {
+    // Bail out early since `HighestSetBitPosition` doesn't accept zero
+    // value input.
+    return -1;
+  }
+
+  switch (HighestSetBitPosition(type_bitset)) {
+    case 6:
+      return kDRegSizeInBytesLog2;
+    case 5:
+      return kSRegSizeInBytesLog2;
+    case 4:
+      return kHRegSizeInBytesLog2;
+    case 3:
+    case 2:
+    case 1:
+      return kBRegSizeInBytesLog2;
+    default:
+      // RESERVED encoding.
+      return -1;
+  }
+}
+
+uint64_t Instruction::DecodeImmBitMask(int32_t n,
+                                       int32_t imm_s,
+                                       int32_t imm_r,
+                                       int32_t size) const {
   // An integer is constructed from the n, imm_s and imm_r bits according to
   // the following table:
   //
@@ -146,7 +755,7 @@ uint64_t Instruction::GetImmLogical() const {
           return 0;
         }
         uint64_t bits = (UINT64_C(1) << ((imm_s & mask) + 1)) - 1;
-        return RepeatBitsAcrossReg(reg_size,
+        return RepeatBitsAcrossReg(size,
                                    RotateRight(bits, imm_r & mask, width),
                                    width);
       }
@@ -397,8 +1006,6 @@ void Instruction::SetImmLLiteral(const Instruction* source) {
 
 
 VectorFormat VectorFormatHalfWidth(VectorFormat vform) {
-  VIXL_ASSERT(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D ||
-              vform == kFormatH || vform == kFormatS || vform == kFormatD);
   switch (vform) {
     case kFormat8H:
       return kFormat8B;
@@ -412,6 +1019,13 @@ VectorFormat VectorFormatHalfWidth(VectorFormat vform) {
       return kFormatH;
     case kFormatD:
       return kFormatS;
+    case kFormatVnH:
+      return kFormatVnB;
+    case kFormatVnS:
+      return kFormatVnH;
+    case kFormatVnD:
+      return kFormatVnS;
+      break;
     default:
       VIXL_UNREACHABLE();
       return kFormatUndefined;
@@ -480,6 +1094,12 @@ VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform) {
       return kFormat2S;
     case kFormat2D:
       return kFormat4S;
+    case kFormatVnH:
+      return kFormatVnB;
+    case kFormatVnS:
+      return kFormatVnH;
+    case kFormatVnD:
+      return kFormatVnS;
     default:
       VIXL_UNREACHABLE();
       return kFormatUndefined;
@@ -518,8 +1138,8 @@ VectorFormat VectorFormatHalfLanes(VectorFormat vform) {
 }
 
 
-VectorFormat ScalarFormatFromLaneSize(int laneSize) {
-  switch (laneSize) {
+VectorFormat ScalarFormatFromLaneSize(int lane_size_in_bits) {
+  switch (lane_size_in_bits) {
     case 8:
       return kFormatB;
     case 16:
@@ -535,6 +1155,69 @@ VectorFormat ScalarFormatFromLaneSize(int laneSize) {
 }
 
 
+bool IsSVEFormat(VectorFormat vform) {
+  switch (vform) {
+    case kFormatVnB:
+    case kFormatVnH:
+    case kFormatVnS:
+    case kFormatVnD:
+    case kFormatVnQ:
+      return true;
+    default:
+      return false;
+  }
+}
+
+
+VectorFormat SVEFormatFromLaneSizeInBytes(int lane_size_in_bytes) {
+  switch (lane_size_in_bytes) {
+    case 1:
+      return kFormatVnB;
+    case 2:
+      return kFormatVnH;
+    case 4:
+      return kFormatVnS;
+    case 8:
+      return kFormatVnD;
+    case 16:
+      return kFormatVnQ;
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
+  }
+}
+
+
+VectorFormat SVEFormatFromLaneSizeInBits(int lane_size_in_bits) {
+  switch (lane_size_in_bits) {
+    case 8:
+    case 16:
+    case 32:
+    case 64:
+    case 128:
+      return SVEFormatFromLaneSizeInBytes(lane_size_in_bits / kBitsPerByte);
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
+  }
+}
+
+
+VectorFormat SVEFormatFromLaneSizeInBytesLog2(int lane_size_in_bytes_log2) {
+  switch (lane_size_in_bytes_log2) {
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+    case 4:
+      return SVEFormatFromLaneSizeInBytes(1 << lane_size_in_bytes_log2);
+    default:
+      VIXL_UNREACHABLE();
+      return kFormatUndefined;
+  }
+}
+
+
 VectorFormat ScalarFormatFromFormat(VectorFormat vform) {
   return ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
 }
@@ -542,6 +1225,7 @@ VectorFormat ScalarFormatFromFormat(VectorFormat vform) {
 
 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) {
   VIXL_ASSERT(vform != kFormatUndefined);
+  VIXL_ASSERT(!IsSVEFormat(vform));
   switch (vform) {
     case kFormatB:
       return kBRegSize;
@@ -551,14 +1235,19 @@ unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) {
     case kFormat2H:
       return kSRegSize;
     case kFormatD:
-      return kDRegSize;
     case kFormat8B:
     case kFormat4H:
     case kFormat2S:
     case kFormat1D:
       return kDRegSize;
-    default:
+    case kFormat16B:
+    case kFormat8H:
+    case kFormat4S:
+    case kFormat2D:
       return kQRegSize;
+    default:
+      VIXL_UNREACHABLE();
+      return 0;
   }
 }
 
@@ -574,20 +1263,26 @@ unsigned LaneSizeInBitsFromFormat(VectorFormat vform) {
     case kFormatB:
     case kFormat8B:
     case kFormat16B:
+    case kFormatVnB:
       return 8;
     case kFormatH:
     case kFormat2H:
     case kFormat4H:
     case kFormat8H:
+    case kFormatVnH:
       return 16;
     case kFormatS:
     case kFormat2S:
     case kFormat4S:
+    case kFormatVnS:
       return 32;
     case kFormatD:
     case kFormat1D:
     case kFormat2D:
+    case kFormatVnD:
       return 64;
+    case kFormatVnQ:
+      return 128;
     default:
       VIXL_UNREACHABLE();
       return 0;
@@ -606,20 +1301,26 @@ int LaneSizeInBytesLog2FromFormat(VectorFormat vform) {
     case kFormatB:
     case kFormat8B:
     case kFormat16B:
+    case kFormatVnB:
       return 0;
     case kFormatH:
     case kFormat2H:
     case kFormat4H:
     case kFormat8H:
+    case kFormatVnH:
       return 1;
     case kFormatS:
     case kFormat2S:
     case kFormat4S:
+    case kFormatVnS:
       return 2;
     case kFormatD:
     case kFormat1D:
     case kFormat2D:
+    case kFormatVnD:
       return 3;
+    case kFormatVnQ:
+      return 4;
     default:
       VIXL_UNREACHABLE();
       return 0;
@@ -697,17 +1398,19 @@ bool IsVectorFormat(VectorFormat vform) {
 
 
 int64_t MaxIntFromFormat(VectorFormat vform) {
-  return INT64_MAX >> (64 - LaneSizeInBitsFromFormat(vform));
+  int lane_size = LaneSizeInBitsFromFormat(vform);
+  return static_cast<int64_t>(GetUintMask(lane_size) >> 1);
 }
 
 
 int64_t MinIntFromFormat(VectorFormat vform) {
-  return INT64_MIN >> (64 - LaneSizeInBitsFromFormat(vform));
+  return -MaxIntFromFormat(vform) - 1;
 }
 
 
 uint64_t MaxUintFromFormat(VectorFormat vform) {
-  return UINT64_MAX >> (64 - LaneSizeInBitsFromFormat(vform));
+  return GetUintMask(LaneSizeInBitsFromFormat(vform));
 }
+
 }  // namespace aarch64
 }  // namespace vixl
diff --git a/src/aarch64/instructions-aarch64.h b/src/aarch64/instructions-aarch64.h
index 6d4f96b4..5f56ae16 100644
--- a/src/aarch64/instructions-aarch64.h
+++ b/src/aarch64/instructions-aarch64.h
@@ -81,6 +81,7 @@ const uint64_t kXRegMask = UINT64_C(0xffffffffffffffff);
 const uint64_t kHRegMask = UINT64_C(0xffff);
 const uint64_t kSRegMask = UINT64_C(0xffffffff);
 const uint64_t kDRegMask = UINT64_C(0xffffffffffffffff);
+const uint64_t kHSignMask = UINT64_C(0x8000);
 const uint64_t kSSignMask = UINT64_C(0x80000000);
 const uint64_t kDSignMask = UINT64_C(0x8000000000000000);
 const uint64_t kWSignMask = UINT64_C(0x80000000);
@@ -116,6 +117,30 @@ VIXL_STATIC_ASSERT(kAddressTagMask == UINT64_C(0xff00000000000000));
 
 const uint64_t kTTBRMask = UINT64_C(1) << 55;
 
+// We can't define a static kZRegSize because the size depends on the
+// implementation. However, it is sometimes useful to know the minimum and
+// maxmimum possible sizes.
+const unsigned kZRegMinSize = 128;
+const unsigned kZRegMinSizeLog2 = 7;
+const unsigned kZRegMinSizeInBytes = kZRegMinSize / 8;
+const unsigned kZRegMinSizeInBytesLog2 = kZRegMinSizeLog2 - 3;
+const unsigned kZRegMaxSize = 2048;
+const unsigned kZRegMaxSizeLog2 = 11;
+const unsigned kZRegMaxSizeInBytes = kZRegMaxSize / 8;
+const unsigned kZRegMaxSizeInBytesLog2 = kZRegMaxSizeLog2 - 3;
+
+// The P register size depends on the Z register size.
+const unsigned kZRegBitsPerPRegBit = kBitsPerByte;
+const unsigned kZRegBitsPerPRegBitLog2 = 3;
+const unsigned kPRegMinSize = kZRegMinSize / kZRegBitsPerPRegBit;
+const unsigned kPRegMinSizeLog2 = kZRegMinSizeLog2 - 3;
+const unsigned kPRegMinSizeInBytes = kPRegMinSize / 8;
+const unsigned kPRegMinSizeInBytesLog2 = kPRegMinSizeLog2 - 3;
+const unsigned kPRegMaxSize = kZRegMaxSize / kZRegBitsPerPRegBit;
+const unsigned kPRegMaxSizeLog2 = kZRegMaxSizeLog2 - 3;
+const unsigned kPRegMaxSizeInBytes = kPRegMaxSize / 8;
+const unsigned kPRegMaxSizeInBytesLog2 = kPRegMaxSizeLog2 - 3;
+
 // Make these moved float constants backwards compatible
 // with explicit vixl::aarch64:: namespace references.
 using vixl::kDoubleMantissaBits;
@@ -151,6 +176,44 @@ enum AddrMode { Offset, PreIndex, PostIndex };
 
 enum Reg31Mode { Reg31IsStackPointer, Reg31IsZeroRegister };
 
+enum VectorFormat {
+  kFormatUndefined = 0xffffffff,
+  kFormat8B = NEON_8B,
+  kFormat16B = NEON_16B,
+  kFormat4H = NEON_4H,
+  kFormat8H = NEON_8H,
+  kFormat2S = NEON_2S,
+  kFormat4S = NEON_4S,
+  kFormat1D = NEON_1D,
+  kFormat2D = NEON_2D,
+
+  // Scalar formats. We add the scalar bit to distinguish between scalar and
+  // vector enumerations; the bit is always set in the encoding of scalar ops
+  // and always clear for vector ops. Although kFormatD and kFormat1D appear
+  // to be the same, their meaning is subtly different. The first is a scalar
+  // operation, the second a vector operation that only affects one lane.
+  kFormatB = NEON_B | NEONScalar,
+  kFormatH = NEON_H | NEONScalar,
+  kFormatS = NEON_S | NEONScalar,
+  kFormatD = NEON_D | NEONScalar,
+
+  // An artificial value, used to distinguish from NEON format category.
+  kFormatSVE = 0x0000fffd,
+  // An artificial value. Q lane size isn't encoded in the usual size field.
+  kFormatSVEQ = 0x000f0000,
+  // Vector element width of SVE register with the unknown lane count since
+  // the vector length is implementation dependent.
+  kFormatVnB = SVE_B | kFormatSVE,
+  kFormatVnH = SVE_H | kFormatSVE,
+  kFormatVnS = SVE_S | kFormatSVE,
+  kFormatVnD = SVE_D | kFormatSVE,
+  kFormatVnQ = kFormatSVEQ | kFormatSVE,
+
+  // An artificial value, used by simulator trace tests and a few oddball
+  // instructions (such as FMLAL).
+  kFormat2H = 0xfffffffe
+};
+
 // Instructions. ---------------------------------------------------------------
 
 class Instruction {
@@ -229,6 +292,29 @@ class Instruction {
   INSTRUCTION_FIELDS_LIST(DEFINE_GETTER)
 #undef DEFINE_GETTER
 
+  template <int msb, int lsb>
+  int32_t GetRx() const {
+    // We don't have any register fields wider than five bits, so the result
+    // will always fit into an int32_t.
+    VIXL_ASSERT((msb - lsb + 1) <= 5);
+    return this->ExtractBits(msb, lsb);
+  }
+
+  VectorFormat GetSVEVectorFormat() const {
+    switch (Mask(SVESizeFieldMask)) {
+      case SVE_B:
+        return kFormatVnB;
+      case SVE_H:
+        return kFormatVnH;
+      case SVE_S:
+        return kFormatVnS;
+      case SVE_D:
+        return kFormatVnD;
+    }
+    VIXL_UNREACHABLE();
+    return kFormatUndefined;
+  }
+
   // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST),
   // formed from ImmPCRelLo and ImmPCRelHi.
   int GetImmPCRel() const {
@@ -254,6 +340,20 @@ class Instruction {
   VIXL_DEPRECATED("GetImmLogical", uint64_t ImmLogical() const) {
     return GetImmLogical();
   }
+  uint64_t GetSVEImmLogical() const;
+  int GetSVEBitwiseImmLaneSizeInBytesLog2() const;
+  uint64_t DecodeImmBitMask(int32_t n,
+                            int32_t imm_s,
+                            int32_t imm_r,
+                            int32_t size) const;
+
+  std::pair<int, int> GetSVEPermuteIndexAndLaneSizeLog2() const;
+
+  std::pair<int, int> GetSVEImmShiftAndLaneSizeLog2(bool is_predicated) const;
+
+  int GetSVEMsizeFromDtype(bool is_signed, int dtype_h_lsb = 23) const;
+
+  int GetSVEEsizeFromDtype(bool is_signed, int dtype_l_lsb = 21) const;
 
   unsigned GetImmNEONabcdefgh() const;
   VIXL_DEPRECATED("GetImmNEONabcdefgh", unsigned ImmNEONabcdefgh() const) {
@@ -280,6 +380,16 @@ class Instruction {
     return GetImmNEONFP64();
   }
 
+  Float16 GetSVEImmFP16() const { return Imm8ToFloat16(ExtractBits(12, 5)); }
+
+  float GetSVEImmFP32() const { return Imm8ToFP32(ExtractBits(12, 5)); }
+
+  double GetSVEImmFP64() const { return Imm8ToFP64(ExtractBits(12, 5)); }
+
+  static Float16 Imm8ToFloat16(uint32_t imm8);
+  static float Imm8ToFP32(uint32_t imm8);
+  static double Imm8ToFP64(uint32_t imm8);
+
   unsigned GetSizeLS() const {
     return CalcLSDataSize(static_cast<LoadStoreOp>(Mask(LoadStoreMask)));
   }
@@ -342,6 +452,9 @@ class Instruction {
     return Mask(LoadStoreAnyFMask) == LoadStoreAnyFixed;
   }
 
+  // True if `this` is valid immediately after the provided movprfx instruction.
+  bool CanTakeSVEMovprfx(Instruction const* movprfx) const;
+
   bool IsLoad() const;
   bool IsStore() const;
 
@@ -557,41 +670,12 @@ class Instruction {
  private:
   int GetImmBranch() const;
 
-  static Float16 Imm8ToFloat16(uint32_t imm8);
-  static float Imm8ToFP32(uint32_t imm8);
-  static double Imm8ToFP64(uint32_t imm8);
-
   void SetPCRelImmTarget(const Instruction* target);
   void SetBranchImmTarget(const Instruction* target);
 };
 
 
-// Functions for handling NEON vector format information.
-enum VectorFormat {
-  kFormatUndefined = 0xffffffff,
-  kFormat8B = NEON_8B,
-  kFormat16B = NEON_16B,
-  kFormat4H = NEON_4H,
-  kFormat8H = NEON_8H,
-  kFormat2S = NEON_2S,
-  kFormat4S = NEON_4S,
-  kFormat1D = NEON_1D,
-  kFormat2D = NEON_2D,
-
-  // Scalar formats. We add the scalar bit to distinguish between scalar and
-  // vector enumerations; the bit is always set in the encoding of scalar ops
-  // and always clear for vector ops. Although kFormatD and kFormat1D appear
-  // to be the same, their meaning is subtly different. The first is a scalar
-  // operation, the second a vector operation that only affects one lane.
-  kFormatB = NEON_B | NEONScalar,
-  kFormatH = NEON_H | NEONScalar,
-  kFormatS = NEON_S | NEONScalar,
-  kFormatD = NEON_D | NEONScalar,
-
-  // An artificial value, used by simulator trace tests and a few oddball
-  // instructions (such as FMLAL).
-  kFormat2H = 0xfffffffe
-};
+// Functions for handling NEON and SVE vector format information.
 
 const int kMaxLanesPerVector = 16;
 
@@ -599,12 +683,16 @@ VectorFormat VectorFormatHalfWidth(VectorFormat vform);
 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
-VectorFormat ScalarFormatFromLaneSize(int lanesize);
+VectorFormat ScalarFormatFromLaneSize(int lane_size_in_bits);
 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
 VectorFormat VectorFormatFillQ(VectorFormat vform);
 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
+VectorFormat SVEFormatFromLaneSizeInBits(int lane_size_in_bits);
+VectorFormat SVEFormatFromLaneSizeInBytes(int lane_size_in_bytes);
+VectorFormat SVEFormatFromLaneSizeInBytesLog2(int lane_size_in_bytes_log_2);
 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
+bool IsSVEFormat(VectorFormat vform);
 // TODO: Make the return types of these functions consistent.
 unsigned LaneSizeInBitsFromFormat(VectorFormat vform);
 int LaneSizeInBytesFromFormat(VectorFormat vform);
diff --git a/src/aarch64/instrument-aarch64.cc b/src/aarch64/instrument-aarch64.cc
deleted file mode 100644
index 7cb6b20e..00000000
--- a/src/aarch64/instrument-aarch64.cc
+++ /dev/null
@@ -1,975 +0,0 @@
-// Copyright 2014, VIXL authors
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-//   * Redistributions of source code must retain the above copyright notice,
-//     this list of conditions and the following disclaimer.
-//   * Redistributions in binary form must reproduce the above copyright notice,
-//     this list of conditions and the following disclaimer in the documentation
-//     and/or other materials provided with the distribution.
-//   * Neither the name of ARM Limited nor the names of its contributors may be
-//     used to endorse or promote products derived from this software without
-//     specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
-// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-#include "instrument-aarch64.h"
-
-namespace vixl {
-namespace aarch64 {
-
-Counter::Counter(const char* name, CounterType type)
-    : count_(0), enabled_(false), type_(type) {
-  VIXL_ASSERT(name != NULL);
-  strncpy(name_, name, kCounterNameMaxLength - 1);
-  // Make sure `name_` is always NULL-terminated, even if the source's length is
-  // higher.
-  name_[kCounterNameMaxLength - 1] = '\0';
-}
-
-
-void Counter::Enable() { enabled_ = true; }
-
-
-void Counter::Disable() { enabled_ = false; }
-
-
-bool Counter::IsEnabled() { return enabled_; }
-
-
-void Counter::Increment() {
-  if (enabled_) {
-    count_++;
-  }
-}
-
-
-uint64_t Counter::GetCount() {
-  uint64_t result = count_;
-  if (type_ == Gauge) {
-    // If the counter is a Gauge, reset the count after reading.
-    count_ = 0;
-  }
-  return result;
-}
-
-
-const char* Counter::GetName() { return name_; }
-
-
-CounterType Counter::GetType() { return type_; }
-
-
-struct CounterDescriptor {
-  const char* name;
-  CounterType type;
-};
-
-
-static const CounterDescriptor kCounterList[] =
-    {{"Instruction", Cumulative},
-
-     {"Move Immediate", Gauge},
-     {"Add/Sub DP", Gauge},
-     {"Logical DP", Gauge},
-     {"Other Int DP", Gauge},
-     {"FP DP", Gauge},
-
-     {"Conditional Select", Gauge},
-     {"Conditional Compare", Gauge},
-
-     {"Unconditional Branch", Gauge},
-     {"Compare and Branch", Gauge},
-     {"Test and Branch", Gauge},
-     {"Conditional Branch", Gauge},
-
-     {"Load Integer", Gauge},
-     {"Load FP", Gauge},
-     {"Load Pair", Gauge},
-     {"Load Literal", Gauge},
-
-     {"Store Integer", Gauge},
-     {"Store FP", Gauge},
-     {"Store Pair", Gauge},
-
-     {"PC Addressing", Gauge},
-     {"Other", Gauge},
-     {"NEON", Gauge},
-     {"Crypto", Gauge}};
-
-
-Instrument::Instrument(const char* datafile, uint64_t sample_period)
-    : output_stream_(stdout), sample_period_(sample_period) {
-  // Set up the output stream. If datafile is non-NULL, use that file. If it
-  // can't be opened, or datafile is NULL, use stdout.
-  if (datafile != NULL) {
-    output_stream_ = fopen(datafile, "w");
-    if (output_stream_ == NULL) {
-      printf("Can't open output file %s. Using stdout.\n", datafile);
-      output_stream_ = stdout;
-    }
-  }
-
-  static const int num_counters =
-      sizeof(kCounterList) / sizeof(CounterDescriptor);
-
-  // Dump an instrumentation description comment at the top of the file.
-  fprintf(output_stream_, "# counters=%d\n", num_counters);
-  fprintf(output_stream_, "# sample_period=%" PRIu64 "\n", sample_period_);
-
-  // Construct Counter objects from counter description array.
-  for (int i = 0; i < num_counters; i++) {
-    Counter* counter = new Counter(kCounterList[i].name, kCounterList[i].type);
-    counters_.push_back(counter);
-  }
-
-  DumpCounterNames();
-}
-
-
-Instrument::~Instrument() {
-  // Dump any remaining instruction data to the output file.
-  DumpCounters();
-
-  // Free all the counter objects.
-  std::list<Counter*>::iterator it;
-  for (it = counters_.begin(); it != counters_.end(); it++) {
-    delete *it;
-  }
-
-  if (output_stream_ != stdout) {
-    fclose(output_stream_);
-  }
-}
-
-
-void Instrument::Update() {
-  // Increment the instruction counter, and dump all counters if a sample period
-  // has elapsed.
-  static Counter* counter = GetCounter("Instruction");
-  VIXL_ASSERT(counter->GetType() == Cumulative);
-  counter->Increment();
-
-  if ((sample_period_ != 0) && counter->IsEnabled() &&
-      (counter->GetCount() % sample_period_) == 0) {
-    DumpCounters();
-  }
-}
-
-
-void Instrument::DumpCounters() {
-  // Iterate through the counter objects, dumping their values to the output
-  // stream.
-  std::list<Counter*>::const_iterator it;
-  for (it = counters_.begin(); it != counters_.end(); it++) {
-    fprintf(output_stream_, "%" PRIu64 ",", (*it)->GetCount());
-  }
-  fprintf(output_stream_, "\n");
-  fflush(output_stream_);
-}
-
-
-void Instrument::DumpCounterNames() {
-  // Iterate through the counter objects, dumping the counter names to the
-  // output stream.
-  std::list<Counter*>::const_iterator it;
-  for (it = counters_.begin(); it != counters_.end(); it++) {
-    fprintf(output_stream_, "%s,", (*it)->GetName());
-  }
-  fprintf(output_stream_, "\n");
-  fflush(output_stream_);
-}
-
-
-void Instrument::HandleInstrumentationEvent(unsigned event) {
-  switch (event) {
-    case InstrumentStateEnable:
-      Enable();
-      break;
-    case InstrumentStateDisable:
-      Disable();
-      break;
-    default:
-      DumpEventMarker(event);
-  }
-}
-
-
-void Instrument::DumpEventMarker(unsigned marker) {
-  // Dumpan event marker to the output stream as a specially formatted comment
-  // line.
-  static Counter* counter = GetCounter("Instruction");
-
-  fprintf(output_stream_,
-          "# %c%c @ %" PRId64 "\n",
-          marker & 0xff,
-          (marker >> 8) & 0xff,
-          counter->GetCount());
-}
-
-
-Counter* Instrument::GetCounter(const char* name) {
-  // Get a Counter object by name from the counter list.
-  std::list<Counter*>::const_iterator it;
-  for (it = counters_.begin(); it != counters_.end(); it++) {
-    if (strcmp((*it)->GetName(), name) == 0) {
-      return *it;
-    }
-  }
-
-  // A Counter by that name does not exist: print an error message to stderr
-  // and the output file, and exit.
-  static const char* error_message =
-      "# Error: Unknown counter \"%s\". Exiting.\n";
-  fprintf(stderr, error_message, name);
-  fprintf(output_stream_, error_message, name);
-  exit(1);
-}
-
-
-void Instrument::Enable() {
-  std::list<Counter*>::iterator it;
-  for (it = counters_.begin(); it != counters_.end(); it++) {
-    (*it)->Enable();
-  }
-}
-
-
-void Instrument::Disable() {
-  std::list<Counter*>::iterator it;
-  for (it = counters_.begin(); it != counters_.end(); it++) {
-    (*it)->Disable();
-  }
-}
-
-
-void Instrument::VisitPCRelAddressing(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("PC Addressing");
-  counter->Increment();
-}
-
-
-void Instrument::VisitAddSubImmediate(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Add/Sub DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitLogicalImmediate(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Logical DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitMoveWideImmediate(const Instruction* instr) {
-  Update();
-  static Counter* counter = GetCounter("Move Immediate");
-
-  if (instr->IsMovn() && (instr->GetRd() == kZeroRegCode)) {
-    unsigned imm = instr->GetImmMoveWide();
-    HandleInstrumentationEvent(imm);
-  } else {
-    counter->Increment();
-  }
-}
-
-
-void Instrument::VisitBitfield(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other Int DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitExtract(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other Int DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitUnconditionalBranch(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Unconditional Branch");
-  counter->Increment();
-}
-
-
-void Instrument::VisitUnconditionalBranchToRegister(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Unconditional Branch");
-  counter->Increment();
-}
-
-
-void Instrument::VisitCompareBranch(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Compare and Branch");
-  counter->Increment();
-}
-
-
-void Instrument::VisitTestBranch(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Test and Branch");
-  counter->Increment();
-}
-
-
-void Instrument::VisitConditionalBranch(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Conditional Branch");
-  counter->Increment();
-}
-
-
-void Instrument::VisitSystem(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-void Instrument::VisitException(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-void Instrument::InstrumentLoadStorePair(const Instruction* instr) {
-  static Counter* load_pair_counter = GetCounter("Load Pair");
-  static Counter* store_pair_counter = GetCounter("Store Pair");
-
-  if (instr->Mask(LoadStorePairLBit) != 0) {
-    load_pair_counter->Increment();
-  } else {
-    store_pair_counter->Increment();
-  }
-}
-
-
-void Instrument::VisitLoadStorePairPostIndex(const Instruction* instr) {
-  Update();
-  InstrumentLoadStorePair(instr);
-}
-
-
-void Instrument::VisitLoadStorePairOffset(const Instruction* instr) {
-  Update();
-  InstrumentLoadStorePair(instr);
-}
-
-
-void Instrument::VisitLoadStorePairPreIndex(const Instruction* instr) {
-  Update();
-  InstrumentLoadStorePair(instr);
-}
-
-
-void Instrument::VisitLoadStorePairNonTemporal(const Instruction* instr) {
-  Update();
-  InstrumentLoadStorePair(instr);
-}
-
-
-void Instrument::VisitLoadStoreExclusive(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-void Instrument::VisitAtomicMemory(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-void Instrument::VisitLoadLiteral(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Load Literal");
-  counter->Increment();
-}
-
-
-void Instrument::VisitLoadStorePAC(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Load Integer");
-  counter->Increment();
-}
-
-
-void Instrument::InstrumentLoadStore(const Instruction* instr) {
-  static Counter* load_int_counter = GetCounter("Load Integer");
-  static Counter* store_int_counter = GetCounter("Store Integer");
-  static Counter* load_fp_counter = GetCounter("Load FP");
-  static Counter* store_fp_counter = GetCounter("Store FP");
-
-  switch (instr->Mask(LoadStoreMask)) {
-    case STRB_w:
-    case STRH_w:
-    case STR_w:
-      VIXL_FALLTHROUGH();
-    case STR_x:
-      store_int_counter->Increment();
-      break;
-    case STR_s:
-      VIXL_FALLTHROUGH();
-    case STR_d:
-      store_fp_counter->Increment();
-      break;
-    case LDRB_w:
-    case LDRH_w:
-    case LDR_w:
-    case LDR_x:
-    case LDRSB_x:
-    case LDRSH_x:
-    case LDRSW_x:
-    case LDRSB_w:
-      VIXL_FALLTHROUGH();
-    case LDRSH_w:
-      load_int_counter->Increment();
-      break;
-    case LDR_s:
-      VIXL_FALLTHROUGH();
-    case LDR_d:
-      load_fp_counter->Increment();
-      break;
-  }
-}
-
-
-void Instrument::VisitLoadStoreUnscaledOffset(const Instruction* instr) {
-  Update();
-  InstrumentLoadStore(instr);
-}
-
-
-void Instrument::VisitLoadStorePostIndex(const Instruction* instr) {
-  USE(instr);
-  Update();
-  InstrumentLoadStore(instr);
-}
-
-
-void Instrument::VisitLoadStorePreIndex(const Instruction* instr) {
-  Update();
-  InstrumentLoadStore(instr);
-}
-
-
-void Instrument::VisitLoadStoreRegisterOffset(const Instruction* instr) {
-  Update();
-  InstrumentLoadStore(instr);
-}
-
-void Instrument::VisitLoadStoreRCpcUnscaledOffset(const Instruction* instr) {
-  Update();
-  switch (instr->Mask(LoadStoreRCpcUnscaledOffsetMask)) {
-    case STLURB:
-    case STLURH:
-    case STLUR_w:
-    case STLUR_x: {
-      static Counter* counter = GetCounter("Store Integer");
-      counter->Increment();
-      break;
-    }
-    case LDAPURB:
-    case LDAPURSB_w:
-    case LDAPURSB_x:
-    case LDAPURH:
-    case LDAPURSH_w:
-    case LDAPURSH_x:
-    case LDAPUR_w:
-    case LDAPURSW:
-    case LDAPUR_x: {
-      static Counter* counter = GetCounter("Load Integer");
-      counter->Increment();
-      break;
-    }
-  }
-}
-
-
-void Instrument::VisitLoadStoreUnsignedOffset(const Instruction* instr) {
-  Update();
-  InstrumentLoadStore(instr);
-}
-
-
-void Instrument::VisitLogicalShifted(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Logical DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitAddSubShifted(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Add/Sub DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitAddSubExtended(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Add/Sub DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitAddSubWithCarry(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Add/Sub DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitRotateRightIntoFlags(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-void Instrument::VisitEvaluateIntoFlags(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-void Instrument::VisitConditionalCompareRegister(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Conditional Compare");
-  counter->Increment();
-}
-
-
-void Instrument::VisitConditionalCompareImmediate(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Conditional Compare");
-  counter->Increment();
-}
-
-
-void Instrument::VisitConditionalSelect(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Conditional Select");
-  counter->Increment();
-}
-
-
-void Instrument::VisitDataProcessing1Source(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other Int DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitDataProcessing2Source(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other Int DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitDataProcessing3Source(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other Int DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPCompare(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("FP DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPConditionalCompare(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Conditional Compare");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPConditionalSelect(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Conditional Select");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPImmediate(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("FP DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPDataProcessing1Source(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("FP DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPDataProcessing2Source(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("FP DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPDataProcessing3Source(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("FP DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPIntegerConvert(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("FP DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitFPFixedPointConvert(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("FP DP");
-  counter->Increment();
-}
-
-
-void Instrument::VisitCrypto2RegSHA(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Crypto");
-  counter->Increment();
-}
-
-
-void Instrument::VisitCrypto3RegSHA(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Crypto");
-  counter->Increment();
-}
-
-
-void Instrument::VisitCryptoAES(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Crypto");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEON2RegMisc(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEON2RegMiscFP16(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEON3Same(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEON3SameFP16(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEON3SameExtra(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEON3Different(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONAcrossLanes(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONByIndexedElement(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONCopy(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONExtract(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONLoadStoreMultiStruct(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONLoadStoreMultiStructPostIndex(
-    const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONLoadStoreSingleStruct(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONLoadStoreSingleStructPostIndex(
-    const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONModifiedImmediate(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalar2RegMisc(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalar2RegMiscFP16(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalar3Diff(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalar3Same(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalar3SameFP16(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalar3SameExtra(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalarByIndexedElement(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalarCopy(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalarPairwise(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONScalarShiftImmediate(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONShiftImmediate(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONTable(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitNEONPerm(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("NEON");
-  counter->Increment();
-}
-
-
-void Instrument::VisitReserved(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-void Instrument::VisitUnallocated(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-void Instrument::VisitUnimplemented(const Instruction* instr) {
-  USE(instr);
-  Update();
-  static Counter* counter = GetCounter("Other");
-  counter->Increment();
-}
-
-
-}  // namespace aarch64
-}  // namespace vixl
diff --git a/src/aarch64/instrument-aarch64.h b/src/aarch64/instrument-aarch64.h
deleted file mode 100644
index 4401b3ea..00000000
--- a/src/aarch64/instrument-aarch64.h
+++ /dev/null
@@ -1,117 +0,0 @@
-// Copyright 2014, VIXL authors
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-//   * Redistributions of source code must retain the above copyright notice,
-//     this list of conditions and the following disclaimer.
-//   * Redistributions in binary form must reproduce the above copyright notice,
-//     this list of conditions and the following disclaimer in the documentation
-//     and/or other materials provided with the distribution.
-//   * Neither the name of ARM Limited nor the names of its contributors may be
-//     used to endorse or promote products derived from this software without
-//     specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
-// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-#ifndef VIXL_AARCH64_INSTRUMENT_AARCH64_H_
-#define VIXL_AARCH64_INSTRUMENT_AARCH64_H_
-
-#include "../globals-vixl.h"
-#include "../utils-vixl.h"
-
-#include "constants-aarch64.h"
-#include "decoder-aarch64.h"
-#include "instrument-aarch64.h"
-
-namespace vixl {
-namespace aarch64 {
-
-const int kCounterNameMaxLength = 256;
-const uint64_t kDefaultInstrumentationSamplingPeriod = 1 << 22;
-
-
-enum InstrumentState { InstrumentStateDisable = 0, InstrumentStateEnable = 1 };
-
-
-enum CounterType {
-  Gauge = 0,      // Gauge counters reset themselves after reading.
-  Cumulative = 1  // Cumulative counters keep their value after reading.
-};
-
-
-class Counter {
- public:
-  explicit Counter(const char* name, CounterType type = Gauge);
-
-  void Increment();
-  void Enable();
-  void Disable();
-  bool IsEnabled();
-  uint64_t GetCount();
-  VIXL_DEPRECATED("GetCount", uint64_t count()) { return GetCount(); }
-
-  const char* GetName();
-  VIXL_DEPRECATED("GetName", const char* name()) { return GetName(); }
-
-  CounterType GetType();
-  VIXL_DEPRECATED("GetType", CounterType type()) { return GetType(); }
-
- private:
-  char name_[kCounterNameMaxLength];
-  uint64_t count_;
-  bool enabled_;
-  CounterType type_;
-};
-
-
-class Instrument : public DecoderVisitor {
- public:
-  explicit Instrument(
-      const char* datafile = NULL,
-      uint64_t sample_period = kDefaultInstrumentationSamplingPeriod);
-  ~Instrument();
-
-  void Enable();
-  void Disable();
-
-// Declare all Visitor functions.
-#define DECLARE(A) void Visit##A(const Instruction* instr) VIXL_OVERRIDE;
-  VISITOR_LIST(DECLARE)
-#undef DECLARE
-
- private:
-  void Update();
-  void DumpCounters();
-  void DumpCounterNames();
-  void DumpEventMarker(unsigned marker);
-  void HandleInstrumentationEvent(unsigned event);
-  Counter* GetCounter(const char* name);
-
-  void InstrumentLoadStore(const Instruction* instr);
-  void InstrumentLoadStorePair(const Instruction* instr);
-
-  std::list<Counter*> counters_;
-
-  FILE* output_stream_;
-
-  // Counter information is dumped every sample_period_ instructions decoded.
-  // For a sample_period_ = 0 a final counter value is only produced when the
-  // Instrumentation class is destroyed.
-  uint64_t sample_period_;
-};
-
-}  // namespace aarch64
-}  // namespace vixl
-
-#endif  // VIXL_AARCH64_INSTRUMENT_AARCH64_H_
diff --git a/src/aarch64/logic-aarch64.cc b/src/aarch64/logic-aarch64.cc
index e7ede2f9..cb82f715 100644
--- a/src/aarch64/logic-aarch64.cc
+++ b/src/aarch64/logic-aarch64.cc
@@ -170,7 +170,7 @@ SimFloat16 Simulator::UFixedToFloat16(uint64_t src,
 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.ReadUintFromMem(vform, i, addr);
+    LoadLane(dst, vform, i, addr);
     addr += LaneSizeInBytesFromFormat(vform);
   }
 }
@@ -180,18 +180,32 @@ void Simulator::ld1(VectorFormat vform,
                     LogicVRegister dst,
                     int index,
                     uint64_t addr) {
-  dst.ReadUintFromMem(vform, index, addr);
+  LoadLane(dst, vform, index, addr);
 }
 
 
-void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
+void Simulator::ld1r(VectorFormat vform,
+                     VectorFormat unpack_vform,
+                     LogicVRegister dst,
+                     uint64_t addr,
+                     bool is_signed) {
+  unsigned unpack_size = LaneSizeInBytesFromFormat(unpack_vform);
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.ReadUintFromMem(vform, i, addr);
+    if (is_signed) {
+      LoadIntToLane(dst, vform, unpack_size, i, addr);
+    } else {
+      LoadUintToLane(dst, vform, unpack_size, i, addr);
+    }
   }
 }
 
 
+void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) {
+  ld1r(vform, vform, dst, addr);
+}
+
+
 void Simulator::ld2(VectorFormat vform,
                     LogicVRegister dst1,
                     LogicVRegister dst2,
@@ -201,8 +215,8 @@ void Simulator::ld2(VectorFormat vform,
   int esize = LaneSizeInBytesFromFormat(vform);
   uint64_t addr2 = addr1 + esize;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst1.ReadUintFromMem(vform, i, addr1);
-    dst2.ReadUintFromMem(vform, i, addr2);
+    LoadLane(dst1, vform, i, addr1);
+    LoadLane(dst2, vform, i, addr2);
     addr1 += 2 * esize;
     addr2 += 2 * esize;
   }
@@ -217,8 +231,8 @@ void Simulator::ld2(VectorFormat vform,
   dst1.ClearForWrite(vform);
   dst2.ClearForWrite(vform);
   uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform);
-  dst1.ReadUintFromMem(vform, index, addr1);
-  dst2.ReadUintFromMem(vform, index, addr2);
+  LoadLane(dst1, vform, index, addr1);
+  LoadLane(dst2, vform, index, addr2);
 }
 
 
@@ -230,8 +244,8 @@ void Simulator::ld2r(VectorFormat vform,
   dst2.ClearForWrite(vform);
   uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst1.ReadUintFromMem(vform, i, addr);
-    dst2.ReadUintFromMem(vform, i, addr2);
+    LoadLane(dst1, vform, i, addr);
+    LoadLane(dst2, vform, i, addr2);
   }
 }
 
@@ -248,9 +262,9 @@ void Simulator::ld3(VectorFormat vform,
   uint64_t addr2 = addr1 + esize;
   uint64_t addr3 = addr2 + esize;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst1.ReadUintFromMem(vform, i, addr1);
-    dst2.ReadUintFromMem(vform, i, addr2);
-    dst3.ReadUintFromMem(vform, i, addr3);
+    LoadLane(dst1, vform, i, addr1);
+    LoadLane(dst2, vform, i, addr2);
+    LoadLane(dst3, vform, i, addr3);
     addr1 += 3 * esize;
     addr2 += 3 * esize;
     addr3 += 3 * esize;
@@ -269,9 +283,9 @@ void Simulator::ld3(VectorFormat vform,
   dst3.ClearForWrite(vform);
   uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform);
   uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform);
-  dst1.ReadUintFromMem(vform, index, addr1);
-  dst2.ReadUintFromMem(vform, index, addr2);
-  dst3.ReadUintFromMem(vform, index, addr3);
+  LoadLane(dst1, vform, index, addr1);
+  LoadLane(dst2, vform, index, addr2);
+  LoadLane(dst3, vform, index, addr3);
 }
 
 
@@ -286,9 +300,9 @@ void Simulator::ld3r(VectorFormat vform,
   uint64_t addr2 = addr + LaneSizeInBytesFromFormat(vform);
   uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst1.ReadUintFromMem(vform, i, addr);
-    dst2.ReadUintFromMem(vform, i, addr2);
-    dst3.ReadUintFromMem(vform, i, addr3);
+    LoadLane(dst1, vform, i, addr);
+    LoadLane(dst2, vform, i, addr2);
+    LoadLane(dst3, vform, i, addr3);
   }
 }
 
@@ -308,10 +322,10 @@ void Simulator::ld4(VectorFormat vform,
   uint64_t addr3 = addr2 + esize;
   uint64_t addr4 = addr3 + esize;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst1.ReadUintFromMem(vform, i, addr1);
-    dst2.ReadUintFromMem(vform, i, addr2);
-    dst3.ReadUintFromMem(vform, i, addr3);
-    dst4.ReadUintFromMem(vform, i, addr4);
+    LoadLane(dst1, vform, i, addr1);
+    LoadLane(dst2, vform, i, addr2);
+    LoadLane(dst3, vform, i, addr3);
+    LoadLane(dst4, vform, i, addr4);
     addr1 += 4 * esize;
     addr2 += 4 * esize;
     addr3 += 4 * esize;
@@ -334,10 +348,10 @@ void Simulator::ld4(VectorFormat vform,
   uint64_t addr2 = addr1 + LaneSizeInBytesFromFormat(vform);
   uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform);
   uint64_t addr4 = addr3 + LaneSizeInBytesFromFormat(vform);
-  dst1.ReadUintFromMem(vform, index, addr1);
-  dst2.ReadUintFromMem(vform, index, addr2);
-  dst3.ReadUintFromMem(vform, index, addr3);
-  dst4.ReadUintFromMem(vform, index, addr4);
+  LoadLane(dst1, vform, index, addr1);
+  LoadLane(dst2, vform, index, addr2);
+  LoadLane(dst3, vform, index, addr3);
+  LoadLane(dst4, vform, index, addr4);
 }
 
 
@@ -355,17 +369,17 @@ void Simulator::ld4r(VectorFormat vform,
   uint64_t addr3 = addr2 + LaneSizeInBytesFromFormat(vform);
   uint64_t addr4 = addr3 + LaneSizeInBytesFromFormat(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst1.ReadUintFromMem(vform, i, addr);
-    dst2.ReadUintFromMem(vform, i, addr2);
-    dst3.ReadUintFromMem(vform, i, addr3);
-    dst4.ReadUintFromMem(vform, i, addr4);
+    LoadLane(dst1, vform, i, addr);
+    LoadLane(dst2, vform, i, addr2);
+    LoadLane(dst3, vform, i, addr3);
+    LoadLane(dst4, vform, i, addr4);
   }
 }
 
 
 void Simulator::st1(VectorFormat vform, LogicVRegister src, uint64_t addr) {
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    src.WriteUintToMem(vform, i, addr);
+    StoreLane(src, vform, i, addr);
     addr += LaneSizeInBytesFromFormat(vform);
   }
 }
@@ -375,19 +389,19 @@ void Simulator::st1(VectorFormat vform,
                     LogicVRegister src,
                     int index,
                     uint64_t addr) {
-  src.WriteUintToMem(vform, index, addr);
+  StoreLane(src, vform, index, addr);
 }
 
 
 void Simulator::st2(VectorFormat vform,
-                    LogicVRegister dst,
-                    LogicVRegister dst2,
+                    LogicVRegister src,
+                    LogicVRegister src2,
                     uint64_t addr) {
   int esize = LaneSizeInBytesFromFormat(vform);
   uint64_t addr2 = addr + esize;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.WriteUintToMem(vform, i, addr);
-    dst2.WriteUintToMem(vform, i, addr2);
+    StoreLane(src, vform, i, addr);
+    StoreLane(src2, vform, i, addr2);
     addr += 2 * esize;
     addr2 += 2 * esize;
   }
@@ -395,28 +409,28 @@ void Simulator::st2(VectorFormat vform,
 
 
 void Simulator::st2(VectorFormat vform,
-                    LogicVRegister dst,
-                    LogicVRegister dst2,
+                    LogicVRegister src,
+                    LogicVRegister src2,
                     int index,
                     uint64_t addr) {
   int esize = LaneSizeInBytesFromFormat(vform);
-  dst.WriteUintToMem(vform, index, addr);
-  dst2.WriteUintToMem(vform, index, addr + 1 * esize);
+  StoreLane(src, vform, index, addr);
+  StoreLane(src2, vform, index, addr + 1 * esize);
 }
 
 
 void Simulator::st3(VectorFormat vform,
-                    LogicVRegister dst,
-                    LogicVRegister dst2,
-                    LogicVRegister dst3,
+                    LogicVRegister src,
+                    LogicVRegister src2,
+                    LogicVRegister src3,
                     uint64_t addr) {
   int esize = LaneSizeInBytesFromFormat(vform);
   uint64_t addr2 = addr + esize;
   uint64_t addr3 = addr2 + esize;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.WriteUintToMem(vform, i, addr);
-    dst2.WriteUintToMem(vform, i, addr2);
-    dst3.WriteUintToMem(vform, i, addr3);
+    StoreLane(src, vform, i, addr);
+    StoreLane(src2, vform, i, addr2);
+    StoreLane(src3, vform, i, addr3);
     addr += 3 * esize;
     addr2 += 3 * esize;
     addr3 += 3 * esize;
@@ -425,33 +439,33 @@ void Simulator::st3(VectorFormat vform,
 
 
 void Simulator::st3(VectorFormat vform,
-                    LogicVRegister dst,
-                    LogicVRegister dst2,
-                    LogicVRegister dst3,
+                    LogicVRegister src,
+                    LogicVRegister src2,
+                    LogicVRegister src3,
                     int index,
                     uint64_t addr) {
   int esize = LaneSizeInBytesFromFormat(vform);
-  dst.WriteUintToMem(vform, index, addr);
-  dst2.WriteUintToMem(vform, index, addr + 1 * esize);
-  dst3.WriteUintToMem(vform, index, addr + 2 * esize);
+  StoreLane(src, vform, index, addr);
+  StoreLane(src2, vform, index, addr + 1 * esize);
+  StoreLane(src3, vform, index, addr + 2 * esize);
 }
 
 
 void Simulator::st4(VectorFormat vform,
-                    LogicVRegister dst,
-                    LogicVRegister dst2,
-                    LogicVRegister dst3,
-                    LogicVRegister dst4,
+                    LogicVRegister src,
+                    LogicVRegister src2,
+                    LogicVRegister src3,
+                    LogicVRegister src4,
                     uint64_t addr) {
   int esize = LaneSizeInBytesFromFormat(vform);
   uint64_t addr2 = addr + esize;
   uint64_t addr3 = addr2 + esize;
   uint64_t addr4 = addr3 + esize;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    dst.WriteUintToMem(vform, i, addr);
-    dst2.WriteUintToMem(vform, i, addr2);
-    dst3.WriteUintToMem(vform, i, addr3);
-    dst4.WriteUintToMem(vform, i, addr4);
+    StoreLane(src, vform, i, addr);
+    StoreLane(src2, vform, i, addr2);
+    StoreLane(src3, vform, i, addr3);
+    StoreLane(src4, vform, i, addr4);
     addr += 4 * esize;
     addr2 += 4 * esize;
     addr3 += 4 * esize;
@@ -461,17 +475,17 @@ void Simulator::st4(VectorFormat vform,
 
 
 void Simulator::st4(VectorFormat vform,
-                    LogicVRegister dst,
-                    LogicVRegister dst2,
-                    LogicVRegister dst3,
-                    LogicVRegister dst4,
+                    LogicVRegister src,
+                    LogicVRegister src2,
+                    LogicVRegister src3,
+                    LogicVRegister src4,
                     int index,
                     uint64_t addr) {
   int esize = LaneSizeInBytesFromFormat(vform);
-  dst.WriteUintToMem(vform, index, addr);
-  dst2.WriteUintToMem(vform, index, addr + 1 * esize);
-  dst3.WriteUintToMem(vform, index, addr + 2 * esize);
-  dst4.WriteUintToMem(vform, index, addr + 3 * esize);
+  StoreLane(src, vform, index, addr);
+  StoreLane(src2, vform, index, addr + 1 * esize);
+  StoreLane(src3, vform, index, addr + 2 * esize);
+  StoreLane(src4, vform, index, addr + 3 * esize);
 }
 
 
@@ -550,6 +564,7 @@ LogicVRegister Simulator::add(VectorFormat vform,
                               const LogicVRegister& src2) {
   int lane_size = LaneSizeInBitsFromFormat(vform);
   dst.ClearForWrite(vform);
+
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     // Test for unsigned saturation.
     uint64_t ua = src1.UintLeftJustified(vform, i);
@@ -568,12 +583,39 @@ LogicVRegister Simulator::add(VectorFormat vform,
     if ((pos_a == pos_b) && (pos_a != pos_r)) {
       dst.SetSignedSat(i, pos_a);
     }
-
     dst.SetInt(vform, i, ur >> (64 - lane_size));
   }
   return dst;
 }
 
+LogicVRegister Simulator::add_uint(VectorFormat vform,
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   uint64_t value) {
+  int lane_size = LaneSizeInBitsFromFormat(vform);
+  VIXL_ASSERT(IsUintN(lane_size, value));
+  dst.ClearForWrite(vform);
+  // Left-justify `value`.
+  uint64_t ub = value << (64 - lane_size);
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    // Test for unsigned saturation.
+    uint64_t ua = src1.UintLeftJustified(vform, i);
+    uint64_t ur = ua + ub;
+    if (ur < ua) {
+      dst.SetUnsignedSat(i, true);
+    }
+
+    // Test for signed saturation.
+    // `value` is always positive, so we have an overflow if the (signed) result
+    // is smaller than the first operand.
+    if (RawbitsToInt64(ur) < RawbitsToInt64(ua)) {
+      dst.SetSignedSat(i, true);
+    }
+
+    dst.SetInt(vform, i, ur >> (64 - lane_size));
+  }
+  return dst;
+}
 
 LogicVRegister Simulator::addp(VectorFormat vform,
                                LogicVRegister dst,
@@ -586,25 +628,68 @@ LogicVRegister Simulator::addp(VectorFormat vform,
   return dst;
 }
 
+LogicVRegister Simulator::sdiv(VectorFormat vform,
+                               LogicVRegister dst,
+                               const LogicVRegister& src1,
+                               const LogicVRegister& src2) {
+  VIXL_ASSERT((vform == kFormatVnS) || (vform == kFormatVnD));
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    int64_t val1 = src1.Int(vform, i);
+    int64_t val2 = src2.Int(vform, i);
+    int64_t min_int = (vform == kFormatVnD) ? kXMinInt : kWMinInt;
+    int64_t quotient = 0;
+    if ((val1 == min_int) && (val2 == -1)) {
+      quotient = min_int;
+    } else if (val2 != 0) {
+      quotient = val1 / val2;
+    }
+    dst.SetInt(vform, i, quotient);
+  }
+
+  return dst;
+}
+
+LogicVRegister Simulator::udiv(VectorFormat vform,
+                               LogicVRegister dst,
+                               const LogicVRegister& src1,
+                               const LogicVRegister& src2) {
+  VIXL_ASSERT((vform == kFormatVnS) || (vform == kFormatVnD));
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    uint64_t val1 = src1.Uint(vform, i);
+    uint64_t val2 = src2.Uint(vform, i);
+    uint64_t quotient = 0;
+    if (val2 != 0) {
+      quotient = val1 / val2;
+    }
+    dst.SetUint(vform, i, quotient);
+  }
+
+  return dst;
+}
+
 
 LogicVRegister Simulator::mla(VectorFormat vform,
                               LogicVRegister dst,
+                              const LogicVRegister& srca,
                               const LogicVRegister& src1,
                               const LogicVRegister& src2) {
   SimVRegister temp;
   mul(vform, temp, src1, src2);
-  add(vform, dst, dst, temp);
+  add(vform, dst, srca, temp);
   return dst;
 }
 
 
 LogicVRegister Simulator::mls(VectorFormat vform,
                               LogicVRegister dst,
+                              const LogicVRegister& srca,
                               const LogicVRegister& src1,
                               const LogicVRegister& src2) {
   SimVRegister temp;
   mul(vform, temp, src1, src2);
-  sub(vform, dst, dst, temp);
+  sub(vform, dst, srca, temp);
   return dst;
 }
 
@@ -614,6 +699,7 @@ LogicVRegister Simulator::mul(VectorFormat vform,
                               const LogicVRegister& src1,
                               const LogicVRegister& src2) {
   dst.ClearForWrite(vform);
+
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     dst.SetUint(vform, i, src1.Uint(vform, i) * src2.Uint(vform, i));
   }
@@ -632,6 +718,70 @@ LogicVRegister Simulator::mul(VectorFormat vform,
 }
 
 
+LogicVRegister Simulator::smulh(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& src1,
+                                const LogicVRegister& src2) {
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    int64_t dst_val;
+    int64_t val1 = src1.Int(vform, i);
+    int64_t val2 = src2.Int(vform, i);
+    switch (LaneSizeInBitsFromFormat(vform)) {
+      case 8:
+        dst_val = internal::MultiplyHigh<8>(val1, val2);
+        break;
+      case 16:
+        dst_val = internal::MultiplyHigh<16>(val1, val2);
+        break;
+      case 32:
+        dst_val = internal::MultiplyHigh<32>(val1, val2);
+        break;
+      case 64:
+        dst_val = internal::MultiplyHigh<64>(val1, val2);
+        break;
+      default:
+        dst_val = 0xbadbeef;
+        VIXL_UNREACHABLE();
+        break;
+    }
+    dst.SetInt(vform, i, dst_val);
+  }
+  return dst;
+}
+
+
+LogicVRegister Simulator::umulh(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& src1,
+                                const LogicVRegister& src2) {
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    uint64_t dst_val;
+    uint64_t val1 = src1.Uint(vform, i);
+    uint64_t val2 = src2.Uint(vform, i);
+    switch (LaneSizeInBitsFromFormat(vform)) {
+      case 8:
+        dst_val = internal::MultiplyHigh<8>(val1, val2);
+        break;
+      case 16:
+        dst_val = internal::MultiplyHigh<16>(val1, val2);
+        break;
+      case 32:
+        dst_val = internal::MultiplyHigh<32>(val1, val2);
+        break;
+      case 64:
+        dst_val = internal::MultiplyHigh<64>(val1, val2);
+        break;
+      default:
+        dst_val = 0xbadbeef;
+        VIXL_UNREACHABLE();
+        break;
+    }
+    dst.SetUint(vform, i, dst_val);
+  }
+  return dst;
+}
+
+
 LogicVRegister Simulator::mla(VectorFormat vform,
                               LogicVRegister dst,
                               const LogicVRegister& src1,
@@ -639,7 +789,7 @@ LogicVRegister Simulator::mla(VectorFormat vform,
                               int index) {
   SimVRegister temp;
   VectorFormat indexform = VectorFormatFillQ(vform);
-  return mla(vform, dst, src1, dup_element(indexform, temp, src2, index));
+  return mla(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
 
@@ -650,7 +800,7 @@ LogicVRegister Simulator::mls(VectorFormat vform,
                               int index) {
   SimVRegister temp;
   VectorFormat indexform = VectorFormatFillQ(vform);
-  return mls(vform, dst, src1, dup_element(indexform, temp, src2, index));
+  return mls(vform, dst, dst, src1, dup_element(indexform, temp, src2, index));
 }
 
 
@@ -898,8 +1048,14 @@ LogicVRegister Simulator::sdot(VectorFormat vform,
                                const LogicVRegister& src2,
                                int index) {
   SimVRegister temp;
-  VectorFormat indexform = VectorFormatFillQ(vform);
-  return sdot(vform, dst, src1, dup_element(indexform, temp, src2, index));
+  // NEON indexed `dot` allows the index value exceed the register size.
+  // Promote the format to Q-sized vector format before the duplication.
+  dup_elements_to_segments(IsSVEFormat(vform) ? vform
+                                              : VectorFormatFillQ(vform),
+                           temp,
+                           src2,
+                           index);
+  return sdot(vform, dst, src1, temp);
 }
 
 
@@ -920,8 +1076,14 @@ LogicVRegister Simulator::udot(VectorFormat vform,
                                const LogicVRegister& src2,
                                int index) {
   SimVRegister temp;
-  VectorFormat indexform = VectorFormatFillQ(vform);
-  return udot(vform, dst, src1, dup_element(indexform, temp, src2, index));
+  // NEON indexed `dot` allows the index value exceed the register size.
+  // Promote the format to Q-sized vector format before the duplication.
+  dup_elements_to_segments(IsSVEFormat(vform) ? vform
+                                              : VectorFormatFillQ(vform),
+                           temp,
+                           src2,
+                           index);
+  return udot(vform, dst, src1, temp);
 }
 
 
@@ -1025,6 +1187,34 @@ LogicVRegister Simulator::sub(VectorFormat vform,
   return dst;
 }
 
+LogicVRegister Simulator::sub_uint(VectorFormat vform,
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src1,
+                                   uint64_t value) {
+  int lane_size = LaneSizeInBitsFromFormat(vform);
+  VIXL_ASSERT(IsUintN(lane_size, value));
+  dst.ClearForWrite(vform);
+  // Left-justify `value`.
+  uint64_t ub = value << (64 - lane_size);
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    // Test for unsigned saturation.
+    uint64_t ua = src1.UintLeftJustified(vform, i);
+    uint64_t ur = ua - ub;
+    if (ub > ua) {
+      dst.SetUnsignedSat(i, false);
+    }
+
+    // Test for signed saturation.
+    // `value` is always positive, so we have an overflow if the (signed) result
+    // is greater than the first operand.
+    if (RawbitsToInt64(ur) > RawbitsToInt64(ua)) {
+      dst.SetSignedSat(i, false);
+    }
+
+    dst.SetInt(vform, i, ur >> (64 - lane_size));
+  }
+  return dst;
+}
 
 LogicVRegister Simulator::and_(VectorFormat vform,
                                LogicVRegister dst,
@@ -1091,12 +1281,12 @@ LogicVRegister Simulator::bic(VectorFormat vform,
                               const LogicVRegister& src,
                               uint64_t imm) {
   uint64_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  int lane_count = LaneCountFromFormat(vform);
+  for (int i = 0; i < lane_count; ++i) {
     result[i] = src.Uint(vform, i) & ~imm;
   }
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -1298,10 +1488,13 @@ LogicVRegister Simulator::uaddlv(VectorFormat vform,
 
 LogicVRegister Simulator::sminmaxv(VectorFormat vform,
                                    LogicVRegister dst,
+                                   const LogicPRegister& pg,
                                    const LogicVRegister& src,
                                    bool max) {
   int64_t dst_val = max ? INT64_MIN : INT64_MAX;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
     int64_t src_val = src.Int(vform, i);
     if (max) {
       dst_val = (src_val > dst_val) ? src_val : dst_val;
@@ -1318,15 +1511,35 @@ LogicVRegister Simulator::sminmaxv(VectorFormat vform,
 LogicVRegister Simulator::smaxv(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src) {
-  sminmaxv(vform, dst, src, true);
+  sminmaxv(vform, dst, GetPTrue(), src, true);
+  return dst;
+}
+
+
+LogicVRegister Simulator::sminv(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& src) {
+  sminmaxv(vform, dst, GetPTrue(), src, false);
+  return dst;
+}
+
+
+LogicVRegister Simulator::smaxv(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  sminmaxv(vform, dst, pg, src, true);
   return dst;
 }
 
 
 LogicVRegister Simulator::sminv(VectorFormat vform,
                                 LogicVRegister dst,
+                                const LogicPRegister& pg,
                                 const LogicVRegister& src) {
-  sminmaxv(vform, dst, src, false);
+  VIXL_ASSERT(IsSVEFormat(vform));
+  sminmaxv(vform, dst, pg, src, false);
   return dst;
 }
 
@@ -1414,10 +1627,13 @@ LogicVRegister Simulator::uminp(VectorFormat vform,
 
 LogicVRegister Simulator::uminmaxv(VectorFormat vform,
                                    LogicVRegister dst,
+                                   const LogicPRegister& pg,
                                    const LogicVRegister& src,
                                    bool max) {
   uint64_t dst_val = max ? 0 : UINT64_MAX;
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
     uint64_t src_val = src.Uint(vform, i);
     if (max) {
       dst_val = (src_val > dst_val) ? src_val : dst_val;
@@ -1434,7 +1650,7 @@ LogicVRegister Simulator::uminmaxv(VectorFormat vform,
 LogicVRegister Simulator::umaxv(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src) {
-  uminmaxv(vform, dst, src, true);
+  uminmaxv(vform, dst, GetPTrue(), src, true);
   return dst;
 }
 
@@ -1442,7 +1658,27 @@ LogicVRegister Simulator::umaxv(VectorFormat vform,
 LogicVRegister Simulator::uminv(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src) {
-  uminmaxv(vform, dst, src, false);
+  uminmaxv(vform, dst, GetPTrue(), src, false);
+  return dst;
+}
+
+
+LogicVRegister Simulator::umaxv(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  uminmaxv(vform, dst, pg, src, true);
+  return dst;
+}
+
+
+LogicVRegister Simulator::uminv(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  uminmaxv(vform, dst, pg, src, false);
   return dst;
 }
 
@@ -1521,14 +1757,104 @@ LogicVRegister Simulator::ushll2(VectorFormat vform,
   return ushl(vform, dst, extendedreg, shiftreg);
 }
 
+std::pair<bool, uint64_t> Simulator::clast(VectorFormat vform,
+                                           const LogicPRegister& pg,
+                                           const LogicVRegister& src,
+                                           int offset_from_last_active) {
+  // Untested for any other values.
+  VIXL_ASSERT((offset_from_last_active == 0) || (offset_from_last_active == 1));
+
+  int last_active = GetLastActive(vform, pg);
+  int lane_count = LaneCountFromFormat(vform);
+  int index =
+      ((last_active + offset_from_last_active) + lane_count) % lane_count;
+  return std::make_pair(last_active >= 0, src.Uint(vform, index));
+}
+
+LogicVRegister Simulator::compact(VectorFormat vform,
+                                  LogicVRegister dst,
+                                  const LogicPRegister& pg,
+                                  const LogicVRegister& src) {
+  int j = 0;
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (pg.IsActive(vform, i)) {
+      dst.SetUint(vform, j++, src.Uint(vform, i));
+    }
+  }
+  for (; j < LaneCountFromFormat(vform); j++) {
+    dst.SetUint(vform, j, 0);
+  }
+  return dst;
+}
+
+LogicVRegister Simulator::splice(VectorFormat vform,
+                                 LogicVRegister dst,
+                                 const LogicPRegister& pg,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2) {
+  int lane_count = LaneCountFromFormat(vform);
+  int first_active = GetFirstActive(vform, pg);
+  int last_active = GetLastActive(vform, pg);
+  int dst_idx = 0;
+  uint64_t result[kZRegMaxSizeInBytes];
+
+  if (first_active >= 0) {
+    VIXL_ASSERT(last_active >= first_active);
+    VIXL_ASSERT(last_active < lane_count);
+    for (int i = first_active; i <= last_active; i++) {
+      result[dst_idx++] = src1.Uint(vform, i);
+    }
+  }
+
+  VIXL_ASSERT(dst_idx <= lane_count);
+  for (int i = dst_idx; i < lane_count; i++) {
+    result[i] = src2.Uint(vform, i - dst_idx);
+  }
+
+  for (int i = 0; i < lane_count; i++) {
+    dst.SetUint(vform, i, result[i]);
+  }
+  return dst;
+}
+
+LogicVRegister Simulator::sel(VectorFormat vform,
+                              LogicVRegister dst,
+                              const SimPRegister& pg,
+                              const LogicVRegister& src1,
+                              const LogicVRegister& src2) {
+  int p_reg_bits_per_lane =
+      LaneSizeInBitsFromFormat(vform) / kZRegBitsPerPRegBit;
+  for (int lane = 0; lane < LaneCountFromFormat(vform); lane++) {
+    uint64_t lane_value = pg.GetBit(lane * p_reg_bits_per_lane)
+                              ? src1.Uint(vform, lane)
+                              : src2.Uint(vform, lane);
+    dst.SetUint(vform, lane, lane_value);
+  }
+  return dst;
+}
+
+
+LogicPRegister Simulator::sel(LogicPRegister dst,
+                              const LogicPRegister& pg,
+                              const LogicPRegister& src1,
+                              const LogicPRegister& src2) {
+  for (int i = 0; i < dst.GetChunkCount(); i++) {
+    LogicPRegister::ChunkType mask = pg.GetChunk(i);
+    LogicPRegister::ChunkType result =
+        (mask & src1.GetChunk(i)) | (~mask & src2.GetChunk(i));
+    dst.SetChunk(i, result);
+  }
+  return dst;
+}
+
 
 LogicVRegister Simulator::sli(VectorFormat vform,
                               LogicVRegister dst,
                               const LogicVRegister& src,
                               int shift) {
   dst.ClearForWrite(vform);
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount; i++) {
+  int lane_count = LaneCountFromFormat(vform);
+  for (int i = 0; i < lane_count; i++) {
     uint64_t src_lane = src.Uint(vform, i);
     uint64_t dst_lane = dst.Uint(vform, i);
     uint64_t shifted = src_lane << shift;
@@ -1577,10 +1903,10 @@ LogicVRegister Simulator::sri(VectorFormat vform,
                               const LogicVRegister& src,
                               int shift) {
   dst.ClearForWrite(vform);
-  int laneCount = LaneCountFromFormat(vform);
+  int lane_count = LaneCountFromFormat(vform);
   VIXL_ASSERT((shift > 0) &&
               (shift <= static_cast<int>(LaneSizeInBitsFromFormat(vform))));
-  for (int i = 0; i < laneCount; i++) {
+  for (int i = 0; i < lane_count; i++) {
     uint64_t src_lane = src.Uint(vform, i);
     uint64_t dst_lane = dst.Uint(vform, i);
     uint64_t shifted;
@@ -1663,15 +1989,18 @@ LogicVRegister Simulator::ursra(VectorFormat vform,
 LogicVRegister Simulator::cls(VectorFormat vform,
                               LogicVRegister dst,
                               const LogicVRegister& src) {
-  uint64_t result[16];
-  int laneSizeInBits = LaneSizeInBitsFromFormat(vform);
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount; i++) {
-    result[i] = CountLeadingSignBits(src.Int(vform, i), laneSizeInBits);
+  int lane_size_in_bits = LaneSizeInBitsFromFormat(vform);
+  int lane_count = LaneCountFromFormat(vform);
+
+  // Ensure that we can store one result per lane.
+  int result[kZRegMaxSizeInBytes];
+
+  for (int i = 0; i < lane_count; i++) {
+    result[i] = CountLeadingSignBits(src.Int(vform, i), lane_size_in_bits);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -1681,38 +2010,51 @@ LogicVRegister Simulator::cls(VectorFormat vform,
 LogicVRegister Simulator::clz(VectorFormat vform,
                               LogicVRegister dst,
                               const LogicVRegister& src) {
-  uint64_t result[16];
-  int laneSizeInBits = LaneSizeInBitsFromFormat(vform);
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount; i++) {
-    result[i] = CountLeadingZeros(src.Uint(vform, i), laneSizeInBits);
+  int lane_size_in_bits = LaneSizeInBitsFromFormat(vform);
+  int lane_count = LaneCountFromFormat(vform);
+
+  // Ensure that we can store one result per lane.
+  int result[kZRegMaxSizeInBytes];
+
+  for (int i = 0; i < lane_count; i++) {
+    result[i] = CountLeadingZeros(src.Uint(vform, i), lane_size_in_bits);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
 }
 
 
+LogicVRegister Simulator::cnot(VectorFormat vform,
+                               LogicVRegister dst,
+                               const LogicVRegister& src) {
+  dst.ClearForWrite(vform);
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    uint64_t value = (src.Uint(vform, i) == 0) ? 1 : 0;
+    dst.SetUint(vform, i, value);
+  }
+  return dst;
+}
+
+
 LogicVRegister Simulator::cnt(VectorFormat vform,
                               LogicVRegister dst,
                               const LogicVRegister& src) {
-  uint64_t result[16];
-  int laneSizeInBits = LaneSizeInBitsFromFormat(vform);
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount; i++) {
-    uint64_t value = src.Uint(vform, i);
-    result[i] = 0;
-    for (int j = 0; j < laneSizeInBits; j++) {
-      result[i] += (value & 1);
-      value >>= 1;
-    }
+  int lane_size_in_bits = LaneSizeInBitsFromFormat(vform);
+  int lane_count = LaneCountFromFormat(vform);
+
+  // Ensure that we can store one result per lane.
+  int result[kZRegMaxSizeInBytes];
+
+  for (int i = 0; i < lane_count; i++) {
+    result[i] = CountSetBits(src.Uint(vform, i), lane_size_in_bits);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -1896,11 +2238,108 @@ LogicVRegister Simulator::abs(VectorFormat vform,
 }
 
 
+LogicVRegister Simulator::andv(VectorFormat vform,
+                               LogicVRegister dst,
+                               const LogicPRegister& pg,
+                               const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  uint64_t result = GetUintMask(LaneSizeInBitsFromFormat(vform));
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    result &= src.Uint(vform, i);
+  }
+  VectorFormat vform_dst =
+      ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
+  dst.ClearForWrite(vform_dst);
+  dst.SetUint(vform_dst, 0, result);
+  return dst;
+}
+
+
+LogicVRegister Simulator::eorv(VectorFormat vform,
+                               LogicVRegister dst,
+                               const LogicPRegister& pg,
+                               const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  uint64_t result = 0;
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    result ^= src.Uint(vform, i);
+  }
+  VectorFormat vform_dst =
+      ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
+  dst.ClearForWrite(vform_dst);
+  dst.SetUint(vform_dst, 0, result);
+  return dst;
+}
+
+
+LogicVRegister Simulator::orv(VectorFormat vform,
+                              LogicVRegister dst,
+                              const LogicPRegister& pg,
+                              const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  uint64_t result = 0;
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    result |= src.Uint(vform, i);
+  }
+  VectorFormat vform_dst =
+      ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
+  dst.ClearForWrite(vform_dst);
+  dst.SetUint(vform_dst, 0, result);
+  return dst;
+}
+
+
+LogicVRegister Simulator::saddv(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) <= kSRegSize);
+  int64_t result = 0;
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    // The destination register always has D-lane sizes and the source register
+    // always has S-lanes or smaller, so signed integer overflow -- undefined
+    // behaviour -- can't occur.
+    result += src.Int(vform, i);
+  }
+
+  dst.ClearForWrite(kFormatD);
+  dst.SetInt(kFormatD, 0, result);
+  return dst;
+}
+
+
+LogicVRegister Simulator::uaddv(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  uint64_t result = 0;
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    result += src.Uint(vform, i);
+  }
+
+  dst.ClearForWrite(kFormatD);
+  dst.SetUint(kFormatD, 0, result);
+  return dst;
+}
+
+
 LogicVRegister Simulator::extractnarrow(VectorFormat dstform,
                                         LogicVRegister dst,
-                                        bool dstIsSigned,
+                                        bool dst_is_signed,
                                         const LogicVRegister& src,
-                                        bool srcIsSigned) {
+                                        bool src_is_signed) {
   bool upperhalf = false;
   VectorFormat srcform = kFormatUndefined;
   int64_t ssrc[8];
@@ -1969,7 +2408,7 @@ LogicVRegister Simulator::extractnarrow(VectorFormat dstform,
     }
 
     // Test for unsigned saturation
-    if (srcIsSigned) {
+    if (src_is_signed) {
       if (ssrc[i] > static_cast<int64_t>(MaxUintFromFormat(dstform))) {
         dst.SetUnsignedSat(offset + i, true);
       } else if (ssrc[i] < 0) {
@@ -1982,13 +2421,13 @@ LogicVRegister Simulator::extractnarrow(VectorFormat dstform,
     }
 
     int64_t result;
-    if (srcIsSigned) {
+    if (src_is_signed) {
       result = ssrc[i] & MaxUintFromFormat(dstform);
     } else {
       result = usrc[i] & MaxUintFromFormat(dstform);
     }
 
-    if (dstIsSigned) {
+    if (dst_is_signed) {
       dst.SetInt(dstform, offset + i, result);
     } else {
       dst.SetUint(dstform, offset + i, result);
@@ -2030,17 +2469,17 @@ LogicVRegister Simulator::absdiff(VectorFormat vform,
                                   LogicVRegister dst,
                                   const LogicVRegister& src1,
                                   const LogicVRegister& src2,
-                                  bool issigned) {
+                                  bool is_signed) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    if (issigned) {
-      int64_t sr = src1.Int(vform, i) - src2.Int(vform, i);
-      sr = sr > 0 ? sr : -sr;
-      dst.SetInt(vform, i, sr);
+    bool src1_gt_src2 = is_signed ? (src1.Int(vform, i) > src2.Int(vform, i))
+                                  : (src1.Uint(vform, i) > src2.Uint(vform, i));
+    // Always calculate the answer using unsigned arithmetic, to avoid
+    // implemenation-defined signed overflow.
+    if (src1_gt_src2) {
+      dst.SetUint(vform, i, src1.Uint(vform, i) - src2.Uint(vform, i));
     } else {
-      int64_t sr = src1.Uint(vform, i) - src2.Uint(vform, i);
-      sr = sr > 0 ? sr : -sr;
-      dst.SetUint(vform, i, sr);
+      dst.SetUint(vform, i, src2.Uint(vform, i) - src1.Uint(vform, i));
     }
   }
   return dst;
@@ -2085,15 +2524,15 @@ LogicVRegister Simulator::not_(VectorFormat vform,
 LogicVRegister Simulator::rbit(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src) {
-  uint64_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  int laneSizeInBits = LaneSizeInBitsFromFormat(vform);
+  uint64_t result[kZRegMaxSizeInBytes];
+  int lane_count = LaneCountFromFormat(vform);
+  int lane_size_in_bits = LaneSizeInBitsFromFormat(vform);
   uint64_t reversed_value;
   uint64_t value;
-  for (int i = 0; i < laneCount; i++) {
+  for (int i = 0; i < lane_count; i++) {
     value = src.Uint(vform, i);
     reversed_value = 0;
-    for (int j = 0; j < laneSizeInBits; j++) {
+    for (int j = 0; j < lane_size_in_bits; j++) {
       reversed_value = (reversed_value << 1) | (value & 1);
       value >>= 1;
     }
@@ -2101,7 +2540,7 @@ LogicVRegister Simulator::rbit(VectorFormat vform,
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -2110,19 +2549,33 @@ LogicVRegister Simulator::rbit(VectorFormat vform,
 
 LogicVRegister Simulator::rev(VectorFormat vform,
                               LogicVRegister dst,
-                              const LogicVRegister& src,
-                              int revSize) {
-  uint64_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  int laneSize = LaneSizeInBytesFromFormat(vform);
-  int lanesPerLoop = revSize / laneSize;
-  for (int i = 0; i < laneCount; i += lanesPerLoop) {
-    for (int j = 0; j < lanesPerLoop; j++) {
-      result[i + lanesPerLoop - 1 - j] = src.Uint(vform, i + j);
+                              const LogicVRegister& src) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  int lane_count = LaneCountFromFormat(vform);
+  for (int i = 0; i < lane_count / 2; i++) {
+    uint64_t t = src.Uint(vform, i);
+    dst.SetUint(vform, i, src.Uint(vform, lane_count - i - 1));
+    dst.SetUint(vform, lane_count - i - 1, t);
+  }
+  return dst;
+}
+
+
+LogicVRegister Simulator::rev_byte(VectorFormat vform,
+                                   LogicVRegister dst,
+                                   const LogicVRegister& src,
+                                   int rev_size) {
+  uint64_t result[kZRegMaxSizeInBytes];
+  int lane_count = LaneCountFromFormat(vform);
+  int lane_size = LaneSizeInBytesFromFormat(vform);
+  int lanes_per_loop = rev_size / lane_size;
+  for (int i = 0; i < lane_count; i += lanes_per_loop) {
+    for (int j = 0; j < lanes_per_loop; j++) {
+      result[i + lanes_per_loop - 1 - j] = src.Uint(vform, i + j);
     }
   }
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -2132,21 +2585,21 @@ LogicVRegister Simulator::rev(VectorFormat vform,
 LogicVRegister Simulator::rev16(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src) {
-  return rev(vform, dst, src, 2);
+  return rev_byte(vform, dst, src, 2);
 }
 
 
 LogicVRegister Simulator::rev32(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src) {
-  return rev(vform, dst, src, 4);
+  return rev_byte(vform, dst, src, 4);
 }
 
 
 LogicVRegister Simulator::rev64(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src) {
-  return rev(vform, dst, src, 8);
+  return rev_byte(vform, dst, src, 8);
 }
 
 
@@ -2215,22 +2668,60 @@ LogicVRegister Simulator::ext(VectorFormat vform,
                               const LogicVRegister& src1,
                               const LogicVRegister& src2,
                               int index) {
-  uint8_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount - index; ++i) {
+  uint8_t result[kZRegMaxSizeInBytes];
+  int lane_count = LaneCountFromFormat(vform);
+  for (int i = 0; i < lane_count - index; ++i) {
     result[i] = src1.Uint(vform, i + index);
   }
   for (int i = 0; i < index; ++i) {
-    result[laneCount - index + i] = src2.Uint(vform, i);
+    result[lane_count - index + i] = src2.Uint(vform, i);
   }
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
 }
 
 template <typename T>
+LogicVRegister Simulator::fadda(VectorFormat vform,
+                                LogicVRegister acc,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src) {
+  T result = acc.Float<T>(0);
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    result = FPAdd(result, src.Float<T>(i));
+  }
+  VectorFormat vform_dst =
+      ScalarFormatFromLaneSize(LaneSizeInBitsFromFormat(vform));
+  acc.ClearForWrite(vform_dst);
+  acc.SetFloat(0, result);
+  return acc;
+}
+
+LogicVRegister Simulator::fadda(VectorFormat vform,
+                                LogicVRegister acc,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src) {
+  switch (LaneSizeInBitsFromFormat(vform)) {
+    case kHRegSize:
+      fadda<SimFloat16>(vform, acc, pg, src);
+      break;
+    case kSRegSize:
+      fadda<float>(vform, acc, pg, src);
+      break;
+    case kDRegSize:
+      fadda<double>(vform, acc, pg, src);
+      break;
+    default:
+      VIXL_UNREACHABLE();
+  }
+  return acc;
+}
+
+template <typename T>
 LogicVRegister Simulator::fcadd(VectorFormat vform,
                                 LogicVRegister dst,          // d
                                 const LogicVRegister& src1,  // n
@@ -2273,7 +2764,7 @@ LogicVRegister Simulator::fcadd(VectorFormat vform,
                                 const LogicVRegister& src2,  // m
                                 int rot) {
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    VIXL_UNIMPLEMENTED();
+    fcadd<SimFloat16>(vform, dst, src1, src2, rot);
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
     fcadd<float>(vform, dst, src1, src2, rot);
   } else {
@@ -2283,12 +2774,12 @@ LogicVRegister Simulator::fcadd(VectorFormat vform,
   return dst;
 }
 
-
 template <typename T>
 LogicVRegister Simulator::fcmla(VectorFormat vform,
-                                LogicVRegister dst,          // d
-                                const LogicVRegister& src1,  // n
-                                const LogicVRegister& src2,  // m
+                                LogicVRegister dst,
+                                const LogicVRegister& src1,
+                                const LogicVRegister& src2,
+                                const LogicVRegister& acc,
                                 int index,
                                 int rot) {
   int elements = LaneCountFromFormat(vform);
@@ -2301,83 +2792,33 @@ LogicVRegister Simulator::fcmla(VectorFormat vform,
   // 4S --> (4/2 = 2) - 1 = 1) --> 2 x Complex Number (2x2 components: r+i)
 
   for (int e = 0; e <= (elements / 2) - 1; e++) {
-    switch (rot) {
-      case 0:
-        element1 = src2.Float<T>(index * 2);
-        element2 = src1.Float<T>(e * 2);
-        element3 = src2.Float<T>(index * 2 + 1);
-        element4 = src1.Float<T>(e * 2);
-        break;
-      case 90:
-        element1 = FPNeg(src2.Float<T>(index * 2 + 1));
-        element2 = src1.Float<T>(e * 2 + 1);
-        element3 = src2.Float<T>(index * 2);
-        element4 = src1.Float<T>(e * 2 + 1);
-        break;
-      case 180:
-        element1 = FPNeg(src2.Float<T>(index * 2));
-        element2 = src1.Float<T>(e * 2);
-        element3 = FPNeg(src2.Float<T>(index * 2 + 1));
-        element4 = src1.Float<T>(e * 2);
-        break;
-      case 270:
-        element1 = src2.Float<T>(index * 2 + 1);
-        element2 = src1.Float<T>(e * 2 + 1);
-        element3 = FPNeg(src2.Float<T>(index * 2));
-        element4 = src1.Float<T>(e * 2 + 1);
-        break;
-      default:
-        VIXL_UNREACHABLE();
-        return dst;  // prevents "element(n) may be unintialized" errors
-    }
-    dst.ClearForWrite(vform);
-    dst.SetFloat<T>(e * 2, FPMulAdd(dst.Float<T>(e * 2), element2, element1));
-    dst.SetFloat<T>(e * 2 + 1,
-                    FPMulAdd(dst.Float<T>(e * 2 + 1), element4, element3));
-  }
-  return dst;
-}
-
-
-template <typename T>
-LogicVRegister Simulator::fcmla(VectorFormat vform,
-                                LogicVRegister dst,          // d
-                                const LogicVRegister& src1,  // n
-                                const LogicVRegister& src2,  // m
-                                int rot) {
-  int elements = LaneCountFromFormat(vform);
+    // Index == -1 indicates a vector/vector rather than vector/indexed-element
+    // operation.
+    int f = (index < 0) ? e : index;
 
-  T element1, element2, element3, element4;
-  rot *= 90;
-
-  // Loop example:
-  // 2S --> (2/2 = 1 - 1 = 0) --> 1 x Complex Number (2x components: r+i)
-  // 4S --> (4/2 = 2) - 1 = 1) --> 2 x Complex Number (2x2 components: r+i)
-
-  for (int e = 0; e <= (elements / 2) - 1; e++) {
     switch (rot) {
       case 0:
-        element1 = src2.Float<T>(e * 2);
+        element1 = src2.Float<T>(f * 2);
         element2 = src1.Float<T>(e * 2);
-        element3 = src2.Float<T>(e * 2 + 1);
+        element3 = src2.Float<T>(f * 2 + 1);
         element4 = src1.Float<T>(e * 2);
         break;
       case 90:
-        element1 = FPNeg(src2.Float<T>(e * 2 + 1));
+        element1 = FPNeg(src2.Float<T>(f * 2 + 1));
         element2 = src1.Float<T>(e * 2 + 1);
-        element3 = src2.Float<T>(e * 2);
+        element3 = src2.Float<T>(f * 2);
         element4 = src1.Float<T>(e * 2 + 1);
         break;
       case 180:
-        element1 = FPNeg(src2.Float<T>(e * 2));
+        element1 = FPNeg(src2.Float<T>(f * 2));
         element2 = src1.Float<T>(e * 2);
-        element3 = FPNeg(src2.Float<T>(e * 2 + 1));
+        element3 = FPNeg(src2.Float<T>(f * 2 + 1));
         element4 = src1.Float<T>(e * 2);
         break;
       case 270:
-        element1 = src2.Float<T>(e * 2 + 1);
+        element1 = src2.Float<T>(f * 2 + 1);
         element2 = src1.Float<T>(e * 2 + 1);
-        element3 = FPNeg(src2.Float<T>(e * 2));
+        element3 = FPNeg(src2.Float<T>(f * 2));
         element4 = src1.Float<T>(e * 2 + 1);
         break;
       default:
@@ -2385,25 +2826,28 @@ LogicVRegister Simulator::fcmla(VectorFormat vform,
         return dst;  // prevents "element(n) may be unintialized" errors
     }
     dst.ClearForWrite(vform);
-    dst.SetFloat<T>(e * 2, FPMulAdd(dst.Float<T>(e * 2), element2, element1));
-    dst.SetFloat<T>(e * 2 + 1,
-                    FPMulAdd(dst.Float<T>(e * 2 + 1), element4, element3));
+    dst.SetFloat<T>(vform,
+                    e * 2,
+                    FPMulAdd(acc.Float<T>(e * 2), element2, element1));
+    dst.SetFloat<T>(vform,
+                    e * 2 + 1,
+                    FPMulAdd(acc.Float<T>(e * 2 + 1), element4, element3));
   }
   return dst;
 }
 
-
 LogicVRegister Simulator::fcmla(VectorFormat vform,
-                                LogicVRegister dst,          // d
-                                const LogicVRegister& src1,  // n
-                                const LogicVRegister& src2,  // m
+                                LogicVRegister dst,
+                                const LogicVRegister& src1,
+                                const LogicVRegister& src2,
+                                const LogicVRegister& acc,
                                 int rot) {
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    VIXL_UNIMPLEMENTED();
+    fcmla<SimFloat16>(vform, dst, src1, src2, acc, -1, rot);
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
-    fcmla<float>(vform, dst, src1, src2, rot);
+    fcmla<float>(vform, dst, src1, src2, acc, -1, rot);
   } else {
-    fcmla<double>(vform, dst, src1, src2, rot);
+    fcmla<double>(vform, dst, src1, src2, acc, -1, rot);
   }
   return dst;
 }
@@ -2418,9 +2862,9 @@ LogicVRegister Simulator::fcmla(VectorFormat vform,
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
     VIXL_UNIMPLEMENTED();
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
-    fcmla<float>(vform, dst, src1, src2, index, rot);
+    fcmla<float>(vform, dst, src1, src2, dst, index, rot);
   } else {
-    fcmla<double>(vform, dst, src1, src2, index, rot);
+    fcmla<double>(vform, dst, src1, src2, dst, index, rot);
   }
   return dst;
 }
@@ -2430,23 +2874,59 @@ LogicVRegister Simulator::dup_element(VectorFormat vform,
                                       LogicVRegister dst,
                                       const LogicVRegister& src,
                                       int src_index) {
-  int laneCount = LaneCountFromFormat(vform);
-  uint64_t value = src.Uint(vform, src_index);
-  dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
-    dst.SetUint(vform, i, value);
+  if (vform == kFormatVnQ) {
+    // When duplicating a 128-bit value, split it into two 64-bit parts, and
+    // then copy the two to their slots on destination register.
+    uint64_t low = src.Uint(kFormatVnD, src_index * 2);
+    uint64_t high = src.Uint(kFormatVnD, (src_index * 2) + 1);
+    dst.ClearForWrite(vform);
+    for (int d_lane = 0; d_lane < LaneCountFromFormat(kFormatVnD);
+         d_lane += 2) {
+      dst.SetUint(kFormatVnD, d_lane, low);
+      dst.SetUint(kFormatVnD, d_lane + 1, high);
+    }
+  } else {
+    int lane_count = LaneCountFromFormat(vform);
+    uint64_t value = src.Uint(vform, src_index);
+    dst.ClearForWrite(vform);
+    for (int i = 0; i < lane_count; ++i) {
+      dst.SetUint(vform, i, value);
+    }
   }
   return dst;
 }
 
+LogicVRegister Simulator::dup_elements_to_segments(VectorFormat vform,
+                                                   LogicVRegister dst,
+                                                   const LogicVRegister& src,
+                                                   int src_index) {
+  // In SVE, a segment is a 128-bit portion of a vector, like a Q register,
+  // whereas in NEON, the size of segment is equal to the size of register
+  // itself.
+  int segment_size = std::min(kQRegSize, RegisterSizeInBitsFromFormat(vform));
+  VIXL_ASSERT(IsMultiple(segment_size, LaneSizeInBitsFromFormat(vform)));
+  int lanes_per_segment = segment_size / LaneSizeInBitsFromFormat(vform);
+
+  VIXL_ASSERT(src_index >= 0);
+  VIXL_ASSERT(src_index < lanes_per_segment);
+
+  dst.ClearForWrite(vform);
+  for (int j = 0; j < LaneCountFromFormat(vform); j += lanes_per_segment) {
+    uint64_t value = src.Uint(vform, j + src_index);
+    for (int i = 0; i < lanes_per_segment; i++) {
+      dst.SetUint(vform, j + i, value);
+    }
+  }
+  return dst;
+}
 
 LogicVRegister Simulator::dup_immediate(VectorFormat vform,
                                         LogicVRegister dst,
                                         uint64_t imm) {
-  int laneCount = LaneCountFromFormat(vform);
+  int lane_count = LaneCountFromFormat(vform);
   uint64_t value = imm & MaxUintFromFormat(vform);
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, value);
   }
   return dst;
@@ -2473,12 +2953,93 @@ LogicVRegister Simulator::ins_immediate(VectorFormat vform,
 }
 
 
+LogicVRegister Simulator::index(VectorFormat vform,
+                                LogicVRegister dst,
+                                uint64_t start,
+                                uint64_t step) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  uint64_t value = start;
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    dst.SetUint(vform, i, value);
+    value += step;
+  }
+  return dst;
+}
+
+
+LogicVRegister Simulator::insr(VectorFormat vform,
+                               LogicVRegister dst,
+                               uint64_t imm) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  for (int i = LaneCountFromFormat(vform) - 1; i > 0; i--) {
+    dst.SetUint(vform, i, dst.Uint(vform, i - 1));
+  }
+  dst.SetUint(vform, 0, imm);
+  return dst;
+}
+
+
+LogicVRegister Simulator::mov(VectorFormat vform,
+                              LogicVRegister dst,
+                              const LogicVRegister& src) {
+  dst.ClearForWrite(vform);
+  for (int lane = 0; lane < LaneCountFromFormat(vform); lane++) {
+    dst.SetUint(vform, lane, src.Uint(vform, lane));
+  }
+  return dst;
+}
+
+
+LogicPRegister Simulator::mov(LogicPRegister dst, const LogicPRegister& src) {
+  // Avoid a copy if the registers already alias.
+  if (dst.Aliases(src)) return dst;
+
+  for (int i = 0; i < dst.GetChunkCount(); i++) {
+    dst.SetChunk(i, src.GetChunk(i));
+  }
+  return dst;
+}
+
+
+LogicVRegister Simulator::mov_merging(VectorFormat vform,
+                                      LogicVRegister dst,
+                                      const SimPRegister& pg,
+                                      const LogicVRegister& src) {
+  return sel(vform, dst, pg, src, dst);
+}
+
+
+LogicVRegister Simulator::mov_zeroing(VectorFormat vform,
+                                      LogicVRegister dst,
+                                      const SimPRegister& pg,
+                                      const LogicVRegister& src) {
+  SimVRegister zero;
+  dup_immediate(vform, zero, 0);
+  return sel(vform, dst, pg, src, zero);
+}
+
+
+LogicPRegister Simulator::mov_merging(LogicPRegister dst,
+                                      const LogicPRegister& pg,
+                                      const LogicPRegister& src) {
+  return sel(dst, pg, src, dst);
+}
+
+
+LogicPRegister Simulator::mov_zeroing(LogicPRegister dst,
+                                      const LogicPRegister& pg,
+                                      const LogicPRegister& src) {
+  SimPRegister all_false;
+  return sel(dst, pg, src, pfalse(all_false));
+}
+
+
 LogicVRegister Simulator::movi(VectorFormat vform,
                                LogicVRegister dst,
                                uint64_t imm) {
-  int laneCount = LaneCountFromFormat(vform);
+  int lane_count = LaneCountFromFormat(vform);
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, imm);
   }
   return dst;
@@ -2488,9 +3049,9 @@ LogicVRegister Simulator::movi(VectorFormat vform,
 LogicVRegister Simulator::mvni(VectorFormat vform,
                                LogicVRegister dst,
                                uint64_t imm) {
-  int laneCount = LaneCountFromFormat(vform);
+  int lane_count = LaneCountFromFormat(vform);
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, ~imm);
   }
   return dst;
@@ -2502,12 +3063,12 @@ LogicVRegister Simulator::orr(VectorFormat vform,
                               const LogicVRegister& src,
                               uint64_t imm) {
   uint64_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  int lane_count = LaneCountFromFormat(vform);
+  for (int i = 0; i < lane_count; ++i) {
     result[i] = src.Uint(vform, i) | imm;
   }
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -2568,6 +3129,37 @@ LogicVRegister Simulator::sxtl2(VectorFormat vform,
 }
 
 
+LogicVRegister Simulator::uxt(VectorFormat vform,
+                              LogicVRegister dst,
+                              const LogicVRegister& src,
+                              unsigned from_size_in_bits) {
+  int lane_count = LaneCountFromFormat(vform);
+  uint64_t mask = GetUintMask(from_size_in_bits);
+
+  dst.ClearForWrite(vform);
+  for (int i = 0; i < lane_count; i++) {
+    dst.SetInt(vform, i, src.Uint(vform, i) & mask);
+  }
+  return dst;
+}
+
+
+LogicVRegister Simulator::sxt(VectorFormat vform,
+                              LogicVRegister dst,
+                              const LogicVRegister& src,
+                              unsigned from_size_in_bits) {
+  int lane_count = LaneCountFromFormat(vform);
+
+  dst.ClearForWrite(vform);
+  for (int i = 0; i < lane_count; i++) {
+    uint64_t value =
+        ExtractSignedBitfield64(from_size_in_bits - 1, 0, src.Uint(vform, i));
+    dst.SetInt(vform, i, value);
+  }
+  return dst;
+}
+
+
 LogicVRegister Simulator::shrn(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src,
@@ -2615,6 +3207,22 @@ LogicVRegister Simulator::rshrn2(VectorFormat vform,
   return extractnarrow(vformdst, dst, false, shifted_src, false);
 }
 
+LogicVRegister Simulator::Table(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& tab,
+                                const LogicVRegister& ind) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  int lane_count = LaneCountFromFormat(vform);
+  for (int i = 0; i < lane_count; i++) {
+    uint64_t index = ind.Uint(vform, i);
+    uint64_t value = (index >= static_cast<uint64_t>(lane_count))
+                         ? 0
+                         : tab.Uint(vform, static_cast<int>(index));
+    dst.SetUint(vform, i, value);
+  }
+  return dst;
+}
+
 
 LogicVRegister Simulator::Table(VectorFormat vform,
                                 LogicVRegister dst,
@@ -3182,7 +3790,7 @@ LogicVRegister Simulator::umlsl(VectorFormat vform,
   SimVRegister temp1, temp2;
   uxtl(vform, temp1, src1);
   uxtl(vform, temp2, src2);
-  mls(vform, dst, temp1, temp2);
+  mls(vform, dst, dst, temp1, temp2);
   return dst;
 }
 
@@ -3194,7 +3802,7 @@ LogicVRegister Simulator::umlsl2(VectorFormat vform,
   SimVRegister temp1, temp2;
   uxtl2(vform, temp1, src1);
   uxtl2(vform, temp2, src2);
-  mls(vform, dst, temp1, temp2);
+  mls(vform, dst, dst, temp1, temp2);
   return dst;
 }
 
@@ -3206,7 +3814,7 @@ LogicVRegister Simulator::smlsl(VectorFormat vform,
   SimVRegister temp1, temp2;
   sxtl(vform, temp1, src1);
   sxtl(vform, temp2, src2);
-  mls(vform, dst, temp1, temp2);
+  mls(vform, dst, dst, temp1, temp2);
   return dst;
 }
 
@@ -3218,7 +3826,7 @@ LogicVRegister Simulator::smlsl2(VectorFormat vform,
   SimVRegister temp1, temp2;
   sxtl2(vform, temp1, src1);
   sxtl2(vform, temp2, src2);
-  mls(vform, dst, temp1, temp2);
+  mls(vform, dst, dst, temp1, temp2);
   return dst;
 }
 
@@ -3230,7 +3838,7 @@ LogicVRegister Simulator::umlal(VectorFormat vform,
   SimVRegister temp1, temp2;
   uxtl(vform, temp1, src1);
   uxtl(vform, temp2, src2);
-  mla(vform, dst, temp1, temp2);
+  mla(vform, dst, dst, temp1, temp2);
   return dst;
 }
 
@@ -3242,7 +3850,7 @@ LogicVRegister Simulator::umlal2(VectorFormat vform,
   SimVRegister temp1, temp2;
   uxtl2(vform, temp1, src1);
   uxtl2(vform, temp2, src2);
-  mla(vform, dst, temp1, temp2);
+  mla(vform, dst, dst, temp1, temp2);
   return dst;
 }
 
@@ -3254,7 +3862,7 @@ LogicVRegister Simulator::smlal(VectorFormat vform,
   SimVRegister temp1, temp2;
   sxtl(vform, temp1, src1);
   sxtl(vform, temp2, src2);
-  mla(vform, dst, temp1, temp2);
+  mla(vform, dst, dst, temp1, temp2);
   return dst;
 }
 
@@ -3266,7 +3874,7 @@ LogicVRegister Simulator::smlal2(VectorFormat vform,
   SimVRegister temp1, temp2;
   sxtl2(vform, temp1, src1);
   sxtl2(vform, temp2, src2);
-  mla(vform, dst, temp1, temp2);
+  mla(vform, dst, dst, temp1, temp2);
   return dst;
 }
 
@@ -3371,7 +3979,7 @@ LogicVRegister Simulator::dot(VectorFormat vform,
 
   dst.ClearForWrite(vform);
   for (int e = 0; e < LaneCountFromFormat(vform); e++) {
-    int64_t result = 0;
+    uint64_t result = 0;
     int64_t element1, element2;
     for (int i = 0; i < 4; i++) {
       int index = 4 * e + i;
@@ -3384,9 +3992,7 @@ LogicVRegister Simulator::dot(VectorFormat vform,
       }
       result += element1 * element2;
     }
-
-    result += dst.Int(vform, e);
-    dst.SetInt(vform, e, result);
+    dst.SetUint(vform, e, result + dst.Uint(vform, e));
   }
   return dst;
 }
@@ -3564,16 +4170,16 @@ LogicVRegister Simulator::trn1(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
-  uint64_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  int pairs = laneCount / 2;
+  uint64_t result[kZRegMaxSizeInBytes];
+  int lane_count = LaneCountFromFormat(vform);
+  int pairs = lane_count / 2;
   for (int i = 0; i < pairs; ++i) {
     result[2 * i] = src1.Uint(vform, 2 * i);
     result[(2 * i) + 1] = src2.Uint(vform, 2 * i);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -3584,16 +4190,16 @@ LogicVRegister Simulator::trn2(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
-  uint64_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  int pairs = laneCount / 2;
+  uint64_t result[kZRegMaxSizeInBytes];
+  int lane_count = LaneCountFromFormat(vform);
+  int pairs = lane_count / 2;
   for (int i = 0; i < pairs; ++i) {
     result[2 * i] = src1.Uint(vform, (2 * i) + 1);
     result[(2 * i) + 1] = src2.Uint(vform, (2 * i) + 1);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -3604,16 +4210,16 @@ LogicVRegister Simulator::zip1(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
-  uint64_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  int pairs = laneCount / 2;
+  uint64_t result[kZRegMaxSizeInBytes];
+  int lane_count = LaneCountFromFormat(vform);
+  int pairs = lane_count / 2;
   for (int i = 0; i < pairs; ++i) {
     result[2 * i] = src1.Uint(vform, i);
     result[(2 * i) + 1] = src2.Uint(vform, i);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -3624,16 +4230,16 @@ LogicVRegister Simulator::zip2(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
-  uint64_t result[16];
-  int laneCount = LaneCountFromFormat(vform);
-  int pairs = laneCount / 2;
+  uint64_t result[kZRegMaxSizeInBytes];
+  int lane_count = LaneCountFromFormat(vform);
+  int pairs = lane_count / 2;
   for (int i = 0; i < pairs; ++i) {
     result[2 * i] = src1.Uint(vform, pairs + i);
     result[(2 * i) + 1] = src2.Uint(vform, pairs + i);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[i]);
   }
   return dst;
@@ -3644,15 +4250,15 @@ LogicVRegister Simulator::uzp1(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
-  uint64_t result[32];
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  uint64_t result[kZRegMaxSizeInBytes * 2];
+  int lane_count = LaneCountFromFormat(vform);
+  for (int i = 0; i < lane_count; ++i) {
     result[i] = src1.Uint(vform, i);
-    result[laneCount + i] = src2.Uint(vform, i);
+    result[lane_count + i] = src2.Uint(vform, i);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[2 * i]);
   }
   return dst;
@@ -3663,15 +4269,15 @@ LogicVRegister Simulator::uzp2(VectorFormat vform,
                                LogicVRegister dst,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
-  uint64_t result[32];
-  int laneCount = LaneCountFromFormat(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  uint64_t result[kZRegMaxSizeInBytes * 2];
+  int lane_count = LaneCountFromFormat(vform);
+  for (int i = 0; i < lane_count; ++i) {
     result[i] = src1.Uint(vform, i);
-    result[laneCount + i] = src2.Uint(vform, i);
+    result[lane_count + i] = src2.Uint(vform, i);
   }
 
   dst.ClearForWrite(vform);
-  for (int i = 0; i < laneCount; ++i) {
+  for (int i = 0; i < lane_count; ++i) {
     dst.SetUint(vform, i, result[(2 * i) + 1]);
   }
   return dst;
@@ -4105,11 +4711,20 @@ double Simulator::FPRoundInt(double value,
 
   double result = FPRoundIntCommon(value, round_mode);
 
+  // We want to compare `result > INT64_MAX` below, but INT64_MAX isn't exactly
+  // representable as a double, and is rounded to (INT64_MAX + 1) when
+  // converted. To avoid this, we compare `result >= int64_max_plus_one`
+  // instead; this is safe because `result` is known to be integral, and
+  // `int64_max_plus_one` is exactly representable as a double.
+  constexpr uint64_t int64_max_plus_one = static_cast<uint64_t>(INT64_MAX) + 1;
+  VIXL_STATIC_ASSERT(static_cast<uint64_t>(static_cast<double>(
+                         int64_max_plus_one)) == int64_max_plus_one);
+
   if (frint_mode == kFrintToInt32) {
     if ((result > INT32_MAX) || (result < INT32_MIN)) {
       return INT32_MIN;
     }
-  } else if ((result > INT64_MAX) || (result < INT64_MIN)) {
+  } else if ((result >= int64_max_plus_one) || (result < INT64_MIN)) {
     return INT64_MIN;
   }
 
@@ -4201,7 +4816,7 @@ uint64_t Simulator::FPToUInt64(double value, FPRounding rmode) {
       } else {                                                   \
         result = OP(op1, op2);                                   \
       }                                                          \
-      dst.SetFloat(i, result);                                   \
+      dst.SetFloat(vform, i, result);                            \
     }                                                            \
     return dst;                                                  \
   }                                                              \
@@ -4244,7 +4859,7 @@ LogicVRegister Simulator::frecps(VectorFormat vform,
     T op1 = -src1.Float<T>(i);
     T op2 = src2.Float<T>(i);
     T result = FPProcessNaNs(op1, op2);
-    dst.SetFloat(i, IsNaN(result) ? result : FPRecipStepFused(op1, op2));
+    dst.SetFloat(vform, i, IsNaN(result) ? result : FPRecipStepFused(op1, op2));
   }
   return dst;
 }
@@ -4276,7 +4891,7 @@ LogicVRegister Simulator::frsqrts(VectorFormat vform,
     T op1 = -src1.Float<T>(i);
     T op2 = src2.Float<T>(i);
     T result = FPProcessNaNs(op1, op2);
-    dst.SetFloat(i, IsNaN(result) ? result : FPRSqrtStepFused(op1, op2));
+    dst.SetFloat(vform, i, IsNaN(result) ? result : FPRSqrtStepFused(op1, op2));
   }
   return dst;
 }
@@ -4309,29 +4924,41 @@ LogicVRegister Simulator::fcmp(VectorFormat vform,
     bool result = false;
     T op1 = src1.Float<T>(i);
     T op2 = src2.Float<T>(i);
-    T nan_result = FPProcessNaNs(op1, op2);
-    if (!IsNaN(nan_result)) {
-      switch (cond) {
-        case eq:
-          result = (op1 == op2);
-          break;
-        case ge:
-          result = (op1 >= op2);
-          break;
-        case gt:
-          result = (op1 > op2);
-          break;
-        case le:
-          result = (op1 <= op2);
-          break;
-        case lt:
-          result = (op1 < op2);
-          break;
-        default:
-          VIXL_UNREACHABLE();
-          break;
-      }
+    bool unordered = IsNaN(FPProcessNaNs(op1, op2));
+
+    switch (cond) {
+      case eq:
+        result = (op1 == op2);
+        break;
+      case ge:
+        result = (op1 >= op2);
+        break;
+      case gt:
+        result = (op1 > op2);
+        break;
+      case le:
+        result = (op1 <= op2);
+        break;
+      case lt:
+        result = (op1 < op2);
+        break;
+      case ne:
+        result = (op1 != op2);
+        break;
+      case uo:
+        result = unordered;
+        break;
+      default:
+        // Other conditions are defined in terms of those above.
+        VIXL_UNREACHABLE();
+        break;
+    }
+
+    if (result && unordered) {
+      // Only `uo` and `ne` can be true for unordered comparisons.
+      VIXL_ASSERT((cond == uo) || (cond == ne));
     }
+
     dst.SetUint(vform, i, result ? MaxUintFromFormat(vform) : 0);
   }
   return dst;
@@ -4403,15 +5030,16 @@ LogicVRegister Simulator::fabscmp(VectorFormat vform,
 template <typename T>
 LogicVRegister Simulator::fmla(VectorFormat vform,
                                LogicVRegister dst,
+                               const LogicVRegister& srca,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     T op1 = src1.Float<T>(i);
     T op2 = src2.Float<T>(i);
-    T acc = dst.Float<T>(i);
+    T acc = srca.Float<T>(i);
     T result = FPMulAdd(acc, op1, op2);
-    dst.SetFloat(i, result);
+    dst.SetFloat(vform, i, result);
   }
   return dst;
 }
@@ -4419,15 +5047,16 @@ LogicVRegister Simulator::fmla(VectorFormat vform,
 
 LogicVRegister Simulator::fmla(VectorFormat vform,
                                LogicVRegister dst,
+                               const LogicVRegister& srca,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    fmla<SimFloat16>(vform, dst, src1, src2);
+    fmla<SimFloat16>(vform, dst, srca, src1, src2);
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
-    fmla<float>(vform, dst, src1, src2);
+    fmla<float>(vform, dst, srca, src1, src2);
   } else {
     VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
-    fmla<double>(vform, dst, src1, src2);
+    fmla<double>(vform, dst, srca, src1, src2);
   }
   return dst;
 }
@@ -4436,13 +5065,14 @@ LogicVRegister Simulator::fmla(VectorFormat vform,
 template <typename T>
 LogicVRegister Simulator::fmls(VectorFormat vform,
                                LogicVRegister dst,
+                               const LogicVRegister& srca,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
   dst.ClearForWrite(vform);
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
     T op1 = -src1.Float<T>(i);
     T op2 = src2.Float<T>(i);
-    T acc = dst.Float<T>(i);
+    T acc = srca.Float<T>(i);
     T result = FPMulAdd(acc, op1, op2);
     dst.SetFloat(i, result);
   }
@@ -4452,15 +5082,16 @@ LogicVRegister Simulator::fmls(VectorFormat vform,
 
 LogicVRegister Simulator::fmls(VectorFormat vform,
                                LogicVRegister dst,
+                               const LogicVRegister& srca,
                                const LogicVRegister& src1,
                                const LogicVRegister& src2) {
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    fmls<SimFloat16>(vform, dst, src1, src2);
+    fmls<SimFloat16>(vform, dst, srca, src1, src2);
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
-    fmls<float>(vform, dst, src1, src2);
+    fmls<float>(vform, dst, srca, src1, src2);
   } else {
     VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
-    fmls<double>(vform, dst, src1, src2);
+    fmls<double>(vform, dst, srca, src1, src2);
   }
   return dst;
 }
@@ -4740,75 +5371,131 @@ NEON_FPPAIRWISE_LIST(DEFINE_NEON_FP_PAIR_OP)
 #undef DEFINE_NEON_FP_PAIR_OP
 
 template <typename T>
-LogicVRegister Simulator::fminmaxv(VectorFormat vform,
-                                   LogicVRegister dst,
-                                   const LogicVRegister& src,
-                                   typename TFPMinMaxOp<T>::type Op) {
-  VIXL_ASSERT((vform == kFormat4H) || (vform == kFormat8H) ||
-              (vform == kFormat4S));
-  USE(vform);
-  T result1 = (this->*Op)(src.Float<T>(0), src.Float<T>(1));
-  T result2 = (this->*Op)(src.Float<T>(2), src.Float<T>(3));
-  if (vform == kFormat8H) {
-    T result3 = (this->*Op)(src.Float<T>(4), src.Float<T>(5));
-    T result4 = (this->*Op)(src.Float<T>(6), src.Float<T>(7));
-    result1 = (this->*Op)(result1, result3);
-    result2 = (this->*Op)(result2, result4);
-  }
-  T result = (this->*Op)(result1, result2);
+LogicVRegister Simulator::FPPairedAcrossHelper(VectorFormat vform,
+                                               LogicVRegister dst,
+                                               const LogicVRegister& src,
+                                               typename TFPPairOp<T>::type fn,
+                                               uint64_t inactive_value) {
+  int lane_count = LaneCountFromFormat(vform);
+  T result[kZRegMaxSizeInBytes / sizeof(T)];
+  // Copy the source vector into a working array. Initialise the unused elements
+  // at the end of the array to the same value that a false predicate would set.
+  for (int i = 0; i < static_cast<int>(ArrayLength(result)); i++) {
+    result[i] = (i < lane_count)
+                    ? src.Float<T>(i)
+                    : RawbitsWithSizeToFP<T>(sizeof(T) * 8, inactive_value);
+  }
+
+  // Pairwise reduce the elements to a single value, using the pair op function
+  // argument.
+  for (int step = 1; step < lane_count; step *= 2) {
+    for (int i = 0; i < lane_count; i += step * 2) {
+      result[i] = (this->*fn)(result[i], result[i + step]);
+    }
+  }
   dst.ClearForWrite(ScalarFormatFromFormat(vform));
-  dst.SetFloat<T>(0, result);
-  return dst;
+  dst.SetFloat<T>(0, result[0]);
+  return dst;
+}
+
+LogicVRegister Simulator::FPPairedAcrossHelper(
+    VectorFormat vform,
+    LogicVRegister dst,
+    const LogicVRegister& src,
+    typename TFPPairOp<SimFloat16>::type fn16,
+    typename TFPPairOp<float>::type fn32,
+    typename TFPPairOp<double>::type fn64,
+    uint64_t inactive_value) {
+  switch (LaneSizeInBitsFromFormat(vform)) {
+    case kHRegSize:
+      return FPPairedAcrossHelper<SimFloat16>(vform,
+                                              dst,
+                                              src,
+                                              fn16,
+                                              inactive_value);
+    case kSRegSize:
+      return FPPairedAcrossHelper<float>(vform, dst, src, fn32, inactive_value);
+    default:
+      VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
+      return FPPairedAcrossHelper<double>(vform,
+                                          dst,
+                                          src,
+                                          fn64,
+                                          inactive_value);
+  }
 }
 
+LogicVRegister Simulator::faddv(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& src) {
+  return FPPairedAcrossHelper(vform,
+                              dst,
+                              src,
+                              &Simulator::FPAdd<SimFloat16>,
+                              &Simulator::FPAdd<float>,
+                              &Simulator::FPAdd<double>,
+                              0);
+}
 
 LogicVRegister Simulator::fmaxv(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src) {
-  if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    return fminmaxv<SimFloat16>(vform, dst, src, &Simulator::FPMax<SimFloat16>);
-  } else {
-    return fminmaxv<float>(vform, dst, src, &Simulator::FPMax<float>);
-  }
+  int lane_size = LaneSizeInBitsFromFormat(vform);
+  uint64_t inactive_value =
+      FPToRawbitsWithSize(lane_size, kFP64NegativeInfinity);
+  return FPPairedAcrossHelper(vform,
+                              dst,
+                              src,
+                              &Simulator::FPMax<SimFloat16>,
+                              &Simulator::FPMax<float>,
+                              &Simulator::FPMax<double>,
+                              inactive_value);
 }
 
 
 LogicVRegister Simulator::fminv(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src) {
-  if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    return fminmaxv<SimFloat16>(vform, dst, src, &Simulator::FPMin<SimFloat16>);
-  } else {
-    return fminmaxv<float>(vform, dst, src, &Simulator::FPMin<float>);
-  }
+  int lane_size = LaneSizeInBitsFromFormat(vform);
+  uint64_t inactive_value =
+      FPToRawbitsWithSize(lane_size, kFP64PositiveInfinity);
+  return FPPairedAcrossHelper(vform,
+                              dst,
+                              src,
+                              &Simulator::FPMin<SimFloat16>,
+                              &Simulator::FPMin<float>,
+                              &Simulator::FPMin<double>,
+                              inactive_value);
 }
 
 
 LogicVRegister Simulator::fmaxnmv(VectorFormat vform,
                                   LogicVRegister dst,
                                   const LogicVRegister& src) {
-  if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    return fminmaxv<SimFloat16>(vform,
-                                dst,
-                                src,
-                                &Simulator::FPMaxNM<SimFloat16>);
-  } else {
-    return fminmaxv<float>(vform, dst, src, &Simulator::FPMaxNM<float>);
-  }
+  int lane_size = LaneSizeInBitsFromFormat(vform);
+  uint64_t inactive_value = FPToRawbitsWithSize(lane_size, kFP64DefaultNaN);
+  return FPPairedAcrossHelper(vform,
+                              dst,
+                              src,
+                              &Simulator::FPMaxNM<SimFloat16>,
+                              &Simulator::FPMaxNM<float>,
+                              &Simulator::FPMaxNM<double>,
+                              inactive_value);
 }
 
 
 LogicVRegister Simulator::fminnmv(VectorFormat vform,
                                   LogicVRegister dst,
                                   const LogicVRegister& src) {
-  if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    return fminmaxv<SimFloat16>(vform,
-                                dst,
-                                src,
-                                &Simulator::FPMinNM<SimFloat16>);
-  } else {
-    return fminmaxv<float>(vform, dst, src, &Simulator::FPMinNM<float>);
-  }
+  int lane_size = LaneSizeInBitsFromFormat(vform);
+  uint64_t inactive_value = FPToRawbitsWithSize(lane_size, kFP64DefaultNaN);
+  return FPPairedAcrossHelper(vform,
+                              dst,
+                              src,
+                              &Simulator::FPMinNM<SimFloat16>,
+                              &Simulator::FPMinNM<float>,
+                              &Simulator::FPMinNM<double>,
+                              inactive_value);
 }
 
 
@@ -4843,14 +5530,14 @@ LogicVRegister Simulator::fmla(VectorFormat vform,
   SimVRegister temp;
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
     LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
-    fmla<SimFloat16>(vform, dst, src1, index_reg);
+    fmla<SimFloat16>(vform, dst, dst, src1, index_reg);
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
     LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
-    fmla<float>(vform, dst, src1, index_reg);
+    fmla<float>(vform, dst, dst, src1, index_reg);
   } else {
     VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
     LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
-    fmla<double>(vform, dst, src1, index_reg);
+    fmla<double>(vform, dst, dst, src1, index_reg);
   }
   return dst;
 }
@@ -4865,14 +5552,14 @@ LogicVRegister Simulator::fmls(VectorFormat vform,
   SimVRegister temp;
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
     LogicVRegister index_reg = dup_element(kFormat8H, temp, src2, index);
-    fmls<SimFloat16>(vform, dst, src1, index_reg);
+    fmls<SimFloat16>(vform, dst, dst, src1, index_reg);
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
     LogicVRegister index_reg = dup_element(kFormat4S, temp, src2, index);
-    fmls<float>(vform, dst, src1, index_reg);
+    fmls<float>(vform, dst, dst, src1, index_reg);
   } else {
     VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
     LogicVRegister index_reg = dup_element(kFormat2D, temp, src2, index);
-    fmls<double>(vform, dst, src1, index_reg);
+    fmls<double>(vform, dst, dst, src1, index_reg);
   }
   return dst;
 }
@@ -4941,62 +5628,142 @@ LogicVRegister Simulator::frint(VectorFormat vform,
   return dst;
 }
 
+LogicVRegister Simulator::fcvt(VectorFormat vform,
+                               unsigned dst_data_size_in_bits,
+                               unsigned src_data_size_in_bits,
+                               LogicVRegister dst,
+                               const LogicPRegister& pg,
+                               const LogicVRegister& src) {
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= dst_data_size_in_bits);
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= src_data_size_in_bits);
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    uint64_t src_raw_bits = ExtractUnsignedBitfield64(src_data_size_in_bits - 1,
+                                                      0,
+                                                      src.Uint(vform, i));
+    double dst_value =
+        RawbitsWithSizeToFP<double>(src_data_size_in_bits, src_raw_bits);
+
+    uint64_t dst_raw_bits =
+        FPToRawbitsWithSize(dst_data_size_in_bits, dst_value);
+
+    dst.SetUint(vform, i, dst_raw_bits);
+  }
+
+  return dst;
+}
 
 LogicVRegister Simulator::fcvts(VectorFormat vform,
+                                unsigned dst_data_size_in_bits,
+                                unsigned src_data_size_in_bits,
                                 LogicVRegister dst,
+                                const LogicPRegister& pg,
                                 const LogicVRegister& src,
-                                FPRounding rounding_mode,
+                                FPRounding round,
                                 int fbits) {
-  dst.ClearForWrite(vform);
-  if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-      SimFloat16 op =
-          static_cast<double>(src.Float<SimFloat16>(i)) * std::pow(2.0, fbits);
-      dst.SetInt(vform, i, FPToInt16(op, rounding_mode));
-    }
-  } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
-    for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-      float op = src.Float<float>(i) * std::pow(2.0f, fbits);
-      dst.SetInt(vform, i, FPToInt32(op, rounding_mode));
-    }
-  } else {
-    VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
-    for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-      double op = src.Float<double>(i) * std::pow(2.0, fbits);
-      dst.SetInt(vform, i, FPToInt64(op, rounding_mode));
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= dst_data_size_in_bits);
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= src_data_size_in_bits);
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    uint64_t value = ExtractUnsignedBitfield64(src_data_size_in_bits - 1,
+                                               0,
+                                               src.Uint(vform, i));
+    double result = RawbitsWithSizeToFP<double>(src_data_size_in_bits, value) *
+                    std::pow(2.0, fbits);
+
+    switch (dst_data_size_in_bits) {
+      case kHRegSize:
+        dst.SetInt(vform, i, FPToInt16(result, round));
+        break;
+      case kSRegSize:
+        dst.SetInt(vform, i, FPToInt32(result, round));
+        break;
+      case kDRegSize:
+        dst.SetInt(vform, i, FPToInt64(result, round));
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
     }
   }
+
   return dst;
 }
 
+LogicVRegister Simulator::fcvts(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& src,
+                                FPRounding round,
+                                int fbits) {
+  dst.ClearForWrite(vform);
+  return fcvts(vform,
+               LaneSizeInBitsFromFormat(vform),
+               LaneSizeInBitsFromFormat(vform),
+               dst,
+               GetPTrue(),
+               src,
+               round,
+               fbits);
+}
 
 LogicVRegister Simulator::fcvtu(VectorFormat vform,
+                                unsigned dst_data_size_in_bits,
+                                unsigned src_data_size_in_bits,
                                 LogicVRegister dst,
+                                const LogicPRegister& pg,
                                 const LogicVRegister& src,
-                                FPRounding rounding_mode,
+                                FPRounding round,
                                 int fbits) {
-  dst.ClearForWrite(vform);
-  if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-    for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-      SimFloat16 op =
-          static_cast<double>(src.Float<SimFloat16>(i)) * std::pow(2.0, fbits);
-      dst.SetUint(vform, i, FPToUInt16(op, rounding_mode));
-    }
-  } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
-    for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-      float op = src.Float<float>(i) * std::pow(2.0f, fbits);
-      dst.SetUint(vform, i, FPToUInt32(op, rounding_mode));
-    }
-  } else {
-    VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
-    for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-      double op = src.Float<double>(i) * std::pow(2.0, fbits);
-      dst.SetUint(vform, i, FPToUInt64(op, rounding_mode));
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= dst_data_size_in_bits);
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= src_data_size_in_bits);
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    uint64_t value = ExtractUnsignedBitfield64(src_data_size_in_bits - 1,
+                                               0,
+                                               src.Uint(vform, i));
+    double result = RawbitsWithSizeToFP<double>(src_data_size_in_bits, value) *
+                    std::pow(2.0, fbits);
+
+    switch (dst_data_size_in_bits) {
+      case kHRegSize:
+        dst.SetUint(vform, i, FPToUInt16(result, round));
+        break;
+      case kSRegSize:
+        dst.SetUint(vform, i, FPToUInt32(result, round));
+        break;
+      case kDRegSize:
+        dst.SetUint(vform, i, FPToUInt64(result, round));
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
     }
   }
+
   return dst;
 }
 
+LogicVRegister Simulator::fcvtu(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& src,
+                                FPRounding round,
+                                int fbits) {
+  dst.ClearForWrite(vform);
+  return fcvtu(vform,
+               LaneSizeInBitsFromFormat(vform),
+               LaneSizeInBitsFromFormat(vform),
+               dst,
+               GetPTrue(),
+               src,
+               round,
+               fbits);
+}
 
 LogicVRegister Simulator::fcvtl(VectorFormat vform,
                                 LogicVRegister dst,
@@ -5208,18 +5975,18 @@ LogicVRegister Simulator::frsqrte(VectorFormat vform,
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
     for (int i = 0; i < LaneCountFromFormat(vform); i++) {
       SimFloat16 input = src.Float<SimFloat16>(i);
-      dst.SetFloat(i, FPRecipSqrtEstimate<SimFloat16>(input));
+      dst.SetFloat(vform, i, FPRecipSqrtEstimate<SimFloat16>(input));
     }
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
     for (int i = 0; i < LaneCountFromFormat(vform); i++) {
       float input = src.Float<float>(i);
-      dst.SetFloat(i, FPRecipSqrtEstimate<float>(input));
+      dst.SetFloat(vform, i, FPRecipSqrtEstimate<float>(input));
     }
   } else {
     VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
     for (int i = 0; i < LaneCountFromFormat(vform); i++) {
       double input = src.Float<double>(i);
-      dst.SetFloat(i, FPRecipSqrtEstimate<double>(input));
+      dst.SetFloat(vform, i, FPRecipSqrtEstimate<double>(input));
     }
   }
   return dst;
@@ -5354,18 +6121,18 @@ LogicVRegister Simulator::frecpe(VectorFormat vform,
   if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
     for (int i = 0; i < LaneCountFromFormat(vform); i++) {
       SimFloat16 input = src.Float<SimFloat16>(i);
-      dst.SetFloat(i, FPRecipEstimate<SimFloat16>(input, round));
+      dst.SetFloat(vform, i, FPRecipEstimate<SimFloat16>(input, round));
     }
   } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
     for (int i = 0; i < LaneCountFromFormat(vform); i++) {
       float input = src.Float<float>(i);
-      dst.SetFloat(i, FPRecipEstimate<float>(input, round));
+      dst.SetFloat(vform, i, FPRecipEstimate<float>(input, round));
     }
   } else {
     VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
     for (int i = 0; i < LaneCountFromFormat(vform); i++) {
       double input = src.Float<double>(i);
-      dst.SetFloat(i, FPRecipEstimate<double>(input, round));
+      dst.SetFloat(vform, i, FPRecipEstimate<double>(input, round));
     }
   }
   return dst;
@@ -5426,6 +6193,47 @@ LogicVRegister Simulator::urecpe(VectorFormat vform,
   return dst;
 }
 
+LogicPRegister Simulator::pfalse(LogicPRegister dst) {
+  dst.Clear();
+  return dst;
+}
+
+LogicPRegister Simulator::pfirst(LogicPRegister dst,
+                                 const LogicPRegister& pg,
+                                 const LogicPRegister& src) {
+  int first_pg = GetFirstActive(kFormatVnB, pg);
+  VIXL_ASSERT(first_pg < LaneCountFromFormat(kFormatVnB));
+  mov(dst, src);
+  if (first_pg >= 0) dst.SetActive(kFormatVnB, first_pg, true);
+  return dst;
+}
+
+LogicPRegister Simulator::ptrue(VectorFormat vform,
+                                LogicPRegister dst,
+                                int pattern) {
+  int count = GetPredicateConstraintLaneCount(vform, pattern);
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    dst.SetActive(vform, i, i < count);
+  }
+  return dst;
+}
+
+LogicPRegister Simulator::pnext(VectorFormat vform,
+                                LogicPRegister dst,
+                                const LogicPRegister& pg,
+                                const LogicPRegister& src) {
+  int next = GetLastActive(vform, src) + 1;
+  while (next < LaneCountFromFormat(vform)) {
+    if (pg.IsActive(vform, next)) break;
+    next++;
+  }
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    dst.SetActive(vform, i, (i == next));
+  }
+  return dst;
+}
+
 template <typename T>
 LogicVRegister Simulator::frecpx(VectorFormat vform,
                                  LogicVRegister dst,
@@ -5477,49 +6285,1133 @@ LogicVRegister Simulator::frecpx(VectorFormat vform,
   return dst;
 }
 
+LogicVRegister Simulator::ftsmul(VectorFormat vform,
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2) {
+  SimVRegister maybe_neg_src1;
+
+  // The bottom bit of src2 controls the sign of the result. Use it to
+  // conditionally invert the sign of one `fmul` operand.
+  shl(vform, maybe_neg_src1, src2, LaneSizeInBitsFromFormat(vform) - 1);
+  eor(vform, maybe_neg_src1, maybe_neg_src1, src1);
+
+  // Multiply src1 by the modified neg_src1, which is potentially its negation.
+  // In the case of NaNs, NaN * -NaN will return the first NaN intact, so src1,
+  // rather than neg_src1, must be the first source argument.
+  fmul(vform, dst, src1, maybe_neg_src1);
+
+  return dst;
+}
+
+LogicVRegister Simulator::ftssel(VectorFormat vform,
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2) {
+  unsigned lane_bits = LaneSizeInBitsFromFormat(vform);
+  uint64_t sign_bit = UINT64_C(1) << (lane_bits - 1);
+  uint64_t one;
+
+  if (lane_bits == kHRegSize) {
+    one = Float16ToRawbits(Float16(1.0));
+  } else if (lane_bits == kSRegSize) {
+    one = FloatToRawbits(1.0);
+  } else {
+    VIXL_ASSERT(lane_bits == kDRegSize);
+    one = DoubleToRawbits(1.0);
+  }
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    // Use integer accessors for this operation, as this is a data manipulation
+    // task requiring no calculation.
+    uint64_t op = src1.Uint(vform, i);
+
+    // Only the bottom two bits of the src2 register are significant, indicating
+    // the quadrant. Bit 0 controls whether src1 or 1.0 is written to dst. Bit 1
+    // determines the sign of the value written to dst.
+    uint64_t q = src2.Uint(vform, i);
+    if ((q & 1) == 1) op = one;
+    if ((q & 2) == 2) op ^= sign_bit;
+
+    dst.SetUint(vform, i, op);
+  }
+
+  return dst;
+}
+
+template <typename T>
+LogicVRegister Simulator::FTMaddHelper(VectorFormat vform,
+                                       LogicVRegister dst,
+                                       const LogicVRegister& src1,
+                                       const LogicVRegister& src2,
+                                       uint64_t coeff_pos,
+                                       uint64_t coeff_neg) {
+  SimVRegister zero;
+  dup_immediate(kFormatVnB, zero, 0);
+
+  SimVRegister cf;
+  SimVRegister cfn;
+  dup_immediate(vform, cf, coeff_pos);
+  dup_immediate(vform, cfn, coeff_neg);
+
+  // The specification requires testing the top bit of the raw value, rather
+  // than the sign of the floating point number, so use an integer comparison
+  // here.
+  SimPRegister is_neg;
+  SVEIntCompareVectorsHelper(lt,
+                             vform,
+                             is_neg,
+                             GetPTrue(),
+                             src2,
+                             zero,
+                             false,
+                             LeaveFlags);
+  mov_merging(vform, cf, is_neg, cfn);
+
+  SimVRegister temp;
+  fabs_<T>(vform, temp, src2);
+  fmla<T>(vform, cf, cf, src1, temp);
+  mov(vform, dst, cf);
+  return dst;
+}
+
+
+LogicVRegister Simulator::ftmad(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& src1,
+                                const LogicVRegister& src2,
+                                unsigned index) {
+  static const uint64_t ftmad_coeff16[] = {0x3c00,
+                                           0xb155,
+                                           0x2030,
+                                           0x0000,
+                                           0x0000,
+                                           0x0000,
+                                           0x0000,
+                                           0x0000,
+                                           0x3c00,
+                                           0xb800,
+                                           0x293a,
+                                           0x0000,
+                                           0x0000,
+                                           0x0000,
+                                           0x0000,
+                                           0x0000};
+
+  static const uint64_t ftmad_coeff32[] = {0x3f800000,
+                                           0xbe2aaaab,
+                                           0x3c088886,
+                                           0xb95008b9,
+                                           0x36369d6d,
+                                           0x00000000,
+                                           0x00000000,
+                                           0x00000000,
+                                           0x3f800000,
+                                           0xbf000000,
+                                           0x3d2aaaa6,
+                                           0xbab60705,
+                                           0x37cd37cc,
+                                           0x00000000,
+                                           0x00000000,
+                                           0x00000000};
+
+  static const uint64_t ftmad_coeff64[] = {0x3ff0000000000000,
+                                           0xbfc5555555555543,
+                                           0x3f8111111110f30c,
+                                           0xbf2a01a019b92fc6,
+                                           0x3ec71de351f3d22b,
+                                           0xbe5ae5e2b60f7b91,
+                                           0x3de5d8408868552f,
+                                           0x0000000000000000,
+                                           0x3ff0000000000000,
+                                           0xbfe0000000000000,
+                                           0x3fa5555555555536,
+                                           0xbf56c16c16c13a0b,
+                                           0x3efa01a019b1e8d8,
+                                           0xbe927e4f7282f468,
+                                           0x3e21ee96d2641b13,
+                                           0xbda8f76380fbb401};
+  VIXL_ASSERT((index + 8) < ArrayLength(ftmad_coeff64));
+  VIXL_ASSERT(ArrayLength(ftmad_coeff16) == ArrayLength(ftmad_coeff64));
+  VIXL_ASSERT(ArrayLength(ftmad_coeff32) == ArrayLength(ftmad_coeff64));
+
+  if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
+    FTMaddHelper<SimFloat16>(vform,
+                             dst,
+                             src1,
+                             src2,
+                             ftmad_coeff16[index],
+                             ftmad_coeff16[index + 8]);
+  } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
+    FTMaddHelper<float>(vform,
+                        dst,
+                        src1,
+                        src2,
+                        ftmad_coeff32[index],
+                        ftmad_coeff32[index + 8]);
+  } else {
+    VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
+    FTMaddHelper<double>(vform,
+                         dst,
+                         src1,
+                         src2,
+                         ftmad_coeff64[index],
+                         ftmad_coeff64[index + 8]);
+  }
+  return dst;
+}
+
+LogicVRegister Simulator::fexpa(VectorFormat vform,
+                                LogicVRegister dst,
+                                const LogicVRegister& src) {
+  static const uint64_t fexpa_coeff16[] = {0x0000, 0x0016, 0x002d, 0x0045,
+                                           0x005d, 0x0075, 0x008e, 0x00a8,
+                                           0x00c2, 0x00dc, 0x00f8, 0x0114,
+                                           0x0130, 0x014d, 0x016b, 0x0189,
+                                           0x01a8, 0x01c8, 0x01e8, 0x0209,
+                                           0x022b, 0x024e, 0x0271, 0x0295,
+                                           0x02ba, 0x02e0, 0x0306, 0x032e,
+                                           0x0356, 0x037f, 0x03a9, 0x03d4};
+
+  static const uint64_t fexpa_coeff32[] =
+      {0x000000, 0x0164d2, 0x02cd87, 0x043a29, 0x05aac3, 0x071f62, 0x08980f,
+       0x0a14d5, 0x0b95c2, 0x0d1adf, 0x0ea43a, 0x1031dc, 0x11c3d3, 0x135a2b,
+       0x14f4f0, 0x16942d, 0x1837f0, 0x19e046, 0x1b8d3a, 0x1d3eda, 0x1ef532,
+       0x20b051, 0x227043, 0x243516, 0x25fed7, 0x27cd94, 0x29a15b, 0x2b7a3a,
+       0x2d583f, 0x2f3b79, 0x3123f6, 0x3311c4, 0x3504f3, 0x36fd92, 0x38fbaf,
+       0x3aff5b, 0x3d08a4, 0x3f179a, 0x412c4d, 0x4346cd, 0x45672a, 0x478d75,
+       0x49b9be, 0x4bec15, 0x4e248c, 0x506334, 0x52a81e, 0x54f35b, 0x5744fd,
+       0x599d16, 0x5bfbb8, 0x5e60f5, 0x60ccdf, 0x633f89, 0x65b907, 0x68396a,
+       0x6ac0c7, 0x6d4f30, 0x6fe4ba, 0x728177, 0x75257d, 0x77d0df, 0x7a83b3,
+       0x7d3e0c};
+
+  static const uint64_t fexpa_coeff64[] =
+      {0X0000000000000, 0X02c9a3e778061, 0X059b0d3158574, 0X0874518759bc8,
+       0X0b5586cf9890f, 0X0e3ec32d3d1a2, 0X11301d0125b51, 0X1429aaea92de0,
+       0X172b83c7d517b, 0X1a35beb6fcb75, 0X1d4873168b9aa, 0X2063b88628cd6,
+       0X2387a6e756238, 0X26b4565e27cdd, 0X29e9df51fdee1, 0X2d285a6e4030b,
+       0X306fe0a31b715, 0X33c08b26416ff, 0X371a7373aa9cb, 0X3a7db34e59ff7,
+       0X3dea64c123422, 0X4160a21f72e2a, 0X44e086061892d, 0X486a2b5c13cd0,
+       0X4bfdad5362a27, 0X4f9b2769d2ca7, 0X5342b569d4f82, 0X56f4736b527da,
+       0X5ab07dd485429, 0X5e76f15ad2148, 0X6247eb03a5585, 0X6623882552225,
+       0X6a09e667f3bcd, 0X6dfb23c651a2f, 0X71f75e8ec5f74, 0X75feb564267c9,
+       0X7a11473eb0187, 0X7e2f336cf4e62, 0X82589994cce13, 0X868d99b4492ed,
+       0X8ace5422aa0db, 0X8f1ae99157736, 0X93737b0cdc5e5, 0X97d829fde4e50,
+       0X9c49182a3f090, 0Xa0c667b5de565, 0Xa5503b23e255d, 0Xa9e6b5579fdbf,
+       0Xae89f995ad3ad, 0Xb33a2b84f15fb, 0Xb7f76f2fb5e47, 0Xbcc1e904bc1d2,
+       0Xc199bdd85529c, 0Xc67f12e57d14b, 0Xcb720dcef9069, 0Xd072d4a07897c,
+       0Xd5818dcfba487, 0Xda9e603db3285, 0Xdfc97337b9b5f, 0Xe502ee78b3ff6,
+       0Xea4afa2a490da, 0Xefa1bee615a27, 0Xf50765b6e4540, 0Xfa7c1819e90d8};
+
+  unsigned lane_size = LaneSizeInBitsFromFormat(vform);
+  int index_highbit = 5;
+  int op_highbit, op_shift;
+  const uint64_t* fexpa_coeff;
+
+  if (lane_size == kHRegSize) {
+    index_highbit = 4;
+    VIXL_ASSERT(ArrayLength(fexpa_coeff16) == (1U << (index_highbit + 1)));
+    fexpa_coeff = fexpa_coeff16;
+    op_highbit = 9;
+    op_shift = 10;
+  } else if (lane_size == kSRegSize) {
+    VIXL_ASSERT(ArrayLength(fexpa_coeff32) == (1U << (index_highbit + 1)));
+    fexpa_coeff = fexpa_coeff32;
+    op_highbit = 13;
+    op_shift = 23;
+  } else {
+    VIXL_ASSERT(lane_size == kDRegSize);
+    VIXL_ASSERT(ArrayLength(fexpa_coeff64) == (1U << (index_highbit + 1)));
+    fexpa_coeff = fexpa_coeff64;
+    op_highbit = 16;
+    op_shift = 52;
+  }
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    uint64_t op = src.Uint(vform, i);
+    uint64_t result = fexpa_coeff[Bits(op, index_highbit, 0)];
+    result |= (Bits(op, op_highbit, index_highbit + 1) << op_shift);
+    dst.SetUint(vform, i, result);
+  }
+  return dst;
+}
+
+template <typename T>
+LogicVRegister Simulator::fscale(VectorFormat vform,
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2) {
+  T two = T(2.0);
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    T s1 = src1.Float<T>(i);
+    if (!IsNaN(s1)) {
+      int64_t scale = src2.Int(vform, i);
+      // TODO: this is a low-performance implementation, but it's simple and
+      // less likely to be buggy. Consider replacing it with something faster.
+
+      // Scales outside of these bounds become infinity or zero, so there's no
+      // point iterating further.
+      scale = std::min<int64_t>(std::max<int64_t>(scale, -2048), 2048);
+
+      // Compute s1 * 2 ^ scale. If scale is positive, multiply by two and
+      // decrement scale until it's zero.
+      while (scale-- > 0) {
+        s1 = FPMul(s1, two);
+      }
+
+      // If scale is negative, divide by two and increment scale until it's
+      // zero. Initially, scale is (src2 - 1), so we pre-increment.
+      while (++scale < 0) {
+        s1 = FPDiv(s1, two);
+      }
+    }
+    dst.SetFloat<T>(i, s1);
+  }
+  return dst;
+}
+
+LogicVRegister Simulator::fscale(VectorFormat vform,
+                                 LogicVRegister dst,
+                                 const LogicVRegister& src1,
+                                 const LogicVRegister& src2) {
+  if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
+    fscale<SimFloat16>(vform, dst, src1, src2);
+  } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
+    fscale<float>(vform, dst, src1, src2);
+  } else {
+    VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
+    fscale<double>(vform, dst, src1, src2);
+  }
+  return dst;
+}
+
+LogicVRegister Simulator::scvtf(VectorFormat vform,
+                                unsigned dst_data_size_in_bits,
+                                unsigned src_data_size_in_bits,
+                                LogicVRegister dst,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src,
+                                FPRounding round,
+                                int fbits) {
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= dst_data_size_in_bits);
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= src_data_size_in_bits);
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    int64_t value = ExtractSignedBitfield64(src_data_size_in_bits - 1,
+                                            0,
+                                            src.Uint(vform, i));
+
+    switch (dst_data_size_in_bits) {
+      case kHRegSize: {
+        SimFloat16 result = FixedToFloat16(value, fbits, round);
+        dst.SetUint(vform, i, Float16ToRawbits(result));
+        break;
+      }
+      case kSRegSize: {
+        float result = FixedToFloat(value, fbits, round);
+        dst.SetUint(vform, i, FloatToRawbits(result));
+        break;
+      }
+      case kDRegSize: {
+        double result = FixedToDouble(value, fbits, round);
+        dst.SetUint(vform, i, DoubleToRawbits(result));
+        break;
+      }
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  }
+
+  return dst;
+}
+
 LogicVRegister Simulator::scvtf(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src,
                                 int fbits,
                                 FPRounding round) {
+  return scvtf(vform,
+               LaneSizeInBitsFromFormat(vform),
+               LaneSizeInBitsFromFormat(vform),
+               dst,
+               GetPTrue(),
+               src,
+               round,
+               fbits);
+}
+
+LogicVRegister Simulator::ucvtf(VectorFormat vform,
+                                unsigned dst_data_size_in_bits,
+                                unsigned src_data_size_in_bits,
+                                LogicVRegister dst,
+                                const LogicPRegister& pg,
+                                const LogicVRegister& src,
+                                FPRounding round,
+                                int fbits) {
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= dst_data_size_in_bits);
+  VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) >= src_data_size_in_bits);
+
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-      SimFloat16 result = FixedToFloat16(src.Int(kFormatH, i), fbits, round);
-      dst.SetFloat<SimFloat16>(i, result);
-    } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
-      float result = FixedToFloat(src.Int(kFormatS, i), fbits, round);
-      dst.SetFloat<float>(i, result);
-    } else {
-      VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
-      double result = FixedToDouble(src.Int(kFormatD, i), fbits, round);
-      dst.SetFloat<double>(i, result);
+    if (!pg.IsActive(vform, i)) continue;
+
+    uint64_t value = ExtractUnsignedBitfield64(src_data_size_in_bits - 1,
+                                               0,
+                                               src.Uint(vform, i));
+
+    switch (dst_data_size_in_bits) {
+      case kHRegSize: {
+        SimFloat16 result = UFixedToFloat16(value, fbits, round);
+        dst.SetUint(vform, i, Float16ToRawbits(result));
+        break;
+      }
+      case kSRegSize: {
+        float result = UFixedToFloat(value, fbits, round);
+        dst.SetUint(vform, i, FloatToRawbits(result));
+        break;
+      }
+      case kDRegSize: {
+        double result = UFixedToDouble(value, fbits, round);
+        dst.SetUint(vform, i, DoubleToRawbits(result));
+        break;
+      }
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
     }
   }
+
   return dst;
 }
 
-
 LogicVRegister Simulator::ucvtf(VectorFormat vform,
                                 LogicVRegister dst,
                                 const LogicVRegister& src,
                                 int fbits,
                                 FPRounding round) {
+  return ucvtf(vform,
+               LaneSizeInBitsFromFormat(vform),
+               LaneSizeInBitsFromFormat(vform),
+               dst,
+               GetPTrue(),
+               src,
+               round,
+               fbits);
+}
+
+LogicVRegister Simulator::unpk(VectorFormat vform,
+                               LogicVRegister dst,
+                               const LogicVRegister& src,
+                               UnpackType unpack_type,
+                               ExtendType extend_type) {
+  VectorFormat vform_half = VectorFormatHalfWidth(vform);
+  const int lane_count = LaneCountFromFormat(vform);
+  const int src_start_lane = (unpack_type == kLoHalf) ? 0 : lane_count;
+
+  switch (extend_type) {
+    case kSignedExtend: {
+      int64_t result[kZRegMaxSizeInBytes];
+      for (int i = 0; i < lane_count; ++i) {
+        result[i] = src.Int(vform_half, i + src_start_lane);
+      }
+      for (int i = 0; i < lane_count; ++i) {
+        dst.SetInt(vform, i, result[i]);
+      }
+      break;
+    }
+    case kUnsignedExtend: {
+      uint64_t result[kZRegMaxSizeInBytes];
+      for (int i = 0; i < lane_count; ++i) {
+        result[i] = src.Uint(vform_half, i + src_start_lane);
+      }
+      for (int i = 0; i < lane_count; ++i) {
+        dst.SetUint(vform, i, result[i]);
+      }
+      break;
+    }
+    default:
+      VIXL_UNREACHABLE();
+  }
+  return dst;
+}
+
+LogicPRegister Simulator::SVEIntCompareVectorsHelper(Condition cond,
+                                                     VectorFormat vform,
+                                                     LogicPRegister dst,
+                                                     const LogicPRegister& mask,
+                                                     const LogicVRegister& src1,
+                                                     const LogicVRegister& src2,
+                                                     bool is_wide_elements,
+                                                     FlagsUpdate flags) {
+  for (int lane = 0; lane < LaneCountFromFormat(vform); lane++) {
+    bool result = false;
+    if (mask.IsActive(vform, lane)) {
+      int64_t op1 = 0xbadbeef;
+      int64_t op2 = 0xbadbeef;
+      int d_lane = (lane * LaneSizeInBitsFromFormat(vform)) / kDRegSize;
+      switch (cond) {
+        case eq:
+        case ge:
+        case gt:
+        case lt:
+        case le:
+        case ne:
+          op1 = src1.Int(vform, lane);
+          op2 = is_wide_elements ? src2.Int(kFormatVnD, d_lane)
+                                 : src2.Int(vform, lane);
+          break;
+        case hi:
+        case hs:
+        case ls:
+        case lo:
+          op1 = src1.Uint(vform, lane);
+          op2 = is_wide_elements ? src2.Uint(kFormatVnD, d_lane)
+                                 : src2.Uint(vform, lane);
+          break;
+        default:
+          VIXL_UNREACHABLE();
+      }
+
+      switch (cond) {
+        case eq:
+          result = (op1 == op2);
+          break;
+        case ne:
+          result = (op1 != op2);
+          break;
+        case ge:
+          result = (op1 >= op2);
+          break;
+        case gt:
+          result = (op1 > op2);
+          break;
+        case le:
+          result = (op1 <= op2);
+          break;
+        case lt:
+          result = (op1 < op2);
+          break;
+        case hs:
+          result = (static_cast<uint64_t>(op1) >= static_cast<uint64_t>(op2));
+          break;
+        case hi:
+          result = (static_cast<uint64_t>(op1) > static_cast<uint64_t>(op2));
+          break;
+        case ls:
+          result = (static_cast<uint64_t>(op1) <= static_cast<uint64_t>(op2));
+          break;
+        case lo:
+          result = (static_cast<uint64_t>(op1) < static_cast<uint64_t>(op2));
+          break;
+        default:
+          VIXL_UNREACHABLE();
+      }
+    }
+    dst.SetActive(vform, lane, result);
+  }
+
+  if (flags == SetFlags) PredTest(vform, mask, dst);
+
+  return dst;
+}
+
+LogicVRegister Simulator::SVEBitwiseShiftHelper(Shift shift_op,
+                                                VectorFormat vform,
+                                                LogicVRegister dst,
+                                                const LogicVRegister& src1,
+                                                const LogicVRegister& src2,
+                                                bool is_wide_elements) {
+  unsigned lane_size = LaneSizeInBitsFromFormat(vform);
+  VectorFormat shift_vform = is_wide_elements ? kFormatVnD : vform;
+
+  for (int lane = 0; lane < LaneCountFromFormat(vform); lane++) {
+    int shift_src_lane = lane;
+    if (is_wide_elements) {
+      // If the shift amount comes from wide elements, select the D-sized lane
+      // which occupies the corresponding lanes of the value to be shifted.
+      shift_src_lane = (lane * lane_size) / kDRegSize;
+    }
+    uint64_t shift_amount = src2.Uint(shift_vform, shift_src_lane);
+
+    // Saturate shift_amount to the size of the lane that will be shifted.
+    if (shift_amount > lane_size) shift_amount = lane_size;
+
+    uint64_t value = src1.Uint(vform, lane);
+    int64_t result = ShiftOperand(lane_size,
+                                  value,
+                                  shift_op,
+                                  static_cast<unsigned>(shift_amount));
+    dst.SetUint(vform, lane, result);
+  }
+
+  return dst;
+}
+
+LogicVRegister Simulator::asrd(VectorFormat vform,
+                               LogicVRegister dst,
+                               const LogicVRegister& src1,
+                               int shift) {
+  VIXL_ASSERT((shift > 0) && (static_cast<unsigned>(shift) <=
+                              LaneSizeInBitsFromFormat(vform)));
+
   for (int i = 0; i < LaneCountFromFormat(vform); i++) {
-    if (LaneSizeInBitsFromFormat(vform) == kHRegSize) {
-      SimFloat16 result = UFixedToFloat16(src.Uint(kFormatH, i), fbits, round);
-      dst.SetFloat<SimFloat16>(i, result);
-    } else if (LaneSizeInBitsFromFormat(vform) == kSRegSize) {
-      float result = UFixedToFloat(src.Uint(kFormatS, i), fbits, round);
-      dst.SetFloat<float>(i, result);
+    int64_t value = src1.Int(vform, i);
+    if (shift <= 63) {
+      if (value < 0) {
+        // The max possible mask is 0x7fff'ffff'ffff'ffff, which can be safely
+        // cast to int64_t, and cannot cause signed overflow in the result.
+        value = value + GetUintMask(shift);
+      }
+      value = ShiftOperand(kDRegSize, value, ASR, shift);
     } else {
-      VIXL_ASSERT(LaneSizeInBitsFromFormat(vform) == kDRegSize);
-      double result = UFixedToDouble(src.Uint(kFormatD, i), fbits, round);
-      dst.SetFloat<double>(i, result);
+      value = 0;
     }
+    dst.SetInt(vform, i, value);
   }
   return dst;
 }
 
+LogicVRegister Simulator::SVEBitwiseLogicalUnpredicatedHelper(
+    LogicalOp logical_op,
+    VectorFormat vform,
+    LogicVRegister zd,
+    const LogicVRegister& zn,
+    const LogicVRegister& zm) {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    uint64_t op1 = zn.Uint(vform, i);
+    uint64_t op2 = zm.Uint(vform, i);
+    uint64_t result;
+    switch (logical_op) {
+      case AND:
+        result = op1 & op2;
+        break;
+      case BIC:
+        result = op1 & ~op2;
+        break;
+      case EOR:
+        result = op1 ^ op2;
+        break;
+      case ORR:
+        result = op1 | op2;
+        break;
+      default:
+        result = 0;
+        VIXL_UNIMPLEMENTED();
+    }
+    zd.SetUint(vform, i, result);
+  }
+
+  return zd;
+}
+
+LogicPRegister Simulator::SVEPredicateLogicalHelper(SVEPredicateLogicalOp op,
+                                                    LogicPRegister pd,
+                                                    const LogicPRegister& pn,
+                                                    const LogicPRegister& pm) {
+  for (int i = 0; i < pn.GetChunkCount(); i++) {
+    LogicPRegister::ChunkType op1 = pn.GetChunk(i);
+    LogicPRegister::ChunkType op2 = pm.GetChunk(i);
+    LogicPRegister::ChunkType result;
+    switch (op) {
+      case ANDS_p_p_pp_z:
+      case AND_p_p_pp_z:
+        result = op1 & op2;
+        break;
+      case BICS_p_p_pp_z:
+      case BIC_p_p_pp_z:
+        result = op1 & ~op2;
+        break;
+      case EORS_p_p_pp_z:
+      case EOR_p_p_pp_z:
+        result = op1 ^ op2;
+        break;
+      case NANDS_p_p_pp_z:
+      case NAND_p_p_pp_z:
+        result = ~(op1 & op2);
+        break;
+      case NORS_p_p_pp_z:
+      case NOR_p_p_pp_z:
+        result = ~(op1 | op2);
+        break;
+      case ORNS_p_p_pp_z:
+      case ORN_p_p_pp_z:
+        result = op1 | ~op2;
+        break;
+      case ORRS_p_p_pp_z:
+      case ORR_p_p_pp_z:
+        result = op1 | op2;
+        break;
+      default:
+        result = 0;
+        VIXL_UNIMPLEMENTED();
+    }
+    pd.SetChunk(i, result);
+  }
+  return pd;
+}
+
+LogicVRegister Simulator::SVEBitwiseImmHelper(
+    SVEBitwiseLogicalWithImm_UnpredicatedOp op,
+    VectorFormat vform,
+    LogicVRegister zd,
+    uint64_t imm) {
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    uint64_t op1 = zd.Uint(vform, i);
+    uint64_t result;
+    switch (op) {
+      case AND_z_zi:
+        result = op1 & imm;
+        break;
+      case EOR_z_zi:
+        result = op1 ^ imm;
+        break;
+      case ORR_z_zi:
+        result = op1 | imm;
+        break;
+      default:
+        result = 0;
+        VIXL_UNIMPLEMENTED();
+    }
+    zd.SetUint(vform, i, result);
+  }
+
+  return zd;
+}
+
+void Simulator::SVEStructuredStoreHelper(VectorFormat vform,
+                                         const LogicPRegister& pg,
+                                         unsigned zt_code,
+                                         const LogicSVEAddressVector& addr) {
+  VIXL_ASSERT(zt_code < kNumberOfZRegisters);
+
+  int esize_in_bytes_log2 = LaneSizeInBytesLog2FromFormat(vform);
+  int msize_in_bytes_log2 = addr.GetMsizeInBytesLog2();
+  int msize_in_bytes = addr.GetMsizeInBytes();
+  int reg_count = addr.GetRegCount();
+
+  VIXL_ASSERT(esize_in_bytes_log2 >= msize_in_bytes_log2);
+  VIXL_ASSERT((reg_count >= 1) && (reg_count <= 4));
+
+  unsigned zt_codes[4] = {zt_code,
+                          (zt_code + 1) % kNumberOfZRegisters,
+                          (zt_code + 2) % kNumberOfZRegisters,
+                          (zt_code + 3) % kNumberOfZRegisters};
+
+  LogicVRegister zt[4] = {
+      ReadVRegister(zt_codes[0]),
+      ReadVRegister(zt_codes[1]),
+      ReadVRegister(zt_codes[2]),
+      ReadVRegister(zt_codes[3]),
+  };
+
+  // For unpacked forms (e.g. `st1b { z0.h }, ...`, the upper parts of the lanes
+  // are ignored, so read the source register using the VectorFormat that
+  // corresponds with the storage format, and multiply the index accordingly.
+  VectorFormat unpack_vform =
+      SVEFormatFromLaneSizeInBytesLog2(msize_in_bytes_log2);
+  int unpack_shift = esize_in_bytes_log2 - msize_in_bytes_log2;
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (!pg.IsActive(vform, i)) continue;
+
+    for (int r = 0; r < reg_count; r++) {
+      uint64_t element_address = addr.GetElementAddress(i, r);
+      StoreLane(zt[r], unpack_vform, i << unpack_shift, element_address);
+    }
+  }
+
+  if (ShouldTraceWrites()) {
+    PrintRegisterFormat format = GetPrintRegisterFormat(vform);
+    if (esize_in_bytes_log2 == msize_in_bytes_log2) {
+      // Use an FP format where it's likely that we're accessing FP data.
+      format = GetPrintRegisterFormatTryFP(format);
+    }
+    // Stores don't represent a change to the source register's value, so only
+    // print the relevant part of the value.
+    format = GetPrintRegPartial(format);
+
+    PrintZStructAccess(zt_code,
+                       reg_count,
+                       pg,
+                       format,
+                       msize_in_bytes,
+                       "->",
+                       addr);
+  }
+}
+
+void Simulator::SVEStructuredLoadHelper(VectorFormat vform,
+                                        const LogicPRegister& pg,
+                                        unsigned zt_code,
+                                        const LogicSVEAddressVector& addr,
+                                        bool is_signed) {
+  int esize_in_bytes_log2 = LaneSizeInBytesLog2FromFormat(vform);
+  int msize_in_bytes_log2 = addr.GetMsizeInBytesLog2();
+  int msize_in_bytes = addr.GetMsizeInBytes();
+  int reg_count = addr.GetRegCount();
+
+  VIXL_ASSERT(zt_code < kNumberOfZRegisters);
+  VIXL_ASSERT(esize_in_bytes_log2 >= msize_in_bytes_log2);
+  VIXL_ASSERT((reg_count >= 1) && (reg_count <= 4));
+
+  unsigned zt_codes[4] = {zt_code,
+                          (zt_code + 1) % kNumberOfZRegisters,
+                          (zt_code + 2) % kNumberOfZRegisters,
+                          (zt_code + 3) % kNumberOfZRegisters};
+  LogicVRegister zt[4] = {
+      ReadVRegister(zt_codes[0]),
+      ReadVRegister(zt_codes[1]),
+      ReadVRegister(zt_codes[2]),
+      ReadVRegister(zt_codes[3]),
+  };
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    for (int r = 0; r < reg_count; r++) {
+      uint64_t element_address = addr.GetElementAddress(i, r);
+
+      if (!pg.IsActive(vform, i)) {
+        zt[r].SetUint(vform, i, 0);
+        continue;
+      }
+
+      if (is_signed) {
+        LoadIntToLane(zt[r], vform, msize_in_bytes, i, element_address);
+      } else {
+        LoadUintToLane(zt[r], vform, msize_in_bytes, i, element_address);
+      }
+    }
+  }
+
+  if (ShouldTraceVRegs()) {
+    PrintRegisterFormat format = GetPrintRegisterFormat(vform);
+    if ((esize_in_bytes_log2 == msize_in_bytes_log2) && !is_signed) {
+      // Use an FP format where it's likely that we're accessing FP data.
+      format = GetPrintRegisterFormatTryFP(format);
+    }
+    PrintZStructAccess(zt_code,
+                       reg_count,
+                       pg,
+                       format,
+                       msize_in_bytes,
+                       "<-",
+                       addr);
+  }
+}
+
+LogicPRegister Simulator::brka(LogicPRegister pd,
+                               const LogicPRegister& pg,
+                               const LogicPRegister& pn) {
+  bool break_ = false;
+  for (int i = 0; i < LaneCountFromFormat(kFormatVnB); i++) {
+    if (pg.IsActive(kFormatVnB, i)) {
+      pd.SetActive(kFormatVnB, i, !break_);
+      break_ |= pn.IsActive(kFormatVnB, i);
+    }
+  }
+
+  return pd;
+}
+
+LogicPRegister Simulator::brkb(LogicPRegister pd,
+                               const LogicPRegister& pg,
+                               const LogicPRegister& pn) {
+  bool break_ = false;
+  for (int i = 0; i < LaneCountFromFormat(kFormatVnB); i++) {
+    if (pg.IsActive(kFormatVnB, i)) {
+      break_ |= pn.IsActive(kFormatVnB, i);
+      pd.SetActive(kFormatVnB, i, !break_);
+    }
+  }
+
+  return pd;
+}
+
+LogicPRegister Simulator::brkn(LogicPRegister pdm,
+                               const LogicPRegister& pg,
+                               const LogicPRegister& pn) {
+  if (!IsLastActive(kFormatVnB, pg, pn)) {
+    pfalse(pdm);
+  }
+  return pdm;
+}
+
+LogicPRegister Simulator::brkpa(LogicPRegister pd,
+                                const LogicPRegister& pg,
+                                const LogicPRegister& pn,
+                                const LogicPRegister& pm) {
+  bool last_active = IsLastActive(kFormatVnB, pg, pn);
+
+  for (int i = 0; i < LaneCountFromFormat(kFormatVnB); i++) {
+    bool active = false;
+    if (pg.IsActive(kFormatVnB, i)) {
+      active = last_active;
+      last_active = last_active && !pm.IsActive(kFormatVnB, i);
+    }
+    pd.SetActive(kFormatVnB, i, active);
+  }
+
+  return pd;
+}
+
+LogicPRegister Simulator::brkpb(LogicPRegister pd,
+                                const LogicPRegister& pg,
+                                const LogicPRegister& pn,
+                                const LogicPRegister& pm) {
+  bool last_active = IsLastActive(kFormatVnB, pg, pn);
+
+  for (int i = 0; i < LaneCountFromFormat(kFormatVnB); i++) {
+    bool active = false;
+    if (pg.IsActive(kFormatVnB, i)) {
+      last_active = last_active && !pm.IsActive(kFormatVnB, i);
+      active = last_active;
+    }
+    pd.SetActive(kFormatVnB, i, active);
+  }
+
+  return pd;
+}
+
+void Simulator::SVEFaultTolerantLoadHelper(VectorFormat vform,
+                                           const LogicPRegister& pg,
+                                           unsigned zt_code,
+                                           const LogicSVEAddressVector& addr,
+                                           SVEFaultTolerantLoadType type,
+                                           bool is_signed) {
+  int esize_in_bytes = LaneSizeInBytesFromFormat(vform);
+  int msize_in_bits = addr.GetMsizeInBits();
+  int msize_in_bytes = addr.GetMsizeInBytes();
+
+  VIXL_ASSERT(zt_code < kNumberOfZRegisters);
+  VIXL_ASSERT(esize_in_bytes >= msize_in_bytes);
+  VIXL_ASSERT(addr.GetRegCount() == 1);
+
+  LogicVRegister zt = ReadVRegister(zt_code);
+  LogicPRegister ffr = ReadFFR();
+
+  // Non-faulting loads are allowed to fail arbitrarily. To stress user
+  // code, fail a random element in roughly one in eight full-vector loads.
+  uint32_t rnd = static_cast<uint32_t>(jrand48(rand_state_));
+  int fake_fault_at_lane = rnd % (LaneCountFromFormat(vform) * 8);
+
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    uint64_t value = 0;
+
+    if (pg.IsActive(vform, i)) {
+      uint64_t element_address = addr.GetElementAddress(i, 0);
+
+      if (type == kSVEFirstFaultLoad) {
+        // First-faulting loads always load the first active element, regardless
+        // of FFR. The result will be discarded if its FFR lane is inactive, but
+        // it could still generate a fault.
+        value = MemReadUint(msize_in_bytes, element_address);
+        // All subsequent elements have non-fault semantics.
+        type = kSVENonFaultLoad;
+
+      } else if (ffr.IsActive(vform, i)) {
+        // Simulation of fault-tolerant loads relies on system calls, and is
+        // likely to be relatively slow, so we only actually perform the load if
+        // its FFR lane is active.
+
+        bool can_read = (i < fake_fault_at_lane) &&
+                        CanReadMemory(element_address, msize_in_bytes);
+        if (can_read) {
+          value = MemReadUint(msize_in_bytes, element_address);
+        } else {
+          // Propagate the fault to the end of FFR.
+          for (int j = i; j < LaneCountFromFormat(vform); j++) {
+            ffr.SetActive(vform, j, false);
+          }
+        }
+      }
+    }
+
+    // The architecture permits a few possible results for inactive FFR lanes
+    // (including those caused by a fault in this instruction). We choose to
+    // leave the register value unchanged (like merging predication) because
+    // no other input to this instruction can have the same behaviour.
+    //
+    // Note that this behaviour takes precedence over pg's zeroing predication.
+
+    if (ffr.IsActive(vform, i)) {
+      int msb = msize_in_bits - 1;
+      if (is_signed) {
+        zt.SetInt(vform, i, ExtractSignedBitfield64(msb, 0, value));
+      } else {
+        zt.SetUint(vform, i, ExtractUnsignedBitfield64(msb, 0, value));
+      }
+    }
+  }
+
+  if (ShouldTraceVRegs()) {
+    PrintRegisterFormat format = GetPrintRegisterFormat(vform);
+    if ((esize_in_bytes == msize_in_bytes) && !is_signed) {
+      // Use an FP format where it's likely that we're accessing FP data.
+      format = GetPrintRegisterFormatTryFP(format);
+    }
+    // Log accessed lanes that are active in both pg and ffr. PrintZStructAccess
+    // expects a single mask, so combine the two predicates.
+    SimPRegister mask;
+    SVEPredicateLogicalHelper(AND_p_p_pp_z, mask, pg, ffr);
+    PrintZStructAccess(zt_code, 1, mask, format, msize_in_bytes, "<-", addr);
+  }
+}
+
+void Simulator::SVEGatherLoadScalarPlusVectorHelper(const Instruction* instr,
+                                                    VectorFormat vform,
+                                                    SVEOffsetModifier mod) {
+  bool is_signed = instr->ExtractBit(14) == 0;
+  bool is_ff = instr->ExtractBit(13) == 1;
+  // Note that these instructions don't use the Dtype encoding.
+  int msize_in_bytes_log2 = instr->ExtractBits(24, 23);
+  int scale = instr->ExtractBit(21) * msize_in_bytes_log2;
+  uint64_t base = ReadXRegister(instr->GetRn());
+  LogicSVEAddressVector addr(base,
+                             &ReadVRegister(instr->GetRm()),
+                             vform,
+                             mod,
+                             scale);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  if (is_ff) {
+    SVEFaultTolerantLoadHelper(vform,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr,
+                               kSVEFirstFaultLoad,
+                               is_signed);
+  } else {
+    SVEStructuredLoadHelper(vform,
+                            ReadPRegister(instr->GetPgLow8()),
+                            instr->GetRt(),
+                            addr,
+                            is_signed);
+  }
+}
+
+int Simulator::GetFirstActive(VectorFormat vform,
+                              const LogicPRegister& pg) const {
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    if (pg.IsActive(vform, i)) return i;
+  }
+  return -1;
+}
+
+int Simulator::GetLastActive(VectorFormat vform,
+                             const LogicPRegister& pg) const {
+  for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) {
+    if (pg.IsActive(vform, i)) return i;
+  }
+  return -1;
+}
+
+int Simulator::CountActiveLanes(VectorFormat vform,
+                                const LogicPRegister& pg) const {
+  int count = 0;
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    count += pg.IsActive(vform, i) ? 1 : 0;
+  }
+  return count;
+}
+
+int Simulator::CountActiveAndTrueLanes(VectorFormat vform,
+                                       const LogicPRegister& pg,
+                                       const LogicPRegister& pn) const {
+  int count = 0;
+  for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+    count += (pg.IsActive(vform, i) && pn.IsActive(vform, i)) ? 1 : 0;
+  }
+  return count;
+}
+
+int Simulator::GetPredicateConstraintLaneCount(VectorFormat vform,
+                                               int pattern) const {
+  VIXL_ASSERT(IsSVEFormat(vform));
+  int all = LaneCountFromFormat(vform);
+  VIXL_ASSERT(all > 0);
+
+  switch (pattern) {
+    case SVE_VL1:
+    case SVE_VL2:
+    case SVE_VL3:
+    case SVE_VL4:
+    case SVE_VL5:
+    case SVE_VL6:
+    case SVE_VL7:
+    case SVE_VL8:
+      // VL1-VL8 are encoded directly.
+      VIXL_STATIC_ASSERT(SVE_VL1 == 1);
+      VIXL_STATIC_ASSERT(SVE_VL8 == 8);
+      return (pattern <= all) ? pattern : 0;
+    case SVE_VL16:
+    case SVE_VL32:
+    case SVE_VL64:
+    case SVE_VL128:
+    case SVE_VL256: {
+      // VL16-VL256 are encoded as log2(N) + c.
+      int min = 16 << (pattern - SVE_VL16);
+      return (min <= all) ? min : 0;
+    }
+    // Special cases.
+    case SVE_POW2:
+      return 1 << HighestSetBitPosition(all);
+    case SVE_MUL4:
+      return all - (all % 4);
+    case SVE_MUL3:
+      return all - (all % 3);
+    case SVE_ALL:
+      return all;
+  }
+  // Unnamed cases archicturally return 0.
+  return 0;
+}
+
+uint64_t LogicSVEAddressVector::GetStructAddress(int lane) const {
+  if (IsContiguous()) {
+    return base_ + (lane * GetRegCount()) * GetMsizeInBytes();
+  }
+
+  VIXL_ASSERT(IsScatterGather());
+  VIXL_ASSERT(vector_ != NULL);
+
+  // For scatter-gather accesses, we need to extract the offset from vector_,
+  // and apply modifiers.
+
+  uint64_t offset = 0;
+  switch (vector_form_) {
+    case kFormatVnS:
+      offset = vector_->GetLane<uint32_t>(lane);
+      break;
+    case kFormatVnD:
+      offset = vector_->GetLane<uint64_t>(lane);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  switch (vector_mod_) {
+    case SVE_MUL_VL:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case SVE_LSL:
+      // We apply the shift below. There's nothing to do here.
+      break;
+    case NO_SVE_OFFSET_MODIFIER:
+      VIXL_ASSERT(vector_shift_ == 0);
+      break;
+    case SVE_UXTW:
+      offset = ExtractUnsignedBitfield64(kWRegSize - 1, 0, offset);
+      break;
+    case SVE_SXTW:
+      offset = ExtractSignedBitfield64(kWRegSize - 1, 0, offset);
+      break;
+  }
+
+  return base_ + (offset << vector_shift_);
+}
+
 
 }  // namespace aarch64
 }  // namespace vixl
diff --git a/src/aarch64/macro-assembler-aarch64.cc b/src/aarch64/macro-assembler-aarch64.cc
index 85954fc9..56c6eaf6 100644
--- a/src/aarch64/macro-assembler-aarch64.cc
+++ b/src/aarch64/macro-assembler-aarch64.cc
@@ -65,7 +65,7 @@ LiteralPool::~LiteralPool() VIXL_NEGATIVE_TESTING_ALLOW_EXCEPTION {
 
 
 void LiteralPool::Reset() {
-  std::vector<RawLiteral *>::iterator it, end;
+  std::vector<RawLiteral*>::iterator it, end;
   for (it = entries_.begin(), end = entries_.end(); it != end; ++it) {
     RawLiteral* literal = *it;
     if (literal->deletion_policy_ == RawLiteral::kDeletedOnPlacementByPool) {
@@ -145,7 +145,7 @@ void LiteralPool::Emit(EmitOption option) {
     }
 
     // Now populate the literal pool.
-    std::vector<RawLiteral *>::iterator it, end;
+    std::vector<RawLiteral*>::iterator it, end;
     for (it = entries_.begin(), end = entries_.end(); it != end; ++it) {
       VIXL_ASSERT((*it)->IsUsed());
       masm_->place(*it);
@@ -321,11 +321,13 @@ MacroAssembler::MacroAssembler(PositionIndependentCodeOption pic)
       generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE),
       sp_(sp),
       tmp_list_(ip0, ip1),
-      fptmp_list_(d31),
+      v_tmp_list_(d31),
+      p_tmp_list_(CPURegList::Empty(CPURegister::kPRegister)),
       current_scratch_scope_(NULL),
       literal_pool_(this),
       veneer_pool_(this),
-      recommended_checkpoint_(Pool::kNoCheckpointRequired) {
+      recommended_checkpoint_(Pool::kNoCheckpointRequired),
+      fp_nan_propagation_(NoFPMacroNaNPropagationSelected) {
   checkpoint_ = GetNextCheckPoint();
 #ifndef VIXL_DEBUG
   USE(allow_macro_instructions_);
@@ -342,11 +344,13 @@ MacroAssembler::MacroAssembler(size_t capacity,
       generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE),
       sp_(sp),
       tmp_list_(ip0, ip1),
-      fptmp_list_(d31),
+      v_tmp_list_(d31),
+      p_tmp_list_(CPURegList::Empty(CPURegister::kPRegister)),
       current_scratch_scope_(NULL),
       literal_pool_(this),
       veneer_pool_(this),
-      recommended_checkpoint_(Pool::kNoCheckpointRequired) {
+      recommended_checkpoint_(Pool::kNoCheckpointRequired),
+      fp_nan_propagation_(NoFPMacroNaNPropagationSelected) {
   checkpoint_ = GetNextCheckPoint();
 }
 
@@ -361,11 +365,13 @@ MacroAssembler::MacroAssembler(byte* buffer,
       generate_simulator_code_(VIXL_AARCH64_GENERATE_SIMULATOR_CODE),
       sp_(sp),
       tmp_list_(ip0, ip1),
-      fptmp_list_(d31),
+      v_tmp_list_(d31),
+      p_tmp_list_(CPURegList::Empty(CPURegister::kPRegister)),
       current_scratch_scope_(NULL),
       literal_pool_(this),
       veneer_pool_(this),
-      recommended_checkpoint_(Pool::kNoCheckpointRequired) {
+      recommended_checkpoint_(Pool::kNoCheckpointRequired),
+      fp_nan_propagation_(NoFPMacroNaNPropagationSelected) {
   checkpoint_ = GetNextCheckPoint();
 }
 
@@ -819,6 +825,12 @@ void MacroAssembler::LogicalMacro(const Register& rd,
   //  * 1 instruction to move to sp
   MacroEmissionCheckScope guard(this);
   UseScratchRegisterScope temps(this);
+  // Use `rd` as a temp, if we can.
+  temps.Include(rd);
+  // We read `rn` after evaluating `operand`.
+  temps.Exclude(rn);
+  // It doesn't matter if `operand` is in `temps` (e.g. because it alises `rd`)
+  // because we don't need it after it is evaluated.
 
   if (operand.IsImmediate()) {
     uint64_t immediate = operand.GetImmediate();
@@ -886,6 +898,7 @@ void MacroAssembler::LogicalMacro(const Register& rd,
     } else {
       // Immediate can't be encoded: synthesize using move immediate.
       Register temp = temps.AcquireSameSizeAs(rn);
+      VIXL_ASSERT(!temp.Aliases(rn));
 
       // If the left-hand input is the stack pointer, we can't pre-shift the
       // immediate, as the encoding won't allow the subsequent post shift.
@@ -910,8 +923,8 @@ void MacroAssembler::LogicalMacro(const Register& rd,
         operand.GetRegister().Is64Bits() ||
         ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX)));
 
-    temps.Exclude(operand.GetRegister());
     Register temp = temps.AcquireSameSizeAs(rn);
+    VIXL_ASSERT(!temp.Aliases(rn));
     EmitExtendShift(temp,
                     operand.GetRegister(),
                     operand.GetExtend(),
@@ -1139,17 +1152,13 @@ void MacroAssembler::Mvn(const Register& rd, const Operand& operand) {
     // Call the macro assembler for generic immediates.
     Mvn(rd, operand.GetImmediate());
   } else if (operand.IsExtendedRegister()) {
-    UseScratchRegisterScope temps(this);
-    temps.Exclude(operand.GetRegister());
-
     // Emit two instructions for the extend case. This differs from Mov, as
     // the extend and invert can't be achieved in one instruction.
-    Register temp = temps.AcquireSameSizeAs(rd);
-    EmitExtendShift(temp,
+    EmitExtendShift(rd,
                     operand.GetRegister(),
                     operand.GetExtend(),
                     operand.GetShiftAmount());
-    mvn(rd, Operand(temp));
+    mvn(rd, rd);
   } else {
     // Otherwise, register and shifted register cases can be handled by the
     // assembler directly, using orn.
@@ -1418,12 +1427,15 @@ void MacroAssembler::Add(const Register& rd,
                          const Operand& operand,
                          FlagsUpdate S) {
   VIXL_ASSERT(allow_macro_instructions_);
-  if (operand.IsImmediate() && (operand.GetImmediate() < 0) &&
-      IsImmAddSub(-operand.GetImmediate())) {
-    AddSubMacro(rd, rn, -operand.GetImmediate(), S, SUB);
-  } else {
-    AddSubMacro(rd, rn, operand, S, ADD);
+  if (operand.IsImmediate()) {
+    int64_t imm = operand.GetImmediate();
+    if ((imm < 0) && (imm != std::numeric_limits<int64_t>::min()) &&
+        IsImmAddSub(-imm)) {
+      AddSubMacro(rd, rn, -imm, S, SUB);
+      return;
+    }
   }
+  AddSubMacro(rd, rn, operand, S, ADD);
 }
 
 
@@ -1439,12 +1451,15 @@ void MacroAssembler::Sub(const Register& rd,
                          const Operand& operand,
                          FlagsUpdate S) {
   VIXL_ASSERT(allow_macro_instructions_);
-  if (operand.IsImmediate() && (operand.GetImmediate() < 0) &&
-      IsImmAddSub(-operand.GetImmediate())) {
-    AddSubMacro(rd, rn, -operand.GetImmediate(), S, ADD);
-  } else {
-    AddSubMacro(rd, rn, operand, S, SUB);
+  if (operand.IsImmediate()) {
+    int64_t imm = operand.GetImmediate();
+    if ((imm < 0) && (imm != std::numeric_limits<int64_t>::min()) &&
+        IsImmAddSub(-imm)) {
+      AddSubMacro(rd, rn, -imm, S, ADD);
+      return;
+    }
   }
+  AddSubMacro(rd, rn, operand, S, SUB);
 }
 
 
@@ -1757,6 +1772,12 @@ void MacroAssembler::AddSubMacro(const Register& rd,
       (rn.IsZero() && !operand.IsShiftedRegister()) ||
       (operand.IsShiftedRegister() && (operand.GetShift() == ROR))) {
     UseScratchRegisterScope temps(this);
+    // Use `rd` as a temp, if we can.
+    temps.Include(rd);
+    // We read `rn` after evaluating `operand`.
+    temps.Exclude(rn);
+    // It doesn't matter if `operand` is in `temps` (e.g. because it alises
+    // `rd`) because we don't need it after it is evaluated.
     Register temp = temps.AcquireSameSizeAs(rn);
     if (operand.IsImmediate()) {
       PreShiftImmMode mode = kAnyShift;
@@ -1842,6 +1863,12 @@ void MacroAssembler::AddSubWithCarryMacro(const Register& rd,
   //  * 1 instruction for add/sub
   MacroEmissionCheckScope guard(this);
   UseScratchRegisterScope temps(this);
+  // Use `rd` as a temp, if we can.
+  temps.Include(rd);
+  // We read `rn` after evaluating `operand`.
+  temps.Exclude(rn);
+  // It doesn't matter if `operand` is in `temps` (e.g. because it alises `rd`)
+  // because we don't need it after it is evaluated.
 
   if (operand.IsImmediate() ||
       (operand.IsShiftedRegister() && (operand.GetShift() == ROR))) {
@@ -1856,7 +1883,6 @@ void MacroAssembler::AddSubWithCarryMacro(const Register& rd,
     VIXL_ASSERT(
         IsUintN(rd.GetSizeInBits() == kXRegSize ? kXRegSizeLog2 : kWRegSizeLog2,
                 operand.GetShiftAmount()));
-    temps.Exclude(operand.GetRegister());
     Register temp = temps.AcquireSameSizeAs(rn);
     EmitShift(temp,
               operand.GetRegister(),
@@ -1872,7 +1898,6 @@ void MacroAssembler::AddSubWithCarryMacro(const Register& rd,
     VIXL_ASSERT(
         operand.GetRegister().Is64Bits() ||
         ((operand.GetExtend() != UXTX) && (operand.GetExtend() != SXTX)));
-    temps.Exclude(operand.GetRegister());
     Register temp = temps.AcquireSameSizeAs(rn);
     EmitExtendShift(temp,
                     operand.GetRegister(),
@@ -2397,7 +2422,8 @@ void MacroAssembler::LoadStoreCPURegListHelper(LoadStoreCPURegListAction op,
   // We do not handle pre-indexing or post-indexing.
   VIXL_ASSERT(!(mem.IsPreIndex() || mem.IsPostIndex()));
   VIXL_ASSERT(!registers.Overlaps(tmp_list_));
-  VIXL_ASSERT(!registers.Overlaps(fptmp_list_));
+  VIXL_ASSERT(!registers.Overlaps(v_tmp_list_));
+  VIXL_ASSERT(!registers.Overlaps(p_tmp_list_));
   VIXL_ASSERT(!registers.IncludesAliasOf(sp));
 
   UseScratchRegisterScope temps(this);
@@ -2481,7 +2507,7 @@ void MacroAssembler::BumpSystemStackPointer(const Operand& space) {
 }
 
 
-// TODO(all): Fix printf for NEON registers.
+// TODO(all): Fix printf for NEON and SVE registers.
 
 // This is the main Printf implementation. All callee-saved registers are
 // preserved, but NZCV and the caller-saved registers may be clobbered.
@@ -2764,32 +2790,6 @@ void MacroAssembler::Log(TraceParameters parameters) {
 }
 
 
-void MacroAssembler::EnableInstrumentation() {
-  VIXL_ASSERT(!isprint(InstrumentStateEnable));
-  ExactAssemblyScope scope(this, kInstructionSize);
-  movn(xzr, InstrumentStateEnable);
-}
-
-
-void MacroAssembler::DisableInstrumentation() {
-  VIXL_ASSERT(!isprint(InstrumentStateDisable));
-  ExactAssemblyScope scope(this, kInstructionSize);
-  movn(xzr, InstrumentStateDisable);
-}
-
-
-void MacroAssembler::AnnotateInstrumentation(const char* marker_name) {
-  VIXL_ASSERT(strlen(marker_name) == 2);
-
-  // We allow only printable characters in the marker names. Unprintable
-  // characters are reserved for controlling features of the instrumentation.
-  VIXL_ASSERT(isprint(marker_name[0]) && isprint(marker_name[1]));
-
-  ExactAssemblyScope scope(this, kInstructionSize);
-  movn(xzr, (marker_name[1] << 8) | marker_name[0]);
-}
-
-
 void MacroAssembler::SetSimulatorCPUFeatures(const CPUFeatures& features) {
   ConfigureSimulatorCPUFeaturesHelper(features, kSetCPUFeaturesOpcode);
 }
@@ -2870,10 +2870,13 @@ void UseScratchRegisterScope::Open(MacroAssembler* masm) {
 
   CPURegList* available = masm->GetScratchRegisterList();
   CPURegList* available_v = masm->GetScratchVRegisterList();
+  CPURegList* available_p = masm->GetScratchPRegisterList();
   old_available_ = available->GetList();
   old_available_v_ = available_v->GetList();
+  old_available_p_ = available_p->GetList();
   VIXL_ASSERT(available->GetType() == CPURegister::kRegister);
   VIXL_ASSERT(available_v->GetType() == CPURegister::kVRegister);
+  VIXL_ASSERT(available_p->GetType() == CPURegister::kPRegister);
 
   parent_ = masm->GetCurrentScratchRegisterScope();
   masm->SetCurrentScratchRegisterScope(this);
@@ -2891,6 +2894,7 @@ void UseScratchRegisterScope::Close() {
 
     masm_->GetScratchRegisterList()->SetList(old_available_);
     masm_->GetScratchVRegisterList()->SetList(old_available_v_);
+    masm_->GetScratchPRegisterList()->SetList(old_available_p_);
 
     masm_ = NULL;
   }
@@ -2899,44 +2903,46 @@ void UseScratchRegisterScope::Close() {
 
 bool UseScratchRegisterScope::IsAvailable(const CPURegister& reg) const {
   return masm_->GetScratchRegisterList()->IncludesAliasOf(reg) ||
-         masm_->GetScratchVRegisterList()->IncludesAliasOf(reg);
+         masm_->GetScratchVRegisterList()->IncludesAliasOf(reg) ||
+         masm_->GetScratchPRegisterList()->IncludesAliasOf(reg);
 }
 
-
 Register UseScratchRegisterScope::AcquireRegisterOfSize(int size_in_bits) {
-  int code = AcquireNextAvailable(masm_->GetScratchRegisterList()).GetCode();
+  int code = AcquireFrom(masm_->GetScratchRegisterList()).GetCode();
   return Register(code, size_in_bits);
 }
 
 
 VRegister UseScratchRegisterScope::AcquireVRegisterOfSize(int size_in_bits) {
-  int code = AcquireNextAvailable(masm_->GetScratchVRegisterList()).GetCode();
+  int code = AcquireFrom(masm_->GetScratchVRegisterList()).GetCode();
   return VRegister(code, size_in_bits);
 }
 
 
 void UseScratchRegisterScope::Release(const CPURegister& reg) {
   VIXL_ASSERT(masm_ != NULL);
-  if (reg.IsRegister()) {
-    ReleaseByCode(masm_->GetScratchRegisterList(), reg.GetCode());
-  } else if (reg.IsVRegister()) {
-    ReleaseByCode(masm_->GetScratchVRegisterList(), reg.GetCode());
-  } else {
-    VIXL_ASSERT(reg.IsNone());
-  }
+
+  // Release(NoReg) has no effect.
+  if (reg.IsNone()) return;
+
+  ReleaseByCode(GetAvailableListFor(reg.GetBank()), reg.GetCode());
 }
 
 
 void UseScratchRegisterScope::Include(const CPURegList& list) {
   VIXL_ASSERT(masm_ != NULL);
+
+  // Including an empty list has no effect.
+  if (list.IsEmpty()) return;
+  VIXL_ASSERT(list.GetType() != CPURegister::kNoRegister);
+
+  RegList reg_list = list.GetList();
   if (list.GetType() == CPURegister::kRegister) {
     // Make sure that neither sp nor xzr are included the list.
-    IncludeByRegList(masm_->GetScratchRegisterList(),
-                     list.GetList() & ~(xzr.GetBit() | sp.GetBit()));
-  } else {
-    VIXL_ASSERT(list.GetType() == CPURegister::kVRegister);
-    IncludeByRegList(masm_->GetScratchVRegisterList(), list.GetList());
+    reg_list &= ~(xzr.GetBit() | sp.GetBit());
   }
+
+  IncludeByRegList(GetAvailableListFor(list.GetBank()), reg_list);
 }
 
 
@@ -2964,13 +2970,43 @@ void UseScratchRegisterScope::Include(const VRegister& reg1,
 }
 
 
-void UseScratchRegisterScope::Exclude(const CPURegList& list) {
-  if (list.GetType() == CPURegister::kRegister) {
-    ExcludeByRegList(masm_->GetScratchRegisterList(), list.GetList());
-  } else {
-    VIXL_ASSERT(list.GetType() == CPURegister::kVRegister);
-    ExcludeByRegList(masm_->GetScratchVRegisterList(), list.GetList());
+void UseScratchRegisterScope::Include(const CPURegister& reg1,
+                                      const CPURegister& reg2,
+                                      const CPURegister& reg3,
+                                      const CPURegister& reg4) {
+  RegList include = 0;
+  RegList include_v = 0;
+  RegList include_p = 0;
+
+  const CPURegister regs[] = {reg1, reg2, reg3, reg4};
+
+  for (size_t i = 0; i < ArrayLength(regs); i++) {
+    RegList bit = regs[i].GetBit();
+    switch (regs[i].GetBank()) {
+      case CPURegister::kNoRegisterBank:
+        // Include(NoReg) has no effect.
+        VIXL_ASSERT(regs[i].IsNone());
+        break;
+      case CPURegister::kRRegisterBank:
+        include |= bit;
+        break;
+      case CPURegister::kVRegisterBank:
+        include_v |= bit;
+        break;
+      case CPURegister::kPRegisterBank:
+        include_p |= bit;
+        break;
+    }
   }
+
+  IncludeByRegList(masm_->GetScratchRegisterList(), include);
+  IncludeByRegList(masm_->GetScratchVRegisterList(), include_v);
+  IncludeByRegList(masm_->GetScratchPRegisterList(), include_p);
+}
+
+
+void UseScratchRegisterScope::Exclude(const CPURegList& list) {
+  ExcludeByRegList(GetAvailableListFor(list.GetBank()), list.GetList());
 }
 
 
@@ -2988,9 +3024,9 @@ void UseScratchRegisterScope::Exclude(const VRegister& reg1,
                                       const VRegister& reg2,
                                       const VRegister& reg3,
                                       const VRegister& reg4) {
-  RegList excludefp =
+  RegList exclude_v =
       reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
-  ExcludeByRegList(masm_->GetScratchVRegisterList(), excludefp);
+  ExcludeByRegList(masm_->GetScratchVRegisterList(), exclude_v);
 }
 
 
@@ -2999,22 +3035,33 @@ void UseScratchRegisterScope::Exclude(const CPURegister& reg1,
                                       const CPURegister& reg3,
                                       const CPURegister& reg4) {
   RegList exclude = 0;
-  RegList excludefp = 0;
+  RegList exclude_v = 0;
+  RegList exclude_p = 0;
 
   const CPURegister regs[] = {reg1, reg2, reg3, reg4};
 
   for (size_t i = 0; i < ArrayLength(regs); i++) {
-    if (regs[i].IsRegister()) {
-      exclude |= regs[i].GetBit();
-    } else if (regs[i].IsVRegister()) {
-      excludefp |= regs[i].GetBit();
-    } else {
-      VIXL_ASSERT(regs[i].IsNone());
+    RegList bit = regs[i].GetBit();
+    switch (regs[i].GetBank()) {
+      case CPURegister::kNoRegisterBank:
+        // Exclude(NoReg) has no effect.
+        VIXL_ASSERT(regs[i].IsNone());
+        break;
+      case CPURegister::kRRegisterBank:
+        exclude |= bit;
+        break;
+      case CPURegister::kVRegisterBank:
+        exclude_v |= bit;
+        break;
+      case CPURegister::kPRegisterBank:
+        exclude_p |= bit;
+        break;
     }
   }
 
   ExcludeByRegList(masm_->GetScratchRegisterList(), exclude);
-  ExcludeByRegList(masm_->GetScratchVRegisterList(), excludefp);
+  ExcludeByRegList(masm_->GetScratchVRegisterList(), exclude_v);
+  ExcludeByRegList(masm_->GetScratchPRegisterList(), exclude_p);
 }
 
 
@@ -3023,13 +3070,15 @@ void UseScratchRegisterScope::ExcludeAll() {
                    masm_->GetScratchRegisterList()->GetList());
   ExcludeByRegList(masm_->GetScratchVRegisterList(),
                    masm_->GetScratchVRegisterList()->GetList());
+  ExcludeByRegList(masm_->GetScratchPRegisterList(),
+                   masm_->GetScratchPRegisterList()->GetList());
 }
 
 
-CPURegister UseScratchRegisterScope::AcquireNextAvailable(
-    CPURegList* available) {
-  VIXL_CHECK(!available->IsEmpty());
-  CPURegister result = available->PopLowestIndex();
+CPURegister UseScratchRegisterScope::AcquireFrom(CPURegList* available,
+                                                 RegList mask) {
+  VIXL_CHECK((available->GetList() & mask) != 0);
+  CPURegister result = available->PopLowestIndex(mask);
   VIXL_ASSERT(!AreAliased(result, xzr, sp));
   return result;
 }
@@ -3057,5 +3106,22 @@ void UseScratchRegisterScope::ExcludeByRegList(CPURegList* available,
   available->SetList(available->GetList() & ~exclude);
 }
 
+CPURegList* UseScratchRegisterScope::GetAvailableListFor(
+    CPURegister::RegisterBank bank) {
+  switch (bank) {
+    case CPURegister::kNoRegisterBank:
+      return NULL;
+    case CPURegister::kRRegisterBank:
+      return masm_->GetScratchRegisterList();
+    case CPURegister::kVRegisterBank:
+      return masm_->GetScratchVRegisterList();
+    case CPURegister::kPRegisterBank:
+      return masm_->GetScratchPRegisterList();
+      return NULL;
+  }
+  VIXL_UNREACHABLE();
+  return NULL;
+}
+
 }  // namespace aarch64
 }  // namespace vixl
diff --git a/src/aarch64/macro-assembler-aarch64.h b/src/aarch64/macro-assembler-aarch64.h
index 31db8dab..8becddbb 100644
--- a/src/aarch64/macro-assembler-aarch64.h
+++ b/src/aarch64/macro-assembler-aarch64.h
@@ -35,7 +35,6 @@
 #include "../macro-assembler-interface.h"
 
 #include "assembler-aarch64.h"
-#include "instrument-aarch64.h"
 // Required for runtime call support.
 // TODO: Break this dependency. We should be able to separate out the necessary
 // parts so that we don't need to include the whole simulator header.
@@ -61,7 +60,7 @@
 #define LSPAIR_MACRO_LIST(V)                             \
   V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2))  \
   V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
-  V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
+  V(Ldpsw, Register&, rt, rt2, LDPSW_x)
 
 namespace vixl {
 namespace aarch64 {
@@ -528,6 +527,57 @@ class MacroEmissionCheckScope : public EmissionCheckScope {
 };
 
 
+// This scope simplifies the handling of the SVE `movprfx` instruction.
+//
+// If dst.Aliases(src):
+// - Start an ExactAssemblyScope(masm, kInstructionSize).
+// Otherwise:
+// - Start an ExactAssemblyScope(masm, 2 * kInstructionSize).
+// - Generate a suitable `movprfx` instruction.
+//
+// In both cases, the ExactAssemblyScope is left with enough remaining space for
+// exactly one destructive instruction.
+class MovprfxHelperScope : public ExactAssemblyScope {
+ public:
+  inline MovprfxHelperScope(MacroAssembler* masm,
+                            const ZRegister& dst,
+                            const ZRegister& src);
+
+  inline MovprfxHelperScope(MacroAssembler* masm,
+                            const ZRegister& dst,
+                            const PRegister& pg,
+                            const ZRegister& src);
+
+  // TODO: Implement constructors that examine _all_ sources. If `dst` aliases
+  // any other source register, we can't use `movprfx`. This isn't obviously
+  // useful, but the MacroAssembler should not generate invalid code for it.
+  // Valid behaviour can be implemented using `mov`.
+  //
+  // The best way to handle this in an instruction-agnostic way is probably to
+  // use variadic templates.
+
+ private:
+  inline bool ShouldGenerateMovprfx(const ZRegister& dst,
+                                    const ZRegister& src) {
+    VIXL_ASSERT(AreSameLaneSize(dst, src));
+    return !dst.Aliases(src);
+  }
+
+  inline bool ShouldGenerateMovprfx(const ZRegister& dst,
+                                    const PRegister& pg,
+                                    const ZRegister& src) {
+    VIXL_ASSERT(pg.IsMerging() || pg.IsZeroing());
+    // We need to emit movprfx in two cases:
+    //  1. To give a predicated merging unary instruction zeroing predication.
+    //  2. To make destructive instructions constructive.
+    //
+    // There are no predicated zeroing instructions that can take movprfx, so we
+    // will never generate an unnecessary movprfx with this logic.
+    return pg.IsZeroing() || ShouldGenerateMovprfx(dst, src);
+  }
+};
+
+
 enum BranchType {
   // Copies of architectural conditions.
   // The associated conditions can be used in place of those, the code will
@@ -566,7 +616,19 @@ enum BranchType {
   kBranchTypeFirstCondition = eq,
   kBranchTypeLastCondition = nv,
   kBranchTypeFirstUsingReg = reg_zero,
-  kBranchTypeFirstUsingBit = reg_bit_clear
+  kBranchTypeFirstUsingBit = reg_bit_clear,
+
+  // SVE branch conditions.
+  integer_none = eq,
+  integer_any = ne,
+  integer_nlast = cs,
+  integer_last = cc,
+  integer_first = mi,
+  integer_nfrst = pl,
+  integer_pmore = hi,
+  integer_plast = ls,
+  integer_tcont = ge,
+  integer_tstop = lt
 };
 
 
@@ -587,6 +649,18 @@ enum PreShiftImmMode {
   kAnyShift          // Allow any pre-shift.
 };
 
+enum FPMacroNaNPropagationOption {
+  // The default option. This generates a run-time error in macros that respect
+  // this option.
+  NoFPMacroNaNPropagationSelected,
+  // For example, Fmin(result, NaN(a), NaN(b)) always selects NaN(a) if both
+  // NaN(a) and NaN(b) are both quiet, or both are signalling, at the
+  // cost of extra code generation in some cases.
+  StrictNaNPropagation,
+  // For example, Fmin(result, NaN(a), NaN(b)) selects either NaN, but using the
+  // fewest instructions.
+  FastNaNPropagation
+};
 
 class MacroAssembler : public Assembler, public MacroAssemblerInterface {
  public:
@@ -946,6 +1020,20 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   void Claim(const Operand& size);
   void Drop(const Operand& size);
 
+  // As above, but for multiples of the SVE vector length.
+  void ClaimVL(int64_t multiplier) {
+    // We never need to worry about sp alignment because the VL is always a
+    // multiple of 16.
+    VIXL_STATIC_ASSERT((kZRegMinSizeInBytes % 16) == 0);
+    VIXL_ASSERT(multiplier >= 0);
+    Addvl(sp, sp, -multiplier);
+  }
+  void DropVL(int64_t multiplier) {
+    VIXL_STATIC_ASSERT((kZRegMinSizeInBytes % 16) == 0);
+    VIXL_ASSERT(multiplier >= 0);
+    Addvl(sp, sp, multiplier);
+  }
+
   // Preserve the callee-saved registers (as defined by AAPCS64).
   //
   // Higher-numbered registers are pushed before lower-numbered registers, and
@@ -1489,13 +1577,8 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   void Fmov(const VRegister& vd, const VRegister& vn) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
-    // Only emit an instruction if vd and vn are different, and they are both D
-    // registers. fmov(s0, s0) is not a no-op because it clears the top word of
-    // d0. Technically, fmov(d0, d0) is not a no-op either because it clears
-    // the top of q0, but VRegister does not currently support Q registers.
-    if (!vd.Is(vn) || !vd.Is64Bits()) {
-      fmov(vd, vn);
-    }
+    // TODO: Use DiscardMoveMode to allow this move to be elided if vd.Is(vn).
+    fmov(vd, vn);
   }
   void Fmov(const VRegister& vd, const Register& rn) {
     VIXL_ASSERT(allow_macro_instructions_);
@@ -1503,12 +1586,6 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
     SingleEmissionCheckScope guard(this);
     fmov(vd, rn);
   }
-  void Fmov(const VRegister& vd, const XRegister& xn) {
-    Fmov(vd, Register(xn));
-  }
-  void Fmov(const VRegister& vd, const WRegister& wn) {
-    Fmov(vd, Register(wn));
-  }
   void Fmov(const VRegister& vd, int index, const Register& rn) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
@@ -2970,6 +3047,43 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   NEON_2VREG_SHIFT_LONG_MACRO_LIST(DEFINE_MACRO_ASM_FUNC)
 #undef DEFINE_MACRO_ASM_FUNC
 
+// SVE 3 vector register instructions.
+#define SVE_3VREG_COMMUTATIVE_MACRO_LIST(V) \
+  V(add, Add)                               \
+  V(and_, And)                              \
+  V(bic, Bic)                               \
+  V(eor, Eor)                               \
+  V(mul, Mul)                               \
+  V(orr, Orr)                               \
+  V(sabd, Sabd)                             \
+  V(smax, Smax)                             \
+  V(smulh, Smulh)                           \
+  V(smin, Smin)                             \
+  V(uabd, Uabd)                             \
+  V(umax, Umax)                             \
+  V(umin, Umin)                             \
+  V(umulh, Umulh)
+
+#define DEFINE_MACRO_ASM_FUNC(ASM, MASM)          \
+  void MASM(const ZRegister& zd,                  \
+            const PRegisterM& pg,                 \
+            const ZRegister& zn,                  \
+            const ZRegister& zm) {                \
+    VIXL_ASSERT(allow_macro_instructions_);       \
+    if (zd.Aliases(zn)) {                         \
+      SingleEmissionCheckScope guard(this);       \
+      ASM(zd, pg, zd, zm);                        \
+    } else if (zd.Aliases(zm)) {                  \
+      SingleEmissionCheckScope guard(this);       \
+      ASM(zd, pg, zd, zn);                        \
+    } else {                                      \
+      MovprfxHelperScope guard(this, zd, pg, zn); \
+      ASM(zd, pg, zd, zm);                        \
+    }                                             \
+  }
+  SVE_3VREG_COMMUTATIVE_MACRO_LIST(DEFINE_MACRO_ASM_FUNC)
+#undef DEFINE_MACRO_ASM_FUNC
+
   void Bic(const VRegister& vd, const int imm8, const int left_shift = 0) {
     VIXL_ASSERT(allow_macro_instructions_);
     SingleEmissionCheckScope guard(this);
@@ -3357,6 +3471,2901 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
     crc32cx(rd, rn, rm);
   }
 
+  // Scalable Vector Extensions.
+  void Abs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    abs(zd, pg, zn);
+  }
+  void Add(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    add(zd, zn, zm);
+  }
+  void Add(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    AddSubHelper(kAddImmediate, zd, zn, imm);
+  }
+  void Addpl(const Register& xd, const Register& xn, int64_t multiplier);
+  void Addvl(const Register& xd, const Register& xn, int64_t multiplier);
+  // Note that unlike the core ISA, SVE's `adr` is not PC-relative.
+  void Adr(const ZRegister& zd, const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    adr(zd, addr);
+  }
+  void And(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    and_(pd, pg, pn, pm);
+  }
+  void And(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (IsImmLogical(imm, zd.GetLaneSizeInBits())) {
+      and_(zd, zn, imm);
+    } else {
+      // TODO: Synthesise the immediate once 'Mov' is implemented.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void And(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+    SingleEmissionCheckScope guard(this);
+    and_(zd.VnD(), zn.VnD(), zm.VnD());
+  }
+  void Ands(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ands(pd, pg, pn, pm);
+  }
+  void Andv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    andv(vd, pg, zn);
+  }
+  void Asr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           int shift) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    asr(zd, pg, zd, shift);
+  }
+  void Asr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+  void Asr(const ZRegister& zd, const ZRegister& zn, int shift) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    asr(zd, zn, shift);
+  }
+  void Asr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    asr(zd, zn, zm);
+  }
+  void Asrd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            int shift) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    asrd(zd, pg, zd, shift);
+  }
+  void Bic(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    bic(pd, pg, pn, pm);
+  }
+  void Bic(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+    SingleEmissionCheckScope guard(this);
+    bic(zd.VnD(), zn.VnD(), zm.VnD());
+  }
+  void Bic(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (IsImmLogical(imm, zd.GetLaneSizeInBits())) {
+      bic(zd, zn, imm);
+    } else {
+      // TODO: Synthesise the immediate once 'Mov' is implemented.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Bics(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    bics(pd, pg, pn, pm);
+  }
+  void Brka(const PRegisterWithLaneSize& pd,
+            const PRegister& pg,
+            const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    brka(pd, pg, pn);
+  }
+  void Brkas(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    brkas(pd, pg, pn);
+  }
+  void Brkb(const PRegisterWithLaneSize& pd,
+            const PRegister& pg,
+            const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    brkb(pd, pg, pn);
+  }
+  void Brkbs(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    brkbs(pd, pg, pn);
+  }
+  void Brkn(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    if (!pd.Aliases(pm)) {
+      Mov(pd, pm);
+    }
+    SingleEmissionCheckScope guard(this);
+    brkn(pd, pg, pn, pd);
+  }
+  void Brkns(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn,
+             const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    if (!pd.Aliases(pm)) {
+      Mov(pd, pm);
+    }
+    SingleEmissionCheckScope guard(this);
+    brkns(pd, pg, pn, pd);
+  }
+  void Brkpa(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn,
+             const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    brkpa(pd, pg, pn, pm);
+  }
+  void Brkpas(const PRegisterWithLaneSize& pd,
+              const PRegisterZ& pg,
+              const PRegisterWithLaneSize& pn,
+              const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    brkpas(pd, pg, pn, pm);
+  }
+  void Brkpb(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn,
+             const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    brkpb(pd, pg, pn, pm);
+  }
+  void Brkpbs(const PRegisterWithLaneSize& pd,
+              const PRegisterZ& pg,
+              const PRegisterWithLaneSize& pn,
+              const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    brkpbs(pd, pg, pn, pm);
+  }
+  void Clasta(const Register& rd,
+              const PRegister& pg,
+              const Register& rn,
+              const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    clasta(rd, pg, rn, zm);
+  }
+  void Clasta(const VRegister& vd,
+              const PRegister& pg,
+              const VRegister& vn,
+              const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    clasta(vd, pg, vn, zm);
+  }
+  void Clasta(const ZRegister& zd,
+              const PRegister& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+  void Clastb(const Register& rd,
+              const PRegister& pg,
+              const Register& rn,
+              const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    clastb(rd, pg, rn, zm);
+  }
+  void Clastb(const VRegister& vd,
+              const PRegister& pg,
+              const VRegister& vn,
+              const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    clastb(vd, pg, vn, zm);
+  }
+  void Clastb(const ZRegister& zd,
+              const PRegister& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+  void Cls(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cls(zd, pg, zn);
+  }
+  void Clz(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    clz(zd, pg, zn);
+  }
+  void Cmpeq(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmpeq(pd, pg, zn, zm);
+  }
+  void Cmpeq(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    int imm5;
+    if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) {
+      SingleEmissionCheckScope guard(this);
+      cmpeq(pd, pg, zn, imm5);
+    } else {
+      CompareHelper(eq, pd, pg, zn, imm);
+    }
+  }
+  void Cmpge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmpge(pd, pg, zn, zm);
+  }
+  void Cmpge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    int imm5;
+    if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) {
+      SingleEmissionCheckScope guard(this);
+      cmpge(pd, pg, zn, imm5);
+    } else {
+      CompareHelper(ge, pd, pg, zn, imm);
+    }
+  }
+  void Cmpgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmpgt(pd, pg, zn, zm);
+  }
+  void Cmpgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    int imm5;
+    if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) {
+      SingleEmissionCheckScope guard(this);
+      cmpgt(pd, pg, zn, imm5);
+    } else {
+      CompareHelper(gt, pd, pg, zn, imm);
+    }
+  }
+  void Cmphi(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmphi(pd, pg, zn, zm);
+  }
+  void Cmphi(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    if (imm.IsUintN(7)) {
+      SingleEmissionCheckScope guard(this);
+      cmphi(pd, pg, zn, static_cast<unsigned>(imm.AsUintN(7)));
+    } else {
+      CompareHelper(hi, pd, pg, zn, imm);
+    }
+  }
+  void Cmphs(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmphs(pd, pg, zn, zm);
+  }
+  void Cmphs(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    if (imm.IsUintN(7)) {
+      SingleEmissionCheckScope guard(this);
+      cmphs(pd, pg, zn, static_cast<unsigned>(imm.AsUintN(7)));
+    } else {
+      CompareHelper(hs, pd, pg, zn, imm);
+    }
+  }
+  void Cmple(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmple(pd, pg, zn, zm);
+  }
+  void Cmple(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    int imm5;
+    if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) {
+      SingleEmissionCheckScope guard(this);
+      cmple(pd, pg, zn, imm5);
+    } else {
+      CompareHelper(le, pd, pg, zn, imm);
+    }
+  }
+  void Cmplo(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmplo(pd, pg, zn, zm);
+  }
+  void Cmplo(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    if (imm.IsUintN(7)) {
+      SingleEmissionCheckScope guard(this);
+      cmplo(pd, pg, zn, static_cast<unsigned>(imm.AsUintN(7)));
+    } else {
+      CompareHelper(lo, pd, pg, zn, imm);
+    }
+  }
+  void Cmpls(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmpls(pd, pg, zn, zm);
+  }
+  void Cmpls(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    if (imm.IsUintN(7)) {
+      SingleEmissionCheckScope guard(this);
+      cmpls(pd, pg, zn, static_cast<unsigned>(imm.AsUintN(7)));
+    } else {
+      CompareHelper(ls, pd, pg, zn, imm);
+    }
+  }
+  void Cmplt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmplt(pd, pg, zn, zm);
+  }
+  void Cmplt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    int imm5;
+    if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) {
+      SingleEmissionCheckScope guard(this);
+      cmplt(pd, pg, zn, imm5);
+    } else {
+      CompareHelper(lt, pd, pg, zn, imm);
+    }
+  }
+  void Cmpne(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cmpne(pd, pg, zn, zm);
+  }
+  void Cmpne(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    int imm5;
+    if (imm.TryEncodeAsIntNForLane<5>(zn, &imm5)) {
+      SingleEmissionCheckScope guard(this);
+      cmpne(pd, pg, zn, imm5);
+    } else {
+      CompareHelper(ne, pd, pg, zn, imm);
+    }
+  }
+  void Cnot(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cnot(zd, pg, zn);
+  }
+  void Cnt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cnt(zd, pg, zn);
+  }
+  void Cntb(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cntb(rd, pattern, multiplier);
+  }
+  void Cntd(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cntd(rd, pattern, multiplier);
+  }
+  void Cnth(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cnth(rd, pattern, multiplier);
+  }
+  void Cntp(const Register& rd,
+            const PRegister& pg,
+            const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    // The `cntp` instruction architecturally takes an X register, but the
+    // result will always be in the range [0, kPRegMaxSize] (and therefore
+    // always fits in a W register), so we can accept a W-sized rd here.
+    cntp(rd.X(), pg, pn);
+  }
+  void Cntw(const Register& rd, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cntw(rd, pattern, multiplier);
+  }
+  void Compact(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    compact(zd, pg, zn);
+  }
+  void Cpy(const ZRegister& zd, const PRegister& pg, IntegerOperand imm);
+  void Cpy(const ZRegister& zd, const PRegisterM& pg, const Register& rn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cpy(zd, pg, rn);
+  }
+  void Cpy(const ZRegister& zd, const PRegisterM& pg, const VRegister& vn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    cpy(zd, pg, vn);
+  }
+  void Ctermeq(const Register& rn, const Register& rm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ctermeq(rn, rm);
+  }
+  void Ctermne(const Register& rn, const Register& rm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ctermne(rn, rm);
+  }
+  void Decb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    decb(rdn, pattern, multiplier);
+  }
+  void Decd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    decd(rdn, pattern, multiplier);
+  }
+  void Decd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    decd(zdn, pattern, multiplier);
+  }
+  void Dech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    dech(rdn, pattern, multiplier);
+  }
+  void Dech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    dech(zdn, pattern, multiplier);
+  }
+  void Decp(const Register& rdn, const PRegisterWithLaneSize& pg) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    decp(rdn, pg);
+  }
+  void Decp(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameFormat(zd, zn));
+    // `decp` writes every lane, so use an unpredicated movprfx.
+    MovprfxHelperScope guard(this, zd, zn);
+    decp(zd, pg);
+  }
+  void Decp(const ZRegister& zdn, const PRegister& pg) { Decp(zdn, pg, zdn); }
+  void Decw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    decw(rdn, pattern, multiplier);
+  }
+  void Decw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    decw(zdn, pattern, multiplier);
+  }
+  void Dup(const ZRegister& zd, const Register& xn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    dup(zd, xn);
+  }
+  void Dup(const ZRegister& zd, const ZRegister& zn, int index) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    dup(zd, zn, index);
+  }
+  void Dup(const ZRegister& zd, IntegerOperand imm);
+  void Eon(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (IsImmLogical(imm, zd.GetLaneSizeInBits())) {
+      eon(zd, zn, imm);
+    } else {
+      // TODO: Synthesise the immediate once 'Mov' is implemented.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Eor(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    eor(pd, pg, pn, pm);
+  }
+  void Eor(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (IsImmLogical(imm, zd.GetLaneSizeInBits())) {
+      eor(zd, zn, imm);
+    } else {
+      // TODO: Synthesise the immediate once 'Mov' is implemented.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Eor(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+    SingleEmissionCheckScope guard(this);
+    eor(zd.VnD(), zn.VnD(), zm.VnD());
+  }
+  void Eors(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    eors(pd, pg, pn, pm);
+  }
+  void Eorv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    eorv(vd, pg, zn);
+  }
+  void Ext(const ZRegister& zd,
+           const ZRegister& zn,
+           const ZRegister& zm,
+           unsigned offset);
+  void Fabd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            FPMacroNaNPropagationOption nan_option);
+  void Fabs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fabs(zd, pg, zn);
+  }
+  void Facge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    facge(pd, pg, zn, zm);
+  }
+  void Facgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    facgt(pd, pg, zn, zm);
+  }
+  void Facle(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    facge(pd, pg, zm, zn);
+  }
+  void Faclt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    facgt(pd, pg, zm, zn);
+  }
+  void Fadd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fadd(zd, pg, zd, imm);
+  }
+  void Fadd(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            FPMacroNaNPropagationOption nan_option);
+  void Fadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fadd(zd, zn, zm);
+  }
+  void Fadda(const VRegister& vd,
+             const PRegister& pg,
+             const VRegister& vn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fadda(vd, pg, vn, zm);
+  }
+  void Faddv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    faddv(vd, pg, zn);
+  }
+  void Fcadd(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             int rot);
+  void Fcmeq(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (zero == 0.0) {
+      fcmeq(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Fcmeq(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcmeq(pd, pg, zn, zm);
+  }
+  void Fcmge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (zero == 0.0) {
+      fcmge(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Fcmge(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcmge(pd, pg, zn, zm);
+  }
+  void Fcmgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (zero == 0.0) {
+      fcmgt(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Fcmgt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcmgt(pd, pg, zn, zm);
+  }
+  void Fcmla(const ZRegister& zda,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             int rot) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zda, pg, zda);
+    fcmla(zda, pg, zn, zm, rot);
+  }
+  void Fcmla(const ZRegister& zda,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             int index,
+             int rot) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcmla(zda, zn, zm, index, rot);
+  }
+  void Fcmle(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (zero == 0.0) {
+      fcmle(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Fcmle(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcmge(pd, pg, zm, zn);
+  }
+  void Fcmlt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (zero == 0.0) {
+      fcmlt(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Fcmlt(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcmgt(pd, pg, zm, zn);
+  }
+  void Fcmne(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             double zero) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (zero == 0.0) {
+      fcmne(pd, pg, zn, zero);
+    } else {
+      // TODO: Synthesise other immediates.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Fcmne(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcmne(pd, pg, zn, zm);
+  }
+  void Fcmuo(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const ZRegister& zn,
+             const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcmuo(pd, pg, zn, zm);
+  }
+  void Fcpy(const ZRegister& zd, const PRegisterM& pg, double imm);
+  void Fcpy(const ZRegister& zd, const PRegisterM& pg, float imm);
+  void Fcpy(const ZRegister& zd, const PRegisterM& pg, Float16 imm);
+  void Fcvt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcvt(zd, pg, zn);
+  }
+  void Fcvt(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    // The element type in this predicated movprfx is determined by the larger
+    // type between the source and destination.
+    int lane_size = std::max(zd.GetLaneSizeInBits(), zn.GetLaneSizeInBits());
+    MovprfxHelperScope guard(this,
+                             zd.WithLaneSize(lane_size),
+                             pg,
+                             zn.WithLaneSize(lane_size));
+    fcvt(zd, pg.Merging(), zn);
+  }
+  void Fcvtzs(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcvtzs(zd, pg, zn);
+  }
+  void Fcvtzu(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fcvtzu(zd, pg, zn);
+  }
+  void Fdiv(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+  void Fdup(const ZRegister& zd, double imm);
+  void Fdup(const ZRegister& zd, float imm);
+  void Fdup(const ZRegister& zd, Float16 imm);
+  void Fexpa(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fexpa(zd, zn);
+  }
+  void Fmad(const ZRegister& zdn,
+            const PRegisterM& pg,
+            const ZRegister& zm,
+            const ZRegister& za) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fmad(zdn, pg, zm, za);
+  }
+  void Fmax(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fmax(zd, pg, zd, imm);
+  }
+  void Fmax(
+      const ZRegister& zd,
+      const PRegisterM& pg,
+      const ZRegister& zn,
+      const ZRegister& zm,
+      FPMacroNaNPropagationOption nan_option = NoFPMacroNaNPropagationSelected);
+  void Fmaxnm(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fmaxnm(zd, pg, zd, imm);
+  }
+  void Fmaxnm(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              const ZRegister& zm,
+              FPMacroNaNPropagationOption nan_option);
+  void Fmaxnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fmaxnmv(vd, pg, zn);
+  }
+  void Fmaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fmaxv(vd, pg, zn);
+  }
+  void Fmin(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fmin(zd, pg, zd, imm);
+  }
+  void Fmin(
+      const ZRegister& zd,
+      const PRegisterM& pg,
+      const ZRegister& zn,
+      const ZRegister& zm,
+      FPMacroNaNPropagationOption nan_option = NoFPMacroNaNPropagationSelected);
+  void Fminnm(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fminnm(zd, pg, zd, imm);
+  }
+  void Fminnm(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              const ZRegister& zm,
+              FPMacroNaNPropagationOption nan_option);
+  void Fminnmv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fminnmv(vd, pg, zn);
+  }
+  void Fminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fminv(vd, pg, zn);
+  }
+  // zd = za + (zn * zm)
+  void Fmla(
+      const ZRegister& zd,
+      const PRegisterM& pg,
+      const ZRegister& za,
+      const ZRegister& zn,
+      const ZRegister& zm,
+      FPMacroNaNPropagationOption nan_option = NoFPMacroNaNPropagationSelected);
+  void Fmla(const ZRegister& zd,
+            const ZRegister& za,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            int index);
+  // zd = za - (zn * zm)
+  void Fmls(
+      const ZRegister& zd,
+      const PRegisterM& pg,
+      const ZRegister& za,
+      const ZRegister& zn,
+      const ZRegister& zm,
+      FPMacroNaNPropagationOption nan_option = NoFPMacroNaNPropagationSelected);
+  void Fmls(const ZRegister& zd,
+            const ZRegister& za,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            int index);
+  void Fmov(const ZRegister& zd, double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Fdup(zd, imm);
+  }
+  void Fmov(const ZRegister& zd, float imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Fdup(zd, imm);
+  }
+  void Fmov(const ZRegister& zd, Float16 imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Fdup(zd, imm);
+  }
+  void Fmov(const ZRegister& zd, const PRegisterM& pg, double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Fcpy(zd, pg, imm);
+  }
+  void Fmov(const ZRegister& zd, const PRegisterM& pg, float imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Fcpy(zd, pg, imm);
+  }
+  void Fmov(const ZRegister& zd, const PRegisterM& pg, Float16 imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Fcpy(zd, pg, imm);
+  }
+  void Fmsb(const ZRegister& zdn,
+            const PRegisterM& pg,
+            const ZRegister& zm,
+            const ZRegister& za) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fmsb(zdn, pg, zm, za);
+  }
+  void Fmul(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fmul(zd, pg, zd, imm);
+  }
+  void Fmul(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            FPMacroNaNPropagationOption nan_option);
+  void Fmul(const ZRegister& zd,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            unsigned index) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fmul(zd, zn, zm, index);
+  }
+  void Fmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fmul(zd, zn, zm);
+  }
+  void Fmulx(const ZRegister& zd,
+             const PRegisterM& pg,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             FPMacroNaNPropagationOption nan_option);
+  void Fneg(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fneg(zd, pg, zn);
+  }
+  void Fnmla(
+      const ZRegister& zda,
+      const PRegisterM& pg,
+      const ZRegister& za,
+      const ZRegister& zn,
+      const ZRegister& zm,
+      FPMacroNaNPropagationOption nan_option = NoFPMacroNaNPropagationSelected);
+  void Fnmls(
+      const ZRegister& zd,
+      const PRegisterM& pg,
+      const ZRegister& za,
+      const ZRegister& zn,
+      const ZRegister& zm,
+      FPMacroNaNPropagationOption nan_option = NoFPMacroNaNPropagationSelected);
+  void Frecpe(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frecpe(zd, zn);
+  }
+  void Frecps(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frecps(zd, zn, zm);
+  }
+  void Frecpx(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frecpx(zd, pg, zn);
+  }
+  void Frecpx(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    frecpx(zd, pg.Merging(), zn);
+  }
+  void Frinta(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frinta(zd, pg, zn);
+  }
+  void Frinta(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    frinta(zd, pg.Merging(), zn);
+  }
+  void Frinti(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frinti(zd, pg, zn);
+  }
+  void Frinti(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    frinti(zd, pg.Merging(), zn);
+  }
+  void Frintm(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frintm(zd, pg, zn);
+  }
+  void Frintm(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    frintm(zd, pg.Merging(), zn);
+  }
+  void Frintn(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frintn(zd, pg, zn);
+  }
+  void Frintn(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    frintn(zd, pg.Merging(), zn);
+  }
+  void Frintp(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frintp(zd, pg, zn);
+  }
+  void Frintp(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    frintp(zd, pg.Merging(), zn);
+  }
+  void Frintx(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frintx(zd, pg, zn);
+  }
+  void Frintx(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    frintx(zd, pg.Merging(), zn);
+  }
+  void Frintz(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frintz(zd, pg, zn);
+  }
+  void Frintz(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    frintz(zd, pg.Merging(), zn);
+  }
+  void Frsqrte(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frsqrte(zd, zn);
+  }
+  void Frsqrts(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    frsqrts(zd, zn, zm);
+  }
+  void Fscale(const ZRegister& zd,
+              const PRegisterM& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+  void Fsqrt(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fsqrt(zd, pg, zn);
+  }
+  void Fsqrt(const ZRegister& zd, const PRegisterZ& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fsqrt(zd, pg.Merging(), zn);
+  }
+  void Fsub(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            double imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fsub(zd, pg, zd, imm);
+  }
+  void Fsub(const ZRegister& zd,
+            const PRegisterM& pg,
+            double imm,
+            const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fsubr(zd, pg, zd, imm);
+  }
+  void Fsub(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+  void Fsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    fsub(zd, zn, zm);
+  }
+  void Ftmad(const ZRegister& zd,
+             const ZRegister& zn,
+             const ZRegister& zm,
+             int imm3);
+  void Ftsmul(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ftsmul(zd, zn, zm);
+  }
+  void Ftssel(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ftssel(zd, zn, zm);
+  }
+  void Incb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    incb(rdn, pattern, multiplier);
+  }
+  void Incd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    incd(rdn, pattern, multiplier);
+  }
+  void Incd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    incd(zdn, pattern, multiplier);
+  }
+  void Inch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    inch(rdn, pattern, multiplier);
+  }
+  void Inch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    inch(zdn, pattern, multiplier);
+  }
+  void Incp(const Register& rdn, const PRegisterWithLaneSize& pg) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    incp(rdn, pg);
+  }
+  void Incp(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameFormat(zd, zn));
+    // `incp` writes every lane, so use an unpredicated movprfx.
+    MovprfxHelperScope guard(this, zd, zn);
+    incp(zd, pg);
+  }
+  void Incp(const ZRegister& zdn, const PRegister& pg) { Incp(zdn, pg, zdn); }
+  void Incw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    incw(rdn, pattern, multiplier);
+  }
+  void Incw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    incw(zdn, pattern, multiplier);
+  }
+  void Index(const ZRegister& zd, const Operand& start, const Operand& step);
+  void Insr(const ZRegister& zdn, const Register& rm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    insr(zdn, rm);
+  }
+  void Insr(const ZRegister& zdn, const VRegister& vm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    insr(zdn, vm);
+  }
+  void Insr(const ZRegister& zdn, IntegerOperand imm);
+  void Lasta(const Register& rd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    lasta(rd, pg, zn);
+  }
+  void Lasta(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    lasta(vd, pg, zn);
+  }
+  void Lastb(const Register& rd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    lastb(rd, pg, zn);
+  }
+  void Lastb(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    lastb(vd, pg, zn);
+  }
+  void Ld1b(const ZRegister& zt,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+  void Ld1h(const ZRegister& zt,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+  void Ld1w(const ZRegister& zt,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+  void Ld1d(const ZRegister& zt,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr);
+  void Ld1rb(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadBroadcastImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rb,
+                              kBRegSizeInBytes);
+  }
+  void Ld1rh(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadBroadcastImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rh,
+                              kHRegSizeInBytes);
+  }
+  void Ld1rw(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadBroadcastImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rw,
+                              kSRegSizeInBytes);
+  }
+  void Ld1rd(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadBroadcastImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rd,
+                              kDRegSizeInBytes);
+  }
+  void Ld1rqb(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ld1rqd(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ld1rqh(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ld1rqw(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ld1rsb(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadBroadcastImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rsb,
+                              kBRegSizeInBytes);
+  }
+  void Ld1rsh(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadBroadcastImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rsh,
+                              kHRegSizeInBytes);
+  }
+  void Ld1rsw(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadBroadcastImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rsw,
+                              kSRegSizeInBytes);
+  }
+  void Ld1sb(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+  void Ld1sh(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+  void Ld1sw(const ZRegister& zt,
+             const PRegisterZ& pg,
+             const SVEMemOperand& addr);
+  void Ld2b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld2b(zt1, zt2, pg, addr);
+  }
+  void Ld2h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld2h(zt1, zt2, pg, addr);
+  }
+  void Ld2w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld2w(zt1, zt2, pg, addr);
+  }
+  void Ld2d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld2d(zt1, zt2, pg, addr);
+  }
+  void Ld3b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld3b(zt1, zt2, zt3, pg, addr);
+  }
+  void Ld3h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld3h(zt1, zt2, zt3, pg, addr);
+  }
+  void Ld3w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld3w(zt1, zt2, zt3, pg, addr);
+  }
+  void Ld3d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld3d(zt1, zt2, zt3, pg, addr);
+  }
+  void Ld4b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld4b(zt1, zt2, zt3, zt4, pg, addr);
+  }
+  void Ld4h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld4h(zt1, zt2, zt3, zt4, pg, addr);
+  }
+  void Ld4w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld4w(zt1, zt2, zt3, zt4, pg, addr);
+  }
+  void Ld4d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegisterZ& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ld4d(zt1, zt2, zt3, zt4, pg, addr);
+  }
+  void Ldff1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ldff1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ldff1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ldff1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ldff1sb(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+  void Ldff1sh(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+  void Ldff1sw(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr);
+  void Ldff1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const Register& xn,
+              const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1b(zt, pg, xn, zm);
+  }
+  void Ldff1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const ZRegister& zn,
+              int imm5) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1b(zt, pg, zn, imm5);
+  }
+  void Ldff1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const Register& xn,
+              const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1d(zt, pg, xn, zm);
+  }
+  void Ldff1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const ZRegister& zn,
+              int imm5) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1d(zt, pg, zn, imm5);
+  }
+  void Ldff1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const Register& xn,
+              const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1h(zt, pg, xn, zm);
+  }
+  void Ldff1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const ZRegister& zn,
+              int imm5) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1h(zt, pg, zn, imm5);
+  }
+  void Ldff1sb(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const Register& xn,
+               const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1sb(zt, pg, xn, zm);
+  }
+  void Ldff1sb(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const ZRegister& zn,
+               int imm5) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1sb(zt, pg, zn, imm5);
+  }
+  void Ldff1sh(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const Register& xn,
+               const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1sh(zt, pg, xn, zm);
+  }
+  void Ldff1sh(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const ZRegister& zn,
+               int imm5) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1sh(zt, pg, zn, imm5);
+  }
+  void Ldff1sw(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const Register& xn,
+               const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1sw(zt, pg, xn, zm);
+  }
+  void Ldff1sw(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const ZRegister& zn,
+               int imm5) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1sw(zt, pg, zn, imm5);
+  }
+  void Ldff1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const Register& xn,
+              const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1w(zt, pg, xn, zm);
+  }
+  void Ldff1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const ZRegister& zn,
+              int imm5) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldff1w(zt, pg, zn, imm5);
+  }
+  void Ldnf1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldnf1b(zt, pg, addr);
+  }
+  void Ldnf1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldnf1d(zt, pg, addr);
+  }
+  void Ldnf1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldnf1h(zt, pg, addr);
+  }
+  void Ldnf1sb(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldnf1sb(zt, pg, addr);
+  }
+  void Ldnf1sh(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldnf1sh(zt, pg, addr);
+  }
+  void Ldnf1sw(const ZRegister& zt,
+               const PRegisterZ& pg,
+               const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldnf1sw(zt, pg, addr);
+  }
+  void Ldnf1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ldnf1w(zt, pg, addr);
+  }
+  void Ldnt1b(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ldnt1d(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ldnt1h(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ldnt1w(const ZRegister& zt,
+              const PRegisterZ& pg,
+              const SVEMemOperand& addr);
+  void Ldr(const CPURegister& rt, const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadStoreScalarImmHelper(rt, addr, &MacroAssembler::ldr);
+  }
+  void Lsl(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           int shift) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    lsl(zd, pg, zd, shift);
+  }
+  void Lsl(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+  void Lsl(const ZRegister& zd, const ZRegister& zn, int shift) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    lsl(zd, zn, shift);
+  }
+  void Lsl(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    lsl(zd, zn, zm);
+  }
+  void Lsr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           int shift) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    lsr(zd, pg, zd, shift);
+  }
+  void Lsr(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+  void Lsr(const ZRegister& zd, const ZRegister& zn, int shift) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    lsr(zd, zn, shift);
+  }
+  void Lsr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    lsr(zd, zn, zm);
+  }
+  void Mov(const PRegister& pd, const PRegister& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(pd.VnB(), pn.VnB());
+  }
+  void Mov(const PRegisterWithLaneSize& pd,
+           const PRegisterM& pg,
+           const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(pd, pg, pn);
+  }
+  void Mov(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(pd, pg, pn);
+  }
+  void Mov(const ZRegister& zd, const Register& xn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(zd, xn);
+  }
+
+  void Mov(const ZRegister& zd, const VRegister& vn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(zd, vn);
+  }
+
+  void Mov(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(zd, zn);
+  }
+  void Mov(const ZRegister& zd, const ZRegister& zn, unsigned index) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(zd, zn, index);
+  }
+  void Mov(const ZRegister& zd, const PRegister& pg, IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Cpy(zd, pg, imm);
+  }
+  // TODO: support zeroing predicated moves using movprfx.
+  void Mov(const ZRegister& zd, const PRegisterM& pg, const Register& rn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(zd, pg, rn);
+  }
+  void Mov(const ZRegister& zd, const PRegisterM& pg, const VRegister& vn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(zd, pg, vn);
+  }
+  void Mov(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    mov(zd, pg, zn);
+  }
+  void Mov(const ZRegister& zd, IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Dup(zd, imm);
+  }
+  void Movs(const PRegister& pd, const PRegister& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    movs(pd, pn);
+  }
+  void Movs(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    movs(pd, pg, pn);
+  }
+  // zd = za + (zn * zm)
+  void Mla(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& za,
+           const ZRegister& zn,
+           const ZRegister& zm);
+  // zd = za - (zn * zm)
+  void Mls(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& za,
+           const ZRegister& zn,
+           const ZRegister& zm);
+  void Mul(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm);
+  void Nand(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    nand(pd, pg, pn, pm);
+  }
+  void Nands(const PRegisterWithLaneSize& pd,
+             const PRegisterZ& pg,
+             const PRegisterWithLaneSize& pn,
+             const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    nands(pd, pg, pn, pm);
+  }
+  // There is no instruction with this form, but we can implement it using
+  // `subr`.
+  void Neg(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    MovprfxHelperScope guard(this, zd, zn);
+    subr(zd, zd, 0);
+  }
+  void Neg(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    neg(zd, pg, zn);
+  }
+  void Nor(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    nor(pd, pg, pn, pm);
+  }
+  void Nors(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    nors(pd, pg, pn, pm);
+  }
+  void Not(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    not_(pd, pg, pn);
+  }
+  void Not(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    not_(zd, pg, zn);
+  }
+  void Nots(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    nots(pd, pg, pn);
+  }
+  void Orn(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    orn(pd, pg, pn, pm);
+  }
+  void Orn(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (IsImmLogical(imm, zd.GetLaneSizeInBits())) {
+      orn(zd, zn, imm);
+    } else {
+      // TODO: Synthesise the immediate once 'Mov' is implemented.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Orns(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    orns(pd, pg, pn, pm);
+  }
+  void Orr(const PRegisterWithLaneSize& pd,
+           const PRegisterZ& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    orr(pd, pg, pn, pm);
+  }
+  void Orr(const ZRegister& zd, const ZRegister& zn, uint64_t imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    if (IsImmLogical(imm, zd.GetLaneSizeInBits())) {
+      orr(zd, zn, imm);
+    } else {
+      // TODO: Synthesise the immediate once 'Mov' is implemented.
+      VIXL_UNIMPLEMENTED();
+    }
+  }
+  void Orr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameLaneSize(zd, zn, zm));
+    SingleEmissionCheckScope guard(this);
+    orr(zd.VnD(), zn.VnD(), zm.VnD());
+  }
+  void Orrs(const PRegisterWithLaneSize& pd,
+            const PRegisterZ& pg,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    orrs(pd, pg, pn, pm);
+  }
+  void Orv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    orv(vd, pg, zn);
+  }
+  void Pfalse(const PRegister& pd) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(pd.IsUnqualified());
+    SingleEmissionCheckScope guard(this);
+    // No matter what the lane size is, overall this operation just writes zeros
+    // throughout the register.
+    pfalse(pd.VnB());
+  }
+  void Pfirst(const PRegisterWithLaneSize& pd,
+              const PRegister& pg,
+              const PRegisterWithLaneSize& pn);
+  void Pnext(const PRegisterWithLaneSize& pd,
+             const PRegister& pg,
+             const PRegisterWithLaneSize& pn);
+  void Prfb(PrefetchOperation prfop,
+            const PRegister& pg,
+            const SVEMemOperand addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    prfb(prfop, pg, addr);
+  }
+  void Prfh(PrefetchOperation prfop,
+            const PRegister& pg,
+            const SVEMemOperand addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    prfh(prfop, pg, addr);
+  }
+  void Prfw(PrefetchOperation prfop,
+            const PRegister& pg,
+            const SVEMemOperand addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    prfw(prfop, pg, addr);
+  }
+  void Prfd(PrefetchOperation prfop,
+            const PRegister& pg,
+            const SVEMemOperand addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    prfd(prfop, pg, addr);
+  }
+  void Ptest(const PRegister& pg, const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ptest(pg, pn);
+  }
+  void Ptrue(const PRegisterWithLaneSize& pd,
+             SVEPredicateConstraint pattern,
+             FlagsUpdate s);
+  void Ptrue(const PRegisterWithLaneSize& pd,
+             SVEPredicateConstraint pattern = SVE_ALL) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ptrue(pd, pattern);
+  }
+  void Ptrues(const PRegisterWithLaneSize& pd,
+              SVEPredicateConstraint pattern = SVE_ALL) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ptrues(pd, pattern);
+  }
+  void Punpkhi(const PRegisterWithLaneSize& pd,
+               const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    punpkhi(pd, pn);
+  }
+  void Punpklo(const PRegisterWithLaneSize& pd,
+               const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    punpklo(pd, pn);
+  }
+  void Rbit(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    rbit(zd, pg, zn);
+  }
+  void Rdffr(const PRegister& pd) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    // Although this is essentially just a move, it writes every bit and so can
+    // only support b-sized lane because other lane sizes would simplicity clear
+    // bits in `pd`.
+    VIXL_ASSERT(!pd.HasLaneSize() || pd.IsLaneSizeB());
+    VIXL_ASSERT(pd.IsUnqualified());
+    SingleEmissionCheckScope guard(this);
+    rdffr(pd.VnB());
+  }
+  void Rdffr(const PRegisterWithLaneSize& pd, const PRegisterZ& pg) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    rdffr(pd, pg);
+  }
+  void Rdffrs(const PRegisterWithLaneSize& pd, const PRegisterZ& pg) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    rdffrs(pd, pg);
+  }
+  // Note that there is no `rdpl` instruction, but this macro emulates it (for
+  // symmetry with `Rdvl`).
+  void Rdpl(const Register& xd, int64_t multiplier) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Addpl(xd, xzr, multiplier);
+  }
+  void Rdvl(const Register& xd, int64_t multiplier) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    Addvl(xd, xzr, multiplier);
+  }
+  void Rev(const PRegisterWithLaneSize& pd, const PRegisterWithLaneSize& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    rev(pd, pn);
+  }
+  void Rev(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    rev(zd, zn);
+  }
+  void Revb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    revb(zd, pg, zn);
+  }
+  void Revh(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    revh(zd, pg, zn);
+  }
+  void Revw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    revw(zd, pg, zn);
+  }
+  void Saddv(const VRegister& dd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    saddv(dd, pg, zn);
+  }
+  void Scvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    scvtf(zd, pg, zn);
+  }
+  void Sdiv(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+  void Sdot(const ZRegister& zd,
+            const ZRegister& za,
+            const ZRegister& zn,
+            const ZRegister& zm);
+  void Sdot(const ZRegister& zd,
+            const ZRegister& za,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            int index);
+  void Sel(const PRegisterWithLaneSize& pd,
+           const PRegister& pg,
+           const PRegisterWithLaneSize& pn,
+           const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sel(pd, pg, pn, pm);
+  }
+  void Sel(const ZRegister& zd,
+           const PRegister& pg,
+           const ZRegister& zn,
+           const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sel(zd, pg, zn, zm);
+  }
+  void Setffr() {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    setffr();
+  }
+  void Smax(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm);
+  void Smaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    smaxv(vd, pg, zn);
+  }
+  void Smin(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm);
+  void Sminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sminv(vd, pg, zn);
+  }
+  void Splice(const ZRegister& zd,
+              const PRegister& pg,
+              const ZRegister& zn,
+              const ZRegister& zm);
+  void Sqadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqadd(zd, zn, zm);
+  }
+  void Sqadd(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(imm.IsUint8() ||
+                (imm.IsUint16() && ((imm.AsUint16() & 0xff) == 0)));
+    MovprfxHelperScope guard(this, zd, zn);
+    sqadd(zd, zd, imm.AsUint16());
+  }
+  void Sqdecb(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecb(xd, wn, pattern, multiplier);
+  }
+  void Sqdecb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecb(rdn, pattern, multiplier);
+  }
+  void Sqdecd(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecd(xd, wn, pattern, multiplier);
+  }
+  void Sqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecd(rdn, pattern, multiplier);
+  }
+  void Sqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecd(zdn, pattern, multiplier);
+  }
+  void Sqdech(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdech(xd, wn, pattern, multiplier);
+  }
+  void Sqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdech(rdn, pattern, multiplier);
+  }
+  void Sqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdech(zdn, pattern, multiplier);
+  }
+  void Sqdecp(const Register& xdn,
+              const PRegisterWithLaneSize& pg,
+              const Register& wdn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecp(xdn, pg, wdn);
+  }
+  void Sqdecp(const Register& xdn, const PRegisterWithLaneSize& pg) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecp(xdn, pg);
+  }
+  void Sqdecp(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameFormat(zd, zn));
+    // `sqdecp` writes every lane, so use an unpredicated movprfx.
+    MovprfxHelperScope guard(this, zd, zn);
+    sqdecp(zd, pg);
+  }
+  void Sqdecp(const ZRegister& zdn, const PRegister& pg) {
+    Sqdecp(zdn, pg, zdn);
+  }
+  void Sqdecw(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecw(xd, wn, pattern, multiplier);
+  }
+  void Sqdecw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecw(rdn, pattern, multiplier);
+  }
+  void Sqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqdecw(zdn, pattern, multiplier);
+  }
+  void Sqincb(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincb(xd, wn, pattern, multiplier);
+  }
+  void Sqincb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincb(rdn, pattern, multiplier);
+  }
+  void Sqincd(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincd(xd, wn, pattern, multiplier);
+  }
+  void Sqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincd(rdn, pattern, multiplier);
+  }
+  void Sqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincd(zdn, pattern, multiplier);
+  }
+  void Sqinch(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqinch(xd, wn, pattern, multiplier);
+  }
+  void Sqinch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqinch(rdn, pattern, multiplier);
+  }
+  void Sqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqinch(zdn, pattern, multiplier);
+  }
+  void Sqincp(const Register& xdn,
+              const PRegisterWithLaneSize& pg,
+              const Register& wdn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincp(xdn, pg, wdn);
+  }
+  void Sqincp(const Register& xdn, const PRegisterWithLaneSize& pg) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincp(xdn, pg);
+  }
+  void Sqincp(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameFormat(zd, zn));
+    // `sqincp` writes every lane, so use an unpredicated movprfx.
+    MovprfxHelperScope guard(this, zd, zn);
+    sqincp(zd, pg);
+  }
+  void Sqincp(const ZRegister& zdn, const PRegister& pg) {
+    Sqincp(zdn, pg, zdn);
+  }
+  void Sqincw(const Register& xd,
+              const Register& wn,
+              int pattern = SVE_ALL,
+              int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincw(xd, wn, pattern, multiplier);
+  }
+  void Sqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincw(rdn, pattern, multiplier);
+  }
+  void Sqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqincw(zdn, pattern, multiplier);
+  }
+  void Sqsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sqsub(zd, zn, zm);
+  }
+  void Sqsub(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(imm.IsUint8() ||
+                (imm.IsUint16() && ((imm.AsUint16() & 0xff) == 0)));
+    MovprfxHelperScope guard(this, zd, zn);
+    sqsub(zd, zd, imm.AsUint16());
+  }
+  void St1b(const ZRegister& zt,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+  void St1h(const ZRegister& zt,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+  void St1w(const ZRegister& zt,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+  void St1d(const ZRegister& zt,
+            const PRegister& pg,
+            const SVEMemOperand& addr);
+  void St2b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st2b(zt1, zt2, pg, addr);
+  }
+  void St2h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st2h(zt1, zt2, pg, addr);
+  }
+  void St2w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st2w(zt1, zt2, pg, addr);
+  }
+  void St2d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st2d(zt1, zt2, pg, addr);
+  }
+  void St3b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st3b(zt1, zt2, zt3, pg, addr);
+  }
+  void St3h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st3h(zt1, zt2, zt3, pg, addr);
+  }
+  void St3w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st3w(zt1, zt2, zt3, pg, addr);
+  }
+  void St3d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st3d(zt1, zt2, zt3, pg, addr);
+  }
+  void St4b(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st4b(zt1, zt2, zt3, zt4, pg, addr);
+  }
+  void St4h(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st4h(zt1, zt2, zt3, zt4, pg, addr);
+  }
+  void St4w(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st4w(zt1, zt2, zt3, zt4, pg, addr);
+  }
+  void St4d(const ZRegister& zt1,
+            const ZRegister& zt2,
+            const ZRegister& zt3,
+            const ZRegister& zt4,
+            const PRegister& pg,
+            const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    st4d(zt1, zt2, zt3, zt4, pg, addr);
+  }
+  void Stnt1b(const ZRegister& zt,
+              const PRegister& pg,
+              const SVEMemOperand& addr);
+  void Stnt1d(const ZRegister& zt,
+              const PRegister& pg,
+              const SVEMemOperand& addr);
+  void Stnt1h(const ZRegister& zt,
+              const PRegister& pg,
+              const SVEMemOperand& addr);
+  void Stnt1w(const ZRegister& zt,
+              const PRegister& pg,
+              const SVEMemOperand& addr);
+  void Str(const CPURegister& rt, const SVEMemOperand& addr) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SVELoadStoreScalarImmHelper(rt, addr, &MacroAssembler::str);
+  }
+  void Sub(const ZRegister& zd,
+           const PRegisterM& pg,
+           const ZRegister& zn,
+           const ZRegister& zm);
+  void Sub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sub(zd, zn, zm);
+  }
+  void Sub(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    AddSubHelper(kSubImmediate, zd, zn, imm);
+  }
+  void Sub(const ZRegister& zd, IntegerOperand imm, const ZRegister& zm);
+  void Sunpkhi(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sunpkhi(zd, zn);
+  }
+  void Sunpklo(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sunpklo(zd, zn);
+  }
+  void Sxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sxtb(zd, pg, zn);
+  }
+  void Sxth(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sxth(zd, pg, zn);
+  }
+  void Sxtw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    sxtw(zd, pg, zn);
+  }
+  void Tbl(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    tbl(zd, zn, zm);
+  }
+  void Trn1(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    trn1(pd, pn, pm);
+  }
+  void Trn1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    trn1(zd, zn, zm);
+  }
+  void Trn2(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    trn2(pd, pn, pm);
+  }
+  void Trn2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    trn2(zd, zn, zm);
+  }
+  void Uaddv(const VRegister& dd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uaddv(dd, pg, zn);
+  }
+  void Ucvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    ucvtf(zd, pg, zn);
+  }
+  void Udiv(const ZRegister& zd,
+            const PRegisterM& pg,
+            const ZRegister& zn,
+            const ZRegister& zm);
+  void Udot(const ZRegister& zd,
+            const ZRegister& za,
+            const ZRegister& zn,
+            const ZRegister& zm);
+  void Udot(const ZRegister& zd,
+            const ZRegister& za,
+            const ZRegister& zn,
+            const ZRegister& zm,
+            int index);
+  void Umax(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm);
+  void Umaxv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    umaxv(vd, pg, zn);
+  }
+  void Umin(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm);
+  void Uminv(const VRegister& vd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uminv(vd, pg, zn);
+  }
+  void Uqadd(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqadd(zd, zn, zm);
+  }
+  void Uqadd(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(imm.IsUint8() ||
+                (imm.IsUint16() && ((imm.AsUint16() & 0xff) == 0)));
+    MovprfxHelperScope guard(this, zd, zn);
+    uqadd(zd, zd, imm.AsUint16());
+  }
+  void Uqdecb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqdecb(rdn, pattern, multiplier);
+  }
+  void Uqdecd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqdecd(rdn, pattern, multiplier);
+  }
+  void Uqdecd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqdecd(zdn, pattern, multiplier);
+  }
+  void Uqdech(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqdech(rdn, pattern, multiplier);
+  }
+  void Uqdech(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqdech(zdn, pattern, multiplier);
+  }
+  // The saturation is based on the size of `rn`. The result is zero-extended
+  // into `rd`, which must be at least as big.
+  void Uqdecp(const Register& rd,
+              const PRegisterWithLaneSize& pg,
+              const Register& rn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(rd.Aliases(rn));
+    VIXL_ASSERT(rd.GetSizeInBytes() >= rn.GetSizeInBytes());
+    SingleEmissionCheckScope guard(this);
+    if (rn.Is64Bits()) {
+      uqdecp(rd, pg);
+    } else {
+      // Convert <Xd> into <Wd>, to make this more consistent with Sqdecp.
+      uqdecp(rd.W(), pg);
+    }
+  }
+  void Uqdecp(const Register& rdn, const PRegisterWithLaneSize& pg) {
+    Uqdecp(rdn, pg, rdn);
+  }
+  void Uqdecp(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameFormat(zd, zn));
+    // `sqdecp` writes every lane, so use an unpredicated movprfx.
+    MovprfxHelperScope guard(this, zd, zn);
+    uqdecp(zd, pg);
+  }
+  void Uqdecp(const ZRegister& zdn, const PRegister& pg) {
+    Uqdecp(zdn, pg, zdn);
+  }
+  void Uqdecw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqdecw(rdn, pattern, multiplier);
+  }
+  void Uqdecw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqdecw(zdn, pattern, multiplier);
+  }
+  void Uqincb(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqincb(rdn, pattern, multiplier);
+  }
+  void Uqincd(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqincd(rdn, pattern, multiplier);
+  }
+  void Uqincd(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqincd(zdn, pattern, multiplier);
+  }
+  void Uqinch(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqinch(rdn, pattern, multiplier);
+  }
+  void Uqinch(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqinch(zdn, pattern, multiplier);
+  }
+  // The saturation is based on the size of `rn`. The result is zero-extended
+  // into `rd`, which must be at least as big.
+  void Uqincp(const Register& rd,
+              const PRegisterWithLaneSize& pg,
+              const Register& rn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(rd.Aliases(rn));
+    VIXL_ASSERT(rd.GetSizeInBytes() >= rn.GetSizeInBytes());
+    SingleEmissionCheckScope guard(this);
+    if (rn.Is64Bits()) {
+      uqincp(rd, pg);
+    } else {
+      // Convert <Xd> into <Wd>, to make this more consistent with Sqincp.
+      uqincp(rd.W(), pg);
+    }
+  }
+  void Uqincp(const Register& rdn, const PRegisterWithLaneSize& pg) {
+    Uqincp(rdn, pg, rdn);
+  }
+  void Uqincp(const ZRegister& zd, const PRegister& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(AreSameFormat(zd, zn));
+    // `sqincp` writes every lane, so use an unpredicated movprfx.
+    MovprfxHelperScope guard(this, zd, zn);
+    uqincp(zd, pg);
+  }
+  void Uqincp(const ZRegister& zdn, const PRegister& pg) {
+    Uqincp(zdn, pg, zdn);
+  }
+  void Uqincw(const Register& rdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqincw(rdn, pattern, multiplier);
+  }
+  void Uqincw(const ZRegister& zdn, int pattern = SVE_ALL, int multiplier = 1) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqincw(zdn, pattern, multiplier);
+  }
+  void Uqsub(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uqsub(zd, zn, zm);
+  }
+  void Uqsub(const ZRegister& zd, const ZRegister& zn, IntegerOperand imm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    VIXL_ASSERT(imm.IsUint8() ||
+                (imm.IsUint16() && ((imm.AsUint16() & 0xff) == 0)));
+    MovprfxHelperScope guard(this, zd, zn);
+    uqsub(zd, zd, imm.AsUint16());
+  }
+  void Uunpkhi(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uunpkhi(zd, zn);
+  }
+  void Uunpklo(const ZRegister& zd, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uunpklo(zd, zn);
+  }
+  void Uxtb(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uxtb(zd, pg, zn);
+  }
+  void Uxth(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uxth(zd, pg, zn);
+  }
+  void Uxtw(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uxtw(zd, pg, zn);
+  }
+  void Uzp1(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uzp1(pd, pn, pm);
+  }
+  void Uzp1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uzp1(zd, zn, zm);
+  }
+  void Uzp2(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uzp2(pd, pn, pm);
+  }
+  void Uzp2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    uzp2(zd, zn, zm);
+  }
+  void Whilele(const PRegisterWithLaneSize& pd,
+               const Register& rn,
+               const Register& rm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    whilele(pd, rn, rm);
+  }
+  void Whilelo(const PRegisterWithLaneSize& pd,
+               const Register& rn,
+               const Register& rm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    whilelo(pd, rn, rm);
+  }
+  void Whilels(const PRegisterWithLaneSize& pd,
+               const Register& rn,
+               const Register& rm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    whilels(pd, rn, rm);
+  }
+  void Whilelt(const PRegisterWithLaneSize& pd,
+               const Register& rn,
+               const Register& rm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    whilelt(pd, rn, rm);
+  }
+  void Wrffr(const PRegister& pn) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    // Although this is essentially just a move, it writes every bit and so can
+    // only support b-sized lane because other lane sizes would implicitly clear
+    // bits in `ffr`.
+    VIXL_ASSERT(!pn.HasLaneSize() || pn.IsLaneSizeB());
+    VIXL_ASSERT(pn.IsUnqualified());
+    SingleEmissionCheckScope guard(this);
+    wrffr(pn.VnB());
+  }
+  void Zip1(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    zip1(pd, pn, pm);
+  }
+  void Zip1(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    zip1(zd, zn, zm);
+  }
+  void Zip2(const PRegisterWithLaneSize& pd,
+            const PRegisterWithLaneSize& pn,
+            const PRegisterWithLaneSize& pm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    zip2(pd, pn, pm);
+  }
+  void Zip2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) {
+    VIXL_ASSERT(allow_macro_instructions_);
+    SingleEmissionCheckScope guard(this);
+    zip2(zd, zn, zm);
+  }
+
   template <typename T>
   Literal<T>* CreateLiteralDestroyedWithPool(T value) {
     return new Literal<T>(value,
@@ -3480,11 +6489,13 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
     return GetScratchRegisterList();
   }
 
-  CPURegList* GetScratchVRegisterList() { return &fptmp_list_; }
+  CPURegList* GetScratchVRegisterList() { return &v_tmp_list_; }
   VIXL_DEPRECATED("GetScratchVRegisterList", CPURegList* FPTmpList()) {
     return GetScratchVRegisterList();
   }
 
+  CPURegList* GetScratchPRegisterList() { return &p_tmp_list_; }
+
   // Get or set the current (most-deeply-nested) UseScratchRegisterScope.
   void SetCurrentScratchRegisterScope(UseScratchRegisterScope* scope) {
     current_scratch_scope_ = scope;
@@ -3548,16 +6559,6 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   // Will output the flags.
   void Log(TraceParameters parameters);
 
-  // Enable or disable instrumentation when an Instrument visitor is attached to
-  // the simulator.
-  void EnableInstrumentation();
-  void DisableInstrumentation();
-
-  // Add a marker to the instrumentation data produced by an Instrument visitor.
-  // The name is a two character string that will be attached to the marker in
-  // the output data.
-  void AnnotateInstrumentation(const char* marker_name);
-
   // Enable or disable CPU features dynamically. This mechanism allows users to
   // strictly check the use of CPU features in different regions of code.
   void SetSimulatorCPUFeatures(const CPUFeatures& features);
@@ -3661,6 +6662,36 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
                                                Condition cond,
                                                bool* should_synthesise_left);
 
+  // Generate code to calculate the address represented by `addr` and write it
+  // into `xd`. This is used as a common fall-back for out-of-range load and
+  // store operands.
+  //
+  // The vl_divisor_log2 argument is used to scale the VL, for use with
+  // SVE_MUL_VL.
+  void CalculateSVEAddress(const Register& xd,
+                           const SVEMemOperand& addr,
+                           int vl_divisor_log2 = 0);
+
+  void CalculateSVEAddress(const Register& xd,
+                           const SVEMemOperand& addr,
+                           const CPURegister& rt) {
+    VIXL_ASSERT(rt.IsPRegister() || rt.IsZRegister());
+    int vl_divisor_log2 = rt.IsPRegister() ? kZRegBitsPerPRegBitLog2 : 0;
+    CalculateSVEAddress(xd, addr, vl_divisor_log2);
+  }
+
+  void SetFPNaNPropagationOption(FPMacroNaNPropagationOption nan_option) {
+    fp_nan_propagation_ = nan_option;
+  }
+
+  void ResolveFPNaNPropagationOption(FPMacroNaNPropagationOption* nan_option) {
+    // The input option has priority over the option that has set.
+    if (*nan_option == NoFPMacroNaNPropagationSelected) {
+      *nan_option = fp_nan_propagation_;
+    }
+    VIXL_ASSERT(*nan_option != NoFPMacroNaNPropagationSelected);
+  }
+
  private:
   // The actual Push and Pop implementations. These don't generate any code
   // other than that required for the push or pop. This allows
@@ -3714,6 +6745,183 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   void ConfigureSimulatorCPUFeaturesHelper(const CPUFeatures& features,
                                            DebugHltOpcode action);
 
+  void CompareHelper(Condition cond,
+                     const PRegisterWithLaneSize& pd,
+                     const PRegisterZ& pg,
+                     const ZRegister& zn,
+                     IntegerOperand imm);
+
+  // E.g. Ld1rb.
+  typedef void (Assembler::*SVELoadBroadcastFn)(const ZRegister& zt,
+                                                const PRegisterZ& pg,
+                                                const SVEMemOperand& addr);
+
+  void SVELoadBroadcastImmHelper(const ZRegister& zt,
+                                 const PRegisterZ& pg,
+                                 const SVEMemOperand& addr,
+                                 SVELoadBroadcastFn fn,
+                                 int divisor);
+
+  // E.g. ldr/str
+  typedef void (Assembler::*SVELoadStoreFn)(const CPURegister& rt,
+                                            const SVEMemOperand& addr);
+
+  void SVELoadStoreScalarImmHelper(const CPURegister& rt,
+                                   const SVEMemOperand& addr,
+                                   SVELoadStoreFn fn);
+
+  typedef void (Assembler::*SVELoad1Fn)(const ZRegister& zt,
+                                        const PRegisterZ& pg,
+                                        const SVEMemOperand& addr);
+  typedef void (Assembler::*SVEStore1Fn)(const ZRegister& zt,
+                                         const PRegister& pg,
+                                         const SVEMemOperand& addr);
+
+  // Helper for predicated Z register loads with addressing modes not directly
+  // encodable in the instruction. The supported_modifier parameter indicates
+  // which offset modifier the calling instruction encoder supports (eg.
+  // SVE_MUL_VL). The ratio log2 of VL to memory access size is passed as
+  // vl_divisor_log2; pass -1 to indicate no dependency.
+  template <typename Tg, typename Tf>
+  void SVELoadStoreScalarImmHelper(
+      const ZRegister& zt,
+      const Tg& pg,
+      const SVEMemOperand& addr,
+      Tf fn,
+      int imm_bits,
+      int shift_amount,
+      SVEOffsetModifier supported_modifier = NO_SVE_OFFSET_MODIFIER,
+      int vl_divisor_log2 = 0);
+
+  template <typename Tg, typename Tf>
+  void SVELoadStore1Helper(int msize_in_bytes_log2,
+                           const ZRegister& zt,
+                           const Tg& pg,
+                           const SVEMemOperand& addr,
+                           Tf fn);
+
+  template <typename Tf>
+  void SVELoadFFHelper(int msize_in_bytes_log2,
+                       const ZRegister& zt,
+                       const PRegisterZ& pg,
+                       const SVEMemOperand& addr,
+                       Tf fn);
+
+  typedef void (MacroAssembler::*IntWideImmMacroFn)(const ZRegister& zd,
+                                                    const ZRegister& zn,
+                                                    IntegerOperand imm);
+
+  typedef void (Assembler::*IntWideImmShiftFn)(const ZRegister& zd,
+                                               const ZRegister& zn,
+                                               int imm,
+                                               int shift);
+
+  typedef void (Assembler::*IntArithFn)(const ZRegister& zd,
+                                        const ZRegister& zn,
+                                        const ZRegister& zm);
+
+  typedef void (Assembler::*IntWideImmFn)(const ZRegister& zd,
+                                          const ZRegister& zn,
+                                          int imm);
+
+  typedef void (Assembler::*IntArithIndexFn)(const ZRegister& zd,
+                                             const ZRegister& zn,
+                                             const ZRegister& zm,
+                                             int index);
+
+  typedef void (MacroAssembler::*SVEArithPredicatedFn)(const ZRegister& zd,
+                                                       const PRegisterM& pg,
+                                                       const ZRegister& zn,
+                                                       const ZRegister& zm);
+
+  void IntWideImmHelper(IntWideImmFn imm_fn,
+                        SVEArithPredicatedFn reg_fn,
+                        const ZRegister& zd,
+                        const ZRegister& zn,
+                        IntegerOperand imm,
+                        bool is_signed_imm);
+
+  enum AddSubHelperOption { kAddImmediate, kSubImmediate };
+
+  void AddSubHelper(AddSubHelperOption option,
+                    const ZRegister& zd,
+                    const ZRegister& zn,
+                    IntegerOperand imm);
+
+  // Try to emit an add- or sub-like instruction (imm_fn) with `imm`, or the
+  // corresponding sub- or add-like instruction (n_imm_fn) with a negated `imm`.
+  // A `movprfx` is automatically generated if one is required. If successful,
+  // return true. Otherwise, return false.
+  //
+  // This helper uses two's complement equivalences, for example treating 0xffff
+  // as -1 for H-sized lanes.
+  bool TrySingleAddSub(AddSubHelperOption option,
+                       const ZRegister& zd,
+                       const ZRegister& zn,
+                       IntegerOperand imm);
+
+  void SVESdotUdotHelper(IntArithFn fn,
+                         const ZRegister& zd,
+                         const ZRegister& za,
+                         const ZRegister& zn,
+                         const ZRegister& zm);
+
+  void SVESdotUdotIndexHelper(IntArithIndexFn fn,
+                              const ZRegister& zd,
+                              const ZRegister& za,
+                              const ZRegister& zn,
+                              const ZRegister& zm,
+                              int index);
+
+  // For noncommutative arithmetic operations.
+  void NoncommutativeArithmeticHelper(const ZRegister& zd,
+                                      const PRegisterM& pg,
+                                      const ZRegister& zn,
+                                      const ZRegister& zm,
+                                      SVEArithPredicatedFn fn,
+                                      SVEArithPredicatedFn rev_fn);
+
+  void FPCommutativeArithmeticHelper(const ZRegister& zd,
+                                     const PRegisterM& pg,
+                                     const ZRegister& zn,
+                                     const ZRegister& zm,
+                                     SVEArithPredicatedFn fn,
+                                     FPMacroNaNPropagationOption nan_option);
+
+  // Floating-point fused multiply-add vectors (predicated), writing addend.
+  typedef void (Assembler::*SVEMulAddPredicatedZdaFn)(const ZRegister& zda,
+                                                      const PRegisterM& pg,
+                                                      const ZRegister& zn,
+                                                      const ZRegister& zm);
+
+  // Floating-point fused multiply-add vectors (predicated), writing
+  // multiplicand.
+  typedef void (Assembler::*SVEMulAddPredicatedZdnFn)(const ZRegister& zdn,
+                                                      const PRegisterM& pg,
+                                                      const ZRegister& zn,
+                                                      const ZRegister& zm);
+
+  void FPMulAddHelper(const ZRegister& zd,
+                      const PRegisterM& pg,
+                      const ZRegister& za,
+                      const ZRegister& zn,
+                      const ZRegister& zm,
+                      SVEMulAddPredicatedZdaFn fn_zda,
+                      SVEMulAddPredicatedZdnFn fn_zdn,
+                      FPMacroNaNPropagationOption nan_option);
+
+  typedef void (Assembler::*SVEMulAddIndexFn)(const ZRegister& zda,
+                                              const ZRegister& zn,
+                                              const ZRegister& zm,
+                                              int index);
+
+  void FPMulAddIndexHelper(SVEMulAddIndexFn fn,
+                           const ZRegister& zd,
+                           const ZRegister& za,
+                           const ZRegister& zn,
+                           const ZRegister& zm,
+                           int index);
+
   // Tell whether any of the macro instruction can be used. When false the
   // MacroAssembler will assert if a method which can emit a variable number
   // of instructions is called.
@@ -3727,7 +6935,8 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
 
   // Scratch registers available for use by the MacroAssembler.
   CPURegList tmp_list_;
-  CPURegList fptmp_list_;
+  CPURegList v_tmp_list_;
+  CPURegList p_tmp_list_;
 
   UseScratchRegisterScope* current_scratch_scope_;
 
@@ -3737,6 +6946,8 @@ class MacroAssembler : public Assembler, public MacroAssemblerInterface {
   ptrdiff_t checkpoint_;
   ptrdiff_t recommended_checkpoint_;
 
+  FPMacroNaNPropagationOption fp_nan_propagation_;
+
   friend class Pool;
   friend class LiteralPool;
 };
@@ -3805,11 +7016,35 @@ class BlockPoolsScope {
   MacroAssembler* masm_;
 };
 
+MovprfxHelperScope::MovprfxHelperScope(MacroAssembler* masm,
+                                       const ZRegister& dst,
+                                       const ZRegister& src)
+    : ExactAssemblyScope(masm,
+                         ShouldGenerateMovprfx(dst, src)
+                             ? (2 * kInstructionSize)
+                             : kInstructionSize) {
+  if (ShouldGenerateMovprfx(dst, src)) {
+    masm->movprfx(dst, src);
+  }
+}
+
+MovprfxHelperScope::MovprfxHelperScope(MacroAssembler* masm,
+                                       const ZRegister& dst,
+                                       const PRegister& pg,
+                                       const ZRegister& src)
+    : ExactAssemblyScope(masm,
+                         ShouldGenerateMovprfx(dst, pg, src)
+                             ? (2 * kInstructionSize)
+                             : kInstructionSize) {
+  if (ShouldGenerateMovprfx(dst, pg, src)) {
+    masm->movprfx(dst, pg, src);
+  }
+}
 
 // This scope utility allows scratch registers to be managed safely. The
-// MacroAssembler's GetScratchRegisterList() (and GetScratchVRegisterList()) is
-// used as a pool of scratch registers. These registers can be allocated on
-// demand, and will be returned at the end of the scope.
+// MacroAssembler's GetScratch*RegisterList() are used as a pool of scratch
+// registers. These registers can be allocated on demand, and will be returned
+// at the end of the scope.
 //
 // When the scope ends, the MacroAssembler's lists will be restored to their
 // original state, even if the lists were modified by some other means.
@@ -3819,14 +7054,22 @@ class UseScratchRegisterScope {
   // must not be `NULL`), so it is ready to use immediately after it has been
   // constructed.
   explicit UseScratchRegisterScope(MacroAssembler* masm)
-      : masm_(NULL), parent_(NULL), old_available_(0), old_available_v_(0) {
+      : masm_(NULL),
+        parent_(NULL),
+        old_available_(0),
+        old_available_v_(0),
+        old_available_p_(0) {
     Open(masm);
   }
   // This constructor does not implicitly initialise the scope. Instead, the
   // user is required to explicitly call the `Open` function before using the
   // scope.
   UseScratchRegisterScope()
-      : masm_(NULL), parent_(NULL), old_available_(0), old_available_v_(0) {}
+      : masm_(NULL),
+        parent_(NULL),
+        old_available_(0),
+        old_available_v_(0),
+        old_available_p_(0) {}
 
   // This function performs the actual initialisation work.
   void Open(MacroAssembler* masm);
@@ -3841,25 +7084,42 @@ class UseScratchRegisterScope {
 
   bool IsAvailable(const CPURegister& reg) const;
 
-
   // Take a register from the appropriate temps list. It will be returned
   // automatically when the scope ends.
   Register AcquireW() {
-    return AcquireNextAvailable(masm_->GetScratchRegisterList()).W();
+    return AcquireFrom(masm_->GetScratchRegisterList()).W();
   }
   Register AcquireX() {
-    return AcquireNextAvailable(masm_->GetScratchRegisterList()).X();
+    return AcquireFrom(masm_->GetScratchRegisterList()).X();
   }
   VRegister AcquireH() {
-    return AcquireNextAvailable(masm_->GetScratchVRegisterList()).H();
+    return AcquireFrom(masm_->GetScratchVRegisterList()).H();
   }
   VRegister AcquireS() {
-    return AcquireNextAvailable(masm_->GetScratchVRegisterList()).S();
+    return AcquireFrom(masm_->GetScratchVRegisterList()).S();
   }
   VRegister AcquireD() {
-    return AcquireNextAvailable(masm_->GetScratchVRegisterList()).D();
+    return AcquireFrom(masm_->GetScratchVRegisterList()).D();
+  }
+  ZRegister AcquireZ() {
+    return AcquireFrom(masm_->GetScratchVRegisterList()).Z();
+  }
+  PRegister AcquireP() {
+    // Prefer to allocate p8-p15 if we can, to leave p0-p7 available for use as
+    // governing predicates.
+    CPURegList* available = masm_->GetScratchPRegisterList();
+    RegList preferred = ~kGoverningPRegisterMask;
+    if ((available->GetList() & preferred) != 0) {
+      return AcquireFrom(available, preferred).P();
+    }
+    return AcquireFrom(available).P();
+  }
+  // Acquire a P register suitable for use as a governing predicate in
+  // instructions which only accept p0-p7 for that purpose.
+  PRegister AcquireGoverningP() {
+    CPURegList* available = masm_->GetScratchPRegisterList();
+    return AcquireFrom(available, kGoverningPRegisterMask).P();
   }
-
 
   Register AcquireRegisterOfSize(int size_in_bits);
   Register AcquireSameSizeAs(const Register& reg) {
@@ -3875,6 +7135,12 @@ class UseScratchRegisterScope {
                : CPURegister(AcquireRegisterOfSize(size_in_bits));
   }
 
+  // Acquire a register big enough to represent one lane of `vector`.
+  Register AcquireRegisterToHoldLane(const CPURegister& vector) {
+    VIXL_ASSERT(vector.GetLaneSizeInBits() <= kXRegSize);
+    return (vector.GetLaneSizeInBits() > kWRegSize) ? AcquireX() : AcquireW();
+  }
+
 
   // Explicitly release an acquired (or excluded) register, putting it back in
   // the appropriate temps list.
@@ -3892,6 +7158,10 @@ class UseScratchRegisterScope {
                const VRegister& reg2 = NoVReg,
                const VRegister& reg3 = NoVReg,
                const VRegister& reg4 = NoVReg);
+  void Include(const CPURegister& reg1,
+               const CPURegister& reg2 = NoCPUReg,
+               const CPURegister& reg3 = NoCPUReg,
+               const CPURegister& reg4 = NoCPUReg);
 
 
   // Make sure that the specified registers are not available in this scope.
@@ -3911,21 +7181,40 @@ class UseScratchRegisterScope {
                const CPURegister& reg3 = NoCPUReg,
                const CPURegister& reg4 = NoCPUReg);
 
+  // Convenience for excluding registers that are part of Operands. This is
+  // useful for sequences like this:
+  //
+  //    // Use 'rd' as a scratch, but only if it's not aliased by an input.
+  //    temps.Include(rd);
+  //    temps.Exclude(rn);
+  //    temps.Exclude(operand);
+  //
+  // Otherwise, a conditional check is needed on the last 'Exclude'.
+  void Exclude(const Operand& operand) {
+    if (operand.IsShiftedRegister() || operand.IsExtendedRegister()) {
+      Exclude(operand.GetRegister());
+    } else {
+      VIXL_ASSERT(operand.IsImmediate());
+    }
+  }
 
   // Prevent any scratch registers from being used in this scope.
   void ExcludeAll();
 
  private:
-  static CPURegister AcquireNextAvailable(CPURegList* available);
+  static CPURegister AcquireFrom(CPURegList* available,
+                                 RegList mask = ~static_cast<RegList>(0));
 
   static void ReleaseByCode(CPURegList* available, int code);
-
   static void ReleaseByRegList(CPURegList* available, RegList regs);
-
   static void IncludeByRegList(CPURegList* available, RegList exclude);
-
   static void ExcludeByRegList(CPURegList* available, RegList exclude);
 
+  CPURegList* GetAvailableListFor(CPURegister::RegisterBank bank);
+
+  static const RegList kGoverningPRegisterMask =
+      (static_cast<RegList>(1) << kNumberOfGoverningPRegisters) - 1;
+
   // The MacroAssembler maintains a list of available scratch registers, and
   // also keeps track of the most recently-opened scope so that on destruction
   // we can check that scopes do not outlive their parents.
@@ -3934,7 +7223,8 @@ class UseScratchRegisterScope {
 
   // The state of the available lists at the start of this scope.
   RegList old_available_;    // kRegister
-  RegList old_available_v_;  // kVRegister
+  RegList old_available_v_;  // kVRegister / kZRegister
+  RegList old_available_p_;  // kPRegister
 
   // Disallow copy constructor and operator=.
   VIXL_NO_RETURN_IN_DEBUG_MODE UseScratchRegisterScope(
@@ -3955,23 +7245,11 @@ class UseScratchRegisterScope {
 // features needs a corresponding macro instruction.
 class SimulationCPUFeaturesScope {
  public:
-  explicit SimulationCPUFeaturesScope(
-      MacroAssembler* masm,
-      CPUFeatures::Feature feature0 = CPUFeatures::kNone,
-      CPUFeatures::Feature feature1 = CPUFeatures::kNone,
-      CPUFeatures::Feature feature2 = CPUFeatures::kNone,
-      CPUFeatures::Feature feature3 = CPUFeatures::kNone)
-      : masm_(masm),
-        cpu_features_scope_(masm, feature0, feature1, feature2, feature3) {
-    masm_->SaveSimulatorCPUFeatures();
-    masm_->EnableSimulatorCPUFeatures(
-        CPUFeatures(feature0, feature1, feature2, feature3));
-  }
-
-  SimulationCPUFeaturesScope(MacroAssembler* masm, const CPUFeatures& other)
-      : masm_(masm), cpu_features_scope_(masm, other) {
+  template <typename... T>
+  explicit SimulationCPUFeaturesScope(MacroAssembler* masm, T... features)
+      : masm_(masm), cpu_features_scope_(masm, features...) {
     masm_->SaveSimulatorCPUFeatures();
-    masm_->EnableSimulatorCPUFeatures(other);
+    masm_->EnableSimulatorCPUFeatures(CPUFeatures(features...));
   }
 
   ~SimulationCPUFeaturesScope() { masm_->RestoreSimulatorCPUFeatures(); }
diff --git a/src/aarch64/macro-assembler-sve-aarch64.cc b/src/aarch64/macro-assembler-sve-aarch64.cc
new file mode 100644
index 00000000..b107f132
--- /dev/null
+++ b/src/aarch64/macro-assembler-sve-aarch64.cc
@@ -0,0 +1,2027 @@
+// Copyright 2019, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "macro-assembler-aarch64.h"
+
+namespace vixl {
+namespace aarch64 {
+
+void MacroAssembler::AddSubHelper(AddSubHelperOption option,
+                                  const ZRegister& zd,
+                                  const ZRegister& zn,
+                                  IntegerOperand imm) {
+  VIXL_ASSERT(imm.FitsInLane(zd));
+
+  // Simple, encodable cases.
+  if (TrySingleAddSub(option, zd, zn, imm)) return;
+
+  VIXL_ASSERT((option == kAddImmediate) || (option == kSubImmediate));
+  bool add_imm = (option == kAddImmediate);
+
+  // Try to translate Add(..., -imm) to Sub(..., imm) if we can encode it in one
+  // instruction. Also interpret the immediate as signed, so we can convert
+  // Add(zd.VnH(), zn.VnH(), 0xffff...) to Sub(..., 1), etc.
+  IntegerOperand signed_imm(imm.AsIntN(zd.GetLaneSizeInBits()));
+  if (signed_imm.IsNegative()) {
+    AddSubHelperOption n_option = add_imm ? kSubImmediate : kAddImmediate;
+    IntegerOperand n_imm(signed_imm.GetMagnitude());
+    // IntegerOperand can represent -INT_MIN, so this is always safe.
+    VIXL_ASSERT(n_imm.IsPositiveOrZero());
+    if (TrySingleAddSub(n_option, zd, zn, n_imm)) return;
+  }
+
+  // Otherwise, fall back to dup + ADD_z_z/SUB_z_z.
+  UseScratchRegisterScope temps(this);
+  ZRegister scratch = temps.AcquireZ().WithLaneSize(zn.GetLaneSizeInBits());
+  Dup(scratch, imm);
+
+  SingleEmissionCheckScope guard(this);
+  if (add_imm) {
+    add(zd, zn, scratch);
+  } else {
+    sub(zd, zn, scratch);
+  }
+}
+
+bool MacroAssembler::TrySingleAddSub(AddSubHelperOption option,
+                                     const ZRegister& zd,
+                                     const ZRegister& zn,
+                                     IntegerOperand imm) {
+  VIXL_ASSERT(imm.FitsInLane(zd));
+
+  int imm8;
+  int shift = -1;
+  if (imm.TryEncodeAsShiftedUintNForLane<8, 0>(zd, &imm8, &shift) ||
+      imm.TryEncodeAsShiftedUintNForLane<8, 8>(zd, &imm8, &shift)) {
+    MovprfxHelperScope guard(this, zd, zn);
+    switch (option) {
+      case kAddImmediate:
+        add(zd, zd, imm8, shift);
+        return true;
+      case kSubImmediate:
+        sub(zd, zd, imm8, shift);
+        return true;
+    }
+  }
+  return false;
+}
+
+void MacroAssembler::IntWideImmHelper(IntWideImmFn imm_fn,
+                                      SVEArithPredicatedFn reg_macro,
+                                      const ZRegister& zd,
+                                      const ZRegister& zn,
+                                      IntegerOperand imm,
+                                      bool is_signed) {
+  if (is_signed) {
+    // E.g. MUL_z_zi, SMIN_z_zi, SMAX_z_zi
+    if (imm.IsInt8()) {
+      MovprfxHelperScope guard(this, zd, zn);
+      (this->*imm_fn)(zd, zd, imm.AsInt8());
+      return;
+    }
+  } else {
+    // E.g. UMIN_z_zi, UMAX_z_zi
+    if (imm.IsUint8()) {
+      MovprfxHelperScope guard(this, zd, zn);
+      (this->*imm_fn)(zd, zd, imm.AsUint8());
+      return;
+    }
+  }
+
+  UseScratchRegisterScope temps(this);
+  PRegister pg = temps.AcquireGoverningP();
+  Ptrue(pg.WithSameLaneSizeAs(zd));
+
+  // Try to re-use zd if we can, so we can avoid a movprfx.
+  ZRegister scratch =
+      zd.Aliases(zn) ? temps.AcquireZ().WithLaneSize(zn.GetLaneSizeInBits())
+                     : zd;
+  Dup(scratch, imm);
+
+  // The vector-form macro for commutative operations will swap the arguments to
+  // avoid movprfx, if necessary.
+  (this->*reg_macro)(zd, pg.Merging(), zn, scratch);
+}
+
+void MacroAssembler::Mul(const ZRegister& zd,
+                         const ZRegister& zn,
+                         IntegerOperand imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  IntWideImmFn imm_fn = &Assembler::mul;
+  SVEArithPredicatedFn reg_fn = &MacroAssembler::Mul;
+  IntWideImmHelper(imm_fn, reg_fn, zd, zn, imm, true);
+}
+
+void MacroAssembler::Smin(const ZRegister& zd,
+                          const ZRegister& zn,
+                          IntegerOperand imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(imm.FitsInSignedLane(zd));
+  IntWideImmFn imm_fn = &Assembler::smin;
+  SVEArithPredicatedFn reg_fn = &MacroAssembler::Smin;
+  IntWideImmHelper(imm_fn, reg_fn, zd, zn, imm, true);
+}
+
+void MacroAssembler::Smax(const ZRegister& zd,
+                          const ZRegister& zn,
+                          IntegerOperand imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(imm.FitsInSignedLane(zd));
+  IntWideImmFn imm_fn = &Assembler::smax;
+  SVEArithPredicatedFn reg_fn = &MacroAssembler::Smax;
+  IntWideImmHelper(imm_fn, reg_fn, zd, zn, imm, true);
+}
+
+void MacroAssembler::Umax(const ZRegister& zd,
+                          const ZRegister& zn,
+                          IntegerOperand imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(imm.FitsInUnsignedLane(zd));
+  IntWideImmFn imm_fn = &Assembler::umax;
+  SVEArithPredicatedFn reg_fn = &MacroAssembler::Umax;
+  IntWideImmHelper(imm_fn, reg_fn, zd, zn, imm, false);
+}
+
+void MacroAssembler::Umin(const ZRegister& zd,
+                          const ZRegister& zn,
+                          IntegerOperand imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(imm.FitsInUnsignedLane(zd));
+  IntWideImmFn imm_fn = &Assembler::umin;
+  SVEArithPredicatedFn reg_fn = &MacroAssembler::Umin;
+  IntWideImmHelper(imm_fn, reg_fn, zd, zn, imm, false);
+}
+
+void MacroAssembler::Addpl(const Register& xd,
+                           const Register& xn,
+                           int64_t multiplier) {
+  VIXL_ASSERT(allow_macro_instructions_);
+
+  // This macro relies on `Rdvl` to handle some out-of-range cases. Check that
+  // `VL * multiplier` cannot overflow, for any possible value of VL.
+  VIXL_ASSERT(multiplier <= (INT64_MAX / kZRegMaxSizeInBytes));
+  VIXL_ASSERT(multiplier >= (INT64_MIN / kZRegMaxSizeInBytes));
+
+  if (xd.IsZero()) return;
+  if (xn.IsZero() && xd.IsSP()) {
+    // TODO: This operation doesn't make much sense, but we could support it
+    // with a scratch register if necessary.
+    VIXL_UNIMPLEMENTED();
+  }
+
+  // Handling xzr requires an extra move, so defer it until later so we can try
+  // to use `rdvl` instead (via `Addvl`).
+  if (IsInt6(multiplier) && !xn.IsZero()) {
+    SingleEmissionCheckScope guard(this);
+    addpl(xd, xn, static_cast<int>(multiplier));
+    return;
+  }
+
+  // If `multiplier` is a multiple of 8, we can use `Addvl` instead.
+  if ((multiplier % kZRegBitsPerPRegBit) == 0) {
+    Addvl(xd, xn, multiplier / kZRegBitsPerPRegBit);
+    return;
+  }
+
+  if (IsInt6(multiplier)) {
+    VIXL_ASSERT(xn.IsZero());  // Other cases were handled with `addpl`.
+    // There is no simple `rdpl` instruction, and `addpl` cannot accept xzr, so
+    // materialise a zero.
+    MacroEmissionCheckScope guard(this);
+    movz(xd, 0);
+    addpl(xd, xd, static_cast<int>(multiplier));
+    return;
+  }
+
+  // TODO: Some probable cases result in rather long sequences. For example,
+  // `Addpl(sp, sp, 33)` requires five instructions, even though it's only just
+  // outside the encodable range. We should look for ways to cover such cases
+  // without drastically increasing the complexity of this logic.
+
+  // For other cases, calculate xn + (PL * multiplier) using discrete
+  // instructions. This requires two scratch registers in the general case, so
+  // try to re-use the destination as a scratch register.
+  UseScratchRegisterScope temps(this);
+  temps.Include(xd);
+  temps.Exclude(xn);
+
+  Register scratch = temps.AcquireX();
+  // Because there is no `rdpl`, so we have to calculate PL from VL. We can't
+  // scale the multiplier because (we already know) it isn't a multiple of 8.
+  Rdvl(scratch, multiplier);
+
+  MacroEmissionCheckScope guard(this);
+  if (xn.IsZero()) {
+    asr(xd, scratch, kZRegBitsPerPRegBitLog2);
+  } else if (xd.IsSP() || xn.IsSP()) {
+    // TODO: MacroAssembler::Add should be able to handle this.
+    asr(scratch, scratch, kZRegBitsPerPRegBitLog2);
+    add(xd, xn, scratch);
+  } else {
+    add(xd, xn, Operand(scratch, ASR, kZRegBitsPerPRegBitLog2));
+  }
+}
+
+void MacroAssembler::Addvl(const Register& xd,
+                           const Register& xn,
+                           int64_t multiplier) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(xd.IsX());
+  VIXL_ASSERT(xn.IsX());
+
+  // Check that `VL * multiplier` cannot overflow, for any possible value of VL.
+  VIXL_ASSERT(multiplier <= (INT64_MAX / kZRegMaxSizeInBytes));
+  VIXL_ASSERT(multiplier >= (INT64_MIN / kZRegMaxSizeInBytes));
+
+  if (xd.IsZero()) return;
+  if (xn.IsZero() && xd.IsSP()) {
+    // TODO: This operation doesn't make much sense, but we could support it
+    // with a scratch register if necessary. `rdvl` cannot write into `sp`.
+    VIXL_UNIMPLEMENTED();
+  }
+
+  if (IsInt6(multiplier)) {
+    SingleEmissionCheckScope guard(this);
+    if (xn.IsZero()) {
+      rdvl(xd, static_cast<int>(multiplier));
+    } else {
+      addvl(xd, xn, static_cast<int>(multiplier));
+    }
+    return;
+  }
+
+  // TODO: Some probable cases result in rather long sequences. For example,
+  // `Addvl(sp, sp, 42)` requires four instructions, even though it's only just
+  // outside the encodable range. We should look for ways to cover such cases
+  // without drastically increasing the complexity of this logic.
+
+  // For other cases, calculate xn + (VL * multiplier) using discrete
+  // instructions. This requires two scratch registers in the general case, so
+  // we try to re-use the destination as a scratch register.
+  UseScratchRegisterScope temps(this);
+  temps.Include(xd);
+  temps.Exclude(xn);
+
+  Register a = temps.AcquireX();
+  Mov(a, multiplier);
+
+  MacroEmissionCheckScope guard(this);
+  Register b = temps.AcquireX();
+  rdvl(b, 1);
+  if (xn.IsZero()) {
+    mul(xd, a, b);
+  } else if (xd.IsSP() || xn.IsSP()) {
+    mul(a, a, b);
+    add(xd, xn, a);
+  } else {
+    madd(xd, a, b, xn);
+  }
+}
+
+void MacroAssembler::CalculateSVEAddress(const Register& xd,
+                                         const SVEMemOperand& addr,
+                                         int vl_divisor_log2) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(!addr.IsScatterGather());
+  VIXL_ASSERT(xd.IsX());
+
+  // The lower bound is where a whole Z register is accessed.
+  VIXL_ASSERT(!addr.IsMulVl() || (vl_divisor_log2 >= 0));
+  // The upper bound is for P register accesses, and for instructions like
+  // "st1b { z0.d } [...]", where one byte is accessed for every D-sized lane.
+  VIXL_ASSERT(vl_divisor_log2 <= static_cast<int>(kZRegBitsPerPRegBitLog2));
+
+  SVEOffsetModifier mod = addr.GetOffsetModifier();
+  Register base = addr.GetScalarBase();
+
+  if (addr.IsEquivalentToScalar()) {
+    // For example:
+    //   [x0]
+    //   [x0, #0]
+    //   [x0, xzr, LSL 2]
+    Mov(xd, base);
+  } else if (addr.IsScalarPlusImmediate()) {
+    // For example:
+    //   [x0, #42]
+    //   [x0, #42, MUL VL]
+    int64_t offset = addr.GetImmediateOffset();
+    VIXL_ASSERT(offset != 0);  // Handled by IsEquivalentToScalar.
+    if (addr.IsMulVl()) {
+      int vl_divisor = 1 << vl_divisor_log2;
+      // For all possible values of vl_divisor, we can simply use `Addpl`. This
+      // will select `addvl` if necessary.
+      VIXL_ASSERT((kZRegBitsPerPRegBit % vl_divisor) == 0);
+      Addpl(xd, base, offset * (kZRegBitsPerPRegBit / vl_divisor));
+    } else {
+      // IsScalarPlusImmediate() ensures that no other modifiers can occur.
+      VIXL_ASSERT(mod == NO_SVE_OFFSET_MODIFIER);
+      Add(xd, base, offset);
+    }
+  } else if (addr.IsScalarPlusScalar()) {
+    // For example:
+    //   [x0, x1]
+    //   [x0, x1, LSL #4]
+    Register offset = addr.GetScalarOffset();
+    VIXL_ASSERT(!offset.IsZero());  // Handled by IsEquivalentToScalar.
+    if (mod == SVE_LSL) {
+      Add(xd, base, Operand(offset, LSL, addr.GetShiftAmount()));
+    } else {
+      // IsScalarPlusScalar() ensures that no other modifiers can occur.
+      VIXL_ASSERT(mod == NO_SVE_OFFSET_MODIFIER);
+      Add(xd, base, offset);
+    }
+  } else {
+    // All other forms are scatter-gather addresses, which cannot be evaluated
+    // into an X register.
+    VIXL_UNREACHABLE();
+  }
+}
+
+void MacroAssembler::Cpy(const ZRegister& zd,
+                         const PRegister& pg,
+                         IntegerOperand imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(imm.FitsInLane(zd));
+  int imm8;
+  int shift;
+  if (imm.TryEncodeAsShiftedIntNForLane<8, 0>(zd, &imm8, &shift) ||
+      imm.TryEncodeAsShiftedIntNForLane<8, 8>(zd, &imm8, &shift)) {
+    SingleEmissionCheckScope guard(this);
+    cpy(zd, pg, imm8, shift);
+    return;
+  }
+
+  // The fallbacks rely on `cpy` variants that only support merging predication.
+  // If zeroing predication was requested, zero the destination first.
+  if (pg.IsZeroing()) {
+    SingleEmissionCheckScope guard(this);
+    dup(zd, 0);
+  }
+  PRegisterM pg_m = pg.Merging();
+
+  // Try to encode the immediate using fcpy.
+  VIXL_ASSERT(imm.FitsInLane(zd));
+  if (zd.GetLaneSizeInBits() >= kHRegSize) {
+    double fp_imm = 0.0;
+    switch (zd.GetLaneSizeInBits()) {
+      case kHRegSize:
+        fp_imm =
+            FPToDouble(RawbitsToFloat16(imm.AsUint16()), kIgnoreDefaultNaN);
+        break;
+      case kSRegSize:
+        fp_imm = RawbitsToFloat(imm.AsUint32());
+        break;
+      case kDRegSize:
+        fp_imm = RawbitsToDouble(imm.AsUint64());
+        break;
+      default:
+        VIXL_UNREACHABLE();
+        break;
+    }
+    // IsImmFP64 is equivalent to IsImmFP<n> for the same arithmetic value, so
+    // we can use IsImmFP64 for all lane sizes.
+    if (IsImmFP64(fp_imm)) {
+      SingleEmissionCheckScope guard(this);
+      fcpy(zd, pg_m, fp_imm);
+      return;
+    }
+  }
+
+  // Fall back to using a scratch register.
+  UseScratchRegisterScope temps(this);
+  Register scratch = temps.AcquireRegisterToHoldLane(zd);
+  Mov(scratch, imm);
+
+  SingleEmissionCheckScope guard(this);
+  cpy(zd, pg_m, scratch);
+}
+
+// TODO: We implement Fcpy (amongst other things) for all FP types because it
+// allows us to preserve user-specified NaNs. We should come up with some
+// FPImmediate type to abstract this, and avoid all the duplication below (and
+// elsewhere).
+
+void MacroAssembler::Fcpy(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          double imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(pg.IsMerging());
+
+  if (IsImmFP64(imm)) {
+    SingleEmissionCheckScope guard(this);
+    fcpy(zd, pg, imm);
+    return;
+  }
+
+  // As a fall-back, cast the immediate to the required lane size, and try to
+  // encode the bit pattern using `Cpy`.
+  Cpy(zd, pg, FPToRawbitsWithSize(zd.GetLaneSizeInBits(), imm));
+}
+
+void MacroAssembler::Fcpy(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          float imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(pg.IsMerging());
+
+  if (IsImmFP32(imm)) {
+    SingleEmissionCheckScope guard(this);
+    fcpy(zd, pg, imm);
+    return;
+  }
+
+  // As a fall-back, cast the immediate to the required lane size, and try to
+  // encode the bit pattern using `Cpy`.
+  Cpy(zd, pg, FPToRawbitsWithSize(zd.GetLaneSizeInBits(), imm));
+}
+
+void MacroAssembler::Fcpy(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          Float16 imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(pg.IsMerging());
+
+  if (IsImmFP16(imm)) {
+    SingleEmissionCheckScope guard(this);
+    fcpy(zd, pg, imm);
+    return;
+  }
+
+  // As a fall-back, cast the immediate to the required lane size, and try to
+  // encode the bit pattern using `Cpy`.
+  Cpy(zd, pg, FPToRawbitsWithSize(zd.GetLaneSizeInBits(), imm));
+}
+
+void MacroAssembler::Dup(const ZRegister& zd, IntegerOperand imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(imm.FitsInLane(zd));
+  unsigned lane_size = zd.GetLaneSizeInBits();
+  int imm8;
+  int shift;
+  if (imm.TryEncodeAsShiftedIntNForLane<8, 0>(zd, &imm8, &shift) ||
+      imm.TryEncodeAsShiftedIntNForLane<8, 8>(zd, &imm8, &shift)) {
+    SingleEmissionCheckScope guard(this);
+    dup(zd, imm8, shift);
+  } else if (IsImmLogical(imm.AsUintN(lane_size), lane_size)) {
+    SingleEmissionCheckScope guard(this);
+    dupm(zd, imm.AsUintN(lane_size));
+  } else {
+    UseScratchRegisterScope temps(this);
+    Register scratch = temps.AcquireRegisterToHoldLane(zd);
+    Mov(scratch, imm);
+
+    SingleEmissionCheckScope guard(this);
+    dup(zd, scratch);
+  }
+}
+
+void MacroAssembler::NoncommutativeArithmeticHelper(
+    const ZRegister& zd,
+    const PRegisterM& pg,
+    const ZRegister& zn,
+    const ZRegister& zm,
+    SVEArithPredicatedFn fn,
+    SVEArithPredicatedFn rev_fn) {
+  if (zd.Aliases(zn)) {
+    // E.g. zd = zd / zm
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zd, pg, zn, zm);
+  } else if (zd.Aliases(zm)) {
+    // E.g. zd = zn / zd
+    SingleEmissionCheckScope guard(this);
+    (this->*rev_fn)(zd, pg, zm, zn);
+  } else {
+    // E.g. zd = zn / zm
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    (this->*fn)(zd, pg, zd, zm);
+  }
+}
+
+void MacroAssembler::FPCommutativeArithmeticHelper(
+    const ZRegister& zd,
+    const PRegisterM& pg,
+    const ZRegister& zn,
+    const ZRegister& zm,
+    SVEArithPredicatedFn fn,
+    FPMacroNaNPropagationOption nan_option) {
+  ResolveFPNaNPropagationOption(&nan_option);
+
+  if (zd.Aliases(zn)) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zd, pg, zd, zm);
+  } else if (zd.Aliases(zm)) {
+    switch (nan_option) {
+      case FastNaNPropagation: {
+        // Swap the arguments.
+        SingleEmissionCheckScope guard(this);
+        (this->*fn)(zd, pg, zd, zn);
+        return;
+      }
+      case StrictNaNPropagation: {
+        UseScratchRegisterScope temps(this);
+        // Use a scratch register to keep the argument order exactly as
+        // specified.
+        ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zn);
+        {
+          MovprfxHelperScope guard(this, scratch, pg, zn);
+          (this->*fn)(scratch, pg, scratch, zm);
+        }
+        Mov(zd, scratch);
+        return;
+      }
+      case NoFPMacroNaNPropagationSelected:
+        VIXL_UNREACHABLE();
+        return;
+    }
+  } else {
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    (this->*fn)(zd, pg, zd, zm);
+  }
+}
+
+void MacroAssembler::Asr(const ZRegister& zd,
+                         const PRegisterM& pg,
+                         const ZRegister& zn,
+                         const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  NoncommutativeArithmeticHelper(zd,
+                                 pg,
+                                 zn,
+                                 zm,
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::asr),
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::asrr));
+}
+
+void MacroAssembler::Lsl(const ZRegister& zd,
+                         const PRegisterM& pg,
+                         const ZRegister& zn,
+                         const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  NoncommutativeArithmeticHelper(zd,
+                                 pg,
+                                 zn,
+                                 zm,
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::lsl),
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::lslr));
+}
+
+void MacroAssembler::Lsr(const ZRegister& zd,
+                         const PRegisterM& pg,
+                         const ZRegister& zn,
+                         const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  NoncommutativeArithmeticHelper(zd,
+                                 pg,
+                                 zn,
+                                 zm,
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::lsr),
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::lsrr));
+}
+
+void MacroAssembler::Fdiv(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  NoncommutativeArithmeticHelper(zd,
+                                 pg,
+                                 zn,
+                                 zm,
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::fdiv),
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::fdivr));
+}
+
+void MacroAssembler::Fsub(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  NoncommutativeArithmeticHelper(zd,
+                                 pg,
+                                 zn,
+                                 zm,
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::fsub),
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::fsubr));
+}
+
+void MacroAssembler::Fadd(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPCommutativeArithmeticHelper(zd,
+                                pg,
+                                zn,
+                                zm,
+                                static_cast<SVEArithPredicatedFn>(
+                                    &Assembler::fadd),
+                                nan_option);
+}
+
+void MacroAssembler::Fabd(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPCommutativeArithmeticHelper(zd,
+                                pg,
+                                zn,
+                                zm,
+                                static_cast<SVEArithPredicatedFn>(
+                                    &Assembler::fabd),
+                                nan_option);
+}
+
+void MacroAssembler::Fmul(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPCommutativeArithmeticHelper(zd,
+                                pg,
+                                zn,
+                                zm,
+                                static_cast<SVEArithPredicatedFn>(
+                                    &Assembler::fmul),
+                                nan_option);
+}
+
+void MacroAssembler::Fmulx(const ZRegister& zd,
+                           const PRegisterM& pg,
+                           const ZRegister& zn,
+                           const ZRegister& zm,
+                           FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPCommutativeArithmeticHelper(zd,
+                                pg,
+                                zn,
+                                zm,
+                                static_cast<SVEArithPredicatedFn>(
+                                    &Assembler::fmulx),
+                                nan_option);
+}
+
+void MacroAssembler::Fmax(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPCommutativeArithmeticHelper(zd,
+                                pg,
+                                zn,
+                                zm,
+                                static_cast<SVEArithPredicatedFn>(
+                                    &Assembler::fmax),
+                                nan_option);
+}
+
+void MacroAssembler::Fmin(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPCommutativeArithmeticHelper(zd,
+                                pg,
+                                zn,
+                                zm,
+                                static_cast<SVEArithPredicatedFn>(
+                                    &Assembler::fmin),
+                                nan_option);
+}
+
+void MacroAssembler::Fmaxnm(const ZRegister& zd,
+                            const PRegisterM& pg,
+                            const ZRegister& zn,
+                            const ZRegister& zm,
+                            FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPCommutativeArithmeticHelper(zd,
+                                pg,
+                                zn,
+                                zm,
+                                static_cast<SVEArithPredicatedFn>(
+                                    &Assembler::fmaxnm),
+                                nan_option);
+}
+
+void MacroAssembler::Fminnm(const ZRegister& zd,
+                            const PRegisterM& pg,
+                            const ZRegister& zn,
+                            const ZRegister& zm,
+                            FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPCommutativeArithmeticHelper(zd,
+                                pg,
+                                zn,
+                                zm,
+                                static_cast<SVEArithPredicatedFn>(
+                                    &Assembler::fminnm),
+                                nan_option);
+}
+
+void MacroAssembler::Fdup(const ZRegister& zd, double imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+
+  switch (zd.GetLaneSizeInBits()) {
+    case kHRegSize:
+      Fdup(zd, Float16(imm));
+      break;
+    case kSRegSize:
+      Fdup(zd, static_cast<float>(imm));
+      break;
+    case kDRegSize:
+      if (IsImmFP64(imm)) {
+        SingleEmissionCheckScope guard(this);
+        fdup(zd, imm);
+      } else {
+        Dup(zd, DoubleToRawbits(imm));
+      }
+      break;
+  }
+}
+
+void MacroAssembler::Fdup(const ZRegister& zd, float imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+
+  switch (zd.GetLaneSizeInBits()) {
+    case kHRegSize:
+      Fdup(zd, Float16(imm));
+      break;
+    case kSRegSize:
+      if (IsImmFP32(imm)) {
+        SingleEmissionCheckScope guard(this);
+        fdup(zd, imm);
+      } else {
+        Dup(zd, FloatToRawbits(imm));
+      }
+      break;
+    case kDRegSize:
+      Fdup(zd, static_cast<double>(imm));
+      break;
+  }
+}
+
+void MacroAssembler::Fdup(const ZRegister& zd, Float16 imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+
+  switch (zd.GetLaneSizeInBits()) {
+    case kHRegSize:
+      if (IsImmFP16(imm)) {
+        SingleEmissionCheckScope guard(this);
+        fdup(zd, imm);
+      } else {
+        Dup(zd, Float16ToRawbits(imm));
+      }
+      break;
+    case kSRegSize:
+      Fdup(zd, FPToFloat(imm, kIgnoreDefaultNaN));
+      break;
+    case kDRegSize:
+      Fdup(zd, FPToDouble(imm, kIgnoreDefaultNaN));
+      break;
+  }
+}
+
+void MacroAssembler::Index(const ZRegister& zd,
+                           const Operand& start,
+                           const Operand& step) {
+  class IndexOperand : public Operand {
+   public:
+    static IndexOperand Prepare(MacroAssembler* masm,
+                                UseScratchRegisterScope* temps,
+                                const Operand& op,
+                                const ZRegister& zd) {
+      // Look for encodable immediates.
+      int imm;
+      if (op.IsImmediate()) {
+        if (IntegerOperand(op).TryEncodeAsIntNForLane<5>(zd, &imm)) {
+          return IndexOperand(imm);
+        }
+        Register scratch = temps->AcquireRegisterToHoldLane(zd);
+        masm->Mov(scratch, op);
+        return IndexOperand(scratch);
+      } else {
+        // Plain registers can be encoded directly.
+        VIXL_ASSERT(op.IsPlainRegister());
+        return IndexOperand(op.GetRegister());
+      }
+    }
+
+    int GetImm5() const {
+      int64_t imm = GetImmediate();
+      VIXL_ASSERT(IsInt5(imm));
+      return static_cast<int>(imm);
+    }
+
+   private:
+    explicit IndexOperand(const Register& reg) : Operand(reg) {}
+    explicit IndexOperand(int64_t imm) : Operand(imm) {}
+  };
+
+  UseScratchRegisterScope temps(this);
+  IndexOperand start_enc = IndexOperand::Prepare(this, &temps, start, zd);
+  IndexOperand step_enc = IndexOperand::Prepare(this, &temps, step, zd);
+
+  SingleEmissionCheckScope guard(this);
+  if (start_enc.IsImmediate()) {
+    if (step_enc.IsImmediate()) {
+      index(zd, start_enc.GetImm5(), step_enc.GetImm5());
+    } else {
+      index(zd, start_enc.GetImm5(), step_enc.GetRegister());
+    }
+  } else {
+    if (step_enc.IsImmediate()) {
+      index(zd, start_enc.GetRegister(), step_enc.GetImm5());
+    } else {
+      index(zd, start_enc.GetRegister(), step_enc.GetRegister());
+    }
+  }
+}
+
+void MacroAssembler::Insr(const ZRegister& zdn, IntegerOperand imm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(imm.FitsInLane(zdn));
+
+  if (imm.IsZero()) {
+    SingleEmissionCheckScope guard(this);
+    insr(zdn, xzr);
+    return;
+  }
+
+  UseScratchRegisterScope temps(this);
+  Register scratch = temps.AcquireRegisterToHoldLane(zdn);
+
+  // TODO: There are many cases where we could optimise immediates, such as by
+  // detecting repeating patterns or FP immediates. We should optimise and
+  // abstract this for use in other SVE mov-immediate-like macros.
+  Mov(scratch, imm);
+
+  SingleEmissionCheckScope guard(this);
+  insr(zdn, scratch);
+}
+
+void MacroAssembler::Mla(const ZRegister& zd,
+                         const PRegisterM& pg,
+                         const ZRegister& za,
+                         const ZRegister& zn,
+                         const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(za)) {
+    // zda = zda + (zn * zm)
+    SingleEmissionCheckScope guard(this);
+    mla(zd, pg, zn, zm);
+  } else if (zd.Aliases(zn)) {
+    // zdn = za + (zdn * zm)
+    SingleEmissionCheckScope guard(this);
+    mad(zd, pg, zm, za);
+  } else if (zd.Aliases(zm)) {
+    // Multiplication is commutative, so we can swap zn and zm.
+    // zdm = za + (zdm * zn)
+    SingleEmissionCheckScope guard(this);
+    mad(zd, pg, zn, za);
+  } else {
+    // zd = za + (zn * zm)
+    ExactAssemblyScope guard(this, 2 * kInstructionSize);
+    movprfx(zd, pg, za);
+    mla(zd, pg, zn, zm);
+  }
+}
+
+void MacroAssembler::Mls(const ZRegister& zd,
+                         const PRegisterM& pg,
+                         const ZRegister& za,
+                         const ZRegister& zn,
+                         const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(za)) {
+    // zda = zda - (zn * zm)
+    SingleEmissionCheckScope guard(this);
+    mls(zd, pg, zn, zm);
+  } else if (zd.Aliases(zn)) {
+    // zdn = za - (zdn * zm)
+    SingleEmissionCheckScope guard(this);
+    msb(zd, pg, zm, za);
+  } else if (zd.Aliases(zm)) {
+    // Multiplication is commutative, so we can swap zn and zm.
+    // zdm = za - (zdm * zn)
+    SingleEmissionCheckScope guard(this);
+    msb(zd, pg, zn, za);
+  } else {
+    // zd = za - (zn * zm)
+    ExactAssemblyScope guard(this, 2 * kInstructionSize);
+    movprfx(zd, pg, za);
+    mls(zd, pg, zn, zm);
+  }
+}
+
+void MacroAssembler::CompareHelper(Condition cond,
+                                   const PRegisterWithLaneSize& pd,
+                                   const PRegisterZ& pg,
+                                   const ZRegister& zn,
+                                   IntegerOperand imm) {
+  UseScratchRegisterScope temps(this);
+  ZRegister zm = temps.AcquireZ().WithLaneSize(zn.GetLaneSizeInBits());
+  Dup(zm, imm);
+  SingleEmissionCheckScope guard(this);
+  cmp(cond, pd, pg, zn, zm);
+}
+
+void MacroAssembler::Pfirst(const PRegisterWithLaneSize& pd,
+                            const PRegister& pg,
+                            const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(pd.IsLaneSizeB());
+  VIXL_ASSERT(pn.IsLaneSizeB());
+  if (pd.Is(pn)) {
+    SingleEmissionCheckScope guard(this);
+    pfirst(pd, pg, pn);
+  } else {
+    UseScratchRegisterScope temps(this);
+    PRegister temp_pg = pg;
+    if (pd.Aliases(pg)) {
+      temp_pg = temps.AcquireP();
+      Mov(temp_pg.VnB(), pg.VnB());
+    }
+    Mov(pd, pn);
+    SingleEmissionCheckScope guard(this);
+    pfirst(pd, temp_pg, pd);
+  }
+}
+
+void MacroAssembler::Pnext(const PRegisterWithLaneSize& pd,
+                           const PRegister& pg,
+                           const PRegisterWithLaneSize& pn) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(AreSameFormat(pd, pn));
+  if (pd.Is(pn)) {
+    SingleEmissionCheckScope guard(this);
+    pnext(pd, pg, pn);
+  } else {
+    UseScratchRegisterScope temps(this);
+    PRegister temp_pg = pg;
+    if (pd.Aliases(pg)) {
+      temp_pg = temps.AcquireP();
+      Mov(temp_pg.VnB(), pg.VnB());
+    }
+    Mov(pd.VnB(), pn.VnB());
+    SingleEmissionCheckScope guard(this);
+    pnext(pd, temp_pg, pd);
+  }
+}
+
+void MacroAssembler::Ptrue(const PRegisterWithLaneSize& pd,
+                           SVEPredicateConstraint pattern,
+                           FlagsUpdate s) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  switch (s) {
+    case LeaveFlags:
+      Ptrue(pd, pattern);
+      return;
+    case SetFlags:
+      Ptrues(pd, pattern);
+      return;
+  }
+  VIXL_UNREACHABLE();
+}
+
+void MacroAssembler::Sdiv(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  NoncommutativeArithmeticHelper(zd,
+                                 pg,
+                                 zn,
+                                 zm,
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::sdiv),
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::sdivr));
+}
+
+void MacroAssembler::Sub(const ZRegister& zd,
+                         IntegerOperand imm,
+                         const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+
+  int imm8;
+  int shift = -1;
+  if (imm.TryEncodeAsShiftedUintNForLane<8, 0>(zd, &imm8, &shift) ||
+      imm.TryEncodeAsShiftedUintNForLane<8, 8>(zd, &imm8, &shift)) {
+    MovprfxHelperScope guard(this, zd, zm);
+    subr(zd, zd, imm8, shift);
+  } else {
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithLaneSize(zm.GetLaneSizeInBits());
+    Dup(scratch, imm);
+
+    SingleEmissionCheckScope guard(this);
+    sub(zd, scratch, zm);
+  }
+}
+
+void MacroAssembler::Sub(const ZRegister& zd,
+                         const PRegisterM& pg,
+                         const ZRegister& zn,
+                         const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  NoncommutativeArithmeticHelper(zd,
+                                 pg,
+                                 zn,
+                                 zm,
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::sub),
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::subr));
+}
+
+void MacroAssembler::Udiv(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& zn,
+                          const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  NoncommutativeArithmeticHelper(zd,
+                                 pg,
+                                 zn,
+                                 zm,
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::udiv),
+                                 static_cast<SVEArithPredicatedFn>(
+                                     &Assembler::udivr));
+}
+
+void MacroAssembler::SVELoadBroadcastImmHelper(const ZRegister& zt,
+                                               const PRegisterZ& pg,
+                                               const SVEMemOperand& addr,
+                                               SVELoadBroadcastFn fn,
+                                               int divisor) {
+  VIXL_ASSERT(addr.IsScalarPlusImmediate());
+  int64_t imm = addr.GetImmediateOffset();
+  if ((imm % divisor == 0) && IsUint6(imm / divisor)) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, addr);
+  } else {
+    UseScratchRegisterScope temps(this);
+    Register scratch = temps.AcquireX();
+    CalculateSVEAddress(scratch, addr, zt);
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, SVEMemOperand(scratch));
+  }
+}
+
+void MacroAssembler::SVELoadStoreScalarImmHelper(const CPURegister& rt,
+                                                 const SVEMemOperand& addr,
+                                                 SVELoadStoreFn fn) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  VIXL_ASSERT(rt.IsZRegister() || rt.IsPRegister());
+
+  if (addr.IsPlainScalar() ||
+      (addr.IsScalarPlusImmediate() && IsInt9(addr.GetImmediateOffset()) &&
+       addr.IsMulVl())) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(rt, addr);
+    return;
+  }
+
+  if (addr.IsEquivalentToScalar()) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(rt, SVEMemOperand(addr.GetScalarBase()));
+    return;
+  }
+
+  UseScratchRegisterScope temps(this);
+  Register scratch = temps.AcquireX();
+  CalculateSVEAddress(scratch, addr, rt);
+  SingleEmissionCheckScope guard(this);
+  (this->*fn)(rt, SVEMemOperand(scratch));
+}
+
+template <typename Tg, typename Tf>
+void MacroAssembler::SVELoadStoreScalarImmHelper(
+    const ZRegister& zt,
+    const Tg& pg,
+    const SVEMemOperand& addr,
+    Tf fn,
+    int imm_bits,
+    int shift_amount,
+    SVEOffsetModifier supported_modifier,
+    int vl_divisor_log2) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  int imm_divisor = 1 << shift_amount;
+
+  if (addr.IsPlainScalar() ||
+      (addr.IsScalarPlusImmediate() &&
+       IsIntN(imm_bits, addr.GetImmediateOffset() / imm_divisor) &&
+       ((addr.GetImmediateOffset() % imm_divisor) == 0) &&
+       (addr.GetOffsetModifier() == supported_modifier))) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, addr);
+    return;
+  }
+
+  if (addr.IsEquivalentToScalar()) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, SVEMemOperand(addr.GetScalarBase()));
+    return;
+  }
+
+  if (addr.IsMulVl() && (supported_modifier != SVE_MUL_VL) &&
+      (vl_divisor_log2 == -1)) {
+    // We don't handle [x0, #imm, MUL VL] if the in-memory access size is not VL
+    // dependent.
+    VIXL_UNIMPLEMENTED();
+  }
+
+  UseScratchRegisterScope temps(this);
+  Register scratch = temps.AcquireX();
+  CalculateSVEAddress(scratch, addr, vl_divisor_log2);
+  SingleEmissionCheckScope guard(this);
+  (this->*fn)(zt, pg, SVEMemOperand(scratch));
+}
+
+template <typename Tg, typename Tf>
+void MacroAssembler::SVELoadStore1Helper(int msize_in_bytes_log2,
+                                         const ZRegister& zt,
+                                         const Tg& pg,
+                                         const SVEMemOperand& addr,
+                                         Tf fn) {
+  if (addr.IsPlainScalar() ||
+      (addr.IsScalarPlusScalar() && !addr.GetScalarOffset().IsZero() &&
+       addr.IsEquivalentToLSL(msize_in_bytes_log2)) ||
+      (addr.IsScalarPlusImmediate() && IsInt4(addr.GetImmediateOffset()) &&
+       addr.IsMulVl())) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, addr);
+    return;
+  }
+
+  if (addr.IsEquivalentToScalar()) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, SVEMemOperand(addr.GetScalarBase()));
+    return;
+  }
+
+  if (addr.IsVectorPlusImmediate()) {
+    uint64_t offset = addr.GetImmediateOffset();
+    if (IsMultiple(offset, (1 << msize_in_bytes_log2)) &&
+        IsUint5(offset >> msize_in_bytes_log2)) {
+      SingleEmissionCheckScope guard(this);
+      (this->*fn)(zt, pg, addr);
+      return;
+    }
+  }
+
+  if (addr.IsScalarPlusVector()) {
+    VIXL_ASSERT(addr.IsScatterGather());
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, addr);
+    return;
+  }
+
+  UseScratchRegisterScope temps(this);
+  if (addr.IsScatterGather()) {
+    // In scatter-gather modes, zt and zn/zm have the same lane size. However,
+    // for 32-bit accesses, the result of each lane's address calculation still
+    // requires 64 bits; we can't naively use `Adr` for the address calculation
+    // because it would truncate each address to 32 bits.
+
+    if (addr.IsVectorPlusImmediate()) {
+      // Synthesise the immediate in an X register, then use a
+      // scalar-plus-vector access with the original vector.
+      Register scratch = temps.AcquireX();
+      Mov(scratch, addr.GetImmediateOffset());
+      SingleEmissionCheckScope guard(this);
+      SVEOffsetModifier om =
+          zt.IsLaneSizeS() ? SVE_UXTW : NO_SVE_OFFSET_MODIFIER;
+      (this->*fn)(zt, pg, SVEMemOperand(scratch, addr.GetVectorBase(), om));
+      return;
+    }
+
+    VIXL_UNIMPLEMENTED();
+  } else {
+    Register scratch = temps.AcquireX();
+    // TODO: If we have an immediate offset that is a multiple of
+    // msize_in_bytes, we can use Rdvl/Rdpl and a scalar-plus-scalar form to
+    // save an instruction.
+    int vl_divisor_log2 = zt.GetLaneSizeInBytesLog2() - msize_in_bytes_log2;
+    CalculateSVEAddress(scratch, addr, vl_divisor_log2);
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, SVEMemOperand(scratch));
+  }
+}
+
+template <typename Tf>
+void MacroAssembler::SVELoadFFHelper(int msize_in_bytes_log2,
+                                     const ZRegister& zt,
+                                     const PRegisterZ& pg,
+                                     const SVEMemOperand& addr,
+                                     Tf fn) {
+  if (addr.IsScatterGather()) {
+    // Scatter-gather first-fault loads share encodings with normal loads.
+    SVELoadStore1Helper(msize_in_bytes_log2, zt, pg, addr, fn);
+    return;
+  }
+
+  // Contiguous first-faulting loads have no scalar-plus-immediate form at all,
+  // so we don't do immediate synthesis.
+
+  // We cannot currently distinguish "[x0]" from "[x0, #0]", and this
+  // is not "scalar-plus-scalar", so we have to permit `IsPlainScalar()` here.
+  if (addr.IsPlainScalar() || (addr.IsScalarPlusScalar() &&
+                               addr.IsEquivalentToLSL(msize_in_bytes_log2))) {
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zt, pg, addr);
+    return;
+  }
+
+  VIXL_UNIMPLEMENTED();
+}
+
+void MacroAssembler::Ld1b(const ZRegister& zt,
+                          const PRegisterZ& pg,
+                          const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kBRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVELoad1Fn>(&Assembler::ld1b));
+}
+
+void MacroAssembler::Ld1h(const ZRegister& zt,
+                          const PRegisterZ& pg,
+                          const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kHRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVELoad1Fn>(&Assembler::ld1h));
+}
+
+void MacroAssembler::Ld1w(const ZRegister& zt,
+                          const PRegisterZ& pg,
+                          const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kWRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVELoad1Fn>(&Assembler::ld1w));
+}
+
+void MacroAssembler::Ld1d(const ZRegister& zt,
+                          const PRegisterZ& pg,
+                          const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kDRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVELoad1Fn>(&Assembler::ld1d));
+}
+
+void MacroAssembler::Ld1sb(const ZRegister& zt,
+                           const PRegisterZ& pg,
+                           const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kBRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVELoad1Fn>(&Assembler::ld1sb));
+}
+
+void MacroAssembler::Ld1sh(const ZRegister& zt,
+                           const PRegisterZ& pg,
+                           const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kHRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVELoad1Fn>(&Assembler::ld1sh));
+}
+
+void MacroAssembler::Ld1sw(const ZRegister& zt,
+                           const PRegisterZ& pg,
+                           const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kSRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVELoad1Fn>(&Assembler::ld1sw));
+}
+
+void MacroAssembler::St1b(const ZRegister& zt,
+                          const PRegister& pg,
+                          const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kBRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVEStore1Fn>(&Assembler::st1b));
+}
+
+void MacroAssembler::St1h(const ZRegister& zt,
+                          const PRegister& pg,
+                          const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kHRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVEStore1Fn>(&Assembler::st1h));
+}
+
+void MacroAssembler::St1w(const ZRegister& zt,
+                          const PRegister& pg,
+                          const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kSRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVEStore1Fn>(&Assembler::st1w));
+}
+
+void MacroAssembler::St1d(const ZRegister& zt,
+                          const PRegister& pg,
+                          const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStore1Helper(kDRegSizeInBytesLog2,
+                      zt,
+                      pg,
+                      addr,
+                      static_cast<SVEStore1Fn>(&Assembler::st1d));
+}
+
+void MacroAssembler::Ldff1b(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadFFHelper(kBRegSizeInBytesLog2,
+                  zt,
+                  pg,
+                  addr,
+                  static_cast<SVELoad1Fn>(&Assembler::ldff1b));
+}
+
+void MacroAssembler::Ldff1h(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadFFHelper(kHRegSizeInBytesLog2,
+                  zt,
+                  pg,
+                  addr,
+                  static_cast<SVELoad1Fn>(&Assembler::ldff1h));
+}
+
+void MacroAssembler::Ldff1w(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadFFHelper(kSRegSizeInBytesLog2,
+                  zt,
+                  pg,
+                  addr,
+                  static_cast<SVELoad1Fn>(&Assembler::ldff1w));
+}
+
+void MacroAssembler::Ldff1d(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadFFHelper(kDRegSizeInBytesLog2,
+                  zt,
+                  pg,
+                  addr,
+                  static_cast<SVELoad1Fn>(&Assembler::ldff1d));
+}
+
+void MacroAssembler::Ldff1sb(const ZRegister& zt,
+                             const PRegisterZ& pg,
+                             const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadFFHelper(kBRegSizeInBytesLog2,
+                  zt,
+                  pg,
+                  addr,
+                  static_cast<SVELoad1Fn>(&Assembler::ldff1sb));
+}
+
+void MacroAssembler::Ldff1sh(const ZRegister& zt,
+                             const PRegisterZ& pg,
+                             const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadFFHelper(kHRegSizeInBytesLog2,
+                  zt,
+                  pg,
+                  addr,
+                  static_cast<SVELoad1Fn>(&Assembler::ldff1sh));
+}
+
+void MacroAssembler::Ldff1sw(const ZRegister& zt,
+                             const PRegisterZ& pg,
+                             const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadFFHelper(kSRegSizeInBytesLog2,
+                  zt,
+                  pg,
+                  addr,
+                  static_cast<SVELoad1Fn>(&Assembler::ldff1sw));
+}
+
+void MacroAssembler::Ld1rqb(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rqb,
+                              4,
+                              4,
+                              NO_SVE_OFFSET_MODIFIER,
+                              -1);
+}
+
+void MacroAssembler::Ld1rqd(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rqd,
+                              4,
+                              4,
+                              NO_SVE_OFFSET_MODIFIER,
+                              -1);
+}
+
+void MacroAssembler::Ld1rqh(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rqh,
+                              4,
+                              4,
+                              NO_SVE_OFFSET_MODIFIER,
+                              -1);
+}
+
+void MacroAssembler::Ld1rqw(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ld1rqw,
+                              4,
+                              4,
+                              NO_SVE_OFFSET_MODIFIER,
+                              -1);
+}
+
+void MacroAssembler::Ldnt1b(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ldnt1b,
+                              4,
+                              0,
+                              SVE_MUL_VL);
+}
+
+void MacroAssembler::Ldnt1d(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ldnt1d,
+                              4,
+                              0,
+                              SVE_MUL_VL);
+}
+
+void MacroAssembler::Ldnt1h(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ldnt1h,
+                              4,
+                              0,
+                              SVE_MUL_VL);
+}
+
+void MacroAssembler::Ldnt1w(const ZRegister& zt,
+                            const PRegisterZ& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::ldnt1w,
+                              4,
+                              0,
+                              SVE_MUL_VL);
+}
+
+void MacroAssembler::Stnt1b(const ZRegister& zt,
+                            const PRegister& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::stnt1b,
+                              4,
+                              0,
+                              SVE_MUL_VL);
+}
+void MacroAssembler::Stnt1d(const ZRegister& zt,
+                            const PRegister& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::stnt1d,
+                              4,
+                              0,
+                              SVE_MUL_VL);
+}
+void MacroAssembler::Stnt1h(const ZRegister& zt,
+                            const PRegister& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::stnt1h,
+                              4,
+                              0,
+                              SVE_MUL_VL);
+}
+void MacroAssembler::Stnt1w(const ZRegister& zt,
+                            const PRegister& pg,
+                            const SVEMemOperand& addr) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVELoadStoreScalarImmHelper(zt,
+                              pg,
+                              addr,
+                              &MacroAssembler::stnt1w,
+                              4,
+                              0,
+                              SVE_MUL_VL);
+}
+
+void MacroAssembler::SVESdotUdotIndexHelper(IntArithIndexFn fn,
+                                            const ZRegister& zd,
+                                            const ZRegister& za,
+                                            const ZRegister& zn,
+                                            const ZRegister& zm,
+                                            int index) {
+  if (zd.Aliases(za)) {
+    // zda = zda + (zn . zm)
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zd, zn, zm, index);
+
+  } else if (zd.Aliases(zn) || zd.Aliases(zm)) {
+    // zdn = za + (zdn . zm[index])
+    // zdm = za + (zn . zdm[index])
+    // zdnm = za + (zdnm . zdnm[index])
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zd);
+    {
+      MovprfxHelperScope guard(this, scratch, za);
+      (this->*fn)(scratch, zn, zm, index);
+    }
+
+    Mov(zd, scratch);
+  } else {
+    // zd = za + (zn . zm)
+    MovprfxHelperScope guard(this, zd, za);
+    (this->*fn)(zd, zn, zm, index);
+  }
+}
+
+void MacroAssembler::SVESdotUdotHelper(IntArithFn fn,
+                                       const ZRegister& zd,
+                                       const ZRegister& za,
+                                       const ZRegister& zn,
+                                       const ZRegister& zm) {
+  if (zd.Aliases(za)) {
+    // zda = zda + (zn . zm)
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zd, zn, zm);
+
+  } else if (zd.Aliases(zn) || zd.Aliases(zm)) {
+    // zdn = za + (zdn . zm)
+    // zdm = za + (zn . zdm)
+    // zdnm = za + (zdnm . zdnm)
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zd);
+    {
+      MovprfxHelperScope guard(this, scratch, za);
+      (this->*fn)(scratch, zn, zm);
+    }
+
+    Mov(zd, scratch);
+  } else {
+    // zd = za + (zn . zm)
+    MovprfxHelperScope guard(this, zd, za);
+    (this->*fn)(zd, zn, zm);
+  }
+}
+
+void MacroAssembler::Fscale(const ZRegister& zd,
+                            const PRegisterM& pg,
+                            const ZRegister& zn,
+                            const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(zm) && !zd.Aliases(zn)) {
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zm);
+    Mov(scratch, zm);
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fscale(zd, pg, zd, scratch);
+  } else {
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fscale(zd, pg, zd, zm);
+  }
+}
+
+void MacroAssembler::Sdot(const ZRegister& zd,
+                          const ZRegister& za,
+                          const ZRegister& zn,
+                          const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVESdotUdotHelper(&Assembler::sdot, zd, za, zn, zm);
+}
+
+void MacroAssembler::Sdot(const ZRegister& zd,
+                          const ZRegister& za,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          int index) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVESdotUdotIndexHelper(&Assembler::sdot, zd, za, zn, zm, index);
+}
+
+void MacroAssembler::Udot(const ZRegister& zd,
+                          const ZRegister& za,
+                          const ZRegister& zn,
+                          const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVESdotUdotHelper(&Assembler::udot, zd, za, zn, zm);
+}
+
+void MacroAssembler::Udot(const ZRegister& zd,
+                          const ZRegister& za,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          int index) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  SVESdotUdotIndexHelper(&Assembler::udot, zd, za, zn, zm, index);
+}
+
+void MacroAssembler::FPMulAddHelper(const ZRegister& zd,
+                                    const PRegisterM& pg,
+                                    const ZRegister& za,
+                                    const ZRegister& zn,
+                                    const ZRegister& zm,
+                                    SVEMulAddPredicatedZdaFn fn_zda,
+                                    SVEMulAddPredicatedZdnFn fn_zdn,
+                                    FPMacroNaNPropagationOption nan_option) {
+  ResolveFPNaNPropagationOption(&nan_option);
+
+  if (zd.Aliases(za)) {
+    // zda = (-)zda + ((-)zn * zm) for fmla, fmls, fnmla and fnmls.
+    SingleEmissionCheckScope guard(this);
+    (this->*fn_zda)(zd, pg, zn, zm);
+  } else if (zd.Aliases(zn)) {
+    // zdn = (-)za + ((-)zdn * zm) for fmad, fmsb, fnmad and fnmsb.
+    SingleEmissionCheckScope guard(this);
+    (this->*fn_zdn)(zd, pg, zm, za);
+  } else if (zd.Aliases(zm)) {
+    switch (nan_option) {
+      case FastNaNPropagation: {
+        // We treat multiplication as commutative in the fast mode, so we can
+        // swap zn and zm.
+        // zdm = (-)za + ((-)zdm * zn) for fmad, fmsb, fnmad and fnmsb.
+        SingleEmissionCheckScope guard(this);
+        (this->*fn_zdn)(zd, pg, zn, za);
+        return;
+      }
+      case StrictNaNPropagation: {
+        UseScratchRegisterScope temps(this);
+        // Use a scratch register to keep the argument order exactly as
+        // specified.
+        ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zn);
+        {
+          MovprfxHelperScope guard(this, scratch, pg, za);
+          // scratch = (-)za + ((-)zn * zm)
+          (this->*fn_zda)(scratch, pg, zn, zm);
+        }
+        Mov(zd, scratch);
+        return;
+      }
+      case NoFPMacroNaNPropagationSelected:
+        VIXL_UNREACHABLE();
+        return;
+    }
+  } else {
+    // zd = (-)za + ((-)zn * zm) for fmla, fmls, fnmla and fnmls.
+    MovprfxHelperScope guard(this, zd, pg, za);
+    (this->*fn_zda)(zd, pg, zn, zm);
+  }
+}
+
+void MacroAssembler::FPMulAddIndexHelper(SVEMulAddIndexFn fn,
+                                         const ZRegister& zd,
+                                         const ZRegister& za,
+                                         const ZRegister& zn,
+                                         const ZRegister& zm,
+                                         int index) {
+  if (zd.Aliases(za)) {
+    // zda = zda + (zn * zm[i])
+    SingleEmissionCheckScope guard(this);
+    (this->*fn)(zd, zn, zm, index);
+
+  } else if (zd.Aliases(zn) || zd.Aliases(zm)) {
+    // zdn = za + (zdn * zm[i])
+    // zdm = za + (zn * zdm[i])
+    // zdnm = za + (zdnm * zdnm[i])
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zd);
+    {
+      MovprfxHelperScope guard(this, scratch, za);
+      (this->*fn)(scratch, zn, zm, index);
+    }
+    Mov(zd, scratch);
+  } else {
+    // zd = za + (zn * zm[i])
+    MovprfxHelperScope guard(this, zd, za);
+    (this->*fn)(zd, zn, zm, index);
+  }
+}
+
+void MacroAssembler::Fmla(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& za,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPMulAddHelper(zd,
+                 pg,
+                 za,
+                 zn,
+                 zm,
+                 &Assembler::fmla,
+                 &Assembler::fmad,
+                 nan_option);
+}
+
+void MacroAssembler::Fmla(const ZRegister& zd,
+                          const ZRegister& za,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          int index) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPMulAddIndexHelper(&Assembler::fmla, zd, za, zn, zm, index);
+}
+
+void MacroAssembler::Fmls(const ZRegister& zd,
+                          const PRegisterM& pg,
+                          const ZRegister& za,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPMulAddHelper(zd,
+                 pg,
+                 za,
+                 zn,
+                 zm,
+                 &Assembler::fmls,
+                 &Assembler::fmsb,
+                 nan_option);
+}
+
+void MacroAssembler::Fmls(const ZRegister& zd,
+                          const ZRegister& za,
+                          const ZRegister& zn,
+                          const ZRegister& zm,
+                          int index) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPMulAddIndexHelper(&Assembler::fmls, zd, za, zn, zm, index);
+}
+
+void MacroAssembler::Fnmla(const ZRegister& zd,
+                           const PRegisterM& pg,
+                           const ZRegister& za,
+                           const ZRegister& zn,
+                           const ZRegister& zm,
+                           FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPMulAddHelper(zd,
+                 pg,
+                 za,
+                 zn,
+                 zm,
+                 &Assembler::fnmla,
+                 &Assembler::fnmad,
+                 nan_option);
+}
+
+void MacroAssembler::Fnmls(const ZRegister& zd,
+                           const PRegisterM& pg,
+                           const ZRegister& za,
+                           const ZRegister& zn,
+                           const ZRegister& zm,
+                           FPMacroNaNPropagationOption nan_option) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  FPMulAddHelper(zd,
+                 pg,
+                 za,
+                 zn,
+                 zm,
+                 &Assembler::fnmls,
+                 &Assembler::fnmsb,
+                 nan_option);
+}
+
+void MacroAssembler::Ftmad(const ZRegister& zd,
+                           const ZRegister& zn,
+                           const ZRegister& zm,
+                           int imm3) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(zm) && !zd.Aliases(zn)) {
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zm);
+    Mov(scratch, zm);
+    MovprfxHelperScope guard(this, zd, zn);
+    ftmad(zd, zd, scratch, imm3);
+  } else {
+    MovprfxHelperScope guard(this, zd, zn);
+    ftmad(zd, zd, zm, imm3);
+  }
+}
+
+void MacroAssembler::Fcadd(const ZRegister& zd,
+                           const PRegisterM& pg,
+                           const ZRegister& zn,
+                           const ZRegister& zm,
+                           int rot) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(zm) && !zd.Aliases(zn)) {
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zd);
+    {
+      MovprfxHelperScope guard(this, scratch, pg, zn);
+      fcadd(scratch, pg, scratch, zm, rot);
+    }
+    Mov(zd, scratch);
+  } else {
+    MovprfxHelperScope guard(this, zd, pg, zn);
+    fcadd(zd, pg, zd, zm, rot);
+  }
+}
+
+void MacroAssembler::Ext(const ZRegister& zd,
+                         const ZRegister& zn,
+                         const ZRegister& zm,
+                         unsigned offset) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(zm) && !zd.Aliases(zn)) {
+    // zd = ext(zn, zd, offset)
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zd);
+    {
+      MovprfxHelperScope guard(this, scratch, zn);
+      ext(scratch, scratch, zm, offset);
+    }
+    Mov(zd, scratch);
+  } else {
+    // zd = ext(zn, zm, offset)
+    // zd = ext(zd, zd, offset)
+    MovprfxHelperScope guard(this, zd, zn);
+    ext(zd, zd, zm, offset);
+  }
+}
+
+void MacroAssembler::Splice(const ZRegister& zd,
+                            const PRegister& pg,
+                            const ZRegister& zn,
+                            const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(zm) && !zd.Aliases(zn)) {
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zd);
+    {
+      MovprfxHelperScope guard(this, scratch, zn);
+      splice(scratch, pg, scratch, zm);
+    }
+    Mov(zd, scratch);
+  } else {
+    MovprfxHelperScope guard(this, zd, zn);
+    splice(zd, pg, zd, zm);
+  }
+}
+
+void MacroAssembler::Clasta(const ZRegister& zd,
+                            const PRegister& pg,
+                            const ZRegister& zn,
+                            const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(zm) && !zd.Aliases(zn)) {
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zd);
+    {
+      MovprfxHelperScope guard(this, scratch, zn);
+      clasta(scratch, pg, scratch, zm);
+    }
+    Mov(zd, scratch);
+  } else {
+    MovprfxHelperScope guard(this, zd, zn);
+    clasta(zd, pg, zd, zm);
+  }
+}
+
+void MacroAssembler::Clastb(const ZRegister& zd,
+                            const PRegister& pg,
+                            const ZRegister& zn,
+                            const ZRegister& zm) {
+  VIXL_ASSERT(allow_macro_instructions_);
+  if (zd.Aliases(zm) && !zd.Aliases(zn)) {
+    UseScratchRegisterScope temps(this);
+    ZRegister scratch = temps.AcquireZ().WithSameLaneSizeAs(zd);
+    {
+      MovprfxHelperScope guard(this, scratch, zn);
+      clastb(scratch, pg, scratch, zm);
+    }
+    Mov(zd, scratch);
+  } else {
+    MovprfxHelperScope guard(this, zd, zn);
+    clastb(zd, pg, zd, zm);
+  }
+}
+
+}  // namespace aarch64
+}  // namespace vixl
diff --git a/src/aarch64/operands-aarch64.cc b/src/aarch64/operands-aarch64.cc
index 20364616..008179e4 100644
--- a/src/aarch64/operands-aarch64.cc
+++ b/src/aarch64/operands-aarch64.cc
@@ -30,32 +30,32 @@ namespace vixl {
 namespace aarch64 {
 
 // CPURegList utilities.
-CPURegister CPURegList::PopLowestIndex() {
-  if (IsEmpty()) {
-    return NoCPUReg;
-  }
-  int index = CountTrailingZeros(list_);
-  VIXL_ASSERT((1 << index) & list_);
+CPURegister CPURegList::PopLowestIndex(RegList mask) {
+  RegList list = list_ & mask;
+  if (list == 0) return NoCPUReg;
+  int index = CountTrailingZeros(list);
+  VIXL_ASSERT(((1 << index) & list) != 0);
   Remove(index);
   return CPURegister(index, size_, type_);
 }
 
 
-CPURegister CPURegList::PopHighestIndex() {
-  VIXL_ASSERT(IsValid());
-  if (IsEmpty()) {
-    return NoCPUReg;
-  }
-  int index = CountLeadingZeros(list_);
+CPURegister CPURegList::PopHighestIndex(RegList mask) {
+  RegList list = list_ & mask;
+  if (list == 0) return NoCPUReg;
+  int index = CountLeadingZeros(list);
   index = kRegListSizeInBits - 1 - index;
-  VIXL_ASSERT((1 << index) & list_);
+  VIXL_ASSERT(((1 << index) & list) != 0);
   Remove(index);
   return CPURegister(index, size_, type_);
 }
 
 
 bool CPURegList::IsValid() const {
-  if ((type_ == CPURegister::kRegister) || (type_ == CPURegister::kVRegister)) {
+  if (type_ == CPURegister::kNoRegister) {
+    // We can't use IsEmpty here because that asserts IsValid().
+    return list_ == 0;
+  } else {
     bool is_valid = true;
     // Try to create a CPURegister for each element in the list.
     for (int i = 0; i < kRegListSizeInBits; i++) {
@@ -64,11 +64,6 @@ bool CPURegList::IsValid() const {
       }
     }
     return is_valid;
-  } else if (type_ == CPURegister::kNoRegister) {
-    // We can't use IsEmpty here because that asserts IsValid().
-    return list_ == 0;
-  } else {
-    return false;
   }
 }
 
@@ -149,145 +144,6 @@ const CPURegList kCalleeSavedV = CPURegList::GetCalleeSavedV();
 const CPURegList kCallerSaved = CPURegList::GetCallerSaved();
 const CPURegList kCallerSavedV = CPURegList::GetCallerSavedV();
 
-
-// Registers.
-#define WREG(n) w##n,
-const Register Register::wregisters[] = {AARCH64_REGISTER_CODE_LIST(WREG)};
-#undef WREG
-
-#define XREG(n) x##n,
-const Register Register::xregisters[] = {AARCH64_REGISTER_CODE_LIST(XREG)};
-#undef XREG
-
-#define BREG(n) b##n,
-const VRegister VRegister::bregisters[] = {AARCH64_REGISTER_CODE_LIST(BREG)};
-#undef BREG
-
-#define HREG(n) h##n,
-const VRegister VRegister::hregisters[] = {AARCH64_REGISTER_CODE_LIST(HREG)};
-#undef HREG
-
-#define SREG(n) s##n,
-const VRegister VRegister::sregisters[] = {AARCH64_REGISTER_CODE_LIST(SREG)};
-#undef SREG
-
-#define DREG(n) d##n,
-const VRegister VRegister::dregisters[] = {AARCH64_REGISTER_CODE_LIST(DREG)};
-#undef DREG
-
-#define QREG(n) q##n,
-const VRegister VRegister::qregisters[] = {AARCH64_REGISTER_CODE_LIST(QREG)};
-#undef QREG
-
-#define VREG(n) v##n,
-const VRegister VRegister::vregisters[] = {AARCH64_REGISTER_CODE_LIST(VREG)};
-#undef VREG
-
-
-const Register& Register::GetWRegFromCode(unsigned code) {
-  if (code == kSPRegInternalCode) {
-    return wsp;
-  } else {
-    VIXL_ASSERT(code < kNumberOfRegisters);
-    return wregisters[code];
-  }
-}
-
-
-const Register& Register::GetXRegFromCode(unsigned code) {
-  if (code == kSPRegInternalCode) {
-    return sp;
-  } else {
-    VIXL_ASSERT(code < kNumberOfRegisters);
-    return xregisters[code];
-  }
-}
-
-
-const VRegister& VRegister::GetBRegFromCode(unsigned code) {
-  VIXL_ASSERT(code < kNumberOfVRegisters);
-  return bregisters[code];
-}
-
-
-const VRegister& VRegister::GetHRegFromCode(unsigned code) {
-  VIXL_ASSERT(code < kNumberOfVRegisters);
-  return hregisters[code];
-}
-
-
-const VRegister& VRegister::GetSRegFromCode(unsigned code) {
-  VIXL_ASSERT(code < kNumberOfVRegisters);
-  return sregisters[code];
-}
-
-
-const VRegister& VRegister::GetDRegFromCode(unsigned code) {
-  VIXL_ASSERT(code < kNumberOfVRegisters);
-  return dregisters[code];
-}
-
-
-const VRegister& VRegister::GetQRegFromCode(unsigned code) {
-  VIXL_ASSERT(code < kNumberOfVRegisters);
-  return qregisters[code];
-}
-
-
-const VRegister& VRegister::GetVRegFromCode(unsigned code) {
-  VIXL_ASSERT(code < kNumberOfVRegisters);
-  return vregisters[code];
-}
-
-
-const Register& CPURegister::W() const {
-  VIXL_ASSERT(IsValidRegister());
-  return Register::GetWRegFromCode(code_);
-}
-
-
-const Register& CPURegister::X() const {
-  VIXL_ASSERT(IsValidRegister());
-  return Register::GetXRegFromCode(code_);
-}
-
-
-const VRegister& CPURegister::B() const {
-  VIXL_ASSERT(IsValidVRegister());
-  return VRegister::GetBRegFromCode(code_);
-}
-
-
-const VRegister& CPURegister::H() const {
-  VIXL_ASSERT(IsValidVRegister());
-  return VRegister::GetHRegFromCode(code_);
-}
-
-
-const VRegister& CPURegister::S() const {
-  VIXL_ASSERT(IsValidVRegister());
-  return VRegister::GetSRegFromCode(code_);
-}
-
-
-const VRegister& CPURegister::D() const {
-  VIXL_ASSERT(IsValidVRegister());
-  return VRegister::GetDRegFromCode(code_);
-}
-
-
-const VRegister& CPURegister::Q() const {
-  VIXL_ASSERT(IsValidVRegister());
-  return VRegister::GetQRegFromCode(code_);
-}
-
-
-const VRegister& CPURegister::V() const {
-  VIXL_ASSERT(IsValidVRegister());
-  return VRegister::GetVRegFromCode(code_);
-}
-
-
 // Operand.
 Operand::Operand(int64_t immediate)
     : immediate_(immediate),
@@ -296,6 +152,12 @@ Operand::Operand(int64_t immediate)
       extend_(NO_EXTEND),
       shift_amount_(0) {}
 
+Operand::Operand(IntegerOperand immediate)
+    : immediate_(immediate.AsIntN(64)),
+      reg_(NoReg),
+      shift_(NO_SHIFT),
+      extend_(NO_EXTEND),
+      shift_amount_(0) {}
 
 Operand::Operand(Register reg, Shift shift, unsigned shift_amount)
     : reg_(reg),
@@ -471,6 +333,24 @@ MemOperand::MemOperand(Register base, const Operand& offset, AddrMode addrmode)
 }
 
 
+bool MemOperand::IsPlainRegister() const {
+  return IsImmediateOffset() && (GetOffset() == 0);
+}
+
+
+bool MemOperand::IsEquivalentToPlainRegister() const {
+  if (regoffset_.Is(NoReg)) {
+    // Immediate offset, pre-index or post-index.
+    return GetOffset() == 0;
+  } else if (GetRegisterOffset().IsZero()) {
+    // Zero register offset, pre-index or post-index.
+    // We can ignore shift and extend options because they all result in zero.
+    return true;
+  }
+  return false;
+}
+
+
 bool MemOperand::IsImmediateOffset() const {
   return (addrmode_ == Offset) && regoffset_.Is(NoReg);
 }
@@ -493,6 +373,62 @@ void MemOperand::AddOffset(int64_t offset) {
 }
 
 
+bool SVEMemOperand::IsValid() const {
+#ifdef VIXL_DEBUG
+  {
+    // It should not be possible for an SVEMemOperand to match multiple types.
+    int count = 0;
+    if (IsScalarPlusImmediate()) count++;
+    if (IsScalarPlusScalar()) count++;
+    if (IsScalarPlusVector()) count++;
+    if (IsVectorPlusImmediate()) count++;
+    if (IsVectorPlusVector()) count++;
+    VIXL_ASSERT(count <= 1);
+  }
+#endif
+
+  // We can't have a register _and_ an immediate offset.
+  if ((offset_ != 0) && (!regoffset_.IsNone())) return false;
+
+  if (shift_amount_ != 0) {
+    // Only shift and extend modifiers can take a shift amount.
+    switch (mod_) {
+      case NO_SVE_OFFSET_MODIFIER:
+      case SVE_MUL_VL:
+        return false;
+      case SVE_LSL:
+      case SVE_UXTW:
+      case SVE_SXTW:
+        // Fall through.
+        break;
+    }
+  }
+
+  return IsScalarPlusImmediate() || IsScalarPlusScalar() ||
+         IsScalarPlusVector() || IsVectorPlusImmediate() ||
+         IsVectorPlusVector();
+}
+
+
+bool SVEMemOperand::IsEquivalentToScalar() const {
+  if (IsScalarPlusImmediate()) {
+    return GetImmediateOffset() == 0;
+  }
+  if (IsScalarPlusScalar()) {
+    // We can ignore the shift because it will still result in zero.
+    return GetScalarOffset().IsZero();
+  }
+  // Forms involving vectors are never equivalent to a single scalar.
+  return false;
+}
+
+bool SVEMemOperand::IsPlainRegister() const {
+  if (IsScalarPlusImmediate()) {
+    return GetImmediateOffset() == 0;
+  }
+  return false;
+}
+
 GenericOperand::GenericOperand(const CPURegister& reg)
     : cpu_register_(reg), mem_op_size_(0) {
   if (reg.IsQ()) {
diff --git a/src/aarch64/operands-aarch64.h b/src/aarch64/operands-aarch64.h
index bfc6b702..ad03a9ee 100644
--- a/src/aarch64/operands-aarch64.h
+++ b/src/aarch64/operands-aarch64.h
@@ -27,525 +27,15 @@
 #ifndef VIXL_AARCH64_OPERANDS_AARCH64_H_
 #define VIXL_AARCH64_OPERANDS_AARCH64_H_
 
+#include <sstream>
+#include <string>
+
 #include "instructions-aarch64.h"
+#include "registers-aarch64.h"
 
 namespace vixl {
 namespace aarch64 {
 
-typedef uint64_t RegList;
-static const int kRegListSizeInBits = sizeof(RegList) * 8;
-
-
-// Registers.
-
-// Some CPURegister methods can return Register or VRegister types, so we need
-// to declare them in advance.
-class Register;
-class VRegister;
-
-class CPURegister {
- public:
-  enum RegisterType {
-    // The kInvalid value is used to detect uninitialized static instances,
-    // which are always zero-initialized before any constructors are called.
-    kInvalid = 0,
-    kRegister,
-    kVRegister,
-    kNoRegister
-  };
-
-  CPURegister() : code_(0), size_(0), type_(kNoRegister) {
-    VIXL_ASSERT(!IsValid());
-    VIXL_ASSERT(IsNone());
-  }
-
-  CPURegister(unsigned code, unsigned size, RegisterType type)
-      : code_(code), size_(size), type_(type) {
-    VIXL_ASSERT(IsValidOrNone());
-  }
-
-  unsigned GetCode() const {
-    VIXL_ASSERT(IsValid());
-    return code_;
-  }
-  VIXL_DEPRECATED("GetCode", unsigned code() const) { return GetCode(); }
-
-  RegisterType GetType() const {
-    VIXL_ASSERT(IsValidOrNone());
-    return type_;
-  }
-  VIXL_DEPRECATED("GetType", RegisterType type() const) { return GetType(); }
-
-  RegList GetBit() const {
-    VIXL_ASSERT(code_ < (sizeof(RegList) * 8));
-    return IsValid() ? (static_cast<RegList>(1) << code_) : 0;
-  }
-  VIXL_DEPRECATED("GetBit", RegList Bit() const) { return GetBit(); }
-
-  int GetSizeInBytes() const {
-    VIXL_ASSERT(IsValid());
-    VIXL_ASSERT(size_ % 8 == 0);
-    return size_ / 8;
-  }
-  VIXL_DEPRECATED("GetSizeInBytes", int SizeInBytes() const) {
-    return GetSizeInBytes();
-  }
-
-  int GetSizeInBits() const {
-    VIXL_ASSERT(IsValid());
-    return size_;
-  }
-  VIXL_DEPRECATED("GetSizeInBits", unsigned size() const) {
-    return GetSizeInBits();
-  }
-  VIXL_DEPRECATED("GetSizeInBits", int SizeInBits() const) {
-    return GetSizeInBits();
-  }
-
-  bool Is8Bits() const {
-    VIXL_ASSERT(IsValid());
-    return size_ == 8;
-  }
-
-  bool Is16Bits() const {
-    VIXL_ASSERT(IsValid());
-    return size_ == 16;
-  }
-
-  bool Is32Bits() const {
-    VIXL_ASSERT(IsValid());
-    return size_ == 32;
-  }
-
-  bool Is64Bits() const {
-    VIXL_ASSERT(IsValid());
-    return size_ == 64;
-  }
-
-  bool Is128Bits() const {
-    VIXL_ASSERT(IsValid());
-    return size_ == 128;
-  }
-
-  bool IsValid() const {
-    if (IsValidRegister() || IsValidVRegister()) {
-      VIXL_ASSERT(!IsNone());
-      return true;
-    } else {
-      // This assert is hit when the register has not been properly initialized.
-      // One cause for this can be an initialisation order fiasco. See
-      // https://isocpp.org/wiki/faq/ctors#static-init-order for some details.
-      VIXL_ASSERT(IsNone());
-      return false;
-    }
-  }
-
-  bool IsValidRegister() const {
-    return IsRegister() && ((size_ == kWRegSize) || (size_ == kXRegSize)) &&
-           ((code_ < kNumberOfRegisters) || (code_ == kSPRegInternalCode));
-  }
-
-  bool IsValidVRegister() const {
-    return IsVRegister() && ((size_ == kBRegSize) || (size_ == kHRegSize) ||
-                             (size_ == kSRegSize) || (size_ == kDRegSize) ||
-                             (size_ == kQRegSize)) &&
-           (code_ < kNumberOfVRegisters);
-  }
-
-  bool IsValidFPRegister() const {
-    return IsValidVRegister() && IsFPRegister();
-  }
-
-  bool IsNone() const {
-    // kNoRegister types should always have size 0 and code 0.
-    VIXL_ASSERT((type_ != kNoRegister) || (code_ == 0));
-    VIXL_ASSERT((type_ != kNoRegister) || (size_ == 0));
-
-    return type_ == kNoRegister;
-  }
-
-  bool Aliases(const CPURegister& other) const {
-    VIXL_ASSERT(IsValidOrNone() && other.IsValidOrNone());
-    return (code_ == other.code_) && (type_ == other.type_);
-  }
-
-  bool Is(const CPURegister& other) const {
-    VIXL_ASSERT(IsValidOrNone() && other.IsValidOrNone());
-    return Aliases(other) && (size_ == other.size_);
-  }
-
-  bool IsZero() const {
-    VIXL_ASSERT(IsValid());
-    return IsRegister() && (code_ == kZeroRegCode);
-  }
-
-  bool IsSP() const {
-    VIXL_ASSERT(IsValid());
-    return IsRegister() && (code_ == kSPRegInternalCode);
-  }
-
-  bool IsRegister() const { return type_ == kRegister; }
-
-  bool IsVRegister() const { return type_ == kVRegister; }
-
-  // CPURegister does not track lanes like VRegister does, so we have to assume
-  // that we have scalar types here.
-  // TODO: Encode lane information in CPURegister so that we can be consistent.
-  bool IsFPRegister() const { return IsH() || IsS() || IsD(); }
-
-  bool IsW() const { return IsValidRegister() && Is32Bits(); }
-  bool IsX() const { return IsValidRegister() && Is64Bits(); }
-
-  // These assertions ensure that the size and type of the register are as
-  // described. They do not consider the number of lanes that make up a vector.
-  // So, for example, Is8B() implies IsD(), and Is1D() implies IsD, but IsD()
-  // does not imply Is1D() or Is8B().
-  // Check the number of lanes, ie. the format of the vector, using methods such
-  // as Is8B(), Is1D(), etc. in the VRegister class.
-  bool IsV() const { return IsVRegister(); }
-  bool IsB() const { return IsV() && Is8Bits(); }
-  bool IsH() const { return IsV() && Is16Bits(); }
-  bool IsS() const { return IsV() && Is32Bits(); }
-  bool IsD() const { return IsV() && Is64Bits(); }
-  bool IsQ() const { return IsV() && Is128Bits(); }
-
-  // Semantic type for sdot and udot instructions.
-  bool IsS4B() const { return IsS(); }
-  const VRegister& S4B() const { return S(); }
-
-  const Register& W() const;
-  const Register& X() const;
-  const VRegister& V() const;
-  const VRegister& B() const;
-  const VRegister& H() const;
-  const VRegister& S() const;
-  const VRegister& D() const;
-  const VRegister& Q() const;
-
-  bool IsSameType(const CPURegister& other) const {
-    return type_ == other.type_;
-  }
-
-  bool IsSameSizeAndType(const CPURegister& other) const {
-    return (size_ == other.size_) && IsSameType(other);
-  }
-
- protected:
-  unsigned code_;
-  int size_;
-  RegisterType type_;
-
- private:
-  bool IsValidOrNone() const { return IsValid() || IsNone(); }
-};
-
-
-class Register : public CPURegister {
- public:
-  Register() : CPURegister() {}
-  explicit Register(const CPURegister& other)
-      : CPURegister(other.GetCode(), other.GetSizeInBits(), other.GetType()) {
-    VIXL_ASSERT(IsValidRegister());
-  }
-  Register(unsigned code, unsigned size) : CPURegister(code, size, kRegister) {}
-
-  bool IsValid() const {
-    VIXL_ASSERT(IsRegister() || IsNone());
-    return IsValidRegister();
-  }
-
-  static const Register& GetWRegFromCode(unsigned code);
-  VIXL_DEPRECATED("GetWRegFromCode",
-                  static const Register& WRegFromCode(unsigned code)) {
-    return GetWRegFromCode(code);
-  }
-
-  static const Register& GetXRegFromCode(unsigned code);
-  VIXL_DEPRECATED("GetXRegFromCode",
-                  static const Register& XRegFromCode(unsigned code)) {
-    return GetXRegFromCode(code);
-  }
-
- private:
-  static const Register wregisters[];
-  static const Register xregisters[];
-};
-
-
-namespace internal {
-
-template <int size_in_bits>
-class FixedSizeRegister : public Register {
- public:
-  FixedSizeRegister() : Register() {}
-  explicit FixedSizeRegister(unsigned code) : Register(code, size_in_bits) {
-    VIXL_ASSERT(IsValidRegister());
-  }
-  explicit FixedSizeRegister(const Register& other)
-      : Register(other.GetCode(), size_in_bits) {
-    VIXL_ASSERT(other.GetSizeInBits() == size_in_bits);
-    VIXL_ASSERT(IsValidRegister());
-  }
-  explicit FixedSizeRegister(const CPURegister& other)
-      : Register(other.GetCode(), other.GetSizeInBits()) {
-    VIXL_ASSERT(other.GetType() == kRegister);
-    VIXL_ASSERT(other.GetSizeInBits() == size_in_bits);
-    VIXL_ASSERT(IsValidRegister());
-  }
-
-  bool IsValid() const {
-    return Register::IsValid() && (GetSizeInBits() == size_in_bits);
-  }
-};
-
-}  // namespace internal
-
-typedef internal::FixedSizeRegister<kXRegSize> XRegister;
-typedef internal::FixedSizeRegister<kWRegSize> WRegister;
-
-
-class VRegister : public CPURegister {
- public:
-  VRegister() : CPURegister(), lanes_(1) {}
-  explicit VRegister(const CPURegister& other)
-      : CPURegister(other.GetCode(), other.GetSizeInBits(), other.GetType()),
-        lanes_(1) {
-    VIXL_ASSERT(IsValidVRegister());
-    VIXL_ASSERT(IsPowerOf2(lanes_) && (lanes_ <= 16));
-  }
-  VRegister(unsigned code, unsigned size, unsigned lanes = 1)
-      : CPURegister(code, size, kVRegister), lanes_(lanes) {
-    VIXL_ASSERT(IsPowerOf2(lanes_) && (lanes_ <= 16));
-  }
-  VRegister(unsigned code, VectorFormat format)
-      : CPURegister(code, RegisterSizeInBitsFromFormat(format), kVRegister),
-        lanes_(IsVectorFormat(format) ? LaneCountFromFormat(format) : 1) {
-    VIXL_ASSERT(IsPowerOf2(lanes_) && (lanes_ <= 16));
-  }
-
-  bool IsValid() const {
-    VIXL_ASSERT(IsVRegister() || IsNone());
-    return IsValidVRegister();
-  }
-
-  static const VRegister& GetBRegFromCode(unsigned code);
-  VIXL_DEPRECATED("GetBRegFromCode",
-                  static const VRegister& BRegFromCode(unsigned code)) {
-    return GetBRegFromCode(code);
-  }
-
-  static const VRegister& GetHRegFromCode(unsigned code);
-  VIXL_DEPRECATED("GetHRegFromCode",
-                  static const VRegister& HRegFromCode(unsigned code)) {
-    return GetHRegFromCode(code);
-  }
-
-  static const VRegister& GetSRegFromCode(unsigned code);
-  VIXL_DEPRECATED("GetSRegFromCode",
-                  static const VRegister& SRegFromCode(unsigned code)) {
-    return GetSRegFromCode(code);
-  }
-
-  static const VRegister& GetDRegFromCode(unsigned code);
-  VIXL_DEPRECATED("GetDRegFromCode",
-                  static const VRegister& DRegFromCode(unsigned code)) {
-    return GetDRegFromCode(code);
-  }
-
-  static const VRegister& GetQRegFromCode(unsigned code);
-  VIXL_DEPRECATED("GetQRegFromCode",
-                  static const VRegister& QRegFromCode(unsigned code)) {
-    return GetQRegFromCode(code);
-  }
-
-  static const VRegister& GetVRegFromCode(unsigned code);
-  VIXL_DEPRECATED("GetVRegFromCode",
-                  static const VRegister& VRegFromCode(unsigned code)) {
-    return GetVRegFromCode(code);
-  }
-
-  VRegister V8B() const { return VRegister(code_, kDRegSize, 8); }
-  VRegister V16B() const { return VRegister(code_, kQRegSize, 16); }
-  VRegister V2H() const { return VRegister(code_, kSRegSize, 2); }
-  VRegister V4H() const { return VRegister(code_, kDRegSize, 4); }
-  VRegister V8H() const { return VRegister(code_, kQRegSize, 8); }
-  VRegister V2S() const { return VRegister(code_, kDRegSize, 2); }
-  VRegister V4S() const { return VRegister(code_, kQRegSize, 4); }
-  VRegister V2D() const { return VRegister(code_, kQRegSize, 2); }
-  VRegister V1D() const { return VRegister(code_, kDRegSize, 1); }
-
-  bool Is8B() const { return (Is64Bits() && (lanes_ == 8)); }
-  bool Is16B() const { return (Is128Bits() && (lanes_ == 16)); }
-  bool Is2H() const { return (Is32Bits() && (lanes_ == 2)); }
-  bool Is4H() const { return (Is64Bits() && (lanes_ == 4)); }
-  bool Is8H() const { return (Is128Bits() && (lanes_ == 8)); }
-  bool Is1S() const { return (Is32Bits() && (lanes_ == 1)); }
-  bool Is2S() const { return (Is64Bits() && (lanes_ == 2)); }
-  bool Is4S() const { return (Is128Bits() && (lanes_ == 4)); }
-  bool Is1D() const { return (Is64Bits() && (lanes_ == 1)); }
-  bool Is2D() const { return (Is128Bits() && (lanes_ == 2)); }
-
-  // For consistency, we assert the number of lanes of these scalar registers,
-  // even though there are no vectors of equivalent total size with which they
-  // could alias.
-  bool Is1B() const {
-    VIXL_ASSERT(!(Is8Bits() && IsVector()));
-    return Is8Bits();
-  }
-  bool Is1H() const {
-    VIXL_ASSERT(!(Is16Bits() && IsVector()));
-    return Is16Bits();
-  }
-
-  // Semantic type for sdot and udot instructions.
-  bool Is1S4B() const { return Is1S(); }
-
-
-  bool IsLaneSizeB() const { return GetLaneSizeInBits() == kBRegSize; }
-  bool IsLaneSizeH() const { return GetLaneSizeInBits() == kHRegSize; }
-  bool IsLaneSizeS() const { return GetLaneSizeInBits() == kSRegSize; }
-  bool IsLaneSizeD() const { return GetLaneSizeInBits() == kDRegSize; }
-
-  int GetLanes() const { return lanes_; }
-  VIXL_DEPRECATED("GetLanes", int lanes() const) { return GetLanes(); }
-
-  bool IsFPRegister() const { return Is1H() || Is1S() || Is1D(); }
-  bool IsValidFPRegister() const {
-    return IsValidVRegister() && IsFPRegister();
-  }
-
-  bool IsScalar() const { return lanes_ == 1; }
-
-  bool IsVector() const { return lanes_ > 1; }
-
-  bool IsSameFormat(const VRegister& other) const {
-    return (size_ == other.size_) && (lanes_ == other.lanes_);
-  }
-
-  unsigned GetLaneSizeInBytes() const { return GetSizeInBytes() / lanes_; }
-  VIXL_DEPRECATED("GetLaneSizeInBytes", unsigned LaneSizeInBytes() const) {
-    return GetLaneSizeInBytes();
-  }
-
-  unsigned GetLaneSizeInBits() const { return GetLaneSizeInBytes() * 8; }
-  VIXL_DEPRECATED("GetLaneSizeInBits", unsigned LaneSizeInBits() const) {
-    return GetLaneSizeInBits();
-  }
-
- private:
-  static const VRegister bregisters[];
-  static const VRegister hregisters[];
-  static const VRegister sregisters[];
-  static const VRegister dregisters[];
-  static const VRegister qregisters[];
-  static const VRegister vregisters[];
-  int lanes_;
-};
-
-
-// No*Reg is used to indicate an unused argument, or an error case. Note that
-// these all compare equal (using the Is() method). The Register and VRegister
-// variants are provided for convenience.
-const Register NoReg;
-const VRegister NoVReg;
-const CPURegister NoCPUReg;
-
-
-#define DEFINE_REGISTERS(N) \
-  const WRegister w##N(N);  \
-  const XRegister x##N(N);
-AARCH64_REGISTER_CODE_LIST(DEFINE_REGISTERS)
-#undef DEFINE_REGISTERS
-const WRegister wsp(kSPRegInternalCode);
-const XRegister sp(kSPRegInternalCode);
-
-
-#define DEFINE_VREGISTERS(N)          \
-  const VRegister b##N(N, kBRegSize); \
-  const VRegister h##N(N, kHRegSize); \
-  const VRegister s##N(N, kSRegSize); \
-  const VRegister d##N(N, kDRegSize); \
-  const VRegister q##N(N, kQRegSize); \
-  const VRegister v##N(N, kQRegSize);
-AARCH64_REGISTER_CODE_LIST(DEFINE_VREGISTERS)
-#undef DEFINE_VREGISTERS
-
-
-// Register aliases.
-const XRegister ip0 = x16;
-const XRegister ip1 = x17;
-const XRegister lr = x30;
-const XRegister xzr = x31;
-const WRegister wzr = w31;
-
-
-// AreAliased returns true if any of the named registers overlap. Arguments
-// set to NoReg are ignored. The system stack pointer may be specified.
-bool AreAliased(const CPURegister& reg1,
-                const CPURegister& reg2,
-                const CPURegister& reg3 = NoReg,
-                const CPURegister& reg4 = NoReg,
-                const CPURegister& reg5 = NoReg,
-                const CPURegister& reg6 = NoReg,
-                const CPURegister& reg7 = NoReg,
-                const CPURegister& reg8 = NoReg);
-
-
-// AreSameSizeAndType returns true if all of the specified registers have the
-// same size, and are of the same type. The system stack pointer may be
-// specified. Arguments set to NoReg are ignored, as are any subsequent
-// arguments. At least one argument (reg1) must be valid (not NoCPUReg).
-bool AreSameSizeAndType(const CPURegister& reg1,
-                        const CPURegister& reg2,
-                        const CPURegister& reg3 = NoCPUReg,
-                        const CPURegister& reg4 = NoCPUReg,
-                        const CPURegister& reg5 = NoCPUReg,
-                        const CPURegister& reg6 = NoCPUReg,
-                        const CPURegister& reg7 = NoCPUReg,
-                        const CPURegister& reg8 = NoCPUReg);
-
-// AreEven returns true if all of the specified registers have even register
-// indices. Arguments set to NoReg are ignored, as are any subsequent
-// arguments. At least one argument (reg1) must be valid (not NoCPUReg).
-bool AreEven(const CPURegister& reg1,
-             const CPURegister& reg2,
-             const CPURegister& reg3 = NoReg,
-             const CPURegister& reg4 = NoReg,
-             const CPURegister& reg5 = NoReg,
-             const CPURegister& reg6 = NoReg,
-             const CPURegister& reg7 = NoReg,
-             const CPURegister& reg8 = NoReg);
-
-
-// AreConsecutive returns true if all of the specified registers are
-// consecutive in the register file. Arguments set to NoReg are ignored, as are
-// any subsequent arguments. At least one argument (reg1) must be valid
-// (not NoCPUReg).
-bool AreConsecutive(const CPURegister& reg1,
-                    const CPURegister& reg2,
-                    const CPURegister& reg3 = NoCPUReg,
-                    const CPURegister& reg4 = NoCPUReg);
-
-
-// AreSameFormat returns true if all of the specified VRegisters have the same
-// vector format. Arguments set to NoReg are ignored, as are any subsequent
-// arguments. At least one argument (reg1) must be valid (not NoVReg).
-bool AreSameFormat(const VRegister& reg1,
-                   const VRegister& reg2,
-                   const VRegister& reg3 = NoVReg,
-                   const VRegister& reg4 = NoVReg);
-
-
-// AreConsecutive returns true if all of the specified VRegisters are
-// consecutive in the register file. Arguments set to NoReg are ignored, as are
-// any subsequent arguments. At least one argument (reg1) must be valid
-// (not NoVReg).
-bool AreConsecutive(const VRegister& reg1,
-                    const VRegister& reg2,
-                    const VRegister& reg3 = NoVReg,
-                    const VRegister& reg4 = NoVReg);
-
-
 // Lists of registers.
 class CPURegList {
  public:
@@ -580,6 +70,28 @@ class CPURegList {
     VIXL_ASSERT(IsValid());
   }
 
+  // Construct an empty CPURegList with the specified size and type. If `size`
+  // is CPURegister::kUnknownSize and the register type requires a size, a valid
+  // but unspecified default will be picked.
+  static CPURegList Empty(CPURegister::RegisterType type,
+                          unsigned size = CPURegister::kUnknownSize) {
+    return CPURegList(type, GetDefaultSizeFor(type, size), 0);
+  }
+
+  // Construct a CPURegList with all possible registers with the specified size
+  // and type. If `size` is CPURegister::kUnknownSize and the register type
+  // requires a size, a valid but unspecified default will be picked.
+  static CPURegList All(CPURegister::RegisterType type,
+                        unsigned size = CPURegister::kUnknownSize) {
+    unsigned number_of_registers = (CPURegister::GetMaxCodeFor(type) + 1);
+    RegList list = (static_cast<RegList>(1) << number_of_registers) - 1;
+    if (type == CPURegister::kRegister) {
+      // GetMaxCodeFor(kRegister) ignores SP, so explicitly include it.
+      list |= (static_cast<RegList>(1) << kSPRegInternalCode);
+    }
+    return CPURegList(type, GetDefaultSizeFor(type, size), list);
+  }
+
   CPURegister::RegisterType GetType() const {
     VIXL_ASSERT(IsValid());
     return type_;
@@ -588,6 +100,10 @@ class CPURegList {
     return GetType();
   }
 
+  CPURegister::RegisterBank GetBank() const {
+    return CPURegister::GetBankFor(GetType());
+  }
+
   // Combine another CPURegList into this one. Registers that already exist in
   // this list are left unchanged. The type and size of the registers in the
   // 'other' list must match those in this list.
@@ -684,8 +200,11 @@ class CPURegList {
   // preparing registers for an AAPCS64 function call, for example.
   void RemoveCalleeSaved();
 
-  CPURegister PopLowestIndex();
-  CPURegister PopHighestIndex();
+  // Find the register in this list that appears in `mask` with the lowest or
+  // highest code, remove it from the list and return it as a CPURegister. If
+  // the list is empty, leave it unchanged and return NoCPUReg.
+  CPURegister PopLowestIndex(RegList mask = ~static_cast<RegList>(0));
+  CPURegister PopHighestIndex(RegList mask = ~static_cast<RegList>(0));
 
   // AAPCS64 callee-saved registers.
   static CPURegList GetCalleeSaved(unsigned size = kXRegSize);
@@ -704,7 +223,7 @@ class CPURegList {
 
   bool IncludesAliasOf(const CPURegister& other) const {
     VIXL_ASSERT(IsValid());
-    return (type_ == other.GetType()) && IncludesAliasOf(other.GetCode());
+    return (GetBank() == other.GetBank()) && IncludesAliasOf(other.GetCode());
   }
 
   bool IncludesAliasOf(int code) const {
@@ -744,6 +263,21 @@ class CPURegList {
   }
 
  private:
+  // If `size` is CPURegister::kUnknownSize and the type requires a known size,
+  // then return an arbitrary-but-valid size.
+  //
+  // Otherwise, the size is checked for validity and returned unchanged.
+  static unsigned GetDefaultSizeFor(CPURegister::RegisterType type,
+                                    unsigned size) {
+    if (size == CPURegister::kUnknownSize) {
+      if (type == CPURegister::kRegister) size = kXRegSize;
+      if (type == CPURegister::kVRegister) size = kQRegSize;
+      // All other types require kUnknownSize.
+    }
+    VIXL_ASSERT(CPURegister(0, size, type).IsValid());
+    return size;
+  }
+
   RegList list_;
   int size_;
   CPURegister::RegisterType type_;
@@ -761,6 +295,7 @@ extern const CPURegList kCalleeSavedV;
 extern const CPURegList kCallerSaved;
 extern const CPURegList kCallerSavedV;
 
+class IntegerOperand;
 
 // Operand.
 class Operand {
@@ -769,7 +304,9 @@ class Operand {
   // where <immediate> is int64_t.
   // This is allowed to be an implicit constructor because Operand is
   // a wrapper class that doesn't normally perform any type conversion.
-  Operand(int64_t immediate = 0);  // NOLINT(runtime/explicit)
+  Operand(int64_t immediate);  // NOLINT(runtime/explicit)
+
+  Operand(IntegerOperand immediate);  // NOLINT(runtime/explicit)
 
   // rm, {<shift> #<shift_amount>}
   // where <shift> is one of {LSL, LSR, ASR, ROR}.
@@ -883,6 +420,16 @@ class MemOperand {
     return shift_amount_;
   }
 
+  // True for MemOperands which represent something like [x0].
+  // Currently, this will also return true for [x0, #0], because MemOperand has
+  // no way to distinguish the two.
+  bool IsPlainRegister() const;
+
+  // True for MemOperands which represent something like [x0], or for compound
+  // MemOperands which are functionally equivalent, such as [x0, #0], [x0, xzr]
+  // or [x0, wzr, UXTW #3].
+  bool IsEquivalentToPlainRegister() const;
+
   // True for immediate-offset (but not indexed) MemOperands.
   bool IsImmediateOffset() const;
   // True for register-offset (but not indexed) MemOperands.
@@ -918,6 +465,448 @@ class MemOperand {
   unsigned shift_amount_;
 };
 
+// SVE supports memory operands which don't make sense to the core ISA, such as
+// scatter-gather forms, in which either the base or offset registers are
+// vectors. This class exists to avoid complicating core-ISA code with
+// SVE-specific behaviour.
+//
+// Note that SVE does not support any pre- or post-index modes.
+class SVEMemOperand {
+ public:
+  // "vector-plus-immediate", like [z0.s, #21]
+  explicit SVEMemOperand(ZRegister base, uint64_t offset = 0)
+      : base_(base),
+        regoffset_(NoReg),
+        offset_(RawbitsToInt64(offset)),
+        mod_(NO_SVE_OFFSET_MODIFIER),
+        shift_amount_(0) {
+    VIXL_ASSERT(IsVectorPlusImmediate());
+    VIXL_ASSERT(IsValid());
+  }
+
+  // "scalar-plus-immediate", like [x0], [x0, #42] or [x0, #42, MUL_VL]
+  // The only supported modifiers are NO_SVE_OFFSET_MODIFIER or SVE_MUL_VL.
+  //
+  // Note that VIXL cannot currently distinguish between `SVEMemOperand(x0)` and
+  // `SVEMemOperand(x0, 0)`. This is only significant in scalar-plus-scalar
+  // instructions where xm defaults to xzr. However, users should not rely on
+  // `SVEMemOperand(x0, 0)` being accepted in such cases.
+  explicit SVEMemOperand(Register base,
+                         uint64_t offset = 0,
+                         SVEOffsetModifier mod = NO_SVE_OFFSET_MODIFIER)
+      : base_(base),
+        regoffset_(NoReg),
+        offset_(RawbitsToInt64(offset)),
+        mod_(mod),
+        shift_amount_(0) {
+    VIXL_ASSERT(IsScalarPlusImmediate());
+    VIXL_ASSERT(IsValid());
+  }
+
+  // "scalar-plus-scalar", like [x0, x1]
+  // "scalar-plus-vector", like [x0, z1.d]
+  SVEMemOperand(Register base, CPURegister offset)
+      : base_(base),
+        regoffset_(offset),
+        offset_(0),
+        mod_(NO_SVE_OFFSET_MODIFIER),
+        shift_amount_(0) {
+    VIXL_ASSERT(IsScalarPlusScalar() || IsScalarPlusVector());
+    if (offset.IsZero()) VIXL_ASSERT(IsEquivalentToScalar());
+    VIXL_ASSERT(IsValid());
+  }
+
+  // "scalar-plus-vector", like [x0, z1.d, UXTW]
+  // The type of `mod` can be any `SVEOffsetModifier` (other than LSL), or a
+  // corresponding `Extend` value.
+  template <typename M>
+  SVEMemOperand(Register base, ZRegister offset, M mod)
+      : base_(base),
+        regoffset_(offset),
+        offset_(0),
+        mod_(GetSVEOffsetModifierFor(mod)),
+        shift_amount_(0) {
+    VIXL_ASSERT(mod_ != SVE_LSL);  // LSL requires an explicit shift amount.
+    VIXL_ASSERT(IsScalarPlusVector());
+    VIXL_ASSERT(IsValid());
+  }
+
+  // "scalar-plus-scalar", like [x0, x1, LSL #1]
+  // "scalar-plus-vector", like [x0, z1.d, LSL #2]
+  // The type of `mod` can be any `SVEOffsetModifier`, or a corresponding
+  // `Shift` or `Extend` value.
+  template <typename M>
+  SVEMemOperand(Register base, CPURegister offset, M mod, unsigned shift_amount)
+      : base_(base),
+        regoffset_(offset),
+        offset_(0),
+        mod_(GetSVEOffsetModifierFor(mod)),
+        shift_amount_(shift_amount) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  // "vector-plus-vector", like [z0.d, z1.d, UXTW]
+  template <typename M = SVEOffsetModifier>
+  SVEMemOperand(ZRegister base,
+                ZRegister offset,
+                M mod = NO_SVE_OFFSET_MODIFIER,
+                unsigned shift_amount = 0)
+      : base_(base),
+        regoffset_(offset),
+        offset_(0),
+        mod_(GetSVEOffsetModifierFor(mod)),
+        shift_amount_(shift_amount) {
+    VIXL_ASSERT(IsValid());
+    VIXL_ASSERT(IsVectorPlusVector());
+  }
+
+  // True for SVEMemOperands which represent something like [x0].
+  // This will also return true for [x0, #0], because there is no way
+  // to distinguish the two.
+  bool IsPlainScalar() const {
+    return IsScalarPlusImmediate() && (offset_ == 0);
+  }
+
+  // True for SVEMemOperands which represent something like [x0], or for
+  // compound SVEMemOperands which are functionally equivalent, such as
+  // [x0, #0], [x0, xzr] or [x0, wzr, UXTW #3].
+  bool IsEquivalentToScalar() const;
+
+  // True for SVEMemOperands like [x0], [x0, #0], false for [x0, xzr] and
+  // similar.
+  bool IsPlainRegister() const;
+
+  bool IsScalarPlusImmediate() const {
+    return base_.IsX() && regoffset_.IsNone() &&
+           ((mod_ == NO_SVE_OFFSET_MODIFIER) || IsMulVl());
+  }
+
+  bool IsScalarPlusScalar() const {
+    // SVE offers no extend modes for scalar-plus-scalar, so both registers must
+    // be X registers.
+    return base_.IsX() && regoffset_.IsX() &&
+           ((mod_ == NO_SVE_OFFSET_MODIFIER) || (mod_ == SVE_LSL));
+  }
+
+  bool IsScalarPlusVector() const {
+    // The modifier can be LSL or an an extend mode (UXTW or SXTW) here. Unlike
+    // in the core ISA, these extend modes do not imply an S-sized lane, so the
+    // modifier is independent from the lane size. The architecture describes
+    // [US]XTW with a D-sized lane as an "unpacked" offset.
+    return base_.IsX() && regoffset_.IsZRegister() &&
+           (regoffset_.IsLaneSizeS() || regoffset_.IsLaneSizeD()) && !IsMulVl();
+  }
+
+  bool IsVectorPlusImmediate() const {
+    return base_.IsZRegister() &&
+           (base_.IsLaneSizeS() || base_.IsLaneSizeD()) &&
+           regoffset_.IsNone() && (mod_ == NO_SVE_OFFSET_MODIFIER);
+  }
+
+  bool IsVectorPlusVector() const {
+    return base_.IsZRegister() && regoffset_.IsZRegister() && (offset_ == 0) &&
+           AreSameFormat(base_, regoffset_) &&
+           (base_.IsLaneSizeS() || base_.IsLaneSizeD());
+  }
+
+  bool IsContiguous() const { return !IsScatterGather(); }
+  bool IsScatterGather() const {
+    return base_.IsZRegister() || regoffset_.IsZRegister();
+  }
+
+  // TODO: If necessary, add helpers like `HasScalarBase()`.
+
+  Register GetScalarBase() const {
+    VIXL_ASSERT(base_.IsX());
+    return Register(base_);
+  }
+
+  ZRegister GetVectorBase() const {
+    VIXL_ASSERT(base_.IsZRegister());
+    VIXL_ASSERT(base_.HasLaneSize());
+    return ZRegister(base_);
+  }
+
+  Register GetScalarOffset() const {
+    VIXL_ASSERT(regoffset_.IsRegister());
+    return Register(regoffset_);
+  }
+
+  ZRegister GetVectorOffset() const {
+    VIXL_ASSERT(regoffset_.IsZRegister());
+    VIXL_ASSERT(regoffset_.HasLaneSize());
+    return ZRegister(regoffset_);
+  }
+
+  int64_t GetImmediateOffset() const {
+    VIXL_ASSERT(regoffset_.IsNone());
+    return offset_;
+  }
+
+  SVEOffsetModifier GetOffsetModifier() const { return mod_; }
+  unsigned GetShiftAmount() const { return shift_amount_; }
+
+  bool IsEquivalentToLSL(unsigned amount) const {
+    if (shift_amount_ != amount) return false;
+    if (amount == 0) {
+      // No-shift is equivalent to "LSL #0".
+      return ((mod_ == SVE_LSL) || (mod_ == NO_SVE_OFFSET_MODIFIER));
+    }
+    return mod_ == SVE_LSL;
+  }
+
+  bool IsMulVl() const { return mod_ == SVE_MUL_VL; }
+
+  bool IsValid() const;
+
+ private:
+  // Allow standard `Shift` and `Extend` arguments to be used.
+  SVEOffsetModifier GetSVEOffsetModifierFor(Shift shift) {
+    if (shift == LSL) return SVE_LSL;
+    if (shift == NO_SHIFT) return NO_SVE_OFFSET_MODIFIER;
+    // SVE does not accept any other shift.
+    VIXL_UNIMPLEMENTED();
+    return NO_SVE_OFFSET_MODIFIER;
+  }
+
+  SVEOffsetModifier GetSVEOffsetModifierFor(Extend extend = NO_EXTEND) {
+    if (extend == UXTW) return SVE_UXTW;
+    if (extend == SXTW) return SVE_SXTW;
+    if (extend == NO_EXTEND) return NO_SVE_OFFSET_MODIFIER;
+    // SVE does not accept any other extend mode.
+    VIXL_UNIMPLEMENTED();
+    return NO_SVE_OFFSET_MODIFIER;
+  }
+
+  SVEOffsetModifier GetSVEOffsetModifierFor(SVEOffsetModifier mod) {
+    return mod;
+  }
+
+  CPURegister base_;
+  CPURegister regoffset_;
+  int64_t offset_;
+  SVEOffsetModifier mod_;
+  unsigned shift_amount_;
+};
+
+// Represent a signed or unsigned integer operand.
+//
+// This is designed to make instructions which naturally accept a _signed_
+// immediate easier to implement and use, when we also want users to be able to
+// specify raw-bits values (such as with hexadecimal constants). The advantage
+// of this class over a simple uint64_t (with implicit C++ sign-extension) is
+// that this class can strictly check the range of allowed values. With a simple
+// uint64_t, it is impossible to distinguish -1 from UINT64_MAX.
+//
+// For example, these instructions are equivalent:
+//
+//     __ Insr(z0.VnB(), -1);
+//     __ Insr(z0.VnB(), 0xff);
+//
+// ... as are these:
+//
+//     __ Insr(z0.VnD(), -1);
+//     __ Insr(z0.VnD(), 0xffffffffffffffff);
+//
+// ... but this is invalid:
+//
+//     __ Insr(z0.VnB(), 0xffffffffffffffff);  // Too big for B-sized lanes.
+class IntegerOperand {
+ public:
+#define VIXL_INT_TYPES(V) \
+  V(char) V(short) V(int) V(long) V(long long)  // NOLINT(runtime/int)
+#define VIXL_DECL_INT_OVERLOADS(T)                                        \
+  /* These are allowed to be implicit constructors because this is a */   \
+  /* wrapper class that doesn't normally perform any type conversion. */  \
+  IntegerOperand(signed T immediate) /* NOLINT(runtime/explicit) */       \
+      : raw_bits_(immediate),        /* Allow implicit sign-extension. */ \
+        is_negative_(immediate < 0) {}                                    \
+  IntegerOperand(unsigned T immediate) /* NOLINT(runtime/explicit) */     \
+      : raw_bits_(immediate), is_negative_(false) {}
+  VIXL_INT_TYPES(VIXL_DECL_INT_OVERLOADS)
+#undef VIXL_DECL_INT_OVERLOADS
+#undef VIXL_INT_TYPES
+
+  // TODO: `Operand` can currently only hold an int64_t, so some large, unsigned
+  // values will be misrepresented here.
+  explicit IntegerOperand(const Operand& operand)
+      : raw_bits_(operand.GetEquivalentImmediate()),
+        is_negative_(operand.GetEquivalentImmediate() < 0) {}
+
+  bool IsIntN(unsigned n) const {
+    return is_negative_ ? vixl::IsIntN(n, RawbitsToInt64(raw_bits_))
+                        : vixl::IsIntN(n, raw_bits_);
+  }
+  bool IsUintN(unsigned n) const {
+    return !is_negative_ && vixl::IsUintN(n, raw_bits_);
+  }
+
+  bool IsUint8() const { return IsUintN(8); }
+  bool IsUint16() const { return IsUintN(16); }
+  bool IsUint32() const { return IsUintN(32); }
+  bool IsUint64() const { return IsUintN(64); }
+
+  bool IsInt8() const { return IsIntN(8); }
+  bool IsInt16() const { return IsIntN(16); }
+  bool IsInt32() const { return IsIntN(32); }
+  bool IsInt64() const { return IsIntN(64); }
+
+  bool FitsInBits(unsigned n) const {
+    return is_negative_ ? IsIntN(n) : IsUintN(n);
+  }
+  bool FitsInLane(const CPURegister& zd) const {
+    return FitsInBits(zd.GetLaneSizeInBits());
+  }
+  bool FitsInSignedLane(const CPURegister& zd) const {
+    return IsIntN(zd.GetLaneSizeInBits());
+  }
+  bool FitsInUnsignedLane(const CPURegister& zd) const {
+    return IsUintN(zd.GetLaneSizeInBits());
+  }
+
+  // Cast a value in the range [INT<n>_MIN, UINT<n>_MAX] to an unsigned integer
+  // in the range [0, UINT<n>_MAX] (using two's complement mapping).
+  uint64_t AsUintN(unsigned n) const {
+    VIXL_ASSERT(FitsInBits(n));
+    return raw_bits_ & GetUintMask(n);
+  }
+
+  uint8_t AsUint8() const { return static_cast<uint8_t>(AsUintN(8)); }
+  uint16_t AsUint16() const { return static_cast<uint16_t>(AsUintN(16)); }
+  uint32_t AsUint32() const { return static_cast<uint32_t>(AsUintN(32)); }
+  uint64_t AsUint64() const { return AsUintN(64); }
+
+  // Cast a value in the range [INT<n>_MIN, UINT<n>_MAX] to a signed integer in
+  // the range [INT<n>_MIN, INT<n>_MAX] (using two's complement mapping).
+  int64_t AsIntN(unsigned n) const {
+    VIXL_ASSERT(FitsInBits(n));
+    return ExtractSignedBitfield64(n - 1, 0, raw_bits_);
+  }
+
+  int8_t AsInt8() const { return static_cast<int8_t>(AsIntN(8)); }
+  int16_t AsInt16() const { return static_cast<int16_t>(AsIntN(16)); }
+  int32_t AsInt32() const { return static_cast<int32_t>(AsIntN(32)); }
+  int64_t AsInt64() const { return AsIntN(64); }
+
+  // Several instructions encode a signed int<N>_t, which is then (optionally)
+  // left-shifted and sign-extended to a Z register lane with a size which may
+  // be larger than N. This helper tries to find an int<N>_t such that the
+  // IntegerOperand's arithmetic value is reproduced in each lane.
+  //
+  // This is the mechanism that allows `Insr(z0.VnB(), 0xff)` to be treated as
+  // `Insr(z0.VnB(), -1)`.
+  template <unsigned N, unsigned kShift, typename T>
+  bool TryEncodeAsShiftedIntNForLane(const CPURegister& zd, T* imm) const {
+    VIXL_STATIC_ASSERT(std::numeric_limits<T>::digits > N);
+    VIXL_ASSERT(FitsInLane(zd));
+    if ((raw_bits_ & GetUintMask(kShift)) != 0) return false;
+
+    // Reverse the specified left-shift.
+    IntegerOperand unshifted(*this);
+    unshifted.ArithmeticShiftRight(kShift);
+
+    if (unshifted.IsIntN(N)) {
+      // This is trivial, since sign-extension produces the same arithmetic
+      // value irrespective of the destination size.
+      *imm = static_cast<T>(unshifted.AsIntN(N));
+      return true;
+    }
+
+    // Otherwise, we might be able to use the sign-extension to produce the
+    // desired bit pattern. We can only do this for values in the range
+    // [INT<N>_MAX + 1, UINT<N>_MAX], where the highest set bit is the sign bit.
+    //
+    // The lane size has to be adjusted to compensate for `kShift`, since the
+    // high bits will be dropped when the encoded value is left-shifted.
+    if (unshifted.IsUintN(zd.GetLaneSizeInBits() - kShift)) {
+      int64_t encoded = unshifted.AsIntN(zd.GetLaneSizeInBits() - kShift);
+      if (vixl::IsIntN(N, encoded)) {
+        *imm = static_cast<T>(encoded);
+        return true;
+      }
+    }
+    return false;
+  }
+
+  // As above, but `kShift` is written to the `*shift` parameter on success, so
+  // that it is easy to chain calls like this:
+  //
+  //     if (imm.TryEncodeAsShiftedIntNForLane<8, 0>(zd, &imm8, &shift) ||
+  //         imm.TryEncodeAsShiftedIntNForLane<8, 8>(zd, &imm8, &shift)) {
+  //       insn(zd, imm8, shift)
+  //     }
+  template <unsigned N, unsigned kShift, typename T, typename S>
+  bool TryEncodeAsShiftedIntNForLane(const CPURegister& zd,
+                                     T* imm,
+                                     S* shift) const {
+    if (TryEncodeAsShiftedIntNForLane<N, kShift>(zd, imm)) {
+      *shift = kShift;
+      return true;
+    }
+    return false;
+  }
+
+  // As above, but assume that `kShift` is 0.
+  template <unsigned N, typename T>
+  bool TryEncodeAsIntNForLane(const CPURegister& zd, T* imm) const {
+    return TryEncodeAsShiftedIntNForLane<N, 0>(zd, imm);
+  }
+
+  // As above, but for unsigned fields. This is usuaully a simple operation, but
+  // is provided for symmetry.
+  template <unsigned N, unsigned kShift, typename T>
+  bool TryEncodeAsShiftedUintNForLane(const CPURegister& zd, T* imm) const {
+    VIXL_STATIC_ASSERT(std::numeric_limits<T>::digits > N);
+    VIXL_ASSERT(FitsInLane(zd));
+
+    // TODO: Should we convert -1 to 0xff here?
+    if (is_negative_) return false;
+    USE(zd);
+
+    if ((raw_bits_ & GetUintMask(kShift)) != 0) return false;
+
+    if (vixl::IsUintN(N, raw_bits_ >> kShift)) {
+      *imm = static_cast<T>(raw_bits_ >> kShift);
+      return true;
+    }
+    return false;
+  }
+
+  template <unsigned N, unsigned kShift, typename T, typename S>
+  bool TryEncodeAsShiftedUintNForLane(const CPURegister& zd,
+                                      T* imm,
+                                      S* shift) const {
+    if (TryEncodeAsShiftedUintNForLane<N, kShift>(zd, imm)) {
+      *shift = kShift;
+      return true;
+    }
+    return false;
+  }
+
+  bool IsZero() const { return raw_bits_ == 0; }
+  bool IsNegative() const { return is_negative_; }
+  bool IsPositiveOrZero() const { return !is_negative_; }
+
+  uint64_t GetMagnitude() const {
+    return is_negative_ ? -raw_bits_ : raw_bits_;
+  }
+
+ private:
+  // Shift the arithmetic value right, with sign extension if is_negative_.
+  void ArithmeticShiftRight(int shift) {
+    VIXL_ASSERT((shift >= 0) && (shift < 64));
+    if (shift == 0) return;
+    if (is_negative_) {
+      raw_bits_ = ExtractSignedBitfield64(63, shift, raw_bits_);
+    } else {
+      raw_bits_ >>= shift;
+    }
+  }
+
+  uint64_t raw_bits_;
+  bool is_negative_;
+};
+
 // This an abstraction that can represent a register or memory location. The
 // `MacroAssembler` provides helpers to move data between generic operands.
 class GenericOperand {
diff --git a/src/aarch64/registers-aarch64.cc b/src/aarch64/registers-aarch64.cc
new file mode 100644
index 00000000..735f43c7
--- /dev/null
+++ b/src/aarch64/registers-aarch64.cc
@@ -0,0 +1,321 @@
+// Copyright 2019, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include <sstream>
+#include <string>
+
+#include "registers-aarch64.h"
+
+namespace vixl {
+namespace aarch64 {
+
+std::string CPURegister::GetArchitecturalName() const {
+  std::ostringstream name;
+  if (IsZRegister()) {
+    name << 'z' << GetCode();
+    if (HasLaneSize()) {
+      name << '.' << GetLaneSizeSymbol();
+    }
+  } else if (IsPRegister()) {
+    name << 'p' << GetCode();
+    if (HasLaneSize()) {
+      name << '.' << GetLaneSizeSymbol();
+    }
+    switch (qualifiers_) {
+      case kNoQualifiers:
+        break;
+      case kMerging:
+        name << "/m";
+        break;
+      case kZeroing:
+        name << "/z";
+        break;
+    }
+  } else {
+    VIXL_UNIMPLEMENTED();
+  }
+  return name.str();
+}
+
+unsigned CPURegister::GetMaxCodeFor(CPURegister::RegisterBank bank) {
+  switch (bank) {
+    case kNoRegisterBank:
+      return 0;
+    case kRRegisterBank:
+      return Register::GetMaxCode();
+    case kVRegisterBank:
+#ifdef VIXL_HAS_CONSTEXPR
+      VIXL_STATIC_ASSERT(VRegister::GetMaxCode() == ZRegister::GetMaxCode());
+#else
+      VIXL_ASSERT(VRegister::GetMaxCode() == ZRegister::GetMaxCode());
+#endif
+      return VRegister::GetMaxCode();
+    case kPRegisterBank:
+      return PRegister::GetMaxCode();
+  }
+  VIXL_UNREACHABLE();
+  return 0;
+}
+
+bool CPURegister::IsValidRegister() const {
+  return ((code_ < kNumberOfRegisters) || (code_ == kSPRegInternalCode)) &&
+         (bank_ == kRRegisterBank) &&
+         ((size_ == kEncodedWRegSize) || (size_ == kEncodedXRegSize)) &&
+         (qualifiers_ == kNoQualifiers) && (lane_size_ == size_);
+}
+
+bool CPURegister::IsValidVRegister() const {
+  VIXL_STATIC_ASSERT(kEncodedBRegSize < kEncodedQRegSize);
+  return (code_ < kNumberOfVRegisters) && (bank_ == kVRegisterBank) &&
+         ((size_ >= kEncodedBRegSize) && (size_ <= kEncodedQRegSize)) &&
+         (qualifiers_ == kNoQualifiers) &&
+         (lane_size_ != kEncodedUnknownSize) && (lane_size_ <= size_);
+}
+
+bool CPURegister::IsValidFPRegister() const {
+  return IsValidVRegister() && IsFPRegister();
+}
+
+bool CPURegister::IsValidZRegister() const {
+  VIXL_STATIC_ASSERT(kEncodedBRegSize < kEncodedQRegSize);
+  // Z registers are valid with or without a lane size, so we don't need to
+  // check lane_size_.
+  return (code_ < kNumberOfZRegisters) && (bank_ == kVRegisterBank) &&
+         (size_ == kEncodedUnknownSize) && (qualifiers_ == kNoQualifiers);
+}
+
+bool CPURegister::IsValidPRegister() const {
+  VIXL_STATIC_ASSERT(kEncodedBRegSize < kEncodedQRegSize);
+  // P registers are valid with or without a lane size, so we don't need to
+  // check lane_size_.
+  return (code_ < kNumberOfPRegisters) && (bank_ == kPRegisterBank) &&
+         (size_ == kEncodedUnknownSize) &&
+         ((qualifiers_ == kNoQualifiers) || (qualifiers_ == kMerging) ||
+          (qualifiers_ == kZeroing));
+}
+
+bool CPURegister::IsValid() const {
+  return IsValidRegister() || IsValidVRegister() || IsValidZRegister() ||
+         IsValidPRegister();
+}
+
+// Most coersions simply invoke the necessary constructor.
+#define VIXL_CPUREG_COERCION_LIST(U) \
+  U(Register, W, R)                  \
+  U(Register, X, R)                  \
+  U(VRegister, B, V)                 \
+  U(VRegister, H, V)                 \
+  U(VRegister, S, V)                 \
+  U(VRegister, D, V)                 \
+  U(VRegister, Q, V)                 \
+  U(VRegister, V, V)                 \
+  U(ZRegister, Z, V)                 \
+  U(PRegister, P, P)
+#define VIXL_DEFINE_CPUREG_COERCION(RET_TYPE, CTOR_TYPE, BANK) \
+  RET_TYPE CPURegister::CTOR_TYPE() const {                    \
+    VIXL_ASSERT(GetBank() == k##BANK##RegisterBank);           \
+    return CTOR_TYPE##Register(GetCode());                     \
+  }
+VIXL_CPUREG_COERCION_LIST(VIXL_DEFINE_CPUREG_COERCION)
+#undef VIXL_CPUREG_COERCION_LIST
+#undef VIXL_DEFINE_CPUREG_COERCION
+
+// NEON lane-format coersions always return VRegisters.
+#define VIXL_CPUREG_NEON_COERCION_LIST(V) \
+  V(8, B)                                 \
+  V(16, B)                                \
+  V(2, H)                                 \
+  V(4, H)                                 \
+  V(8, H)                                 \
+  V(2, S)                                 \
+  V(4, S)                                 \
+  V(1, D)                                 \
+  V(2, D)
+#define VIXL_DEFINE_CPUREG_NEON_COERCION(LANES, LANE_TYPE)             \
+  VRegister VRegister::V##LANES##LANE_TYPE() const {                   \
+    VIXL_ASSERT(IsVRegister());                                        \
+    return VRegister(GetCode(), LANES * k##LANE_TYPE##RegSize, LANES); \
+  }
+VIXL_CPUREG_NEON_COERCION_LIST(VIXL_DEFINE_CPUREG_NEON_COERCION)
+#undef VIXL_CPUREG_NEON_COERCION_LIST
+#undef VIXL_DEFINE_CPUREG_NEON_COERCION
+
+// Semantic type coersion for sdot and udot.
+// TODO: Use the qualifiers_ field to distinguish this from ::S().
+VRegister VRegister::S4B() const {
+  VIXL_ASSERT(IsVRegister());
+  return SRegister(GetCode());
+}
+
+bool AreAliased(const CPURegister& reg1,
+                const CPURegister& reg2,
+                const CPURegister& reg3,
+                const CPURegister& reg4,
+                const CPURegister& reg5,
+                const CPURegister& reg6,
+                const CPURegister& reg7,
+                const CPURegister& reg8) {
+  int number_of_valid_regs = 0;
+  int number_of_valid_vregs = 0;
+  int number_of_valid_pregs = 0;
+
+  RegList unique_regs = 0;
+  RegList unique_vregs = 0;
+  RegList unique_pregs = 0;
+
+  const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
+
+  for (size_t i = 0; i < ArrayLength(regs); i++) {
+    switch (regs[i].GetBank()) {
+      case CPURegister::kRRegisterBank:
+        number_of_valid_regs++;
+        unique_regs |= regs[i].GetBit();
+        break;
+      case CPURegister::kVRegisterBank:
+        number_of_valid_vregs++;
+        unique_vregs |= regs[i].GetBit();
+        break;
+      case CPURegister::kPRegisterBank:
+        number_of_valid_pregs++;
+        unique_pregs |= regs[i].GetBit();
+        break;
+      case CPURegister::kNoRegisterBank:
+        VIXL_ASSERT(regs[i].IsNone());
+        break;
+    }
+  }
+
+  int number_of_unique_regs = CountSetBits(unique_regs);
+  int number_of_unique_vregs = CountSetBits(unique_vregs);
+  int number_of_unique_pregs = CountSetBits(unique_pregs);
+
+  VIXL_ASSERT(number_of_valid_regs >= number_of_unique_regs);
+  VIXL_ASSERT(number_of_valid_vregs >= number_of_unique_vregs);
+  VIXL_ASSERT(number_of_valid_pregs >= number_of_unique_pregs);
+
+  return (number_of_valid_regs != number_of_unique_regs) ||
+         (number_of_valid_vregs != number_of_unique_vregs) ||
+         (number_of_valid_pregs != number_of_unique_pregs);
+}
+
+bool AreSameSizeAndType(const CPURegister& reg1,
+                        const CPURegister& reg2,
+                        const CPURegister& reg3,
+                        const CPURegister& reg4,
+                        const CPURegister& reg5,
+                        const CPURegister& reg6,
+                        const CPURegister& reg7,
+                        const CPURegister& reg8) {
+  VIXL_ASSERT(reg1.IsValid());
+  bool match = true;
+  match &= !reg2.IsValid() || reg2.IsSameSizeAndType(reg1);
+  match &= !reg3.IsValid() || reg3.IsSameSizeAndType(reg1);
+  match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
+  match &= !reg5.IsValid() || reg5.IsSameSizeAndType(reg1);
+  match &= !reg6.IsValid() || reg6.IsSameSizeAndType(reg1);
+  match &= !reg7.IsValid() || reg7.IsSameSizeAndType(reg1);
+  match &= !reg8.IsValid() || reg8.IsSameSizeAndType(reg1);
+  return match;
+}
+
+bool AreEven(const CPURegister& reg1,
+             const CPURegister& reg2,
+             const CPURegister& reg3,
+             const CPURegister& reg4,
+             const CPURegister& reg5,
+             const CPURegister& reg6,
+             const CPURegister& reg7,
+             const CPURegister& reg8) {
+  VIXL_ASSERT(reg1.IsValid());
+  bool even = (reg1.GetCode() % 2) == 0;
+  even &= !reg2.IsValid() || ((reg2.GetCode() % 2) == 0);
+  even &= !reg3.IsValid() || ((reg3.GetCode() % 2) == 0);
+  even &= !reg4.IsValid() || ((reg4.GetCode() % 2) == 0);
+  even &= !reg5.IsValid() || ((reg5.GetCode() % 2) == 0);
+  even &= !reg6.IsValid() || ((reg6.GetCode() % 2) == 0);
+  even &= !reg7.IsValid() || ((reg7.GetCode() % 2) == 0);
+  even &= !reg8.IsValid() || ((reg8.GetCode() % 2) == 0);
+  return even;
+}
+
+bool AreConsecutive(const CPURegister& reg1,
+                    const CPURegister& reg2,
+                    const CPURegister& reg3,
+                    const CPURegister& reg4) {
+  VIXL_ASSERT(reg1.IsValid());
+
+  if (!reg2.IsValid()) {
+    return true;
+  } else if (reg2.GetCode() !=
+             ((reg1.GetCode() + 1) % (reg1.GetMaxCode() + 1))) {
+    return false;
+  }
+
+  if (!reg3.IsValid()) {
+    return true;
+  } else if (reg3.GetCode() !=
+             ((reg2.GetCode() + 1) % (reg1.GetMaxCode() + 1))) {
+    return false;
+  }
+
+  if (!reg4.IsValid()) {
+    return true;
+  } else if (reg4.GetCode() !=
+             ((reg3.GetCode() + 1) % (reg1.GetMaxCode() + 1))) {
+    return false;
+  }
+
+  return true;
+}
+
+bool AreSameFormat(const CPURegister& reg1,
+                   const CPURegister& reg2,
+                   const CPURegister& reg3,
+                   const CPURegister& reg4) {
+  VIXL_ASSERT(reg1.IsValid());
+  bool match = true;
+  match &= !reg2.IsValid() || reg2.IsSameFormat(reg1);
+  match &= !reg3.IsValid() || reg3.IsSameFormat(reg1);
+  match &= !reg4.IsValid() || reg4.IsSameFormat(reg1);
+  return match;
+}
+
+bool AreSameLaneSize(const CPURegister& reg1,
+                     const CPURegister& reg2,
+                     const CPURegister& reg3,
+                     const CPURegister& reg4) {
+  VIXL_ASSERT(reg1.IsValid());
+  bool match = true;
+  match &=
+      !reg2.IsValid() || (reg2.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());
+  match &=
+      !reg3.IsValid() || (reg3.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());
+  match &=
+      !reg4.IsValid() || (reg4.GetLaneSizeInBits() == reg1.GetLaneSizeInBits());
+  return match;
+}
+}
+}  // namespace vixl::aarch64
diff --git a/src/aarch64/registers-aarch64.h b/src/aarch64/registers-aarch64.h
new file mode 100644
index 00000000..911974a8
--- /dev/null
+++ b/src/aarch64/registers-aarch64.h
@@ -0,0 +1,900 @@
+// Copyright 2019, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#ifndef VIXL_AARCH64_REGISTERS_AARCH64_H_
+#define VIXL_AARCH64_REGISTERS_AARCH64_H_
+
+#include <string>
+
+#include "instructions-aarch64.h"
+
+namespace vixl {
+namespace aarch64 {
+
+// An integer type capable of representing a homogeneous, non-overlapping set of
+// registers as a bitmask of their codes.
+typedef uint64_t RegList;
+static const int kRegListSizeInBits = sizeof(RegList) * 8;
+
+class Register;
+class WRegister;
+class XRegister;
+
+class VRegister;
+class BRegister;
+class HRegister;
+class SRegister;
+class DRegister;
+class QRegister;
+
+class ZRegister;
+
+class PRegister;
+class PRegisterWithLaneSize;
+class PRegisterM;
+class PRegisterZ;
+
+// A container for any single register supported by the processor. Selected
+// qualifications are also supported. Basic registers can be constructed
+// directly as CPURegister objects. Other variants should be constructed as one
+// of the derived classes.
+//
+// CPURegister aims to support any getter that would also be available to more
+// specialised register types. However, using the equivalent functions on the
+// specialised register types can avoid run-time checks, and should therefore be
+// preferred where run-time polymorphism isn't required.
+//
+// Type-specific modifers are typically implemented only on the derived classes.
+//
+// The encoding is such that CPURegister objects are cheap to pass by value.
+class CPURegister {
+ public:
+  enum RegisterBank : uint8_t {
+    kNoRegisterBank = 0,
+    kRRegisterBank,
+    kVRegisterBank,
+    kPRegisterBank
+  };
+  enum RegisterType {
+    kNoRegister,
+    kRegister,
+    kVRegister,
+    kZRegister,
+    kPRegister
+  };
+
+  static const unsigned kUnknownSize = 0;
+
+  VIXL_CONSTEXPR CPURegister()
+      : code_(0),
+        bank_(kNoRegisterBank),
+        size_(kEncodedUnknownSize),
+        qualifiers_(kNoQualifiers),
+        lane_size_(kEncodedUnknownSize) {}
+
+  CPURegister(int code, int size_in_bits, RegisterType type)
+      : code_(code),
+        bank_(GetBankFor(type)),
+        size_(EncodeSizeInBits(size_in_bits)),
+        qualifiers_(kNoQualifiers),
+        lane_size_(EncodeSizeInBits(size_in_bits)) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  // Basic accessors.
+
+  // TODO: Make this return 'int'.
+  unsigned GetCode() const { return code_; }
+
+  RegisterBank GetBank() const { return bank_; }
+
+  // For scalar registers, the lane size matches the register size, and is
+  // always known.
+  bool HasSize() const { return size_ != kEncodedUnknownSize; }
+  bool HasLaneSize() const { return lane_size_ != kEncodedUnknownSize; }
+
+  RegList GetBit() const {
+    if (IsNone()) return 0;
+    VIXL_ASSERT(code_ < kRegListSizeInBits);
+    return static_cast<RegList>(1) << code_;
+  }
+
+  // Return the architectural name for this register.
+  // TODO: This is temporary. Ultimately, we should move the
+  // Simulator::*RegNameForCode helpers out of the simulator, and provide an
+  // independent way to obtain the name of a register.
+  std::string GetArchitecturalName() const;
+
+  // Return the highest valid register code for this type, to allow generic
+  // loops to be written. This excludes kSPRegInternalCode, since it is not
+  // contiguous, and sp usually requires special handling anyway.
+  unsigned GetMaxCode() const { return GetMaxCodeFor(GetBank()); }
+
+  // Registers without a known size report kUnknownSize.
+  int GetSizeInBits() const { return DecodeSizeInBits(size_); }
+  int GetSizeInBytes() const { return DecodeSizeInBytes(size_); }
+  // TODO: Make these return 'int'.
+  unsigned GetLaneSizeInBits() const { return DecodeSizeInBits(lane_size_); }
+  unsigned GetLaneSizeInBytes() const { return DecodeSizeInBytes(lane_size_); }
+  unsigned GetLaneSizeInBytesLog2() const {
+    VIXL_ASSERT(HasLaneSize());
+    return DecodeSizeInBytesLog2(lane_size_);
+  }
+
+  int GetLanes() const {
+    if (HasSize() && HasLaneSize()) {
+      // Take advantage of the size encoding to calculate this efficiently.
+      VIXL_STATIC_ASSERT(kEncodedHRegSize == (kEncodedBRegSize + 1));
+      VIXL_STATIC_ASSERT(kEncodedSRegSize == (kEncodedHRegSize + 1));
+      VIXL_STATIC_ASSERT(kEncodedDRegSize == (kEncodedSRegSize + 1));
+      VIXL_STATIC_ASSERT(kEncodedQRegSize == (kEncodedDRegSize + 1));
+      int log2_delta = static_cast<int>(size_) - static_cast<int>(lane_size_);
+      VIXL_ASSERT(log2_delta >= 0);
+      return 1 << log2_delta;
+    }
+    return kUnknownSize;
+  }
+
+  bool Is8Bits() const { return size_ == kEncodedBRegSize; }
+  bool Is16Bits() const { return size_ == kEncodedHRegSize; }
+  bool Is32Bits() const { return size_ == kEncodedSRegSize; }
+  bool Is64Bits() const { return size_ == kEncodedDRegSize; }
+  bool Is128Bits() const { return size_ == kEncodedQRegSize; }
+
+  bool IsLaneSizeB() const { return lane_size_ == kEncodedBRegSize; }
+  bool IsLaneSizeH() const { return lane_size_ == kEncodedHRegSize; }
+  bool IsLaneSizeS() const { return lane_size_ == kEncodedSRegSize; }
+  bool IsLaneSizeD() const { return lane_size_ == kEncodedDRegSize; }
+  bool IsLaneSizeQ() const { return lane_size_ == kEncodedQRegSize; }
+
+  // If Is<Foo>Register(), then it is valid to convert the CPURegister to some
+  // <Foo>Register<Bar> type.
+  //
+  //  If...                              ... then it is safe to construct ...
+  //      r.IsRegister()                       -> Register(r)
+  //      r.IsVRegister()                      -> VRegister(r)
+  //      r.IsZRegister()                      -> ZRegister(r)
+  //      r.IsPRegister()                      -> PRegister(r)
+  //
+  //      r.IsPRegister() && HasLaneSize()     -> PRegisterWithLaneSize(r)
+  //      r.IsPRegister() && IsMerging()       -> PRegisterM(r)
+  //      r.IsPRegister() && IsZeroing()       -> PRegisterZ(r)
+  bool IsRegister() const { return GetType() == kRegister; }
+  bool IsVRegister() const { return GetType() == kVRegister; }
+  bool IsZRegister() const { return GetType() == kZRegister; }
+  bool IsPRegister() const { return GetType() == kPRegister; }
+
+  bool IsNone() const { return GetType() == kNoRegister; }
+
+  // `GetType() == kNoRegister` implies IsNone(), and vice-versa.
+  // `GetType() == k<Foo>Register` implies Is<Foo>Register(), and vice-versa.
+  RegisterType GetType() const {
+    switch (bank_) {
+      case kNoRegisterBank:
+        return kNoRegister;
+      case kRRegisterBank:
+        return kRegister;
+      case kVRegisterBank:
+        return HasSize() ? kVRegister : kZRegister;
+      case kPRegisterBank:
+        return kPRegister;
+    }
+    VIXL_UNREACHABLE();
+    return kNoRegister;
+  }
+
+  // IsFPRegister() is true for scalar FP types (and therefore implies
+  // IsVRegister()). There is no corresponding FPRegister type.
+  bool IsFPRegister() const { return Is1H() || Is1S() || Is1D(); }
+
+  // TODO: These are stricter forms of the helpers above. We should make the
+  // basic helpers strict, and remove these.
+  bool IsValidRegister() const;
+  bool IsValidVRegister() const;
+  bool IsValidFPRegister() const;
+  bool IsValidZRegister() const;
+  bool IsValidPRegister() const;
+
+  bool IsValid() const;
+  bool IsValidOrNone() const { return IsNone() || IsValid(); }
+
+  bool IsVector() const { return HasLaneSize() && (size_ != lane_size_); }
+  bool IsScalar() const { return HasLaneSize() && (size_ == lane_size_); }
+
+  bool IsSameType(const CPURegister& other) const {
+    return GetType() == other.GetType();
+  }
+
+  bool IsSameBank(const CPURegister& other) const {
+    return GetBank() == other.GetBank();
+  }
+
+  // Two registers with unknown size are considered to have the same size if
+  // they also have the same type. For example, all Z registers have the same
+  // size, even though we don't know what that is.
+  bool IsSameSizeAndType(const CPURegister& other) const {
+    return IsSameType(other) && (size_ == other.size_);
+  }
+
+  bool IsSameFormat(const CPURegister& other) const {
+    return IsSameSizeAndType(other) && (lane_size_ == other.lane_size_);
+  }
+
+  // Note that NoReg aliases itself, so that 'Is' implies 'Aliases'.
+  bool Aliases(const CPURegister& other) const {
+    return IsSameBank(other) && (code_ == other.code_);
+  }
+
+  bool Is(const CPURegister& other) const {
+    if (IsRegister() || IsVRegister()) {
+      // For core (W, X) and FP/NEON registers, we only consider the code, size
+      // and type. This is legacy behaviour.
+      // TODO: We should probably check every field for all registers.
+      return Aliases(other) && (size_ == other.size_);
+    } else {
+      // For Z and P registers, we require all fields to match exactly.
+      VIXL_ASSERT(IsNone() || IsZRegister() || IsPRegister());
+      return (code_ == other.code_) && (bank_ == other.bank_) &&
+             (size_ == other.size_) && (qualifiers_ == other.qualifiers_) &&
+             (lane_size_ == other.lane_size_);
+    }
+  }
+
+  // Conversions to specific register types. The result is a register that
+  // aliases the original CPURegister. That is, the original register bank
+  // (`GetBank()`) is checked and the code (`GetCode()`) preserved, but all
+  // other properties are ignored.
+  //
+  // Typical usage:
+  //
+  //     if (reg.GetBank() == kVRegisterBank) {
+  //       DRegister d = reg.D();
+  //       ...
+  //     }
+  //
+  // These could all return types with compile-time guarantees (like XRegister),
+  // but this breaks backwards-compatibility quite severely, particularly with
+  // code like `cond ? reg.W() : reg.X()`, which would have indeterminate type.
+
+  // Core registers, like "w0".
+  Register W() const;
+  Register X() const;
+  // FP/NEON registers, like "b0".
+  VRegister B() const;
+  VRegister H() const;
+  VRegister S() const;
+  VRegister D() const;
+  VRegister Q() const;
+  VRegister V() const;
+  // SVE registers, like "z0".
+  ZRegister Z() const;
+  PRegister P() const;
+
+  // Utilities for kRegister types.
+
+  bool IsZero() const { return IsRegister() && (code_ == kZeroRegCode); }
+  bool IsSP() const { return IsRegister() && (code_ == kSPRegInternalCode); }
+  bool IsW() const { return IsRegister() && Is32Bits(); }
+  bool IsX() const { return IsRegister() && Is64Bits(); }
+
+  // Utilities for FP/NEON kVRegister types.
+
+  // These helpers ensure that the size and type of the register are as
+  // described. They do not consider the number of lanes that make up a vector.
+  // So, for example, Is8B() implies IsD(), and Is1D() implies IsD, but IsD()
+  // does not imply Is1D() or Is8B().
+  // Check the number of lanes, ie. the format of the vector, using methods such
+  // as Is8B(), Is1D(), etc.
+  bool IsB() const { return IsVRegister() && Is8Bits(); }
+  bool IsH() const { return IsVRegister() && Is16Bits(); }
+  bool IsS() const { return IsVRegister() && Is32Bits(); }
+  bool IsD() const { return IsVRegister() && Is64Bits(); }
+  bool IsQ() const { return IsVRegister() && Is128Bits(); }
+
+  // As above, but also check that the register has exactly one lane. For
+  // example, reg.Is1D() implies DRegister(reg).IsValid(), but reg.IsD() does
+  // not.
+  bool Is1B() const { return IsB() && IsScalar(); }
+  bool Is1H() const { return IsH() && IsScalar(); }
+  bool Is1S() const { return IsS() && IsScalar(); }
+  bool Is1D() const { return IsD() && IsScalar(); }
+  bool Is1Q() const { return IsQ() && IsScalar(); }
+
+  // Check the specific NEON format.
+  bool Is8B() const { return IsD() && IsLaneSizeB(); }
+  bool Is16B() const { return IsQ() && IsLaneSizeB(); }
+  bool Is2H() const { return IsS() && IsLaneSizeH(); }
+  bool Is4H() const { return IsD() && IsLaneSizeH(); }
+  bool Is8H() const { return IsQ() && IsLaneSizeH(); }
+  bool Is2S() const { return IsD() && IsLaneSizeS(); }
+  bool Is4S() const { return IsQ() && IsLaneSizeS(); }
+  bool Is2D() const { return IsQ() && IsLaneSizeD(); }
+
+  // A semantic alias for sdot and udot (indexed and by element) instructions.
+  // The current CPURegister implementation cannot not tell this from Is1S(),
+  // but it might do later.
+  // TODO: Do this with the qualifiers_ field.
+  bool Is1S4B() const { return Is1S(); }
+
+  // Utilities for SVE registers.
+
+  bool IsUnqualified() const { return qualifiers_ == kNoQualifiers; }
+  bool IsMerging() const { return IsPRegister() && (qualifiers_ == kMerging); }
+  bool IsZeroing() const { return IsPRegister() && (qualifiers_ == kZeroing); }
+
+  // SVE types have unknown sizes, but within known bounds.
+
+  int GetMaxSizeInBytes() const {
+    switch (GetType()) {
+      case kZRegister:
+        return kZRegMaxSizeInBytes;
+      case kPRegister:
+        return kPRegMaxSizeInBytes;
+      default:
+        VIXL_ASSERT(HasSize());
+        return GetSizeInBits();
+    }
+  }
+
+  int GetMinSizeInBytes() const {
+    switch (GetType()) {
+      case kZRegister:
+        return kZRegMinSizeInBytes;
+      case kPRegister:
+        return kPRegMinSizeInBytes;
+      default:
+        VIXL_ASSERT(HasSize());
+        return GetSizeInBits();
+    }
+  }
+
+  int GetMaxSizeInBits() const { return GetMaxSizeInBytes() * kBitsPerByte; }
+  int GetMinSizeInBits() const { return GetMinSizeInBytes() * kBitsPerByte; }
+
+  static RegisterBank GetBankFor(RegisterType type) {
+    switch (type) {
+      case kNoRegister:
+        return kNoRegisterBank;
+      case kRegister:
+        return kRRegisterBank;
+      case kVRegister:
+      case kZRegister:
+        return kVRegisterBank;
+      case kPRegister:
+        return kPRegisterBank;
+    }
+    VIXL_UNREACHABLE();
+    return kNoRegisterBank;
+  }
+
+  static unsigned GetMaxCodeFor(CPURegister::RegisterType type) {
+    return GetMaxCodeFor(GetBankFor(type));
+  }
+
+ protected:
+  enum EncodedSize : uint8_t {
+    // Ensure that kUnknownSize (and therefore kNoRegister) is encoded as zero.
+    kEncodedUnknownSize = 0,
+
+    // The implementation assumes that the remaining sizes are encoded as
+    // `log2(size) + c`, so the following names must remain in sequence.
+    kEncodedBRegSize,
+    kEncodedHRegSize,
+    kEncodedSRegSize,
+    kEncodedDRegSize,
+    kEncodedQRegSize,
+
+    kEncodedWRegSize = kEncodedSRegSize,
+    kEncodedXRegSize = kEncodedDRegSize
+  };
+  VIXL_STATIC_ASSERT(kSRegSize == kWRegSize);
+  VIXL_STATIC_ASSERT(kDRegSize == kXRegSize);
+
+  char GetLaneSizeSymbol() const {
+    switch (lane_size_) {
+      case kEncodedBRegSize:
+        return 'B';
+      case kEncodedHRegSize:
+        return 'H';
+      case kEncodedSRegSize:
+        return 'S';
+      case kEncodedDRegSize:
+        return 'D';
+      case kEncodedQRegSize:
+        return 'Q';
+      case kEncodedUnknownSize:
+        break;
+    }
+    VIXL_UNREACHABLE();
+    return '?';
+  }
+
+  static EncodedSize EncodeSizeInBits(int size_in_bits) {
+    switch (size_in_bits) {
+      case kUnknownSize:
+        return kEncodedUnknownSize;
+      case kBRegSize:
+        return kEncodedBRegSize;
+      case kHRegSize:
+        return kEncodedHRegSize;
+      case kSRegSize:
+        return kEncodedSRegSize;
+      case kDRegSize:
+        return kEncodedDRegSize;
+      case kQRegSize:
+        return kEncodedQRegSize;
+    }
+    VIXL_UNREACHABLE();
+    return kEncodedUnknownSize;
+  }
+
+  static int DecodeSizeInBytesLog2(EncodedSize encoded_size) {
+    switch (encoded_size) {
+      case kEncodedUnknownSize:
+        // Log2 of B-sized lane in bytes is 0, so we can't just return 0 here.
+        VIXL_UNREACHABLE();
+        return -1;
+      case kEncodedBRegSize:
+        return kBRegSizeInBytesLog2;
+      case kEncodedHRegSize:
+        return kHRegSizeInBytesLog2;
+      case kEncodedSRegSize:
+        return kSRegSizeInBytesLog2;
+      case kEncodedDRegSize:
+        return kDRegSizeInBytesLog2;
+      case kEncodedQRegSize:
+        return kQRegSizeInBytesLog2;
+    }
+    VIXL_UNREACHABLE();
+    return kUnknownSize;
+  }
+
+  static int DecodeSizeInBytes(EncodedSize encoded_size) {
+    if (encoded_size == kEncodedUnknownSize) {
+      return kUnknownSize;
+    }
+    return 1 << DecodeSizeInBytesLog2(encoded_size);
+  }
+
+  static int DecodeSizeInBits(EncodedSize encoded_size) {
+    VIXL_STATIC_ASSERT(kUnknownSize == 0);
+    return DecodeSizeInBytes(encoded_size) * kBitsPerByte;
+  }
+
+  static unsigned GetMaxCodeFor(CPURegister::RegisterBank bank);
+
+  enum Qualifiers : uint8_t {
+    kNoQualifiers = 0,
+    // Used by P registers.
+    kMerging,
+    kZeroing
+  };
+
+  // An unchecked constructor, for use by derived classes.
+  CPURegister(int code,
+              EncodedSize size,
+              RegisterBank bank,
+              EncodedSize lane_size,
+              Qualifiers qualifiers = kNoQualifiers)
+      : code_(code),
+        bank_(bank),
+        size_(size),
+        qualifiers_(qualifiers),
+        lane_size_(lane_size) {}
+
+  // TODO: Check that access to these fields is reasonably efficient.
+  uint8_t code_;
+  RegisterBank bank_;
+  EncodedSize size_;
+  Qualifiers qualifiers_;
+  EncodedSize lane_size_;
+};
+// Ensure that CPURegisters can fit in a single (64-bit) register. This is a
+// proxy for being "cheap to pass by value", which is hard to check directly.
+VIXL_STATIC_ASSERT(sizeof(CPURegister) <= sizeof(uint64_t));
+
+// TODO: Add constexpr constructors.
+#define VIXL_DECLARE_REGISTER_COMMON(NAME, REGISTER_TYPE, PARENT_TYPE) \
+  VIXL_CONSTEXPR NAME() : PARENT_TYPE() {}                             \
+                                                                       \
+  explicit NAME(CPURegister other) : PARENT_TYPE(other) {              \
+    VIXL_ASSERT(IsValid());                                            \
+  }                                                                    \
+                                                                       \
+  VIXL_CONSTEXPR static unsigned GetMaxCode() {                        \
+    return kNumberOf##REGISTER_TYPE##s - 1;                            \
+  }
+
+// Any W or X register, including the zero register and the stack pointer.
+class Register : public CPURegister {
+ public:
+  VIXL_DECLARE_REGISTER_COMMON(Register, Register, CPURegister)
+
+  Register(int code, int size_in_bits)
+      : CPURegister(code, size_in_bits, kRegister) {
+    VIXL_ASSERT(IsValidRegister());
+  }
+
+  bool IsValid() const { return IsValidRegister(); }
+};
+
+// Any FP or NEON V register, including vector (V.<T>) and scalar forms
+// (B, H, S, D, Q).
+class VRegister : public CPURegister {
+ public:
+  VIXL_DECLARE_REGISTER_COMMON(VRegister, VRegister, CPURegister)
+
+  // For historical reasons, VRegister(0) returns v0.1Q (or equivalently, q0).
+  explicit VRegister(int code, int size_in_bits = kQRegSize, int lanes = 1)
+      : CPURegister(code,
+                    EncodeSizeInBits(size_in_bits),
+                    kVRegisterBank,
+                    EncodeLaneSizeInBits(size_in_bits, lanes)) {
+    VIXL_ASSERT(IsValidVRegister());
+  }
+
+  VRegister(int code, VectorFormat format)
+      : CPURegister(code,
+                    EncodeSizeInBits(RegisterSizeInBitsFromFormat(format)),
+                    kVRegisterBank,
+                    EncodeSizeInBits(LaneSizeInBitsFromFormat(format)),
+                    kNoQualifiers) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  VRegister V8B() const;
+  VRegister V16B() const;
+  VRegister V2H() const;
+  VRegister V4H() const;
+  VRegister V8H() const;
+  VRegister V2S() const;
+  VRegister V4S() const;
+  VRegister V1D() const;
+  VRegister V2D() const;
+  VRegister S4B() const;
+
+  bool IsValid() const { return IsValidVRegister(); }
+
+ protected:
+  static EncodedSize EncodeLaneSizeInBits(int size_in_bits, int lanes) {
+    VIXL_ASSERT(lanes >= 1);
+    VIXL_ASSERT((size_in_bits % lanes) == 0);
+    return EncodeSizeInBits(size_in_bits / lanes);
+  }
+};
+
+// Any SVE Z register, with or without a lane size specifier.
+class ZRegister : public CPURegister {
+ public:
+  VIXL_DECLARE_REGISTER_COMMON(ZRegister, ZRegister, CPURegister)
+
+  explicit ZRegister(int code, int lane_size_in_bits = kUnknownSize)
+      : CPURegister(code,
+                    kEncodedUnknownSize,
+                    kVRegisterBank,
+                    EncodeSizeInBits(lane_size_in_bits)) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  ZRegister(int code, VectorFormat format)
+      : CPURegister(code,
+                    kEncodedUnknownSize,
+                    kVRegisterBank,
+                    EncodeSizeInBits(LaneSizeInBitsFromFormat(format)),
+                    kNoQualifiers) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  // Return a Z register with a known lane size (like "z0.B").
+  ZRegister VnB() const { return ZRegister(GetCode(), kBRegSize); }
+  ZRegister VnH() const { return ZRegister(GetCode(), kHRegSize); }
+  ZRegister VnS() const { return ZRegister(GetCode(), kSRegSize); }
+  ZRegister VnD() const { return ZRegister(GetCode(), kDRegSize); }
+  ZRegister VnQ() const { return ZRegister(GetCode(), kQRegSize); }
+
+  template <typename T>
+  ZRegister WithLaneSize(T format) const {
+    return ZRegister(GetCode(), format);
+  }
+
+  ZRegister WithSameLaneSizeAs(const CPURegister& other) const {
+    VIXL_ASSERT(other.HasLaneSize());
+    return this->WithLaneSize(other.GetLaneSizeInBits());
+  }
+
+  bool IsValid() const { return IsValidZRegister(); }
+};
+
+// Any SVE P register, with or without a qualifier or lane size specifier.
+class PRegister : public CPURegister {
+ public:
+  VIXL_DECLARE_REGISTER_COMMON(PRegister, PRegister, CPURegister)
+
+  explicit PRegister(int code) : CPURegister(code, kUnknownSize, kPRegister) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  bool IsValid() const {
+    return IsValidPRegister() && !HasLaneSize() && IsUnqualified();
+  }
+
+  // Return a P register with a known lane size (like "p0.B").
+  PRegisterWithLaneSize VnB() const;
+  PRegisterWithLaneSize VnH() const;
+  PRegisterWithLaneSize VnS() const;
+  PRegisterWithLaneSize VnD() const;
+
+  template <typename T>
+  PRegisterWithLaneSize WithLaneSize(T format) const;
+
+  PRegisterWithLaneSize WithSameLaneSizeAs(const CPURegister& other) const;
+
+  // SVE predicates are specified (in normal assembly) with a "/z" (zeroing) or
+  // "/m" (merging) suffix. These methods are VIXL's equivalents.
+  PRegisterZ Zeroing() const;
+  PRegisterM Merging() const;
+
+ protected:
+  // Unchecked constructors, for use by derived classes.
+  PRegister(int code, EncodedSize encoded_lane_size)
+      : CPURegister(code,
+                    kEncodedUnknownSize,
+                    kPRegisterBank,
+                    encoded_lane_size,
+                    kNoQualifiers) {}
+
+  PRegister(int code, Qualifiers qualifiers)
+      : CPURegister(code,
+                    kEncodedUnknownSize,
+                    kPRegisterBank,
+                    kEncodedUnknownSize,
+                    qualifiers) {}
+};
+
+// Any SVE P register with a known lane size (like "p0.B").
+class PRegisterWithLaneSize : public PRegister {
+ public:
+  VIXL_DECLARE_REGISTER_COMMON(PRegisterWithLaneSize, PRegister, PRegister)
+
+  PRegisterWithLaneSize(int code, int lane_size_in_bits)
+      : PRegister(code, EncodeSizeInBits(lane_size_in_bits)) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  PRegisterWithLaneSize(int code, VectorFormat format)
+      : PRegister(code, EncodeSizeInBits(LaneSizeInBitsFromFormat(format))) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  bool IsValid() const {
+    return IsValidPRegister() && HasLaneSize() && IsUnqualified();
+  }
+
+  // Overload lane size accessors so we can assert `HasLaneSize()`. This allows
+  // tools such as clang-tidy to prove that the result of GetLaneSize* is
+  // non-zero.
+
+  // TODO: Make these return 'int'.
+  unsigned GetLaneSizeInBits() const {
+    VIXL_ASSERT(HasLaneSize());
+    return PRegister::GetLaneSizeInBits();
+  }
+
+  unsigned GetLaneSizeInBytes() const {
+    VIXL_ASSERT(HasLaneSize());
+    return PRegister::GetLaneSizeInBytes();
+  }
+};
+
+// Any SVE P register with the zeroing qualifier (like "p0/z").
+class PRegisterZ : public PRegister {
+ public:
+  VIXL_DECLARE_REGISTER_COMMON(PRegisterZ, PRegister, PRegister)
+
+  explicit PRegisterZ(int code) : PRegister(code, kZeroing) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  bool IsValid() const {
+    return IsValidPRegister() && !HasLaneSize() && IsZeroing();
+  }
+};
+
+// Any SVE P register with the merging qualifier (like "p0/m").
+class PRegisterM : public PRegister {
+ public:
+  VIXL_DECLARE_REGISTER_COMMON(PRegisterM, PRegister, PRegister)
+
+  explicit PRegisterM(int code) : PRegister(code, kMerging) {
+    VIXL_ASSERT(IsValid());
+  }
+
+  bool IsValid() const {
+    return IsValidPRegister() && !HasLaneSize() && IsMerging();
+  }
+};
+
+inline PRegisterWithLaneSize PRegister::VnB() const {
+  return PRegisterWithLaneSize(GetCode(), kBRegSize);
+}
+inline PRegisterWithLaneSize PRegister::VnH() const {
+  return PRegisterWithLaneSize(GetCode(), kHRegSize);
+}
+inline PRegisterWithLaneSize PRegister::VnS() const {
+  return PRegisterWithLaneSize(GetCode(), kSRegSize);
+}
+inline PRegisterWithLaneSize PRegister::VnD() const {
+  return PRegisterWithLaneSize(GetCode(), kDRegSize);
+}
+
+template <typename T>
+inline PRegisterWithLaneSize PRegister::WithLaneSize(T format) const {
+  return PRegisterWithLaneSize(GetCode(), format);
+}
+
+inline PRegisterWithLaneSize PRegister::WithSameLaneSizeAs(
+    const CPURegister& other) const {
+  VIXL_ASSERT(other.HasLaneSize());
+  return this->WithLaneSize(other.GetLaneSizeInBits());
+}
+
+inline PRegisterZ PRegister::Zeroing() const { return PRegisterZ(GetCode()); }
+inline PRegisterM PRegister::Merging() const { return PRegisterM(GetCode()); }
+
+#define VIXL_REGISTER_WITH_SIZE_LIST(V) \
+  V(WRegister, kWRegSize, Register)     \
+  V(XRegister, kXRegSize, Register)     \
+  V(QRegister, kQRegSize, VRegister)    \
+  V(DRegister, kDRegSize, VRegister)    \
+  V(SRegister, kSRegSize, VRegister)    \
+  V(HRegister, kHRegSize, VRegister)    \
+  V(BRegister, kBRegSize, VRegister)
+
+#define VIXL_DEFINE_REGISTER_WITH_SIZE(NAME, SIZE, PARENT)           \
+  class NAME : public PARENT {                                       \
+   public:                                                           \
+    VIXL_CONSTEXPR NAME() : PARENT() {}                              \
+    explicit NAME(int code) : PARENT(code, SIZE) {}                  \
+                                                                     \
+    explicit NAME(PARENT other) : PARENT(other) {                    \
+      VIXL_ASSERT(GetSizeInBits() == SIZE);                          \
+    }                                                                \
+                                                                     \
+    PARENT As##PARENT() const { return *this; }                      \
+                                                                     \
+    VIXL_CONSTEXPR int GetSizeInBits() const { return SIZE; }        \
+                                                                     \
+    bool IsValid() const {                                           \
+      return PARENT::IsValid() && (PARENT::GetSizeInBits() == SIZE); \
+    }                                                                \
+  };
+
+VIXL_REGISTER_WITH_SIZE_LIST(VIXL_DEFINE_REGISTER_WITH_SIZE)
+
+// No*Reg is used to provide default values for unused arguments, error cases
+// and so on. Note that these (and the default constructors) all compare equal
+// (using the Is() method).
+const Register NoReg;
+const VRegister NoVReg;
+const CPURegister NoCPUReg;
+const ZRegister NoZReg;
+
+// TODO: Ideally, these would use specialised register types (like XRegister and
+// so on). However, doing so throws up template overloading problems elsewhere.
+#define VIXL_DEFINE_REGISTERS(N)       \
+  const Register w##N = WRegister(N);  \
+  const Register x##N = XRegister(N);  \
+  const VRegister b##N = BRegister(N); \
+  const VRegister h##N = HRegister(N); \
+  const VRegister s##N = SRegister(N); \
+  const VRegister d##N = DRegister(N); \
+  const VRegister q##N = QRegister(N); \
+  const VRegister v##N(N);             \
+  const ZRegister z##N(N);
+AARCH64_REGISTER_CODE_LIST(VIXL_DEFINE_REGISTERS)
+#undef VIXL_DEFINE_REGISTERS
+
+#define VIXL_DEFINE_P_REGISTERS(N) const PRegister p##N(N);
+AARCH64_P_REGISTER_CODE_LIST(VIXL_DEFINE_P_REGISTERS)
+#undef VIXL_DEFINE_P_REGISTERS
+
+// VIXL represents 'sp' with a unique code, to tell it apart from 'xzr'.
+const Register wsp = WRegister(kSPRegInternalCode);
+const Register sp = XRegister(kSPRegInternalCode);
+
+// Standard aliases.
+const Register ip0 = x16;
+const Register ip1 = x17;
+const Register lr = x30;
+const Register xzr = x31;
+const Register wzr = w31;
+
+// AreAliased returns true if any of the named registers overlap. Arguments
+// set to NoReg are ignored. The system stack pointer may be specified.
+bool AreAliased(const CPURegister& reg1,
+                const CPURegister& reg2,
+                const CPURegister& reg3 = NoReg,
+                const CPURegister& reg4 = NoReg,
+                const CPURegister& reg5 = NoReg,
+                const CPURegister& reg6 = NoReg,
+                const CPURegister& reg7 = NoReg,
+                const CPURegister& reg8 = NoReg);
+
+// AreSameSizeAndType returns true if all of the specified registers have the
+// same size, and are of the same type. The system stack pointer may be
+// specified. Arguments set to NoReg are ignored, as are any subsequent
+// arguments. At least one argument (reg1) must be valid (not NoCPUReg).
+bool AreSameSizeAndType(const CPURegister& reg1,
+                        const CPURegister& reg2,
+                        const CPURegister& reg3 = NoCPUReg,
+                        const CPURegister& reg4 = NoCPUReg,
+                        const CPURegister& reg5 = NoCPUReg,
+                        const CPURegister& reg6 = NoCPUReg,
+                        const CPURegister& reg7 = NoCPUReg,
+                        const CPURegister& reg8 = NoCPUReg);
+
+// AreEven returns true if all of the specified registers have even register
+// indices. Arguments set to NoReg are ignored, as are any subsequent
+// arguments. At least one argument (reg1) must be valid (not NoCPUReg).
+bool AreEven(const CPURegister& reg1,
+             const CPURegister& reg2,
+             const CPURegister& reg3 = NoReg,
+             const CPURegister& reg4 = NoReg,
+             const CPURegister& reg5 = NoReg,
+             const CPURegister& reg6 = NoReg,
+             const CPURegister& reg7 = NoReg,
+             const CPURegister& reg8 = NoReg);
+
+// AreConsecutive returns true if all of the specified registers are
+// consecutive in the register file. Arguments set to NoReg are ignored, as are
+// any subsequent arguments. At least one argument (reg1) must be valid
+// (not NoCPUReg).
+bool AreConsecutive(const CPURegister& reg1,
+                    const CPURegister& reg2,
+                    const CPURegister& reg3 = NoCPUReg,
+                    const CPURegister& reg4 = NoCPUReg);
+
+// AreSameFormat returns true if all of the specified registers have the same
+// vector format. Arguments set to NoReg are ignored, as are any subsequent
+// arguments. At least one argument (reg1) must be valid (not NoVReg).
+bool AreSameFormat(const CPURegister& reg1,
+                   const CPURegister& reg2,
+                   const CPURegister& reg3 = NoCPUReg,
+                   const CPURegister& reg4 = NoCPUReg);
+
+// AreSameLaneSize returns true if all of the specified registers have the same
+// element lane size, B, H, S or D. It doesn't compare the type of registers.
+// Arguments set to NoReg are ignored, as are any subsequent arguments.
+// At least one argument (reg1) must be valid (not NoVReg).
+// TODO: Remove this, and replace its uses with AreSameFormat.
+bool AreSameLaneSize(const CPURegister& reg1,
+                     const CPURegister& reg2,
+                     const CPURegister& reg3 = NoCPUReg,
+                     const CPURegister& reg4 = NoCPUReg);
+}
+}  // namespace vixl::aarch64
+
+#endif  // VIXL_AARCH64_REGISTERS_AARCH64_H_
diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc
index 855a2971..cae59b21 100644
--- a/src/aarch64/simulator-aarch64.cc
+++ b/src/aarch64/simulator-aarch64.cc
@@ -26,6 +26,9 @@
 
 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
 
+#include <errno.h>
+#include <unistd.h>
+
 #include <cmath>
 #include <cstring>
 #include <limits>
@@ -64,13 +67,16 @@ SimSystemRegister SimSystemRegister::DefaultValueFor(SystemRegister id) {
 }
 
 
-Simulator::Simulator(Decoder* decoder, FILE* stream)
-    : cpu_features_auditor_(decoder, CPUFeatures::All()) {
+Simulator::Simulator(Decoder* decoder, FILE* stream, SimStack::Allocated stack)
+    : memory_(std::move(stack)),
+      movprfx_(NULL),
+      cpu_features_auditor_(decoder, CPUFeatures::All()) {
   // Ensure that shift operations act as the simulator expects.
   VIXL_ASSERT((static_cast<int32_t>(-1) >> 1) == -1);
   VIXL_ASSERT((static_cast<uint32_t>(-1) >> 1) == 0x7fffffff);
 
-  instruction_stats_ = false;
+  // Set up a placeholder pipe for CanReadMemory.
+  VIXL_CHECK(pipe(placeholder_pipe_fd_) == 0);
 
   // Set up the decoder.
   decoder_ = decoder;
@@ -91,21 +97,11 @@ Simulator::Simulator(Decoder* decoder, FILE* stream)
   SetColouredTrace(false);
   trace_parameters_ = LOG_NONE;
 
-  ResetState();
-
-  // Allocate and set up the simulator stack.
-  stack_ = new byte[stack_size_];
-  stack_limit_ = stack_ + stack_protection_size_;
-  // Configure the starting stack pointer.
-  //  - Find the top of the stack.
-  byte* tos = stack_ + stack_size_;
-  //  - There's a protection region at both ends of the stack.
-  tos -= stack_protection_size_;
-  //  - The stack pointer must be 16-byte aligned.
-  tos = AlignDown(tos, 16);
-  WriteSp(tos);
+  // We have to configure the SVE vector register length before calling
+  // ResetState().
+  SetVectorLengthInBits(kZRegMinSize);
 
-  instrumentation_ = NULL;
+  ResetState();
 
   // Print a warning about exclusive-access instructions, but only the first
   // time they are encountered. This warning can be silenced using
@@ -116,52 +112,112 @@ Simulator::Simulator(Decoder* decoder, FILE* stream)
 
   // Initialize the common state of RNDR and RNDRRS.
   uint16_t seed[3] = {11, 22, 33};
-  VIXL_STATIC_ASSERT(sizeof(seed) == sizeof(rndr_state_));
-  memcpy(rndr_state_, seed, sizeof(rndr_state_));
-}
+  VIXL_STATIC_ASSERT(sizeof(seed) == sizeof(rand_state_));
+  memcpy(rand_state_, seed, sizeof(rand_state_));
 
+  // Initialize all bits of pseudo predicate register to true.
+  LogicPRegister ones(pregister_all_true_);
+  ones.SetAllBits();
+}
 
-void Simulator::ResetState() {
+void Simulator::ResetSystemRegisters() {
   // Reset the system registers.
   nzcv_ = SimSystemRegister::DefaultValueFor(NZCV);
   fpcr_ = SimSystemRegister::DefaultValueFor(FPCR);
+  ResetFFR();
+}
 
-  // Reset registers to 0.
-  pc_ = NULL;
-  pc_modified_ = false;
+void Simulator::ResetRegisters() {
   for (unsigned i = 0; i < kNumberOfRegisters; i++) {
     WriteXRegister(i, 0xbadbeef);
   }
-  // Set FP registers to a value that is a NaN in both 32-bit and 64-bit FP.
-  uint64_t nan_bits[] = {
-      UINT64_C(0x7ff00cab7f8ba9e1), UINT64_C(0x7ff0dead7f8beef1),
-  };
-  VIXL_ASSERT(IsSignallingNaN(RawbitsToDouble(nan_bits[0] & kDRegMask)));
-  VIXL_ASSERT(IsSignallingNaN(RawbitsToFloat(nan_bits[0] & kSRegMask)));
+  // Returning to address 0 exits the Simulator.
+  WriteLr(kEndOfSimAddress);
+}
 
-  qreg_t q_bits;
-  VIXL_ASSERT(sizeof(q_bits) == sizeof(nan_bits));
-  memcpy(&q_bits, nan_bits, sizeof(nan_bits));
+void Simulator::ResetVRegisters() {
+  // Set SVE/FP registers to a value that is a NaN in both 32-bit and 64-bit FP.
+  VIXL_ASSERT((GetVectorLengthInBytes() % kDRegSizeInBytes) == 0);
+  int lane_count = GetVectorLengthInBytes() / kDRegSizeInBytes;
+  for (unsigned i = 0; i < kNumberOfZRegisters; i++) {
+    VIXL_ASSERT(vregisters_[i].GetSizeInBytes() == GetVectorLengthInBytes());
+    vregisters_[i].NotifyAccessAsZ();
+    for (int lane = 0; lane < lane_count; lane++) {
+      // Encode the register number and (D-sized) lane into each NaN, to
+      // make them easier to trace.
+      uint64_t nan_bits = 0x7ff0f0007f80f000 | (0x0000000100000000 * i) |
+                          (0x0000000000000001 * lane);
+      VIXL_ASSERT(IsSignallingNaN(RawbitsToDouble(nan_bits & kDRegMask)));
+      VIXL_ASSERT(IsSignallingNaN(RawbitsToFloat(nan_bits & kSRegMask)));
+      vregisters_[i].Insert(lane, nan_bits);
+    }
+  }
+}
 
-  for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
-    WriteQRegister(i, q_bits);
+void Simulator::ResetPRegisters() {
+  VIXL_ASSERT((GetPredicateLengthInBytes() % kHRegSizeInBytes) == 0);
+  int lane_count = GetPredicateLengthInBytes() / kHRegSizeInBytes;
+  // Ensure the register configuration fits in this bit encoding.
+  VIXL_STATIC_ASSERT(kNumberOfPRegisters <= UINT8_MAX);
+  VIXL_ASSERT(lane_count <= UINT8_MAX);
+  for (unsigned i = 0; i < kNumberOfPRegisters; i++) {
+    VIXL_ASSERT(pregisters_[i].GetSizeInBytes() == GetPredicateLengthInBytes());
+    for (int lane = 0; lane < lane_count; lane++) {
+      // Encode the register number and (H-sized) lane into each lane slot.
+      uint16_t bits = (0x0100 * lane) | i;
+      pregisters_[i].Insert(lane, bits);
+    }
   }
-  // Returning to address 0 exits the Simulator.
-  WriteLr(kEndOfSimAddress);
+}
+
+void Simulator::ResetFFR() {
+  VIXL_ASSERT((GetPredicateLengthInBytes() % kHRegSizeInBytes) == 0);
+  int default_active_lanes = GetPredicateLengthInBytes() / kHRegSizeInBytes;
+  ffr_register_.Write(static_cast<uint16_t>(GetUintMask(default_active_lanes)));
+}
 
+void Simulator::ResetState() {
+  ResetSystemRegisters();
+  ResetRegisters();
+  ResetVRegisters();
+  ResetPRegisters();
+
+  WriteSp(memory_.GetStack().GetBase());
+
+  pc_ = NULL;
+  pc_modified_ = false;
+
+  // BTI state.
   btype_ = DefaultBType;
   next_btype_ = DefaultBType;
 }
 
+void Simulator::SetVectorLengthInBits(unsigned vector_length) {
+  VIXL_ASSERT((vector_length >= kZRegMinSize) &&
+              (vector_length <= kZRegMaxSize));
+  VIXL_ASSERT((vector_length % kZRegMinSize) == 0);
+  vector_length_ = vector_length;
+
+  for (unsigned i = 0; i < kNumberOfZRegisters; i++) {
+    vregisters_[i].SetSizeInBytes(GetVectorLengthInBytes());
+  }
+  for (unsigned i = 0; i < kNumberOfPRegisters; i++) {
+    pregisters_[i].SetSizeInBytes(GetPredicateLengthInBytes());
+  }
+
+  ffr_register_.SetSizeInBytes(GetPredicateLengthInBytes());
+
+  ResetVRegisters();
+  ResetPRegisters();
+  ResetFFR();
+}
 
 Simulator::~Simulator() {
-  delete[] stack_;
   // The decoder may outlive the simulator.
   decoder_->RemoveVisitor(print_disasm_);
   delete print_disasm_;
-
-  decoder_->RemoveVisitor(instrumentation_);
-  delete instrumentation_;
+  close(placeholder_pipe_fd_[0]);
+  close(placeholder_pipe_fd_[1]);
 }
 
 
@@ -182,6 +238,7 @@ void Simulator::RunFrom(const Instruction* first) {
 }
 
 
+// clang-format off
 const char* Simulator::xreg_names[] = {"x0",  "x1",  "x2",  "x3",  "x4",  "x5",
                                        "x6",  "x7",  "x8",  "x9",  "x10", "x11",
                                        "x12", "x13", "x14", "x15", "x16", "x17",
@@ -196,6 +253,13 @@ const char* Simulator::wreg_names[] = {"w0",  "w1",  "w2",  "w3",  "w4",  "w5",
                                        "w24", "w25", "w26", "w27", "w28", "w29",
                                        "w30", "wzr", "wsp"};
 
+const char* Simulator::breg_names[] = {"b0",  "b1",  "b2",  "b3",  "b4",  "b5",
+                                       "b6",  "b7",  "b8",  "b9",  "b10", "b11",
+                                       "b12", "b13", "b14", "b15", "b16", "b17",
+                                       "b18", "b19", "b20", "b21", "b22", "b23",
+                                       "b24", "b25", "b26", "b27", "b28", "b29",
+                                       "b30", "b31"};
+
 const char* Simulator::hreg_names[] = {"h0",  "h1",  "h2",  "h3",  "h4",  "h5",
                                        "h6",  "h7",  "h8",  "h9",  "h10", "h11",
                                        "h12", "h13", "h14", "h15", "h16", "h17",
@@ -224,27 +288,47 @@ const char* Simulator::vreg_names[] = {"v0",  "v1",  "v2",  "v3",  "v4",  "v5",
                                        "v24", "v25", "v26", "v27", "v28", "v29",
                                        "v30", "v31"};
 
+const char* Simulator::zreg_names[] = {"z0",  "z1",  "z2",  "z3",  "z4",  "z5",
+                                       "z6",  "z7",  "z8",  "z9",  "z10", "z11",
+                                       "z12", "z13", "z14", "z15", "z16", "z17",
+                                       "z18", "z19", "z20", "z21", "z22", "z23",
+                                       "z24", "z25", "z26", "z27", "z28", "z29",
+                                       "z30", "z31"};
+
+const char* Simulator::preg_names[] = {"p0",  "p1",  "p2",  "p3",  "p4",  "p5",
+                                       "p6",  "p7",  "p8",  "p9",  "p10", "p11",
+                                       "p12", "p13", "p14", "p15"};
+// clang-format on
+
 
 const char* Simulator::WRegNameForCode(unsigned code, Reg31Mode mode) {
-  VIXL_ASSERT(code < kNumberOfRegisters);
   // If the code represents the stack pointer, index the name after zr.
-  if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
+  if ((code == kSPRegInternalCode) ||
+      ((code == kZeroRegCode) && (mode == Reg31IsStackPointer))) {
     code = kZeroRegCode + 1;
   }
+  VIXL_ASSERT(code < ArrayLength(wreg_names));
   return wreg_names[code];
 }
 
 
 const char* Simulator::XRegNameForCode(unsigned code, Reg31Mode mode) {
-  VIXL_ASSERT(code < kNumberOfRegisters);
   // If the code represents the stack pointer, index the name after zr.
-  if ((code == kZeroRegCode) && (mode == Reg31IsStackPointer)) {
+  if ((code == kSPRegInternalCode) ||
+      ((code == kZeroRegCode) && (mode == Reg31IsStackPointer))) {
     code = kZeroRegCode + 1;
   }
+  VIXL_ASSERT(code < ArrayLength(xreg_names));
   return xreg_names[code];
 }
 
 
+const char* Simulator::BRegNameForCode(unsigned code) {
+  VIXL_ASSERT(code < kNumberOfVRegisters);
+  return breg_names[code];
+}
+
+
 const char* Simulator::HRegNameForCode(unsigned code) {
   VIXL_ASSERT(code < kNumberOfVRegisters);
   return hreg_names[code];
@@ -269,6 +353,39 @@ const char* Simulator::VRegNameForCode(unsigned code) {
 }
 
 
+const char* Simulator::ZRegNameForCode(unsigned code) {
+  VIXL_ASSERT(code < kNumberOfZRegisters);
+  return zreg_names[code];
+}
+
+
+const char* Simulator::PRegNameForCode(unsigned code) {
+  VIXL_ASSERT(code < kNumberOfPRegisters);
+  return preg_names[code];
+}
+
+SimVRegister Simulator::ExpandToSimVRegister(const SimPRegister& pg) {
+  SimVRegister ones, result;
+  dup_immediate(kFormatVnB, ones, 0xff);
+  mov_zeroing(kFormatVnB, result, pg, ones);
+  return result;
+}
+
+void Simulator::ExtractFromSimVRegister(VectorFormat vform,
+                                        SimPRegister& pd,
+                                        SimVRegister vreg) {
+  SimVRegister zero;
+  dup_immediate(kFormatVnB, zero, 0);
+  SVEIntCompareVectorsHelper(ne,
+                             vform,
+                             pd,
+                             GetPTrue(),
+                             vreg,
+                             zero,
+                             false,
+                             LeaveFlags);
+}
+
 #define COLOUR(colour_code) "\033[0;" colour_code "m"
 #define COLOUR_BOLD(colour_code) "\033[1;" colour_code "m"
 #define COLOUR_HIGHLIGHT "\033[43m"
@@ -291,6 +408,8 @@ void Simulator::SetColouredTrace(bool value) {
   clr_reg_value = value ? COLOUR(CYAN) : "";
   clr_vreg_name = value ? COLOUR_BOLD(MAGENTA) : "";
   clr_vreg_value = value ? COLOUR(MAGENTA) : "";
+  clr_preg_name = value ? COLOUR_BOLD(GREEN) : "";
+  clr_preg_value = value ? COLOUR(GREEN) : "";
   clr_memory_address = value ? COLOUR_BOLD(BLUE) : "";
   clr_warning = value ? COLOUR_BOLD(YELLOW) : "";
   clr_warning_message = value ? COLOUR(YELLOW) : "";
@@ -322,22 +441,6 @@ void Simulator::SetTraceParameters(int parameters) {
 }
 
 
-void Simulator::SetInstructionStats(bool value) {
-  if (value != instruction_stats_) {
-    if (value) {
-      if (instrumentation_ == NULL) {
-        // Set the sample period to 10, as the VIXL examples and tests are
-        // short.
-        instrumentation_ = new Instrument("vixl_stats.csv", 10);
-      }
-      decoder_->AppendVisitor(instrumentation_);
-    } else if (instrumentation_ != NULL) {
-      decoder_->RemoveVisitor(instrumentation_);
-    }
-    instruction_stats_ = value;
-  }
-}
-
 // Helpers ---------------------------------------------------------------------
 uint64_t Simulator::AddWithCarry(unsigned reg_size,
                                  bool set_flags,
@@ -379,44 +482,50 @@ uint64_t Simulator::AddWithCarry(unsigned reg_size,
 
 
 int64_t Simulator::ShiftOperand(unsigned reg_size,
-                                int64_t value,
+                                uint64_t uvalue,
                                 Shift shift_type,
                                 unsigned amount) const {
-  VIXL_ASSERT((reg_size == kWRegSize) || (reg_size == kXRegSize));
-  if (amount == 0) {
-    return value;
-  }
-  uint64_t uvalue = static_cast<uint64_t>(value);
-  uint64_t mask = kWRegMask;
-  bool is_negative = (uvalue & kWSignMask) != 0;
-  if (reg_size == kXRegSize) {
-    mask = kXRegMask;
-    is_negative = (uvalue & kXSignMask) != 0;
-  }
-
-  switch (shift_type) {
-    case LSL:
-      uvalue <<= amount;
-      break;
-    case LSR:
-      uvalue >>= amount;
-      break;
-    case ASR:
-      uvalue >>= amount;
-      if (is_negative) {
-        // Simulate sign-extension to 64 bits.
-        uvalue |= ~UINT64_C(0) << (reg_size - amount);
+  VIXL_ASSERT((reg_size == kBRegSize) || (reg_size == kHRegSize) ||
+              (reg_size == kSRegSize) || (reg_size == kDRegSize));
+  if (amount > 0) {
+    uint64_t mask = GetUintMask(reg_size);
+    bool is_negative = (uvalue & GetSignMask(reg_size)) != 0;
+    // The behavior is undefined in c++ if the shift amount greater than or
+    // equal to the register lane size. Work out the shifted result based on
+    // architectural behavior before performing the c++ type shfit operations.
+    switch (shift_type) {
+      case LSL:
+        if (amount >= reg_size) {
+          return UINT64_C(0);
+        }
+        uvalue <<= amount;
+        break;
+      case LSR:
+        if (amount >= reg_size) {
+          return UINT64_C(0);
+        }
+        uvalue >>= amount;
+        break;
+      case ASR:
+        if (amount >= reg_size) {
+          return is_negative ? ~UINT64_C(0) : UINT64_C(0);
+        }
+        uvalue >>= amount;
+        if (is_negative) {
+          // Simulate sign-extension to 64 bits.
+          uvalue |= ~UINT64_C(0) << (reg_size - amount);
+        }
+        break;
+      case ROR: {
+        uvalue = RotateRight(uvalue, amount, reg_size);
+        break;
       }
-      break;
-    case ROR: {
-      uvalue = RotateRight(uvalue, amount, reg_size);
-      break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        return 0;
     }
-    default:
-      VIXL_UNIMPLEMENTED();
-      return 0;
+    uvalue &= mask;
   }
-  uvalue &= mask;
 
   int64_t result;
   memcpy(&result, &uvalue, sizeof(result));
@@ -592,6 +701,15 @@ Simulator::PrintRegisterFormat Simulator::GetPrintRegisterFormat(
       return kPrintReg1S;
     case kFormatD:
       return kPrintReg1D;
+
+    case kFormatVnB:
+      return kPrintRegVnB;
+    case kFormatVnH:
+      return kPrintRegVnH;
+    case kFormatVnS:
+      return kPrintRegVnS;
+    case kFormatVnD:
+      return kPrintRegVnD;
   }
 }
 
@@ -623,301 +741,445 @@ Simulator::PrintRegisterFormat Simulator::GetPrintRegisterFormatFP(
   }
 }
 
-
-void Simulator::PrintWrittenRegisters() {
+void Simulator::PrintRegisters() {
   for (unsigned i = 0; i < kNumberOfRegisters; i++) {
-    if (registers_[i].WrittenSinceLastLog()) PrintRegister(i);
+    if (i == kSpRegCode) i = kSPRegInternalCode;
+    PrintRegister(i);
   }
 }
 
-
-void Simulator::PrintWrittenVRegisters() {
+void Simulator::PrintVRegisters() {
   for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
-    // At this point there is no type information, so print as a raw 1Q.
-    if (vregisters_[i].WrittenSinceLastLog()) PrintVRegister(i, kPrintReg1Q);
+    PrintVRegister(i);
   }
 }
 
-
-void Simulator::PrintSystemRegisters() {
-  PrintSystemRegister(NZCV);
-  PrintSystemRegister(FPCR);
+void Simulator::PrintZRegisters() {
+  for (unsigned i = 0; i < kNumberOfZRegisters; i++) {
+    PrintZRegister(i);
+  }
 }
 
-
-void Simulator::PrintRegisters() {
+void Simulator::PrintWrittenRegisters() {
   for (unsigned i = 0; i < kNumberOfRegisters; i++) {
-    PrintRegister(i);
+    if (registers_[i].WrittenSinceLastLog()) {
+      if (i == kSpRegCode) i = kSPRegInternalCode;
+      PrintRegister(i);
+    }
   }
 }
 
-
-void Simulator::PrintVRegisters() {
+void Simulator::PrintWrittenVRegisters() {
+  bool has_sve = GetCPUFeatures()->Has(CPUFeatures::kSVE);
   for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
-    // At this point there is no type information, so print as a raw 1Q.
-    PrintVRegister(i, kPrintReg1Q);
+    if (vregisters_[i].WrittenSinceLastLog()) {
+      // Z registers are initialised in the constructor before the user can
+      // configure the CPU features, so we must also check for SVE here.
+      if (vregisters_[i].AccessedAsZSinceLastLog() && has_sve) {
+        PrintZRegister(i);
+      } else {
+        PrintVRegister(i);
+      }
+    }
   }
 }
 
-
-// Print a register's name and raw value.
-//
-// Only the least-significant `size_in_bytes` bytes of the register are printed,
-// but the value is aligned as if the whole register had been printed.
-//
-// For typical register updates, size_in_bytes should be set to kXRegSizeInBytes
-// -- the default -- so that the whole register is printed. Other values of
-// size_in_bytes are intended for use when the register hasn't actually been
-// updated (such as in PrintWrite).
-//
-// No newline is printed. This allows the caller to print more details (such as
-// a memory access annotation).
-void Simulator::PrintRegisterRawHelper(unsigned code,
-                                       Reg31Mode r31mode,
-                                       int size_in_bytes) {
-  // The template for all supported sizes.
-  //   "# x{code}: 0xffeeddccbbaa9988"
-  //   "# w{code}:         0xbbaa9988"
-  //   "# w{code}<15:0>:       0x9988"
-  //   "# w{code}<7:0>:          0x88"
-  unsigned padding_chars = (kXRegSizeInBytes - size_in_bytes) * 2;
-
-  const char* name = "";
-  const char* suffix = "";
-  switch (size_in_bytes) {
-    case kXRegSizeInBytes:
-      name = XRegNameForCode(code, r31mode);
-      break;
-    case kWRegSizeInBytes:
-      name = WRegNameForCode(code, r31mode);
-      break;
-    case 2:
-      name = WRegNameForCode(code, r31mode);
-      suffix = "<15:0>";
-      padding_chars -= strlen(suffix);
-      break;
-    case 1:
-      name = WRegNameForCode(code, r31mode);
-      suffix = "<7:0>";
-      padding_chars -= strlen(suffix);
-      break;
-    default:
-      VIXL_UNREACHABLE();
-  }
-  fprintf(stream_, "# %s%5s%s: ", clr_reg_name, name, suffix);
-
-  // Print leading padding spaces.
-  VIXL_ASSERT(padding_chars < (kXRegSizeInBytes * 2));
-  for (unsigned i = 0; i < padding_chars; i++) {
-    putc(' ', stream_);
+void Simulator::PrintWrittenPRegisters() {
+  // P registers are initialised in the constructor before the user can
+  // configure the CPU features, so we must check for SVE here.
+  if (!GetCPUFeatures()->Has(CPUFeatures::kSVE)) return;
+  for (unsigned i = 0; i < kNumberOfPRegisters; i++) {
+    if (pregisters_[i].WrittenSinceLastLog()) {
+      PrintPRegister(i);
+    }
   }
-
-  // Print the specified bits in hexadecimal format.
-  uint64_t bits = ReadRegister<uint64_t>(code, r31mode);
-  bits &= kXRegMask >> ((kXRegSizeInBytes - size_in_bytes) * 8);
-  VIXL_STATIC_ASSERT(sizeof(bits) == kXRegSizeInBytes);
-
-  int chars = size_in_bytes * 2;
-  fprintf(stream_,
-          "%s0x%0*" PRIx64 "%s",
-          clr_reg_value,
-          chars,
-          bits,
-          clr_normal);
+  if (ReadFFR().WrittenSinceLastLog()) PrintFFR();
 }
 
-
-void Simulator::PrintRegister(unsigned code, Reg31Mode r31mode) {
-  registers_[code].NotifyRegisterLogged();
-
-  // Don't print writes into xzr.
-  if ((code == kZeroRegCode) && (r31mode == Reg31IsZeroRegister)) {
-    return;
-  }
-
-  // The template for all x and w registers:
-  //   "# x{code}: 0x{value}"
-  //   "# w{code}: 0x{value}"
-
-  PrintRegisterRawHelper(code, r31mode);
-  fprintf(stream_, "\n");
+void Simulator::PrintSystemRegisters() {
+  PrintSystemRegister(NZCV);
+  PrintSystemRegister(FPCR);
 }
 
-
-// Print a register's name and raw value.
-//
-// The `bytes` and `lsb` arguments can be used to limit the bytes that are
-// printed. These arguments are intended for use in cases where register hasn't
-// actually been updated (such as in PrintVWrite).
-//
-// No newline is printed. This allows the caller to print more details (such as
-// a floating-point interpretation or a memory access annotation).
-void Simulator::PrintVRegisterRawHelper(unsigned code, int bytes, int lsb) {
-  // The template for vector types:
-  //   "# v{code}: 0xffeeddccbbaa99887766554433221100".
-  // An example with bytes=4 and lsb=8:
-  //   "# v{code}:         0xbbaa9988                ".
-  fprintf(stream_,
-          "# %s%5s: %s",
-          clr_vreg_name,
-          VRegNameForCode(code),
-          clr_vreg_value);
-
-  int msb = lsb + bytes - 1;
-  int byte = kQRegSizeInBytes - 1;
-
-  // Print leading padding spaces. (Two spaces per byte.)
-  while (byte > msb) {
+void Simulator::PrintRegisterValue(const uint8_t* value,
+                                   int value_size,
+                                   PrintRegisterFormat format) {
+  int print_width = GetPrintRegSizeInBytes(format);
+  VIXL_ASSERT(print_width <= value_size);
+  for (int i = value_size - 1; i >= print_width; i--) {
+    // Pad with spaces so that values align vertically.
     fprintf(stream_, "  ");
-    byte--;
+    // If we aren't explicitly printing a partial value, ensure that the
+    // unprinted bits are zero.
+    VIXL_ASSERT(((format & kPrintRegPartial) != 0) || (value[i] == 0));
   }
-
-  // Print the specified part of the value, byte by byte.
-  qreg_t rawbits = ReadQRegister(code);
   fprintf(stream_, "0x");
-  while (byte >= lsb) {
-    fprintf(stream_, "%02x", rawbits.val[byte]);
-    byte--;
+  for (int i = print_width - 1; i >= 0; i--) {
+    fprintf(stream_, "%02x", value[i]);
   }
+}
 
-  // Print trailing padding spaces.
-  while (byte >= 0) {
-    fprintf(stream_, "  ");
-    byte--;
+void Simulator::PrintRegisterValueFPAnnotations(const uint8_t* value,
+                                                uint16_t lane_mask,
+                                                PrintRegisterFormat format) {
+  VIXL_ASSERT((format & kPrintRegAsFP) != 0);
+  int lane_size = GetPrintRegLaneSizeInBytes(format);
+  fprintf(stream_, " (");
+  bool last_inactive = false;
+  const char* sep = "";
+  for (int i = GetPrintRegLaneCount(format) - 1; i >= 0; i--, sep = ", ") {
+    bool access = (lane_mask & (1 << (i * lane_size))) != 0;
+    if (access) {
+      // Read the lane as a double, so we can format all FP types in the same
+      // way. We squash NaNs, and a double can exactly represent any other value
+      // that the smaller types can represent, so this is lossless.
+      double element;
+      switch (lane_size) {
+        case kHRegSizeInBytes: {
+          Float16 element_fp16;
+          VIXL_STATIC_ASSERT(sizeof(element_fp16) == kHRegSizeInBytes);
+          memcpy(&element_fp16, &value[i * lane_size], sizeof(element_fp16));
+          element = FPToDouble(element_fp16, kUseDefaultNaN);
+          break;
+        }
+        case kSRegSizeInBytes: {
+          float element_fp32;
+          memcpy(&element_fp32, &value[i * lane_size], sizeof(element_fp32));
+          element = static_cast<double>(element_fp32);
+          break;
+        }
+        case kDRegSizeInBytes: {
+          memcpy(&element, &value[i * lane_size], sizeof(element));
+          break;
+        }
+        default:
+          VIXL_UNREACHABLE();
+          fprintf(stream_, "{UnknownFPValue}");
+          continue;
+      }
+      if (IsNaN(element)) {
+        // The fprintf behaviour for NaNs is implementation-defined. Always
+        // print "nan", so that traces are consistent.
+        fprintf(stream_, "%s%snan%s", sep, clr_vreg_value, clr_normal);
+      } else {
+        fprintf(stream_,
+                "%s%s%#.4g%s",
+                sep,
+                clr_vreg_value,
+                element,
+                clr_normal);
+      }
+      last_inactive = false;
+    } else if (!last_inactive) {
+      // Replace each contiguous sequence of inactive lanes with "...".
+      fprintf(stream_, "%s...", sep);
+      last_inactive = true;
+    }
   }
-  fprintf(stream_, "%s", clr_normal);
+  fprintf(stream_, ")");
 }
 
+void Simulator::PrintRegister(int code,
+                              PrintRegisterFormat format,
+                              const char* suffix) {
+  VIXL_ASSERT((static_cast<unsigned>(code) < kNumberOfRegisters) ||
+              (static_cast<unsigned>(code) == kSPRegInternalCode));
+  VIXL_ASSERT((format & kPrintRegAsVectorMask) == kPrintRegAsScalar);
+  VIXL_ASSERT((format & kPrintRegAsFP) == 0);
 
-// Print each of the specified lanes of a register as a float or double value.
-//
-// The `lane_count` and `lslane` arguments can be used to limit the lanes that
-// are printed. These arguments are intended for use in cases where register
-// hasn't actually been updated (such as in PrintVWrite).
-//
-// No newline is printed. This allows the caller to print more details (such as
-// a memory access annotation).
-void Simulator::PrintVRegisterFPHelper(unsigned code,
-                                       unsigned lane_size_in_bytes,
-                                       int lane_count,
-                                       int rightmost_lane) {
-  VIXL_ASSERT((lane_size_in_bytes == kHRegSizeInBytes) ||
-              (lane_size_in_bytes == kSRegSizeInBytes) ||
-              (lane_size_in_bytes == kDRegSizeInBytes));
-
-  unsigned msb = ((lane_count + rightmost_lane) * lane_size_in_bytes);
-  VIXL_ASSERT(msb <= kQRegSizeInBytes);
-
-  // For scalar types ((lane_count == 1) && (rightmost_lane == 0)), a register
-  // name is used:
-  //   " (h{code}: {value})"
-  //   " (s{code}: {value})"
-  //   " (d{code}: {value})"
-  // For vector types, "..." is used to represent one or more omitted lanes.
-  //   " (..., {value}, {value}, ...)"
-  if (lane_size_in_bytes == kHRegSizeInBytes) {
-    // TODO: Trace tests will fail until we regenerate them.
-    return;
-  }
-  if ((lane_count == 1) && (rightmost_lane == 0)) {
-    const char* name;
-    switch (lane_size_in_bytes) {
-      case kHRegSizeInBytes:
-        name = HRegNameForCode(code);
-        break;
-      case kSRegSizeInBytes:
-        name = SRegNameForCode(code);
+  SimRegister* reg;
+  SimRegister zero;
+  if (code == kZeroRegCode) {
+    reg = &zero;
+  } else {
+    // registers_[31] holds the SP.
+    VIXL_STATIC_ASSERT((kSPRegInternalCode % kNumberOfRegisters) == 31);
+    reg = &registers_[code % kNumberOfRegisters];
+  }
+
+  // We trace register writes as whole register values, implying that any
+  // unprinted bits are all zero:
+  //   "#       x{code}: 0x{-----value----}"
+  //   "#       w{code}:         0x{-value}"
+  // Stores trace partial register values, implying nothing about the unprinted
+  // bits:
+  //   "# x{code}<63:0>: 0x{-----value----}"
+  //   "# x{code}<31:0>:         0x{-value}"
+  //   "# x{code}<15:0>:             0x{--}"
+  //   "#  x{code}<7:0>:               0x{}"
+
+  bool is_partial = (format & kPrintRegPartial) != 0;
+  unsigned print_reg_size = GetPrintRegSizeInBits(format);
+  std::stringstream name;
+  if (is_partial) {
+    name << XRegNameForCode(code) << GetPartialRegSuffix(format);
+  } else {
+    // Notify the register that it has been logged, but only if we're printing
+    // all of it.
+    reg->NotifyRegisterLogged();
+    switch (print_reg_size) {
+      case kWRegSize:
+        name << WRegNameForCode(code);
         break;
-      case kDRegSizeInBytes:
-        name = DRegNameForCode(code);
+      case kXRegSize:
+        name << XRegNameForCode(code);
         break;
       default:
-        name = NULL;
         VIXL_UNREACHABLE();
-    }
-    fprintf(stream_, " (%s%s: ", clr_vreg_name, name);
-  } else {
-    if (msb < (kQRegSizeInBytes - 1)) {
-      fprintf(stream_, " (..., ");
-    } else {
-      fprintf(stream_, " (");
+        return;
     }
   }
 
-  // Print the list of values.
-  const char* separator = "";
-  int leftmost_lane = rightmost_lane + lane_count - 1;
-  for (int lane = leftmost_lane; lane >= rightmost_lane; lane--) {
-    double value;
-    switch (lane_size_in_bytes) {
-      case kHRegSizeInBytes:
-        value = ReadVRegister(code).GetLane<uint16_t>(lane);
+  fprintf(stream_,
+          "# %s%*s: %s",
+          clr_reg_name,
+          kPrintRegisterNameFieldWidth,
+          name.str().c_str(),
+          clr_reg_value);
+  PrintRegisterValue(*reg, format);
+  fprintf(stream_, "%s%s", clr_normal, suffix);
+}
+
+void Simulator::PrintVRegister(int code,
+                               PrintRegisterFormat format,
+                               const char* suffix) {
+  VIXL_ASSERT(static_cast<unsigned>(code) < kNumberOfVRegisters);
+  VIXL_ASSERT(((format & kPrintRegAsVectorMask) == kPrintRegAsScalar) ||
+              ((format & kPrintRegAsVectorMask) == kPrintRegAsDVector) ||
+              ((format & kPrintRegAsVectorMask) == kPrintRegAsQVector));
+
+  // We trace register writes as whole register values, implying that any
+  // unprinted bits are all zero:
+  //   "#        v{code}: 0x{-------------value------------}"
+  //   "#        d{code}:                 0x{-----value----}"
+  //   "#        s{code}:                         0x{-value}"
+  //   "#        h{code}:                             0x{--}"
+  //   "#        b{code}:                               0x{}"
+  // Stores trace partial register values, implying nothing about the unprinted
+  // bits:
+  //   "# v{code}<127:0>: 0x{-------------value------------}"
+  //   "#  v{code}<63:0>:                 0x{-----value----}"
+  //   "#  v{code}<31:0>:                         0x{-value}"
+  //   "#  v{code}<15:0>:                             0x{--}"
+  //   "#   v{code}<7:0>:                               0x{}"
+
+  bool is_partial = ((format & kPrintRegPartial) != 0);
+  std::stringstream name;
+  unsigned print_reg_size = GetPrintRegSizeInBits(format);
+  if (is_partial) {
+    name << VRegNameForCode(code) << GetPartialRegSuffix(format);
+  } else {
+    // Notify the register that it has been logged, but only if we're printing
+    // all of it.
+    vregisters_[code].NotifyRegisterLogged();
+    switch (print_reg_size) {
+      case kBRegSize:
+        name << BRegNameForCode(code);
         break;
-      case kSRegSizeInBytes:
-        value = ReadVRegister(code).GetLane<float>(lane);
+      case kHRegSize:
+        name << HRegNameForCode(code);
         break;
-      case kDRegSizeInBytes:
-        value = ReadVRegister(code).GetLane<double>(lane);
+      case kSRegSize:
+        name << SRegNameForCode(code);
+        break;
+      case kDRegSize:
+        name << DRegNameForCode(code);
+        break;
+      case kQRegSize:
+        name << VRegNameForCode(code);
         break;
       default:
-        value = 0.0;
         VIXL_UNREACHABLE();
+        return;
     }
-    if (IsNaN(value)) {
-      // The output for NaNs is implementation defined. Always print `nan`, so
-      // that traces are coherent across different implementations.
-      fprintf(stream_, "%s%snan%s", separator, clr_vreg_value, clr_normal);
-    } else {
-      fprintf(stream_,
-              "%s%s%#g%s",
-              separator,
-              clr_vreg_value,
-              value,
-              clr_normal);
-    }
-    separator = ", ";
   }
 
-  if (rightmost_lane > 0) {
-    fprintf(stream_, ", ...");
+  fprintf(stream_,
+          "# %s%*s: %s",
+          clr_vreg_name,
+          kPrintRegisterNameFieldWidth,
+          name.str().c_str(),
+          clr_vreg_value);
+  PrintRegisterValue(vregisters_[code], format);
+  fprintf(stream_, "%s", clr_normal);
+  if ((format & kPrintRegAsFP) != 0) {
+    PrintRegisterValueFPAnnotations(vregisters_[code], format);
+  }
+  fprintf(stream_, "%s", suffix);
+}
+
+void Simulator::PrintVRegistersForStructuredAccess(int rt_code,
+                                                   int reg_count,
+                                                   uint16_t focus_mask,
+                                                   PrintRegisterFormat format) {
+  bool print_fp = (format & kPrintRegAsFP) != 0;
+  // Suppress FP formatting, so we can specify the lanes we're interested in.
+  PrintRegisterFormat format_no_fp =
+      static_cast<PrintRegisterFormat>(format & ~kPrintRegAsFP);
+
+  for (int r = 0; r < reg_count; r++) {
+    int code = (rt_code + r) % kNumberOfVRegisters;
+    PrintVRegister(code, format_no_fp, "");
+    if (print_fp) {
+      PrintRegisterValueFPAnnotations(vregisters_[code], focus_mask, format);
+    }
+    fprintf(stream_, "\n");
   }
-  fprintf(stream_, ")");
 }
 
+void Simulator::PrintZRegistersForStructuredAccess(int rt_code,
+                                                   int q_index,
+                                                   int reg_count,
+                                                   uint16_t focus_mask,
+                                                   PrintRegisterFormat format) {
+  bool print_fp = (format & kPrintRegAsFP) != 0;
+  // Suppress FP formatting, so we can specify the lanes we're interested in.
+  PrintRegisterFormat format_no_fp =
+      static_cast<PrintRegisterFormat>(format & ~kPrintRegAsFP);
 
-void Simulator::PrintVRegister(unsigned code, PrintRegisterFormat format) {
+  PrintRegisterFormat format_q = GetPrintRegAsQChunkOfSVE(format);
+
+  const unsigned size = kQRegSizeInBytes;
+  unsigned byte_index = q_index * size;
+  const uint8_t* value = vregisters_[rt_code].GetBytes() + byte_index;
+  VIXL_ASSERT((byte_index + size) <= vregisters_[rt_code].GetSizeInBytes());
+
+  for (int r = 0; r < reg_count; r++) {
+    int code = (rt_code + r) % kNumberOfZRegisters;
+    PrintPartialZRegister(code, q_index, format_no_fp, "");
+    if (print_fp) {
+      PrintRegisterValueFPAnnotations(value, focus_mask, format_q);
+    }
+    fprintf(stream_, "\n");
+  }
+}
+
+void Simulator::PrintZRegister(int code, PrintRegisterFormat format) {
+  // We're going to print the register in parts, so force a partial format.
+  format = GetPrintRegPartial(format);
+  VIXL_ASSERT((format & kPrintRegAsVectorMask) == kPrintRegAsSVEVector);
+  int vl = GetVectorLengthInBits();
+  VIXL_ASSERT((vl % kQRegSize) == 0);
+  for (unsigned i = 0; i < (vl / kQRegSize); i++) {
+    PrintPartialZRegister(code, i, format);
+  }
   vregisters_[code].NotifyRegisterLogged();
+}
 
-  int lane_size_log2 = format & kPrintRegLaneSizeMask;
+void Simulator::PrintPRegister(int code, PrintRegisterFormat format) {
+  // We're going to print the register in parts, so force a partial format.
+  format = GetPrintRegPartial(format);
+  VIXL_ASSERT((format & kPrintRegAsVectorMask) == kPrintRegAsSVEVector);
+  int vl = GetVectorLengthInBits();
+  VIXL_ASSERT((vl % kQRegSize) == 0);
+  for (unsigned i = 0; i < (vl / kQRegSize); i++) {
+    PrintPartialPRegister(code, i, format);
+  }
+  pregisters_[code].NotifyRegisterLogged();
+}
 
-  int reg_size_log2;
-  if (format & kPrintRegAsQVector) {
-    reg_size_log2 = kQRegSizeInBytesLog2;
-  } else if (format & kPrintRegAsDVector) {
-    reg_size_log2 = kDRegSizeInBytesLog2;
-  } else {
-    // Scalar types.
-    reg_size_log2 = lane_size_log2;
+void Simulator::PrintFFR(PrintRegisterFormat format) {
+  // We're going to print the register in parts, so force a partial format.
+  format = GetPrintRegPartial(format);
+  VIXL_ASSERT((format & kPrintRegAsVectorMask) == kPrintRegAsSVEVector);
+  int vl = GetVectorLengthInBits();
+  VIXL_ASSERT((vl % kQRegSize) == 0);
+  SimPRegister& ffr = ReadFFR();
+  for (unsigned i = 0; i < (vl / kQRegSize); i++) {
+    PrintPartialPRegister("FFR", ffr, i, format);
   }
+  ffr.NotifyRegisterLogged();
+}
+
+void Simulator::PrintPartialZRegister(int code,
+                                      int q_index,
+                                      PrintRegisterFormat format,
+                                      const char* suffix) {
+  VIXL_ASSERT(static_cast<unsigned>(code) < kNumberOfZRegisters);
+  VIXL_ASSERT((format & kPrintRegAsVectorMask) == kPrintRegAsSVEVector);
+  VIXL_ASSERT((format & kPrintRegPartial) != 0);
+  VIXL_ASSERT((q_index * kQRegSize) < GetVectorLengthInBits());
+
+  // We _only_ trace partial Z register values in Q-sized chunks, because
+  // they're often too large to reasonably fit on a single line. Each line
+  // implies nothing about the unprinted bits.
+  //   "# z{code}<127:0>: 0x{-------------value------------}"
+
+  format = GetPrintRegAsQChunkOfSVE(format);
 
-  int lane_count = 1 << (reg_size_log2 - lane_size_log2);
-  int lane_size = 1 << lane_size_log2;
+  const unsigned size = kQRegSizeInBytes;
+  unsigned byte_index = q_index * size;
+  const uint8_t* value = vregisters_[code].GetBytes() + byte_index;
+  VIXL_ASSERT((byte_index + size) <= vregisters_[code].GetSizeInBytes());
 
-  // The template for vector types:
-  //   "# v{code}: 0x{rawbits} (..., {value}, ...)".
-  // The template for scalar types:
-  //   "# v{code}: 0x{rawbits} ({reg}:{value})".
-  // The values in parentheses after the bit representations are floating-point
-  // interpretations. They are displayed only if the kPrintVRegAsFP bit is set.
+  int lsb = q_index * kQRegSize;
+  int msb = lsb + kQRegSize - 1;
+  std::stringstream name;
+  name << ZRegNameForCode(code) << '<' << msb << ':' << lsb << '>';
 
-  PrintVRegisterRawHelper(code);
-  if (format & kPrintRegAsFP) {
-    PrintVRegisterFPHelper(code, lane_size, lane_count);
+  fprintf(stream_,
+          "# %s%*s: %s",
+          clr_vreg_name,
+          kPrintRegisterNameFieldWidth,
+          name.str().c_str(),
+          clr_vreg_value);
+  PrintRegisterValue(value, size, format);
+  fprintf(stream_, "%s", clr_normal);
+  if ((format & kPrintRegAsFP) != 0) {
+    PrintRegisterValueFPAnnotations(value, GetPrintRegLaneMask(format), format);
   }
+  fprintf(stream_, "%s", suffix);
+}
+
+void Simulator::PrintPartialPRegister(const char* name,
+                                      const SimPRegister& reg,
+                                      int q_index,
+                                      PrintRegisterFormat format,
+                                      const char* suffix) {
+  VIXL_ASSERT((format & kPrintRegAsVectorMask) == kPrintRegAsSVEVector);
+  VIXL_ASSERT((format & kPrintRegPartial) != 0);
+  VIXL_ASSERT((q_index * kQRegSize) < GetVectorLengthInBits());
+
+  // We don't currently use the format for anything here.
+  USE(format);
 
-  fprintf(stream_, "\n");
+  // We _only_ trace partial P register values, because they're often too large
+  // to reasonably fit on a single line. Each line implies nothing about the
+  // unprinted bits.
+  //
+  // We print values in binary, with spaces between each bit, in order for the
+  // bits to align with the Z register bytes that they predicate.
+  //   "# {name}<15:0>: 0b{-------------value------------}"
+
+  int print_size_in_bits = kQRegSize / kZRegBitsPerPRegBit;
+  int lsb = q_index * print_size_in_bits;
+  int msb = lsb + print_size_in_bits - 1;
+  std::stringstream prefix;
+  prefix << name << '<' << msb << ':' << lsb << '>';
+
+  fprintf(stream_,
+          "# %s%*s: %s0b",
+          clr_preg_name,
+          kPrintRegisterNameFieldWidth,
+          prefix.str().c_str(),
+          clr_preg_value);
+  for (int i = msb; i >= lsb; i--) {
+    fprintf(stream_, " %c", reg.GetBit(i) ? '1' : '0');
+  }
+  fprintf(stream_, "%s%s", clr_normal, suffix);
 }
 
+void Simulator::PrintPartialPRegister(int code,
+                                      int q_index,
+                                      PrintRegisterFormat format,
+                                      const char* suffix) {
+  VIXL_ASSERT(static_cast<unsigned>(code) < kNumberOfPRegisters);
+  PrintPartialPRegister(PRegNameForCode(code),
+                        pregisters_[code],
+                        q_index,
+                        format,
+                        suffix);
+}
 
 void Simulator::PrintSystemRegister(SystemRegister id) {
   switch (id) {
@@ -954,90 +1216,347 @@ void Simulator::PrintSystemRegister(SystemRegister id) {
   }
 }
 
-
-void Simulator::PrintRead(uintptr_t address,
-                          unsigned reg_code,
-                          PrintRegisterFormat format) {
-  registers_[reg_code].NotifyRegisterLogged();
-
-  USE(format);
-
-  // The template is "# {reg}: 0x{value} <- {address}".
-  PrintRegisterRawHelper(reg_code, Reg31IsZeroRegister);
+uint16_t Simulator::PrintPartialAccess(uint16_t access_mask,
+                                       uint16_t future_access_mask,
+                                       int struct_element_count,
+                                       int lane_size_in_bytes,
+                                       const char* op,
+                                       uintptr_t address,
+                                       int reg_size_in_bytes) {
+  // We want to assume that we'll access at least one lane.
+  VIXL_ASSERT(access_mask != 0);
+  VIXL_ASSERT((reg_size_in_bytes == kXRegSizeInBytes) ||
+              (reg_size_in_bytes == kQRegSizeInBytes));
+  bool started_annotation = false;
+  // Indent to match the register field, the fixed formatting, and the value
+  // prefix ("0x"): "# {name}: 0x"
+  fprintf(stream_, "# %*s    ", kPrintRegisterNameFieldWidth, "");
+  // First, annotate the lanes (byte by byte).
+  for (int lane = reg_size_in_bytes - 1; lane >= 0; lane--) {
+    bool access = (access_mask & (1 << lane)) != 0;
+    bool future = (future_access_mask & (1 << lane)) != 0;
+    if (started_annotation) {
+      // If we've started an annotation, draw a horizontal line in addition to
+      // any other symbols.
+      if (access) {
+        fprintf(stream_, "─╨");
+      } else if (future) {
+        fprintf(stream_, "─║");
+      } else {
+        fprintf(stream_, "──");
+      }
+    } else {
+      if (access) {
+        started_annotation = true;
+        fprintf(stream_, " ╙");
+      } else if (future) {
+        fprintf(stream_, " ║");
+      } else {
+        fprintf(stream_, "  ");
+      }
+    }
+  }
+  VIXL_ASSERT(started_annotation);
+  fprintf(stream_, "─ 0x");
+  int lane_size_in_nibbles = lane_size_in_bytes * 2;
+  // Print the most-significant struct element first.
+  const char* sep = "";
+  for (int i = struct_element_count - 1; i >= 0; i--) {
+    int offset = lane_size_in_bytes * i;
+    uint64_t nibble = MemReadUint(lane_size_in_bytes, address + offset);
+    fprintf(stream_, "%s%0*" PRIx64, sep, lane_size_in_nibbles, nibble);
+    sep = "'";
+  }
   fprintf(stream_,
-          " <- %s0x%016" PRIxPTR "%s\n",
+          " %s %s0x%016" PRIxPTR "%s\n",
+          op,
           clr_memory_address,
           address,
           clr_normal);
+  return future_access_mask & ~access_mask;
 }
 
-
-void Simulator::PrintVRead(uintptr_t address,
-                           unsigned reg_code,
-                           PrintRegisterFormat format,
-                           unsigned lane) {
-  vregisters_[reg_code].NotifyRegisterLogged();
-
-  // The template is "# v{code}: 0x{rawbits} <- address".
-  PrintVRegisterRawHelper(reg_code);
-  if (format & kPrintRegAsFP) {
-    PrintVRegisterFPHelper(reg_code,
-                           GetPrintRegLaneSizeInBytes(format),
-                           GetPrintRegLaneCount(format),
-                           lane);
+void Simulator::PrintAccess(int code,
+                            PrintRegisterFormat format,
+                            const char* op,
+                            uintptr_t address) {
+  VIXL_ASSERT(GetPrintRegLaneCount(format) == 1);
+  VIXL_ASSERT((strcmp(op, "->") == 0) || (strcmp(op, "<-") == 0));
+  if ((format & kPrintRegPartial) == 0) {
+    registers_[code].NotifyRegisterLogged();
   }
+  // Scalar-format accesses use a simple format:
+  //   "# {reg}: 0x{value} -> {address}"
+
+  // Suppress the newline, so the access annotation goes on the same line.
+  PrintRegister(code, format, "");
   fprintf(stream_,
-          " <- %s0x%016" PRIxPTR "%s\n",
+          " %s %s0x%016" PRIxPTR "%s\n",
+          op,
           clr_memory_address,
           address,
           clr_normal);
 }
 
+void Simulator::PrintVAccess(int code,
+                             PrintRegisterFormat format,
+                             const char* op,
+                             uintptr_t address) {
+  VIXL_ASSERT((strcmp(op, "->") == 0) || (strcmp(op, "<-") == 0));
 
-void Simulator::PrintWrite(uintptr_t address,
-                           unsigned reg_code,
-                           PrintRegisterFormat format) {
-  VIXL_ASSERT(GetPrintRegLaneCount(format) == 1);
+  // Scalar-format accesses use a simple format:
+  //   "# v{code}: 0x{value} -> {address}"
 
-  // The template is "# v{code}: 0x{value} -> {address}". To keep the trace tidy
-  // and readable, the value is aligned with the values in the register trace.
-  PrintRegisterRawHelper(reg_code,
-                         Reg31IsZeroRegister,
-                         GetPrintRegSizeInBytes(format));
+  // Suppress the newline, so the access annotation goes on the same line.
+  PrintVRegister(code, format, "");
   fprintf(stream_,
-          " -> %s0x%016" PRIxPTR "%s\n",
+          " %s %s0x%016" PRIxPTR "%s\n",
+          op,
           clr_memory_address,
           address,
           clr_normal);
 }
 
+void Simulator::PrintVStructAccess(int rt_code,
+                                   int reg_count,
+                                   PrintRegisterFormat format,
+                                   const char* op,
+                                   uintptr_t address) {
+  VIXL_ASSERT((strcmp(op, "->") == 0) || (strcmp(op, "<-") == 0));
+
+  // For example:
+  //   "# v{code}: 0x{value}"
+  //   "#     ...: 0x{value}"
+  //   "#              ║   ╙─ {struct_value} -> {lowest_address}"
+  //   "#              ╙───── {struct_value} -> {highest_address}"
+
+  uint16_t lane_mask = GetPrintRegLaneMask(format);
+  PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format);
+
+  int reg_size_in_bytes = GetPrintRegSizeInBytes(format);
+  int lane_size_in_bytes = GetPrintRegLaneSizeInBytes(format);
+  for (int i = 0; i < reg_size_in_bytes; i += lane_size_in_bytes) {
+    uint16_t access_mask = 1 << i;
+    VIXL_ASSERT((lane_mask & access_mask) != 0);
+    lane_mask = PrintPartialAccess(access_mask,
+                                   lane_mask,
+                                   reg_count,
+                                   lane_size_in_bytes,
+                                   op,
+                                   address + (i * reg_count));
+  }
+}
+
+void Simulator::PrintVSingleStructAccess(int rt_code,
+                                         int reg_count,
+                                         int lane,
+                                         PrintRegisterFormat format,
+                                         const char* op,
+                                         uintptr_t address) {
+  VIXL_ASSERT((strcmp(op, "->") == 0) || (strcmp(op, "<-") == 0));
+
+  // For example:
+  //   "# v{code}: 0x{value}"
+  //   "#     ...: 0x{value}"
+  //   "#              ╙───── {struct_value} -> {address}"
+
+  int lane_size_in_bytes = GetPrintRegLaneSizeInBytes(format);
+  uint16_t lane_mask = 1 << (lane * lane_size_in_bytes);
+  PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format);
+  PrintPartialAccess(lane_mask, 0, reg_count, lane_size_in_bytes, op, address);
+}
+
+void Simulator::PrintVReplicatingStructAccess(int rt_code,
+                                              int reg_count,
+                                              PrintRegisterFormat format,
+                                              const char* op,
+                                              uintptr_t address) {
+  VIXL_ASSERT((strcmp(op, "->") == 0) || (strcmp(op, "<-") == 0));
+
+  // For example:
+  //   "# v{code}: 0x{value}"
+  //   "#     ...: 0x{value}"
+  //   "#            ╙─╨─╨─╨─ {struct_value} -> {address}"
+
+  int lane_size_in_bytes = GetPrintRegLaneSizeInBytes(format);
+  uint16_t lane_mask = GetPrintRegLaneMask(format);
+  PrintVRegistersForStructuredAccess(rt_code, reg_count, lane_mask, format);
+  PrintPartialAccess(lane_mask, 0, reg_count, lane_size_in_bytes, op, address);
+}
+
+void Simulator::PrintZAccess(int rt_code, const char* op, uintptr_t address) {
+  VIXL_ASSERT((strcmp(op, "->") == 0) || (strcmp(op, "<-") == 0));
+
+  // Scalar-format accesses are split into separate chunks, each of which uses a
+  // simple format:
+  //   "#   z{code}<127:0>: 0x{value} -> {address}"
+  //   "# z{code}<255:128>: 0x{value} -> {address + 16}"
+  //   "# z{code}<383:256>: 0x{value} -> {address + 32}"
+  // etc
+
+  int vl = GetVectorLengthInBits();
+  VIXL_ASSERT((vl % kQRegSize) == 0);
+  for (unsigned q_index = 0; q_index < (vl / kQRegSize); q_index++) {
+    // Suppress the newline, so the access annotation goes on the same line.
+    PrintPartialZRegister(rt_code, q_index, kPrintRegVnQPartial, "");
+    fprintf(stream_,
+            " %s %s0x%016" PRIxPTR "%s\n",
+            op,
+            clr_memory_address,
+            address,
+            clr_normal);
+    address += kQRegSizeInBytes;
+  }
+}
+
+void Simulator::PrintZStructAccess(int rt_code,
+                                   int reg_count,
+                                   const LogicPRegister& pg,
+                                   PrintRegisterFormat format,
+                                   int msize_in_bytes,
+                                   const char* op,
+                                   const LogicSVEAddressVector& addr) {
+  VIXL_ASSERT((strcmp(op, "->") == 0) || (strcmp(op, "<-") == 0));
+
+  // For example:
+  //   "# z{code}<255:128>: 0x{value}"
+  //   "#     ...<255:128>: 0x{value}"
+  //   "#                       ║   ╙─ {struct_value} -> {first_address}"
+  //   "#                       ╙───── {struct_value} -> {last_address}"
+
+  // We're going to print the register in parts, so force a partial format.
+  bool skip_inactive_chunks = (format & kPrintRegPartial) != 0;
+  format = GetPrintRegPartial(format);
+
+  int esize_in_bytes = GetPrintRegLaneSizeInBytes(format);
+  int vl = GetVectorLengthInBits();
+  VIXL_ASSERT((vl % kQRegSize) == 0);
+  int lanes_per_q = kQRegSizeInBytes / esize_in_bytes;
+  for (unsigned q_index = 0; q_index < (vl / kQRegSize); q_index++) {
+    uint16_t pred =
+        pg.GetActiveMask<uint16_t>(q_index) & GetPrintRegLaneMask(format);
+    if ((pred == 0) && skip_inactive_chunks) continue;
+
+    PrintZRegistersForStructuredAccess(rt_code,
+                                       q_index,
+                                       reg_count,
+                                       pred,
+                                       format);
+    if (pred == 0) {
+      // This register chunk has no active lanes. The loop below would print
+      // nothing, so leave a blank line to keep structures grouped together.
+      fprintf(stream_, "#\n");
+      continue;
+    }
+    for (int i = 0; i < lanes_per_q; i++) {
+      uint16_t access = 1 << (i * esize_in_bytes);
+      int lane = (q_index * lanes_per_q) + i;
+      // Skip inactive lanes.
+      if ((pred & access) == 0) continue;
+      pred = PrintPartialAccess(access,
+                                pred,
+                                reg_count,
+                                msize_in_bytes,
+                                op,
+                                addr.GetStructAddress(lane));
+    }
+  }
 
-void Simulator::PrintVWrite(uintptr_t address,
-                            unsigned reg_code,
-                            PrintRegisterFormat format,
-                            unsigned lane) {
-  // The templates:
-  //   "# v{code}: 0x{rawbits} -> {address}"
-  //   "# v{code}: 0x{rawbits} (..., {value}, ...) -> {address}".
-  //   "# v{code}: 0x{rawbits} ({reg}:{value}) -> {address}"
-  // Because this trace doesn't represent a change to the source register's
-  // value, only the relevant part of the value is printed. To keep the trace
-  // tidy and readable, the raw value is aligned with the other values in the
-  // register trace.
-  int lane_count = GetPrintRegLaneCount(format);
-  int lane_size = GetPrintRegLaneSizeInBytes(format);
-  int reg_size = GetPrintRegSizeInBytes(format);
-  PrintVRegisterRawHelper(reg_code, reg_size, lane_size * lane);
-  if (format & kPrintRegAsFP) {
-    PrintVRegisterFPHelper(reg_code, lane_size, lane_count, lane);
+  // We print the whole register, even for stores.
+  for (int i = 0; i < reg_count; i++) {
+    vregisters_[(rt_code + i) % kNumberOfZRegisters].NotifyRegisterLogged();
   }
-  fprintf(stream_,
-          " -> %s0x%016" PRIxPTR "%s\n",
-          clr_memory_address,
-          address,
-          clr_normal);
 }
 
+void Simulator::PrintPAccess(int code, const char* op, uintptr_t address) {
+  VIXL_ASSERT((strcmp(op, "->") == 0) || (strcmp(op, "<-") == 0));
+
+  // Scalar-format accesses are split into separate chunks, each of which uses a
+  // simple format:
+  //   "#  p{code}<15:0>: 0b{value} -> {address}"
+  //   "# p{code}<31:16>: 0b{value} -> {address + 2}"
+  //   "# p{code}<47:32>: 0b{value} -> {address + 4}"
+  // etc
+
+  int vl = GetVectorLengthInBits();
+  VIXL_ASSERT((vl % kQRegSize) == 0);
+  for (unsigned q_index = 0; q_index < (vl / kQRegSize); q_index++) {
+    // Suppress the newline, so the access annotation goes on the same line.
+    PrintPartialPRegister(code, q_index, kPrintRegVnQPartial, "");
+    fprintf(stream_,
+            " %s %s0x%016" PRIxPTR "%s\n",
+            op,
+            clr_memory_address,
+            address,
+            clr_normal);
+    address += kQRegSizeInBytes;
+  }
+}
+
+void Simulator::PrintRead(int rt_code,
+                          PrintRegisterFormat format,
+                          uintptr_t address) {
+  VIXL_ASSERT(GetPrintRegLaneCount(format) == 1);
+  registers_[rt_code].NotifyRegisterLogged();
+  PrintAccess(rt_code, format, "<-", address);
+}
+
+void Simulator::PrintExtendingRead(int rt_code,
+                                   PrintRegisterFormat format,
+                                   int access_size_in_bytes,
+                                   uintptr_t address) {
+  int reg_size_in_bytes = GetPrintRegSizeInBytes(format);
+  if (access_size_in_bytes == reg_size_in_bytes) {
+    // There is no extension here, so print a simple load.
+    PrintRead(rt_code, format, address);
+    return;
+  }
+  VIXL_ASSERT(access_size_in_bytes < reg_size_in_bytes);
+
+  // For sign- and zero-extension, make it clear that the resulting register
+  // value is different from what is loaded from memory.
+  VIXL_ASSERT(GetPrintRegLaneCount(format) == 1);
+  registers_[rt_code].NotifyRegisterLogged();
+  PrintRegister(rt_code, format);
+  PrintPartialAccess(1,
+                     0,
+                     1,
+                     access_size_in_bytes,
+                     "<-",
+                     address,
+                     kXRegSizeInBytes);
+}
+
+void Simulator::PrintVRead(int rt_code,
+                           PrintRegisterFormat format,
+                           uintptr_t address) {
+  VIXL_ASSERT(GetPrintRegLaneCount(format) == 1);
+  vregisters_[rt_code].NotifyRegisterLogged();
+  PrintVAccess(rt_code, format, "<-", address);
+}
+
+void Simulator::PrintWrite(int rt_code,
+                           PrintRegisterFormat format,
+                           uintptr_t address) {
+  // Because this trace doesn't represent a change to the source register's
+  // value, only print the relevant part of the value.
+  format = GetPrintRegPartial(format);
+  VIXL_ASSERT(GetPrintRegLaneCount(format) == 1);
+  registers_[rt_code].NotifyRegisterLogged();
+  PrintAccess(rt_code, format, "->", address);
+}
+
+void Simulator::PrintVWrite(int rt_code,
+                            PrintRegisterFormat format,
+                            uintptr_t address) {
+  // Because this trace doesn't represent a change to the source register's
+  // value, only print the relevant part of the value.
+  format = GetPrintRegPartial(format);
+  // It only makes sense to write scalar values here. Vectors are handled by
+  // PrintVStructAccess.
+  VIXL_ASSERT(GetPrintRegLaneCount(format) == 1);
+  PrintVAccess(rt_code, format, "->", address);
+}
 
 void Simulator::PrintTakenBranch(const Instruction* target) {
   fprintf(stream_,
@@ -1047,7 +1566,6 @@ void Simulator::PrintTakenBranch(const Instruction* target) {
           reinterpret_cast<uint64_t>(target));
 }
 
-
 // Visitors---------------------------------------------------------------------
 
 
@@ -1289,7 +1807,7 @@ void Simulator::VisitAddSubShifted(const Instruction* instr) {
 
 void Simulator::VisitAddSubImmediate(const Instruction* instr) {
   int64_t op2 = instr->GetImmAddSub()
-                << ((instr->GetShiftAddSub() == 1) ? 12 : 0);
+                << ((instr->GetImmAddSubShift() == 1) ? 12 : 0);
   AddSubHelper(instr, op2);
 }
 
@@ -1367,7 +1885,11 @@ void Simulator::VisitLogicalShifted(const Instruction* instr) {
 
 
 void Simulator::VisitLogicalImmediate(const Instruction* instr) {
-  LogicalHelper(instr, instr->GetImmLogical());
+  if (instr->GetImmLogical() == 0) {
+    VIXL_UNIMPLEMENTED();
+  } else {
+    LogicalHelper(instr, instr->GetImmLogical());
+  }
 }
 
 
@@ -1484,12 +2006,12 @@ void Simulator::LoadAcquireRCpcUnscaledOffsetHelper(const Instruction* instr) {
     VIXL_ALIGNMENT_EXCEPTION();
   }
 
-  WriteRegister<T1>(rt, static_cast<T1>(Memory::Read<T2>(address)));
+  WriteRegister<T1>(rt, static_cast<T1>(MemRead<T2>(address)));
 
   // Approximate load-acquire by issuing a full barrier after the load.
   __sync_synchronize();
 
-  LogRead(address, rt, GetPrintRegisterFormat(element_size));
+  LogRead(rt, GetPrintRegisterFormat(element_size), address);
 }
 
 
@@ -1514,9 +2036,9 @@ void Simulator::StoreReleaseUnscaledOffsetHelper(const Instruction* instr) {
   // Approximate store-release by issuing a full barrier after the load.
   __sync_synchronize();
 
-  Memory::Write<T>(address, ReadRegister<T>(rt));
+  MemWrite<T>(address, ReadRegister<T>(rt));
 
-  LogWrite(address, rt, GetPrintRegisterFormat(element_size));
+  LogWrite(rt, GetPrintRegisterFormat(element_size), address);
 }
 
 
@@ -1601,9 +2123,9 @@ void Simulator::VisitLoadStorePAC(const Instruction* instr) {
   // Verify that the calculated address is available to the host.
   VIXL_ASSERT(address == addr_ptr);
 
-  WriteXRegister(dst, Memory::Read<uint64_t>(addr_ptr), NoRegLog);
+  WriteXRegister(dst, MemRead<uint64_t>(addr_ptr), NoRegLog);
   unsigned access_size = 1 << 3;
-  LogRead(addr_ptr, dst, GetPrintRegisterFormatForSize(access_size));
+  LogRead(dst, GetPrintRegisterFormatForSize(access_size), addr_ptr);
 }
 
 
@@ -1624,77 +2146,98 @@ void Simulator::LoadStoreHelper(const Instruction* instr,
   unsigned srcdst = instr->GetRt();
   uintptr_t address = AddressModeHelper(instr->GetRn(), offset, addrmode);
 
+  bool rt_is_vreg = false;
+  int extend_to_size = 0;
   LoadStoreOp op = static_cast<LoadStoreOp>(instr->Mask(LoadStoreMask));
   switch (op) {
     case LDRB_w:
-      WriteWRegister(srcdst, Memory::Read<uint8_t>(address), NoRegLog);
+      WriteWRegister(srcdst, MemRead<uint8_t>(address), NoRegLog);
+      extend_to_size = kWRegSizeInBytes;
       break;
     case LDRH_w:
-      WriteWRegister(srcdst, Memory::Read<uint16_t>(address), NoRegLog);
+      WriteWRegister(srcdst, MemRead<uint16_t>(address), NoRegLog);
+      extend_to_size = kWRegSizeInBytes;
       break;
     case LDR_w:
-      WriteWRegister(srcdst, Memory::Read<uint32_t>(address), NoRegLog);
+      WriteWRegister(srcdst, MemRead<uint32_t>(address), NoRegLog);
+      extend_to_size = kWRegSizeInBytes;
       break;
     case LDR_x:
-      WriteXRegister(srcdst, Memory::Read<uint64_t>(address), NoRegLog);
+      WriteXRegister(srcdst, MemRead<uint64_t>(address), NoRegLog);
+      extend_to_size = kXRegSizeInBytes;
       break;
     case LDRSB_w:
-      WriteWRegister(srcdst, Memory::Read<int8_t>(address), NoRegLog);
+      WriteWRegister(srcdst, MemRead<int8_t>(address), NoRegLog);
+      extend_to_size = kWRegSizeInBytes;
       break;
     case LDRSH_w:
-      WriteWRegister(srcdst, Memory::Read<int16_t>(address), NoRegLog);
+      WriteWRegister(srcdst, MemRead<int16_t>(address), NoRegLog);
+      extend_to_size = kWRegSizeInBytes;
       break;
     case LDRSB_x:
-      WriteXRegister(srcdst, Memory::Read<int8_t>(address), NoRegLog);
+      WriteXRegister(srcdst, MemRead<int8_t>(address), NoRegLog);
+      extend_to_size = kXRegSizeInBytes;
       break;
     case LDRSH_x:
-      WriteXRegister(srcdst, Memory::Read<int16_t>(address), NoRegLog);
+      WriteXRegister(srcdst, MemRead<int16_t>(address), NoRegLog);
+      extend_to_size = kXRegSizeInBytes;
       break;
     case LDRSW_x:
-      WriteXRegister(srcdst, Memory::Read<int32_t>(address), NoRegLog);
+      WriteXRegister(srcdst, MemRead<int32_t>(address), NoRegLog);
+      extend_to_size = kXRegSizeInBytes;
       break;
     case LDR_b:
-      WriteBRegister(srcdst, Memory::Read<uint8_t>(address), NoRegLog);
+      WriteBRegister(srcdst, MemRead<uint8_t>(address), NoRegLog);
+      rt_is_vreg = true;
       break;
     case LDR_h:
-      WriteHRegister(srcdst, Memory::Read<uint16_t>(address), NoRegLog);
+      WriteHRegister(srcdst, MemRead<uint16_t>(address), NoRegLog);
+      rt_is_vreg = true;
       break;
     case LDR_s:
-      WriteSRegister(srcdst, Memory::Read<float>(address), NoRegLog);
+      WriteSRegister(srcdst, MemRead<float>(address), NoRegLog);
+      rt_is_vreg = true;
       break;
     case LDR_d:
-      WriteDRegister(srcdst, Memory::Read<double>(address), NoRegLog);
+      WriteDRegister(srcdst, MemRead<double>(address), NoRegLog);
+      rt_is_vreg = true;
       break;
     case LDR_q:
-      WriteQRegister(srcdst, Memory::Read<qreg_t>(address), NoRegLog);
+      WriteQRegister(srcdst, MemRead<qreg_t>(address), NoRegLog);
+      rt_is_vreg = true;
       break;
 
     case STRB_w:
-      Memory::Write<uint8_t>(address, ReadWRegister(srcdst));
+      MemWrite<uint8_t>(address, ReadWRegister(srcdst));
       break;
     case STRH_w:
-      Memory::Write<uint16_t>(address, ReadWRegister(srcdst));
+      MemWrite<uint16_t>(address, ReadWRegister(srcdst));
       break;
     case STR_w:
-      Memory::Write<uint32_t>(address, ReadWRegister(srcdst));
+      MemWrite<uint32_t>(address, ReadWRegister(srcdst));
       break;
     case STR_x:
-      Memory::Write<uint64_t>(address, ReadXRegister(srcdst));
+      MemWrite<uint64_t>(address, ReadXRegister(srcdst));
       break;
     case STR_b:
-      Memory::Write<uint8_t>(address, ReadBRegister(srcdst));
+      MemWrite<uint8_t>(address, ReadBRegister(srcdst));
+      rt_is_vreg = true;
       break;
     case STR_h:
-      Memory::Write<uint16_t>(address, ReadHRegisterBits(srcdst));
+      MemWrite<uint16_t>(address, ReadHRegisterBits(srcdst));
+      rt_is_vreg = true;
       break;
     case STR_s:
-      Memory::Write<float>(address, ReadSRegister(srcdst));
+      MemWrite<float>(address, ReadSRegister(srcdst));
+      rt_is_vreg = true;
       break;
     case STR_d:
-      Memory::Write<double>(address, ReadDRegister(srcdst));
+      MemWrite<double>(address, ReadDRegister(srcdst));
+      rt_is_vreg = true;
       break;
     case STR_q:
-      Memory::Write<qreg_t>(address, ReadQRegister(srcdst));
+      MemWrite<qreg_t>(address, ReadQRegister(srcdst));
+      rt_is_vreg = true;
       break;
 
     // Ignore prfm hint instructions.
@@ -1705,22 +2248,25 @@ void Simulator::LoadStoreHelper(const Instruction* instr,
       VIXL_UNIMPLEMENTED();
   }
 
+  // Print a detailed trace (including the memory address).
+  bool extend = (extend_to_size != 0);
   unsigned access_size = 1 << instr->GetSizeLS();
+  unsigned result_size = extend ? extend_to_size : access_size;
+  PrintRegisterFormat print_format =
+      rt_is_vreg ? GetPrintRegisterFormatForSizeTryFP(result_size)
+                 : GetPrintRegisterFormatForSize(result_size);
+
   if (instr->IsLoad()) {
-    if ((op == LDR_s) || (op == LDR_d)) {
-      LogVRead(address, srcdst, GetPrintRegisterFormatForSizeFP(access_size));
-    } else if ((op == LDR_b) || (op == LDR_h) || (op == LDR_q)) {
-      LogVRead(address, srcdst, GetPrintRegisterFormatForSize(access_size));
+    if (rt_is_vreg) {
+      LogVRead(srcdst, print_format, address);
     } else {
-      LogRead(address, srcdst, GetPrintRegisterFormatForSize(access_size));
+      LogExtendingRead(srcdst, print_format, access_size, address);
     }
   } else if (instr->IsStore()) {
-    if ((op == STR_s) || (op == STR_d)) {
-      LogVWrite(address, srcdst, GetPrintRegisterFormatForSizeFP(access_size));
-    } else if ((op == STR_b) || (op == STR_h) || (op == STR_q)) {
-      LogVWrite(address, srcdst, GetPrintRegisterFormatForSize(access_size));
+    if (rt_is_vreg) {
+      LogVWrite(srcdst, print_format, address);
     } else {
-      LogWrite(address, srcdst, GetPrintRegisterFormatForSize(access_size));
+      LogWrite(srcdst, GetPrintRegisterFormatForSize(result_size), address);
     }
   } else {
     VIXL_ASSERT(op == PRFM);
@@ -1765,91 +2311,101 @@ void Simulator::LoadStorePairHelper(const Instruction* instr,
   // 'rt' and 'rt2' can only be aliased for stores.
   VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2));
 
+  bool rt_is_vreg = false;
+  bool sign_extend = false;
   switch (op) {
     // Use NoRegLog to suppress the register trace (LOG_REGS, LOG_FP_REGS). We
     // will print a more detailed log.
     case LDP_w: {
-      WriteWRegister(rt, Memory::Read<uint32_t>(address), NoRegLog);
-      WriteWRegister(rt2, Memory::Read<uint32_t>(address2), NoRegLog);
+      WriteWRegister(rt, MemRead<uint32_t>(address), NoRegLog);
+      WriteWRegister(rt2, MemRead<uint32_t>(address2), NoRegLog);
       break;
     }
     case LDP_s: {
-      WriteSRegister(rt, Memory::Read<float>(address), NoRegLog);
-      WriteSRegister(rt2, Memory::Read<float>(address2), NoRegLog);
+      WriteSRegister(rt, MemRead<float>(address), NoRegLog);
+      WriteSRegister(rt2, MemRead<float>(address2), NoRegLog);
+      rt_is_vreg = true;
       break;
     }
     case LDP_x: {
-      WriteXRegister(rt, Memory::Read<uint64_t>(address), NoRegLog);
-      WriteXRegister(rt2, Memory::Read<uint64_t>(address2), NoRegLog);
+      WriteXRegister(rt, MemRead<uint64_t>(address), NoRegLog);
+      WriteXRegister(rt2, MemRead<uint64_t>(address2), NoRegLog);
       break;
     }
     case LDP_d: {
-      WriteDRegister(rt, Memory::Read<double>(address), NoRegLog);
-      WriteDRegister(rt2, Memory::Read<double>(address2), NoRegLog);
+      WriteDRegister(rt, MemRead<double>(address), NoRegLog);
+      WriteDRegister(rt2, MemRead<double>(address2), NoRegLog);
+      rt_is_vreg = true;
       break;
     }
     case LDP_q: {
-      WriteQRegister(rt, Memory::Read<qreg_t>(address), NoRegLog);
-      WriteQRegister(rt2, Memory::Read<qreg_t>(address2), NoRegLog);
+      WriteQRegister(rt, MemRead<qreg_t>(address), NoRegLog);
+      WriteQRegister(rt2, MemRead<qreg_t>(address2), NoRegLog);
+      rt_is_vreg = true;
       break;
     }
     case LDPSW_x: {
-      WriteXRegister(rt, Memory::Read<int32_t>(address), NoRegLog);
-      WriteXRegister(rt2, Memory::Read<int32_t>(address2), NoRegLog);
+      WriteXRegister(rt, MemRead<int32_t>(address), NoRegLog);
+      WriteXRegister(rt2, MemRead<int32_t>(address2), NoRegLog);
+      sign_extend = true;
       break;
     }
     case STP_w: {
-      Memory::Write<uint32_t>(address, ReadWRegister(rt));
-      Memory::Write<uint32_t>(address2, ReadWRegister(rt2));
+      MemWrite<uint32_t>(address, ReadWRegister(rt));
+      MemWrite<uint32_t>(address2, ReadWRegister(rt2));
       break;
     }
     case STP_s: {
-      Memory::Write<float>(address, ReadSRegister(rt));
-      Memory::Write<float>(address2, ReadSRegister(rt2));
+      MemWrite<float>(address, ReadSRegister(rt));
+      MemWrite<float>(address2, ReadSRegister(rt2));
+      rt_is_vreg = true;
       break;
     }
     case STP_x: {
-      Memory::Write<uint64_t>(address, ReadXRegister(rt));
-      Memory::Write<uint64_t>(address2, ReadXRegister(rt2));
+      MemWrite<uint64_t>(address, ReadXRegister(rt));
+      MemWrite<uint64_t>(address2, ReadXRegister(rt2));
       break;
     }
     case STP_d: {
-      Memory::Write<double>(address, ReadDRegister(rt));
-      Memory::Write<double>(address2, ReadDRegister(rt2));
+      MemWrite<double>(address, ReadDRegister(rt));
+      MemWrite<double>(address2, ReadDRegister(rt2));
+      rt_is_vreg = true;
       break;
     }
     case STP_q: {
-      Memory::Write<qreg_t>(address, ReadQRegister(rt));
-      Memory::Write<qreg_t>(address2, ReadQRegister(rt2));
+      MemWrite<qreg_t>(address, ReadQRegister(rt));
+      MemWrite<qreg_t>(address2, ReadQRegister(rt2));
+      rt_is_vreg = true;
       break;
     }
     default:
       VIXL_UNREACHABLE();
   }
 
-  // Print a detailed trace (including the memory address) instead of the basic
-  // register:value trace generated by set_*reg().
+  // Print a detailed trace (including the memory address).
+  unsigned result_size = sign_extend ? kXRegSizeInBytes : element_size;
+  PrintRegisterFormat print_format =
+      rt_is_vreg ? GetPrintRegisterFormatForSizeTryFP(result_size)
+                 : GetPrintRegisterFormatForSize(result_size);
+
   if (instr->IsLoad()) {
-    if ((op == LDP_s) || (op == LDP_d)) {
-      LogVRead(address, rt, GetPrintRegisterFormatForSizeFP(element_size));
-      LogVRead(address2, rt2, GetPrintRegisterFormatForSizeFP(element_size));
-    } else if (op == LDP_q) {
-      LogVRead(address, rt, GetPrintRegisterFormatForSize(element_size));
-      LogVRead(address2, rt2, GetPrintRegisterFormatForSize(element_size));
+    if (rt_is_vreg) {
+      LogVRead(rt, print_format, address);
+      LogVRead(rt2, print_format, address2);
+    } else if (sign_extend) {
+      LogExtendingRead(rt, print_format, element_size, address);
+      LogExtendingRead(rt2, print_format, element_size, address2);
     } else {
-      LogRead(address, rt, GetPrintRegisterFormatForSize(element_size));
-      LogRead(address2, rt2, GetPrintRegisterFormatForSize(element_size));
+      LogRead(rt, print_format, address);
+      LogRead(rt2, print_format, address2);
     }
   } else {
-    if ((op == STP_s) || (op == STP_d)) {
-      LogVWrite(address, rt, GetPrintRegisterFormatForSizeFP(element_size));
-      LogVWrite(address2, rt2, GetPrintRegisterFormatForSizeFP(element_size));
-    } else if (op == STP_q) {
-      LogVWrite(address, rt, GetPrintRegisterFormatForSize(element_size));
-      LogVWrite(address2, rt2, GetPrintRegisterFormatForSize(element_size));
+    if (rt_is_vreg) {
+      LogVWrite(rt, print_format, address);
+      LogVWrite(rt2, print_format, address2);
     } else {
-      LogWrite(address, rt, GetPrintRegisterFormatForSize(element_size));
-      LogWrite(address2, rt2, GetPrintRegisterFormatForSize(element_size));
+      LogWrite(rt, print_format, address);
+      LogWrite(rt2, print_format, address2);
     }
   }
 
@@ -1878,7 +2434,7 @@ void Simulator::CompareAndSwapHelper(const Instruction* instr) {
   // associated with that location, even if the compare subsequently fails.
   local_monitor_.Clear();
 
-  T data = Memory::Read<T>(address);
+  T data = MemRead<T>(address);
   if (is_acquire) {
     // Approximate load-acquire by issuing a full barrier after the load.
     __sync_synchronize();
@@ -1889,11 +2445,11 @@ void Simulator::CompareAndSwapHelper(const Instruction* instr) {
       // Approximate store-release by issuing a full barrier before the store.
       __sync_synchronize();
     }
-    Memory::Write<T>(address, newvalue);
-    LogWrite(address, rt, GetPrintRegisterFormatForSize(element_size));
+    MemWrite<T>(address, newvalue);
+    LogWrite(rt, GetPrintRegisterFormatForSize(element_size), address);
   }
-  WriteRegister<T>(rs, data);
-  LogRead(address, rs, GetPrintRegisterFormatForSize(element_size));
+  WriteRegister<T>(rs, data, NoRegLog);
+  LogRead(rs, GetPrintRegisterFormatForSize(element_size), address);
 }
 
 
@@ -1904,7 +2460,7 @@ void Simulator::CompareAndSwapPairHelper(const Instruction* instr) {
   unsigned rt = instr->GetRt();
   unsigned rn = instr->GetRn();
 
-  VIXL_ASSERT((rs % 2 == 0) && (rs % 2 == 0));
+  VIXL_ASSERT((rs % 2 == 0) && (rt % 2 == 0));
 
   unsigned element_size = sizeof(T);
   uint64_t address = ReadRegister<uint64_t>(rn, Reg31IsStackPointer);
@@ -1925,8 +2481,8 @@ void Simulator::CompareAndSwapPairHelper(const Instruction* instr) {
   // associated with that location, even if the compare subsequently fails.
   local_monitor_.Clear();
 
-  T data_high = Memory::Read<T>(address);
-  T data_low = Memory::Read<T>(address2);
+  T data_low = MemRead<T>(address);
+  T data_high = MemRead<T>(address2);
 
   if (is_acquire) {
     // Approximate load-acquire by issuing a full barrier after the load.
@@ -1941,22 +2497,82 @@ void Simulator::CompareAndSwapPairHelper(const Instruction* instr) {
       __sync_synchronize();
     }
 
-    Memory::Write<T>(address, newvalue_high);
-    Memory::Write<T>(address2, newvalue_low);
+    MemWrite<T>(address, newvalue_low);
+    MemWrite<T>(address2, newvalue_high);
   }
 
-  WriteRegister<T>(rs + 1, data_high);
-  WriteRegister<T>(rs, data_low);
+  WriteRegister<T>(rs + 1, data_high, NoRegLog);
+  WriteRegister<T>(rs, data_low, NoRegLog);
 
-  LogRead(address, rs + 1, GetPrintRegisterFormatForSize(element_size));
-  LogRead(address2, rs, GetPrintRegisterFormatForSize(element_size));
+  PrintRegisterFormat format = GetPrintRegisterFormatForSize(element_size);
+  LogRead(rs, format, address);
+  LogRead(rs + 1, format, address2);
 
   if (same) {
-    LogWrite(address, rt + 1, GetPrintRegisterFormatForSize(element_size));
-    LogWrite(address2, rt, GetPrintRegisterFormatForSize(element_size));
+    LogWrite(rt, format, address);
+    LogWrite(rt + 1, format, address2);
+  }
+}
+
+bool Simulator::CanReadMemory(uintptr_t address, size_t size) {
+  // To simulate fault-tolerant loads, we need to know what host addresses we
+  // can access without generating a real fault. One way to do that is to
+  // attempt to `write()` the memory to a placeholder pipe[1]. This is more
+  // portable and less intrusive than using (global) signal handlers.
+  //
+  // [1]: https://stackoverflow.com/questions/7134590
+
+  size_t written = 0;
+  bool can_read = true;
+  // `write` will normally return after one invocation, but it is allowed to
+  // handle only part of the operation, so wrap it in a loop.
+  while (can_read && (written < size)) {
+    ssize_t result = write(placeholder_pipe_fd_[1],
+                           reinterpret_cast<void*>(address + written),
+                           size - written);
+    if (result > 0) {
+      written += result;
+    } else {
+      switch (result) {
+        case -EPERM:
+        case -EFAULT:
+          // The address range is not accessible.
+          // `write` is supposed to return -EFAULT in this case, but in practice
+          // it seems to return -EPERM, so we accept that too.
+          can_read = false;
+          break;
+        case -EINTR:
+          // The call was interrupted by a signal. Just try again.
+          break;
+        default:
+          // Any other error is fatal.
+          VIXL_ABORT();
+      }
+    }
+  }
+  // Drain the read side of the pipe. If we don't do this, we'll leak memory as
+  // the placeholder data is buffered. As before, we expect to drain the whole
+  // write in one invocation, but cannot guarantee that, so we wrap it in a
+  // loop. This function is primarily intended to implement SVE fault-tolerant
+  // loads, so the maximum Z register size is a good default buffer size.
+  char buffer[kZRegMaxSizeInBytes];
+  while (written > 0) {
+    ssize_t result = read(placeholder_pipe_fd_[0],
+                          reinterpret_cast<void*>(buffer),
+                          sizeof(buffer));
+    // `read` blocks, and returns 0 only at EOF. We should not hit EOF until
+    // we've read everything that was written, so treat 0 as an error.
+    if (result > 0) {
+      VIXL_ASSERT(static_cast<size_t>(result) <= written);
+      written -= result;
+    } else {
+      // For -EINTR, just try again. We can't handle any other error.
+      VIXL_CHECK(result == -EINTR);
+    }
   }
-}
 
+  return can_read;
+}
 
 void Simulator::PrintExclusiveAccessWarning() {
   if (print_exclusive_access_warning_) {
@@ -1971,7 +2587,6 @@ void Simulator::PrintExclusiveAccessWarning() {
   }
 }
 
-
 void Simulator::VisitLoadStoreExclusive(const Instruction* instr) {
   LoadStoreExclusive op =
       static_cast<LoadStoreExclusive>(instr->Mask(LoadStoreExclusiveMask));
@@ -2045,44 +2660,51 @@ void Simulator::VisitLoadStoreExclusive(const Instruction* instr) {
 
         // Use NoRegLog to suppress the register trace (LOG_REGS, LOG_FP_REGS).
         // We will print a more detailed log.
+        unsigned reg_size = 0;
         switch (op) {
           case LDXRB_w:
           case LDAXRB_w:
           case LDARB_w:
           case LDLARB:
-            WriteWRegister(rt, Memory::Read<uint8_t>(address), NoRegLog);
+            WriteWRegister(rt, MemRead<uint8_t>(address), NoRegLog);
+            reg_size = kWRegSizeInBytes;
             break;
           case LDXRH_w:
           case LDAXRH_w:
           case LDARH_w:
           case LDLARH:
-            WriteWRegister(rt, Memory::Read<uint16_t>(address), NoRegLog);
+            WriteWRegister(rt, MemRead<uint16_t>(address), NoRegLog);
+            reg_size = kWRegSizeInBytes;
             break;
           case LDXR_w:
           case LDAXR_w:
           case LDAR_w:
           case LDLAR_w:
-            WriteWRegister(rt, Memory::Read<uint32_t>(address), NoRegLog);
+            WriteWRegister(rt, MemRead<uint32_t>(address), NoRegLog);
+            reg_size = kWRegSizeInBytes;
             break;
           case LDXR_x:
           case LDAXR_x:
           case LDAR_x:
           case LDLAR_x:
-            WriteXRegister(rt, Memory::Read<uint64_t>(address), NoRegLog);
+            WriteXRegister(rt, MemRead<uint64_t>(address), NoRegLog);
+            reg_size = kXRegSizeInBytes;
             break;
           case LDXP_w:
           case LDAXP_w:
-            WriteWRegister(rt, Memory::Read<uint32_t>(address), NoRegLog);
+            WriteWRegister(rt, MemRead<uint32_t>(address), NoRegLog);
             WriteWRegister(rt2,
-                           Memory::Read<uint32_t>(address + element_size),
+                           MemRead<uint32_t>(address + element_size),
                            NoRegLog);
+            reg_size = kWRegSizeInBytes;
             break;
           case LDXP_x:
           case LDAXP_x:
-            WriteXRegister(rt, Memory::Read<uint64_t>(address), NoRegLog);
+            WriteXRegister(rt, MemRead<uint64_t>(address), NoRegLog);
             WriteXRegister(rt2,
-                           Memory::Read<uint64_t>(address + element_size),
+                           MemRead<uint64_t>(address + element_size),
                            NoRegLog);
+            reg_size = kXRegSizeInBytes;
             break;
           default:
             VIXL_UNREACHABLE();
@@ -2093,11 +2715,10 @@ void Simulator::VisitLoadStoreExclusive(const Instruction* instr) {
           __sync_synchronize();
         }
 
-        LogRead(address, rt, GetPrintRegisterFormatForSize(element_size));
+        PrintRegisterFormat format = GetPrintRegisterFormatForSize(reg_size);
+        LogExtendingRead(rt, format, element_size, address);
         if (is_pair) {
-          LogRead(address + element_size,
-                  rt2,
-                  GetPrintRegisterFormatForSize(element_size));
+          LogExtendingRead(rt2, format, element_size, address + element_size);
         }
       } else {
         if (is_acquire_release) {
@@ -2125,47 +2746,45 @@ void Simulator::VisitLoadStoreExclusive(const Instruction* instr) {
             case STLXRB_w:
             case STLRB_w:
             case STLLRB:
-              Memory::Write<uint8_t>(address, ReadWRegister(rt));
+              MemWrite<uint8_t>(address, ReadWRegister(rt));
               break;
             case STXRH_w:
             case STLXRH_w:
             case STLRH_w:
             case STLLRH:
-              Memory::Write<uint16_t>(address, ReadWRegister(rt));
+              MemWrite<uint16_t>(address, ReadWRegister(rt));
               break;
             case STXR_w:
             case STLXR_w:
             case STLR_w:
             case STLLR_w:
-              Memory::Write<uint32_t>(address, ReadWRegister(rt));
+              MemWrite<uint32_t>(address, ReadWRegister(rt));
               break;
             case STXR_x:
             case STLXR_x:
             case STLR_x:
             case STLLR_x:
-              Memory::Write<uint64_t>(address, ReadXRegister(rt));
+              MemWrite<uint64_t>(address, ReadXRegister(rt));
               break;
             case STXP_w:
             case STLXP_w:
-              Memory::Write<uint32_t>(address, ReadWRegister(rt));
-              Memory::Write<uint32_t>(address + element_size,
-                                      ReadWRegister(rt2));
+              MemWrite<uint32_t>(address, ReadWRegister(rt));
+              MemWrite<uint32_t>(address + element_size, ReadWRegister(rt2));
               break;
             case STXP_x:
             case STLXP_x:
-              Memory::Write<uint64_t>(address, ReadXRegister(rt));
-              Memory::Write<uint64_t>(address + element_size,
-                                      ReadXRegister(rt2));
+              MemWrite<uint64_t>(address, ReadXRegister(rt));
+              MemWrite<uint64_t>(address + element_size, ReadXRegister(rt2));
               break;
             default:
               VIXL_UNREACHABLE();
           }
 
-          LogWrite(address, rt, GetPrintRegisterFormatForSize(element_size));
+          PrintRegisterFormat format =
+              GetPrintRegisterFormatForSize(element_size);
+          LogWrite(rt, format, address);
           if (is_pair) {
-            LogWrite(address + element_size,
-                     rt2,
-                     GetPrintRegisterFormatForSize(element_size));
+            LogWrite(rt2, format, address + element_size);
           }
         }
       }
@@ -2188,7 +2807,7 @@ void Simulator::AtomicMemorySimpleHelper(const Instruction* instr) {
 
   T value = ReadRegister<T>(rs);
 
-  T data = Memory::Read<T>(address);
+  T data = MemRead<T>(address);
 
   if (is_acquire) {
     // Approximate load-acquire by issuing a full barrier after the load.
@@ -2229,11 +2848,12 @@ void Simulator::AtomicMemorySimpleHelper(const Instruction* instr) {
     __sync_synchronize();
   }
 
-  Memory::Write<T>(address, result);
+  MemWrite<T>(address, result);
   WriteRegister<T>(rt, data, NoRegLog);
 
-  LogRead(address, rt, GetPrintRegisterFormatForSize(element_size));
-  LogWrite(address, rs, GetPrintRegisterFormatForSize(element_size));
+  PrintRegisterFormat format = GetPrintRegisterFormatForSize(element_size);
+  LogRead(rt, format, address);
+  LogWrite(rs, format, address);
 }
 
 template <typename T>
@@ -2250,7 +2870,7 @@ void Simulator::AtomicMemorySwapHelper(const Instruction* instr) {
 
   CheckIsValidUnalignedAtomicAccess(rn, address, element_size);
 
-  T data = Memory::Read<T>(address);
+  T data = MemRead<T>(address);
   if (is_acquire) {
     // Approximate load-acquire by issuing a full barrier after the load.
     __sync_synchronize();
@@ -2260,12 +2880,13 @@ void Simulator::AtomicMemorySwapHelper(const Instruction* instr) {
     // Approximate store-release by issuing a full barrier before the store.
     __sync_synchronize();
   }
-  Memory::Write<T>(address, ReadRegister<T>(rs));
+  MemWrite<T>(address, ReadRegister<T>(rs));
 
   WriteRegister<T>(rt, data);
 
-  LogRead(address, rt, GetPrintRegisterFormat(element_size));
-  LogWrite(address, rs, GetPrintRegisterFormat(element_size));
+  PrintRegisterFormat format = GetPrintRegisterFormatForSize(element_size);
+  LogRead(rt, format, address);
+  LogWrite(rs, format, address);
 }
 
 template <typename T>
@@ -2278,12 +2899,12 @@ void Simulator::LoadAcquireRCpcHelper(const Instruction* instr) {
 
   CheckIsValidUnalignedAtomicAccess(rn, address, element_size);
 
-  WriteRegister<T>(rt, Memory::Read<T>(address));
+  WriteRegister<T>(rt, MemRead<T>(address));
 
   // Approximate load-acquire by issuing a full barrier after the load.
   __sync_synchronize();
 
-  LogRead(address, rt, GetPrintRegisterFormat(element_size));
+  LogRead(rt, GetPrintRegisterFormatForSize(element_size), address);
 }
 
 #define ATOMIC_MEMORY_SIMPLE_UINT_LIST(V) \
@@ -2399,28 +3020,28 @@ void Simulator::VisitLoadLiteral(const Instruction* instr) {
     // Use NoRegLog to suppress the register trace (LOG_REGS, LOG_VREGS), then
     // print a more detailed log.
     case LDR_w_lit:
-      WriteWRegister(rt, Memory::Read<uint32_t>(address), NoRegLog);
-      LogRead(address, rt, kPrintWReg);
+      WriteWRegister(rt, MemRead<uint32_t>(address), NoRegLog);
+      LogRead(rt, kPrintWReg, address);
       break;
     case LDR_x_lit:
-      WriteXRegister(rt, Memory::Read<uint64_t>(address), NoRegLog);
-      LogRead(address, rt, kPrintXReg);
+      WriteXRegister(rt, MemRead<uint64_t>(address), NoRegLog);
+      LogRead(rt, kPrintXReg, address);
       break;
     case LDR_s_lit:
-      WriteSRegister(rt, Memory::Read<float>(address), NoRegLog);
-      LogVRead(address, rt, kPrintSReg);
+      WriteSRegister(rt, MemRead<float>(address), NoRegLog);
+      LogVRead(rt, kPrintSRegFP, address);
       break;
     case LDR_d_lit:
-      WriteDRegister(rt, Memory::Read<double>(address), NoRegLog);
-      LogVRead(address, rt, kPrintDReg);
+      WriteDRegister(rt, MemRead<double>(address), NoRegLog);
+      LogVRead(rt, kPrintDRegFP, address);
       break;
     case LDR_q_lit:
-      WriteQRegister(rt, Memory::Read<qreg_t>(address), NoRegLog);
-      LogVRead(address, rt, kPrintReg1Q);
+      WriteQRegister(rt, MemRead<qreg_t>(address), NoRegLog);
+      LogVRead(rt, kPrintReg1Q, address);
       break;
     case LDRSW_x_lit:
-      WriteXRegister(rt, Memory::Read<int32_t>(address), NoRegLog);
-      LogRead(address, rt, kPrintWReg);
+      WriteXRegister(rt, MemRead<int32_t>(address), NoRegLog);
+      LogExtendingRead(rt, kPrintXReg, kWRegSizeInBytes, address);
       break;
 
     // Ignore prfm hint instructions.
@@ -2795,40 +3416,6 @@ void Simulator::VisitDataProcessing2Source(const Instruction* instr) {
 }
 
 
-// The algorithm used is adapted from the one described in section 8.2 of
-//   Hacker's Delight, by Henry S. Warren, Jr.
-template <typename T>
-static int64_t MultiplyHigh(T u, T v) {
-  uint64_t u0, v0, w0, u1, v1, w1, w2, t;
-  uint64_t sign_mask = UINT64_C(0x8000000000000000);
-  uint64_t sign_ext = 0;
-  if (std::numeric_limits<T>::is_signed) {
-    sign_ext = UINT64_C(0xffffffff00000000);
-  }
-
-  VIXL_ASSERT(sizeof(u) == sizeof(uint64_t));
-  VIXL_ASSERT(sizeof(u) == sizeof(u0));
-
-  u0 = u & 0xffffffff;
-  u1 = u >> 32 | (((u & sign_mask) != 0) ? sign_ext : 0);
-  v0 = v & 0xffffffff;
-  v1 = v >> 32 | (((v & sign_mask) != 0) ? sign_ext : 0);
-
-  w0 = u0 * v0;
-  t = u1 * v0 + (w0 >> 32);
-
-  w1 = t & 0xffffffff;
-  w2 = t >> 32 | (((t & sign_mask) != 0) ? sign_ext : 0);
-  w1 = u0 * v1 + w1;
-  w1 = w1 >> 32 | (((w1 & sign_mask) != 0) ? sign_ext : 0);
-
-  uint64_t value = u1 * v1 + w2 + w1;
-  int64_t result;
-  memcpy(&result, &value, sizeof(result));
-  return result;
-}
-
-
 void Simulator::VisitDataProcessing3Source(const Instruction* instr) {
   unsigned reg_size = instr->GetSixtyFourBits() ? kXRegSize : kWRegSize;
 
@@ -2864,12 +3451,13 @@ void Simulator::VisitDataProcessing3Source(const Instruction* instr) {
       result = ReadXRegister(instr->GetRa()) - (rn_u32 * rm_u32);
       break;
     case UMULH_x:
-      result = MultiplyHigh(ReadRegister<uint64_t>(instr->GetRn()),
-                            ReadRegister<uint64_t>(instr->GetRm()));
+      result =
+          internal::MultiplyHigh<64>(ReadRegister<uint64_t>(instr->GetRn()),
+                                     ReadRegister<uint64_t>(instr->GetRm()));
       break;
     case SMULH_x:
-      result = MultiplyHigh(ReadXRegister(instr->GetRn()),
-                            ReadXRegister(instr->GetRm()));
+      result = internal::MultiplyHigh<64>(ReadXRegister(instr->GetRn()),
+                                          ReadXRegister(instr->GetRm()));
       break;
     default:
       VIXL_UNIMPLEMENTED();
@@ -2936,9 +3524,10 @@ void Simulator::VisitExtract(const Instruction* instr) {
   unsigned reg_size = (instr->GetSixtyFourBits() == 1) ? kXRegSize : kWRegSize;
   uint64_t low_res =
       static_cast<uint64_t>(ReadRegister(reg_size, instr->GetRm())) >> lsb;
-  uint64_t high_res =
-      (lsb == 0) ? 0 : ReadRegister<uint64_t>(reg_size, instr->GetRn())
-                           << (reg_size - lsb);
+  uint64_t high_res = (lsb == 0)
+                          ? 0
+                          : ReadRegister<uint64_t>(reg_size, instr->GetRn())
+                                << (reg_size - lsb);
   WriteRegister(reg_size, instr->GetRd(), low_res | high_res);
 }
 
@@ -3837,9 +4426,9 @@ void Simulator::SysOp_W(int op, int64_t val) {
     case CVAP:
     case CVADP:
     case CIVAC: {
-      // Perform a dummy memory access to ensure that we have read access
+      // Perform a placeholder memory access to ensure that we have read access
       // to the specified address.
-      volatile uint8_t y = Memory::Read<uint8_t>(val);
+      volatile uint8_t y = MemRead<uint8_t>(val);
       USE(y);
       // TODO: Implement "case ZVA:".
       break;
@@ -3948,8 +4537,8 @@ void Simulator::VisitSystem(const Instruction* instr) {
             break;
           case RNDR:
           case RNDRRS: {
-            uint64_t high = jrand48(rndr_state_);
-            uint64_t low = jrand48(rndr_state_);
+            uint64_t high = jrand48(rand_state_);
+            uint64_t low = jrand48(rand_state_);
             uint64_t rand_num = (high << 32) | (low & 0xffffffff);
             WriteXRegister(instr->GetRt(), rand_num);
             // Simulate successful random number generation.
@@ -4530,10 +5119,10 @@ void Simulator::VisitNEON3Same(const Instruction* instr) {
         fminnm(vf, rd, rn, rm);
         break;
       case NEON_FMLA:
-        fmla(vf, rd, rn, rm);
+        fmla(vf, rd, rd, rn, rm);
         break;
       case NEON_FMLS:
-        fmls(vf, rd, rn, rm);
+        fmls(vf, rd, rd, rn, rm);
         break;
       case NEON_FMULX:
         fmulx(vf, rd, rn, rm);
@@ -4624,10 +5213,10 @@ void Simulator::VisitNEON3Same(const Instruction* instr) {
         cmptst(vf, rd, rn, rm);
         break;
       case NEON_MLS:
-        mls(vf, rd, rn, rm);
+        mls(vf, rd, rd, rn, rm);
         break;
       case NEON_MLA:
-        mla(vf, rd, rn, rm);
+        mla(vf, rd, rd, rn, rm);
         break;
       case NEON_MUL:
         mul(vf, rd, rn, rm);
@@ -4754,13 +5343,11 @@ void Simulator::VisitNEON3SameFP16(const Instruction* instr) {
     B(vf, rd, rn, rm); \
     break;
     SIM_FUNC(FMAXNM, fmaxnm);
-    SIM_FUNC(FMLA, fmla);
     SIM_FUNC(FADD, fadd);
     SIM_FUNC(FMULX, fmulx);
     SIM_FUNC(FMAX, fmax);
     SIM_FUNC(FRECPS, frecps);
     SIM_FUNC(FMINNM, fminnm);
-    SIM_FUNC(FMLS, fmls);
     SIM_FUNC(FSUB, fsub);
     SIM_FUNC(FMIN, fmin);
     SIM_FUNC(FRSQRTS, frsqrts);
@@ -4773,6 +5360,12 @@ void Simulator::VisitNEON3SameFP16(const Instruction* instr) {
     SIM_FUNC(FABD, fabd);
     SIM_FUNC(FMINP, fminp);
 #undef SIM_FUNC
+    case NEON_FMLA_H:
+      fmla(vf, rd, rd, rn, rm);
+      break;
+    case NEON_FMLS_H:
+      fmls(vf, rd, rd, rn, rm);
+      break;
     case NEON_FCMEQ_H:
       fcmp(vf, rd, rn, rm, eq);
       break;
@@ -4803,7 +5396,7 @@ void Simulator::VisitNEON3SameExtra(const Instruction* instr) {
   VectorFormat vf = nfd.GetVectorFormat();
   if (instr->Mask(NEON3SameExtraFCMLAMask) == NEON_FCMLA) {
     rot = instr->GetImmRotFcmlaVec();
-    fcmla(vf, rd, rn, rm, rot);
+    fcmla(vf, rd, rn, rm, rd, rot);
   } else if (instr->Mask(NEON3SameExtraFCADDMask) == NEON_FCADD) {
     rot = instr->GetImmRotFcadd();
     fcadd(vf, rd, rn, rm, rot);
@@ -5347,7 +5940,8 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
     reg[i] = (instr->GetRt() + i) % kNumberOfVRegisters;
     addr[i] = addr_base + (i * reg_size);
   }
-  int count = 1;
+  int struct_parts = 1;
+  int reg_count = 1;
   bool log_read = true;
 
   // Bit 23 determines whether this is an offset or post-index addressing mode.
@@ -5363,17 +5957,17 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
     case NEON_LD1_4v:
     case NEON_LD1_4v_post:
       ld1(vf, ReadVRegister(reg[3]), addr[3]);
-      count++;
+      reg_count++;
       VIXL_FALLTHROUGH();
     case NEON_LD1_3v:
     case NEON_LD1_3v_post:
       ld1(vf, ReadVRegister(reg[2]), addr[2]);
-      count++;
+      reg_count++;
       VIXL_FALLTHROUGH();
     case NEON_LD1_2v:
     case NEON_LD1_2v_post:
       ld1(vf, ReadVRegister(reg[1]), addr[1]);
-      count++;
+      reg_count++;
       VIXL_FALLTHROUGH();
     case NEON_LD1_1v:
     case NEON_LD1_1v_post:
@@ -5382,17 +5976,17 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
     case NEON_ST1_4v:
     case NEON_ST1_4v_post:
       st1(vf, ReadVRegister(reg[3]), addr[3]);
-      count++;
+      reg_count++;
       VIXL_FALLTHROUGH();
     case NEON_ST1_3v:
     case NEON_ST1_3v_post:
       st1(vf, ReadVRegister(reg[2]), addr[2]);
-      count++;
+      reg_count++;
       VIXL_FALLTHROUGH();
     case NEON_ST1_2v:
     case NEON_ST1_2v_post:
       st1(vf, ReadVRegister(reg[1]), addr[1]);
-      count++;
+      reg_count++;
       VIXL_FALLTHROUGH();
     case NEON_ST1_1v:
     case NEON_ST1_1v_post:
@@ -5402,12 +5996,14 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
     case NEON_LD2_post:
     case NEON_LD2:
       ld2(vf, ReadVRegister(reg[0]), ReadVRegister(reg[1]), addr[0]);
-      count = 2;
+      struct_parts = 2;
+      reg_count = 2;
       break;
     case NEON_ST2:
     case NEON_ST2_post:
       st2(vf, ReadVRegister(reg[0]), ReadVRegister(reg[1]), addr[0]);
-      count = 2;
+      struct_parts = 2;
+      reg_count = 2;
       log_read = false;
       break;
     case NEON_LD3_post:
@@ -5417,7 +6013,8 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
           ReadVRegister(reg[1]),
           ReadVRegister(reg[2]),
           addr[0]);
-      count = 3;
+      struct_parts = 3;
+      reg_count = 3;
       break;
     case NEON_ST3:
     case NEON_ST3_post:
@@ -5426,7 +6023,8 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
           ReadVRegister(reg[1]),
           ReadVRegister(reg[2]),
           addr[0]);
-      count = 3;
+      struct_parts = 3;
+      reg_count = 3;
       log_read = false;
       break;
     case NEON_ST4:
@@ -5437,7 +6035,8 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
           ReadVRegister(reg[2]),
           ReadVRegister(reg[3]),
           addr[0]);
-      count = 4;
+      struct_parts = 4;
+      reg_count = 4;
       log_read = false;
       break;
     case NEON_LD4_post:
@@ -5448,22 +6047,31 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
           ReadVRegister(reg[2]),
           ReadVRegister(reg[3]),
           addr[0]);
-      count = 4;
+      struct_parts = 4;
+      reg_count = 4;
       break;
     default:
       VIXL_UNIMPLEMENTED();
   }
 
-  // Explicitly log the register update whilst we have type information.
-  for (int i = 0; i < count; i++) {
-    // For de-interleaving loads, only print the base address.
-    int lane_size = LaneSizeInBytesFromFormat(vf);
-    PrintRegisterFormat format = GetPrintRegisterFormatTryFP(
-        GetPrintRegisterFormatForSize(reg_size, lane_size));
+  bool do_trace = log_read ? ShouldTraceVRegs() : ShouldTraceWrites();
+  if (do_trace) {
+    PrintRegisterFormat print_format =
+        GetPrintRegisterFormatTryFP(GetPrintRegisterFormat(vf));
+    const char* op;
     if (log_read) {
-      LogVRead(addr_base, reg[i], format);
+      op = "<-";
     } else {
-      LogVWrite(addr_base, reg[i], format);
+      op = "->";
+      // Stores don't represent a change to the source register's value, so only
+      // print the relevant part of the value.
+      print_format = GetPrintRegPartial(print_format);
+    }
+
+    VIXL_ASSERT((struct_parts == reg_count) || (struct_parts == 1));
+    for (int s = reg_count - struct_parts; s >= 0; s -= struct_parts) {
+      uintptr_t address = addr_base + (s * RegisterSizeInBytesFromFormat(vf));
+      PrintVStructAccess(reg[s], struct_parts, print_format, op, address);
     }
   }
 
@@ -5471,7 +6079,7 @@ void Simulator::NEONLoadStoreMultiStructHelper(const Instruction* instr,
     int rm = instr->GetRm();
     // The immediate post index addressing mode is indicated by rm = 31.
     // The immediate is implied by the number of vector registers used.
-    addr_base += (rm == 31) ? RegisterSizeInBytesFromFormat(vf) * count
+    addr_base += (rm == 31) ? (RegisterSizeInBytesFromFormat(vf) * reg_count)
                             : ReadXRegister(rm);
     WriteXRegister(instr->GetRn(), addr_base);
   } else {
@@ -5507,6 +6115,8 @@ void Simulator::NEONLoadStoreSingleStructHelper(const Instruction* instr,
   // and PostIndex addressing.
   bool do_load = false;
 
+  bool replicating = false;
+
   NEONFormatDecoder nfd(instr, NEONFormatDecoder::LoadStoreFormatMap());
   VectorFormat vf_t = nfd.GetVectorFormat();
 
@@ -5581,99 +6191,67 @@ void Simulator::NEONLoadStoreSingleStructHelper(const Instruction* instr,
     }
 
     case NEON_LD1R:
-    case NEON_LD1R_post: {
-      vf = vf_t;
-      ld1r(vf, ReadVRegister(rt), addr);
-      do_load = true;
-      break;
-    }
-
+    case NEON_LD1R_post:
     case NEON_LD2R:
-    case NEON_LD2R_post: {
-      vf = vf_t;
-      int rt2 = (rt + 1) % kNumberOfVRegisters;
-      ld2r(vf, ReadVRegister(rt), ReadVRegister(rt2), addr);
-      do_load = true;
-      break;
-    }
-
+    case NEON_LD2R_post:
     case NEON_LD3R:
-    case NEON_LD3R_post: {
-      vf = vf_t;
-      int rt2 = (rt + 1) % kNumberOfVRegisters;
-      int rt3 = (rt2 + 1) % kNumberOfVRegisters;
-      ld3r(vf, ReadVRegister(rt), ReadVRegister(rt2), ReadVRegister(rt3), addr);
-      do_load = true;
-      break;
-    }
-
+    case NEON_LD3R_post:
     case NEON_LD4R:
-    case NEON_LD4R_post: {
+    case NEON_LD4R_post:
       vf = vf_t;
-      int rt2 = (rt + 1) % kNumberOfVRegisters;
-      int rt3 = (rt2 + 1) % kNumberOfVRegisters;
-      int rt4 = (rt3 + 1) % kNumberOfVRegisters;
-      ld4r(vf,
-           ReadVRegister(rt),
-           ReadVRegister(rt2),
-           ReadVRegister(rt3),
-           ReadVRegister(rt4),
-           addr);
       do_load = true;
+      replicating = true;
       break;
-    }
+
     default:
       VIXL_UNIMPLEMENTED();
   }
 
-  PrintRegisterFormat print_format =
-      GetPrintRegisterFormatTryFP(GetPrintRegisterFormat(vf));
-  // Make sure that the print_format only includes a single lane.
-  print_format =
-      static_cast<PrintRegisterFormat>(print_format & ~kPrintRegAsVectorMask);
-
-  int esize = LaneSizeInBytesFromFormat(vf);
   int index_shift = LaneSizeInBytesLog2FromFormat(vf);
   int lane = instr->GetNEONLSIndex(index_shift);
-  int scale = 0;
+  int reg_count = 0;
   int rt2 = (rt + 1) % kNumberOfVRegisters;
   int rt3 = (rt2 + 1) % kNumberOfVRegisters;
   int rt4 = (rt3 + 1) % kNumberOfVRegisters;
   switch (instr->Mask(NEONLoadStoreSingleLenMask)) {
     case NEONLoadStoreSingle1:
-      scale = 1;
-      if (do_load) {
+      reg_count = 1;
+      if (replicating) {
+        VIXL_ASSERT(do_load);
+        ld1r(vf, ReadVRegister(rt), addr);
+      } else if (do_load) {
         ld1(vf, ReadVRegister(rt), lane, addr);
-        LogVRead(addr, rt, print_format, lane);
       } else {
         st1(vf, ReadVRegister(rt), lane, addr);
-        LogVWrite(addr, rt, print_format, lane);
       }
       break;
     case NEONLoadStoreSingle2:
-      scale = 2;
-      if (do_load) {
+      reg_count = 2;
+      if (replicating) {
+        VIXL_ASSERT(do_load);
+        ld2r(vf, ReadVRegister(rt), ReadVRegister(rt2), addr);
+      } else if (do_load) {
         ld2(vf, ReadVRegister(rt), ReadVRegister(rt2), lane, addr);
-        LogVRead(addr, rt, print_format, lane);
-        LogVRead(addr + esize, rt2, print_format, lane);
       } else {
         st2(vf, ReadVRegister(rt), ReadVRegister(rt2), lane, addr);
-        LogVWrite(addr, rt, print_format, lane);
-        LogVWrite(addr + esize, rt2, print_format, lane);
       }
       break;
     case NEONLoadStoreSingle3:
-      scale = 3;
-      if (do_load) {
+      reg_count = 3;
+      if (replicating) {
+        VIXL_ASSERT(do_load);
+        ld3r(vf,
+             ReadVRegister(rt),
+             ReadVRegister(rt2),
+             ReadVRegister(rt3),
+             addr);
+      } else if (do_load) {
         ld3(vf,
             ReadVRegister(rt),
             ReadVRegister(rt2),
             ReadVRegister(rt3),
             lane,
             addr);
-        LogVRead(addr, rt, print_format, lane);
-        LogVRead(addr + esize, rt2, print_format, lane);
-        LogVRead(addr + (2 * esize), rt3, print_format, lane);
       } else {
         st3(vf,
             ReadVRegister(rt),
@@ -5681,14 +6259,19 @@ void Simulator::NEONLoadStoreSingleStructHelper(const Instruction* instr,
             ReadVRegister(rt3),
             lane,
             addr);
-        LogVWrite(addr, rt, print_format, lane);
-        LogVWrite(addr + esize, rt2, print_format, lane);
-        LogVWrite(addr + (2 * esize), rt3, print_format, lane);
       }
       break;
     case NEONLoadStoreSingle4:
-      scale = 4;
-      if (do_load) {
+      reg_count = 4;
+      if (replicating) {
+        VIXL_ASSERT(do_load);
+        ld4r(vf,
+             ReadVRegister(rt),
+             ReadVRegister(rt2),
+             ReadVRegister(rt3),
+             ReadVRegister(rt4),
+             addr);
+      } else if (do_load) {
         ld4(vf,
             ReadVRegister(rt),
             ReadVRegister(rt2),
@@ -5696,10 +6279,6 @@ void Simulator::NEONLoadStoreSingleStructHelper(const Instruction* instr,
             ReadVRegister(rt4),
             lane,
             addr);
-        LogVRead(addr, rt, print_format, lane);
-        LogVRead(addr + esize, rt2, print_format, lane);
-        LogVRead(addr + (2 * esize), rt3, print_format, lane);
-        LogVRead(addr + (3 * esize), rt4, print_format, lane);
       } else {
         st4(vf,
             ReadVRegister(rt),
@@ -5708,22 +6287,38 @@ void Simulator::NEONLoadStoreSingleStructHelper(const Instruction* instr,
             ReadVRegister(rt4),
             lane,
             addr);
-        LogVWrite(addr, rt, print_format, lane);
-        LogVWrite(addr + esize, rt2, print_format, lane);
-        LogVWrite(addr + (2 * esize), rt3, print_format, lane);
-        LogVWrite(addr + (3 * esize), rt4, print_format, lane);
       }
       break;
     default:
       VIXL_UNIMPLEMENTED();
   }
 
+  // Trace registers and/or memory writes.
+  PrintRegisterFormat print_format =
+      GetPrintRegisterFormatTryFP(GetPrintRegisterFormat(vf));
+  if (do_load) {
+    if (ShouldTraceVRegs()) {
+      if (replicating) {
+        PrintVReplicatingStructAccess(rt, reg_count, print_format, "<-", addr);
+      } else {
+        PrintVSingleStructAccess(rt, reg_count, lane, print_format, "<-", addr);
+      }
+    }
+  } else {
+    if (ShouldTraceWrites()) {
+      // Stores don't represent a change to the source register's value, so only
+      // print the relevant part of the value.
+      print_format = GetPrintRegPartial(print_format);
+      PrintVSingleStructAccess(rt, reg_count, lane, print_format, "->", addr);
+    }
+  }
+
   if (addr_mode == PostIndex) {
     int rm = instr->GetRm();
     int lane_size = LaneSizeInBytesFromFormat(vf);
     WriteXRegister(instr->GetRn(),
-                   addr +
-                       ((rm == 31) ? (scale * lane_size) : ReadXRegister(rm)));
+                   addr + ((rm == 31) ? (reg_count * lane_size)
+                                      : ReadXRegister(rm)));
   }
 }
 
@@ -6421,10 +7016,10 @@ void Simulator::VisitNEONScalarShiftImmediate(const Instruction* instr) {
   NEONFormatDecoder nfd(instr, &map);
   VectorFormat vf = nfd.GetVectorFormat();
 
-  int highestSetBit = HighestSetBitPosition(instr->GetImmNEONImmh());
-  int immhimmb = instr->GetImmNEONImmhImmb();
-  int right_shift = (16 << highestSetBit) - immhimmb;
-  int left_shift = immhimmb - (8 << highestSetBit);
+  int highest_set_bit = HighestSetBitPosition(instr->GetImmNEONImmh());
+  int immh_immb = instr->GetImmNEONImmhImmb();
+  int right_shift = (16 << highest_set_bit) - immh_immb;
+  int left_shift = immh_immb - (8 << highest_set_bit);
   switch (instr->Mask(NEONScalarShiftImmediateMask)) {
     case NEON_SHL_scalar:
       shl(vf, rd, rn, left_shift);
@@ -6529,10 +7124,10 @@ void Simulator::VisitNEONShiftImmediate(const Instruction* instr) {
        {NF_UNDEF, NF_8H, NF_4S, NF_4S, NF_2D, NF_2D, NF_2D, NF_2D}};
   VectorFormat vf_l = nfd.GetVectorFormat(&map_l);
 
-  int highestSetBit = HighestSetBitPosition(instr->GetImmNEONImmh());
-  int immhimmb = instr->GetImmNEONImmhImmb();
-  int right_shift = (16 << highestSetBit) - immhimmb;
-  int left_shift = immhimmb - (8 << highestSetBit);
+  int highest_set_bit = HighestSetBitPosition(instr->GetImmNEONImmh());
+  int immh_immb = instr->GetImmNEONImmhImmb();
+  int right_shift = (16 << highest_set_bit) - immh_immb;
+  int left_shift = immh_immb - (8 << highest_set_bit);
 
   switch (instr->Mask(NEONShiftImmediateMask)) {
     case NEON_SHL:
@@ -6741,6 +7336,4356 @@ void Simulator::VisitNEONPerm(const Instruction* instr) {
   }
 }
 
+void Simulator::VisitSVEAddressGeneration(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+  SimVRegister temp;
+
+  VectorFormat vform = kFormatVnD;
+  mov(vform, temp, zm);
+
+  switch (instr->Mask(SVEAddressGenerationMask)) {
+    case ADR_z_az_d_s32_scaled:
+      sxt(vform, temp, temp, kSRegSize);
+      break;
+    case ADR_z_az_d_u32_scaled:
+      uxt(vform, temp, temp, kSRegSize);
+      break;
+    case ADR_z_az_s_same_scaled:
+      vform = kFormatVnS;
+      break;
+    case ADR_z_az_d_same_scaled:
+      // Nothing to do.
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  int shift_amount = instr->ExtractBits(11, 10);
+  shl(vform, temp, temp, shift_amount);
+  add(vform, zd, zn, temp);
+}
+
+void Simulator::VisitSVEBitwiseLogicalWithImm_Unpredicated(
+    const Instruction* instr) {
+  Instr op = instr->Mask(SVEBitwiseLogicalWithImm_UnpredicatedMask);
+  switch (op) {
+    case AND_z_zi:
+    case EOR_z_zi:
+    case ORR_z_zi: {
+      int lane_size = instr->GetSVEBitwiseImmLaneSizeInBytesLog2();
+      uint64_t imm = instr->GetSVEImmLogical();
+      // Valid immediate is a non-zero bits
+      VIXL_ASSERT(imm != 0);
+      SVEBitwiseImmHelper(static_cast<SVEBitwiseLogicalWithImm_UnpredicatedOp>(
+                              op),
+                          SVEFormatFromLaneSizeInBytesLog2(lane_size),
+                          ReadVRegister(instr->GetRd()),
+                          imm);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEBroadcastBitmaskImm(const Instruction* instr) {
+  switch (instr->Mask(SVEBroadcastBitmaskImmMask)) {
+    case DUPM_z_i: {
+      /* DUPM uses the same lane size and immediate encoding as bitwise logical
+       * immediate instructions. */
+      int lane_size = instr->GetSVEBitwiseImmLaneSizeInBytesLog2();
+      uint64_t imm = instr->GetSVEImmLogical();
+      VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size);
+      dup_immediate(vform, ReadVRegister(instr->GetRd()), imm);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEBitwiseLogicalUnpredicated(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+  Instr op = instr->Mask(SVEBitwiseLogicalUnpredicatedMask);
+
+  LogicalOp logical_op;
+  switch (op) {
+    case AND_z_zz:
+      logical_op = AND;
+      break;
+    case BIC_z_zz:
+      logical_op = BIC;
+      break;
+    case EOR_z_zz:
+      logical_op = EOR;
+      break;
+    case ORR_z_zz:
+      logical_op = ORR;
+      break;
+    default:
+      logical_op = LogicalOpMask;
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  // Lane size of registers is irrelevant to the bitwise operations, so perform
+  // the operation on D-sized lanes.
+  SVEBitwiseLogicalUnpredicatedHelper(logical_op, kFormatVnD, zd, zn, zm);
+}
+
+void Simulator::VisitSVEBitwiseShiftByImm_Predicated(const Instruction* instr) {
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  SimVRegister scratch;
+  SimVRegister result;
+
+  bool for_division = false;
+  Shift shift_op = NO_SHIFT;
+  switch (instr->Mask(SVEBitwiseShiftByImm_PredicatedMask)) {
+    case ASRD_z_p_zi:
+      shift_op = ASR;
+      for_division = true;
+      break;
+    case ASR_z_p_zi:
+      shift_op = ASR;
+      break;
+    case LSL_z_p_zi:
+      shift_op = LSL;
+      break;
+    case LSR_z_p_zi:
+      shift_op = LSR;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  std::pair<int, int> shift_and_lane_size =
+      instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ true);
+  unsigned lane_size = shift_and_lane_size.second;
+  VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size);
+  int shift_dist = shift_and_lane_size.first;
+
+  if ((shift_op == ASR) && for_division) {
+    asrd(vform, result, zdn, shift_dist);
+  } else {
+    if (shift_op == LSL) {
+      // Shift distance is computed differently for LSL. Convert the result.
+      shift_dist = (8 << lane_size) - shift_dist;
+    }
+    dup_immediate(vform, scratch, shift_dist);
+    SVEBitwiseShiftHelper(shift_op, vform, result, zdn, scratch, false);
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEBitwiseShiftByVector_Predicated(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  SimVRegister result;
+  SimVRegister shiftand;  // Vector to be shifted.
+  SimVRegister shiftor;   // Vector shift amount.
+
+  Shift shift_op = ASR;
+  mov(vform, shiftand, zdn);
+  mov(vform, shiftor, zm);
+
+  switch (instr->Mask(SVEBitwiseShiftByVector_PredicatedMask)) {
+    case ASRR_z_p_zz:
+      mov(vform, shiftand, zm);
+      mov(vform, shiftor, zdn);
+      VIXL_FALLTHROUGH();
+    case ASR_z_p_zz:
+      break;
+    case LSLR_z_p_zz:
+      mov(vform, shiftand, zm);
+      mov(vform, shiftor, zdn);
+      VIXL_FALLTHROUGH();
+    case LSL_z_p_zz:
+      shift_op = LSL;
+      break;
+    case LSRR_z_p_zz:
+      mov(vform, shiftand, zm);
+      mov(vform, shiftor, zdn);
+      VIXL_FALLTHROUGH();
+    case LSR_z_p_zz:
+      shift_op = LSR;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  SVEBitwiseShiftHelper(shift_op,
+                        vform,
+                        result,
+                        shiftand,
+                        shiftor,
+                        /* is_wide_elements = */ false);
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEBitwiseShiftByWideElements_Predicated(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  SimVRegister result;
+  Shift shift_op = ASR;
+
+  switch (instr->Mask(SVEBitwiseShiftByWideElements_PredicatedMask)) {
+    case ASR_z_p_zw:
+      break;
+    case LSL_z_p_zw:
+      shift_op = LSL;
+      break;
+    case LSR_z_p_zw:
+      shift_op = LSR;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  SVEBitwiseShiftHelper(shift_op,
+                        vform,
+                        result,
+                        zdn,
+                        zm,
+                        /* is_wide_elements = */ true);
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEBitwiseShiftUnpredicated(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+
+  Shift shift_op;
+  switch (instr->Mask(SVEBitwiseShiftUnpredicatedMask)) {
+    case ASR_z_zi:
+    case ASR_z_zw:
+      shift_op = ASR;
+      break;
+    case LSL_z_zi:
+    case LSL_z_zw:
+      shift_op = LSL;
+      break;
+    case LSR_z_zi:
+    case LSR_z_zw:
+      shift_op = LSR;
+      break;
+    default:
+      shift_op = NO_SHIFT;
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  switch (instr->Mask(SVEBitwiseShiftUnpredicatedMask)) {
+    case ASR_z_zi:
+    case LSL_z_zi:
+    case LSR_z_zi: {
+      SimVRegister scratch;
+      std::pair<int, int> shift_and_lane_size =
+          instr->GetSVEImmShiftAndLaneSizeLog2(/* is_predicated = */ false);
+      unsigned lane_size = shift_and_lane_size.second;
+      VIXL_ASSERT(lane_size <= kDRegSizeInBytesLog2);
+      VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(lane_size);
+      int shift_dist = shift_and_lane_size.first;
+      if (shift_op == LSL) {
+        // Shift distance is computed differently for LSL. Convert the result.
+        shift_dist = (8 << lane_size) - shift_dist;
+      }
+      dup_immediate(vform, scratch, shift_dist);
+      SVEBitwiseShiftHelper(shift_op, vform, zd, zn, scratch, false);
+      break;
+    }
+    case ASR_z_zw:
+    case LSL_z_zw:
+    case LSR_z_zw:
+      SVEBitwiseShiftHelper(shift_op,
+                            instr->GetSVEVectorFormat(),
+                            zd,
+                            zn,
+                            ReadVRegister(instr->GetRm()),
+                            true);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEIncDecRegisterByElementCount(const Instruction* instr) {
+  // Although the instructions have a separate encoding class, the lane size is
+  // encoded in the same way as most other SVE instructions.
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  int pattern = instr->GetImmSVEPredicateConstraint();
+  int count = GetPredicateConstraintLaneCount(vform, pattern);
+  int multiplier = instr->ExtractBits(19, 16) + 1;
+
+  switch (instr->Mask(SVEIncDecRegisterByElementCountMask)) {
+    case DECB_r_rs:
+    case DECD_r_rs:
+    case DECH_r_rs:
+    case DECW_r_rs:
+      count = -count;
+      break;
+    case INCB_r_rs:
+    case INCD_r_rs:
+    case INCH_r_rs:
+    case INCW_r_rs:
+      // Nothing to do.
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      return;
+  }
+
+  WriteXRegister(instr->GetRd(),
+                 IncDecN(ReadXRegister(instr->GetRd()),
+                         count * multiplier,
+                         kXRegSize));
+}
+
+void Simulator::VisitSVEIncDecVectorByElementCount(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  if (LaneSizeInBitsFromFormat(vform) == kBRegSize) {
+    VIXL_UNIMPLEMENTED();
+  }
+
+  int pattern = instr->GetImmSVEPredicateConstraint();
+  int count = GetPredicateConstraintLaneCount(vform, pattern);
+  int multiplier = instr->ExtractBits(19, 16) + 1;
+
+  switch (instr->Mask(SVEIncDecVectorByElementCountMask)) {
+    case DECD_z_zs:
+    case DECH_z_zs:
+    case DECW_z_zs:
+      count = -count;
+      break;
+    case INCD_z_zs:
+    case INCH_z_zs:
+    case INCW_z_zs:
+      // Nothing to do.
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister scratch;
+  dup_immediate(vform,
+                scratch,
+                IncDecN(0,
+                        count * multiplier,
+                        LaneSizeInBitsFromFormat(vform)));
+  add(vform, zd, zd, scratch);
+}
+
+void Simulator::VisitSVESaturatingIncDecRegisterByElementCount(
+    const Instruction* instr) {
+  // Although the instructions have a separate encoding class, the lane size is
+  // encoded in the same way as most other SVE instructions.
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  int pattern = instr->GetImmSVEPredicateConstraint();
+  int count = GetPredicateConstraintLaneCount(vform, pattern);
+  int multiplier = instr->ExtractBits(19, 16) + 1;
+
+  unsigned width = kXRegSize;
+  bool is_signed = false;
+
+  switch (instr->Mask(SVESaturatingIncDecRegisterByElementCountMask)) {
+    case SQDECB_r_rs_sx:
+    case SQDECD_r_rs_sx:
+    case SQDECH_r_rs_sx:
+    case SQDECW_r_rs_sx:
+      width = kWRegSize;
+      VIXL_FALLTHROUGH();
+    case SQDECB_r_rs_x:
+    case SQDECD_r_rs_x:
+    case SQDECH_r_rs_x:
+    case SQDECW_r_rs_x:
+      is_signed = true;
+      count = -count;
+      break;
+    case SQINCB_r_rs_sx:
+    case SQINCD_r_rs_sx:
+    case SQINCH_r_rs_sx:
+    case SQINCW_r_rs_sx:
+      width = kWRegSize;
+      VIXL_FALLTHROUGH();
+    case SQINCB_r_rs_x:
+    case SQINCD_r_rs_x:
+    case SQINCH_r_rs_x:
+    case SQINCW_r_rs_x:
+      is_signed = true;
+      break;
+    case UQDECB_r_rs_uw:
+    case UQDECD_r_rs_uw:
+    case UQDECH_r_rs_uw:
+    case UQDECW_r_rs_uw:
+      width = kWRegSize;
+      VIXL_FALLTHROUGH();
+    case UQDECB_r_rs_x:
+    case UQDECD_r_rs_x:
+    case UQDECH_r_rs_x:
+    case UQDECW_r_rs_x:
+      count = -count;
+      break;
+    case UQINCB_r_rs_uw:
+    case UQINCD_r_rs_uw:
+    case UQINCH_r_rs_uw:
+    case UQINCW_r_rs_uw:
+      width = kWRegSize;
+      VIXL_FALLTHROUGH();
+    case UQINCB_r_rs_x:
+    case UQINCD_r_rs_x:
+    case UQINCH_r_rs_x:
+    case UQINCW_r_rs_x:
+      // Nothing to do.
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  WriteXRegister(instr->GetRd(),
+                 IncDecN(ReadXRegister(instr->GetRd()),
+                         count * multiplier,
+                         width,
+                         true,
+                         is_signed));
+}
+
+void Simulator::VisitSVESaturatingIncDecVectorByElementCount(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  if (LaneSizeInBitsFromFormat(vform) == kBRegSize) {
+    VIXL_UNIMPLEMENTED();
+  }
+
+  int pattern = instr->GetImmSVEPredicateConstraint();
+  int count = GetPredicateConstraintLaneCount(vform, pattern);
+  int multiplier = instr->ExtractBits(19, 16) + 1;
+
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister scratch;
+  dup_immediate(vform,
+                scratch,
+                IncDecN(0,
+                        count * multiplier,
+                        LaneSizeInBitsFromFormat(vform)));
+
+  switch (instr->Mask(SVESaturatingIncDecVectorByElementCountMask)) {
+    case SQDECD_z_zs:
+    case SQDECH_z_zs:
+    case SQDECW_z_zs:
+      sub(vform, zd, zd, scratch).SignedSaturate(vform);
+      break;
+    case SQINCD_z_zs:
+    case SQINCH_z_zs:
+    case SQINCW_z_zs:
+      add(vform, zd, zd, scratch).SignedSaturate(vform);
+      break;
+    case UQDECD_z_zs:
+    case UQDECH_z_zs:
+    case UQDECW_z_zs:
+      sub(vform, zd, zd, scratch).UnsignedSaturate(vform);
+      break;
+    case UQINCD_z_zs:
+    case UQINCH_z_zs:
+    case UQINCW_z_zs:
+      add(vform, zd, zd, scratch).UnsignedSaturate(vform);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEElementCount(const Instruction* instr) {
+  switch (instr->Mask(SVEElementCountMask)) {
+    case CNTB_r_s:
+    case CNTD_r_s:
+    case CNTH_r_s:
+    case CNTW_r_s:
+      // All handled below.
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  // Although the instructions are separated, the lane size is encoded in the
+  // same way as most other SVE instructions.
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  int pattern = instr->GetImmSVEPredicateConstraint();
+  int count = GetPredicateConstraintLaneCount(vform, pattern);
+  int multiplier = instr->ExtractBits(19, 16) + 1;
+  WriteXRegister(instr->GetRd(), count * multiplier);
+}
+
+void Simulator::VisitSVEFPAccumulatingReduction(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& vdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  switch (instr->Mask(SVEFPAccumulatingReductionMask)) {
+    case FADDA_v_p_z:
+      fadda(vform, vdn, pg, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEFPArithmetic_Predicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  SimVRegister result;
+
+  switch (instr->Mask(SVEFPArithmetic_PredicatedMask)) {
+    case FABD_z_p_zz:
+      fabd(vform, result, zdn, zm);
+      break;
+    case FADD_z_p_zz:
+      fadd(vform, result, zdn, zm);
+      break;
+    case FDIVR_z_p_zz:
+      fdiv(vform, result, zm, zdn);
+      break;
+    case FDIV_z_p_zz:
+      fdiv(vform, result, zdn, zm);
+      break;
+    case FMAXNM_z_p_zz:
+      fmaxnm(vform, result, zdn, zm);
+      break;
+    case FMAX_z_p_zz:
+      fmax(vform, result, zdn, zm);
+      break;
+    case FMINNM_z_p_zz:
+      fminnm(vform, result, zdn, zm);
+      break;
+    case FMIN_z_p_zz:
+      fmin(vform, result, zdn, zm);
+      break;
+    case FMULX_z_p_zz:
+      fmulx(vform, result, zdn, zm);
+      break;
+    case FMUL_z_p_zz:
+      fmul(vform, result, zdn, zm);
+      break;
+    case FSCALE_z_p_zz:
+      fscale(vform, result, zdn, zm);
+      break;
+    case FSUBR_z_p_zz:
+      fsub(vform, result, zm, zdn);
+      break;
+    case FSUB_z_p_zz:
+      fsub(vform, result, zdn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEFPArithmeticWithImm_Predicated(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  if (LaneSizeInBitsFromFormat(vform) == kBRegSize) {
+    VIXL_UNIMPLEMENTED();
+  }
+
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister result;
+
+  int i1 = instr->ExtractBit(5);
+  SimVRegister add_sub_imm, min_max_imm, mul_imm;
+  uint64_t half = FPToRawbitsWithSize(LaneSizeInBitsFromFormat(vform), 0.5);
+  uint64_t one = FPToRawbitsWithSize(LaneSizeInBitsFromFormat(vform), 1.0);
+  uint64_t two = FPToRawbitsWithSize(LaneSizeInBitsFromFormat(vform), 2.0);
+  dup_immediate(vform, add_sub_imm, i1 ? one : half);
+  dup_immediate(vform, min_max_imm, i1 ? one : 0);
+  dup_immediate(vform, mul_imm, i1 ? two : half);
+
+  switch (instr->Mask(SVEFPArithmeticWithImm_PredicatedMask)) {
+    case FADD_z_p_zs:
+      fadd(vform, result, zdn, add_sub_imm);
+      break;
+    case FMAXNM_z_p_zs:
+      fmaxnm(vform, result, zdn, min_max_imm);
+      break;
+    case FMAX_z_p_zs:
+      fmax(vform, result, zdn, min_max_imm);
+      break;
+    case FMINNM_z_p_zs:
+      fminnm(vform, result, zdn, min_max_imm);
+      break;
+    case FMIN_z_p_zs:
+      fmin(vform, result, zdn, min_max_imm);
+      break;
+    case FMUL_z_p_zs:
+      fmul(vform, result, zdn, mul_imm);
+      break;
+    case FSUBR_z_p_zs:
+      fsub(vform, result, add_sub_imm, zdn);
+      break;
+    case FSUB_z_p_zs:
+      fsub(vform, result, zdn, add_sub_imm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEFPTrigMulAddCoefficient(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+
+  switch (instr->Mask(SVEFPTrigMulAddCoefficientMask)) {
+    case FTMAD_z_zzi:
+      ftmad(vform, zd, zd, zm, instr->ExtractBits(18, 16));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEFPArithmeticUnpredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+
+  switch (instr->Mask(SVEFPArithmeticUnpredicatedMask)) {
+    case FADD_z_zz:
+      fadd(vform, zd, zn, zm);
+      break;
+    case FMUL_z_zz:
+      fmul(vform, zd, zn, zm);
+      break;
+    case FRECPS_z_zz:
+      frecps(vform, zd, zn, zm);
+      break;
+    case FRSQRTS_z_zz:
+      frsqrts(vform, zd, zn, zm);
+      break;
+    case FSUB_z_zz:
+      fsub(vform, zd, zn, zm);
+      break;
+    case FTSMUL_z_zz:
+      ftsmul(vform, zd, zn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEFPCompareVectors(const Instruction* instr) {
+  SimPRegister& pd = ReadPRegister(instr->GetPd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister result;
+
+  switch (instr->Mask(SVEFPCompareVectorsMask)) {
+    case FACGE_p_p_zz:
+      fabscmp(vform, result, zn, zm, ge);
+      break;
+    case FACGT_p_p_zz:
+      fabscmp(vform, result, zn, zm, gt);
+      break;
+    case FCMEQ_p_p_zz:
+      fcmp(vform, result, zn, zm, eq);
+      break;
+    case FCMGE_p_p_zz:
+      fcmp(vform, result, zn, zm, ge);
+      break;
+    case FCMGT_p_p_zz:
+      fcmp(vform, result, zn, zm, gt);
+      break;
+    case FCMNE_p_p_zz:
+      fcmp(vform, result, zn, zm, ne);
+      break;
+    case FCMUO_p_p_zz:
+      fcmp(vform, result, zn, zm, uo);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  ExtractFromSimVRegister(vform, pd, result);
+  mov_zeroing(pd, pg, pd);
+}
+
+void Simulator::VisitSVEFPCompareWithZero(const Instruction* instr) {
+  SimPRegister& pd = ReadPRegister(instr->GetPd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister result;
+
+  SimVRegister zeros;
+  dup_immediate(kFormatVnD, zeros, 0);
+
+  switch (instr->Mask(SVEFPCompareWithZeroMask)) {
+    case FCMEQ_p_p_z0:
+      fcmp(vform, result, zn, zeros, eq);
+      break;
+    case FCMGE_p_p_z0:
+      fcmp(vform, result, zn, zeros, ge);
+      break;
+    case FCMGT_p_p_z0:
+      fcmp(vform, result, zn, zeros, gt);
+      break;
+    case FCMLE_p_p_z0:
+      fcmp(vform, result, zn, zeros, le);
+      break;
+    case FCMLT_p_p_z0:
+      fcmp(vform, result, zn, zeros, lt);
+      break;
+    case FCMNE_p_p_z0:
+      fcmp(vform, result, zn, zeros, ne);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  ExtractFromSimVRegister(vform, pd, result);
+  mov_zeroing(pd, pg, pd);
+}
+
+void Simulator::VisitSVEFPComplexAddition(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  if (LaneSizeInBitsFromFormat(vform) == kBRegSize) {
+    VIXL_UNIMPLEMENTED();
+  }
+
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  int rot = instr->ExtractBit(16);
+
+  SimVRegister result;
+
+  switch (instr->Mask(SVEFPComplexAdditionMask)) {
+    case FCADD_z_p_zz:
+      fcadd(vform, result, zdn, zm, rot);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEFPComplexMulAdd(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  if (LaneSizeInBitsFromFormat(vform) == kBRegSize) {
+    VIXL_UNIMPLEMENTED();
+  }
+
+  SimVRegister& zda = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  int rot = instr->ExtractBits(14, 13);
+
+  SimVRegister result;
+
+  switch (instr->Mask(SVEFPComplexMulAddMask)) {
+    case FCMLA_z_p_zzz:
+      fcmla(vform, result, zn, zm, zda, rot);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zda, pg, result);
+}
+
+void Simulator::VisitSVEFPComplexMulAddIndex(const Instruction* instr) {
+  SimVRegister& zda = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  int rot = instr->ExtractBits(11, 10);
+  unsigned zm_code = instr->GetRm();
+  int index = -1;
+  VectorFormat vform, vform_dup;
+
+  switch (instr->Mask(SVEFPComplexMulAddIndexMask)) {
+    case FCMLA_z_zzzi_h:
+      vform = kFormatVnH;
+      vform_dup = kFormatVnS;
+      index = zm_code >> 3;
+      zm_code &= 0x7;
+      break;
+    case FCMLA_z_zzzi_s:
+      vform = kFormatVnS;
+      vform_dup = kFormatVnD;
+      index = zm_code >> 4;
+      zm_code &= 0xf;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (index >= 0) {
+    SimVRegister temp;
+    dup_elements_to_segments(vform_dup, temp, ReadVRegister(zm_code), index);
+    fcmla(vform, zda, zn, temp, zda, rot);
+  }
+}
+
+typedef LogicVRegister (Simulator::*FastReduceFn)(VectorFormat vform,
+                                                  LogicVRegister dst,
+                                                  const LogicVRegister& src);
+
+void Simulator::VisitSVEFPFastReduction(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& vd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  int lane_size = LaneSizeInBitsFromFormat(vform);
+
+  uint64_t inactive_value = 0;
+  FastReduceFn fn = nullptr;
+
+  switch (instr->Mask(SVEFPFastReductionMask)) {
+    case FADDV_v_p_z:
+      fn = &Simulator::faddv;
+      break;
+    case FMAXNMV_v_p_z:
+      inactive_value = FPToRawbitsWithSize(lane_size, kFP64DefaultNaN);
+      fn = &Simulator::fmaxnmv;
+      break;
+    case FMAXV_v_p_z:
+      inactive_value = FPToRawbitsWithSize(lane_size, kFP64NegativeInfinity);
+      fn = &Simulator::fmaxv;
+      break;
+    case FMINNMV_v_p_z:
+      inactive_value = FPToRawbitsWithSize(lane_size, kFP64DefaultNaN);
+      fn = &Simulator::fminnmv;
+      break;
+    case FMINV_v_p_z:
+      inactive_value = FPToRawbitsWithSize(lane_size, kFP64PositiveInfinity);
+      fn = &Simulator::fminv;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SimVRegister scratch;
+  dup_immediate(vform, scratch, inactive_value);
+  mov_merging(vform, scratch, pg, zn);
+  if (fn != nullptr) (this->*fn)(vform, vd, scratch);
+}
+
+void Simulator::VisitSVEFPMulIndex(const Instruction* instr) {
+  VectorFormat vform = kFormatUndefined;
+  unsigned zm_code = instr->GetRm() & 0xf;
+  unsigned index = instr->ExtractBits(20, 19);
+
+  switch (instr->Mask(SVEFPMulIndexMask)) {
+    case FMUL_z_zzi_d:
+      vform = kFormatVnD;
+      index >>= 1;  // Only bit 20 is the index for D lanes.
+      break;
+    case FMUL_z_zzi_h_i3h:
+      index += 4;  // Bit 22 (i3h) is the top bit of index.
+      VIXL_FALLTHROUGH();
+    case FMUL_z_zzi_h:
+      vform = kFormatVnH;
+      zm_code &= 7;  // Three bits used for zm.
+      break;
+    case FMUL_z_zzi_s:
+      vform = kFormatVnS;
+      zm_code &= 7;  // Three bits used for zm.
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister temp;
+
+  dup_elements_to_segments(vform, temp, ReadVRegister(zm_code), index);
+  fmul(vform, zd, zn, temp);
+}
+
+void Simulator::VisitSVEFPMulAdd(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister result;
+
+  if (instr->ExtractBit(15) == 0) {
+    // Floating-point multiply-accumulate writing addend.
+    SimVRegister& zm = ReadVRegister(instr->GetRm());
+    SimVRegister& zn = ReadVRegister(instr->GetRn());
+
+    switch (instr->Mask(SVEFPMulAddMask)) {
+      // zda = zda + zn * zm
+      case FMLA_z_p_zzz:
+        fmla(vform, result, zd, zn, zm);
+        break;
+      // zda = -zda + -zn * zm
+      case FNMLA_z_p_zzz:
+        fneg(vform, result, zd);
+        fmls(vform, result, result, zn, zm);
+        break;
+      // zda = zda + -zn * zm
+      case FMLS_z_p_zzz:
+        fmls(vform, result, zd, zn, zm);
+        break;
+      // zda = -zda + zn * zm
+      case FNMLS_z_p_zzz:
+        fneg(vform, result, zd);
+        fmla(vform, result, result, zn, zm);
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  } else {
+    // Floating-point multiply-accumulate writing multiplicand.
+    SimVRegister& za = ReadVRegister(instr->GetRm());
+    SimVRegister& zm = ReadVRegister(instr->GetRn());
+
+    switch (instr->Mask(SVEFPMulAddMask)) {
+      // zdn = za + zdn * zm
+      case FMAD_z_p_zzz:
+        fmla(vform, result, za, zd, zm);
+        break;
+      // zdn = -za + -zdn * zm
+      case FNMAD_z_p_zzz:
+        fneg(vform, result, za);
+        fmls(vform, result, result, zd, zm);
+        break;
+      // zdn = za + -zdn * zm
+      case FMSB_z_p_zzz:
+        fmls(vform, result, za, zd, zm);
+        break;
+      // zdn = -za + zdn * zm
+      case FNMSB_z_p_zzz:
+        fneg(vform, result, za);
+        fmla(vform, result, result, zd, zm);
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  }
+
+  mov_merging(vform, zd, pg, result);
+}
+
+void Simulator::VisitSVEFPMulAddIndex(const Instruction* instr) {
+  VectorFormat vform = kFormatUndefined;
+  unsigned zm_code = 0xffffffff;
+  unsigned index = 0xffffffff;
+
+  switch (instr->Mask(SVEFPMulAddIndexMask)) {
+    case FMLA_z_zzzi_d:
+    case FMLS_z_zzzi_d:
+      vform = kFormatVnD;
+      zm_code = instr->GetRmLow16();
+      // Only bit 20 is the index for D lanes.
+      index = instr->ExtractBit(20);
+      break;
+    case FMLA_z_zzzi_s:
+    case FMLS_z_zzzi_s:
+      vform = kFormatVnS;
+      zm_code = instr->GetRm() & 0x7;  // Three bits used for zm.
+      index = instr->ExtractBits(20, 19);
+      break;
+    case FMLA_z_zzzi_h:
+    case FMLS_z_zzzi_h:
+    case FMLA_z_zzzi_h_i3h:
+    case FMLS_z_zzzi_h_i3h:
+      vform = kFormatVnH;
+      zm_code = instr->GetRm() & 0x7;  // Three bits used for zm.
+      index = (instr->ExtractBit(22) << 2) | instr->ExtractBits(20, 19);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister temp;
+
+  dup_elements_to_segments(vform, temp, ReadVRegister(zm_code), index);
+  if (instr->ExtractBit(10) == 1) {
+    fmls(vform, zd, zd, zn, temp);
+  } else {
+    fmla(vform, zd, zd, zn, temp);
+  }
+}
+
+void Simulator::VisitSVEFPConvertToInt(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  int dst_data_size;
+  int src_data_size;
+
+  switch (instr->Mask(SVEFPConvertToIntMask)) {
+    case FCVTZS_z_p_z_d2w:
+    case FCVTZU_z_p_z_d2w:
+      dst_data_size = kSRegSize;
+      src_data_size = kDRegSize;
+      break;
+    case FCVTZS_z_p_z_d2x:
+    case FCVTZU_z_p_z_d2x:
+      dst_data_size = kDRegSize;
+      src_data_size = kDRegSize;
+      break;
+    case FCVTZS_z_p_z_fp162h:
+    case FCVTZU_z_p_z_fp162h:
+      dst_data_size = kHRegSize;
+      src_data_size = kHRegSize;
+      break;
+    case FCVTZS_z_p_z_fp162w:
+    case FCVTZU_z_p_z_fp162w:
+      dst_data_size = kSRegSize;
+      src_data_size = kHRegSize;
+      break;
+    case FCVTZS_z_p_z_fp162x:
+    case FCVTZU_z_p_z_fp162x:
+      dst_data_size = kDRegSize;
+      src_data_size = kHRegSize;
+      break;
+    case FCVTZS_z_p_z_s2w:
+    case FCVTZU_z_p_z_s2w:
+      dst_data_size = kSRegSize;
+      src_data_size = kSRegSize;
+      break;
+    case FCVTZS_z_p_z_s2x:
+    case FCVTZU_z_p_z_s2x:
+      dst_data_size = kDRegSize;
+      src_data_size = kSRegSize;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      dst_data_size = 0;
+      src_data_size = 0;
+      break;
+  }
+
+  VectorFormat vform =
+      SVEFormatFromLaneSizeInBits(std::max(dst_data_size, src_data_size));
+
+  if (instr->ExtractBit(16) == 0) {
+    fcvts(vform, dst_data_size, src_data_size, zd, pg, zn, FPZero);
+  } else {
+    fcvtu(vform, dst_data_size, src_data_size, zd, pg, zn, FPZero);
+  }
+}
+
+void Simulator::VisitSVEFPConvertPrecision(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  int dst_data_size;
+  int src_data_size;
+
+  switch (instr->Mask(SVEFPConvertPrecisionMask)) {
+    case FCVT_z_p_z_d2h:
+      dst_data_size = kHRegSize;
+      src_data_size = kDRegSize;
+      break;
+    case FCVT_z_p_z_d2s:
+      dst_data_size = kSRegSize;
+      src_data_size = kDRegSize;
+      break;
+    case FCVT_z_p_z_h2d:
+      dst_data_size = kDRegSize;
+      src_data_size = kHRegSize;
+      break;
+    case FCVT_z_p_z_h2s:
+      dst_data_size = kSRegSize;
+      src_data_size = kHRegSize;
+      break;
+    case FCVT_z_p_z_s2d:
+      dst_data_size = kDRegSize;
+      src_data_size = kSRegSize;
+      break;
+    case FCVT_z_p_z_s2h:
+      dst_data_size = kHRegSize;
+      src_data_size = kSRegSize;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      dst_data_size = 0;
+      src_data_size = 0;
+      break;
+  }
+  VectorFormat vform =
+      SVEFormatFromLaneSizeInBits(std::max(dst_data_size, src_data_size));
+
+  fcvt(vform, dst_data_size, src_data_size, zd, pg, zn);
+}
+
+void Simulator::VisitSVEFPUnaryOp(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister result;
+
+  switch (instr->Mask(SVEFPUnaryOpMask)) {
+    case FRECPX_z_p_z:
+      frecpx(vform, result, zn);
+      break;
+    case FSQRT_z_p_z:
+      fsqrt(vform, result, zn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zd, pg, result);
+}
+
+void Simulator::VisitSVEFPRoundToIntegralValue(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  FPRounding fpcr_rounding = static_cast<FPRounding>(ReadFpcr().GetRMode());
+  bool exact_exception = false;
+
+  switch (instr->Mask(SVEFPRoundToIntegralValueMask)) {
+    case FRINTA_z_p_z:
+      fpcr_rounding = FPTieAway;
+      break;
+    case FRINTI_z_p_z:
+      break;  // Use FPCR rounding mode.
+    case FRINTM_z_p_z:
+      fpcr_rounding = FPNegativeInfinity;
+      break;
+    case FRINTN_z_p_z:
+      fpcr_rounding = FPTieEven;
+      break;
+    case FRINTP_z_p_z:
+      fpcr_rounding = FPPositiveInfinity;
+      break;
+    case FRINTX_z_p_z:
+      exact_exception = true;
+      break;
+    case FRINTZ_z_p_z:
+      fpcr_rounding = FPZero;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SimVRegister result;
+  frint(vform, result, zn, fpcr_rounding, exact_exception, kFrintToInteger);
+  mov_merging(vform, zd, pg, result);
+}
+
+void Simulator::VisitSVEIntConvertToFP(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  FPRounding fpcr_rounding = static_cast<FPRounding>(ReadFpcr().GetRMode());
+  int dst_data_size;
+  int src_data_size;
+
+  switch (instr->Mask(SVEIntConvertToFPMask)) {
+    case SCVTF_z_p_z_h2fp16:
+    case UCVTF_z_p_z_h2fp16:
+      dst_data_size = kHRegSize;
+      src_data_size = kHRegSize;
+      break;
+    case SCVTF_z_p_z_w2d:
+    case UCVTF_z_p_z_w2d:
+      dst_data_size = kDRegSize;
+      src_data_size = kSRegSize;
+      break;
+    case SCVTF_z_p_z_w2fp16:
+    case UCVTF_z_p_z_w2fp16:
+      dst_data_size = kHRegSize;
+      src_data_size = kSRegSize;
+      break;
+    case SCVTF_z_p_z_w2s:
+    case UCVTF_z_p_z_w2s:
+      dst_data_size = kSRegSize;
+      src_data_size = kSRegSize;
+      break;
+    case SCVTF_z_p_z_x2d:
+    case UCVTF_z_p_z_x2d:
+      dst_data_size = kDRegSize;
+      src_data_size = kDRegSize;
+      break;
+    case SCVTF_z_p_z_x2fp16:
+    case UCVTF_z_p_z_x2fp16:
+      dst_data_size = kHRegSize;
+      src_data_size = kDRegSize;
+      break;
+    case SCVTF_z_p_z_x2s:
+    case UCVTF_z_p_z_x2s:
+      dst_data_size = kSRegSize;
+      src_data_size = kDRegSize;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      dst_data_size = 0;
+      src_data_size = 0;
+      break;
+  }
+
+  VectorFormat vform =
+      SVEFormatFromLaneSizeInBits(std::max(dst_data_size, src_data_size));
+
+  if (instr->ExtractBit(16) == 0) {
+    scvtf(vform, dst_data_size, src_data_size, zd, pg, zn, fpcr_rounding);
+  } else {
+    ucvtf(vform, dst_data_size, src_data_size, zd, pg, zn, fpcr_rounding);
+  }
+}
+
+void Simulator::VisitSVEFPUnaryOpUnpredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  FPRounding fpcr_rounding = static_cast<FPRounding>(ReadFpcr().GetRMode());
+
+  switch (instr->Mask(SVEFPUnaryOpUnpredicatedMask)) {
+    case FRECPE_z_z:
+      frecpe(vform, zd, zn, fpcr_rounding);
+      break;
+    case FRSQRTE_z_z:
+      frsqrte(vform, zd, zn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEIncDecByPredicateCount(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(8, 5));
+
+  int count = CountActiveLanes(vform, pg);
+
+  if (instr->ExtractBit(11) == 0) {
+    SimVRegister& zdn = ReadVRegister(instr->GetRd());
+    switch (instr->Mask(SVEIncDecByPredicateCountMask)) {
+      case DECP_z_p_z:
+        sub_uint(vform, zdn, zdn, count);
+        break;
+      case INCP_z_p_z:
+        add_uint(vform, zdn, zdn, count);
+        break;
+      case SQDECP_z_p_z:
+        sub_uint(vform, zdn, zdn, count).SignedSaturate(vform);
+        break;
+      case SQINCP_z_p_z:
+        add_uint(vform, zdn, zdn, count).SignedSaturate(vform);
+        break;
+      case UQDECP_z_p_z:
+        sub_uint(vform, zdn, zdn, count).UnsignedSaturate(vform);
+        break;
+      case UQINCP_z_p_z:
+        add_uint(vform, zdn, zdn, count).UnsignedSaturate(vform);
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  } else {
+    bool is_saturating = (instr->ExtractBit(18) == 0);
+    bool decrement =
+        is_saturating ? instr->ExtractBit(17) : instr->ExtractBit(16);
+    bool is_signed = (instr->ExtractBit(16) == 0);
+    bool sf = is_saturating ? (instr->ExtractBit(10) != 0) : true;
+    unsigned width = sf ? kXRegSize : kWRegSize;
+
+    switch (instr->Mask(SVEIncDecByPredicateCountMask)) {
+      case DECP_r_p_r:
+      case INCP_r_p_r:
+      case SQDECP_r_p_r_sx:
+      case SQDECP_r_p_r_x:
+      case SQINCP_r_p_r_sx:
+      case SQINCP_r_p_r_x:
+      case UQDECP_r_p_r_uw:
+      case UQDECP_r_p_r_x:
+      case UQINCP_r_p_r_uw:
+      case UQINCP_r_p_r_x:
+        WriteXRegister(instr->GetRd(),
+                       IncDecN(ReadXRegister(instr->GetRd()),
+                               decrement ? -count : count,
+                               width,
+                               is_saturating,
+                               is_signed));
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  }
+}
+
+uint64_t Simulator::IncDecN(uint64_t acc,
+                            int64_t delta,
+                            unsigned n,
+                            bool is_saturating,
+                            bool is_signed) {
+  VIXL_ASSERT(n <= 64);
+  VIXL_ASSERT(IsIntN(n, delta));
+
+  uint64_t sign_mask = UINT64_C(1) << (n - 1);
+  uint64_t mask = GetUintMask(n);
+
+  acc &= mask;  // Ignore initial accumulator high bits.
+  uint64_t result = (acc + delta) & mask;
+
+  bool result_negative = ((result & sign_mask) != 0);
+
+  if (is_saturating) {
+    if (is_signed) {
+      bool acc_negative = ((acc & sign_mask) != 0);
+      bool delta_negative = delta < 0;
+
+      // If the signs of the operands are the same, but different from the
+      // result, there was an overflow.
+      if ((acc_negative == delta_negative) &&
+          (acc_negative != result_negative)) {
+        if (result_negative) {
+          // Saturate to [..., INT<n>_MAX].
+          result_negative = false;
+          result = mask & ~sign_mask;  // E.g. 0x000000007fffffff
+        } else {
+          // Saturate to [INT<n>_MIN, ...].
+          result_negative = true;
+          result = ~mask | sign_mask;  // E.g. 0xffffffff80000000
+        }
+      }
+    } else {
+      if ((delta < 0) && (result > acc)) {
+        // Saturate to [0, ...].
+        result = 0;
+      } else if ((delta > 0) && (result < acc)) {
+        // Saturate to [..., UINT<n>_MAX].
+        result = mask;
+      }
+    }
+  }
+
+  // Sign-extend if necessary.
+  if (result_negative && is_signed) result |= ~mask;
+
+  return result;
+}
+
+void Simulator::VisitSVEIndexGeneration(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  switch (instr->Mask(SVEIndexGenerationMask)) {
+    case INDEX_z_ii:
+    case INDEX_z_ir:
+    case INDEX_z_ri:
+    case INDEX_z_rr: {
+      uint64_t start = instr->ExtractBit(10) ? ReadXRegister(instr->GetRn())
+                                             : instr->ExtractSignedBits(9, 5);
+      uint64_t step = instr->ExtractBit(11) ? ReadXRegister(instr->GetRm())
+                                            : instr->ExtractSignedBits(20, 16);
+      index(vform, zd, start, step);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEIntArithmeticUnpredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+  switch (instr->Mask(SVEIntArithmeticUnpredicatedMask)) {
+    case ADD_z_zz:
+      add(vform, zd, zn, zm);
+      break;
+    case SQADD_z_zz:
+      add(vform, zd, zn, zm).SignedSaturate(vform);
+      break;
+    case SQSUB_z_zz:
+      sub(vform, zd, zn, zm).SignedSaturate(vform);
+      break;
+    case SUB_z_zz:
+      sub(vform, zd, zn, zm);
+      break;
+    case UQADD_z_zz:
+      add(vform, zd, zn, zm).UnsignedSaturate(vform);
+      break;
+    case UQSUB_z_zz:
+      sub(vform, zd, zn, zm).UnsignedSaturate(vform);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEIntAddSubtractVectors_Predicated(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister result;
+
+  switch (instr->Mask(SVEIntAddSubtractVectors_PredicatedMask)) {
+    case ADD_z_p_zz:
+      add(vform, result, zdn, zm);
+      break;
+    case SUBR_z_p_zz:
+      sub(vform, result, zm, zdn);
+      break;
+    case SUB_z_p_zz:
+      sub(vform, result, zdn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEBitwiseLogical_Predicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister result;
+
+  switch (instr->Mask(SVEBitwiseLogical_PredicatedMask)) {
+    case AND_z_p_zz:
+      SVEBitwiseLogicalUnpredicatedHelper(AND, vform, result, zdn, zm);
+      break;
+    case BIC_z_p_zz:
+      SVEBitwiseLogicalUnpredicatedHelper(BIC, vform, result, zdn, zm);
+      break;
+    case EOR_z_p_zz:
+      SVEBitwiseLogicalUnpredicatedHelper(EOR, vform, result, zdn, zm);
+      break;
+    case ORR_z_p_zz:
+      SVEBitwiseLogicalUnpredicatedHelper(ORR, vform, result, zdn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEIntMulVectors_Predicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister result;
+
+  switch (instr->Mask(SVEIntMulVectors_PredicatedMask)) {
+    case MUL_z_p_zz:
+      mul(vform, result, zdn, zm);
+      break;
+    case SMULH_z_p_zz:
+      smulh(vform, result, zdn, zm);
+      break;
+    case UMULH_z_p_zz:
+      umulh(vform, result, zdn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEIntMinMaxDifference_Predicated(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister result;
+
+  switch (instr->Mask(SVEIntMinMaxDifference_PredicatedMask)) {
+    case SABD_z_p_zz:
+      absdiff(vform, result, zdn, zm, true);
+      break;
+    case SMAX_z_p_zz:
+      smax(vform, result, zdn, zm);
+      break;
+    case SMIN_z_p_zz:
+      smin(vform, result, zdn, zm);
+      break;
+    case UABD_z_p_zz:
+      absdiff(vform, result, zdn, zm, false);
+      break;
+    case UMAX_z_p_zz:
+      umax(vform, result, zdn, zm);
+      break;
+    case UMIN_z_p_zz:
+      umin(vform, result, zdn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEIntMulImm_Unpredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister scratch;
+
+  switch (instr->Mask(SVEIntMulImm_UnpredicatedMask)) {
+    case MUL_z_zi:
+      dup_immediate(vform, scratch, instr->GetImmSVEIntWideSigned());
+      mul(vform, zd, zd, scratch);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEIntDivideVectors_Predicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister result;
+
+  VIXL_ASSERT((vform == kFormatVnS) || (vform == kFormatVnD));
+
+  switch (instr->Mask(SVEIntDivideVectors_PredicatedMask)) {
+    case SDIVR_z_p_zz:
+      sdiv(vform, result, zm, zdn);
+      break;
+    case SDIV_z_p_zz:
+      sdiv(vform, result, zdn, zm);
+      break;
+    case UDIVR_z_p_zz:
+      udiv(vform, result, zm, zdn);
+      break;
+    case UDIV_z_p_zz:
+      udiv(vform, result, zdn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zdn, pg, result);
+}
+
+void Simulator::VisitSVEIntMinMaxImm_Unpredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister scratch;
+
+  uint64_t unsigned_imm = instr->GetImmSVEIntWideUnsigned();
+  int64_t signed_imm = instr->GetImmSVEIntWideSigned();
+
+  switch (instr->Mask(SVEIntMinMaxImm_UnpredicatedMask)) {
+    case SMAX_z_zi:
+      dup_immediate(vform, scratch, signed_imm);
+      smax(vform, zd, zd, scratch);
+      break;
+    case SMIN_z_zi:
+      dup_immediate(vform, scratch, signed_imm);
+      smin(vform, zd, zd, scratch);
+      break;
+    case UMAX_z_zi:
+      dup_immediate(vform, scratch, unsigned_imm);
+      umax(vform, zd, zd, scratch);
+      break;
+    case UMIN_z_zi:
+      dup_immediate(vform, scratch, unsigned_imm);
+      umin(vform, zd, zd, scratch);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEIntCompareScalarCountAndLimit(
+    const Instruction* instr) {
+  unsigned rn_code = instr->GetRn();
+  unsigned rm_code = instr->GetRm();
+  SimPRegister& pd = ReadPRegister(instr->GetPd());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  bool is_64_bit = instr->ExtractBit(12) == 1;
+  int64_t src1 = is_64_bit ? ReadXRegister(rn_code) : ReadWRegister(rn_code);
+  int64_t src2 = is_64_bit ? ReadXRegister(rm_code) : ReadWRegister(rm_code);
+
+  bool last = true;
+  for (int lane = 0; lane < LaneCountFromFormat(vform); lane++) {
+    bool cond = false;
+    switch (instr->Mask(SVEIntCompareScalarCountAndLimitMask)) {
+      case WHILELE_p_p_rr:
+        cond = src1 <= src2;
+        break;
+      case WHILELO_p_p_rr:
+        cond = static_cast<uint64_t>(src1) < static_cast<uint64_t>(src2);
+        break;
+      case WHILELS_p_p_rr:
+        cond = static_cast<uint64_t>(src1) <= static_cast<uint64_t>(src2);
+        break;
+      case WHILELT_p_p_rr:
+        cond = src1 < src2;
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+    last = last && cond;
+    LogicPRegister dst(pd);
+    dst.SetActive(vform, lane, last);
+    src1 += 1;
+  }
+
+  PredTest(vform, GetPTrue(), pd);
+  LogSystemRegister(NZCV);
+}
+
+void Simulator::VisitSVEConditionallyTerminateScalars(
+    const Instruction* instr) {
+  unsigned rn_code = instr->GetRn();
+  unsigned rm_code = instr->GetRm();
+  bool is_64_bit = instr->ExtractBit(22) == 1;
+  uint64_t src1 = is_64_bit ? ReadXRegister(rn_code) : ReadWRegister(rn_code);
+  uint64_t src2 = is_64_bit ? ReadXRegister(rm_code) : ReadWRegister(rm_code);
+  bool term;
+  switch (instr->Mask(SVEConditionallyTerminateScalarsMask)) {
+    case CTERMEQ_rr:
+      term = src1 == src2;
+      break;
+    case CTERMNE_rr:
+      term = src1 != src2;
+      break;
+    default:
+      term = false;
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  ReadNzcv().SetN(term ? 1 : 0);
+  ReadNzcv().SetV(term ? 0 : !ReadC());
+  LogSystemRegister(NZCV);
+}
+
+void Simulator::VisitSVEIntCompareSignedImm(const Instruction* instr) {
+  bool commute_inputs = false;
+  Condition cond;
+  switch (instr->Mask(SVEIntCompareSignedImmMask)) {
+    case CMPEQ_p_p_zi:
+      cond = eq;
+      break;
+    case CMPGE_p_p_zi:
+      cond = ge;
+      break;
+    case CMPGT_p_p_zi:
+      cond = gt;
+      break;
+    case CMPLE_p_p_zi:
+      cond = ge;
+      commute_inputs = true;
+      break;
+    case CMPLT_p_p_zi:
+      cond = gt;
+      commute_inputs = true;
+      break;
+    case CMPNE_p_p_zi:
+      cond = ne;
+      break;
+    default:
+      cond = al;
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister src2;
+  dup_immediate(vform,
+                src2,
+                ExtractSignedBitfield64(4, 0, instr->ExtractBits(20, 16)));
+  SVEIntCompareVectorsHelper(cond,
+                             vform,
+                             ReadPRegister(instr->GetPd()),
+                             ReadPRegister(instr->GetPgLow8()),
+                             commute_inputs ? src2
+                                            : ReadVRegister(instr->GetRn()),
+                             commute_inputs ? ReadVRegister(instr->GetRn())
+                                            : src2);
+}
+
+void Simulator::VisitSVEIntCompareUnsignedImm(const Instruction* instr) {
+  bool commute_inputs = false;
+  Condition cond;
+  switch (instr->Mask(SVEIntCompareUnsignedImmMask)) {
+    case CMPHI_p_p_zi:
+      cond = hi;
+      break;
+    case CMPHS_p_p_zi:
+      cond = hs;
+      break;
+    case CMPLO_p_p_zi:
+      cond = hi;
+      commute_inputs = true;
+      break;
+    case CMPLS_p_p_zi:
+      cond = hs;
+      commute_inputs = true;
+      break;
+    default:
+      cond = al;
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister src2;
+  dup_immediate(vform, src2, instr->ExtractBits(20, 14));
+  SVEIntCompareVectorsHelper(cond,
+                             vform,
+                             ReadPRegister(instr->GetPd()),
+                             ReadPRegister(instr->GetPgLow8()),
+                             commute_inputs ? src2
+                                            : ReadVRegister(instr->GetRn()),
+                             commute_inputs ? ReadVRegister(instr->GetRn())
+                                            : src2);
+}
+
+void Simulator::VisitSVEIntCompareVectors(const Instruction* instr) {
+  Instr op = instr->Mask(SVEIntCompareVectorsMask);
+  bool is_wide_elements = false;
+  switch (op) {
+    case CMPEQ_p_p_zw:
+    case CMPGE_p_p_zw:
+    case CMPGT_p_p_zw:
+    case CMPHI_p_p_zw:
+    case CMPHS_p_p_zw:
+    case CMPLE_p_p_zw:
+    case CMPLO_p_p_zw:
+    case CMPLS_p_p_zw:
+    case CMPLT_p_p_zw:
+    case CMPNE_p_p_zw:
+      is_wide_elements = true;
+      break;
+  }
+
+  Condition cond;
+  switch (op) {
+    case CMPEQ_p_p_zw:
+    case CMPEQ_p_p_zz:
+      cond = eq;
+      break;
+    case CMPGE_p_p_zw:
+    case CMPGE_p_p_zz:
+      cond = ge;
+      break;
+    case CMPGT_p_p_zw:
+    case CMPGT_p_p_zz:
+      cond = gt;
+      break;
+    case CMPHI_p_p_zw:
+    case CMPHI_p_p_zz:
+      cond = hi;
+      break;
+    case CMPHS_p_p_zw:
+    case CMPHS_p_p_zz:
+      cond = hs;
+      break;
+    case CMPNE_p_p_zw:
+    case CMPNE_p_p_zz:
+      cond = ne;
+      break;
+    case CMPLE_p_p_zw:
+      cond = le;
+      break;
+    case CMPLO_p_p_zw:
+      cond = lo;
+      break;
+    case CMPLS_p_p_zw:
+      cond = ls;
+      break;
+    case CMPLT_p_p_zw:
+      cond = lt;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      cond = al;
+      break;
+  }
+
+  SVEIntCompareVectorsHelper(cond,
+                             instr->GetSVEVectorFormat(),
+                             ReadPRegister(instr->GetPd()),
+                             ReadPRegister(instr->GetPgLow8()),
+                             ReadVRegister(instr->GetRn()),
+                             ReadVRegister(instr->GetRm()),
+                             is_wide_elements);
+}
+
+void Simulator::VisitSVEFPExponentialAccelerator(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+
+  VIXL_ASSERT((vform == kFormatVnH) || (vform == kFormatVnS) ||
+              (vform == kFormatVnD));
+
+  switch (instr->Mask(SVEFPExponentialAcceleratorMask)) {
+    case FEXPA_z_z:
+      fexpa(vform, zd, zn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEFPTrigSelectCoefficient(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+
+  VIXL_ASSERT((vform == kFormatVnH) || (vform == kFormatVnS) ||
+              (vform == kFormatVnD));
+
+  switch (instr->Mask(SVEFPTrigSelectCoefficientMask)) {
+    case FTSSEL_z_zz:
+      ftssel(vform, zd, zn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEConstructivePrefix_Unpredicated(
+    const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+
+  switch (instr->Mask(SVEConstructivePrefix_UnpredicatedMask)) {
+    case MOVPRFX_z_z:
+      mov(kFormatVnD, zd, zn);  // The lane size is arbitrary.
+      // Record the movprfx, so the next ExecuteInstruction() can check it.
+      movprfx_ = instr;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEIntMulAddPredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+
+  SimVRegister result;
+  switch (instr->Mask(SVEIntMulAddPredicatedMask)) {
+    case MLA_z_p_zzz:
+      mla(vform, result, zd, ReadVRegister(instr->GetRn()), zm);
+      break;
+    case MLS_z_p_zzz:
+      mls(vform, result, zd, ReadVRegister(instr->GetRn()), zm);
+      break;
+    case MAD_z_p_zzz:
+      // 'za' is encoded in 'Rn'.
+      mla(vform, result, ReadVRegister(instr->GetRn()), zd, zm);
+      break;
+    case MSB_z_p_zzz: {
+      // 'za' is encoded in 'Rn'.
+      mls(vform, result, ReadVRegister(instr->GetRn()), zd, zm);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zd, ReadPRegister(instr->GetPgLow8()), result);
+}
+
+void Simulator::VisitSVEIntMulAddUnpredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zda = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+
+  switch (instr->Mask(SVEIntMulAddUnpredicatedMask)) {
+    case SDOT_z_zzz:
+      sdot(vform, zda, zn, zm);
+      break;
+    case UDOT_z_zzz:
+      udot(vform, zda, zn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEMovprfx(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+
+  switch (instr->Mask(SVEMovprfxMask)) {
+    case MOVPRFX_z_p_z:
+      if (instr->ExtractBit(16)) {
+        mov_merging(vform, zd, pg, zn);
+      } else {
+        mov_zeroing(vform, zd, pg, zn);
+      }
+
+      // Record the movprfx, so the next ExecuteInstruction() can check it.
+      movprfx_ = instr;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEIntReduction(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& vd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  if (instr->Mask(SVEIntReductionLogicalFMask) == SVEIntReductionLogicalFixed) {
+    switch (instr->Mask(SVEIntReductionLogicalMask)) {
+      case ANDV_r_p_z:
+        andv(vform, vd, pg, zn);
+        break;
+      case EORV_r_p_z:
+        eorv(vform, vd, pg, zn);
+        break;
+      case ORV_r_p_z:
+        orv(vform, vd, pg, zn);
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  } else {
+    switch (instr->Mask(SVEIntReductionMask)) {
+      case SADDV_r_p_z:
+        saddv(vform, vd, pg, zn);
+        break;
+      case SMAXV_r_p_z:
+        smaxv(vform, vd, pg, zn);
+        break;
+      case SMINV_r_p_z:
+        sminv(vform, vd, pg, zn);
+        break;
+      case UADDV_r_p_z:
+        uaddv(vform, vd, pg, zn);
+        break;
+      case UMAXV_r_p_z:
+        umaxv(vform, vd, pg, zn);
+        break;
+      case UMINV_r_p_z:
+        uminv(vform, vd, pg, zn);
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  }
+}
+
+void Simulator::VisitSVEIntUnaryArithmeticPredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+
+  SimVRegister result;
+  switch (instr->Mask(SVEIntUnaryArithmeticPredicatedMask)) {
+    case ABS_z_p_z:
+      abs(vform, result, zn);
+      break;
+    case CLS_z_p_z:
+      cls(vform, result, zn);
+      break;
+    case CLZ_z_p_z:
+      clz(vform, result, zn);
+      break;
+    case CNOT_z_p_z:
+      cnot(vform, result, zn);
+      break;
+    case CNT_z_p_z:
+      cnt(vform, result, zn);
+      break;
+    case FABS_z_p_z:
+      fabs_(vform, result, zn);
+      break;
+    case FNEG_z_p_z:
+      fneg(vform, result, zn);
+      break;
+    case NEG_z_p_z:
+      neg(vform, result, zn);
+      break;
+    case NOT_z_p_z:
+      not_(vform, result, zn);
+      break;
+    case SXTB_z_p_z:
+    case SXTH_z_p_z:
+    case SXTW_z_p_z:
+      sxt(vform, result, zn, (kBitsPerByte << instr->ExtractBits(18, 17)));
+      break;
+    case UXTB_z_p_z:
+    case UXTH_z_p_z:
+    case UXTW_z_p_z:
+      uxt(vform, result, zn, (kBitsPerByte << instr->ExtractBits(18, 17)));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  mov_merging(vform, zd, pg, result);
+}
+
+void Simulator::VisitSVECopyFPImm_Predicated(const Instruction* instr) {
+  // There is only one instruction in this group.
+  VIXL_ASSERT(instr->Mask(SVECopyFPImm_PredicatedMask) == FCPY_z_p_i);
+
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(19, 16));
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+
+  SimVRegister result;
+  switch (instr->Mask(SVECopyFPImm_PredicatedMask)) {
+    case FCPY_z_p_i: {
+      int imm8 = instr->ExtractBits(12, 5);
+      uint64_t value = FPToRawbitsWithSize(LaneSizeInBitsFromFormat(vform),
+                                           Instruction::Imm8ToFP64(imm8));
+      dup_immediate(vform, result, value);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  mov_merging(vform, zd, pg, result);
+}
+
+void Simulator::VisitSVEIntAddSubtractImm_Unpredicated(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister scratch;
+
+  uint64_t imm = instr->GetImmSVEIntWideUnsigned();
+  imm <<= instr->ExtractBit(13) * 8;
+
+  switch (instr->Mask(SVEIntAddSubtractImm_UnpredicatedMask)) {
+    case ADD_z_zi:
+      add_uint(vform, zd, zd, imm);
+      break;
+    case SQADD_z_zi:
+      add_uint(vform, zd, zd, imm).SignedSaturate(vform);
+      break;
+    case SQSUB_z_zi:
+      sub_uint(vform, zd, zd, imm).SignedSaturate(vform);
+      break;
+    case SUBR_z_zi:
+      dup_immediate(vform, scratch, imm);
+      sub(vform, zd, scratch, zd);
+      break;
+    case SUB_z_zi:
+      sub_uint(vform, zd, zd, imm);
+      break;
+    case UQADD_z_zi:
+      add_uint(vform, zd, zd, imm).UnsignedSaturate(vform);
+      break;
+    case UQSUB_z_zi:
+      sub_uint(vform, zd, zd, imm).UnsignedSaturate(vform);
+      break;
+    default:
+      break;
+  }
+}
+
+void Simulator::VisitSVEBroadcastIntImm_Unpredicated(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+
+  VectorFormat format = instr->GetSVEVectorFormat();
+  int64_t imm = instr->GetImmSVEIntWideSigned();
+  int shift = instr->ExtractBit(13) * 8;
+  imm *= 1 << shift;
+
+  switch (instr->Mask(SVEBroadcastIntImm_UnpredicatedMask)) {
+    case DUP_z_i:
+      // The encoding of byte-sized lanes with lsl #8 is undefined.
+      if ((format == kFormatVnB) && (shift == 8)) {
+        VIXL_UNIMPLEMENTED();
+      } else {
+        dup_immediate(format, zd, imm);
+      }
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEBroadcastFPImm_Unpredicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+
+  switch (instr->Mask(SVEBroadcastFPImm_UnpredicatedMask)) {
+    case FDUP_z_i:
+      switch (vform) {
+        case kFormatVnH:
+          dup_immediate(vform, zd, Float16ToRawbits(instr->GetSVEImmFP16()));
+          break;
+        case kFormatVnS:
+          dup_immediate(vform, zd, FloatToRawbits(instr->GetSVEImmFP32()));
+          break;
+        case kFormatVnD:
+          dup_immediate(vform, zd, DoubleToRawbits(instr->GetSVEImmFP64()));
+          break;
+        default:
+          VIXL_UNIMPLEMENTED();
+      }
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(
+      SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask)) {
+    case LD1H_z_p_bz_s_x32_scaled:
+    case LD1SH_z_p_bz_s_x32_scaled:
+    case LDFF1H_z_p_bz_s_x32_scaled:
+    case LDFF1SH_z_p_bz_s_x32_scaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
+  SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod);
+}
+
+void Simulator::VisitSVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask)) {
+    case LD1B_z_p_bz_s_x32_unscaled:
+    case LD1H_z_p_bz_s_x32_unscaled:
+    case LD1SB_z_p_bz_s_x32_unscaled:
+    case LD1SH_z_p_bz_s_x32_unscaled:
+    case LD1W_z_p_bz_s_x32_unscaled:
+    case LDFF1B_z_p_bz_s_x32_unscaled:
+    case LDFF1H_z_p_bz_s_x32_unscaled:
+    case LDFF1SB_z_p_bz_s_x32_unscaled:
+    case LDFF1SH_z_p_bz_s_x32_unscaled:
+    case LDFF1W_z_p_bz_s_x32_unscaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
+  SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod);
+}
+
+void Simulator::VisitSVE32BitGatherLoad_VectorPlusImm(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE32BitGatherLoad_VectorPlusImmMask)) {
+    case LD1B_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LD1H_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LD1SB_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LD1SH_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LD1W_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LDFF1B_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LDFF1H_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LDFF1SB_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LDFF1SH_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    case LDFF1W_z_p_ai_s:
+      VIXL_UNIMPLEMENTED();
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsets(
+    const Instruction* instr) {
+  switch (
+      instr->Mask(SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask)) {
+    case LD1W_z_p_bz_s_x32_scaled:
+    case LDFF1W_z_p_bz_s_x32_scaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
+  SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnS, mod);
+}
+
+void Simulator::VisitSVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsets(
+    const Instruction* instr) {
+  switch (
+      instr->Mask(SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask)) {
+    // Ignore prefetch hint instructions.
+    case PRFB_i_p_bz_s_x32_scaled:
+    case PRFD_i_p_bz_s_x32_scaled:
+    case PRFH_i_p_bz_s_x32_scaled:
+    case PRFW_i_p_bz_s_x32_scaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE32BitGatherPrefetch_VectorPlusImm(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE32BitGatherPrefetch_VectorPlusImmMask)) {
+    // Ignore prefetch hint instructions.
+    case PRFB_i_p_ai_s:
+    case PRFD_i_p_ai_s:
+    case PRFH_i_p_ai_s:
+    case PRFW_i_p_ai_s:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEContiguousPrefetch_ScalarPlusImm(
+    const Instruction* instr) {
+  switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusImmMask)) {
+    // Ignore prefetch hint instructions.
+    case PRFB_i_p_bi_s:
+    case PRFD_i_p_bi_s:
+    case PRFH_i_p_bi_s:
+    case PRFW_i_p_bi_s:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEContiguousPrefetch_ScalarPlusScalar(
+    const Instruction* instr) {
+  switch (instr->Mask(SVEContiguousPrefetch_ScalarPlusScalarMask)) {
+    // Ignore prefetch hint instructions.
+    case PRFB_i_p_br_s:
+    case PRFD_i_p_br_s:
+    case PRFH_i_p_br_s:
+    case PRFW_i_p_br_s:
+      if (instr->GetRm() == kZeroRegCode) {
+        VIXL_UNIMPLEMENTED();
+      }
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVELoadAndBroadcastElement(const Instruction* instr) {
+  bool is_signed;
+  switch (instr->Mask(SVELoadAndBroadcastElementMask)) {
+    case LD1RB_z_p_bi_u8:
+    case LD1RB_z_p_bi_u16:
+    case LD1RB_z_p_bi_u32:
+    case LD1RB_z_p_bi_u64:
+    case LD1RH_z_p_bi_u16:
+    case LD1RH_z_p_bi_u32:
+    case LD1RH_z_p_bi_u64:
+    case LD1RW_z_p_bi_u32:
+    case LD1RW_z_p_bi_u64:
+    case LD1RD_z_p_bi_u64:
+      is_signed = false;
+      break;
+    case LD1RSB_z_p_bi_s16:
+    case LD1RSB_z_p_bi_s32:
+    case LD1RSB_z_p_bi_s64:
+    case LD1RSH_z_p_bi_s32:
+    case LD1RSH_z_p_bi_s64:
+    case LD1RSW_z_p_bi_s64:
+      is_signed = true;
+      break;
+    default:
+      // This encoding group is complete, so no other values should be possible.
+      VIXL_UNREACHABLE();
+      is_signed = false;
+      break;
+  }
+
+  int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
+  int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed, 13);
+  VIXL_ASSERT(msize_in_bytes_log2 <= esize_in_bytes_log2);
+  VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2);
+  uint64_t offset = instr->ExtractBits(21, 16) << msize_in_bytes_log2;
+  uint64_t base = ReadXRegister(instr->GetRn()) + offset;
+  VectorFormat unpack_vform =
+      SVEFormatFromLaneSizeInBytesLog2(msize_in_bytes_log2);
+  SimVRegister temp;
+  ld1r(vform, unpack_vform, temp, base, is_signed);
+  mov_zeroing(vform,
+              ReadVRegister(instr->GetRt()),
+              ReadPRegister(instr->GetPgLow8()),
+              temp);
+}
+
+void Simulator::VisitSVELoadPredicateRegister(const Instruction* instr) {
+  switch (instr->Mask(SVELoadPredicateRegisterMask)) {
+    case LDR_p_bi: {
+      SimPRegister& pt = ReadPRegister(instr->GetPt());
+      int pl = GetPredicateLengthInBytes();
+      int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10);
+      uint64_t multiplier = ExtractSignedBitfield64(8, 0, imm9);
+      uint64_t address = ReadXRegister(instr->GetRn()) + multiplier * pl;
+      for (int i = 0; i < pl; i++) {
+        pt.Insert(i, MemRead<uint8_t>(address + i));
+      }
+      LogPRead(instr->GetPt(), address);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVELoadVectorRegister(const Instruction* instr) {
+  switch (instr->Mask(SVELoadVectorRegisterMask)) {
+    case LDR_z_bi: {
+      SimVRegister& zt = ReadVRegister(instr->GetRt());
+      int vl = GetVectorLengthInBytes();
+      int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10);
+      uint64_t multiplier = ExtractSignedBitfield64(8, 0, imm9);
+      uint64_t address = ReadXRegister(instr->GetRn()) + multiplier * vl;
+      for (int i = 0; i < vl; i++) {
+        zt.Insert(i, MemRead<uint8_t>(address + i));
+      }
+      LogZRead(instr->GetRt(), address);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(
+      SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask)) {
+    case LD1D_z_p_bz_d_x32_scaled:
+    case LD1H_z_p_bz_d_x32_scaled:
+    case LD1SH_z_p_bz_d_x32_scaled:
+    case LD1SW_z_p_bz_d_x32_scaled:
+    case LD1W_z_p_bz_d_x32_scaled:
+    case LDFF1H_z_p_bz_d_x32_scaled:
+    case LDFF1W_z_p_bz_d_x32_scaled:
+    case LDFF1D_z_p_bz_d_x32_scaled:
+    case LDFF1SH_z_p_bz_d_x32_scaled:
+    case LDFF1SW_z_p_bz_d_x32_scaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
+  SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, mod);
+}
+
+void Simulator::VisitSVE64BitGatherLoad_ScalarPlus64BitScaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask)) {
+    case LD1D_z_p_bz_d_64_scaled:
+    case LD1H_z_p_bz_d_64_scaled:
+    case LD1SH_z_p_bz_d_64_scaled:
+    case LD1SW_z_p_bz_d_64_scaled:
+    case LD1W_z_p_bz_d_64_scaled:
+    case LDFF1H_z_p_bz_d_64_scaled:
+    case LDFF1W_z_p_bz_d_64_scaled:
+    case LDFF1D_z_p_bz_d_64_scaled:
+    case LDFF1SH_z_p_bz_d_64_scaled:
+    case LDFF1SW_z_p_bz_d_64_scaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, SVE_LSL);
+}
+
+void Simulator::VisitSVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask)) {
+    case LD1B_z_p_bz_d_64_unscaled:
+    case LD1D_z_p_bz_d_64_unscaled:
+    case LD1H_z_p_bz_d_64_unscaled:
+    case LD1SB_z_p_bz_d_64_unscaled:
+    case LD1SH_z_p_bz_d_64_unscaled:
+    case LD1SW_z_p_bz_d_64_unscaled:
+    case LD1W_z_p_bz_d_64_unscaled:
+    case LDFF1B_z_p_bz_d_64_unscaled:
+    case LDFF1D_z_p_bz_d_64_unscaled:
+    case LDFF1H_z_p_bz_d_64_unscaled:
+    case LDFF1SB_z_p_bz_d_64_unscaled:
+    case LDFF1SH_z_p_bz_d_64_unscaled:
+    case LDFF1SW_z_p_bz_d_64_unscaled:
+    case LDFF1W_z_p_bz_d_64_unscaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SVEGatherLoadScalarPlusVectorHelper(instr,
+                                      kFormatVnD,
+                                      NO_SVE_OFFSET_MODIFIER);
+}
+
+void Simulator::VisitSVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(
+      SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask)) {
+    case LD1B_z_p_bz_d_x32_unscaled:
+    case LD1D_z_p_bz_d_x32_unscaled:
+    case LD1H_z_p_bz_d_x32_unscaled:
+    case LD1SB_z_p_bz_d_x32_unscaled:
+    case LD1SH_z_p_bz_d_x32_unscaled:
+    case LD1SW_z_p_bz_d_x32_unscaled:
+    case LD1W_z_p_bz_d_x32_unscaled:
+    case LDFF1B_z_p_bz_d_x32_unscaled:
+    case LDFF1H_z_p_bz_d_x32_unscaled:
+    case LDFF1W_z_p_bz_d_x32_unscaled:
+    case LDFF1D_z_p_bz_d_x32_unscaled:
+    case LDFF1SB_z_p_bz_d_x32_unscaled:
+    case LDFF1SH_z_p_bz_d_x32_unscaled:
+    case LDFF1SW_z_p_bz_d_x32_unscaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  SVEOffsetModifier mod = (instr->ExtractBit(22) == 1) ? SVE_SXTW : SVE_UXTW;
+  SVEGatherLoadScalarPlusVectorHelper(instr, kFormatVnD, mod);
+}
+
+void Simulator::VisitSVE64BitGatherLoad_VectorPlusImm(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE64BitGatherLoad_VectorPlusImmMask)) {
+    case LD1B_z_p_ai_d:
+    case LD1D_z_p_ai_d:
+    case LD1H_z_p_ai_d:
+    case LD1SB_z_p_ai_d:
+    case LD1SH_z_p_ai_d:
+    case LD1SW_z_p_ai_d:
+    case LD1W_z_p_ai_d:
+    case LDFF1B_z_p_ai_d:
+    case LDFF1D_z_p_ai_d:
+    case LDFF1H_z_p_ai_d:
+    case LDFF1SB_z_p_ai_d:
+    case LDFF1SH_z_p_ai_d:
+    case LDFF1SW_z_p_ai_d:
+    case LDFF1W_z_p_ai_d:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  bool is_signed = instr->ExtractBit(14) == 0;
+  bool is_ff = instr->ExtractBit(13) == 1;
+  // Note that these instructions don't use the Dtype encoding.
+  int msize_in_bytes_log2 = instr->ExtractBits(24, 23);
+  uint64_t imm = instr->ExtractBits(20, 16) << msize_in_bytes_log2;
+  LogicSVEAddressVector addr(imm, &ReadVRegister(instr->GetRn()), kFormatVnD);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  if (is_ff) {
+    VIXL_UNIMPLEMENTED();
+  } else {
+    SVEStructuredLoadHelper(kFormatVnD,
+                            ReadPRegister(instr->GetPgLow8()),
+                            instr->GetRt(),
+                            addr,
+                            is_signed);
+  }
+}
+
+void Simulator::VisitSVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsets(
+    const Instruction* instr) {
+  switch (
+      instr->Mask(SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask)) {
+    // Ignore prefetch hint instructions.
+    case PRFB_i_p_bz_d_64_scaled:
+    case PRFD_i_p_bz_d_64_scaled:
+    case PRFH_i_p_bz_d_64_scaled:
+    case PRFW_i_p_bz_d_64_scaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::
+    VisitSVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsets(
+        const Instruction* instr) {
+  switch (instr->Mask(
+      SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask)) {
+    // Ignore prefetch hint instructions.
+    case PRFB_i_p_bz_d_x32_scaled:
+    case PRFD_i_p_bz_d_x32_scaled:
+    case PRFH_i_p_bz_d_x32_scaled:
+    case PRFW_i_p_bz_d_x32_scaled:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE64BitGatherPrefetch_VectorPlusImm(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE64BitGatherPrefetch_VectorPlusImmMask)) {
+    // Ignore prefetch hint instructions.
+    case PRFB_i_p_ai_d:
+    case PRFD_i_p_ai_d:
+    case PRFH_i_p_ai_d:
+    case PRFW_i_p_ai_d:
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEContiguousFirstFaultLoad_ScalarPlusScalar(
+    const Instruction* instr) {
+  bool is_signed;
+  switch (instr->Mask(SVEContiguousLoad_ScalarPlusScalarMask)) {
+    case LDFF1B_z_p_br_u8:
+    case LDFF1B_z_p_br_u16:
+    case LDFF1B_z_p_br_u32:
+    case LDFF1B_z_p_br_u64:
+    case LDFF1H_z_p_br_u16:
+    case LDFF1H_z_p_br_u32:
+    case LDFF1H_z_p_br_u64:
+    case LDFF1W_z_p_br_u32:
+    case LDFF1W_z_p_br_u64:
+    case LDFF1D_z_p_br_u64:
+      is_signed = false;
+      break;
+    case LDFF1SB_z_p_br_s16:
+    case LDFF1SB_z_p_br_s32:
+    case LDFF1SB_z_p_br_s64:
+    case LDFF1SH_z_p_br_s32:
+    case LDFF1SH_z_p_br_s64:
+    case LDFF1SW_z_p_br_s64:
+      is_signed = true;
+      break;
+    default:
+      // This encoding group is complete, so no other values should be possible.
+      VIXL_UNREACHABLE();
+      is_signed = false;
+      break;
+  }
+
+  int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
+  int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed);
+  VIXL_ASSERT(msize_in_bytes_log2 <= esize_in_bytes_log2);
+  VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2);
+  uint64_t offset = ReadXRegister(instr->GetRm());
+  offset <<= msize_in_bytes_log2;
+  LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  SVEFaultTolerantLoadHelper(vform,
+                             ReadPRegister(instr->GetPgLow8()),
+                             instr->GetRt(),
+                             addr,
+                             kSVEFirstFaultLoad,
+                             is_signed);
+}
+
+void Simulator::VisitSVEContiguousNonFaultLoad_ScalarPlusImm(
+    const Instruction* instr) {
+  bool is_signed = false;
+  switch (instr->Mask(SVEContiguousNonFaultLoad_ScalarPlusImmMask)) {
+    case LDNF1B_z_p_bi_u16:
+    case LDNF1B_z_p_bi_u32:
+    case LDNF1B_z_p_bi_u64:
+    case LDNF1B_z_p_bi_u8:
+    case LDNF1D_z_p_bi_u64:
+    case LDNF1H_z_p_bi_u16:
+    case LDNF1H_z_p_bi_u32:
+    case LDNF1H_z_p_bi_u64:
+    case LDNF1W_z_p_bi_u32:
+    case LDNF1W_z_p_bi_u64:
+      break;
+    case LDNF1SB_z_p_bi_s16:
+    case LDNF1SB_z_p_bi_s32:
+    case LDNF1SB_z_p_bi_s64:
+    case LDNF1SH_z_p_bi_s32:
+    case LDNF1SH_z_p_bi_s64:
+    case LDNF1SW_z_p_bi_s64:
+      is_signed = true;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
+  int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed);
+  VIXL_ASSERT(msize_in_bytes_log2 <= esize_in_bytes_log2);
+  VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2);
+  int vl = GetVectorLengthInBytes();
+  int vl_divisor_log2 = esize_in_bytes_log2 - msize_in_bytes_log2;
+  uint64_t offset =
+      (instr->ExtractSignedBits(19, 16) * vl) / (1 << vl_divisor_log2);
+  LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  SVEFaultTolerantLoadHelper(vform,
+                             ReadPRegister(instr->GetPgLow8()),
+                             instr->GetRt(),
+                             addr,
+                             kSVENonFaultLoad,
+                             is_signed);
+}
+
+void Simulator::VisitSVEContiguousNonTemporalLoad_ScalarPlusImm(
+    const Instruction* instr) {
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  VectorFormat vform = kFormatUndefined;
+
+  switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusImmMask)) {
+    case LDNT1B_z_p_bi_contiguous:
+      vform = kFormatVnB;
+      break;
+    case LDNT1D_z_p_bi_contiguous:
+      vform = kFormatVnD;
+      break;
+    case LDNT1H_z_p_bi_contiguous:
+      vform = kFormatVnH;
+      break;
+    case LDNT1W_z_p_bi_contiguous:
+      vform = kFormatVnS;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  int msize_in_bytes_log2 = LaneSizeInBytesLog2FromFormat(vform);
+  int vl = GetVectorLengthInBytes();
+  uint64_t offset = instr->ExtractSignedBits(19, 16) * vl;
+  LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  SVEStructuredLoadHelper(vform,
+                          pg,
+                          instr->GetRt(),
+                          addr,
+                          /* is_signed = */ false);
+}
+
+void Simulator::VisitSVEContiguousNonTemporalLoad_ScalarPlusScalar(
+    const Instruction* instr) {
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  VectorFormat vform = kFormatUndefined;
+
+  switch (instr->Mask(SVEContiguousNonTemporalLoad_ScalarPlusScalarMask)) {
+    case LDNT1B_z_p_br_contiguous:
+      vform = kFormatVnB;
+      break;
+    case LDNT1D_z_p_br_contiguous:
+      vform = kFormatVnD;
+      break;
+    case LDNT1H_z_p_br_contiguous:
+      vform = kFormatVnH;
+      break;
+    case LDNT1W_z_p_br_contiguous:
+      vform = kFormatVnS;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  int msize_in_bytes_log2 = LaneSizeInBytesLog2FromFormat(vform);
+  uint64_t offset = ReadXRegister(instr->GetRm()) << msize_in_bytes_log2;
+  LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  SVEStructuredLoadHelper(vform,
+                          pg,
+                          instr->GetRt(),
+                          addr,
+                          /* is_signed = */ false);
+}
+
+void Simulator::VisitSVELoadAndBroadcastQuadword_ScalarPlusImm(
+    const Instruction* instr) {
+  SimVRegister& zt = ReadVRegister(instr->GetRt());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  uint64_t addr = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
+  uint64_t offset = instr->ExtractSignedBits(19, 16) * 16;
+
+  VectorFormat vform = kFormatUndefined;
+  switch (instr->Mask(SVELoadAndBroadcastQuadword_ScalarPlusImmMask)) {
+    case LD1RQB_z_p_bi_u8:
+      vform = kFormatVnB;
+      break;
+    case LD1RQD_z_p_bi_u64:
+      vform = kFormatVnD;
+      break;
+    case LD1RQH_z_p_bi_u16:
+      vform = kFormatVnH;
+      break;
+    case LD1RQW_z_p_bi_u32:
+      vform = kFormatVnS;
+      break;
+    default:
+      addr = offset = 0;
+      break;
+  }
+  ld1(kFormat16B, zt, addr + offset);
+  mov_zeroing(vform, zt, pg, zt);
+  dup_element(kFormatVnQ, zt, zt, 0);
+}
+
+void Simulator::VisitSVELoadAndBroadcastQuadword_ScalarPlusScalar(
+    const Instruction* instr) {
+  SimVRegister& zt = ReadVRegister(instr->GetRt());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  uint64_t addr = ReadXRegister(instr->GetRn(), Reg31IsStackPointer);
+  uint64_t offset = ReadXRegister(instr->GetRm());
+
+  VectorFormat vform = kFormatUndefined;
+  switch (instr->Mask(SVELoadAndBroadcastQuadword_ScalarPlusScalarMask)) {
+    case LD1RQB_z_p_br_contiguous:
+      vform = kFormatVnB;
+      break;
+    case LD1RQD_z_p_br_contiguous:
+      vform = kFormatVnD;
+      offset <<= 3;
+      break;
+    case LD1RQH_z_p_br_contiguous:
+      vform = kFormatVnH;
+      offset <<= 1;
+      break;
+    case LD1RQW_z_p_br_contiguous:
+      vform = kFormatVnS;
+      offset <<= 2;
+      break;
+    default:
+      addr = offset = 0;
+      break;
+  }
+  ld1(kFormat16B, zt, addr + offset);
+  mov_zeroing(vform, zt, pg, zt);
+  dup_element(kFormatVnQ, zt, zt, 0);
+}
+
+void Simulator::VisitSVELoadMultipleStructures_ScalarPlusImm(
+    const Instruction* instr) {
+  switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusImmMask)) {
+    case LD2B_z_p_bi_contiguous:
+    case LD2D_z_p_bi_contiguous:
+    case LD2H_z_p_bi_contiguous:
+    case LD2W_z_p_bi_contiguous:
+    case LD3B_z_p_bi_contiguous:
+    case LD3D_z_p_bi_contiguous:
+    case LD3H_z_p_bi_contiguous:
+    case LD3W_z_p_bi_contiguous:
+    case LD4B_z_p_bi_contiguous:
+    case LD4D_z_p_bi_contiguous:
+    case LD4H_z_p_bi_contiguous:
+    case LD4W_z_p_bi_contiguous: {
+      int vl = GetVectorLengthInBytes();
+      int msz = instr->ExtractBits(24, 23);
+      int reg_count = instr->ExtractBits(22, 21) + 1;
+      uint64_t offset = instr->ExtractSignedBits(19, 16) * vl * reg_count;
+      LogicSVEAddressVector addr(
+          ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset);
+      addr.SetMsizeInBytesLog2(msz);
+      addr.SetRegCount(reg_count);
+      SVEStructuredLoadHelper(SVEFormatFromLaneSizeInBytesLog2(msz),
+                              ReadPRegister(instr->GetPgLow8()),
+                              instr->GetRt(),
+                              addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVELoadMultipleStructures_ScalarPlusScalar(
+    const Instruction* instr) {
+  switch (instr->Mask(SVELoadMultipleStructures_ScalarPlusScalarMask)) {
+    case LD2B_z_p_br_contiguous:
+    case LD2D_z_p_br_contiguous:
+    case LD2H_z_p_br_contiguous:
+    case LD2W_z_p_br_contiguous:
+    case LD3B_z_p_br_contiguous:
+    case LD3D_z_p_br_contiguous:
+    case LD3H_z_p_br_contiguous:
+    case LD3W_z_p_br_contiguous:
+    case LD4B_z_p_br_contiguous:
+    case LD4D_z_p_br_contiguous:
+    case LD4H_z_p_br_contiguous:
+    case LD4W_z_p_br_contiguous: {
+      int msz = instr->ExtractBits(24, 23);
+      uint64_t offset = ReadXRegister(instr->GetRm()) * (1 << msz);
+      VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(msz);
+      LogicSVEAddressVector addr(
+          ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset);
+      addr.SetMsizeInBytesLog2(msz);
+      addr.SetRegCount(instr->ExtractBits(22, 21) + 1);
+      SVEStructuredLoadHelper(vform,
+                              ReadPRegister(instr->GetPgLow8()),
+                              instr->GetRt(),
+                              addr,
+                              false);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE32BitScatterStore_ScalarPlus32BitScaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask)) {
+    case ST1H_z_p_bz_s_x32_scaled:
+    case ST1W_z_p_bz_s_x32_scaled: {
+      unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
+      VIXL_ASSERT(kDRegSizeInBytesLog2 >= msize_in_bytes_log2);
+      int scale = instr->ExtractBit(21) * msize_in_bytes_log2;
+      uint64_t base = ReadXRegister(instr->GetRn());
+      SVEOffsetModifier mod =
+          (instr->ExtractBit(14) == 1) ? SVE_SXTW : SVE_UXTW;
+      LogicSVEAddressVector addr(base,
+                                 &ReadVRegister(instr->GetRm()),
+                                 kFormatVnS,
+                                 mod,
+                                 scale);
+      addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+      SVEStructuredStoreHelper(kFormatVnS,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE32BitScatterStore_ScalarPlus32BitUnscaledOffsets(
+    const Instruction* instr) {
+  switch (
+      instr->Mask(SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask)) {
+    case ST1B_z_p_bz_s_x32_unscaled:
+    case ST1H_z_p_bz_s_x32_unscaled:
+    case ST1W_z_p_bz_s_x32_unscaled: {
+      unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
+      VIXL_ASSERT(kDRegSizeInBytesLog2 >= msize_in_bytes_log2);
+      uint64_t base = ReadXRegister(instr->GetRn());
+      SVEOffsetModifier mod =
+          (instr->ExtractBit(14) == 1) ? SVE_SXTW : SVE_UXTW;
+      LogicSVEAddressVector addr(base,
+                                 &ReadVRegister(instr->GetRm()),
+                                 kFormatVnS,
+                                 mod);
+      addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+      SVEStructuredStoreHelper(kFormatVnS,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE32BitScatterStore_VectorPlusImm(
+    const Instruction* instr) {
+  int msz = 0;
+  switch (instr->Mask(SVE32BitScatterStore_VectorPlusImmMask)) {
+    case ST1B_z_p_ai_s:
+      msz = 0;
+      break;
+    case ST1H_z_p_ai_s:
+      msz = 1;
+      break;
+    case ST1W_z_p_ai_s:
+      msz = 2;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  uint64_t imm = instr->ExtractBits(20, 16) << msz;
+  LogicSVEAddressVector addr(imm, &ReadVRegister(instr->GetRn()), kFormatVnS);
+  addr.SetMsizeInBytesLog2(msz);
+  SVEStructuredStoreHelper(kFormatVnS,
+                           ReadPRegister(instr->GetPgLow8()),
+                           instr->GetRt(),
+                           addr);
+}
+
+void Simulator::VisitSVE64BitScatterStore_ScalarPlus64BitScaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask)) {
+    case ST1D_z_p_bz_d_64_scaled:
+    case ST1H_z_p_bz_d_64_scaled:
+    case ST1W_z_p_bz_d_64_scaled: {
+      unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
+      VIXL_ASSERT(kDRegSizeInBytesLog2 >= msize_in_bytes_log2);
+      int scale = instr->ExtractBit(21) * msize_in_bytes_log2;
+      uint64_t base = ReadXRegister(instr->GetRn());
+      LogicSVEAddressVector addr(base,
+                                 &ReadVRegister(instr->GetRm()),
+                                 kFormatVnD,
+                                 SVE_LSL,
+                                 scale);
+      addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+      SVEStructuredStoreHelper(kFormatVnD,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE64BitScatterStore_ScalarPlus64BitUnscaledOffsets(
+    const Instruction* instr) {
+  switch (
+      instr->Mask(SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask)) {
+    case ST1B_z_p_bz_d_64_unscaled:
+    case ST1D_z_p_bz_d_64_unscaled:
+    case ST1H_z_p_bz_d_64_unscaled:
+    case ST1W_z_p_bz_d_64_unscaled: {
+      unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
+      VIXL_ASSERT(kDRegSizeInBytesLog2 >= msize_in_bytes_log2);
+      uint64_t base = ReadXRegister(instr->GetRn());
+      LogicSVEAddressVector addr(base,
+                                 &ReadVRegister(instr->GetRm()),
+                                 kFormatVnD,
+                                 NO_SVE_OFFSET_MODIFIER);
+      addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+      SVEStructuredStoreHelper(kFormatVnD,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsets(
+    const Instruction* instr) {
+  switch (instr->Mask(
+      SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask)) {
+    case ST1D_z_p_bz_d_x32_scaled:
+    case ST1H_z_p_bz_d_x32_scaled:
+    case ST1W_z_p_bz_d_x32_scaled: {
+      unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
+      VIXL_ASSERT(kDRegSizeInBytesLog2 >= msize_in_bytes_log2);
+      int scale = instr->ExtractBit(21) * msize_in_bytes_log2;
+      uint64_t base = ReadXRegister(instr->GetRn());
+      SVEOffsetModifier mod =
+          (instr->ExtractBit(14) == 1) ? SVE_SXTW : SVE_UXTW;
+      LogicSVEAddressVector addr(base,
+                                 &ReadVRegister(instr->GetRm()),
+                                 kFormatVnD,
+                                 mod,
+                                 scale);
+      addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+      SVEStructuredStoreHelper(kFormatVnD,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::
+    VisitSVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsets(
+        const Instruction* instr) {
+  switch (instr->Mask(
+      SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask)) {
+    case ST1B_z_p_bz_d_x32_unscaled:
+    case ST1D_z_p_bz_d_x32_unscaled:
+    case ST1H_z_p_bz_d_x32_unscaled:
+    case ST1W_z_p_bz_d_x32_unscaled: {
+      unsigned msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
+      VIXL_ASSERT(kDRegSizeInBytesLog2 >= msize_in_bytes_log2);
+      uint64_t base = ReadXRegister(instr->GetRn());
+      SVEOffsetModifier mod =
+          (instr->ExtractBit(14) == 1) ? SVE_SXTW : SVE_UXTW;
+      LogicSVEAddressVector addr(base,
+                                 &ReadVRegister(instr->GetRm()),
+                                 kFormatVnD,
+                                 mod);
+      addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+      SVEStructuredStoreHelper(kFormatVnD,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVE64BitScatterStore_VectorPlusImm(
+    const Instruction* instr) {
+  int msz = 0;
+  switch (instr->Mask(SVE64BitScatterStore_VectorPlusImmMask)) {
+    case ST1B_z_p_ai_d:
+      msz = 0;
+      break;
+    case ST1D_z_p_ai_d:
+      msz = 3;
+      break;
+    case ST1H_z_p_ai_d:
+      msz = 1;
+      break;
+    case ST1W_z_p_ai_d:
+      msz = 2;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  uint64_t imm = instr->ExtractBits(20, 16) << msz;
+  LogicSVEAddressVector addr(imm, &ReadVRegister(instr->GetRn()), kFormatVnD);
+  addr.SetMsizeInBytesLog2(msz);
+  SVEStructuredStoreHelper(kFormatVnD,
+                           ReadPRegister(instr->GetPgLow8()),
+                           instr->GetRt(),
+                           addr);
+}
+
+void Simulator::VisitSVEContiguousNonTemporalStore_ScalarPlusImm(
+    const Instruction* instr) {
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  VectorFormat vform = kFormatUndefined;
+
+  switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusImmMask)) {
+    case STNT1B_z_p_bi_contiguous:
+      vform = kFormatVnB;
+      break;
+    case STNT1D_z_p_bi_contiguous:
+      vform = kFormatVnD;
+      break;
+    case STNT1H_z_p_bi_contiguous:
+      vform = kFormatVnH;
+      break;
+    case STNT1W_z_p_bi_contiguous:
+      vform = kFormatVnS;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  int msize_in_bytes_log2 = LaneSizeInBytesLog2FromFormat(vform);
+  int vl = GetVectorLengthInBytes();
+  uint64_t offset = instr->ExtractSignedBits(19, 16) * vl;
+  LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  SVEStructuredStoreHelper(vform, pg, instr->GetRt(), addr);
+}
+
+void Simulator::VisitSVEContiguousNonTemporalStore_ScalarPlusScalar(
+    const Instruction* instr) {
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  VectorFormat vform = kFormatUndefined;
+
+  switch (instr->Mask(SVEContiguousNonTemporalStore_ScalarPlusScalarMask)) {
+    case STNT1B_z_p_br_contiguous:
+      vform = kFormatVnB;
+      break;
+    case STNT1D_z_p_br_contiguous:
+      vform = kFormatVnD;
+      break;
+    case STNT1H_z_p_br_contiguous:
+      vform = kFormatVnH;
+      break;
+    case STNT1W_z_p_br_contiguous:
+      vform = kFormatVnS;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  int msize_in_bytes_log2 = LaneSizeInBytesLog2FromFormat(vform);
+  uint64_t offset = ReadXRegister(instr->GetRm()) << msize_in_bytes_log2;
+  LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  SVEStructuredStoreHelper(vform, pg, instr->GetRt(), addr);
+}
+
+void Simulator::VisitSVEContiguousStore_ScalarPlusImm(
+    const Instruction* instr) {
+  switch (instr->Mask(SVEContiguousStore_ScalarPlusImmMask)) {
+    case ST1B_z_p_bi:
+    case ST1D_z_p_bi:
+    case ST1H_z_p_bi:
+    case ST1W_z_p_bi: {
+      int vl = GetVectorLengthInBytes();
+      int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(false);
+      int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(false);
+      VIXL_ASSERT(esize_in_bytes_log2 >= msize_in_bytes_log2);
+      int vl_divisor_log2 = esize_in_bytes_log2 - msize_in_bytes_log2;
+      uint64_t offset =
+          (instr->ExtractSignedBits(19, 16) * vl) / (1 << vl_divisor_log2);
+      VectorFormat vform =
+          SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2);
+      LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+      addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+      SVEStructuredStoreHelper(vform,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEContiguousStore_ScalarPlusScalar(
+    const Instruction* instr) {
+  switch (instr->Mask(SVEContiguousStore_ScalarPlusScalarMask)) {
+    case ST1B_z_p_br:
+    case ST1D_z_p_br:
+    case ST1H_z_p_br:
+    case ST1W_z_p_br: {
+      uint64_t offset = ReadXRegister(instr->GetRm());
+      offset <<= instr->ExtractBits(24, 23);
+      VectorFormat vform =
+          SVEFormatFromLaneSizeInBytesLog2(instr->ExtractBits(22, 21));
+      LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+      addr.SetMsizeInBytesLog2(instr->ExtractBits(24, 23));
+      SVEStructuredStoreHelper(vform,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVECopySIMDFPScalarRegisterToVector_Predicated(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister z_result;
+
+  switch (instr->Mask(SVECopySIMDFPScalarRegisterToVector_PredicatedMask)) {
+    case CPY_z_p_v:
+      dup_element(vform, z_result, ReadVRegister(instr->GetRn()), 0);
+      mov_merging(vform, ReadVRegister(instr->GetRd()), pg, z_result);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEStoreMultipleStructures_ScalarPlusImm(
+    const Instruction* instr) {
+  switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusImmMask)) {
+    case ST2B_z_p_bi_contiguous:
+    case ST2D_z_p_bi_contiguous:
+    case ST2H_z_p_bi_contiguous:
+    case ST2W_z_p_bi_contiguous:
+    case ST3B_z_p_bi_contiguous:
+    case ST3D_z_p_bi_contiguous:
+    case ST3H_z_p_bi_contiguous:
+    case ST3W_z_p_bi_contiguous:
+    case ST4B_z_p_bi_contiguous:
+    case ST4D_z_p_bi_contiguous:
+    case ST4H_z_p_bi_contiguous:
+    case ST4W_z_p_bi_contiguous: {
+      int vl = GetVectorLengthInBytes();
+      int msz = instr->ExtractBits(24, 23);
+      int reg_count = instr->ExtractBits(22, 21) + 1;
+      uint64_t offset = instr->ExtractSignedBits(19, 16) * vl * reg_count;
+      LogicSVEAddressVector addr(
+          ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset);
+      addr.SetMsizeInBytesLog2(msz);
+      addr.SetRegCount(reg_count);
+      SVEStructuredStoreHelper(SVEFormatFromLaneSizeInBytesLog2(msz),
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEStoreMultipleStructures_ScalarPlusScalar(
+    const Instruction* instr) {
+  switch (instr->Mask(SVEStoreMultipleStructures_ScalarPlusScalarMask)) {
+    case ST2B_z_p_br_contiguous:
+    case ST2D_z_p_br_contiguous:
+    case ST2H_z_p_br_contiguous:
+    case ST2W_z_p_br_contiguous:
+    case ST3B_z_p_br_contiguous:
+    case ST3D_z_p_br_contiguous:
+    case ST3H_z_p_br_contiguous:
+    case ST3W_z_p_br_contiguous:
+    case ST4B_z_p_br_contiguous:
+    case ST4D_z_p_br_contiguous:
+    case ST4H_z_p_br_contiguous:
+    case ST4W_z_p_br_contiguous: {
+      int msz = instr->ExtractBits(24, 23);
+      uint64_t offset = ReadXRegister(instr->GetRm()) * (1 << msz);
+      VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(msz);
+      LogicSVEAddressVector addr(
+          ReadXRegister(instr->GetRn(), Reg31IsStackPointer) + offset);
+      addr.SetMsizeInBytesLog2(msz);
+      addr.SetRegCount(instr->ExtractBits(22, 21) + 1);
+      SVEStructuredStoreHelper(vform,
+                               ReadPRegister(instr->GetPgLow8()),
+                               instr->GetRt(),
+                               addr);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEStorePredicateRegister(const Instruction* instr) {
+  switch (instr->Mask(SVEStorePredicateRegisterMask)) {
+    case STR_p_bi: {
+      SimPRegister& pt = ReadPRegister(instr->GetPt());
+      int pl = GetPredicateLengthInBytes();
+      int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10);
+      uint64_t multiplier = ExtractSignedBitfield64(8, 0, imm9);
+      uint64_t address = ReadXRegister(instr->GetRn()) + multiplier * pl;
+      for (int i = 0; i < pl; i++) {
+        MemWrite(address + i, pt.GetLane<uint8_t>(i));
+      }
+      LogPWrite(instr->GetPt(), address);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEStoreVectorRegister(const Instruction* instr) {
+  switch (instr->Mask(SVEStoreVectorRegisterMask)) {
+    case STR_z_bi: {
+      SimVRegister& zt = ReadVRegister(instr->GetRt());
+      int vl = GetVectorLengthInBytes();
+      int imm9 = (instr->ExtractBits(21, 16) << 3) | instr->ExtractBits(12, 10);
+      uint64_t multiplier = ExtractSignedBitfield64(8, 0, imm9);
+      uint64_t address = ReadXRegister(instr->GetRn()) + multiplier * vl;
+      for (int i = 0; i < vl; i++) {
+        MemWrite(address + i, zt.GetLane<uint8_t>(i));
+      }
+      LogZWrite(instr->GetRt(), address);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEMulIndex(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zda = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+
+  switch (instr->Mask(SVEMulIndexMask)) {
+    case SDOT_z_zzzi_d:
+      sdot(vform,
+           zda,
+           zn,
+           ReadVRegister(instr->ExtractBits(19, 16)),
+           instr->ExtractBit(20));
+      break;
+    case SDOT_z_zzzi_s:
+      sdot(vform,
+           zda,
+           zn,
+           ReadVRegister(instr->ExtractBits(18, 16)),
+           instr->ExtractBits(20, 19));
+      break;
+    case UDOT_z_zzzi_d:
+      udot(vform,
+           zda,
+           zn,
+           ReadVRegister(instr->ExtractBits(19, 16)),
+           instr->ExtractBit(20));
+      break;
+    case UDOT_z_zzzi_s:
+      udot(vform,
+           zda,
+           zn,
+           ReadVRegister(instr->ExtractBits(18, 16)),
+           instr->ExtractBits(20, 19));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEPartitionBreakCondition(const Instruction* instr) {
+  SimPRegister& pd = ReadPRegister(instr->GetPd());
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
+  SimPRegister& pn = ReadPRegister(instr->GetPn());
+  SimPRegister result;
+
+  switch (instr->Mask(SVEPartitionBreakConditionMask)) {
+    case BRKAS_p_p_p_z:
+    case BRKA_p_p_p:
+      brka(result, pg, pn);
+      break;
+    case BRKBS_p_p_p_z:
+    case BRKB_p_p_p:
+      brkb(result, pg, pn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (instr->ExtractBit(4) == 1) {
+    mov_merging(pd, pg, result);
+  } else {
+    mov_zeroing(pd, pg, result);
+  }
+
+  // Set flag if needed.
+  if (instr->ExtractBit(22) == 1) {
+    PredTest(kFormatVnB, pg, pd);
+  }
+}
+
+void Simulator::VisitSVEPropagateBreakToNextPartition(
+    const Instruction* instr) {
+  SimPRegister& pdm = ReadPRegister(instr->GetPd());
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
+  SimPRegister& pn = ReadPRegister(instr->GetPn());
+
+  switch (instr->Mask(SVEPropagateBreakToNextPartitionMask)) {
+    case BRKNS_p_p_pp:
+    case BRKN_p_p_pp:
+      brkn(pdm, pg, pn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  // Set flag if needed.
+  if (instr->ExtractBit(22) == 1) {
+    // Note that this ignores `pg`.
+    PredTest(kFormatVnB, GetPTrue(), pdm);
+  }
+}
+
+void Simulator::VisitSVEUnpackPredicateElements(const Instruction* instr) {
+  SimPRegister& pd = ReadPRegister(instr->GetPd());
+  SimPRegister& pn = ReadPRegister(instr->GetPn());
+
+  SimVRegister temp = Simulator::ExpandToSimVRegister(pn);
+  SimVRegister zero;
+  dup_immediate(kFormatVnB, zero, 0);
+
+  switch (instr->Mask(SVEUnpackPredicateElementsMask)) {
+    case PUNPKHI_p_p:
+      zip2(kFormatVnB, temp, temp, zero);
+      break;
+    case PUNPKLO_p_p:
+      zip1(kFormatVnB, temp, temp, zero);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp);
+}
+
+void Simulator::VisitSVEPermutePredicateElements(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimPRegister& pd = ReadPRegister(instr->GetPd());
+  SimPRegister& pn = ReadPRegister(instr->GetPn());
+  SimPRegister& pm = ReadPRegister(instr->GetPm());
+
+  SimVRegister temp0 = Simulator::ExpandToSimVRegister(pn);
+  SimVRegister temp1 = Simulator::ExpandToSimVRegister(pm);
+
+  switch (instr->Mask(SVEPermutePredicateElementsMask)) {
+    case TRN1_p_pp:
+      trn1(vform, temp0, temp0, temp1);
+      break;
+    case TRN2_p_pp:
+      trn2(vform, temp0, temp0, temp1);
+      break;
+    case UZP1_p_pp:
+      uzp1(vform, temp0, temp0, temp1);
+      break;
+    case UZP2_p_pp:
+      uzp2(vform, temp0, temp0, temp1);
+      break;
+    case ZIP1_p_pp:
+      zip1(vform, temp0, temp0, temp1);
+      break;
+    case ZIP2_p_pp:
+      zip2(vform, temp0, temp0, temp1);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+  Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp0);
+}
+
+void Simulator::VisitSVEReversePredicateElements(const Instruction* instr) {
+  switch (instr->Mask(SVEReversePredicateElementsMask)) {
+    case REV_p_p: {
+      VectorFormat vform = instr->GetSVEVectorFormat();
+      SimPRegister& pn = ReadPRegister(instr->GetPn());
+      SimPRegister& pd = ReadPRegister(instr->GetPd());
+      SimVRegister temp = Simulator::ExpandToSimVRegister(pn);
+      rev(vform, temp, temp);
+      Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEPermuteVectorExtract(const Instruction* instr) {
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  // Second source register "Zm" is encoded where "Zn" would usually be.
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+
+  const int imm8h_mask = 0x001F0000;
+  const int imm8l_mask = 0x00001C00;
+  int index = instr->ExtractBits<imm8h_mask | imm8l_mask>();
+  int vl = GetVectorLengthInBytes();
+  index = (index >= vl) ? 0 : index;
+
+  switch (instr->Mask(SVEPermuteVectorExtractMask)) {
+    case EXT_z_zi_des:
+      ext(kFormatVnB, zdn, zdn, zm, index);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEPermuteVectorInterleaving(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+
+  switch (instr->Mask(SVEPermuteVectorInterleavingMask)) {
+    case TRN1_z_zz:
+      trn1(vform, zd, zn, zm);
+      break;
+    case TRN2_z_zz:
+      trn2(vform, zd, zn, zm);
+      break;
+    case UZP1_z_zz:
+      uzp1(vform, zd, zn, zm);
+      break;
+    case UZP2_z_zz:
+      uzp2(vform, zd, zn, zm);
+      break;
+    case ZIP1_z_zz:
+      zip1(vform, zd, zn, zm);
+      break;
+    case ZIP2_z_zz:
+      zip2(vform, zd, zn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEConditionallyBroadcastElementToVector(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  int active_offset = -1;
+  switch (instr->Mask(SVEConditionallyBroadcastElementToVectorMask)) {
+    case CLASTA_z_p_zz:
+      active_offset = 1;
+      break;
+    case CLASTB_z_p_zz:
+      active_offset = 0;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (active_offset >= 0) {
+    std::pair<bool, uint64_t> value = clast(vform, pg, zm, active_offset);
+    if (value.first) {
+      dup_immediate(vform, zdn, value.second);
+    } else {
+      // Trigger a line of trace for the operation, even though it doesn't
+      // change the register value.
+      mov(vform, zdn, zdn);
+    }
+  }
+}
+
+void Simulator::VisitSVEConditionallyExtractElementToSIMDFPScalar(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& vdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  int active_offset = -1;
+  switch (instr->Mask(SVEConditionallyExtractElementToSIMDFPScalarMask)) {
+    case CLASTA_v_p_z:
+      active_offset = 1;
+      break;
+    case CLASTB_v_p_z:
+      active_offset = 0;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (active_offset >= 0) {
+    LogicVRegister dst(vdn);
+    uint64_t src1_value = dst.Uint(vform, 0);
+    std::pair<bool, uint64_t> src2_value = clast(vform, pg, zm, active_offset);
+    dup_immediate(vform, vdn, 0);
+    dst.SetUint(vform, 0, src2_value.first ? src2_value.second : src1_value);
+  }
+}
+
+void Simulator::VisitSVEConditionallyExtractElementToGeneralRegister(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  int active_offset = -1;
+  switch (instr->Mask(SVEConditionallyExtractElementToGeneralRegisterMask)) {
+    case CLASTA_r_p_z:
+      active_offset = 1;
+      break;
+    case CLASTB_r_p_z:
+      active_offset = 0;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (active_offset >= 0) {
+    std::pair<bool, uint64_t> value = clast(vform, pg, zm, active_offset);
+    uint64_t masked_src = ReadXRegister(instr->GetRd()) &
+                          GetUintMask(LaneSizeInBitsFromFormat(vform));
+    WriteXRegister(instr->GetRd(), value.first ? value.second : masked_src);
+  }
+}
+
+void Simulator::VisitSVEExtractElementToSIMDFPScalarRegister(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& vdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  int active_offset = -1;
+  switch (instr->Mask(SVEExtractElementToSIMDFPScalarRegisterMask)) {
+    case LASTA_v_p_z:
+      active_offset = 1;
+      break;
+    case LASTB_v_p_z:
+      active_offset = 0;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (active_offset >= 0) {
+    LogicVRegister dst(vdn);
+    std::pair<bool, uint64_t> value = clast(vform, pg, zm, active_offset);
+    dup_immediate(vform, vdn, 0);
+    dst.SetUint(vform, 0, value.second);
+  }
+}
+
+void Simulator::VisitSVEExtractElementToGeneralRegister(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  int active_offset = -1;
+  switch (instr->Mask(SVEExtractElementToGeneralRegisterMask)) {
+    case LASTA_r_p_z:
+      active_offset = 1;
+      break;
+    case LASTB_r_p_z:
+      active_offset = 0;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (active_offset >= 0) {
+    std::pair<bool, uint64_t> value = clast(vform, pg, zm, active_offset);
+    WriteXRegister(instr->GetRd(), value.second);
+  }
+}
+
+void Simulator::VisitSVECompressActiveElements(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  switch (instr->Mask(SVECompressActiveElementsMask)) {
+    case COMPACT_z_p_z:
+      compact(vform, zd, pg, zn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVECopyGeneralRegisterToVector_Predicated(
+    const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister z_result;
+
+  switch (instr->Mask(SVECopyGeneralRegisterToVector_PredicatedMask)) {
+    case CPY_z_p_r:
+      dup_immediate(vform,
+                    z_result,
+                    ReadXRegister(instr->GetRn(), Reg31IsStackPointer));
+      mov_merging(vform, ReadVRegister(instr->GetRd()), pg, z_result);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVECopyIntImm_Predicated(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(19, 16));
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+
+  SimVRegister result;
+  switch (instr->Mask(SVECopyIntImm_PredicatedMask)) {
+    case CPY_z_p_i: {
+      // Use unsigned arithmetic to avoid undefined behaviour during the shift.
+      uint64_t imm8 = instr->GetImmSVEIntWideSigned();
+      dup_immediate(vform, result, imm8 << (instr->ExtractBit(13) * 8));
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (instr->ExtractBit(14) != 0) {
+    mov_merging(vform, zd, pg, result);
+  } else {
+    mov_zeroing(vform, zd, pg, result);
+  }
+}
+
+void Simulator::VisitSVEReverseWithinElements(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+  SimVRegister result;
+
+  // In NEON, the chunk size in which elements are REVersed is in the
+  // instruction mnemonic, and the element size attached to the register.
+  // SVE reverses the semantics; the mapping to logic functions below is to
+  // account for this.
+  VectorFormat chunk_form = instr->GetSVEVectorFormat();
+  VectorFormat element_form = kFormatUndefined;
+
+  switch (instr->Mask(SVEReverseWithinElementsMask)) {
+    case RBIT_z_p_z:
+      rbit(chunk_form, result, zn);
+      break;
+    case REVB_z_z:
+      VIXL_ASSERT((chunk_form == kFormatVnH) || (chunk_form == kFormatVnS) ||
+                  (chunk_form == kFormatVnD));
+      element_form = kFormatVnB;
+      break;
+    case REVH_z_z:
+      VIXL_ASSERT((chunk_form == kFormatVnS) || (chunk_form == kFormatVnD));
+      element_form = kFormatVnH;
+      break;
+    case REVW_z_z:
+      VIXL_ASSERT(chunk_form == kFormatVnD);
+      element_form = kFormatVnS;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (instr->Mask(SVEReverseWithinElementsMask) != RBIT_z_p_z) {
+    VIXL_ASSERT(element_form != kFormatUndefined);
+    switch (chunk_form) {
+      case kFormatVnH:
+        rev16(element_form, result, zn);
+        break;
+      case kFormatVnS:
+        rev32(element_form, result, zn);
+        break;
+      case kFormatVnD:
+        rev64(element_form, result, zn);
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+    }
+  }
+
+  mov_merging(chunk_form, zd, pg, result);
+}
+
+void Simulator::VisitSVEVectorSplice_Destructive(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zdn = ReadVRegister(instr->GetRd());
+  SimVRegister& zm = ReadVRegister(instr->GetRn());
+  SimPRegister& pg = ReadPRegister(instr->GetPgLow8());
+
+  switch (instr->Mask(SVEVectorSplice_DestructiveMask)) {
+    case SPLICE_z_p_zz_des:
+      splice(vform, zdn, pg, zdn, zm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEBroadcastGeneralRegister(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  switch (instr->Mask(SVEBroadcastGeneralRegisterMask)) {
+    case DUP_z_r:
+      dup_immediate(instr->GetSVEVectorFormat(),
+                    zd,
+                    ReadXRegister(instr->GetRn(), Reg31IsStackPointer));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEInsertSIMDFPScalarRegister(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  switch (instr->Mask(SVEInsertSIMDFPScalarRegisterMask)) {
+    case INSR_z_v:
+      insr(vform, zd, ReadDRegisterBits(instr->GetRn()));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEInsertGeneralRegister(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  switch (instr->Mask(SVEInsertGeneralRegisterMask)) {
+    case INSR_z_r:
+      insr(vform, zd, ReadXRegister(instr->GetRn()));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEBroadcastIndexElement(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  switch (instr->Mask(SVEBroadcastIndexElementMask)) {
+    case DUP_z_zi: {
+      std::pair<int, int> index_and_lane_size =
+          instr->GetSVEPermuteIndexAndLaneSizeLog2();
+      int index = index_and_lane_size.first;
+      int lane_size_in_bytes_log_2 = index_and_lane_size.second;
+      VectorFormat vform =
+          SVEFormatFromLaneSizeInBytesLog2(lane_size_in_bytes_log_2);
+      if ((index < 0) || (index >= LaneCountFromFormat(vform))) {
+        // Out of bounds, set the destination register to zero.
+        dup_immediate(kFormatVnD, zd, 0);
+      } else {
+        dup_element(vform, zd, ReadVRegister(instr->GetRn()), index);
+      }
+      return;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEReverseVectorElements(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  switch (instr->Mask(SVEReverseVectorElementsMask)) {
+    case REV_z_z:
+      rev(vform, zd, ReadVRegister(instr->GetRn()));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEUnpackVectorElements(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  switch (instr->Mask(SVEUnpackVectorElementsMask)) {
+    case SUNPKHI_z_z:
+      unpk(vform, zd, ReadVRegister(instr->GetRn()), kHiHalf, kSignedExtend);
+      break;
+    case SUNPKLO_z_z:
+      unpk(vform, zd, ReadVRegister(instr->GetRn()), kLoHalf, kSignedExtend);
+      break;
+    case UUNPKHI_z_z:
+      unpk(vform, zd, ReadVRegister(instr->GetRn()), kHiHalf, kUnsignedExtend);
+      break;
+    case UUNPKLO_z_z:
+      unpk(vform, zd, ReadVRegister(instr->GetRn()), kLoHalf, kUnsignedExtend);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVETableLookup(const Instruction* instr) {
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  switch (instr->Mask(SVETableLookupMask)) {
+    case TBL_z_zz_1:
+      Table(instr->GetSVEVectorFormat(),
+            zd,
+            ReadVRegister(instr->GetRn()),
+            ReadVRegister(instr->GetRm()));
+      return;
+    default:
+      break;
+  }
+}
+
+void Simulator::VisitSVEPredicateCount(const Instruction* instr) {
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
+  SimPRegister& pn = ReadPRegister(instr->GetPn());
+
+  switch (instr->Mask(SVEPredicateCountMask)) {
+    case CNTP_r_p_p: {
+      WriteXRegister(instr->GetRd(), CountActiveAndTrueLanes(vform, pg, pn));
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEPredicateLogical(const Instruction* instr) {
+  Instr op = instr->Mask(SVEPredicateLogicalMask);
+  SimPRegister& pd = ReadPRegister(instr->GetPd());
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
+  SimPRegister& pn = ReadPRegister(instr->GetPn());
+  SimPRegister& pm = ReadPRegister(instr->GetPm());
+  SimPRegister result;
+  switch (op) {
+    case ANDS_p_p_pp_z:
+    case AND_p_p_pp_z:
+    case BICS_p_p_pp_z:
+    case BIC_p_p_pp_z:
+    case EORS_p_p_pp_z:
+    case EOR_p_p_pp_z:
+    case NANDS_p_p_pp_z:
+    case NAND_p_p_pp_z:
+    case NORS_p_p_pp_z:
+    case NOR_p_p_pp_z:
+    case ORNS_p_p_pp_z:
+    case ORN_p_p_pp_z:
+    case ORRS_p_p_pp_z:
+    case ORR_p_p_pp_z:
+      SVEPredicateLogicalHelper(static_cast<SVEPredicateLogicalOp>(op),
+                                result,
+                                pn,
+                                pm);
+      break;
+    case SEL_p_p_pp:
+      sel(pd, pg, pn, pm);
+      return;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  mov_zeroing(pd, pg, result);
+  if (instr->Mask(SVEPredicateLogicalSetFlagsBit) != 0) {
+    PredTest(kFormatVnB, pg, pd);
+  }
+}
+
+void Simulator::VisitSVEPredicateFirstActive(const Instruction* instr) {
+  LogicPRegister pg = ReadPRegister(instr->ExtractBits(8, 5));
+  LogicPRegister pdn = ReadPRegister(instr->GetPd());
+  switch (instr->Mask(SVEPredicateFirstActiveMask)) {
+    case PFIRST_p_p_p:
+      pfirst(pdn, pg, pdn);
+      // TODO: Is this broken when pg == pdn?
+      PredTest(kFormatVnB, pg, pdn);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEPredicateInitialize(const Instruction* instr) {
+  // This group only contains PTRUE{S}, and there are no unallocated encodings.
+  VIXL_STATIC_ASSERT(
+      SVEPredicateInitializeMask ==
+      (SVEPredicateInitializeFMask | SVEPredicateInitializeSetFlagsBit));
+  VIXL_ASSERT((instr->Mask(SVEPredicateInitializeMask) == PTRUE_p_s) ||
+              (instr->Mask(SVEPredicateInitializeMask) == PTRUES_p_s));
+
+  LogicPRegister pdn = ReadPRegister(instr->GetPd());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  ptrue(vform, pdn, instr->GetImmSVEPredicateConstraint());
+  if (instr->ExtractBit(16)) PredTest(vform, pdn, pdn);
+}
+
+void Simulator::VisitSVEPredicateNextActive(const Instruction* instr) {
+  // This group only contains PNEXT, and there are no unallocated encodings.
+  VIXL_STATIC_ASSERT(SVEPredicateNextActiveFMask == SVEPredicateNextActiveMask);
+  VIXL_ASSERT(instr->Mask(SVEPredicateNextActiveMask) == PNEXT_p_p_p);
+
+  LogicPRegister pg = ReadPRegister(instr->ExtractBits(8, 5));
+  LogicPRegister pdn = ReadPRegister(instr->GetPd());
+  VectorFormat vform = instr->GetSVEVectorFormat();
+
+  pnext(vform, pdn, pg, pdn);
+  // TODO: Is this broken when pg == pdn?
+  PredTest(vform, pg, pdn);
+}
+
+void Simulator::VisitSVEPredicateReadFromFFR_Predicated(
+    const Instruction* instr) {
+  LogicPRegister pd(ReadPRegister(instr->GetPd()));
+  LogicPRegister pg(ReadPRegister(instr->GetPn()));
+  FlagsUpdate flags = LeaveFlags;
+  switch (instr->Mask(SVEPredicateReadFromFFR_PredicatedMask)) {
+    case RDFFR_p_p_f:
+      // Do nothing.
+      break;
+    case RDFFRS_p_p_f:
+      flags = SetFlags;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  LogicPRegister ffr(ReadFFR());
+  mov_zeroing(pd, pg, ffr);
+
+  if (flags == SetFlags) {
+    PredTest(kFormatVnB, pg, pd);
+  }
+}
+
+void Simulator::VisitSVEPredicateReadFromFFR_Unpredicated(
+    const Instruction* instr) {
+  LogicPRegister pd(ReadPRegister(instr->GetPd()));
+  LogicPRegister ffr(ReadFFR());
+  switch (instr->Mask(SVEPredicateReadFromFFR_UnpredicatedMask)) {
+    case RDFFR_p_f:
+      mov(pd, ffr);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEPredicateTest(const Instruction* instr) {
+  switch (instr->Mask(SVEPredicateTestMask)) {
+    case PTEST_p_p:
+      PredTest(kFormatVnB,
+               ReadPRegister(instr->ExtractBits(13, 10)),
+               ReadPRegister(instr->GetPn()));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEPredicateZero(const Instruction* instr) {
+  switch (instr->Mask(SVEPredicateZeroMask)) {
+    case PFALSE_p:
+      pfalse(ReadPRegister(instr->GetPd()));
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEPropagateBreak(const Instruction* instr) {
+  SimPRegister& pd = ReadPRegister(instr->GetPd());
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
+  SimPRegister& pn = ReadPRegister(instr->GetPn());
+  SimPRegister& pm = ReadPRegister(instr->GetPm());
+
+  bool set_flags = false;
+  switch (instr->Mask(SVEPropagateBreakMask)) {
+    case BRKPAS_p_p_pp:
+      set_flags = true;
+      VIXL_FALLTHROUGH();
+    case BRKPA_p_p_pp:
+      brkpa(pd, pg, pn, pm);
+      break;
+    case BRKPBS_p_p_pp:
+      set_flags = true;
+      VIXL_FALLTHROUGH();
+    case BRKPB_p_p_pp:
+      brkpb(pd, pg, pn, pm);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+
+  if (set_flags) {
+    PredTest(kFormatVnB, pg, pd);
+  }
+}
+
+void Simulator::VisitSVEStackFrameAdjustment(const Instruction* instr) {
+  uint64_t length = 0;
+  switch (instr->Mask(SVEStackFrameAdjustmentMask)) {
+    case ADDPL_r_ri:
+      length = GetPredicateLengthInBytes();
+      break;
+    case ADDVL_r_ri:
+      length = GetVectorLengthInBytes();
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+  }
+  uint64_t base = ReadXRegister(instr->GetRm(), Reg31IsStackPointer);
+  WriteXRegister(instr->GetRd(),
+                 base + (length * instr->GetImmSVEVLScale()),
+                 LogRegWrites,
+                 Reg31IsStackPointer);
+}
+
+void Simulator::VisitSVEStackFrameSize(const Instruction* instr) {
+  int64_t scale = instr->GetImmSVEVLScale();
+
+  switch (instr->Mask(SVEStackFrameSizeMask)) {
+    case RDVL_r_i:
+      WriteXRegister(instr->GetRd(), GetVectorLengthInBytes() * scale);
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+  }
+}
+
+void Simulator::VisitSVEVectorSelect(const Instruction* instr) {
+  // The only instruction in this group is `sel`, and there are no unused
+  // encodings.
+  VIXL_ASSERT(instr->Mask(SVEVectorSelectMask) == SEL_z_p_zz);
+
+  VectorFormat vform = instr->GetSVEVectorFormat();
+  SimVRegister& zd = ReadVRegister(instr->GetRd());
+  SimPRegister& pg = ReadPRegister(instr->ExtractBits(13, 10));
+  SimVRegister& zn = ReadVRegister(instr->GetRn());
+  SimVRegister& zm = ReadVRegister(instr->GetRm());
+
+  sel(vform, zd, pg, zn, zm);
+}
+
+void Simulator::VisitSVEFFRInitialise(const Instruction* instr) {
+  switch (instr->Mask(SVEFFRInitialiseMask)) {
+    case SETFFR_f: {
+      LogicPRegister ffr(ReadFFR());
+      ffr.SetAllBits();
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEFFRWriteFromPredicate(const Instruction* instr) {
+  switch (instr->Mask(SVEFFRWriteFromPredicateMask)) {
+    case WRFFR_f_p: {
+      SimPRegister pn(ReadPRegister(instr->GetPn()));
+      bool last_active = true;
+      for (unsigned i = 0; i < pn.GetSizeInBits(); i++) {
+        bool active = pn.GetBit(i);
+        if (active && !last_active) {
+          // `pn` is non-monotonic. This is UNPREDICTABLE.
+          VIXL_ABORT();
+        }
+        last_active = active;
+      }
+      mov(ReadFFR(), pn);
+      break;
+    }
+    default:
+      VIXL_UNIMPLEMENTED();
+      break;
+  }
+}
+
+void Simulator::VisitSVEContiguousLoad_ScalarPlusImm(const Instruction* instr) {
+  bool is_signed;
+  switch (instr->Mask(SVEContiguousLoad_ScalarPlusImmMask)) {
+    case LD1B_z_p_bi_u8:
+    case LD1B_z_p_bi_u16:
+    case LD1B_z_p_bi_u32:
+    case LD1B_z_p_bi_u64:
+    case LD1H_z_p_bi_u16:
+    case LD1H_z_p_bi_u32:
+    case LD1H_z_p_bi_u64:
+    case LD1W_z_p_bi_u32:
+    case LD1W_z_p_bi_u64:
+    case LD1D_z_p_bi_u64:
+      is_signed = false;
+      break;
+    case LD1SB_z_p_bi_s16:
+    case LD1SB_z_p_bi_s32:
+    case LD1SB_z_p_bi_s64:
+    case LD1SH_z_p_bi_s32:
+    case LD1SH_z_p_bi_s64:
+    case LD1SW_z_p_bi_s64:
+      is_signed = true;
+      break;
+    default:
+      // This encoding group is complete, so no other values should be possible.
+      VIXL_UNREACHABLE();
+      is_signed = false;
+      break;
+  }
+
+  int vl = GetVectorLengthInBytes();
+  int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
+  int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed);
+  VIXL_ASSERT(esize_in_bytes_log2 >= msize_in_bytes_log2);
+  int vl_divisor_log2 = esize_in_bytes_log2 - msize_in_bytes_log2;
+  uint64_t offset =
+      (instr->ExtractSignedBits(19, 16) * vl) / (1 << vl_divisor_log2);
+  VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2);
+  LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  SVEStructuredLoadHelper(vform,
+                          ReadPRegister(instr->GetPgLow8()),
+                          instr->GetRt(),
+                          addr,
+                          is_signed);
+}
+
+void Simulator::VisitSVEContiguousLoad_ScalarPlusScalar(
+    const Instruction* instr) {
+  bool is_signed;
+  switch (instr->Mask(SVEContiguousLoad_ScalarPlusScalarMask)) {
+    case LD1B_z_p_br_u8:
+    case LD1B_z_p_br_u16:
+    case LD1B_z_p_br_u32:
+    case LD1B_z_p_br_u64:
+    case LD1H_z_p_br_u16:
+    case LD1H_z_p_br_u32:
+    case LD1H_z_p_br_u64:
+    case LD1W_z_p_br_u32:
+    case LD1W_z_p_br_u64:
+    case LD1D_z_p_br_u64:
+      is_signed = false;
+      break;
+    case LD1SB_z_p_br_s16:
+    case LD1SB_z_p_br_s32:
+    case LD1SB_z_p_br_s64:
+    case LD1SH_z_p_br_s32:
+    case LD1SH_z_p_br_s64:
+    case LD1SW_z_p_br_s64:
+      is_signed = true;
+      break;
+    default:
+      // This encoding group is complete, so no other values should be possible.
+      VIXL_UNREACHABLE();
+      is_signed = false;
+      break;
+  }
+
+  int msize_in_bytes_log2 = instr->GetSVEMsizeFromDtype(is_signed);
+  int esize_in_bytes_log2 = instr->GetSVEEsizeFromDtype(is_signed);
+  VIXL_ASSERT(msize_in_bytes_log2 <= esize_in_bytes_log2);
+  VectorFormat vform = SVEFormatFromLaneSizeInBytesLog2(esize_in_bytes_log2);
+  uint64_t offset = ReadXRegister(instr->GetRm());
+  offset <<= msize_in_bytes_log2;
+  LogicSVEAddressVector addr(ReadXRegister(instr->GetRn()) + offset);
+  addr.SetMsizeInBytesLog2(msize_in_bytes_log2);
+  SVEStructuredLoadHelper(vform,
+                          ReadPRegister(instr->GetPgLow8()),
+                          instr->GetRt(),
+                          addr,
+                          is_signed);
+}
 
 void Simulator::DoUnreachable(const Instruction* instr) {
   VIXL_ASSERT((instr->Mask(ExceptionMask) == HLT) &&
@@ -6922,11 +11867,11 @@ void Simulator::DoRuntimeCall(const Instruction* instr) {
   // The appropriate `Simulator::SimulateRuntimeCall()` wrapper and the function
   // to call are passed inlined in the assembly.
   uintptr_t call_wrapper_address =
-      Memory::Read<uintptr_t>(instr + kRuntimeCallWrapperOffset);
+      MemRead<uintptr_t>(instr + kRuntimeCallWrapperOffset);
   uintptr_t function_address =
-      Memory::Read<uintptr_t>(instr + kRuntimeCallFunctionOffset);
+      MemRead<uintptr_t>(instr + kRuntimeCallFunctionOffset);
   RuntimeCallType call_type = static_cast<RuntimeCallType>(
-      Memory::Read<uint32_t>(instr + kRuntimeCallTypeOffset));
+      MemRead<uint32_t>(instr + kRuntimeCallTypeOffset));
   auto runtime_call_wrapper =
       reinterpret_cast<void (*)(Simulator*, uintptr_t)>(call_wrapper_address);
 
@@ -6961,7 +11906,7 @@ void Simulator::DoConfigureCPUFeatures(const Instruction* instr) {
   // Read the kNone-terminated list of features.
   CPUFeatures parameters;
   while (true) {
-    ElementType feature = Memory::Read<ElementType>(instr + offset);
+    ElementType feature = MemRead<ElementType>(instr + offset);
     offset += element_size;
     if (feature == static_cast<ElementType>(CPUFeatures::kNone)) break;
     parameters.Combine(static_cast<CPUFeatures::Feature>(feature));
diff --git a/src/aarch64/simulator-aarch64.h b/src/aarch64/simulator-aarch64.h
index 7cb7419a..44fb0cdb 100644
--- a/src/aarch64/simulator-aarch64.h
+++ b/src/aarch64/simulator-aarch64.h
@@ -27,6 +27,7 @@
 #ifndef VIXL_AARCH64_SIMULATOR_AARCH64_H_
 #define VIXL_AARCH64_SIMULATOR_AARCH64_H_
 
+#include <memory>
 #include <vector>
 
 #include "../globals-vixl.h"
@@ -37,7 +38,6 @@
 #include "cpu-features-auditor-aarch64.h"
 #include "disasm-aarch64.h"
 #include "instructions-aarch64.h"
-#include "instrument-aarch64.h"
 #include "simulator-constants-aarch64.h"
 
 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
@@ -55,11 +55,112 @@
 namespace vixl {
 namespace aarch64 {
 
+class SimStack {
+ public:
+  SimStack() {}
+  explicit SimStack(size_t size) : usable_size_(size) {}
+
+  // Guard against accesses above the stack base. This could occur, for example,
+  // if the first simulated function tries to read stack arguments that haven't
+  // been properly initialised in the Simulator's stack.
+  void SetBaseGuardSize(size_t size) { base_guard_size_ = size; }
+
+  // Guard against stack overflows. The size should be large enough to detect
+  // the largest stride made (by `MacroAssembler::Claim()` or equivalent) whilst
+  // initialising stack objects.
+  void SetLimitGuardSize(size_t size) { limit_guard_size_ = size; }
+
+  // The minimum usable size of the stack.
+  // Equal to "stack base" - "stack limit", in AAPCS64 terminology.
+  void SetUsableSize(size_t size) { usable_size_ = size; }
+
+  // Set the minimum alignment for the stack parameters.
+  void AlignToBytesLog2(int align_log2) { align_log2_ = align_log2; }
+
+  class Allocated {
+   public:
+    // Using AAPCS64 terminology, highest addresses at the top:
+    //
+    //  data_.get() + alloc_size ->
+    //                              |
+    //                              | Base guard
+    //                 GetBase() -> |                  |
+    //                                |                |
+    //                                |                | AAPCS64-legal
+    //                                | Usable stack   | values of 'sp'.
+    //                                |                |
+    //                                |                |
+    //                GetLimit() -> |
+    //                              | Limit guard
+    //               data_.get() -> |
+    //
+    // The Simulator detects (and forbids) accesses to either guard region.
+
+    char* GetBase() const { return base_; }
+    char* GetLimit() const { return limit_; }
+
+    template <typename T>
+    bool IsAccessInGuardRegion(const T* base, size_t size) const {
+      VIXL_ASSERT(size > 0);
+      // Inclusive bounds.
+      const char* start = reinterpret_cast<const char*>(base);
+      const char* end = start + size - 1;
+      const char* data_start = data_.get();
+      const char* data_end = data_start + alloc_size_ - 1;
+      bool in_base_guard = (start <= data_end) && (end >= base_);
+      bool in_limit_guard = (start <= limit_) && (end >= data_start);
+      return in_base_guard || in_limit_guard;
+    }
+
+   private:
+    std::unique_ptr<char[]> data_;
+    char* limit_;
+    char* base_;
+    size_t alloc_size_;
+
+    friend class SimStack;
+  };
+
+  // Allocate the stack, locking the parameters.
+  Allocated Allocate() {
+    size_t align_to = 1 << align_log2_;
+    size_t l = AlignUp(limit_guard_size_, align_to);
+    size_t u = AlignUp(usable_size_, align_to);
+    size_t b = AlignUp(base_guard_size_, align_to);
+    size_t size = l + u + b;
+
+    Allocated a;
+    size_t alloc_size = (align_to - 1) + size;
+    a.data_ = std::make_unique<char[]>(alloc_size);
+    void* data = a.data_.get();
+    auto data_aligned =
+        reinterpret_cast<char*>(std::align(align_to, size, data, alloc_size));
+    a.limit_ = data_aligned + l - 1;
+    a.base_ = data_aligned + l + u;
+    a.alloc_size_ = alloc_size;
+    return a;
+  }
+
+ private:
+  size_t base_guard_size_ = 256;
+  size_t limit_guard_size_ = 4 * 1024;
+  size_t usable_size_ = 8 * 1024;
+  size_t align_log2_ = 4;
+
+  static const size_t kDefaultBaseGuardSize = 256;
+  static const size_t kDefaultLimitGuardSize = 4 * 1024;
+  static const size_t kDefaultUsableSize = 8 * 1024;
+};
+
 // Representation of memory, with typed getters and setters for access.
 class Memory {
  public:
+  explicit Memory(SimStack::Allocated stack) : stack_(std::move(stack)) {}
+
+  const SimStack::Allocated& GetStack() { return stack_; }
+
   template <typename T>
-  static T AddressUntag(T address) {
+  T AddressUntag(T address) const {
     // Cast the address using a C-style cast. A reinterpret_cast would be
     // appropriate, but it can't cast one integral type to another.
     uint64_t bits = (uint64_t)address;
@@ -67,39 +168,111 @@ class Memory {
   }
 
   template <typename T, typename A>
-  static T Read(A address) {
+  T Read(A address) const {
     T value;
     address = AddressUntag(address);
-    VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
-                (sizeof(value) == 4) || (sizeof(value) == 8) ||
-                (sizeof(value) == 16));
-    memcpy(&value, reinterpret_cast<const char*>(address), sizeof(value));
+    VIXL_STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
+                       (sizeof(value) == 4) || (sizeof(value) == 8) ||
+                       (sizeof(value) == 16));
+    auto base = reinterpret_cast<const char*>(address);
+    if (stack_.IsAccessInGuardRegion(base, sizeof(value))) {
+      VIXL_ABORT_WITH_MSG("Attempt to read from stack guard region");
+    }
+    memcpy(&value, base, sizeof(value));
     return value;
   }
 
   template <typename T, typename A>
-  static void Write(A address, T value) {
+  void Write(A address, T value) const {
     address = AddressUntag(address);
-    VIXL_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
-                (sizeof(value) == 4) || (sizeof(value) == 8) ||
-                (sizeof(value) == 16));
-    memcpy(reinterpret_cast<char*>(address), &value, sizeof(value));
+    VIXL_STATIC_ASSERT((sizeof(value) == 1) || (sizeof(value) == 2) ||
+                       (sizeof(value) == 4) || (sizeof(value) == 8) ||
+                       (sizeof(value) == 16));
+    auto base = reinterpret_cast<char*>(address);
+    if (stack_.IsAccessInGuardRegion(base, sizeof(value))) {
+      VIXL_ABORT_WITH_MSG("Attempt to write to stack guard region");
+    }
+    memcpy(base, &value, sizeof(value));
+  }
+
+  template <typename A>
+  uint64_t ReadUint(int size_in_bytes, A address) const {
+    switch (size_in_bytes) {
+      case 1:
+        return Read<uint8_t>(address);
+      case 2:
+        return Read<uint16_t>(address);
+      case 4:
+        return Read<uint32_t>(address);
+      case 8:
+        return Read<uint64_t>(address);
+    }
+    VIXL_UNREACHABLE();
+    return 0;
+  }
+
+  template <typename A>
+  int64_t ReadInt(int size_in_bytes, A address) const {
+    switch (size_in_bytes) {
+      case 1:
+        return Read<int8_t>(address);
+      case 2:
+        return Read<int16_t>(address);
+      case 4:
+        return Read<int32_t>(address);
+      case 8:
+        return Read<int64_t>(address);
+    }
+    VIXL_UNREACHABLE();
+    return 0;
+  }
+
+  template <typename A>
+  void Write(int size_in_bytes, A address, uint64_t value) const {
+    switch (size_in_bytes) {
+      case 1:
+        return Write(address, static_cast<uint8_t>(value));
+      case 2:
+        return Write(address, static_cast<uint16_t>(value));
+      case 4:
+        return Write(address, static_cast<uint32_t>(value));
+      case 8:
+        return Write(address, value);
+    }
+    VIXL_UNREACHABLE();
   }
+
+ private:
+  SimStack::Allocated stack_;
 };
 
-// Represent a register (r0-r31, v0-v31).
-template <int kSizeInBytes>
+// Represent a register (r0-r31, v0-v31, z0-z31, p0-p15).
+template <unsigned kMaxSizeInBits>
 class SimRegisterBase {
  public:
-  SimRegisterBase() : written_since_last_log_(false) {}
+  static const unsigned kMaxSizeInBytes = kMaxSizeInBits / kBitsPerByte;
+  VIXL_STATIC_ASSERT((kMaxSizeInBytes * kBitsPerByte) == kMaxSizeInBits);
+
+  SimRegisterBase() : size_in_bytes_(kMaxSizeInBytes) { Clear(); }
+
+  unsigned GetSizeInBits() const { return size_in_bytes_ * kBitsPerByte; }
+  unsigned GetSizeInBytes() const { return size_in_bytes_; }
+
+  void SetSizeInBytes(unsigned size_in_bytes) {
+    VIXL_ASSERT(size_in_bytes <= kMaxSizeInBytes);
+    size_in_bytes_ = size_in_bytes;
+  }
+  void SetSizeInBits(unsigned size_in_bits) {
+    VIXL_ASSERT(size_in_bits <= kMaxSizeInBits);
+    VIXL_ASSERT((size_in_bits % kBitsPerByte) == 0);
+    SetSizeInBytes(size_in_bits / kBitsPerByte);
+  }
 
   // Write the specified value. The value is zero-extended if necessary.
   template <typename T>
   void Write(T new_value) {
-    if (sizeof(new_value) < kSizeInBytes) {
-      // All AArch64 registers are zero-extending.
-      memset(value_ + sizeof(new_value), 0, kSizeInBytes - sizeof(new_value));
-    }
+    // All AArch64 registers are zero-extending.
+    if (sizeof(new_value) < GetSizeInBytes()) Clear();
     WriteLane(new_value, 0);
     NotifyRegisterWrite();
   }
@@ -108,6 +281,11 @@ class SimRegisterBase {
     Write(new_value);
   }
 
+  void Clear() {
+    memset(value_, 0, kMaxSizeInBytes);
+    NotifyRegisterWrite();
+  }
+
   // Insert a typed value into a register, leaving the rest of the register
   // unchanged. The lane parameter indicates where in the register the value
   // should be inserted, in the range [ 0, sizeof(value_) / sizeof(T) ), where
@@ -137,6 +315,17 @@ class SimRegisterBase {
     return GetLane(lane);
   }
 
+  // Get the value of a specific bit, indexed from the least-significant bit of
+  // lane 0.
+  bool GetBit(int bit) const {
+    int bit_in_byte = bit % (sizeof(value_[0]) * kBitsPerByte);
+    int byte = bit / (sizeof(value_[0]) * kBitsPerByte);
+    return ((value_[byte] >> bit_in_byte) & 1) != 0;
+  }
+
+  // Return a pointer to the raw, underlying byte array.
+  const uint8_t* GetBytes() const { return value_; }
+
   // TODO: Make this return a map of updated bytes, so that we can highlight
   // updated lanes for load-and-insert. (That never happens for scalar code, but
   // NEON has some instructions that can update individual lanes.)
@@ -145,7 +334,9 @@ class SimRegisterBase {
   void NotifyRegisterLogged() { written_since_last_log_ = false; }
 
  protected:
-  uint8_t value_[kSizeInBytes];
+  uint8_t value_[kMaxSizeInBytes];
+
+  unsigned size_in_bytes_;
 
   // Helpers to aid with register tracing.
   bool written_since_last_log_;
@@ -156,38 +347,152 @@ class SimRegisterBase {
   template <typename T>
   void ReadLane(T* dst, int lane) const {
     VIXL_ASSERT(lane >= 0);
-    VIXL_ASSERT((sizeof(*dst) + (lane * sizeof(*dst))) <= kSizeInBytes);
+    VIXL_ASSERT((sizeof(*dst) + (lane * sizeof(*dst))) <= GetSizeInBytes());
     memcpy(dst, &value_[lane * sizeof(*dst)], sizeof(*dst));
   }
 
   template <typename T>
   void WriteLane(T src, int lane) {
     VIXL_ASSERT(lane >= 0);
-    VIXL_ASSERT((sizeof(src) + (lane * sizeof(src))) <= kSizeInBytes);
+    VIXL_ASSERT((sizeof(src) + (lane * sizeof(src))) <= GetSizeInBytes());
     memcpy(&value_[lane * sizeof(src)], &src, sizeof(src));
   }
+
+  // The default ReadLane and WriteLane methods assume what we are copying is
+  // "trivially copyable" by using memcpy. We have to provide alternative
+  // implementations for SimFloat16 which cannot be copied this way.
+
+  void ReadLane(vixl::internal::SimFloat16* dst, int lane) const {
+    uint16_t rawbits;
+    ReadLane(&rawbits, lane);
+    *dst = RawbitsToFloat16(rawbits);
+  }
+
+  void WriteLane(vixl::internal::SimFloat16 src, int lane) {
+    WriteLane(Float16ToRawbits(src), lane);
+  }
+};
+
+typedef SimRegisterBase<kXRegSize> SimRegister;      // r0-r31
+typedef SimRegisterBase<kPRegMaxSize> SimPRegister;  // p0-p15
+// FFR has the same format as a predicate register.
+typedef SimPRegister SimFFRRegister;
+
+// v0-v31 and z0-z31
+class SimVRegister : public SimRegisterBase<kZRegMaxSize> {
+ public:
+  SimVRegister() : SimRegisterBase<kZRegMaxSize>(), accessed_as_z_(false) {}
+
+  void NotifyAccessAsZ() { accessed_as_z_ = true; }
+
+  void NotifyRegisterLogged() {
+    SimRegisterBase<kZRegMaxSize>::NotifyRegisterLogged();
+    accessed_as_z_ = false;
+  }
+
+  bool AccessedAsZSinceLastLog() const { return accessed_as_z_; }
+
+ private:
+  bool accessed_as_z_;
+};
+
+// Representation of a SVE predicate register.
+class LogicPRegister {
+ public:
+  inline LogicPRegister(
+      SimPRegister& other)  // NOLINT(runtime/references)(runtime/explicit)
+      : register_(other) {}
+
+  // Set a conveniently-sized block to 16 bits as the minimum predicate length
+  // is 16 bits and allow to be increased to multiples of 16 bits.
+  typedef uint16_t ChunkType;
+
+  // Assign a bit into the end positon of the specified lane.
+  // The bit is zero-extended if necessary.
+  void SetActive(VectorFormat vform, int lane_index, bool value) {
+    int psize = LaneSizeInBytesFromFormat(vform);
+    int bit_index = lane_index * psize;
+    int byte_index = bit_index / kBitsPerByte;
+    int bit_offset = bit_index % kBitsPerByte;
+    uint8_t byte = register_.GetLane<uint8_t>(byte_index);
+    register_.Insert(byte_index, ZeroExtend(byte, bit_offset, psize, value));
+  }
+
+  bool IsActive(VectorFormat vform, int lane_index) const {
+    int psize = LaneSizeInBytesFromFormat(vform);
+    int bit_index = lane_index * psize;
+    int byte_index = bit_index / kBitsPerByte;
+    int bit_offset = bit_index % kBitsPerByte;
+    uint8_t byte = register_.GetLane<uint8_t>(byte_index);
+    return ExtractBit(byte, bit_offset);
+  }
+
+  // The accessors for bulk processing.
+  int GetChunkCount() const {
+    VIXL_ASSERT((register_.GetSizeInBytes() % sizeof(ChunkType)) == 0);
+    return register_.GetSizeInBytes() / sizeof(ChunkType);
+  }
+
+  ChunkType GetChunk(int lane) const { return GetActiveMask<ChunkType>(lane); }
+
+  void SetChunk(int lane, ChunkType new_value) {
+    SetActiveMask(lane, new_value);
+  }
+
+  void SetAllBits() {
+    int chunk_size = sizeof(ChunkType) * kBitsPerByte;
+    ChunkType bits = GetUintMask(chunk_size);
+    for (int lane = 0;
+         lane < (static_cast<int>(register_.GetSizeInBits() / chunk_size));
+         lane++) {
+      SetChunk(lane, bits);
+    }
+  }
+
+  template <typename T>
+  T GetActiveMask(int lane) const {
+    return register_.GetLane<T>(lane);
+  }
+
+  template <typename T>
+  void SetActiveMask(int lane, T new_value) {
+    register_.Insert<T>(lane, new_value);
+  }
+
+  void Clear() { register_.Clear(); }
+
+  bool Aliases(const LogicPRegister& other) const {
+    return &register_ == &other.register_;
+  }
+
+ private:
+  // The bit assignment is zero-extended to fill the size of predicate element.
+  uint8_t ZeroExtend(uint8_t byte, int index, int psize, bool value) {
+    VIXL_ASSERT(index >= 0);
+    VIXL_ASSERT(index + psize <= kBitsPerByte);
+    int bits = value ? 1 : 0;
+    switch (psize) {
+      case 1:
+        AssignBit(byte, index, bits);
+        break;
+      case 2:
+        AssignBits(byte, index, 0x03, bits);
+        break;
+      case 4:
+        AssignBits(byte, index, 0x0f, bits);
+        break;
+      case 8:
+        AssignBits(byte, index, 0xff, bits);
+        break;
+      default:
+        VIXL_UNREACHABLE();
+        return 0;
+    }
+    return byte;
+  }
+
+  SimPRegister& register_;
 };
-typedef SimRegisterBase<kXRegSizeInBytes> SimRegister;   // r0-r31
-typedef SimRegisterBase<kQRegSizeInBytes> SimVRegister;  // v0-v31
-
-// The default ReadLane and WriteLane methods assume what we are copying is
-// "trivially copyable" by using memcpy. We have to provide alternative
-// implementations for SimFloat16 which cannot be copied this way.
-
-template <>
-template <>
-inline void SimVRegister::ReadLane(vixl::internal::SimFloat16* dst,
-                                   int lane) const {
-  uint16_t rawbits;
-  ReadLane(&rawbits, lane);
-  *dst = RawbitsToFloat16(rawbits);
-}
-
-template <>
-template <>
-inline void SimVRegister::WriteLane(vixl::internal::SimFloat16 src, int lane) {
-  WriteLane(Float16ToRawbits(src), lane);
-}
 
 // Representation of a vector register, with typed getters and setters for lanes
 // and additional information to represent lane state.
@@ -205,6 +510,7 @@ class LogicVRegister {
   }
 
   int64_t Int(VectorFormat vform, int index) const {
+    if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
     int64_t element;
     switch (LaneSizeInBitsFromFormat(vform)) {
       case 8:
@@ -227,6 +533,7 @@ class LogicVRegister {
   }
 
   uint64_t Uint(VectorFormat vform, int index) const {
+    if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
     uint64_t element;
     switch (LaneSizeInBitsFromFormat(vform)) {
       case 8:
@@ -260,6 +567,7 @@ class LogicVRegister {
   }
 
   void SetInt(VectorFormat vform, int index, int64_t value) const {
+    if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
     switch (LaneSizeInBitsFromFormat(vform)) {
       case 8:
         register_.Insert(index, static_cast<int8_t>(value));
@@ -287,6 +595,7 @@ class LogicVRegister {
   }
 
   void SetUint(VectorFormat vform, int index, uint64_t value) const {
+    if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
     switch (LaneSizeInBitsFromFormat(vform)) {
       case 8:
         register_.Insert(index, static_cast<uint8_t>(value));
@@ -313,44 +622,6 @@ class LogicVRegister {
     }
   }
 
-  void ReadUintFromMem(VectorFormat vform, int index, uint64_t addr) const {
-    switch (LaneSizeInBitsFromFormat(vform)) {
-      case 8:
-        register_.Insert(index, Memory::Read<uint8_t>(addr));
-        break;
-      case 16:
-        register_.Insert(index, Memory::Read<uint16_t>(addr));
-        break;
-      case 32:
-        register_.Insert(index, Memory::Read<uint32_t>(addr));
-        break;
-      case 64:
-        register_.Insert(index, Memory::Read<uint64_t>(addr));
-        break;
-      default:
-        VIXL_UNREACHABLE();
-        return;
-    }
-  }
-
-  void WriteUintToMem(VectorFormat vform, int index, uint64_t addr) const {
-    uint64_t value = Uint(vform, index);
-    switch (LaneSizeInBitsFromFormat(vform)) {
-      case 8:
-        Memory::Write(addr, static_cast<uint8_t>(value));
-        break;
-      case 16:
-        Memory::Write(addr, static_cast<uint16_t>(value));
-        break;
-      case 32:
-        Memory::Write(addr, static_cast<uint32_t>(value));
-        break;
-      case 64:
-        Memory::Write(addr, value);
-        break;
-    }
-  }
-
   template <typename T>
   T Float(int index) const {
     return register_.GetLane<T>(index);
@@ -361,11 +632,20 @@ class LogicVRegister {
     register_.Insert(index, value);
   }
 
-  // When setting a result in a register of size less than Q, the top bits of
-  // the Q register must be cleared.
+  template <typename T>
+  void SetFloat(VectorFormat vform, int index, T value) const {
+    if (IsSVEFormat(vform)) register_.NotifyAccessAsZ();
+    register_.Insert(index, value);
+  }
+
+  // When setting a result in a register larger than the result itself, the top
+  // bits of the register must be cleared.
   void ClearForWrite(VectorFormat vform) const {
+    // SVE destinations write whole registers, so we have nothing to clear.
+    if (IsSVEFormat(vform)) return;
+
     unsigned size = RegisterSizeInBytesFromFormat(vform);
-    for (unsigned i = size; i < kQRegSizeInBytes; i++) {
+    for (unsigned i = size; i < register_.GetSizeInBytes(); i++) {
       SetUint(kFormat16B, i, 0);
     }
   }
@@ -470,26 +750,142 @@ class LogicVRegister {
     for (int i = 0; i < LaneCountFromFormat(vform); i++) {
       int64_t val = Int(vform, i);
       SetRounding(i, (val & 1) == 1);
-      val >>= 1;
-      if (GetSignedSaturation(i) != kNotSaturated) {
+      val = ExtractSignedBitfield64(63, 1, val);  // >>= 1
+      if (GetSignedSaturation(i) == kNotSaturated) {
+        SetInt(vform, i, val);
+      } else {
         // If the operation causes signed saturation, the sign bit must be
         // inverted.
-        val ^= (MaxUintFromFormat(vform) >> 1) + 1;
+        uint64_t uval = static_cast<uint64_t>(val);
+        SetUint(vform, i, uval ^ ((MaxUintFromFormat(vform) >> 1) + 1));
       }
-      SetInt(vform, i, val);
     }
     return *this;
   }
 
+  int LaneCountFromFormat(VectorFormat vform) const {
+    if (IsSVEFormat(vform)) {
+      return register_.GetSizeInBits() / LaneSizeInBitsFromFormat(vform);
+    } else {
+      return vixl::aarch64::LaneCountFromFormat(vform);
+    }
+  }
+
  private:
   SimVRegister& register_;
 
   // Allocate one saturation state entry per lane; largest register is type Q,
   // and lanes can be a minimum of one byte wide.
-  Saturation saturated_[kQRegSizeInBytes];
+  Saturation saturated_[kZRegMaxSizeInBytes];
 
   // Allocate one rounding state entry per lane.
-  bool round_[kQRegSizeInBytes];
+  bool round_[kZRegMaxSizeInBytes];
+};
+
+// Represent an SVE addressing mode and abstract per-lane address generation to
+// make iteration easy.
+//
+// Contiguous accesses are described with a simple base address, the memory
+// occupied by each lane (`SetMsizeInBytesLog2()`) and the number of elements in
+// each struct (`SetRegCount()`).
+//
+// Scatter-gather accesses also require a SimVRegister and information about how
+// to extract lanes from it.
+class LogicSVEAddressVector {
+ public:
+  // scalar-plus-scalar
+  // scalar-plus-immediate
+  explicit LogicSVEAddressVector(uint64_t base)
+      : base_(base),
+        msize_in_bytes_log2_(kUnknownMsizeInBytesLog2),
+        reg_count_(1),
+        vector_(NULL),
+        vector_form_(kFormatUndefined),
+        vector_mod_(NO_SVE_OFFSET_MODIFIER),
+        vector_shift_(0) {}
+
+  // scalar-plus-vector
+  // vector-plus-immediate
+  //    `base` should be the constant used for each element. That is, the value
+  //    of `xn`, or `#<imm>`.
+  //    `vector` should be the SimVRegister with offsets for each element. The
+  //    vector format must be specified; SVE scatter/gather accesses typically
+  //    support both 32-bit and 64-bit addressing.
+  //
+  //    `mod` and `shift` correspond to the modifiers applied to each element in
+  //    scalar-plus-vector forms, such as those used for unpacking and
+  //    sign-extension. They are not used for vector-plus-immediate.
+  LogicSVEAddressVector(uint64_t base,
+                        const SimVRegister* vector,
+                        VectorFormat vform,
+                        SVEOffsetModifier mod = NO_SVE_OFFSET_MODIFIER,
+                        int shift = 0)
+      : base_(base),
+        msize_in_bytes_log2_(kUnknownMsizeInBytesLog2),
+        reg_count_(1),
+        vector_(vector),
+        vector_form_(vform),
+        vector_mod_(mod),
+        vector_shift_(shift) {}
+
+  // Set `msize` -- the memory occupied by each lane -- for address
+  // calculations.
+  void SetMsizeInBytesLog2(int msize_in_bytes_log2) {
+    VIXL_ASSERT(msize_in_bytes_log2 >= static_cast<int>(kBRegSizeInBytesLog2));
+    VIXL_ASSERT(msize_in_bytes_log2 <= static_cast<int>(kDRegSizeInBytesLog2));
+    msize_in_bytes_log2_ = msize_in_bytes_log2;
+  }
+
+  bool HasMsize() const {
+    return msize_in_bytes_log2_ != kUnknownMsizeInBytesLog2;
+  }
+
+  int GetMsizeInBytesLog2() const {
+    VIXL_ASSERT(HasMsize());
+    return msize_in_bytes_log2_;
+  }
+  int GetMsizeInBitsLog2() const {
+    return GetMsizeInBytesLog2() + kBitsPerByteLog2;
+  }
+
+  int GetMsizeInBytes() const { return 1 << GetMsizeInBytesLog2(); }
+  int GetMsizeInBits() const { return 1 << GetMsizeInBitsLog2(); }
+
+  void SetRegCount(int reg_count) {
+    VIXL_ASSERT(reg_count >= 1);  // E.g. ld1/st1
+    VIXL_ASSERT(reg_count <= 4);  // E.g. ld4/st4
+    reg_count_ = reg_count;
+  }
+
+  int GetRegCount() const { return reg_count_; }
+
+  // Full per-element address calculation for structured accesses.
+  //
+  // Note that the register number argument (`reg`) is zero-based.
+  uint64_t GetElementAddress(int lane, int reg) const {
+    VIXL_ASSERT(reg < GetRegCount());
+    // Individual structures are always contiguous in memory, so this
+    // implementation works for both contiguous and scatter-gather addressing.
+    return GetStructAddress(lane) + (reg * GetMsizeInBytes());
+  }
+
+  // Full per-struct address calculation for structured accesses.
+  uint64_t GetStructAddress(int lane) const;
+
+  bool IsContiguous() const { return vector_ == NULL; }
+  bool IsScatterGather() const { return !IsContiguous(); }
+
+ private:
+  uint64_t base_;
+  int msize_in_bytes_log2_;
+  int reg_count_;
+
+  const SimVRegister* vector_;
+  VectorFormat vector_form_;
+  SVEOffsetModifier vector_mod_;
+  int vector_shift_;
+
+  static const int kUnknownMsizeInBytesLog2 = -1;
 };
 
 // The proper way to initialize a simulated system register (such as NZCV) is as
@@ -623,7 +1019,9 @@ class SimExclusiveGlobalMonitor {
 
 class Simulator : public DecoderVisitor {
  public:
-  explicit Simulator(Decoder* decoder, FILE* stream = stdout);
+  explicit Simulator(Decoder* decoder,
+                     FILE* stream = stdout,
+                     SimStack::Allocated stack = SimStack().Allocate());
   ~Simulator();
 
   void ResetState();
@@ -701,7 +1099,7 @@ class Simulator : public DecoderVisitor {
   void WritePc(const Instruction* new_pc,
                BranchLogMode log_mode = LogBranches) {
     if (log_mode == LogBranches) LogTakenBranch(new_pc);
-    pc_ = Memory::AddressUntag(new_pc);
+    pc_ = memory_.AddressUntag(new_pc);
     pc_modified_ = true;
   }
   VIXL_DEPRECATED("WritePc", void set_pc(const Instruction* new_pc)) {
@@ -733,6 +1131,11 @@ class Simulator : public DecoderVisitor {
     VIXL_ASSERT(IsWordAligned(pc_));
     pc_modified_ = false;
 
+    if (movprfx_ != NULL) {
+      VIXL_CHECK(pc_->CanTakeSVEMovprfx(movprfx_));
+      movprfx_ = NULL;
+    }
+
     // On guarded pages, if BType is not zero, take an exception on any
     // instruction other than BTI, PACI[AB]SP, HLT or BRK.
     if (PcIsInGuardedPage() && (ReadBType() != DefaultBType)) {
@@ -774,13 +1177,6 @@ class Simulator : public DecoderVisitor {
 #undef DECLARE
 
 
-#define DECLARE(A)                                                             \
-  VIXL_NO_RETURN_IN_DEBUG_MODE virtual void Visit##A(const Instruction* instr) \
-      VIXL_OVERRIDE;
-  VISITOR_LIST_THAT_DONT_RETURN_IN_DEBUG_MODE(DECLARE)
-#undef DECLARE
-
-
   // Integer register accessors.
 
   // Basic accessor: Read the register as the specified type.
@@ -827,6 +1223,13 @@ class Simulator : public DecoderVisitor {
     return ReadXRegister(code, r31mode);
   }
 
+  SimPRegister& ReadPRegister(unsigned code) {
+    VIXL_ASSERT(code < kNumberOfPRegisters);
+    return pregisters_[code];
+  }
+
+  SimFFRRegister& ReadFFR() { return ffr_register_; }
+
   // As above, with parameterized size and return type. The value is
   // either zero-extended or truncated to fit, as required.
   template <typename T>
@@ -877,6 +1280,10 @@ class Simulator : public DecoderVisitor {
 
   // Write 'value' into an integer register. The value is zero-extended. This
   // behaviour matches AArch64 register writes.
+  //
+  // SP may be specified in one of two ways:
+  //  - (code == kSPRegInternalCode) && (r31mode == Reg31IsZeroRegister)
+  //  - (code == 31) && (r31mode == Reg31IsStackPointer)
   template <typename T>
   void WriteRegister(unsigned code,
                      T value,
@@ -896,20 +1303,25 @@ class Simulator : public DecoderVisitor {
     VIXL_ASSERT((sizeof(T) == kWRegSizeInBytes) ||
                 (sizeof(T) == kXRegSizeInBytes));
     VIXL_ASSERT(
-        code < kNumberOfRegisters ||
+        (code < kNumberOfRegisters) ||
         ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode)));
 
-    if ((code == 31) && (r31mode == Reg31IsZeroRegister)) {
-      return;
-    }
-
-    if ((r31mode == Reg31IsZeroRegister) && (code == kSPRegInternalCode)) {
-      code = 31;
+    if (code == 31) {
+      if (r31mode == Reg31IsZeroRegister) {
+        // Discard writes to the zero register.
+        return;
+      } else {
+        code = kSPRegInternalCode;
+      }
     }
 
-    registers_[code].Write(value);
+    // registers_[31] is the stack pointer.
+    VIXL_STATIC_ASSERT((kSPRegInternalCode % kNumberOfRegisters) == 31);
+    registers_[code % kNumberOfRegisters].Write(value);
 
-    if (log_mode == LogRegWrites) LogRegister(code, r31mode);
+    if (log_mode == LogRegWrites) {
+      LogRegister(code, GetPrintRegisterFormatForSize(sizeof(T)));
+    }
   }
   template <typename T>
   VIXL_DEPRECATED("WriteRegister",
@@ -1015,6 +1427,11 @@ class Simulator : public DecoderVisitor {
     uint8_t val[kQRegSizeInBytes];
   };
 
+  // A structure for representing a SVE Z register.
+  struct zreg_t {
+    uint8_t val[kZRegMaxSizeInBytes];
+  };
+
   // Basic accessor: read the register as the specified type.
   template <typename T>
   T ReadVRegister(unsigned code) const {
@@ -1130,7 +1547,8 @@ class Simulator : public DecoderVisitor {
                        (sizeof(value) == kHRegSizeInBytes) ||
                        (sizeof(value) == kSRegSizeInBytes) ||
                        (sizeof(value) == kDRegSizeInBytes) ||
-                       (sizeof(value) == kQRegSizeInBytes));
+                       (sizeof(value) == kQRegSizeInBytes) ||
+                       (sizeof(value) == kZRegMaxSizeInBytes));
     VIXL_ASSERT(code < kNumberOfVRegisters);
     vregisters_[code].Write(value);
 
@@ -1237,6 +1655,12 @@ class Simulator : public DecoderVisitor {
     WriteQRegister(code, value, log_mode);
   }
 
+  void WriteZRegister(unsigned code,
+                      zreg_t value,
+                      RegLogMode log_mode = LogRegWrites) {
+    WriteVRegister(code, value, log_mode);
+  }
+
   template <typename T>
   T ReadRegister(Register reg) const {
     return ReadRegister<T>(reg.GetCode(), Reg31IsZeroRegister);
@@ -1281,6 +1705,63 @@ class Simulator : public DecoderVisitor {
     }
   }
 
+  template <typename T, typename A>
+  T MemRead(A address) const {
+    return memory_.Read<T>(address);
+  }
+
+  template <typename T, typename A>
+  void MemWrite(A address, T value) const {
+    return memory_.Write(address, value);
+  }
+
+  template <typename A>
+  uint64_t MemReadUint(int size_in_bytes, A address) const {
+    return memory_.ReadUint(size_in_bytes, address);
+  }
+
+  template <typename A>
+  int64_t MemReadInt(int size_in_bytes, A address) const {
+    return memory_.ReadInt(size_in_bytes, address);
+  }
+
+  template <typename A>
+  void MemWrite(int size_in_bytes, A address, uint64_t value) const {
+    return memory_.Write(size_in_bytes, address, value);
+  }
+
+  void LoadLane(LogicVRegister dst,
+                VectorFormat vform,
+                int index,
+                uint64_t addr) const {
+    unsigned msize_in_bytes = LaneSizeInBytesFromFormat(vform);
+    LoadUintToLane(dst, vform, msize_in_bytes, index, addr);
+  }
+
+  void LoadUintToLane(LogicVRegister dst,
+                      VectorFormat vform,
+                      unsigned msize_in_bytes,
+                      int index,
+                      uint64_t addr) const {
+    dst.SetUint(vform, index, MemReadUint(msize_in_bytes, addr));
+  }
+
+  void LoadIntToLane(LogicVRegister dst,
+                     VectorFormat vform,
+                     unsigned msize_in_bytes,
+                     int index,
+                     uint64_t addr) const {
+    dst.SetInt(vform, index, MemReadInt(msize_in_bytes, addr));
+  }
+
+  void StoreLane(const LogicVRegister& src,
+                 VectorFormat vform,
+                 int index,
+                 uint64_t addr) const {
+    unsigned msize_in_bytes = LaneSizeInBytesFromFormat(vform);
+    MemWrite(msize_in_bytes, addr, src.Uint(vform, index));
+  }
+
   uint64_t ComputeMemOperandAddress(const MemOperand& mem_op) const;
 
   template <typename T>
@@ -1289,7 +1770,7 @@ class Simulator : public DecoderVisitor {
       return ReadCPURegister<T>(operand.GetCPURegister());
     } else {
       VIXL_ASSERT(operand.IsMemOperand());
-      return Memory::Read<T>(ComputeMemOperandAddress(operand.GetMemOperand()));
+      return MemRead<T>(ComputeMemOperandAddress(operand.GetMemOperand()));
     }
   }
 
@@ -1310,7 +1791,7 @@ class Simulator : public DecoderVisitor {
       WriteCPURegister(operand.GetCPURegister(), raw, log_mode);
     } else {
       VIXL_ASSERT(operand.IsMemOperand());
-      Memory::Write(ComputeMemOperandAddress(operand.GetMemOperand()), value);
+      MemWrite(ComputeMemOperandAddress(operand.GetMemOperand()), value);
     }
   }
 
@@ -1357,14 +1838,16 @@ class Simulator : public DecoderVisitor {
     kPrintRegLaneSizeD = 3 << 0,
     kPrintRegLaneSizeX = kPrintRegLaneSizeD,
     kPrintRegLaneSizeQ = 4 << 0,
+    kPrintRegLaneSizeUnknown = 5 << 0,
 
     kPrintRegLaneSizeOffset = 0,
     kPrintRegLaneSizeMask = 7 << 0,
 
-    // The lane count.
+    // The overall register size.
     kPrintRegAsScalar = 0,
     kPrintRegAsDVector = 1 << 3,
     kPrintRegAsQVector = 2 << 3,
+    kPrintRegAsSVEVector = 3 << 3,
 
     kPrintRegAsVectorMask = 3 << 3,
 
@@ -1372,37 +1855,98 @@ class Simulator : public DecoderVisitor {
     // S-, H-, and D-sized lanes.)
     kPrintRegAsFP = 1 << 5,
 
-    // Supported combinations.
-
-    kPrintXReg = kPrintRegLaneSizeX | kPrintRegAsScalar,
-    kPrintWReg = kPrintRegLaneSizeW | kPrintRegAsScalar,
-    kPrintHReg = kPrintRegLaneSizeH | kPrintRegAsScalar | kPrintRegAsFP,
-    kPrintSReg = kPrintRegLaneSizeS | kPrintRegAsScalar | kPrintRegAsFP,
-    kPrintDReg = kPrintRegLaneSizeD | kPrintRegAsScalar | kPrintRegAsFP,
-
-    kPrintReg1B = kPrintRegLaneSizeB | kPrintRegAsScalar,
-    kPrintReg8B = kPrintRegLaneSizeB | kPrintRegAsDVector,
-    kPrintReg16B = kPrintRegLaneSizeB | kPrintRegAsQVector,
-    kPrintReg1H = kPrintRegLaneSizeH | kPrintRegAsScalar,
-    kPrintReg4H = kPrintRegLaneSizeH | kPrintRegAsDVector,
-    kPrintReg8H = kPrintRegLaneSizeH | kPrintRegAsQVector,
-    kPrintReg1S = kPrintRegLaneSizeS | kPrintRegAsScalar,
-    kPrintReg2S = kPrintRegLaneSizeS | kPrintRegAsDVector,
-    kPrintReg4S = kPrintRegLaneSizeS | kPrintRegAsQVector,
-    kPrintReg1HFP = kPrintRegLaneSizeH | kPrintRegAsScalar | kPrintRegAsFP,
-    kPrintReg4HFP = kPrintRegLaneSizeH | kPrintRegAsDVector | kPrintRegAsFP,
-    kPrintReg8HFP = kPrintRegLaneSizeH | kPrintRegAsQVector | kPrintRegAsFP,
-    kPrintReg1SFP = kPrintRegLaneSizeS | kPrintRegAsScalar | kPrintRegAsFP,
-    kPrintReg2SFP = kPrintRegLaneSizeS | kPrintRegAsDVector | kPrintRegAsFP,
-    kPrintReg4SFP = kPrintRegLaneSizeS | kPrintRegAsQVector | kPrintRegAsFP,
-    kPrintReg1D = kPrintRegLaneSizeD | kPrintRegAsScalar,
-    kPrintReg2D = kPrintRegLaneSizeD | kPrintRegAsQVector,
-    kPrintReg1DFP = kPrintRegLaneSizeD | kPrintRegAsScalar | kPrintRegAsFP,
-    kPrintReg2DFP = kPrintRegLaneSizeD | kPrintRegAsQVector | kPrintRegAsFP,
-    kPrintReg1Q = kPrintRegLaneSizeQ | kPrintRegAsScalar
+    // With this flag, print helpers won't check that the upper bits are zero.
+    // This also forces the register name to be printed with the `reg<msb:0>`
+    // format.
+    //
+    // The flag is supported with any PrintRegisterFormat other than those with
+    // kPrintRegAsSVEVector.
+    kPrintRegPartial = 1 << 6,
+
+// Supported combinations.
+// These exist so that they can be referred to by name, but also because C++
+// does not allow enum types to hold values that aren't explicitly
+// enumerated, and we want to be able to combine the above flags.
+
+// Scalar formats.
+#define VIXL_DECL_PRINT_REG_SCALAR(size)                           \
+  kPrint##size##Reg = kPrintRegLaneSize##size | kPrintRegAsScalar, \
+  kPrint##size##RegPartial = kPrintRegLaneSize##size | kPrintRegPartial
+#define VIXL_DECL_PRINT_REG_SCALAR_FP(size)                  \
+  VIXL_DECL_PRINT_REG_SCALAR(size)                           \
+  , kPrint##size##RegFP = kPrint##size##Reg | kPrintRegAsFP, \
+    kPrint##size##RegPartialFP = kPrint##size##RegPartial | kPrintRegAsFP
+    VIXL_DECL_PRINT_REG_SCALAR(W),
+    VIXL_DECL_PRINT_REG_SCALAR(X),
+    VIXL_DECL_PRINT_REG_SCALAR_FP(H),
+    VIXL_DECL_PRINT_REG_SCALAR_FP(S),
+    VIXL_DECL_PRINT_REG_SCALAR_FP(D),
+    VIXL_DECL_PRINT_REG_SCALAR(Q),
+#undef VIXL_DECL_PRINT_REG_SCALAR
+#undef VIXL_DECL_PRINT_REG_SCALAR_FP
+
+#define VIXL_DECL_PRINT_REG_NEON(count, type, size)                     \
+  kPrintReg##count##type = kPrintRegLaneSize##type | kPrintRegAs##size, \
+  kPrintReg##count##type##Partial = kPrintReg##count##type | kPrintRegPartial
+#define VIXL_DECL_PRINT_REG_NEON_FP(count, type, size)                   \
+  VIXL_DECL_PRINT_REG_NEON(count, type, size)                            \
+  , kPrintReg##count##type##FP = kPrintReg##count##type | kPrintRegAsFP, \
+    kPrintReg##count##type##PartialFP =                                  \
+        kPrintReg##count##type##Partial | kPrintRegAsFP
+    VIXL_DECL_PRINT_REG_NEON(1, B, Scalar),
+    VIXL_DECL_PRINT_REG_NEON(8, B, DVector),
+    VIXL_DECL_PRINT_REG_NEON(16, B, QVector),
+    VIXL_DECL_PRINT_REG_NEON_FP(1, H, Scalar),
+    VIXL_DECL_PRINT_REG_NEON_FP(4, H, DVector),
+    VIXL_DECL_PRINT_REG_NEON_FP(8, H, QVector),
+    VIXL_DECL_PRINT_REG_NEON_FP(1, S, Scalar),
+    VIXL_DECL_PRINT_REG_NEON_FP(2, S, DVector),
+    VIXL_DECL_PRINT_REG_NEON_FP(4, S, QVector),
+    VIXL_DECL_PRINT_REG_NEON_FP(1, D, Scalar),
+    VIXL_DECL_PRINT_REG_NEON_FP(2, D, QVector),
+    VIXL_DECL_PRINT_REG_NEON(1, Q, Scalar),
+#undef VIXL_DECL_PRINT_REG_NEON
+#undef VIXL_DECL_PRINT_REG_NEON_FP
+
+#define VIXL_DECL_PRINT_REG_SVE(type)                                 \
+  kPrintRegVn##type = kPrintRegLaneSize##type | kPrintRegAsSVEVector, \
+  kPrintRegVn##type##Partial = kPrintRegVn##type | kPrintRegPartial
+#define VIXL_DECL_PRINT_REG_SVE_FP(type)                       \
+  VIXL_DECL_PRINT_REG_SVE(type)                                \
+  , kPrintRegVn##type##FP = kPrintRegVn##type | kPrintRegAsFP, \
+    kPrintRegVn##type##PartialFP = kPrintRegVn##type##Partial | kPrintRegAsFP
+    VIXL_DECL_PRINT_REG_SVE(B),
+    VIXL_DECL_PRINT_REG_SVE_FP(H),
+    VIXL_DECL_PRINT_REG_SVE_FP(S),
+    VIXL_DECL_PRINT_REG_SVE_FP(D),
+    VIXL_DECL_PRINT_REG_SVE(Q)
+#undef VIXL_DECL_PRINT_REG_SVE
+#undef VIXL_DECL_PRINT_REG_SVE_FP
   };
 
+  // Return `format` with the kPrintRegPartial flag set.
+  PrintRegisterFormat GetPrintRegPartial(PrintRegisterFormat format) {
+    // Every PrintRegisterFormat has a kPrintRegPartial counterpart, so the
+    // result of this cast will always be well-defined.
+    return static_cast<PrintRegisterFormat>(format | kPrintRegPartial);
+  }
+
+  // For SVE formats, return the format of a Q register part of it.
+  PrintRegisterFormat GetPrintRegAsQChunkOfSVE(PrintRegisterFormat format) {
+    VIXL_ASSERT((format & kPrintRegAsVectorMask) == kPrintRegAsSVEVector);
+    // Keep the FP and lane size fields.
+    int q_format = format & (kPrintRegLaneSizeMask | kPrintRegAsFP);
+    // The resulting format must always be partial, because we're not formatting
+    // the whole Z register.
+    q_format |= (kPrintRegAsQVector | kPrintRegPartial);
+
+    // This cast is always safe because NEON QVector formats support every
+    // combination of FP and lane size that SVE formats do.
+    return static_cast<PrintRegisterFormat>(q_format);
+  }
+
   unsigned GetPrintRegLaneSizeInBytesLog2(PrintRegisterFormat format) {
+    VIXL_ASSERT((format & kPrintRegLaneSizeMask) != kPrintRegLaneSizeUnknown);
     return (format & kPrintRegLaneSizeMask) >> kPrintRegLaneSizeOffset;
   }
 
@@ -1411,17 +1955,51 @@ class Simulator : public DecoderVisitor {
   }
 
   unsigned GetPrintRegSizeInBytesLog2(PrintRegisterFormat format) {
-    if (format & kPrintRegAsDVector) return kDRegSizeInBytesLog2;
-    if (format & kPrintRegAsQVector) return kQRegSizeInBytesLog2;
-
-    // Scalar types.
-    return GetPrintRegLaneSizeInBytesLog2(format);
+    switch (format & kPrintRegAsVectorMask) {
+      case kPrintRegAsScalar:
+        return GetPrintRegLaneSizeInBytesLog2(format);
+      case kPrintRegAsDVector:
+        return kDRegSizeInBytesLog2;
+      case kPrintRegAsQVector:
+        return kQRegSizeInBytesLog2;
+      default:
+      case kPrintRegAsSVEVector:
+        // We print SVE vectors in Q-sized chunks. These need special handling,
+        // and it's probably an error to call this function in that case.
+        VIXL_UNREACHABLE();
+        return kQRegSizeInBytesLog2;
+    }
   }
 
   unsigned GetPrintRegSizeInBytes(PrintRegisterFormat format) {
     return 1 << GetPrintRegSizeInBytesLog2(format);
   }
 
+  unsigned GetPrintRegSizeInBitsLog2(PrintRegisterFormat format) {
+    return GetPrintRegSizeInBytesLog2(format) + kBitsPerByteLog2;
+  }
+
+  unsigned GetPrintRegSizeInBits(PrintRegisterFormat format) {
+    return 1 << GetPrintRegSizeInBitsLog2(format);
+  }
+
+  const char* GetPartialRegSuffix(PrintRegisterFormat format) {
+    switch (GetPrintRegSizeInBitsLog2(format)) {
+      case kBRegSizeLog2:
+        return "<7:0>";
+      case kHRegSizeLog2:
+        return "<15:0>";
+      case kSRegSizeLog2:
+        return "<31:0>";
+      case kDRegSizeLog2:
+        return "<63:0>";
+      case kQRegSizeLog2:
+        return "<127:0>";
+    }
+    VIXL_UNREACHABLE();
+    return "<UNKNOWN>";
+  }
+
   unsigned GetPrintRegLaneCount(PrintRegisterFormat format) {
     unsigned reg_size_log2 = GetPrintRegSizeInBytesLog2(format);
     unsigned lane_size_log2 = GetPrintRegLaneSizeInBytesLog2(format);
@@ -1429,6 +2007,21 @@ class Simulator : public DecoderVisitor {
     return 1 << (reg_size_log2 - lane_size_log2);
   }
 
+  uint16_t GetPrintRegLaneMask(PrintRegisterFormat format) {
+    int print_as = format & kPrintRegAsVectorMask;
+    if (print_as == kPrintRegAsScalar) return 1;
+
+    // Vector formats, including SVE formats printed in Q-sized chunks.
+    static const uint16_t masks[] = {0xffff, 0x5555, 0x1111, 0x0101, 0x0001};
+    unsigned size_in_bytes_log2 = GetPrintRegLaneSizeInBytesLog2(format);
+    VIXL_ASSERT(size_in_bytes_log2 < ArrayLength(masks));
+    uint16_t mask = masks[size_in_bytes_log2];
+
+    // Exclude lanes that aren't visible in D vectors.
+    if (print_as == kPrintRegAsDVector) mask &= 0x00ff;
+    return mask;
+  }
+
   PrintRegisterFormat GetPrintRegisterFormatForSize(unsigned reg_size,
                                                     unsigned lane_size);
 
@@ -1459,6 +2052,10 @@ class Simulator : public DecoderVisitor {
     return format;
   }
 
+  PrintRegisterFormat GetPrintRegisterFormatForSizeTryFP(unsigned size) {
+    return GetPrintRegisterFormatTryFP(GetPrintRegisterFormatForSize(size));
+  }
+
   template <typename T>
   PrintRegisterFormat GetPrintRegisterFormat(T value) {
     return GetPrintRegisterFormatForSize(sizeof(value));
@@ -1485,99 +2082,314 @@ class Simulator : public DecoderVisitor {
   // Print all registers of the specified types.
   void PrintRegisters();
   void PrintVRegisters();
+  void PrintZRegisters();
   void PrintSystemRegisters();
 
   // As above, but only print the registers that have been updated.
   void PrintWrittenRegisters();
   void PrintWrittenVRegisters();
+  void PrintWrittenPRegisters();
 
   // As above, but respect LOG_REG and LOG_VREG.
   void LogWrittenRegisters() {
-    if (GetTraceParameters() & LOG_REGS) PrintWrittenRegisters();
+    if (ShouldTraceRegs()) PrintWrittenRegisters();
   }
   void LogWrittenVRegisters() {
-    if (GetTraceParameters() & LOG_VREGS) PrintWrittenVRegisters();
+    if (ShouldTraceVRegs()) PrintWrittenVRegisters();
+  }
+  void LogWrittenPRegisters() {
+    if (ShouldTraceVRegs()) PrintWrittenPRegisters();
   }
   void LogAllWrittenRegisters() {
     LogWrittenRegisters();
     LogWrittenVRegisters();
+    LogWrittenPRegisters();
+  }
+
+  // The amount of space to leave for a register name. This is used to keep the
+  // values vertically aligned. The longest register name has the form
+  // "z31<2047:1920>". The total overall value indentation must also take into
+  // account the fixed formatting: "# {name}: 0x{value}".
+  static const int kPrintRegisterNameFieldWidth = 14;
+
+  // Print whole, individual register values.
+  // - The format can be used to restrict how much of the register is printed,
+  //   but such formats indicate that the unprinted high-order bits are zero and
+  //   these helpers will assert that.
+  // - If the format includes the kPrintRegAsFP flag then human-friendly FP
+  //   value annotations will be printed.
+  // - The suffix can be used to add annotations (such as memory access
+  //   details), or to suppress the newline.
+  void PrintRegister(int code,
+                     PrintRegisterFormat format = kPrintXReg,
+                     const char* suffix = "\n");
+  void PrintVRegister(int code,
+                      PrintRegisterFormat format = kPrintReg1Q,
+                      const char* suffix = "\n");
+  // PrintZRegister and PrintPRegister print over several lines, so they cannot
+  // allow the suffix to be overridden.
+  void PrintZRegister(int code, PrintRegisterFormat format = kPrintRegVnQ);
+  void PrintPRegister(int code, PrintRegisterFormat format = kPrintRegVnQ);
+  void PrintFFR(PrintRegisterFormat format = kPrintRegVnQ);
+  // Print a single Q-sized part of a Z register, or the corresponding two-byte
+  // part of a P register. These print single lines, and therefore allow the
+  // suffix to be overridden. The format must include the kPrintRegPartial flag.
+  void PrintPartialZRegister(int code,
+                             int q_index,
+                             PrintRegisterFormat format = kPrintRegVnQ,
+                             const char* suffix = "\n");
+  void PrintPartialPRegister(int code,
+                             int q_index,
+                             PrintRegisterFormat format = kPrintRegVnQ,
+                             const char* suffix = "\n");
+  void PrintPartialPRegister(const char* name,
+                             const SimPRegister& reg,
+                             int q_index,
+                             PrintRegisterFormat format = kPrintRegVnQ,
+                             const char* suffix = "\n");
+
+  // Like Print*Register (above), but respect trace parameters.
+  void LogRegister(unsigned code, PrintRegisterFormat format) {
+    if (ShouldTraceRegs()) PrintRegister(code, format);
+  }
+  void LogVRegister(unsigned code, PrintRegisterFormat format) {
+    if (ShouldTraceVRegs()) PrintVRegister(code, format);
+  }
+  void LogZRegister(unsigned code, PrintRegisterFormat format) {
+    if (ShouldTraceVRegs()) PrintZRegister(code, format);
+  }
+  void LogPRegister(unsigned code, PrintRegisterFormat format) {
+    if (ShouldTraceVRegs()) PrintPRegister(code, format);
+  }
+  void LogFFR(PrintRegisterFormat format) {
+    if (ShouldTraceVRegs()) PrintFFR(format);
   }
 
-  // Print individual register values (after update).
-  void PrintRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer);
-  void PrintVRegister(unsigned code, PrintRegisterFormat format);
+  // Other state updates, including system registers.
   void PrintSystemRegister(SystemRegister id);
   void PrintTakenBranch(const Instruction* target);
+  void LogSystemRegister(SystemRegister id) {
+    if (ShouldTraceSysRegs()) PrintSystemRegister(id);
+  }
+  void LogTakenBranch(const Instruction* target) {
+    if (ShouldTraceBranches()) PrintTakenBranch(target);
+  }
 
-  // Like Print* (above), but respect GetTraceParameters().
-  void LogRegister(unsigned code, Reg31Mode r31mode = Reg31IsStackPointer) {
-    if (GetTraceParameters() & LOG_REGS) PrintRegister(code, r31mode);
+  // Trace memory accesses.
+
+  // Common, contiguous register accesses (such as for scalars).
+  // The *Write variants automatically set kPrintRegPartial on the format.
+  void PrintRead(int rt_code, PrintRegisterFormat format, uintptr_t address);
+  void PrintExtendingRead(int rt_code,
+                          PrintRegisterFormat format,
+                          int access_size_in_bytes,
+                          uintptr_t address);
+  void PrintWrite(int rt_code, PrintRegisterFormat format, uintptr_t address);
+  void PrintVRead(int rt_code, PrintRegisterFormat format, uintptr_t address);
+  void PrintVWrite(int rt_code, PrintRegisterFormat format, uintptr_t address);
+  // Simple, unpredicated SVE accesses always access the whole vector, and never
+  // know the lane type, so there's no need to accept a `format`.
+  void PrintZRead(int rt_code, uintptr_t address) {
+    vregisters_[rt_code].NotifyRegisterLogged();
+    PrintZAccess(rt_code, "<-", address);
   }
-  void LogVRegister(unsigned code, PrintRegisterFormat format) {
-    if (GetTraceParameters() & LOG_VREGS) PrintVRegister(code, format);
+  void PrintZWrite(int rt_code, uintptr_t address) {
+    PrintZAccess(rt_code, "->", address);
   }
-  void LogSystemRegister(SystemRegister id) {
-    if (GetTraceParameters() & LOG_SYSREGS) PrintSystemRegister(id);
+  void PrintPRead(int rt_code, uintptr_t address) {
+    pregisters_[rt_code].NotifyRegisterLogged();
+    PrintPAccess(rt_code, "<-", address);
+  }
+  void PrintPWrite(int rt_code, uintptr_t address) {
+    PrintPAccess(rt_code, "->", address);
   }
-  void LogTakenBranch(const Instruction* target) {
-    if (GetTraceParameters() & LOG_BRANCH) PrintTakenBranch(target);
-  }
-
-  // Print memory accesses.
-  void PrintRead(uintptr_t address,
-                 unsigned reg_code,
-                 PrintRegisterFormat format);
-  void PrintWrite(uintptr_t address,
-                  unsigned reg_code,
-                  PrintRegisterFormat format);
-  void PrintVRead(uintptr_t address,
-                  unsigned reg_code,
-                  PrintRegisterFormat format,
-                  unsigned lane);
-  void PrintVWrite(uintptr_t address,
-                   unsigned reg_code,
-                   PrintRegisterFormat format,
-                   unsigned lane);
 
   // Like Print* (above), but respect GetTraceParameters().
-  void LogRead(uintptr_t address,
-               unsigned reg_code,
-               PrintRegisterFormat format) {
-    if (GetTraceParameters() & LOG_REGS) PrintRead(address, reg_code, format);
-  }
-  void LogWrite(uintptr_t address,
-                unsigned reg_code,
-                PrintRegisterFormat format) {
-    if (GetTraceParameters() & LOG_WRITE) PrintWrite(address, reg_code, format);
-  }
-  void LogVRead(uintptr_t address,
-                unsigned reg_code,
-                PrintRegisterFormat format,
-                unsigned lane = 0) {
-    if (GetTraceParameters() & LOG_VREGS) {
-      PrintVRead(address, reg_code, format, lane);
+  void LogRead(int rt_code, PrintRegisterFormat format, uintptr_t address) {
+    if (ShouldTraceRegs()) PrintRead(rt_code, format, address);
+  }
+  void LogExtendingRead(int rt_code,
+                        PrintRegisterFormat format,
+                        int access_size_in_bytes,
+                        uintptr_t address) {
+    if (ShouldTraceRegs()) {
+      PrintExtendingRead(rt_code, format, access_size_in_bytes, address);
     }
   }
-  void LogVWrite(uintptr_t address,
-                 unsigned reg_code,
-                 PrintRegisterFormat format,
-                 unsigned lane = 0) {
-    if (GetTraceParameters() & LOG_WRITE) {
-      PrintVWrite(address, reg_code, format, lane);
-    }
+  void LogWrite(int rt_code, PrintRegisterFormat format, uintptr_t address) {
+    if (ShouldTraceWrites()) PrintWrite(rt_code, format, address);
+  }
+  void LogVRead(int rt_code, PrintRegisterFormat format, uintptr_t address) {
+    if (ShouldTraceVRegs()) PrintVRead(rt_code, format, address);
+  }
+  void LogVWrite(int rt_code, PrintRegisterFormat format, uintptr_t address) {
+    if (ShouldTraceWrites()) PrintVWrite(rt_code, format, address);
+  }
+  void LogZRead(int rt_code, uintptr_t address) {
+    if (ShouldTraceVRegs()) PrintZRead(rt_code, address);
+  }
+  void LogZWrite(int rt_code, uintptr_t address) {
+    if (ShouldTraceWrites()) PrintZWrite(rt_code, address);
+  }
+  void LogPRead(int rt_code, uintptr_t address) {
+    if (ShouldTraceVRegs()) PrintPRead(rt_code, address);
+  }
+  void LogPWrite(int rt_code, uintptr_t address) {
+    if (ShouldTraceWrites()) PrintPWrite(rt_code, address);
+  }
+
+  // Helpers for the above, where the access operation is parameterised.
+  // - For loads, set op = "<-".
+  // - For stores, set op = "->".
+  void PrintAccess(int rt_code,
+                   PrintRegisterFormat format,
+                   const char* op,
+                   uintptr_t address);
+  void PrintVAccess(int rt_code,
+                    PrintRegisterFormat format,
+                    const char* op,
+                    uintptr_t address);
+  // Simple, unpredicated SVE accesses always access the whole vector, and never
+  // know the lane type, so these don't accept a `format`.
+  void PrintZAccess(int rt_code, const char* op, uintptr_t address);
+  void PrintPAccess(int rt_code, const char* op, uintptr_t address);
+
+  // Multiple-structure accesses.
+  void PrintVStructAccess(int rt_code,
+                          int reg_count,
+                          PrintRegisterFormat format,
+                          const char* op,
+                          uintptr_t address);
+  // Single-structure (single-lane) accesses.
+  void PrintVSingleStructAccess(int rt_code,
+                                int reg_count,
+                                int lane,
+                                PrintRegisterFormat format,
+                                const char* op,
+                                uintptr_t address);
+  // Replicating accesses.
+  void PrintVReplicatingStructAccess(int rt_code,
+                                     int reg_count,
+                                     PrintRegisterFormat format,
+                                     const char* op,
+                                     uintptr_t address);
+
+  // Multiple-structure accesses.
+  void PrintZStructAccess(int rt_code,
+                          int reg_count,
+                          const LogicPRegister& pg,
+                          PrintRegisterFormat format,
+                          int msize_in_bytes,
+                          const char* op,
+                          const LogicSVEAddressVector& addr);
+
+  // Register-printing helper for all structured accessors.
+  //
+  // All lanes (according to `format`) are printed, but lanes indicated by
+  // `focus_mask` are of particular interest. Each bit corresponds to a byte in
+  // the printed register, in a manner similar to SVE's predicates. Currently,
+  // this is used to determine when to print human-readable FP annotations.
+  void PrintVRegistersForStructuredAccess(int rt_code,
+                                          int reg_count,
+                                          uint16_t focus_mask,
+                                          PrintRegisterFormat format);
+
+  // As for the VRegister variant, but print partial Z register names.
+  void PrintZRegistersForStructuredAccess(int rt_code,
+                                          int q_index,
+                                          int reg_count,
+                                          uint16_t focus_mask,
+                                          PrintRegisterFormat format);
+
+  // Print part of a memory access. This should be used for annotating
+  // non-trivial accesses, such as structured or sign-extending loads. Call
+  // Print*Register (or Print*RegistersForStructuredAccess), then
+  // PrintPartialAccess for each contiguous access that makes up the
+  // instruction.
+  //
+  //  access_mask:
+  //      The lanes to be printed. Each bit corresponds to a byte in the printed
+  //      register, in a manner similar to SVE's predicates, except that the
+  //      lane size is not respected when interpreting lane_mask: unaligned bits
+  //      must be zeroed.
+  //
+  //      This function asserts that this mask is non-zero.
+  //
+  //  future_access_mask:
+  //      The lanes to be printed by a future invocation. This must be specified
+  //      because vertical lines are drawn for partial accesses that haven't yet
+  //      been printed. The format is the same as for accessed_mask.
+  //
+  //      If a lane is active in both `access_mask` and `future_access_mask`,
+  //      `access_mask` takes precedence.
+  //
+  //  struct_element_count:
+  //      The number of elements in each structure. For non-structured accesses,
+  //      set this to one. Along with lane_size_in_bytes, this is used determine
+  //      the size of each access, and to format the accessed value.
+  //
+  //  op:
+  //      For stores, use "->". For loads, use "<-".
+  //
+  //  address:
+  //      The address of this partial access. (Not the base address of the whole
+  //      instruction.) The traced value is read from this address (according to
+  //      part_count and lane_size_in_bytes) so it must be accessible, and when
+  //      tracing stores, the store must have been executed before this function
+  //      is called.
+  //
+  //  reg_size_in_bytes:
+  //      The size of the register being accessed. This helper is usually used
+  //      for V registers or Q-sized chunks of Z registers, so that is the
+  //      default, but it is possible to use this to annotate X register
+  //      accesses by specifying kXRegSizeInBytes.
+  //
+  // The return value is a future_access_mask suitable for the next iteration,
+  // so that it is possible to execute this in a loop, until the mask is zero.
+  // Note that accessed_mask must still be updated by the caller for each call.
+  uint16_t PrintPartialAccess(uint16_t access_mask,
+                              uint16_t future_access_mask,
+                              int struct_element_count,
+                              int lane_size_in_bytes,
+                              const char* op,
+                              uintptr_t address,
+                              int reg_size_in_bytes = kQRegSizeInBytes);
+
+  // Print an abstract register value. This works for all register types, and
+  // can print parts of registers. This exists to ensure consistent formatting
+  // of values.
+  void PrintRegisterValue(const uint8_t* value,
+                          int value_size,
+                          PrintRegisterFormat format);
+  template <typename T>
+  void PrintRegisterValue(const T& sim_register, PrintRegisterFormat format) {
+    PrintRegisterValue(sim_register.GetBytes(),
+                       std::min(sim_register.GetSizeInBytes(),
+                                kQRegSizeInBytes),
+                       format);
   }
 
-  // Helper functions for register tracing.
-  void PrintRegisterRawHelper(unsigned code,
-                              Reg31Mode r31mode,
-                              int size_in_bytes = kXRegSizeInBytes);
-  void PrintVRegisterRawHelper(unsigned code,
-                               int bytes = kQRegSizeInBytes,
-                               int lsb = 0);
-  void PrintVRegisterFPHelper(unsigned code,
-                              unsigned lane_size_in_bytes,
-                              int lane_count = 1,
-                              int rightmost_lane = 0);
+  // As above, but format as an SVE predicate value, using binary notation with
+  // spaces between each bit so that they align with the Z register bytes that
+  // they predicate.
+  void PrintPRegisterValue(uint16_t value);
+
+  void PrintRegisterValueFPAnnotations(const uint8_t* value,
+                                       uint16_t lane_mask,
+                                       PrintRegisterFormat format);
+  template <typename T>
+  void PrintRegisterValueFPAnnotations(const T& sim_register,
+                                       uint16_t lane_mask,
+                                       PrintRegisterFormat format) {
+    PrintRegisterValueFPAnnotations(sim_register.GetBytes(), lane_mask, format);
+  }
+  template <typename T>
+  void PrintRegisterValueFPAnnotations(const T& sim_register,
+                                       PrintRegisterFormat format) {
+    PrintRegisterValueFPAnnotations(sim_register.GetBytes(),
+                                    GetPrintRegLaneMask(format),
+                                    format);
+  }
 
   VIXL_NO_RETURN void DoUnreachable(const Instruction* instr);
   void DoTrace(const Instruction* instr);
@@ -1587,10 +2399,13 @@ class Simulator : public DecoderVisitor {
                                      Reg31Mode mode = Reg31IsZeroRegister);
   static const char* XRegNameForCode(unsigned code,
                                      Reg31Mode mode = Reg31IsZeroRegister);
+  static const char* BRegNameForCode(unsigned code);
   static const char* HRegNameForCode(unsigned code);
   static const char* SRegNameForCode(unsigned code);
   static const char* DRegNameForCode(unsigned code);
   static const char* VRegNameForCode(unsigned code);
+  static const char* ZRegNameForCode(unsigned code);
+  static const char* PRegNameForCode(unsigned code);
 
   bool IsColouredTrace() const { return coloured_trace_; }
   VIXL_DEPRECATED("IsColouredTrace", bool coloured_trace() const) {
@@ -1609,18 +2424,28 @@ class Simulator : public DecoderVisitor {
     return GetTraceParameters();
   }
 
+  bool ShouldTraceWrites() const {
+    return (GetTraceParameters() & LOG_WRITE) != 0;
+  }
+  bool ShouldTraceRegs() const {
+    return (GetTraceParameters() & LOG_REGS) != 0;
+  }
+  bool ShouldTraceVRegs() const {
+    return (GetTraceParameters() & LOG_VREGS) != 0;
+  }
+  bool ShouldTraceSysRegs() const {
+    return (GetTraceParameters() & LOG_SYSREGS) != 0;
+  }
+  bool ShouldTraceBranches() const {
+    return (GetTraceParameters() & LOG_BRANCH) != 0;
+  }
+
   void SetTraceParameters(int parameters);
   VIXL_DEPRECATED("SetTraceParameters",
                   void set_trace_parameters(int parameters)) {
     SetTraceParameters(parameters);
   }
 
-  void SetInstructionStats(bool value);
-  VIXL_DEPRECATED("SetInstructionStats",
-                  void set_instruction_stats(bool value)) {
-    SetInstructionStats(value);
-  }
-
   // Clear the simulated local monitor to force the next store-exclusive
   // instruction to fail.
   void ClearLocalMonitor() { local_monitor_.Clear(); }
@@ -1803,6 +2628,92 @@ class Simulator : public DecoderVisitor {
   };
 #endif
 
+  // Configure the simulated value of 'VL', which is the size of a Z register.
+  // Because this cannot occur during a program's lifetime, this function also
+  // resets the SVE registers.
+  void SetVectorLengthInBits(unsigned vector_length);
+
+  unsigned GetVectorLengthInBits() const { return vector_length_; }
+  unsigned GetVectorLengthInBytes() const {
+    VIXL_ASSERT((vector_length_ % kBitsPerByte) == 0);
+    return vector_length_ / kBitsPerByte;
+  }
+  unsigned GetPredicateLengthInBits() const {
+    VIXL_ASSERT((GetVectorLengthInBits() % kZRegBitsPerPRegBit) == 0);
+    return GetVectorLengthInBits() / kZRegBitsPerPRegBit;
+  }
+  unsigned GetPredicateLengthInBytes() const {
+    VIXL_ASSERT((GetVectorLengthInBytes() % kZRegBitsPerPRegBit) == 0);
+    return GetVectorLengthInBytes() / kZRegBitsPerPRegBit;
+  }
+
+  unsigned RegisterSizeInBitsFromFormat(VectorFormat vform) const {
+    if (IsSVEFormat(vform)) {
+      return GetVectorLengthInBits();
+    } else {
+      return vixl::aarch64::RegisterSizeInBitsFromFormat(vform);
+    }
+  }
+
+  unsigned RegisterSizeInBytesFromFormat(VectorFormat vform) const {
+    unsigned size_in_bits = RegisterSizeInBitsFromFormat(vform);
+    VIXL_ASSERT((size_in_bits % kBitsPerByte) == 0);
+    return size_in_bits / kBitsPerByte;
+  }
+
+  int LaneCountFromFormat(VectorFormat vform) const {
+    if (IsSVEFormat(vform)) {
+      return GetVectorLengthInBits() / LaneSizeInBitsFromFormat(vform);
+    } else {
+      return vixl::aarch64::LaneCountFromFormat(vform);
+    }
+  }
+
+  bool IsFirstActive(VectorFormat vform,
+                     const LogicPRegister& mask,
+                     const LogicPRegister& bits) {
+    for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+      if (mask.IsActive(vform, i)) {
+        return bits.IsActive(vform, i);
+      }
+    }
+    return false;
+  }
+
+  bool AreNoneActive(VectorFormat vform,
+                     const LogicPRegister& mask,
+                     const LogicPRegister& bits) {
+    for (int i = 0; i < LaneCountFromFormat(vform); i++) {
+      if (mask.IsActive(vform, i) && bits.IsActive(vform, i)) {
+        return false;
+      }
+    }
+    return true;
+  }
+
+  bool IsLastActive(VectorFormat vform,
+                    const LogicPRegister& mask,
+                    const LogicPRegister& bits) {
+    for (int i = LaneCountFromFormat(vform) - 1; i >= 0; i--) {
+      if (mask.IsActive(vform, i)) {
+        return bits.IsActive(vform, i);
+      }
+    }
+    return false;
+  }
+
+  void PredTest(VectorFormat vform,
+                const LogicPRegister& mask,
+                const LogicPRegister& bits) {
+    ReadNzcv().SetN(IsFirstActive(vform, mask, bits));
+    ReadNzcv().SetZ(AreNoneActive(vform, mask, bits));
+    ReadNzcv().SetC(!IsLastActive(vform, mask, bits));
+    ReadNzcv().SetV(0);
+    LogSystemRegister(NZCV);
+  }
+
+  SimPRegister& GetPTrue() { return pregister_all_true_; }
+
  protected:
   const char* clr_normal;
   const char* clr_flag_name;
@@ -1811,6 +2722,8 @@ class Simulator : public DecoderVisitor {
   const char* clr_reg_value;
   const char* clr_vreg_name;
   const char* clr_vreg_value;
+  const char* clr_preg_name;
+  const char* clr_preg_value;
   const char* clr_memory_address;
   const char* clr_warning;
   const char* clr_warning_message;
@@ -1818,6 +2731,13 @@ class Simulator : public DecoderVisitor {
   const char* clr_branch_marker;
 
   // Simulation helpers ------------------------------------
+
+  void ResetSystemRegisters();
+  void ResetRegisters();
+  void ResetVRegisters();
+  void ResetPRegisters();
+  void ResetFFR();
+
   bool ConditionPassed(Condition cond) {
     switch (cond) {
       case eq:
@@ -1907,7 +2827,7 @@ class Simulator : public DecoderVisitor {
   }
 
   int64_t ShiftOperand(unsigned reg_size,
-                       int64_t value,
+                       uint64_t value,
                        Shift shift_type,
                        unsigned amount) const;
   int64_t ExtendValue(unsigned reg_width,
@@ -1919,6 +2839,11 @@ class Simulator : public DecoderVisitor {
   void ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr);
   void ld1(VectorFormat vform, LogicVRegister dst, int index, uint64_t addr);
   void ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr);
+  void ld1r(VectorFormat vform,
+            VectorFormat unpack_vform,
+            LogicVRegister dst,
+            uint64_t addr,
+            bool is_signed = false);
   void ld2(VectorFormat vform,
            LogicVRegister dst1,
            LogicVRegister dst2,
@@ -2020,16 +2945,43 @@ class Simulator : public DecoderVisitor {
                      LogicVRegister dst,
                      const LogicVRegister& src1,
                      const LogicVRegister& src2);
+  // Add `value` to each lane of `src1`, treating `value` as unsigned for the
+  // purposes of setting the saturation flags.
+  LogicVRegister add_uint(VectorFormat vform,
+                          LogicVRegister dst,
+                          const LogicVRegister& src1,
+                          uint64_t value);
   LogicVRegister addp(VectorFormat vform,
                       LogicVRegister dst,
                       const LogicVRegister& src1,
                       const LogicVRegister& src2);
+  LogicPRegister brka(LogicPRegister pd,
+                      const LogicPRegister& pg,
+                      const LogicPRegister& pn);
+  LogicPRegister brkb(LogicPRegister pd,
+                      const LogicPRegister& pg,
+                      const LogicPRegister& pn);
+  LogicPRegister brkn(LogicPRegister pdm,
+                      const LogicPRegister& pg,
+                      const LogicPRegister& pn);
+  LogicPRegister brkpa(LogicPRegister pd,
+                       const LogicPRegister& pg,
+                       const LogicPRegister& pn,
+                       const LogicPRegister& pm);
+  LogicPRegister brkpb(LogicPRegister pd,
+                       const LogicPRegister& pg,
+                       const LogicPRegister& pn,
+                       const LogicPRegister& pm);
+  // dst = srca + src1 * src2
   LogicVRegister mla(VectorFormat vform,
                      LogicVRegister dst,
+                     const LogicVRegister& srca,
                      const LogicVRegister& src1,
                      const LogicVRegister& src2);
+  // dst = srca - src1 * src2
   LogicVRegister mls(VectorFormat vform,
                      LogicVRegister dst,
+                     const LogicVRegister& srca,
                      const LogicVRegister& src1,
                      const LogicVRegister& src2);
   LogicVRegister mul(VectorFormat vform,
@@ -2055,6 +3007,14 @@ class Simulator : public DecoderVisitor {
                       LogicVRegister dst,
                       const LogicVRegister& src1,
                       const LogicVRegister& src2);
+  LogicVRegister sdiv(VectorFormat vform,
+                      LogicVRegister dst,
+                      const LogicVRegister& src1,
+                      const LogicVRegister& src2);
+  LogicVRegister udiv(VectorFormat vform,
+                      LogicVRegister dst,
+                      const LogicVRegister& src1,
+                      const LogicVRegister& src2);
 
   typedef LogicVRegister (Simulator::*ByElementOp)(VectorFormat vform,
                                                    LogicVRegister dst,
@@ -2101,6 +3061,10 @@ class Simulator : public DecoderVisitor {
                        const LogicVRegister& src1,
                        const LogicVRegister& src2,
                        int index);
+  LogicVRegister smulh(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicVRegister& src1,
+                       const LogicVRegister& src2);
   LogicVRegister smull(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src1,
@@ -2161,6 +3125,10 @@ class Simulator : public DecoderVisitor {
                         const LogicVRegister& src1,
                         const LogicVRegister& src2,
                         int index);
+  LogicVRegister umulh(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicVRegister& src1,
+                       const LogicVRegister& src2);
   LogicVRegister sqdmull(VectorFormat vform,
                          LogicVRegister dst,
                          const LogicVRegister& src1,
@@ -2225,6 +3193,12 @@ class Simulator : public DecoderVisitor {
                      LogicVRegister dst,
                      const LogicVRegister& src1,
                      const LogicVRegister& src2);
+  // Subtract `value` from each lane of `src1`, treating `value` as unsigned for
+  // the purposes of setting the saturation flags.
+  LogicVRegister sub_uint(VectorFormat vform,
+                          LogicVRegister dst,
+                          const LogicVRegister& src1,
+                          uint64_t value);
   LogicVRegister and_(VectorFormat vform,
                       LogicVRegister dst,
                       const LogicVRegister& src1,
@@ -2267,6 +3241,9 @@ class Simulator : public DecoderVisitor {
   LogicVRegister clz(VectorFormat vform,
                      LogicVRegister dst,
                      const LogicVRegister& src);
+  LogicVRegister cnot(VectorFormat vform,
+                      LogicVRegister dst,
+                      const LogicVRegister& src);
   LogicVRegister cnt(VectorFormat vform,
                      LogicVRegister dst,
                      const LogicVRegister& src);
@@ -2278,8 +3255,11 @@ class Simulator : public DecoderVisitor {
                       const LogicVRegister& src);
   LogicVRegister rev(VectorFormat vform,
                      LogicVRegister dst,
-                     const LogicVRegister& src,
-                     int revSize);
+                     const LogicVRegister& src);
+  LogicVRegister rev_byte(VectorFormat vform,
+                          LogicVRegister dst,
+                          const LogicVRegister& src,
+                          int rev_size);
   LogicVRegister rev16(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src);
@@ -2327,6 +3307,7 @@ class Simulator : public DecoderVisitor {
                        LogicVRegister dst,
                        const LogicVRegister& src1,
                        const LogicVRegister& src2,
+                       const LogicVRegister& acc,
                        int index,
                        int rot);
   LogicVRegister fcmla(VectorFormat vform,
@@ -2335,17 +3316,25 @@ class Simulator : public DecoderVisitor {
                        const LogicVRegister& src2,
                        int index,
                        int rot);
-  template <typename T>
   LogicVRegister fcmla(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src1,
                        const LogicVRegister& src2,
+                       const LogicVRegister& acc,
                        int rot);
-  LogicVRegister fcmla(VectorFormat vform,
+  template <typename T>
+  LogicVRegister fadda(VectorFormat vform,
+                       LogicVRegister acc,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src);
+  LogicVRegister fadda(VectorFormat vform,
+                       LogicVRegister acc,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src);
+  LogicVRegister index(VectorFormat vform,
                        LogicVRegister dst,
-                       const LogicVRegister& src1,
-                       const LogicVRegister& src2,
-                       int rot);
+                       uint64_t start,
+                       uint64_t step);
   LogicVRegister ins_element(VectorFormat vform,
                              LogicVRegister dst,
                              int dst_index,
@@ -2355,13 +3344,36 @@ class Simulator : public DecoderVisitor {
                                LogicVRegister dst,
                                int dst_index,
                                uint64_t imm);
+  LogicVRegister insr(VectorFormat vform, LogicVRegister dst, uint64_t imm);
   LogicVRegister dup_element(VectorFormat vform,
                              LogicVRegister dst,
                              const LogicVRegister& src,
                              int src_index);
+  LogicVRegister dup_elements_to_segments(VectorFormat vform,
+                                          LogicVRegister dst,
+                                          const LogicVRegister& src,
+                                          int src_index);
   LogicVRegister dup_immediate(VectorFormat vform,
                                LogicVRegister dst,
                                uint64_t imm);
+  LogicVRegister mov(VectorFormat vform,
+                     LogicVRegister dst,
+                     const LogicVRegister& src);
+  LogicPRegister mov(LogicPRegister dst, const LogicPRegister& src);
+  LogicVRegister mov_merging(VectorFormat vform,
+                             LogicVRegister dst,
+                             const SimPRegister& pg,
+                             const LogicVRegister& src);
+  LogicVRegister mov_zeroing(VectorFormat vform,
+                             LogicVRegister dst,
+                             const SimPRegister& pg,
+                             const LogicVRegister& src);
+  LogicPRegister mov_merging(LogicPRegister dst,
+                             const LogicPRegister& pg,
+                             const LogicPRegister& src);
+  LogicPRegister mov_zeroing(LogicPRegister dst,
+                             const LogicPRegister& pg,
+                             const LogicPRegister& src);
   LogicVRegister movi(VectorFormat vform, LogicVRegister dst, uint64_t imm);
   LogicVRegister mvni(VectorFormat vform, LogicVRegister dst, uint64_t imm);
   LogicVRegister orr(VectorFormat vform,
@@ -2376,6 +3388,32 @@ class Simulator : public DecoderVisitor {
                       LogicVRegister dst,
                       const LogicVRegister& src1,
                       const LogicVRegister& src2);
+  // Perform a "conditional last" operation. The first part of the pair is true
+  // if any predicate lane is active, false otherwise. The second part takes the
+  // value of the last active (plus offset) lane, or last (plus offset) lane if
+  // none active.
+  std::pair<bool, uint64_t> clast(VectorFormat vform,
+                                  const LogicPRegister& pg,
+                                  const LogicVRegister& src2,
+                                  int offset_from_last_active);
+  LogicVRegister compact(VectorFormat vform,
+                         LogicVRegister dst,
+                         const LogicPRegister& pg,
+                         const LogicVRegister& src);
+  LogicVRegister splice(VectorFormat vform,
+                        LogicVRegister dst,
+                        const LogicPRegister& pg,
+                        const LogicVRegister& src1,
+                        const LogicVRegister& src2);
+  LogicVRegister sel(VectorFormat vform,
+                     LogicVRegister dst,
+                     const SimPRegister& pg,
+                     const LogicVRegister& src1,
+                     const LogicVRegister& src2);
+  LogicPRegister sel(LogicPRegister dst,
+                     const LogicPRegister& pg,
+                     const LogicPRegister& src1,
+                     const LogicPRegister& src2);
   LogicVRegister sminmax(VectorFormat vform,
                          LogicVRegister dst,
                          const LogicVRegister& src1,
@@ -2416,6 +3454,7 @@ class Simulator : public DecoderVisitor {
                         const LogicVRegister& src);
   LogicVRegister sminmaxv(VectorFormat vform,
                           LogicVRegister dst,
+                          const LogicPRegister& pg,
                           const LogicVRegister& src,
                           bool max);
   LogicVRegister smaxv(VectorFormat vform,
@@ -2436,6 +3475,14 @@ class Simulator : public DecoderVisitor {
   LogicVRegister sxtl2(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src);
+  LogicVRegister uxt(VectorFormat vform,
+                     LogicVRegister dst,
+                     const LogicVRegister& src,
+                     unsigned from_size_in_bits);
+  LogicVRegister sxt(VectorFormat vform,
+                     LogicVRegister dst,
+                     const LogicVRegister& src,
+                     unsigned from_size_in_bits);
   LogicVRegister tbl(VectorFormat vform,
                      LogicVRegister dst,
                      const LogicVRegister& tab,
@@ -2460,6 +3507,10 @@ class Simulator : public DecoderVisitor {
                      const LogicVRegister& ind);
   LogicVRegister Table(VectorFormat vform,
                        LogicVRegister dst,
+                       const LogicVRegister& src,
+                       const LogicVRegister& tab);
+  LogicVRegister Table(VectorFormat vform,
+                       LogicVRegister dst,
                        const LogicVRegister& ind,
                        bool zero_out_of_bounds,
                        const LogicVRegister* tab1,
@@ -2580,6 +3631,7 @@ class Simulator : public DecoderVisitor {
                        const LogicVRegister& src2);
   LogicVRegister uminmaxv(VectorFormat vform,
                           LogicVRegister dst,
+                          const LogicPRegister& pg,
                           const LogicVRegister& src,
                           bool max);
   LogicVRegister umaxv(VectorFormat vform,
@@ -2617,11 +3669,27 @@ class Simulator : public DecoderVisitor {
                      const LogicVRegister& src,
                      int shift);
   LogicVRegister scvtf(VectorFormat vform,
+                       unsigned dst_data_size_in_bits,
+                       unsigned src_data_size_in_bits,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src,
+                       FPRounding round,
+                       int fbits = 0);
+  LogicVRegister scvtf(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src,
                        int fbits,
                        FPRounding rounding_mode);
   LogicVRegister ucvtf(VectorFormat vform,
+                       unsigned dst_data_size,
+                       unsigned src_data_size,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src,
+                       FPRounding round,
+                       int fbits = 0);
+  LogicVRegister ucvtf(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src,
                        int fbits,
@@ -2706,9 +3774,9 @@ class Simulator : public DecoderVisitor {
                      const LogicVRegister& src);
   LogicVRegister extractnarrow(VectorFormat vform,
                                LogicVRegister dst,
-                               bool dstIsSigned,
+                               bool dst_is_signed,
                                const LogicVRegister& src,
-                               bool srcIsSigned);
+                               bool src_is_signed);
   LogicVRegister xtn(VectorFormat vform,
                      LogicVRegister dst,
                      const LogicVRegister& src);
@@ -2725,7 +3793,7 @@ class Simulator : public DecoderVisitor {
                          LogicVRegister dst,
                          const LogicVRegister& src1,
                          const LogicVRegister& src2,
-                         bool issigned);
+                         bool is_signed);
   LogicVRegister saba(VectorFormat vform,
                       LogicVRegister dst,
                       const LogicVRegister& src1,
@@ -2951,19 +4019,23 @@ class Simulator : public DecoderVisitor {
   template <typename T>
   LogicVRegister fmla(VectorFormat vform,
                       LogicVRegister dst,
+                      const LogicVRegister& srca,
                       const LogicVRegister& src1,
                       const LogicVRegister& src2);
   LogicVRegister fmla(VectorFormat vform,
                       LogicVRegister dst,
+                      const LogicVRegister& srca,
                       const LogicVRegister& src1,
                       const LogicVRegister& src2);
   template <typename T>
   LogicVRegister fmls(VectorFormat vform,
                       LogicVRegister dst,
+                      const LogicVRegister& srca,
                       const LogicVRegister& src1,
                       const LogicVRegister& src2);
   LogicVRegister fmls(VectorFormat vform,
                       LogicVRegister dst,
+                      const LogicVRegister& srca,
                       const LogicVRegister& src1,
                       const LogicVRegister& src2);
   LogicVRegister fnmul(VectorFormat vform,
@@ -3023,6 +4095,31 @@ class Simulator : public DecoderVisitor {
   LogicVRegister frecpx(VectorFormat vform,
                         LogicVRegister dst,
                         const LogicVRegister& src);
+  LogicVRegister ftsmul(VectorFormat vform,
+                        LogicVRegister dst,
+                        const LogicVRegister& src1,
+                        const LogicVRegister& src2);
+  LogicVRegister ftssel(VectorFormat vform,
+                        LogicVRegister dst,
+                        const LogicVRegister& src1,
+                        const LogicVRegister& src2);
+  LogicVRegister ftmad(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicVRegister& src1,
+                       const LogicVRegister& src2,
+                       unsigned index);
+  LogicVRegister fexpa(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicVRegister& src);
+  template <typename T>
+  LogicVRegister fscale(VectorFormat vform,
+                        LogicVRegister dst,
+                        const LogicVRegister& src1,
+                        const LogicVRegister& src2);
+  LogicVRegister fscale(VectorFormat vform,
+                        LogicVRegister dst,
+                        const LogicVRegister& src1,
+                        const LogicVRegister& src2);
   template <typename T>
   LogicVRegister fabs_(VectorFormat vform,
                        LogicVRegister dst,
@@ -3034,19 +4131,40 @@ class Simulator : public DecoderVisitor {
                       LogicVRegister dst,
                       const LogicVRegister& src1,
                       const LogicVRegister& src2);
-
   LogicVRegister frint(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src,
                        FPRounding rounding_mode,
                        bool inexact_exception = false,
                        FrintMode frint_mode = kFrintToInteger);
+  LogicVRegister fcvt(VectorFormat vform,
+                      unsigned dst_data_size_in_bits,
+                      unsigned src_data_size_in_bits,
+                      LogicVRegister dst,
+                      const LogicPRegister& pg,
+                      const LogicVRegister& src);
+  LogicVRegister fcvts(VectorFormat vform,
+                       unsigned dst_data_size_in_bits,
+                       unsigned src_data_size_in_bits,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src,
+                       FPRounding round,
+                       int fbits = 0);
   LogicVRegister fcvts(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src,
                        FPRounding rounding_mode,
                        int fbits = 0);
   LogicVRegister fcvtu(VectorFormat vform,
+                       unsigned dst_data_size_in_bits,
+                       unsigned src_data_size_in_bits,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src,
+                       FPRounding round,
+                       int fbits = 0);
+  LogicVRegister fcvtu(VectorFormat vform,
                        LogicVRegister dst,
                        const LogicVRegister& src,
                        FPRounding rounding_mode,
@@ -3086,16 +4204,78 @@ class Simulator : public DecoderVisitor {
                         LogicVRegister dst,
                         const LogicVRegister& src);
 
+  LogicPRegister pfalse(LogicPRegister dst);
+  LogicPRegister pfirst(LogicPRegister dst,
+                        const LogicPRegister& pg,
+                        const LogicPRegister& src);
+  LogicPRegister ptrue(VectorFormat vform, LogicPRegister dst, int pattern);
+  LogicPRegister pnext(VectorFormat vform,
+                       LogicPRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicPRegister& src);
+
+  LogicVRegister asrd(VectorFormat vform,
+                      LogicVRegister dst,
+                      const LogicVRegister& src1,
+                      int shift);
+
+  LogicVRegister andv(VectorFormat vform,
+                      LogicVRegister dst,
+                      const LogicPRegister& pg,
+                      const LogicVRegister& src);
+  LogicVRegister eorv(VectorFormat vform,
+                      LogicVRegister dst,
+                      const LogicPRegister& pg,
+                      const LogicVRegister& src);
+  LogicVRegister orv(VectorFormat vform,
+                     LogicVRegister dst,
+                     const LogicPRegister& pg,
+                     const LogicVRegister& src);
+  LogicVRegister saddv(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src);
+  LogicVRegister sminv(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src);
+  LogicVRegister smaxv(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src);
+  LogicVRegister uaddv(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src);
+  LogicVRegister uminv(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src);
+  LogicVRegister umaxv(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicPRegister& pg,
+                       const LogicVRegister& src);
+
   template <typename T>
-  struct TFPMinMaxOp {
+  struct TFPPairOp {
     typedef T (Simulator::*type)(T a, T b);
   };
 
   template <typename T>
-  LogicVRegister fminmaxv(VectorFormat vform,
-                          LogicVRegister dst,
-                          const LogicVRegister& src,
-                          typename TFPMinMaxOp<T>::type Op);
+  LogicVRegister FPPairedAcrossHelper(VectorFormat vform,
+                                      LogicVRegister dst,
+                                      const LogicVRegister& src,
+                                      typename TFPPairOp<T>::type fn,
+                                      uint64_t inactive_value);
+
+  LogicVRegister FPPairedAcrossHelper(
+      VectorFormat vform,
+      LogicVRegister dst,
+      const LogicVRegister& src,
+      typename TFPPairOp<vixl::internal::SimFloat16>::type fn16,
+      typename TFPPairOp<float>::type fn32,
+      typename TFPPairOp<double>::type fn64,
+      uint64_t inactive_value);
 
   LogicVRegister fminv(VectorFormat vform,
                        LogicVRegister dst,
@@ -3109,6 +4289,9 @@ class Simulator : public DecoderVisitor {
   LogicVRegister fmaxnmv(VectorFormat vform,
                          LogicVRegister dst,
                          const LogicVRegister& src);
+  LogicVRegister faddv(VectorFormat vform,
+                       LogicVRegister dst,
+                       const LogicVRegister& src);
 
   static const uint32_t CRC32_POLY = 0x04C11DB7;
   static const uint32_t CRC32C_POLY = 0x1EDC6F41;
@@ -3209,6 +4392,129 @@ class Simulator : public DecoderVisitor {
   void DoSaveCPUFeatures(const Instruction* instr);
   void DoRestoreCPUFeatures(const Instruction* instr);
 
+  // General arithmetic helpers ----------------------------
+
+  // Add `delta` to the accumulator (`acc`), optionally saturate, then zero- or
+  // sign-extend. Initial `acc` bits outside `n` are ignored, but the delta must
+  // be a valid int<n>_t.
+  uint64_t IncDecN(uint64_t acc,
+                   int64_t delta,
+                   unsigned n,
+                   bool is_saturating = false,
+                   bool is_signed = false);
+
+  // SVE helpers -------------------------------------------
+  LogicVRegister SVEBitwiseLogicalUnpredicatedHelper(LogicalOp op,
+                                                     VectorFormat vform,
+                                                     LogicVRegister zd,
+                                                     const LogicVRegister& zn,
+                                                     const LogicVRegister& zm);
+
+  LogicPRegister SVEPredicateLogicalHelper(SVEPredicateLogicalOp op,
+                                           LogicPRegister Pd,
+                                           const LogicPRegister& pn,
+                                           const LogicPRegister& pm);
+
+  LogicVRegister SVEBitwiseImmHelper(SVEBitwiseLogicalWithImm_UnpredicatedOp op,
+                                     VectorFormat vform,
+                                     LogicVRegister zd,
+                                     uint64_t imm);
+  enum UnpackType { kHiHalf, kLoHalf };
+  enum ExtendType { kSignedExtend, kUnsignedExtend };
+  LogicVRegister unpk(VectorFormat vform,
+                      LogicVRegister zd,
+                      const LogicVRegister& zn,
+                      UnpackType unpack_type,
+                      ExtendType extend_type);
+
+  LogicPRegister SVEIntCompareVectorsHelper(Condition cc,
+                                            VectorFormat vform,
+                                            LogicPRegister dst,
+                                            const LogicPRegister& mask,
+                                            const LogicVRegister& src1,
+                                            const LogicVRegister& src2,
+                                            bool is_wide_elements = false,
+                                            FlagsUpdate flags = SetFlags);
+
+  void SVEGatherLoadScalarPlusVectorHelper(const Instruction* instr,
+                                           VectorFormat vform,
+                                           SVEOffsetModifier mod);
+
+  // Store each active zt<i>[lane] to `addr.GetElementAddress(lane, ...)`.
+  //
+  // `zt_code` specifies the code of the first register (zt). Each additional
+  // register (up to `reg_count`) is `(zt_code + i) % 32`.
+  //
+  // This helper calls LogZWrite in the proper way, according to `addr`.
+  void SVEStructuredStoreHelper(VectorFormat vform,
+                                const LogicPRegister& pg,
+                                unsigned zt_code,
+                                const LogicSVEAddressVector& addr);
+  // Load each active zt<i>[lane] from `addr.GetElementAddress(lane, ...)`.
+  void SVEStructuredLoadHelper(VectorFormat vform,
+                               const LogicPRegister& pg,
+                               unsigned zt_code,
+                               const LogicSVEAddressVector& addr,
+                               bool is_signed = false);
+
+  enum SVEFaultTolerantLoadType {
+    // - Elements active in both FFR and pg are accessed as usual. If the access
+    //   fails, the corresponding lane and all subsequent lanes are filled with
+    //   an unpredictable value, and made inactive in FFR.
+    //
+    // - Elements active in FFR but not pg are set to zero.
+    //
+    // - Elements that are not active in FFR are filled with an unpredictable
+    //   value, regardless of pg.
+    kSVENonFaultLoad,
+
+    // If type == kSVEFirstFaultLoad, the behaviour is the same, except that the
+    // first active element is always accessed, regardless of FFR, and will
+    // generate a real fault if it is inaccessible. If the lane is not active in
+    // FFR, the actual value loaded into the result is still unpredictable.
+    kSVEFirstFaultLoad
+  };
+
+  // Load with first-faulting or non-faulting load semantics, respecting and
+  // updating FFR.
+  void SVEFaultTolerantLoadHelper(VectorFormat vform,
+                                  const LogicPRegister& pg,
+                                  unsigned zt_code,
+                                  const LogicSVEAddressVector& addr,
+                                  SVEFaultTolerantLoadType type,
+                                  bool is_signed);
+
+  LogicVRegister SVEBitwiseShiftHelper(Shift shift_op,
+                                       VectorFormat vform,
+                                       LogicVRegister dst,
+                                       const LogicVRegister& src1,
+                                       const LogicVRegister& src2,
+                                       bool is_wide_elements);
+
+  template <typename T>
+  LogicVRegister FTMaddHelper(VectorFormat vform,
+                              LogicVRegister dst,
+                              const LogicVRegister& src1,
+                              const LogicVRegister& src2,
+                              uint64_t coeff_pos,
+                              uint64_t coeff_neg);
+
+  // Return the first or last active lane, or -1 if none are active.
+  int GetFirstActive(VectorFormat vform, const LogicPRegister& pg) const;
+  int GetLastActive(VectorFormat vform, const LogicPRegister& pg) const;
+
+  int CountActiveLanes(VectorFormat vform, const LogicPRegister& pg) const;
+
+  // Count active and true lanes in `pn`.
+  int CountActiveAndTrueLanes(VectorFormat vform,
+                              const LogicPRegister& pg,
+                              const LogicPRegister& pn) const;
+
+  // Count the number of lanes referred to by `pattern`, given the vector
+  // length. If `pattern` is not a recognised SVEPredicateConstraint, this
+  // returns zero.
+  int GetPredicateConstraintLaneCount(VectorFormat vform, int pattern) const;
+
   // Simulate a runtime call.
   void DoRuntimeCall(const Instruction* instr);
 
@@ -3222,15 +4528,21 @@ class Simulator : public DecoderVisitor {
   FILE* stream_;
   PrintDisassembler* print_disasm_;
 
-  // Instruction statistics instrumentation.
-  Instrument* instrumentation_;
-
   // General purpose registers. Register 31 is the stack pointer.
   SimRegister registers_[kNumberOfRegisters];
 
   // Vector registers
   SimVRegister vregisters_[kNumberOfVRegisters];
 
+  // SVE predicate registers.
+  SimPRegister pregisters_[kNumberOfPRegisters];
+
+  // SVE first-fault register.
+  SimFFRRegister ffr_register_;
+
+  // A pseudo SVE predicate register with all bits set to true.
+  SimPRegister pregister_all_true_;
+
   // Program Status Register.
   // bits[31, 27]: Condition flags N, Z, C, and V.
   //               (Negative, Zero, Carry, Overflow)
@@ -3263,12 +4575,11 @@ class Simulator : public DecoderVisitor {
 
   static const uint32_t kConditionFlagsMask = 0xf0000000;
 
-  // Stack
-  byte* stack_;
-  static const int stack_protection_size_ = 256;
-  // 2 KB stack.
-  static const int stack_size_ = 2 * 1024 + 2 * stack_protection_size_;
-  byte* stack_limit_;
+  Memory memory_;
+
+  static const size_t kDefaultStackGuardStartSize = 0;
+  static const size_t kDefaultStackGuardEndSize = 4 * 1024;
+  static const size_t kDefaultStackUsableSize = 8 * 1024;
 
   Decoder* decoder_;
   // Indicates if the pc has been modified by the instruction and should not be
@@ -3276,6 +4587,10 @@ class Simulator : public DecoderVisitor {
   bool pc_modified_;
   const Instruction* pc_;
 
+  // If non-NULL, the last instruction was a movprfx, and validity needs to be
+  // checked.
+  Instruction const* movprfx_;
+
   // Branch type register, used for branch target identification.
   BType btype_;
 
@@ -3289,10 +4604,13 @@ class Simulator : public DecoderVisitor {
 
   static const char* xreg_names[];
   static const char* wreg_names[];
+  static const char* breg_names[];
   static const char* hreg_names[];
   static const char* sreg_names[];
   static const char* dreg_names[];
   static const char* vreg_names[];
+  static const char* zreg_names[];
+  static const char* preg_names[];
 
  private:
   static const PACKey kPACKeyIA;
@@ -3301,6 +4619,13 @@ class Simulator : public DecoderVisitor {
   static const PACKey kPACKeyDB;
   static const PACKey kPACKeyGA;
 
+  bool CanReadMemory(uintptr_t address, size_t size);
+
+  // CanReadMemory needs placeholder file descriptors, so we use a pipe. We can
+  // save some system call overhead by opening them on construction, rather than
+  // on every call to CanReadMemory.
+  int placeholder_pipe_fd_[2];
+
   template <typename T>
   static T FPDefaultNaN();
 
@@ -3353,14 +4678,24 @@ class Simulator : public DecoderVisitor {
     }
   }
 
+  // Construct a SimVRegister from a SimPRegister, where each byte-sized lane of
+  // the destination is set to all true (0xff) when the corresponding
+  // predicate flag is set, and false (0x00) otherwise.
+  SimVRegister ExpandToSimVRegister(const SimPRegister& preg);
+
+  // Set each predicate flag in pd where the corresponding assigned-sized lane
+  // in vreg is non-zero. Clear the flag, otherwise. This is almost the opposite
+  // operation to ExpandToSimVRegister(), except that any non-zero lane is
+  // interpreted as true.
+  void ExtractFromSimVRegister(VectorFormat vform,
+                               SimPRegister& pd,  // NOLINT(runtime/references)
+                               SimVRegister vreg);
+
   bool coloured_trace_;
 
   // A set of TraceParameters flags.
   int trace_parameters_;
 
-  // Indicates whether the instruction instrumentation is active.
-  bool instruction_stats_;
-
   // Indicates whether the exclusive-access warning has been printed.
   bool print_exclusive_access_warning_;
   void PrintExclusiveAccessWarning();
@@ -3368,8 +4703,14 @@ class Simulator : public DecoderVisitor {
   CPUFeaturesAuditor cpu_features_auditor_;
   std::vector<CPUFeatures> saved_cpu_features_;
 
-  // The simulated state of RNDR and RNDRRS for generating a random number.
-  uint16_t rndr_state_[3];
+  // State for *rand48 functions, used to simulate randomness with repeatable
+  // behaviour (so that tests are deterministic). This is used to simulate RNDR
+  // and RNDRRS, as well as to simulate a source of entropy for architecturally
+  // undefined behaviour.
+  uint16_t rand_state_[3];
+
+  // A configurable size of SVE vector registers.
+  unsigned vector_length_;
 };
 
 #if defined(VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT) && __cplusplus < 201402L
diff --git a/src/aarch64/simulator-constants-aarch64.h b/src/aarch64/simulator-constants-aarch64.h
index 3256f30e..e2389f11 100644
--- a/src/aarch64/simulator-constants-aarch64.h
+++ b/src/aarch64/simulator-constants-aarch64.h
@@ -121,7 +121,7 @@ const unsigned kTraceLength = 3 * kInstructionSize;
 enum TraceParameters {
   LOG_DISASM = 1 << 0,   // Log disassembly.
   LOG_REGS = 1 << 1,     // Log general purpose registers.
-  LOG_VREGS = 1 << 2,    // Log NEON and floating-point registers.
+  LOG_VREGS = 1 << 2,    // Log SVE, NEON and floating-point registers.
   LOG_SYSREGS = 1 << 3,  // Log the flags and system registers.
   LOG_WRITE = 1 << 4,    // Log writes to memory.
   LOG_BRANCH = 1 << 5,   // Log taken branches.
diff --git a/src/code-buffer-vixl.h b/src/code-buffer-vixl.h
index a43c5843..9a1efd44 100644
--- a/src/code-buffer-vixl.h
+++ b/src/code-buffer-vixl.h
@@ -164,8 +164,8 @@ class CodeBuffer {
     *has_grown = is_full;
   }
   void EnsureSpaceFor(size_t amount) {
-    bool dummy;
-    EnsureSpaceFor(amount, &dummy);
+    bool placeholder;
+    EnsureSpaceFor(amount, &placeholder);
   }
 
  private:
diff --git a/src/cpu-features.cc b/src/cpu-features.cc
index ea1e0d3e..08db3f44 100644
--- a/src/cpu-features.cc
+++ b/src/cpu-features.cc
@@ -37,31 +37,9 @@
 
 namespace vixl {
 
-static uint64_t MakeFeatureMask(CPUFeatures::Feature feature) {
-  if (feature == CPUFeatures::kNone) {
-    return 0;
-  } else {
-    // Check that the shift is well-defined, and that the feature is valid.
-    VIXL_STATIC_ASSERT(CPUFeatures::kNumberOfFeatures <=
-                       (sizeof(uint64_t) * 8));
-    VIXL_ASSERT(feature < CPUFeatures::kNumberOfFeatures);
-    return UINT64_C(1) << feature;
-  }
-}
-
-CPUFeatures::CPUFeatures(Feature feature0,
-                         Feature feature1,
-                         Feature feature2,
-                         Feature feature3)
-    : features_(0) {
-  Combine(feature0, feature1, feature2, feature3);
-}
-
 CPUFeatures CPUFeatures::All() {
   CPUFeatures all;
-  // Check that the shift is well-defined.
-  VIXL_STATIC_ASSERT(CPUFeatures::kNumberOfFeatures < (sizeof(uint64_t) * 8));
-  all.features_ = (UINT64_C(1) << kNumberOfFeatures) - 1;
+  all.features_.set();
   return all;
 }
 
@@ -89,74 +67,27 @@ void CPUFeatures::Combine(const CPUFeatures& other) {
   features_ |= other.features_;
 }
 
-void CPUFeatures::Combine(Feature feature0,
-                          Feature feature1,
-                          Feature feature2,
-                          Feature feature3) {
-  features_ |= MakeFeatureMask(feature0);
-  features_ |= MakeFeatureMask(feature1);
-  features_ |= MakeFeatureMask(feature2);
-  features_ |= MakeFeatureMask(feature3);
+void CPUFeatures::Combine(Feature feature) {
+  if (feature != CPUFeatures::kNone) features_.set(feature);
 }
 
 void CPUFeatures::Remove(const CPUFeatures& other) {
   features_ &= ~other.features_;
 }
 
-void CPUFeatures::Remove(Feature feature0,
-                         Feature feature1,
-                         Feature feature2,
-                         Feature feature3) {
-  features_ &= ~MakeFeatureMask(feature0);
-  features_ &= ~MakeFeatureMask(feature1);
-  features_ &= ~MakeFeatureMask(feature2);
-  features_ &= ~MakeFeatureMask(feature3);
-}
-
-CPUFeatures CPUFeatures::With(const CPUFeatures& other) const {
-  CPUFeatures f(*this);
-  f.Combine(other);
-  return f;
-}
-
-CPUFeatures CPUFeatures::With(Feature feature0,
-                              Feature feature1,
-                              Feature feature2,
-                              Feature feature3) const {
-  CPUFeatures f(*this);
-  f.Combine(feature0, feature1, feature2, feature3);
-  return f;
-}
-
-CPUFeatures CPUFeatures::Without(const CPUFeatures& other) const {
-  CPUFeatures f(*this);
-  f.Remove(other);
-  return f;
-}
-
-CPUFeatures CPUFeatures::Without(Feature feature0,
-                                 Feature feature1,
-                                 Feature feature2,
-                                 Feature feature3) const {
-  CPUFeatures f(*this);
-  f.Remove(feature0, feature1, feature2, feature3);
-  return f;
+void CPUFeatures::Remove(Feature feature) {
+  if (feature != CPUFeatures::kNone) features_.reset(feature);
 }
 
 bool CPUFeatures::Has(const CPUFeatures& other) const {
   return (features_ & other.features_) == other.features_;
 }
 
-bool CPUFeatures::Has(Feature feature0,
-                      Feature feature1,
-                      Feature feature2,
-                      Feature feature3) const {
-  uint64_t mask = MakeFeatureMask(feature0) | MakeFeatureMask(feature1) |
-                  MakeFeatureMask(feature2) | MakeFeatureMask(feature3);
-  return (features_ & mask) == mask;
+bool CPUFeatures::Has(Feature feature) const {
+  return (feature == CPUFeatures::kNone) || features_[feature];
 }
 
-size_t CPUFeatures::Count() const { return CountSetBits(features_); }
+size_t CPUFeatures::Count() const { return features_.count(); }
 
 std::ostream& operator<<(std::ostream& os, CPUFeatures::Feature feature) {
   // clang-format off
@@ -177,12 +108,9 @@ VIXL_CPU_FEATURE_LIST(VIXL_FORMAT_FEATURE)
 }
 
 CPUFeatures::const_iterator CPUFeatures::begin() const {
-  if (features_ == 0) return const_iterator(this, kNone);
-
-  int feature_number = CountTrailingZeros(features_);
-  vixl::CPUFeatures::Feature feature =
-      static_cast<CPUFeatures::Feature>(feature_number);
-  return const_iterator(this, feature);
+  // For iterators in general, it's undefined to increment `end()`, but here we
+  // control the implementation and it is safe to do this.
+  return ++end();
 }
 
 CPUFeatures::const_iterator CPUFeatures::end() const {
@@ -190,11 +118,11 @@ CPUFeatures::const_iterator CPUFeatures::end() const {
 }
 
 std::ostream& operator<<(std::ostream& os, const CPUFeatures& features) {
-  CPUFeatures::const_iterator it = features.begin();
-  while (it != features.end()) {
-    os << *it;
-    ++it;
-    if (it != features.end()) os << ", ";
+  bool need_separator = false;
+  for (CPUFeatures::Feature feature : features) {
+    if (need_separator) os << ", ";
+    need_separator = true;
+    os << feature;
   }
   return os;
 }
@@ -205,7 +133,7 @@ bool CPUFeaturesConstIterator::operator==(
   return (cpu_features_ == other.cpu_features_) && (feature_ == other.feature_);
 }
 
-CPUFeatures::Feature CPUFeaturesConstIterator::operator++() {  // Prefix
+CPUFeaturesConstIterator& CPUFeaturesConstIterator::operator++() {  // Prefix
   VIXL_ASSERT(IsValid());
   do {
     // Find the next feature. The order is unspecified.
@@ -219,11 +147,11 @@ CPUFeatures::Feature CPUFeaturesConstIterator::operator++() {  // Prefix
     // cpu_features_->Has(kNone) is always true, so this will terminate even if
     // the features list is empty.
   } while (!cpu_features_->Has(feature_));
-  return feature_;
+  return *this;
 }
 
-CPUFeatures::Feature CPUFeaturesConstIterator::operator++(int) {  // Postfix
-  CPUFeatures::Feature result = feature_;
+CPUFeaturesConstIterator CPUFeaturesConstIterator::operator++(int) {  // Postfix
+  CPUFeaturesConstIterator result = *this;
   ++(*this);
   return result;
 }
diff --git a/src/cpu-features.h b/src/cpu-features.h
index 50ddc267..1b0f2c24 100644
--- a/src/cpu-features.h
+++ b/src/cpu-features.h
@@ -27,6 +27,7 @@
 #ifndef VIXL_CPU_FEATURES_H
 #define VIXL_CPU_FEATURES_H
 
+#include <bitset>
 #include <ostream>
 
 #include "globals-vixl.h"
@@ -34,16 +35,65 @@
 namespace vixl {
 
 
+// VIXL aims to handle and detect all architectural features that are likely to
+// influence code-generation decisions at EL0 (user-space).
+//
+// - There may be multiple VIXL feature flags for a given architectural
+//   extension. This occurs where the extension allow components to be
+//   implemented independently, or where kernel support is needed, and is likely
+//   to be fragmented.
+//
+//   For example, Pointer Authentication (kPAuth*) has a separate feature flag
+//   for access to PACGA, and to indicate that the QARMA algorithm is
+//   implemented.
+//
+// - Conversely, some extensions have configuration options that do not affect
+//   EL0, so these are presented as a single VIXL feature.
+//
+//   For example, the RAS extension (kRAS) has several variants, but the only
+//   feature relevant to VIXL is the addition of the ESB instruction so we only
+//   need a single flag.
+//
+// - VIXL offers separate flags for separate features even if they're
+//   architecturally linked.
+//
+//   For example, the architecture requires kFPHalf and kNEONHalf to be equal,
+//   but they have separate hardware ID register fields so VIXL presents them as
+//   separate features.
+//
+// - VIXL can detect every feature for which it can generate code.
+//
+// - VIXL can detect some features for which it cannot generate code.
+//
+// The CPUFeatures::Feature enum — derived from the macro list below — is
+// frequently extended. New features may be added to the list at any point, and
+// no assumptions should be made about the numerical values assigned to each
+// enum constant. The symbolic names can be considered to be stable.
+//
+// The debug descriptions are used only for debug output. The 'cpuinfo' strings
+// are informative; VIXL does not use /proc/cpuinfo for feature detection.
+
 // clang-format off
 #define VIXL_CPU_FEATURE_LIST(V)                                               \
   /* If set, the OS traps and emulates MRS accesses to relevant (EL1) ID_*  */ \
   /* registers, so that the detailed feature registers can be read          */ \
   /* directly.                                                              */ \
+                                                                               \
+  /* Constant name        Debug description         Linux 'cpuinfo' string. */ \
   V(kIDRegisterEmulation, "ID register emulation",  "cpuid")                   \
                                                                                \
   V(kFP,                  "FP",                     "fp")                      \
   V(kNEON,                "NEON",                   "asimd")                   \
   V(kCRC32,               "CRC32",                  "crc32")                   \
+  V(kDGH,                 "DGH",                    "dgh")                     \
+  /* Speculation control features.                                          */ \
+  V(kCSV2,                "CSV2",                   NULL)                      \
+  V(kSCXTNUM,             "SCXTNUM",                NULL)                      \
+  V(kCSV3,                "CSV3",                   NULL)                      \
+  V(kSB,                  "SB",                     "sb")                      \
+  V(kSPECRES,             "SPECRES",                NULL)                      \
+  V(kSSBS,                "SSBS",                   NULL)                      \
+  V(kSSBSControl,         "SSBS (PSTATE control)",  "ssbs")                    \
   /* Cryptographic support instructions.                                    */ \
   V(kAES,                 "AES",                    "aes")                     \
   V(kSHA1,                "SHA1",                   "sha1")                    \
@@ -58,28 +108,36 @@ namespace vixl {
   V(kRDM,                 "RDM",                    "asimdrdm")                \
   /* Scalable Vector Extension.                                             */ \
   V(kSVE,                 "SVE",                    "sve")                     \
+  V(kSVEF64MM,            "SVE F64MM",              "svef64mm")                \
+  V(kSVEF32MM,            "SVE F32MM",              "svef32mm")                \
+  V(kSVEI8MM,             "SVE I8MM",               "svei8imm")                \
+  V(kSVEBF16,             "SVE BFloat16",           "svebf16")                 \
   /* SDOT and UDOT support (in NEON).                                       */ \
   V(kDotProduct,          "DotProduct",             "asimddp")                 \
+  /* Int8 matrix multiplication (in NEON).                                  */ \
+  V(kI8MM,                "NEON I8MM",              "i8mm")                    \
   /* Half-precision (FP16) support for FP and NEON, respectively.           */ \
   V(kFPHalf,              "FPHalf",                 "fphp")                    \
   V(kNEONHalf,            "NEONHalf",               "asimdhp")                 \
+  /* BFloat16 support (in both FP and NEON.)                                */ \
+  V(kBF16,                "FP/NEON BFloat 16",      "bf16")                    \
   /* The RAS extension, including the ESB instruction.                      */ \
   V(kRAS,                 "RAS",                    NULL)                      \
   /* Data cache clean to the point of persistence: DC CVAP.                 */ \
   V(kDCPoP,               "DCPoP",                  "dcpop")                   \
   /* Data cache clean to the point of deep persistence: DC CVADP.           */ \
-  V(kDCCVADP,             "DCCVADP",                NULL)                      \
+  V(kDCCVADP,             "DCCVADP",                "dcpodp")                  \
   /* Cryptographic support instructions.                                    */ \
   V(kSHA3,                "SHA3",                   "sha3")                    \
   V(kSHA512,              "SHA512",                 "sha512")                  \
   V(kSM3,                 "SM3",                    "sm3")                     \
   V(kSM4,                 "SM4",                    "sm4")                     \
   /* Pointer authentication for addresses.                                  */ \
-  V(kPAuth,               "PAuth",                  NULL)                      \
+  V(kPAuth,               "PAuth",                  "paca")                    \
   /* Pointer authentication for addresses uses QARMA.                       */ \
   V(kPAuthQARMA,          "PAuthQARMA",             NULL)                      \
   /* Generic authentication (using the PACGA instruction).                  */ \
-  V(kPAuthGeneric,        "PAuthGeneric",           NULL)                      \
+  V(kPAuthGeneric,        "PAuthGeneric",           "pacg")                    \
   /* Generic authentication uses QARMA.                                     */ \
   V(kPAuthGenericQARMA,   "PAuthGenericQARMA",      NULL)                      \
   /* JavaScript-style FP -> integer conversion instruction: FJCVTZS.        */ \
@@ -98,13 +156,21 @@ namespace vixl {
   /* Data-independent timing (for selected instructions).                   */ \
   V(kDIT,                 "DIT",                    "dit")                     \
   /* Branch target identification.                                          */ \
-  V(kBTI,                 "BTI",                    NULL)                      \
+  V(kBTI,                 "BTI",                    "bti")                     \
   /* Flag manipulation instructions: {AX,XA}FLAG                            */ \
-  V(kAXFlag,              "AXFlag",                 NULL)                      \
+  V(kAXFlag,              "AXFlag",                 "flagm2")                  \
   /* Random number generation extension,                                    */ \
-  V(kRNG,                 "RNG",                    NULL)                      \
+  V(kRNG,                 "RNG",                    "rng")                     \
   /* Floating-point round to {32,64}-bit integer.                           */ \
-  V(kFrintToFixedSizedInt,"Frint (bounded)",        NULL)
+  V(kFrintToFixedSizedInt,"Frint (bounded)",        "frint")                   \
+  /* Memory Tagging Extension.                                              */ \
+  V(kMTEInstructions,     "MTE (EL0 instructions)", NULL)                      \
+  V(kMTE,                 "MTE",                    NULL)                      \
+  /* PAuth extensions.                                                      */ \
+  V(kPAuthEnhancedPAC,    "PAuth EnhancedPAC",      NULL)                      \
+  V(kPAuthEnhancedPAC2,   "PAuth EnhancedPAC2",     NULL)                      \
+  V(kPAuthFPAC,           "PAuth FPAC",             NULL)                      \
+  V(kPAuthFPACCombined,   "PAuth FPACCombined",     NULL)
 // clang-format on
 
 
@@ -197,13 +263,13 @@ class CPUFeatures {
   // clang-format on
 
   // By default, construct with no features enabled.
-  CPUFeatures() : features_(0) {}
+  CPUFeatures() : features_{} {}
 
   // Construct with some features already enabled.
-  CPUFeatures(Feature feature0,
-              Feature feature1 = kNone,
-              Feature feature2 = kNone,
-              Feature feature3 = kNone);
+  template <typename T, typename... U>
+  CPUFeatures(T first, U... others) : features_{} {
+    Combine(first, others...);
+  }
 
   // Construct with all features enabled. This can be used to disable feature
   // checking: `Has(...)` returns true regardless of the argument.
@@ -236,41 +302,59 @@ class CPUFeatures {
   // exist in this set are left unchanged.
   void Combine(const CPUFeatures& other);
 
-  // Combine specific features into this set. Features that already exist in
-  // this set are left unchanged.
-  void Combine(Feature feature0,
-               Feature feature1 = kNone,
-               Feature feature2 = kNone,
-               Feature feature3 = kNone);
+  // Combine a specific feature into this set. If it already exists in the set,
+  // the set is left unchanged.
+  void Combine(Feature feature);
+
+  // Combine multiple features (or feature sets) into this set.
+  template <typename T, typename... U>
+  void Combine(T first, U... others) {
+    Combine(first);
+    Combine(others...);
+  }
 
   // Remove features in another CPUFeatures object from this one.
   void Remove(const CPUFeatures& other);
 
-  // Remove specific features from this set.
-  void Remove(Feature feature0,
-              Feature feature1 = kNone,
-              Feature feature2 = kNone,
-              Feature feature3 = kNone);
-
-  // Chaining helpers for convenient construction.
-  CPUFeatures With(const CPUFeatures& other) const;
-  CPUFeatures With(Feature feature0,
-                   Feature feature1 = kNone,
-                   Feature feature2 = kNone,
-                   Feature feature3 = kNone) const;
-  CPUFeatures Without(const CPUFeatures& other) const;
-  CPUFeatures Without(Feature feature0,
-                      Feature feature1 = kNone,
-                      Feature feature2 = kNone,
-                      Feature feature3 = kNone) const;
-
-  // Query features.
-  // Note that an empty query (like `Has(kNone)`) always returns true.
+  // Remove a specific feature from this set. This has no effect if the feature
+  // doesn't exist in the set.
+  void Remove(Feature feature0);
+
+  // Remove multiple features (or feature sets) from this set.
+  template <typename T, typename... U>
+  void Remove(T first, U... others) {
+    Remove(first);
+    Remove(others...);
+  }
+
+  // Chaining helpers for convenient construction by combining other CPUFeatures
+  // or individual Features.
+  template <typename... T>
+  CPUFeatures With(T... others) const {
+    CPUFeatures f(*this);
+    f.Combine(others...);
+    return f;
+  }
+
+  template <typename... T>
+  CPUFeatures Without(T... others) const {
+    CPUFeatures f(*this);
+    f.Remove(others...);
+    return f;
+  }
+
+  // Test whether the `other` feature set is equal to or a subset of this one.
   bool Has(const CPUFeatures& other) const;
-  bool Has(Feature feature0,
-           Feature feature1 = kNone,
-           Feature feature2 = kNone,
-           Feature feature3 = kNone) const;
+
+  // Test whether a single feature exists in this set.
+  // Note that `Has(kNone)` always returns true.
+  bool Has(Feature feature) const;
+
+  // Test whether all of the specified features exist in this set.
+  template <typename T, typename... U>
+  bool Has(T first, U... others) const {
+    return Has(first) && Has(others...);
+  }
 
   // Return the number of enabled features.
   size_t Count() const;
@@ -288,9 +372,8 @@ class CPUFeatures {
   const_iterator end() const;
 
  private:
-  // Each bit represents a feature. This field will be replaced as needed if
-  // features are added.
-  uint64_t features_;
+  // Each bit represents a feature. This set will be extended as needed.
+  std::bitset<kNumberOfFeatures> features_;
 
   friend std::ostream& operator<<(std::ostream& os,
                                   const vixl::CPUFeatures& features);
@@ -313,8 +396,8 @@ class CPUFeaturesConstIterator {
   bool operator!=(const CPUFeaturesConstIterator& other) const {
     return !(*this == other);
   }
-  CPUFeatures::Feature operator++();
-  CPUFeatures::Feature operator++(int);
+  CPUFeaturesConstIterator& operator++();
+  CPUFeaturesConstIterator operator++(int);
 
   CPUFeatures::Feature operator*() const {
     VIXL_ASSERT(IsValid());
@@ -359,21 +442,17 @@ class CPUFeaturesScope {
   // Start a CPUFeaturesScope on any object that implements
   // `CPUFeatures* GetCPUFeatures()`.
   template <typename T>
-  explicit CPUFeaturesScope(T* cpu_features_wrapper,
-                            CPUFeatures::Feature feature0 = CPUFeatures::kNone,
-                            CPUFeatures::Feature feature1 = CPUFeatures::kNone,
-                            CPUFeatures::Feature feature2 = CPUFeatures::kNone,
-                            CPUFeatures::Feature feature3 = CPUFeatures::kNone)
+  explicit CPUFeaturesScope(T* cpu_features_wrapper)
       : cpu_features_(cpu_features_wrapper->GetCPUFeatures()),
-        old_features_(*cpu_features_) {
-    cpu_features_->Combine(feature0, feature1, feature2, feature3);
-  }
+        old_features_(*cpu_features_) {}
 
-  template <typename T>
-  CPUFeaturesScope(T* cpu_features_wrapper, const CPUFeatures& other)
+  // Start a CPUFeaturesScope on any object that implements
+  // `CPUFeatures* GetCPUFeatures()`, with the specified features enabled.
+  template <typename T, typename U, typename... V>
+  CPUFeaturesScope(T* cpu_features_wrapper, U first, V... features)
       : cpu_features_(cpu_features_wrapper->GetCPUFeatures()),
         old_features_(*cpu_features_) {
-    cpu_features_->Combine(other);
+    cpu_features_->Combine(first, features...);
   }
 
   ~CPUFeaturesScope() { *cpu_features_ = old_features_; }
diff --git a/src/globals-vixl.h b/src/globals-vixl.h
index 640b4b9b..4dc8c024 100644
--- a/src/globals-vixl.h
+++ b/src/globals-vixl.h
@@ -27,6 +27,10 @@
 #ifndef VIXL_GLOBALS_H
 #define VIXL_GLOBALS_H
 
+#if __cplusplus < 201402L
+#error VIXL requires C++14
+#endif
+
 // Get standard C99 macros for integer types.
 #ifndef __STDC_CONSTANT_MACROS
 #define __STDC_CONSTANT_MACROS
@@ -66,7 +70,8 @@ typedef uint8_t byte;
 const int KBytes = 1024;
 const int MBytes = 1024 * KBytes;
 
-const int kBitsPerByte = 8;
+const int kBitsPerByteLog2 = 3;
+const int kBitsPerByte = 1 << kBitsPerByteLog2;
 
 template <int SizeInBits>
 struct Unsigned;
@@ -223,8 +228,11 @@ inline void USE(const T1&, const T2&, const T3&, const T4&) {}
 
 #if __cplusplus >= 201103L
 #define VIXL_OVERRIDE override
+#define VIXL_CONSTEXPR constexpr
+#define VIXL_HAS_CONSTEXPR 1
 #else
 #define VIXL_OVERRIDE
+#define VIXL_CONSTEXPR
 #endif
 
 // With VIXL_NEGATIVE_TESTING on, VIXL_ASSERT and VIXL_CHECK will throw
diff --git a/src/invalset-vixl.h b/src/invalset-vixl.h
index fbfb6a01..8bd6035e 100644
--- a/src/invalset-vixl.h
+++ b/src/invalset-vixl.h
@@ -842,9 +842,7 @@ InvalSetIterator<S>::InvalSetIterator(const InvalSetIterator<S>& other)
 #if __cplusplus >= 201103L
 template <class S>
 InvalSetIterator<S>::InvalSetIterator(InvalSetIterator<S>&& other) noexcept
-    : using_vector_(false),
-      index_(0),
-      inval_set_(NULL) {
+    : using_vector_(false), index_(0), inval_set_(NULL) {
   swap(*this, other);
 }
 #endif
diff --git a/src/pool-manager-impl.h b/src/pool-manager-impl.h
index 66ecd6a4..a1bcaaad 100644
--- a/src/pool-manager-impl.h
+++ b/src/pool-manager-impl.h
@@ -264,14 +264,14 @@ bool PoolManager<T>::MustEmit(T pc,
     if (checkpoint < temp.min_location_) return true;
   }
 
-  bool tempNotPlacedYet = true;
+  bool temp_not_placed_yet = true;
   for (int i = static_cast<int>(objects_.size()) - 1; i >= 0; --i) {
     const PoolObject<T>& current = objects_[i];
-    if (tempNotPlacedYet && PoolObjectLessThan(current, temp)) {
+    if (temp_not_placed_yet && PoolObjectLessThan(current, temp)) {
       checkpoint = UpdateCheckpointForObject(checkpoint, &temp);
       if (checkpoint < temp.min_location_) return true;
       if (CheckFuturePC(pc, checkpoint)) return true;
-      tempNotPlacedYet = false;
+      temp_not_placed_yet = false;
     }
     if (current.label_base_ == label_base) continue;
     checkpoint = UpdateCheckpointForObject(checkpoint, &current);
@@ -279,7 +279,7 @@ bool PoolManager<T>::MustEmit(T pc,
     if (CheckFuturePC(pc, checkpoint)) return true;
   }
   // temp is the object with the smallest max_location_.
-  if (tempNotPlacedYet) {
+  if (temp_not_placed_yet) {
     checkpoint = UpdateCheckpointForObject(checkpoint, &temp);
     if (checkpoint < temp.min_location_) return true;
   }
@@ -497,7 +497,7 @@ PoolManager<T>::~PoolManager<T>() VIXL_NEGATIVE_TESTING_ALLOW_EXCEPTION {
   }
 #endif
   // Delete objects the pool manager owns.
-  for (typename std::vector<LocationBase<T> *>::iterator
+  for (typename std::vector<LocationBase<T>*>::iterator
            iter = delete_on_destruction_.begin(),
            end = delete_on_destruction_.end();
        iter != end;
diff --git a/src/utils-vixl.h b/src/utils-vixl.h
index c9287e40..0ae6dfc0 100644
--- a/src/utils-vixl.h
+++ b/src/utils-vixl.h
@@ -67,7 +67,7 @@ namespace vixl {
 #endif
 
 template <typename T, size_t n>
-size_t ArrayLength(const T (&)[n]) {
+constexpr size_t ArrayLength(const T (&)[n]) {
   return n;
 }
 
@@ -77,25 +77,30 @@ inline uint64_t GetUintMask(unsigned bits) {
   return base - 1;
 }
 
+inline uint64_t GetSignMask(unsigned bits) {
+  VIXL_ASSERT(bits <= 64);
+  return UINT64_C(1) << (bits - 1);
+}
+
 // Check number width.
 // TODO: Refactor these using templates.
 inline bool IsIntN(unsigned n, uint32_t x) {
-  VIXL_ASSERT((0 < n) && (n < 32));
-  uint32_t limit = UINT32_C(1) << (n - 1);
-  return x < limit;
+  VIXL_ASSERT((0 < n) && (n <= 32));
+  return x <= static_cast<uint32_t>(INT32_MAX >> (32 - n));
 }
 inline bool IsIntN(unsigned n, int32_t x) {
-  VIXL_ASSERT((0 < n) && (n < 32));
+  VIXL_ASSERT((0 < n) && (n <= 32));
+  if (n == 32) return true;
   int32_t limit = INT32_C(1) << (n - 1);
   return (-limit <= x) && (x < limit);
 }
 inline bool IsIntN(unsigned n, uint64_t x) {
-  VIXL_ASSERT((0 < n) && (n < 64));
-  uint64_t limit = UINT64_C(1) << (n - 1);
-  return x < limit;
+  VIXL_ASSERT((0 < n) && (n <= 64));
+  return x <= static_cast<uint64_t>(INT64_MAX >> (64 - n));
 }
 inline bool IsIntN(unsigned n, int64_t x) {
-  VIXL_ASSERT((0 < n) && (n < 64));
+  VIXL_ASSERT((0 < n) && (n <= 64));
+  if (n == 64) return true;
   int64_t limit = INT64_C(1) << (n - 1);
   return (-limit <= x) && (x < limit);
 }
@@ -104,7 +109,8 @@ VIXL_DEPRECATED("IsIntN", inline bool is_intn(unsigned n, int64_t x)) {
 }
 
 inline bool IsUintN(unsigned n, uint32_t x) {
-  VIXL_ASSERT((0 < n) && (n < 32));
+  VIXL_ASSERT((0 < n) && (n <= 32));
+  if (n >= 32) return true;
   return !(x >> n);
 }
 inline bool IsUintN(unsigned n, int32_t x) {
@@ -113,7 +119,8 @@ inline bool IsUintN(unsigned n, int32_t x) {
   return !(static_cast<uint32_t>(x) >> n);
 }
 inline bool IsUintN(unsigned n, uint64_t x) {
-  VIXL_ASSERT((0 < n) && (n < 64));
+  VIXL_ASSERT((0 < n) && (n <= 64));
+  if (n >= 64) return true;
   return !(x >> n);
 }
 inline bool IsUintN(unsigned n, int64_t x) {
@@ -189,7 +196,7 @@ inline uint64_t ExtractUnsignedBitfield64(int msb, int lsb, uint64_t x) {
 }
 
 
-inline uint32_t ExtractUnsignedBitfield32(int msb, int lsb, uint32_t x) {
+inline uint32_t ExtractUnsignedBitfield32(int msb, int lsb, uint64_t x) {
   VIXL_ASSERT((static_cast<size_t>(msb) < sizeof(x) * 8) && (lsb >= 0) &&
               (msb >= lsb));
   return TruncateToUint32(ExtractUnsignedBitfield64(msb, lsb, x));
@@ -209,8 +216,7 @@ inline int64_t ExtractSignedBitfield64(int msb, int lsb, uint64_t x) {
   return result;
 }
 
-
-inline int32_t ExtractSignedBitfield32(int msb, int lsb, uint32_t x) {
+inline int32_t ExtractSignedBitfield32(int msb, int lsb, uint64_t x) {
   VIXL_ASSERT((static_cast<size_t>(msb) < sizeof(x) * 8) && (lsb >= 0) &&
               (msb >= lsb));
   uint32_t temp = TruncateToUint32(ExtractSignedBitfield64(msb, lsb, x));
@@ -219,7 +225,6 @@ inline int32_t ExtractSignedBitfield32(int msb, int lsb, uint32_t x) {
   return result;
 }
 
-
 inline uint64_t RotateRight(uint64_t value,
                             unsigned int rotate,
                             unsigned int width) {
@@ -277,6 +282,19 @@ VIXL_DEPRECATED("RawbitsToDouble",
   return RawbitsToDouble(bits);
 }
 
+// Convert unsigned to signed numbers in a well-defined way (using two's
+// complement representations).
+inline int64_t RawbitsToInt64(uint64_t bits) {
+  return (bits >= UINT64_C(0x8000000000000000))
+             ? (-static_cast<int64_t>(-bits - 1) - 1)
+             : static_cast<int64_t>(bits);
+}
+
+inline int32_t RawbitsToInt32(uint32_t bits) {
+  return (bits >= UINT64_C(0x80000000)) ? (-static_cast<int32_t>(-bits - 1) - 1)
+                                        : static_cast<int32_t>(bits);
+}
+
 namespace internal {
 
 // Internal simulation class used solely by the simulator to
@@ -371,6 +389,10 @@ VIXL_DEPRECATED("Float16Classify", inline int float16classify(uint16_t value)) {
 
 bool IsZero(Float16 value);
 
+inline bool IsPositiveZero(double value) {
+  return (value == 0.0) && (copysign(1.0, value) > 0.0);
+}
+
 inline bool IsNaN(float value) { return std::isnan(value); }
 
 inline bool IsNaN(double value) { return std::isnan(value); }
@@ -490,11 +512,11 @@ T ReverseBits(T value) {
 
 
 template <typename T>
-inline T SignExtend(T val, int bitSize) {
-  VIXL_ASSERT(bitSize > 0);
-  T mask = (T(2) << (bitSize - 1)) - T(1);
+inline T SignExtend(T val, int size_in_bits) {
+  VIXL_ASSERT(size_in_bits > 0);
+  T mask = (T(2) << (size_in_bits - 1)) - T(1);
   val &= mask;
-  T sign_bits = -((val >> (bitSize - 1)) << bitSize);
+  T sign_bits = -((val >> (size_in_bits - 1)) << size_in_bits);
   val |= sign_bits;
   return val;
 }
@@ -576,7 +598,7 @@ T AlignUp(T pointer,
   // reinterpret_cast behaviour for other types.
 
   typename Unsigned<sizeof(T)* kBitsPerByte>::type pointer_raw =
-      (typename Unsigned<sizeof(T) * kBitsPerByte>::type)pointer;
+      (typename Unsigned<sizeof(T) * kBitsPerByte>::type) pointer;
   VIXL_STATIC_ASSERT(sizeof(pointer) <= sizeof(pointer_raw));
 
   size_t mask = alignment - 1;
@@ -596,7 +618,7 @@ T AlignDown(T pointer,
   // reinterpret_cast behaviour for other types.
 
   typename Unsigned<sizeof(T)* kBitsPerByte>::type pointer_raw =
-      (typename Unsigned<sizeof(T) * kBitsPerByte>::type)pointer;
+      (typename Unsigned<sizeof(T) * kBitsPerByte>::type) pointer;
   VIXL_STATIC_ASSERT(sizeof(pointer) <= sizeof(pointer_raw));
 
   size_t mask = alignment - 1;
@@ -980,6 +1002,42 @@ Uint64::Uint64(Uint128 data) : data_(data.ToUint64().Get()) {}
 
 Int64 BitCount(Uint32 value);
 
+// The algorithm used is adapted from the one described in section 8.2 of
+// Hacker's Delight, by Henry S. Warren, Jr.
+template <unsigned N, typename T>
+int64_t MultiplyHigh(T u, T v) {
+  uint64_t u0, v0, w0, u1, v1, w1, w2, t;
+  VIXL_STATIC_ASSERT((N == 8) || (N == 16) || (N == 32) || (N == 64));
+  uint64_t sign_mask = UINT64_C(1) << (N - 1);
+  uint64_t sign_ext = 0;
+  unsigned half_bits = N / 2;
+  uint64_t half_mask = GetUintMask(half_bits);
+  if (std::numeric_limits<T>::is_signed) {
+    sign_ext = UINT64_C(0xffffffffffffffff) << half_bits;
+  }
+
+  VIXL_ASSERT(sizeof(u) == sizeof(uint64_t));
+  VIXL_ASSERT(sizeof(u) == sizeof(u0));
+
+  u0 = u & half_mask;
+  u1 = u >> half_bits | (((u & sign_mask) != 0) ? sign_ext : 0);
+  v0 = v & half_mask;
+  v1 = v >> half_bits | (((v & sign_mask) != 0) ? sign_ext : 0);
+
+  w0 = u0 * v0;
+  t = u1 * v0 + (w0 >> half_bits);
+
+  w1 = t & half_mask;
+  w2 = t >> half_bits | (((t & sign_mask) != 0) ? sign_ext : 0);
+  w1 = u0 * v1 + w1;
+  w1 = w1 >> half_bits | (((w1 & sign_mask) != 0) ? sign_ext : 0);
+
+  uint64_t value = u1 * v1 + w2 + w1;
+  int64_t result;
+  memcpy(&result, &value, sizeof(result));
+  return result;
+}
+
 }  // namespace internal
 
 // The default NaN values (for FPCR.DN=1).
@@ -1244,9 +1302,8 @@ inline Float16 FPRoundToFloat16(int64_t sign,
                                 uint64_t mantissa,
                                 FPRounding round_mode) {
   return RawbitsToFloat16(
-      FPRound<uint16_t,
-              kFloat16ExponentBits,
-              kFloat16MantissaBits>(sign, exponent, mantissa, round_mode));
+      FPRound<uint16_t, kFloat16ExponentBits, kFloat16MantissaBits>(
+          sign, exponent, mantissa, round_mode));
 }
 
 
@@ -1282,6 +1339,62 @@ Float16 FPToFloat16(double value,
                     FPRounding round_mode,
                     UseDefaultNaN DN,
                     bool* exception = NULL);
+
+// Like static_cast<T>(value), but with specialisations for the Float16 type.
+template <typename T, typename F>
+T StaticCastFPTo(F value) {
+  return static_cast<T>(value);
+}
+
+template <>
+inline float StaticCastFPTo<float, Float16>(Float16 value) {
+  return FPToFloat(value, kIgnoreDefaultNaN);
+}
+
+template <>
+inline double StaticCastFPTo<double, Float16>(Float16 value) {
+  return FPToDouble(value, kIgnoreDefaultNaN);
+}
+
+template <>
+inline Float16 StaticCastFPTo<Float16, float>(float value) {
+  return FPToFloat16(value, FPTieEven, kIgnoreDefaultNaN);
+}
+
+template <>
+inline Float16 StaticCastFPTo<Float16, double>(double value) {
+  return FPToFloat16(value, FPTieEven, kIgnoreDefaultNaN);
+}
+
+template <typename T>
+uint64_t FPToRawbitsWithSize(unsigned size_in_bits, T value) {
+  switch (size_in_bits) {
+    case 16:
+      return Float16ToRawbits(StaticCastFPTo<Float16>(value));
+    case 32:
+      return FloatToRawbits(StaticCastFPTo<float>(value));
+    case 64:
+      return DoubleToRawbits(StaticCastFPTo<double>(value));
+  }
+  VIXL_UNREACHABLE();
+  return 0;
+}
+
+template <typename T>
+T RawbitsWithSizeToFP(unsigned size_in_bits, uint64_t value) {
+  VIXL_ASSERT(IsUintN(size_in_bits, value));
+  switch (size_in_bits) {
+    case 16:
+      return StaticCastFPTo<T>(RawbitsToFloat16(static_cast<uint16_t>(value)));
+    case 32:
+      return StaticCastFPTo<T>(RawbitsToFloat(static_cast<uint32_t>(value)));
+    case 64:
+      return StaticCastFPTo<T>(RawbitsToDouble(value));
+  }
+  VIXL_UNREACHABLE();
+  return 0;
+}
+
 }  // namespace vixl
 
 #endif  // VIXL_UTILS_H
diff --git a/test/aarch32/test-assembler-aarch32.cc b/test/aarch32/test-assembler-aarch32.cc
index 24096e58..0be51e15 100644
--- a/test/aarch32/test-assembler-aarch32.cc
+++ b/test/aarch32/test-assembler-aarch32.cc
@@ -3192,6 +3192,7 @@ TEST_NOASM(set_isa_empty) {
 }
 
 
+// clang-format off
 TEST_NOASM(set_isa_noop) {
 // It is possible to call a no-op UseA32/T32 or UseInstructionSet even if
 // one or more instructions have been generated.
@@ -3251,6 +3252,7 @@ TEST_NOASM(set_isa_noop) {
   }
 #endif
 }
+// clang-format on
 
 
 TEST(logical_arithmetic_identities) {
diff --git a/test/aarch64/examples/test-examples.cc b/test/aarch64/examples/test-examples.cc
index 24ad3ba8..3cbbe8d1 100644
--- a/test/aarch64/examples/test-examples.cc
+++ b/test/aarch64/examples/test-examples.cc
@@ -177,13 +177,7 @@ uint32_t SumArrayC(uint8_t* array, uint32_t size) {
                  TRACE_ENABLE);                                          \
     }                                                                    \
   }                                                                      \
-  if (Test::instruction_stats()) {                                       \
-    masm.EnableInstrumentation();                                        \
-  }                                                                      \
   masm.Blr(test_function_reg);                                           \
-  if (Test::instruction_stats()) {                                       \
-    masm.DisableInstrumentation();                                       \
-  }                                                                      \
   masm.Trace(LOG_ALL, TRACE_DISABLE);                                    \
   regs.Dump(&masm);                                                      \
   masm.Mov(lr, reinterpret_cast<uint64_t>(Simulator::kEndOfSimAddress)); \
@@ -623,4 +617,36 @@ TEST(runtime_calls) {
 
 #endif  // VIXL_HAS_SIMULATED_RUNTIME_CALL_SUPPORT
 
+TEST(sve_strlen) {
+  START();
+
+  CPUFeatures cpu_features(CPUFeatures::kSVE);
+  masm.SetCPUFeatures(cpu_features);
+
+  Label sve_strlen;
+  masm.Bind(&sve_strlen);
+  GenerateSVEStrlen(&masm);
+  masm.FinalizeCode();
+
+  if (CanRun(cpu_features)) {
+    const char* inputs[] =
+        {"Exactly 15 chrs",
+         "Exactly 16 chars",
+         "Exactly 17 chars.",
+
+         "This string is very long and will require multiple iterations, even "
+         "with the maximum VL (256 bytes). This string is very long and will "
+         "require multiple iterations, even with the maximum VL (256 bytes). "
+         "This string is very long and will require multiple iterations, even "
+         "with the maximum VL (256 bytes)."};
+
+    for (size_t i = 0; i < ArrayLength(inputs); i++) {
+      simulator.ResetState();
+      simulator.WriteXRegister(0, reinterpret_cast<uintptr_t>(inputs[i]));
+      TEST_FUNCTION(sve_strlen);
+      VIXL_CHECK(static_cast<size_t>(regs.xreg(0)) == strlen(inputs[i]));
+    }
+  }
+}
+
 #endif  // VIXL_INCLUDE_SIMULATOR_AARCH64
diff --git a/test/aarch64/test-api-aarch64.cc b/test/aarch64/test-api-aarch64.cc
index 97103e7c..b25fa7cb 100644
--- a/test/aarch64/test-api-aarch64.cc
+++ b/test/aarch64/test-api-aarch64.cc
@@ -33,6 +33,8 @@
 #include "aarch64/test-utils-aarch64.h"
 
 #include "aarch64/macro-assembler-aarch64.h"
+#include "aarch64/registers-aarch64.h"
+#include "aarch64/simulator-aarch64.h"
 
 #define __ masm.
 #define TEST(name) TEST_(AARCH64_API_##name)
@@ -118,6 +120,22 @@ TEST(float16_operators) {
                ::vixl::internal::SimFloat16(kFP16NegativeZero)));
 }
 
+TEST(rawbits_conversions) {
+  VIXL_CHECK(RawbitsToInt64(0x0) == 0x0);
+  VIXL_CHECK(RawbitsToInt64(0x123) == 0x123);
+  VIXL_CHECK(RawbitsToInt64(INT64_MAX) == INT64_MAX);
+  VIXL_CHECK(RawbitsToInt64(UINT64_C(0xffffffffffffffff)) == -1);
+  VIXL_CHECK(RawbitsToInt64(UINT64_C(0x8000000000000000)) == INT64_MIN);
+  VIXL_CHECK(RawbitsToInt64(UINT64_C(0x8000000000000001)) == -INT64_MAX);
+
+  VIXL_CHECK(RawbitsToInt32(0x0) == 0x0);
+  VIXL_CHECK(RawbitsToInt32(0x123) == 0x123);
+  VIXL_CHECK(RawbitsToInt32(INT32_MAX) == INT32_MAX);
+  VIXL_CHECK(RawbitsToInt32(UINT32_C(0xffffffff)) == -1);
+  VIXL_CHECK(RawbitsToInt32(UINT32_C(0x80000000)) == INT32_MIN);
+  VIXL_CHECK(RawbitsToInt32(UINT32_C(0x80000001)) == -INT32_MAX);
+}
+
 // Check moved FP constants are still accessible via the AArch64 namespace.
 TEST(float_constants_scope) {
   VIXL_CHECK(vixl::aarch64::kFP64PositiveInfinity ==
@@ -193,6 +211,173 @@ TEST(noreg) {
 }
 
 
+TEST(constructors) {
+  // *Register(code)
+  VIXL_CHECK(WRegister(0).Is(w0));
+  VIXL_CHECK(XRegister(1).Is(x1));
+
+  VIXL_CHECK(BRegister(2).Is(b2));
+  VIXL_CHECK(HRegister(3).Is(h3));
+  VIXL_CHECK(SRegister(4).Is(s4));
+  VIXL_CHECK(DRegister(5).Is(d5));
+  VIXL_CHECK(QRegister(6).Is(q6));
+
+  VIXL_CHECK(ZRegister(7).Is(z7));
+  VIXL_CHECK(PRegister(8).Is(p8));
+}
+
+
+TEST(constructors_r) {
+  // Register(code, size_in_bits)
+  VIXL_CHECK(Register(0, kWRegSize).Is(w0));
+  VIXL_CHECK(Register(1, kXRegSize).Is(x1));
+}
+
+
+TEST(constructors_v) {
+  // VRegister(code)
+  VIXL_CHECK(VRegister(0).Is(v0));
+  VIXL_CHECK(VRegister(1).Is(v1));
+  VIXL_CHECK(VRegister(2).Is(v2));
+  VIXL_CHECK(VRegister(3).Is(v3));
+  VIXL_CHECK(VRegister(4).Is(v4));
+
+  // VRegister(code, size_in_bits)
+  VIXL_CHECK(VRegister(0, kBRegSize).Is(b0));
+  VIXL_CHECK(VRegister(1, kHRegSize).Is(h1));
+  VIXL_CHECK(VRegister(2, kSRegSize).Is(s2));
+  VIXL_CHECK(VRegister(3, kDRegSize).Is(d3));
+  VIXL_CHECK(VRegister(4, kQRegSize).Is(q4));
+
+  // VRegister(code, size_in_bits, lanes)
+  VIXL_CHECK(VRegister(0, kBRegSize, 1).Is(b0));
+  VIXL_CHECK(VRegister(1, kHRegSize, 1).Is(h1));
+  VIXL_CHECK(VRegister(2, kSRegSize, 1).Is(s2));
+  VIXL_CHECK(VRegister(3, kDRegSize, 1).Is(d3));
+  VIXL_CHECK(VRegister(4, kQRegSize, 1).Is(q4));
+
+  VIXL_CHECK(VRegister(0, kSRegSize, 2).Is(v0.V2H()));
+
+  VIXL_CHECK(VRegister(1, kDRegSize, 1).Is(v1.V1D()));
+  VIXL_CHECK(VRegister(2, kDRegSize, 2).Is(v2.V2S()));
+  VIXL_CHECK(VRegister(3, kDRegSize, 4).Is(v3.V4H()));
+  VIXL_CHECK(VRegister(4, kDRegSize, 8).Is(v4.V8B()));
+
+  VIXL_CHECK(VRegister(5, kQRegSize, 2).Is(v5.V2D()));
+  VIXL_CHECK(VRegister(6, kQRegSize, 4).Is(v6.V4S()));
+  VIXL_CHECK(VRegister(7, kQRegSize, 8).Is(v7.V8H()));
+  VIXL_CHECK(VRegister(8, kQRegSize, 16).Is(v8.V16B()));
+
+  // VRegister(code, format)
+  VIXL_CHECK(VRegister(0, kFormatB).Is(b0));
+  VIXL_CHECK(VRegister(1, kFormatH).Is(h1));
+  VIXL_CHECK(VRegister(2, kFormatS).Is(s2));
+  VIXL_CHECK(VRegister(3, kFormatD).Is(d3));
+  VIXL_CHECK(VRegister(4, kFormat8B).Is(v4.V8B()));
+  VIXL_CHECK(VRegister(5, kFormat16B).Is(v5.V16B()));
+  VIXL_CHECK(VRegister(6, kFormat2H).Is(v6.V2H()));
+  VIXL_CHECK(VRegister(7, kFormat4H).Is(v7.V4H()));
+  VIXL_CHECK(VRegister(8, kFormat8H).Is(v8.V8H()));
+  VIXL_CHECK(VRegister(9, kFormat2S).Is(v9.V2S()));
+  VIXL_CHECK(VRegister(10, kFormat4S).Is(v10.V4S()));
+  VIXL_CHECK(VRegister(11, kFormat1D).Is(v11.V1D()));
+  VIXL_CHECK(VRegister(12, kFormat2D).Is(v12.V2D()));
+}
+
+
+TEST(constructors_z) {
+  // ZRegister(code, lane_size_in_bits)
+  VIXL_CHECK(ZRegister(0, kBRegSize).Is(z0.VnB()));
+  VIXL_CHECK(ZRegister(1, kHRegSize).Is(z1.VnH()));
+  VIXL_CHECK(ZRegister(2, kSRegSize).Is(z2.VnS()));
+  VIXL_CHECK(ZRegister(3, kDRegSize).Is(z3.VnD()));
+
+  // ZRegister(code, format)
+  VIXL_CHECK(ZRegister(0, kFormatVnB).Is(z0.VnB()));
+  VIXL_CHECK(ZRegister(1, kFormatVnH).Is(z1.VnH()));
+  VIXL_CHECK(ZRegister(2, kFormatVnS).Is(z2.VnS()));
+  VIXL_CHECK(ZRegister(3, kFormatVnD).Is(z3.VnD()));
+}
+
+
+TEST(constructors_p) {
+  // ZRegister(code, lane_size_in_bits)
+  VIXL_CHECK(PRegisterWithLaneSize(0, kBRegSize).Is(p0.VnB()));
+  VIXL_CHECK(PRegisterWithLaneSize(1, kHRegSize).Is(p1.VnH()));
+  VIXL_CHECK(PRegisterWithLaneSize(2, kSRegSize).Is(p2.VnS()));
+  VIXL_CHECK(PRegisterWithLaneSize(3, kDRegSize).Is(p3.VnD()));
+
+  // ZRegister(code, format)
+  VIXL_CHECK(PRegisterWithLaneSize(0, kFormatVnB).Is(p0.VnB()));
+  VIXL_CHECK(PRegisterWithLaneSize(1, kFormatVnH).Is(p1.VnH()));
+  VIXL_CHECK(PRegisterWithLaneSize(2, kFormatVnS).Is(p2.VnS()));
+  VIXL_CHECK(PRegisterWithLaneSize(3, kFormatVnD).Is(p3.VnD()));
+
+  VIXL_CHECK(PRegisterZ(0).Is(p0.Zeroing()));
+  VIXL_CHECK(PRegisterM(1).Is(p1.Merging()));
+}
+
+
+TEST(constructors_cpu) {
+  // ZRegister(code, size_in_bits, type)
+  VIXL_CHECK(CPURegister(0, kWRegSize, CPURegister::kRegister).Is(w0));
+  VIXL_CHECK(CPURegister(1, kXRegSize, CPURegister::kRegister).Is(x1));
+
+  VIXL_CHECK(CPURegister(2, kBRegSize, CPURegister::kVRegister).Is(b2));
+  VIXL_CHECK(CPURegister(3, kHRegSize, CPURegister::kVRegister).Is(h3));
+  VIXL_CHECK(CPURegister(4, kSRegSize, CPURegister::kVRegister).Is(s4));
+  VIXL_CHECK(CPURegister(5, kDRegSize, CPURegister::kVRegister).Is(d5));
+  VIXL_CHECK(CPURegister(6, kQRegSize, CPURegister::kVRegister).Is(q6));
+  VIXL_CHECK(CPURegister(7, kQRegSize, CPURegister::kVRegister).Is(v7));
+
+  VIXL_CHECK(CPURegister(0, CPURegister::kUnknownSize, CPURegister::kVRegister)
+                 .Is(z0));
+  VIXL_CHECK(CPURegister(1, CPURegister::kUnknownSize, CPURegister::kPRegister)
+                 .Is(p1));
+}
+
+
+#ifdef __aarch64__
+static void CPURegisterByValueHelper(CPURegister reg) {
+  // Test that `reg` can be passed in one register. We'd like to use
+  // __attribute__((naked)) for this, but it isn't supported for AArch64, so
+  // generate a function using VIXL instead.
+
+  MacroAssembler masm;
+  // CPURegister fn(int placeholder, CPURegister reg);
+  // Move `reg` to its result register.
+  __ Mov(x0, x1);
+  // Clobber all other result registers.
+  __ Mov(x1, 0xfffffffffffffff1);
+  __ Mov(x2, 0xfffffffffffffff2);
+  __ Mov(x3, 0xfffffffffffffff3);
+  __ Mov(x4, 0xfffffffffffffff4);
+  __ Mov(x5, 0xfffffffffffffff5);
+  __ Mov(x6, 0xfffffffffffffff6);
+  __ Mov(x7, 0xfffffffffffffff7);
+  __ Ret();
+  masm.FinalizeCode();
+
+  CodeBuffer* buffer = masm.GetBuffer();
+  auto fn = buffer->GetStartAddress<CPURegister (*)(int, CPURegister)>();
+  buffer->SetExecutable();
+  CPURegister out = fn(42, reg);
+
+  VIXL_CHECK(out.Is(reg));
+}
+
+
+TEST(cpureg_by_value) {
+  VIXL_STATIC_ASSERT(sizeof(CPURegister) <= sizeof(void*));
+  // Check some arbitrary registers to try to exercise each encoding field.
+  CPURegisterByValueHelper(x0);
+  CPURegisterByValueHelper(v31.V8H());
+  CPURegisterByValueHelper(z16.VnD());
+  CPURegisterByValueHelper(p15.Merging());
+}
+#endif  // __aarch64__
+
+
 TEST(isvalid) {
   VIXL_CHECK(!NoReg.IsValid());
   VIXL_CHECK(!NoVReg.IsValid());
@@ -376,6 +561,134 @@ TEST(areconsecutive) {
 }
 
 
+TEST(sve_p_registers) {
+  enum Qualification { kNone, kZeroing, kMerging, kWithLaneSize };
+  class Helper {
+   public:
+    static Qualification GetQualification(PRegister) { return kNone; }
+    static Qualification GetQualification(PRegisterZ) { return kZeroing; }
+    static Qualification GetQualification(PRegisterM) { return kMerging; }
+    static Qualification GetQualification(PRegisterWithLaneSize) {
+      return kWithLaneSize;
+    }
+  };
+
+  VIXL_CHECK(kNumberOfPRegisters == 16);
+  VIXL_CHECK(p0.GetCode() == 0);
+  VIXL_CHECK(p15.GetCode() == 15);
+  VIXL_CHECK(p14.VnB().GetLaneSizeInBits() == kBRegSize);
+  VIXL_CHECK(p14.VnH().GetLaneSizeInBits() == kHRegSize);
+  VIXL_CHECK(p14.VnS().GetLaneSizeInBits() == kSRegSize);
+  VIXL_CHECK(p14.VnD().GetLaneSizeInBits() == kDRegSize);
+  VIXL_CHECK(p14.VnB().GetLaneSizeInBytes() == kBRegSizeInBytes);
+  VIXL_CHECK(p14.VnH().GetLaneSizeInBytes() == kHRegSizeInBytes);
+  VIXL_CHECK(p14.VnS().GetLaneSizeInBytes() == kSRegSizeInBytes);
+  VIXL_CHECK(p14.VnD().GetLaneSizeInBytes() == kDRegSizeInBytes);
+  VIXL_CHECK(Helper::GetQualification(p1) == kNone);
+  VIXL_CHECK(Helper::GetQualification(p2.Zeroing()) == kZeroing);
+  VIXL_CHECK(Helper::GetQualification(p3.Merging()) == kMerging);
+  VIXL_CHECK(Helper::GetQualification(p4.VnB()) == kWithLaneSize);
+  VIXL_CHECK(Helper::GetQualification(p5.VnH()) == kWithLaneSize);
+  VIXL_CHECK(Helper::GetQualification(p6.VnS()) == kWithLaneSize);
+  VIXL_CHECK(Helper::GetQualification(p7.VnD()) == kWithLaneSize);
+}
+
+
+TEST(sve_z_registers) {
+  VIXL_CHECK(z0.GetCode() == 0);
+  VIXL_CHECK(z31.GetCode() == 31);
+
+  VIXL_CHECK(z0.Is(z0));
+  VIXL_CHECK(!z0.Is(z1));
+  VIXL_CHECK(!z0.Is(v0));
+  VIXL_CHECK(!z0.Is(b0));
+  VIXL_CHECK(!z0.Is(q0));
+
+  VIXL_CHECK(AreAliased(z5, z5));
+  VIXL_CHECK(AreAliased(z5, b5));
+  VIXL_CHECK(AreAliased(b5, z5));
+  VIXL_CHECK(AreAliased(z5, z5.B()));
+  VIXL_CHECK(AreAliased(z5, z5.VnB()));
+
+  VIXL_CHECK(!AreAliased(z6, z7));
+  VIXL_CHECK(!AreAliased(b6, z7));
+  VIXL_CHECK(!AreAliased(x7, z7));
+}
+
+
+TEST(sve_z_registers_vs_neon) {
+  // There are three related register variants to consider in VIXL's API:
+  //
+  //    "b0": NEON: The least-significant byte of v0.
+  //    "v0.B": NEON: v0, with an unspecified number of byte-sized lanes.
+  //    "z0.B": SVE: z0, with an unspecified number of byte-sized lanes.
+  //
+  // The first two cases are indistinguishable in VIXL; both are obtained using
+  // something like `v0.B()`. This is fine for NEON because there is no
+  // ambiguity in practice; the "v0.B" form is always used with an index that
+  // makes the meaning clear.
+
+  VIXL_ASSERT(v6.B().Is(b6));
+  VIXL_ASSERT(v7.H().Is(h7));
+  VIXL_ASSERT(v8.S().Is(s8));
+  VIXL_ASSERT(v9.D().Is(d9));
+
+  VIXL_ASSERT(z6.B().Is(b6));
+  VIXL_ASSERT(z7.H().Is(h7));
+  VIXL_ASSERT(z8.S().Is(s8));
+  VIXL_ASSERT(z9.D().Is(d9));
+
+  // We cannot use the same approach for SVE's "z0.B" because, for example,
+  // `Add(VRegister, ...)` and `Add(ZRegister, ...)` generate different
+  // instructions.
+
+  // Test that the variants can be distinguished with `Is`.
+  VIXL_CHECK(!z6.VnB().Is(b6));
+  VIXL_CHECK(!z7.VnH().Is(h7));
+  VIXL_CHECK(!z8.VnS().Is(s8));
+  VIXL_CHECK(!z9.VnD().Is(d9));
+
+  VIXL_CHECK(!z6.VnB().Is(v6.B()));
+  VIXL_CHECK(!z7.VnH().Is(v7.H()));
+  VIXL_CHECK(!z8.VnS().Is(v8.S()));
+  VIXL_CHECK(!z9.VnD().Is(v9.D()));
+
+  VIXL_CHECK(!z6.VnB().Is(z6.B()));
+  VIXL_CHECK(!z7.VnH().Is(z7.H()));
+  VIXL_CHECK(!z8.VnS().Is(z8.S()));
+  VIXL_CHECK(!z9.VnD().Is(z9.D()));
+
+  // Test that the variants can be distinguished at compile-time using
+  // overloading. VIXL's API relies on this.
+  enum Variant { kNEON, kSVE, kUnknown };
+  class Helper {
+   public:
+    static Variant GetVariant(ZRegister) { return kSVE; }
+    static Variant GetVariant(VRegister) { return kNEON; }
+    static Variant GetVariant(CPURegister) { return kUnknown; }
+  };
+  VIXL_CHECK(Helper::GetVariant(z10.VnB()) == kSVE);
+  VIXL_CHECK(Helper::GetVariant(z11.VnH()) == kSVE);
+  VIXL_CHECK(Helper::GetVariant(z12.VnS()) == kSVE);
+  VIXL_CHECK(Helper::GetVariant(z13.VnD()) == kSVE);
+
+  VIXL_CHECK(Helper::GetVariant(v10.B()) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(v11.H()) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(v12.S()) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(v13.D()) == kNEON);
+
+  VIXL_CHECK(Helper::GetVariant(v10.V16B()) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(v11.V8H()) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(v12.V4S()) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(v13.V2D()) == kNEON);
+
+  VIXL_CHECK(Helper::GetVariant(b10) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(h11) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(s12) == kNEON);
+  VIXL_CHECK(Helper::GetVariant(d13) == kNEON);
+}
+
+
 TEST(move_immediate_helpers) {
   // Using these helpers to query information (without generating code) should
   // not crash.
@@ -411,6 +724,228 @@ TEST(generic_operand_helpers) {
 }
 
 
+TEST(integer_operand_is) {
+  VIXL_CHECK(IntegerOperand(0).IsZero());
+  VIXL_CHECK(!IntegerOperand(1).IsZero());
+  VIXL_CHECK(!IntegerOperand(-1).IsZero());
+
+  VIXL_CHECK(!IntegerOperand(-0x81).IsIntN(8));
+  VIXL_CHECK(IntegerOperand(-0x80).IsIntN(8));
+  VIXL_CHECK(IntegerOperand(-1).IsIntN(8));
+  VIXL_CHECK(IntegerOperand(0).IsIntN(8));
+  VIXL_CHECK(IntegerOperand(1).IsIntN(8));
+  VIXL_CHECK(IntegerOperand(0x7f).IsIntN(8));
+  VIXL_CHECK(!IntegerOperand(0x80).IsIntN(8));
+
+  VIXL_CHECK(!IntegerOperand(-1).IsUintN(8));
+  VIXL_CHECK(IntegerOperand(0).IsUintN(8));
+  VIXL_CHECK(IntegerOperand(1).IsUintN(8));
+  VIXL_CHECK(IntegerOperand(0xff).IsUintN(8));
+  VIXL_CHECK(!IntegerOperand(0x100).IsUintN(8));
+
+  VIXL_CHECK(IntegerOperand(INT64_MIN).IsIntN(64));
+  VIXL_CHECK(IntegerOperand(0).IsIntN(64));
+  VIXL_CHECK(IntegerOperand(INT64_MAX).IsIntN(64));
+  VIXL_CHECK(!IntegerOperand(0x8000000000000000).IsIntN(64));
+
+  VIXL_CHECK(!IntegerOperand(-1).IsUintN(64));
+  VIXL_CHECK(IntegerOperand(0).IsUintN(64));
+  VIXL_CHECK(IntegerOperand(UINT64_MAX).IsUintN(64));
+
+  VIXL_CHECK(!IntegerOperand(-0x801).FitsInBits(12));
+  VIXL_CHECK(IntegerOperand(-0x800).FitsInBits(12));
+  VIXL_CHECK(IntegerOperand(0).FitsInBits(12));
+  VIXL_CHECK(IntegerOperand(0x7ff).FitsInBits(12));
+  VIXL_CHECK(IntegerOperand(0x800).FitsInBits(12));
+  VIXL_CHECK(IntegerOperand(0xfff).FitsInBits(12));
+  VIXL_CHECK(!IntegerOperand(0x1000).FitsInBits(12));
+
+  VIXL_CHECK(!IntegerOperand(-0x8001).FitsInLane(z0.VnH()));
+  VIXL_CHECK(IntegerOperand(-0x8000).FitsInLane(z0.VnH()));
+  VIXL_CHECK(IntegerOperand(0).FitsInLane(z0.VnH()));
+  VIXL_CHECK(IntegerOperand(0x7fff).FitsInLane(z0.VnH()));
+  VIXL_CHECK(IntegerOperand(0x8000).FitsInLane(z0.VnH()));
+  VIXL_CHECK(IntegerOperand(0xffff).FitsInLane(z0.VnH()));
+  VIXL_CHECK(!IntegerOperand(0x10000).FitsInLane(z0.VnH()));
+}
+
+TEST(integer_operand_as_uint) {
+  // Simple cases.
+  VIXL_CHECK(IntegerOperand(1).AsUintN(8) == 1);
+  VIXL_CHECK(IntegerOperand(1).AsUintN(16) == 1);
+  VIXL_CHECK(IntegerOperand(1).AsUintN(32) == 1);
+  VIXL_CHECK(IntegerOperand(1).AsUintN(64) == 1);
+  VIXL_CHECK(IntegerOperand(-1).AsUintN(8) == 0xff);
+  VIXL_CHECK(IntegerOperand(-1).AsUintN(16) == 0xffff);
+  VIXL_CHECK(IntegerOperand(-1).AsUintN(32) == 0xffffffff);
+  VIXL_CHECK(IntegerOperand(-1).AsUintN(64) == 0xffffffffffffffff);
+  VIXL_CHECK(IntegerOperand(0xf0).AsUintN(8) == 0xf0);
+  VIXL_CHECK(IntegerOperand(0xf420).AsUintN(16) == 0xf420);
+  VIXL_CHECK(IntegerOperand(0xf4242420).AsUintN(32) == 0xf4242420);
+  VIXL_CHECK(IntegerOperand(0xf424242424242420).AsUintN(64) ==
+             0xf424242424242420);
+
+  // Boundary conditions for known-size types.
+  VIXL_CHECK(IntegerOperand(INT8_MIN).AsUintN(8) == 0x80);
+  VIXL_CHECK(IntegerOperand(INT8_MAX).AsUintN(8) == 0x7f);
+  VIXL_CHECK(IntegerOperand(UINT8_MAX).AsUintN(8) == 0xff);
+
+  VIXL_CHECK(IntegerOperand(INT16_MIN).AsUintN(16) == 0x8000);
+  VIXL_CHECK(IntegerOperand(INT16_MAX).AsUintN(16) == 0x7fff);
+  VIXL_CHECK(IntegerOperand(UINT16_MAX).AsUintN(16) == 0xffff);
+
+  VIXL_CHECK(IntegerOperand(INT32_MIN).AsUintN(32) == 0x80000000);
+  VIXL_CHECK(IntegerOperand(INT32_MAX).AsUintN(32) == 0x7fffffff);
+  VIXL_CHECK(IntegerOperand(UINT32_MAX).AsUintN(32) == 0xffffffff);
+
+  VIXL_CHECK(IntegerOperand(INT64_MIN).AsUintN(64) == 0x8000000000000000);
+  VIXL_CHECK(IntegerOperand(INT64_MAX).AsUintN(64) == 0x7fffffffffffffff);
+  VIXL_CHECK(IntegerOperand(UINT64_MAX).AsUintN(64) == 0xffffffffffffffff);
+}
+
+TEST(integer_operand_as_int) {
+  // Simple cases.
+  VIXL_CHECK(IntegerOperand(1).AsIntN(8) == 1);
+  VIXL_CHECK(IntegerOperand(1).AsIntN(16) == 1);
+  VIXL_CHECK(IntegerOperand(1).AsIntN(32) == 1);
+  VIXL_CHECK(IntegerOperand(1).AsIntN(64) == 1);
+  VIXL_CHECK(IntegerOperand(-1).AsIntN(8) == -1);
+  VIXL_CHECK(IntegerOperand(-1).AsIntN(16) == -1);
+  VIXL_CHECK(IntegerOperand(-1).AsIntN(32) == -1);
+  VIXL_CHECK(IntegerOperand(-1).AsIntN(64) == -1);
+  VIXL_CHECK(IntegerOperand(0x70).AsIntN(8) == 0x70);
+  VIXL_CHECK(IntegerOperand(0x7420).AsIntN(16) == 0x7420);
+  VIXL_CHECK(IntegerOperand(0x74242420).AsIntN(32) == 0x74242420);
+  VIXL_CHECK(IntegerOperand(0x7424242424242420).AsIntN(64) ==
+             0x7424242424242420);
+
+  // Boundary conditions for known-size types.
+  VIXL_CHECK(IntegerOperand(UINT8_MAX).AsIntN(8) == -1);
+  VIXL_CHECK(IntegerOperand(UINT16_MAX).AsIntN(16) == -1);
+  VIXL_CHECK(IntegerOperand(UINT32_MAX).AsIntN(32) == -1);
+  VIXL_CHECK(IntegerOperand(UINT64_MAX).AsIntN(64) == -1);
+
+  VIXL_CHECK(IntegerOperand(INT8_MAX).AsIntN(8) == INT8_MAX);
+  VIXL_CHECK(IntegerOperand(INT16_MAX).AsIntN(16) == INT16_MAX);
+  VIXL_CHECK(IntegerOperand(INT32_MAX).AsIntN(32) == INT32_MAX);
+  VIXL_CHECK(IntegerOperand(INT64_MAX).AsIntN(64) == INT64_MAX);
+
+  VIXL_CHECK(IntegerOperand(0x80).AsIntN(8) == INT8_MIN);
+  VIXL_CHECK(IntegerOperand(0x8000).AsIntN(16) == INT16_MIN);
+  VIXL_CHECK(IntegerOperand(0x80000000).AsIntN(32) == INT32_MIN);
+  VIXL_CHECK(IntegerOperand(0x8000000000000000).AsIntN(64) == INT64_MIN);
+}
+
+template <unsigned N>
+class IntegerOperandTryEncodeShiftedIntHelper {
+ public:
+  IntegerOperandTryEncodeShiftedIntHelper() {}
+
+  template <unsigned kShift, typename T>
+  void TestEncodable(T value, const ZRegister& zd, int64_t expected_imm) {
+    VIXL_CHECK(TestImpl<kShift>(value, zd, expected_imm));
+  }
+
+  template <unsigned kShift, typename T>
+  void TestUnencodable(T value, const ZRegister& zd) {
+    // The `expected_imm` value is ignored, so its value is arbitrary.
+    VIXL_CHECK(!TestImpl<kShift>(value, zd, 0));
+  }
+
+ private:
+  template <unsigned kShift, typename T>
+  bool TestImpl(T value, const ZRegister& zd, int64_t expected_imm) {
+    IntegerOperand operand(value);
+    int64_t imm = 0xdeadbeef42;
+    unsigned shift = 0xbeef43;
+    bool success =
+        operand.TryEncodeAsShiftedIntNForLane<N, kShift>(zd, &imm, &shift);
+    if (success) {
+      VIXL_CHECK(imm == expected_imm);
+      VIXL_CHECK(shift == kShift);
+    } else {
+      // Check that the outputs were unmodified.
+      VIXL_CHECK(imm == 0xdeadbeef42);
+      VIXL_CHECK(shift == 0xbeef43);
+    }
+
+    // If kShift is 0, also check TryEncodeAsIntNForLane.
+    if (kShift == 0) {
+      int64_t unshifted_imm = 0xdeadbeef99;
+      bool unshifted_success =
+          operand.TryEncodeAsIntNForLane<N>(zd, &unshifted_imm);
+
+      VIXL_CHECK(unshifted_success == success);
+      if (unshifted_success) {
+        VIXL_CHECK(unshifted_imm == expected_imm);
+      } else {
+        VIXL_CHECK(unshifted_imm == 0xdeadbeef99);
+      }
+    }
+
+    return success;
+  }
+};
+
+TEST(integer_operand_encode_as_intn) {
+  IntegerOperandTryEncodeShiftedIntHelper<4> int4_helper;
+  IntegerOperandTryEncodeShiftedIntHelper<8> int8_helper;
+  IntegerOperandTryEncodeShiftedIntHelper<12> int12_helper;
+
+  // Simple cases, where the value is directly encodable.
+  int4_helper.TestEncodable<0>(-8, z0.VnH(), -8);
+  int4_helper.TestEncodable<0>(-7, z0.VnH(), -7);
+  int4_helper.TestEncodable<0>(-1, z0.VnS(), -1);
+  int4_helper.TestEncodable<0>(0, z0.VnD(), 0);
+  int4_helper.TestEncodable<0>(1, z0.VnB(), 1);
+  int4_helper.TestEncodable<0>(7, z0.VnH(), 7);
+
+  int8_helper.TestEncodable<0>(0x7f, z0.VnB(), 0x7f);
+  int8_helper.TestEncodable<0>(0x7f, z0.VnH(), 0x7f);
+  int12_helper.TestEncodable<0>(0x7ff, z0.VnH(), 0x7ff);
+
+  int8_helper.TestEncodable<0>(-0x80, z0.VnB(), -0x80);
+  int8_helper.TestEncodable<0>(-0x80, z0.VnH(), -0x80);
+  int12_helper.TestEncodable<0>(-0x800, z0.VnH(), -0x800);
+
+  // Cases that are directly encodable with a shift.
+  int8_helper.TestEncodable<4>(-0x800, z0.VnH(), -0x80);
+  int8_helper.TestEncodable<4>(-0x7f0, z0.VnH(), -0x7f);
+  int8_helper.TestEncodable<4>(-0x010, z0.VnH(), -1);
+  int8_helper.TestEncodable<4>(0x000, z0.VnH(), 0);
+  int8_helper.TestEncodable<4>(0x010, z0.VnH(), 1);
+  int8_helper.TestEncodable<4>(0x7f0, z0.VnH(), 0x7f);
+
+  // Ensure that (positive) bit representations of negative values are treated
+  // as negative values, even though their arithmetic values are unencodable.
+  int12_helper.TestEncodable<0>(0xffd6, z0.VnH(), -42);
+  int12_helper.TestEncodable<0>(0xffffffd6, z0.VnS(), -42);
+  int12_helper.TestEncodable<4>(0xfd60, z0.VnH(), -42);
+  int12_helper.TestEncodable<8>(0xffffd600, z0.VnS(), -42);
+
+  int8_helper.TestEncodable<0>(UINT8_MAX, z0.VnB(), -1);
+  int8_helper.TestEncodable<0>(UINT16_MAX, z0.VnH(), -1);
+  int8_helper.TestEncodable<0>(UINT32_MAX, z0.VnS(), -1);
+  int8_helper.TestEncodable<0>(UINT64_MAX, z0.VnD(), -1);
+
+  int4_helper.TestEncodable<1>(UINT8_MAX ^ 0x1, z0.VnB(), -1);
+  int4_helper.TestEncodable<2>(UINT16_MAX ^ 0x3, z0.VnH(), -1);
+  int4_helper.TestEncodable<3>(UINT32_MAX ^ 0x7, z0.VnS(), -1);
+  int4_helper.TestEncodable<4>(UINT64_MAX ^ 0xf, z0.VnD(), -1);
+
+  // Unencodable cases.
+  int8_helper.TestUnencodable<0>(INT16_MAX, z0.VnH());
+  int8_helper.TestUnencodable<0>(INT32_MAX, z0.VnS());
+  int8_helper.TestUnencodable<0>(INT64_MAX, z0.VnD());
+
+  int4_helper.TestUnencodable<0>(0x10, z0.VnB());
+  int4_helper.TestUnencodable<1>(0x20, z0.VnB());
+
+  int12_helper.TestUnencodable<1>(1, z0.VnD());
+  int12_helper.TestUnencodable<12>(1, z0.VnD());
+  int12_helper.TestUnencodable<12>(0x800, z0.VnD());
+}
+
 TEST(static_register_types) {
   // [WX]Register implicitly casts to Register.
   XRegister x_x0(0);
@@ -444,7 +979,7 @@ TEST(static_register_types) {
 }
 
 
-TEST(is_plain_register) {
+TEST(operand_is_plain_register) {
   VIXL_CHECK(Operand(x0).IsPlainRegister());
   VIXL_CHECK(Operand(x1, LSL, 0).IsPlainRegister());
   VIXL_CHECK(Operand(x2, LSR, 0).IsPlainRegister());
@@ -479,5 +1014,756 @@ TEST(is_plain_register) {
 }
 
 
+TEST(memoperand_is_plain_register) {
+  VIXL_CHECK(MemOperand(x0).IsPlainRegister());
+  VIXL_CHECK(MemOperand(sp).IsPlainRegister());
+  VIXL_CHECK(MemOperand(x1, 0).IsPlainRegister());
+
+  VIXL_CHECK(!MemOperand(x2, xzr).IsPlainRegister());
+  VIXL_CHECK(!MemOperand(x3, xzr, SXTX).IsPlainRegister());
+  VIXL_CHECK(!MemOperand(x4, xzr, SXTX, 2).IsPlainRegister());
+  VIXL_CHECK(!MemOperand(x5, wzr, UXTW).IsPlainRegister());
+  VIXL_CHECK(!MemOperand(x6, wzr, UXTW, 3).IsPlainRegister());
+
+  VIXL_CHECK(!MemOperand(x7, 0, PostIndex).IsPlainRegister());
+  VIXL_CHECK(!MemOperand(x8, 0, PreIndex).IsPlainRegister());
+  VIXL_CHECK(!MemOperand(x9, xzr, PostIndex).IsPlainRegister());
+
+  VIXL_CHECK(!MemOperand(x20, 1).IsPlainRegister());
+  VIXL_CHECK(!MemOperand(x21, x30).IsPlainRegister());
+}
+
+TEST(memoperand_is_plain_register_or_equivalent) {
+  VIXL_CHECK(MemOperand(x0).IsEquivalentToPlainRegister());
+  VIXL_CHECK(MemOperand(sp).IsEquivalentToPlainRegister());
+  VIXL_CHECK(MemOperand(x1, 0).IsEquivalentToPlainRegister());
+
+  VIXL_CHECK(MemOperand(x2, xzr).IsEquivalentToPlainRegister());
+  VIXL_CHECK(MemOperand(x3, xzr, SXTX).IsEquivalentToPlainRegister());
+  VIXL_CHECK(MemOperand(x4, xzr, SXTX, 2).IsEquivalentToPlainRegister());
+  VIXL_CHECK(MemOperand(x5, wzr, UXTW).IsEquivalentToPlainRegister());
+  VIXL_CHECK(MemOperand(x6, wzr, UXTW, 3).IsEquivalentToPlainRegister());
+
+  VIXL_CHECK(MemOperand(x7, 0, PostIndex).IsEquivalentToPlainRegister());
+  VIXL_CHECK(MemOperand(x8, 0, PreIndex).IsEquivalentToPlainRegister());
+  VIXL_CHECK(MemOperand(x9, xzr, PostIndex).IsEquivalentToPlainRegister());
+
+  VIXL_CHECK(!MemOperand(x20, 1).IsEquivalentToPlainRegister());
+  VIXL_CHECK(!MemOperand(x21, x30).IsEquivalentToPlainRegister());
+}
+
+TEST(sve_memoperand_is_plain_scalar) {
+  VIXL_CHECK(SVEMemOperand(x0).IsPlainScalar());
+  VIXL_CHECK(SVEMemOperand(sp).IsPlainScalar());
+  VIXL_CHECK(SVEMemOperand(x1, 0).IsPlainScalar());
+
+  VIXL_CHECK(!SVEMemOperand(x2, xzr).IsPlainScalar());
+  VIXL_CHECK(!SVEMemOperand(x4, xzr, LSL, 2).IsPlainScalar());
+
+  VIXL_CHECK(!SVEMemOperand(x20, 1).IsPlainScalar());
+  VIXL_CHECK(!SVEMemOperand(x21, x30).IsPlainScalar());
+
+  VIXL_CHECK(!SVEMemOperand(x0, z1.VnD()).IsPlainScalar());
+  VIXL_CHECK(!SVEMemOperand(x2, z3.VnS(), UXTW).IsPlainScalar());
+  VIXL_CHECK(!SVEMemOperand(z4.VnD(), 0).IsPlainScalar());
+}
+
+TEST(sve_memoperand_is_scalar_or_equivalent) {
+  VIXL_CHECK(SVEMemOperand(x0).IsEquivalentToScalar());
+  VIXL_CHECK(SVEMemOperand(sp).IsEquivalentToScalar());
+  VIXL_CHECK(SVEMemOperand(x1, 0).IsEquivalentToScalar());
+
+  VIXL_CHECK(SVEMemOperand(x2, xzr).IsEquivalentToScalar());
+  VIXL_CHECK(SVEMemOperand(x4, xzr, LSL, 2).IsEquivalentToScalar());
+
+  VIXL_CHECK(!SVEMemOperand(x20, 1).IsEquivalentToScalar());
+  VIXL_CHECK(!SVEMemOperand(x21, x30).IsEquivalentToScalar());
+
+  VIXL_CHECK(!SVEMemOperand(x0, z1.VnD()).IsEquivalentToScalar());
+  VIXL_CHECK(!SVEMemOperand(x2, z3.VnD(), SXTW).IsEquivalentToScalar());
+  VIXL_CHECK(!SVEMemOperand(z4.VnD(), 0).IsEquivalentToScalar());
+}
+
+TEST(sve_memoperand_types) {
+  VIXL_CHECK(SVEMemOperand(x0, 42).IsScalarPlusImmediate());
+  VIXL_CHECK(SVEMemOperand(x1, 42, SVE_MUL_VL).IsScalarPlusImmediate());
+  VIXL_CHECK(SVEMemOperand(x2, -42, SVE_MUL_VL).IsScalarPlusImmediate());
+
+  VIXL_CHECK(SVEMemOperand(sp, x3).IsScalarPlusScalar());
+  VIXL_CHECK(SVEMemOperand(x4, xzr).IsScalarPlusScalar());
+  VIXL_CHECK(SVEMemOperand(x5, x6, LSL, 1).IsScalarPlusScalar());
+
+  VIXL_CHECK(SVEMemOperand(x7, z0.VnD()).IsScalarPlusVector());
+  VIXL_CHECK(SVEMemOperand(x8, z1.VnS(), SXTW).IsScalarPlusVector());
+  VIXL_CHECK(SVEMemOperand(x9, z2.VnD(), UXTW).IsScalarPlusVector());
+  VIXL_CHECK(SVEMemOperand(x10, z3.VnD(), LSL, 2).IsScalarPlusVector());
+
+  VIXL_CHECK(SVEMemOperand(z4.VnD(), 42).IsVectorPlusImmediate());
+  VIXL_CHECK(SVEMemOperand(z5.VnS(), -42).IsVectorPlusImmediate());
+}
+
+TEST(sve_memoperand_scatter_gather) {
+  // Single-address accesses.
+  VIXL_CHECK(!SVEMemOperand(x0, 42).IsScatterGather());
+  VIXL_CHECK(!SVEMemOperand(x1, 42, SVE_MUL_VL).IsScatterGather());
+  VIXL_CHECK(!SVEMemOperand(x2, -42, SVE_MUL_VL).IsScatterGather());
+
+  VIXL_CHECK(!SVEMemOperand(sp, x3).IsScatterGather());
+  VIXL_CHECK(!SVEMemOperand(x4, xzr).IsScatterGather());
+  VIXL_CHECK(!SVEMemOperand(x5, x6, LSL, 1).IsScatterGather());
+
+  // Scatter-gather accesses.
+  VIXL_CHECK(SVEMemOperand(x7, z0.VnD()).IsScatterGather());
+  VIXL_CHECK(SVEMemOperand(x8, z1.VnS(), SXTW).IsScatterGather());
+  VIXL_CHECK(SVEMemOperand(x9, z2.VnD(), UXTW).IsScatterGather());
+  VIXL_CHECK(SVEMemOperand(x10, z3.VnD(), LSL, 2).IsScatterGather());
+
+  VIXL_CHECK(SVEMemOperand(z4.VnD(), 42).IsScatterGather());
+  VIXL_CHECK(SVEMemOperand(z5.VnS(), -42).IsScatterGather());
+}
+
+TEST(scratch_scope_basic) {
+  MacroAssembler masm;
+  // x16 and x17 are available as scratch registers by default.
+  {
+    UseScratchRegisterScope temps(&masm);
+    Register temp1 = temps.AcquireW();
+    Register temp2 = temps.AcquireX();
+    VIXL_CHECK(temp1.Is(w16));
+    VIXL_CHECK(temp2.Is(x17));
+  }
+  {
+    UseScratchRegisterScope temps(&masm);
+    Register temp1 = temps.AcquireRegisterOfSize(kXRegSize);
+    Register temp2 = temps.AcquireRegisterOfSize(kWRegSize);
+    VIXL_CHECK(temp1.Is(x16));
+    VIXL_CHECK(temp2.Is(w17));
+  }
+}
+
+TEST(scratch_scope_basic_v) {
+  MacroAssembler masm;
+  // v31 is the only V scratch register available by default.
+  {
+    UseScratchRegisterScope temps(&masm);
+    VRegister temp = temps.AcquireH();
+    VIXL_CHECK(temp.Is(h31));
+  }
+  {
+    UseScratchRegisterScope temps(&masm);
+    VRegister temp = temps.AcquireS();
+    VIXL_CHECK(temp.Is(s31));
+  }
+  {
+    UseScratchRegisterScope temps(&masm);
+    VRegister temp = temps.AcquireD();
+    VIXL_CHECK(temp.Is(d31));
+  }
+  {
+    UseScratchRegisterScope temps(&masm);
+    VRegister temp = temps.AcquireVRegisterOfSize(kQRegSize);
+    VIXL_CHECK(temp.Is(q31));
+  }
+  {
+    UseScratchRegisterScope temps(&masm);
+    VRegister temp = temps.AcquireVRegisterOfSize(kDRegSize);
+    VIXL_CHECK(temp.Is(d31));
+  }
+  {
+    UseScratchRegisterScope temps(&masm);
+    VRegister temp = temps.AcquireVRegisterOfSize(kSRegSize);
+    VIXL_CHECK(temp.Is(s31));
+  }
+}
+
+TEST(scratch_scope_basic_z) {
+  MacroAssembler masm;
+  // z31 is the only Z scratch register available by default.
+  {
+    UseScratchRegisterScope temps(&masm);
+    VIXL_CHECK(temps.IsAvailable(v31));
+    VIXL_CHECK(temps.IsAvailable(z31));
+    ZRegister temp = temps.AcquireZ();
+    VIXL_CHECK(temp.Is(z31));
+    // Check that allocating a Z register properly reserves the corresponding V
+    // register.
+    VIXL_CHECK(!temps.IsAvailable(v31));
+    VIXL_CHECK(!temps.IsAvailable(z31));
+  }
+  // Check that the destructor restored the acquired register.
+  UseScratchRegisterScope temps(&masm);
+  VIXL_CHECK(temps.IsAvailable(v31));
+  VIXL_CHECK(temps.IsAvailable(z31));
+}
+
+TEST(scratch_scope_basic_p) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    // There are no P scratch registers available by default.
+    VIXL_CHECK(masm.GetScratchPRegisterList()->IsEmpty());
+    temps.Include(p0, p1);
+    VIXL_CHECK(temps.IsAvailable(p0));
+    VIXL_CHECK(temps.IsAvailable(p1));
+    temps.Include(p7, p8, p15);
+    VIXL_CHECK(temps.IsAvailable(p7));
+    VIXL_CHECK(temps.IsAvailable(p8));
+    VIXL_CHECK(temps.IsAvailable(p15));
+
+    // AcquireGoverningP() can only return p0-p7.
+    VIXL_CHECK(temps.AcquireGoverningP().GetCode() <
+               kNumberOfGoverningPRegisters);
+    VIXL_CHECK(temps.AcquireGoverningP().GetCode() <
+               kNumberOfGoverningPRegisters);
+    VIXL_CHECK(temps.IsAvailable(p8));
+    VIXL_CHECK(temps.IsAvailable(p15));
+
+    // AcquireP() prefers p8-p15, ...
+    VIXL_CHECK(temps.AcquireP().GetCode() >= kNumberOfGoverningPRegisters);
+    VIXL_CHECK(temps.AcquireP().GetCode() >= kNumberOfGoverningPRegisters);
+    // ... but will return p0-p7 if none of p8-p15 are available.
+    VIXL_CHECK(temps.AcquireP().GetCode() < kNumberOfGoverningPRegisters);
+
+    VIXL_CHECK(masm.GetScratchPRegisterList()->IsEmpty());
+
+    // Leave some registers available so we can test the destructor.
+    temps.Include(p3, p6, p9, p12);
+    VIXL_CHECK(!masm.GetScratchPRegisterList()->IsEmpty());
+  }
+  // Check that the destructor correctly cleared the list.
+  VIXL_CHECK(masm.GetScratchPRegisterList()->IsEmpty());
+}
+
+TEST(scratch_scope_include_ignored) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    // Start with an empty set of scratch registers.
+    temps.ExcludeAll();
+
+    // Including NoReg has no effect.
+    temps.Include(NoReg);
+    temps.Include(NoCPUReg);
+    temps.Include(CPURegList(CPURegister::kNoRegister, 0, 0));
+
+    // Including sp or zr has no effect, since they are never appropriate
+    // scratch registers.
+    temps.Include(sp);
+    temps.Include(xzr, wsp);
+    temps.Include(wzr);
+    temps.Include(CPURegList(xzr, sp));
+
+    VIXL_CHECK(masm.GetScratchRegisterList()->IsEmpty());
+    VIXL_CHECK(masm.GetScratchVRegisterList()->IsEmpty());
+  }
+}
+
+class ScratchScopeHelper {
+ public:
+  enum Action { kRelease, kInclude, kExclude };
+
+  ScratchScopeHelper(MacroAssembler* masm,
+                     Action action,
+                     CPURegister::RegisterType type)
+      : masm_(masm),
+        action_(action),
+        type_(type),
+        expected_(GetGuardListFor(CPURegister::kRegister)),
+        expected_v_(GetGuardListFor(CPURegister::kVRegister)),
+        expected_p_(GetGuardListFor(CPURegister::kPRegister)) {
+    *GetExpectedFor(type) = GetInitialList();
+    masm->GetScratchRegisterList()->SetList(expected_);
+    masm->GetScratchVRegisterList()->SetList(expected_v_);
+    masm->GetScratchPRegisterList()->SetList(expected_p_);
+  }
+
+  // Notify the helper that the registers in `update` have been passed into
+  // DoAction(), and assert that the MacroAssembler's scratch lists are as
+  // expected.
+  void RecordActionsAndCheck(RegList update) {
+    RegList* expected = GetExpectedFor(type_);
+    switch (action_) {
+      case kRelease:
+        // It isn't valid to release a register that is already available.
+        VIXL_CHECK((*expected & update) == 0);
+        VIXL_FALLTHROUGH();
+      case kInclude:
+        *expected |= update;
+        break;
+      case kExclude:
+        *expected &= ~update;
+        break;
+    }
+    VIXL_CHECK(masm_->GetScratchRegisterList()->GetList() == expected_);
+    VIXL_CHECK(masm_->GetScratchVRegisterList()->GetList() == expected_v_);
+    VIXL_CHECK(masm_->GetScratchPRegisterList()->GetList() == expected_p_);
+  }
+
+ private:
+  RegList GetInitialList() {
+    switch (action_) {
+      case kRelease:
+      case kInclude:
+        return 0;
+      case kExclude:
+        return GetPotentialListFor(type_);
+    }
+    VIXL_UNREACHABLE();
+    return 0;
+  }
+
+  // Return some valid, non-zero RegList suitable for use as a guard value.
+  static RegList GetGuardListFor(CPURegister::RegisterType type) {
+    return (0x1111111111111111 * (type + 1)) & GetPotentialListFor(type);
+  }
+
+  static RegList GetPotentialListFor(CPURegister::RegisterType type) {
+    RegList list = CPURegList::All(type).GetList();
+    // The zr and sp registers cannot be scratch registers.
+    if (type == CPURegister::kRegister) list &= ~(xzr.GetBit() | sp.GetBit());
+    return list;
+  }
+
+  RegList* GetExpectedFor(CPURegister::RegisterType type) {
+    switch (type) {
+      case CPURegister::kNoRegister:
+        VIXL_UNREACHABLE();
+        return NULL;
+      case CPURegister::kRegister:
+        return &expected_;
+      case CPURegister::kVRegister:
+      case CPURegister::kZRegister:
+        return &expected_v_;
+      case CPURegister::kPRegister:
+        return &expected_p_;
+    }
+    VIXL_UNREACHABLE();
+    return NULL;
+  }
+
+  MacroAssembler* masm_;
+  Action action_;
+  CPURegister::RegisterType type_;
+
+  RegList expected_;
+  RegList expected_v_;
+  RegList expected_p_;
+};
+
+TEST(scratch_scope_include) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kInclude,
+                              CPURegister::kRegister);
+
+    // Any suitable register type deriving from CPURegister can be included.
+    temps.Include(w0);
+    temps.Include(x1);
+    temps.Include(WRegister(2));
+    temps.Include(XRegister(3));
+    temps.Include(Register(w4));
+    temps.Include(Register(x5));
+    temps.Include(CPURegister(w6));
+    temps.Include(CPURegister(x7));
+    helper.RecordActionsAndCheck(0xff);
+    // Multiple registers can be included at once.
+    temps.Include(x8, w9, x10);
+    temps.Include(Register(w12), Register(x13), Register(w14));
+    temps.Include(XRegister(16), XRegister(17), XRegister(18));
+    temps.Include(WRegister(20), WRegister(21), WRegister(22));
+    temps.Include(CPURegList(w24, w25, w26));
+    helper.RecordActionsAndCheck(0x7777700);
+    // Including a register again has no effect.
+    temps.Include(Register(w26));
+    temps.Include(Register(x25));
+    temps.Include(CPURegister(x24));
+    temps.Include(CPURegister(x22));
+    temps.Include(x21, x20, w18, x17);
+    temps.Include(CPURegList(x16, x14, x13, x12));
+    helper.RecordActionsAndCheck(0x7777700);
+  }
+}
+
+TEST(scratch_scope_exclude) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kExclude,
+                              CPURegister::kRegister);
+
+    // Any suitable register type deriving from CPURegister can be excluded.
+    temps.Exclude(w0);
+    temps.Exclude(x1);
+    temps.Exclude(WRegister(2));
+    temps.Exclude(XRegister(3));
+    temps.Exclude(Register(w4));
+    temps.Exclude(Register(x5));
+    temps.Exclude(CPURegister(w6));
+    temps.Exclude(CPURegister(x7));
+    helper.RecordActionsAndCheck(0xff);
+    // Multiple registers can be excluded at once.
+    temps.Exclude(x8, w9, x10);
+    temps.Exclude(Register(w12), Register(x13), Register(w14));
+    temps.Exclude(XRegister(16), XRegister(17), XRegister(18));
+    temps.Exclude(WRegister(20), WRegister(21), WRegister(22));
+    temps.Exclude(CPURegList(w24, w25, w26));
+    helper.RecordActionsAndCheck(0x7777700);
+    // Excluding a register again has no effect.
+    temps.Exclude(Register(w26));
+    temps.Exclude(Register(x25));
+    temps.Exclude(CPURegister(x24));
+    temps.Exclude(CPURegister(x22));
+    temps.Exclude(x21, x20, w18, x17);
+    temps.Exclude(CPURegList(x16, x14, x13, x12));
+    helper.RecordActionsAndCheck(0x7777700);
+  }
+}
+
+TEST(scratch_scope_release) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kRelease,
+                              CPURegister::kRegister);
+
+    // Any suitable register type deriving from CPURegister can be released.
+    temps.Release(w0);
+    temps.Release(x1);
+    temps.Release(WRegister(2));
+    temps.Release(XRegister(3));
+    temps.Release(Register(w4));
+    temps.Release(Register(x5));
+    temps.Release(CPURegister(w6));
+    temps.Release(CPURegister(x7));
+    helper.RecordActionsAndCheck(0xff);
+    // It is not possible to release more than one register at a time, and it is
+    // invalid to release a register that is already available.
+  }
+}
+
+TEST(scratch_scope_include_v) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kInclude,
+                              CPURegister::kVRegister);
+
+    // Any suitable register type deriving from CPURegister can be included.
+    temps.Include(b0);
+    temps.Include(h1);
+    temps.Include(SRegister(2));
+    temps.Include(DRegister(3));
+    temps.Include(VRegister(q4));
+    temps.Include(VRegister(v5.V8B()));
+    temps.Include(CPURegister(d6));
+    temps.Include(CPURegister(v7.S4B()));
+    helper.RecordActionsAndCheck(0xff);
+    // Multiple registers can be included at once.
+    temps.Include(b8, h9, s10);
+    temps.Include(VRegister(d12), VRegister(d13), VRegister(d14));
+    temps.Include(QRegister(16), QRegister(17), QRegister(18));
+    temps.Include(BRegister(20), BRegister(21), BRegister(22));
+    temps.Include(CPURegList(s24, s25, s26));
+    helper.RecordActionsAndCheck(0x7777700);
+    // Including a register again has no effect.
+    temps.Include(VRegister(b26));
+    temps.Include(VRegister(h25));
+    temps.Include(CPURegister(s24));
+    temps.Include(CPURegister(v22.V4H()));
+    temps.Include(q21, d20, s18, h17);
+    temps.Include(CPURegList(h16, h14, h13, h12));
+    helper.RecordActionsAndCheck(0x7777700);
+  }
+}
+
+TEST(scratch_scope_exclude_v) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kExclude,
+                              CPURegister::kVRegister);
+
+    // Any suitable register type deriving from CPURegister can be excluded.
+    temps.Exclude(b0);
+    temps.Exclude(h1);
+    temps.Exclude(SRegister(2));
+    temps.Exclude(DRegister(3));
+    temps.Exclude(VRegister(q4));
+    temps.Exclude(VRegister(v5.V8B()));
+    temps.Exclude(CPURegister(d6));
+    temps.Exclude(CPURegister(v7.S4B()));
+    helper.RecordActionsAndCheck(0xff);
+    // Multiple registers can be excluded at once.
+    temps.Exclude(b8, h9, s10);
+    temps.Exclude(VRegister(d12), VRegister(d13), VRegister(d14));
+    temps.Exclude(QRegister(16), QRegister(17), QRegister(18));
+    temps.Exclude(BRegister(20), BRegister(21), BRegister(22));
+    temps.Exclude(CPURegList(s24, s25, s26));
+    helper.RecordActionsAndCheck(0x7777700);
+    // Excluding a register again has no effect.
+    temps.Exclude(VRegister(b26));
+    temps.Exclude(VRegister(h25));
+    temps.Exclude(CPURegister(s24));
+    temps.Exclude(CPURegister(v22.V4H()));
+    temps.Exclude(q21, d20, s18, h17);
+    temps.Exclude(CPURegList(h16, h14, h13, h12));
+    helper.RecordActionsAndCheck(0x7777700);
+  }
+}
+
+TEST(scratch_scope_release_v) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kRelease,
+                              CPURegister::kVRegister);
+
+    // Any suitable register type deriving from CPURegister can be released.
+    temps.Release(b0);
+    temps.Release(h1);
+    temps.Release(SRegister(2));
+    temps.Release(DRegister(3));
+    temps.Release(VRegister(q4));
+    temps.Release(VRegister(v5.V8B()));
+    temps.Release(CPURegister(d6));
+    temps.Release(CPURegister(v7.S4B()));
+    helper.RecordActionsAndCheck(0xff);
+    // It is not possible to release more than one register at a time, and it is
+    // invalid to release a register that is already available.
+  }
+}
+
+TEST(scratch_scope_include_z) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kInclude,
+                              CPURegister::kZRegister);
+
+    // Any suitable register type deriving from CPURegister can be included.
+    temps.Include(z0);
+    temps.Include(z1.VnB());
+    temps.Include(ZRegister(2));
+    temps.Include(ZRegister(3, kFormatVnD));
+    temps.Include(CPURegister(z4));
+    temps.Include(CPURegister(z5.VnH()));
+    helper.RecordActionsAndCheck(0x3f);
+    // Multiple registers can be included at once.
+    temps.Include(z8, z9, z10.VnS());
+    temps.Include(ZRegister(12), ZRegister(13, kHRegSize), z14);
+    temps.Include(CPURegList(z16, z17, z18));
+    helper.RecordActionsAndCheck(0x77700);
+    // Including a register again has no effect.
+    temps.Include(ZRegister(18));
+    temps.Include(ZRegister(17, kFormatVnB));
+    temps.Include(CPURegister(z16));
+    temps.Include(CPURegister(z13.VnD()));
+    temps.Include(z12, z10, z9.VnB(), z8);
+    temps.Include(CPURegList(z5, z4, z3, z2));
+    helper.RecordActionsAndCheck(0x77700);
+  }
+}
+
+TEST(scratch_scope_exclude_z) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kExclude,
+                              CPURegister::kZRegister);
+
+    // Any suitable register type deriving from CPURegister can be excluded.
+    temps.Exclude(z0);
+    temps.Exclude(z1.VnB());
+    temps.Exclude(ZRegister(2));
+    temps.Exclude(ZRegister(3, kFormatVnD));
+    temps.Exclude(CPURegister(z4));
+    temps.Exclude(CPURegister(z5.VnH()));
+    helper.RecordActionsAndCheck(0x3f);
+    // Multiple registers can be excluded at once.
+    temps.Exclude(z8, z9, z10.VnS());
+    temps.Exclude(ZRegister(12), ZRegister(13, kHRegSize), z14);
+    temps.Exclude(CPURegList(z16, z17, z18));
+    helper.RecordActionsAndCheck(0x77700);
+    // Exluding a register again has no effect.
+    temps.Exclude(ZRegister(18));
+    temps.Exclude(ZRegister(17, kFormatVnB));
+    temps.Exclude(CPURegister(z16));
+    temps.Exclude(CPURegister(z13.VnD()));
+    temps.Exclude(z12, z10, z9.VnB(), z8);
+    temps.Exclude(CPURegList(z5, z4, z3, z2));
+    helper.RecordActionsAndCheck(0x77700);
+  }
+}
+
+TEST(scratch_scope_release_z) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kRelease,
+                              CPURegister::kZRegister);
+
+    // Any suitable register type deriving from CPURegister can be released.
+    temps.Release(z0);
+    temps.Release(z1.VnB());
+    temps.Release(ZRegister(2));
+    temps.Release(ZRegister(3, kFormatVnD));
+    temps.Release(CPURegister(z4));
+    temps.Release(CPURegister(z5.VnH()));
+    helper.RecordActionsAndCheck(0x3f);
+    // It is not possible to release more than one register at a time, and it is
+    // invalid to release a register that is already available.
+  }
+}
+
+TEST(scratch_scope_include_p) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kInclude,
+                              CPURegister::kPRegister);
+
+    // Any suitable register type deriving from CPURegister can be included.
+    temps.Include(p0);
+    temps.Include(PRegister(1));
+    temps.Include(PRegisterWithLaneSize(2, kFormatVnD));
+    temps.Include(PRegisterM(3));
+    temps.Include(CPURegister(PRegister(4)));
+    temps.Include(CPURegister(PRegisterZ(5)));
+    helper.RecordActionsAndCheck(0x3f);
+    // Multiple registers can be included at once.
+    temps.Include(p7, p8.Merging(), p9.VnS());
+    temps.Include(PRegister(11), PRegisterWithLaneSize(12, kHRegSize));
+    temps.Include(CPURegList(p15));
+    helper.RecordActionsAndCheck(0x9b80);
+    // Including a register again has no effect.
+    temps.Include(PRegister(15));
+    temps.Include(PRegisterWithLaneSize(12, kFormatVnB));
+    temps.Include(CPURegister(p11));
+    temps.Include(CPURegister(p9.VnD()));
+    temps.Include(p8.Merging(), p7.Zeroing(), p5.VnB(), p4);
+    temps.Include(CPURegList(p3, p2, p1, p0));
+    helper.RecordActionsAndCheck(0x9b80);
+  }
+}
+
+TEST(scratch_scope_exclude_p) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kExclude,
+                              CPURegister::kPRegister);
+
+    // Any suitable register type deriving from CPURegister can be excluded.
+    temps.Exclude(p0);
+    temps.Exclude(PRegister(1));
+    temps.Exclude(PRegisterWithLaneSize(2, kFormatVnD));
+    temps.Exclude(PRegisterM(3));
+    temps.Exclude(CPURegister(PRegister(4)));
+    temps.Exclude(CPURegister(PRegisterZ(5)));
+    helper.RecordActionsAndCheck(0x3f);
+    // Multiple registers can be excluded at once.
+    temps.Exclude(p7, p8.Merging(), p9.VnS());
+    temps.Exclude(PRegister(11), PRegisterWithLaneSize(12, kHRegSize));
+    temps.Exclude(CPURegList(p15));
+    helper.RecordActionsAndCheck(0x9b80);
+    // Excluding a register again has no effect.
+    temps.Exclude(PRegister(15));
+    temps.Exclude(PRegisterWithLaneSize(12, kFormatVnB));
+    temps.Exclude(CPURegister(p11));
+    temps.Exclude(CPURegister(p9.VnD()));
+    temps.Exclude(p8.Merging(), p7.Zeroing(), p5.VnB(), p4);
+    temps.Exclude(CPURegList(p3, p2, p1, p0));
+    helper.RecordActionsAndCheck(0x9b80);
+  }
+}
+
+TEST(scratch_scope_release_p) {
+  MacroAssembler masm;
+  {
+    UseScratchRegisterScope temps(&masm);
+    ScratchScopeHelper helper(&masm,
+                              ScratchScopeHelper::kRelease,
+                              CPURegister::kPRegister);
+
+    // Any suitable register type deriving from CPURegister can be excluded.
+    temps.Release(p0);
+    temps.Release(PRegister(1));
+    temps.Release(PRegisterWithLaneSize(2, kFormatVnD));
+    temps.Release(PRegisterM(3));
+    temps.Release(CPURegister(PRegister(4)));
+    temps.Release(CPURegister(PRegisterZ(5)));
+    helper.RecordActionsAndCheck(0x3f);
+    // It is not possible to release more than one register at a time, and it is
+    // invalid to release a register that is already available.
+  }
+}
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+TEST(sim_stack_default) {
+  SimStack::Allocated s = SimStack().Allocate();
+
+  // The default stack is at least 16-byte aligned.
+  VIXL_CHECK(IsAligned<16>(s.GetBase()));
+  VIXL_CHECK(IsAligned<16>(s.GetLimit() + 1));
+
+  VIXL_CHECK(s.GetBase() > s.GetLimit());
+
+  // The default guard regions are sufficient to detect at least off-by-one
+  // errors.
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetBase(), 1));
+  VIXL_CHECK(!s.IsAccessInGuardRegion(s.GetBase() - 1, 1));
+  // The limit is one below the lowest address on the stack.
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetLimit(), 1));
+  VIXL_CHECK(!s.IsAccessInGuardRegion(s.GetLimit() + 1, 1));
+
+  // We need to be able to access 16-byte granules at both extremes.
+  VIXL_CHECK(!s.IsAccessInGuardRegion(s.GetBase() - 16, 16));
+  VIXL_CHECK(!s.IsAccessInGuardRegion(s.GetLimit() + 1, 16));
+}
+
+TEST(sim_stack) {
+  SimStack builder;
+  builder.AlignToBytesLog2(WhichPowerOf2(1024));
+  builder.SetBaseGuardSize(42);
+  builder.SetLimitGuardSize(2049);
+  builder.SetUsableSize(2048);
+  SimStack::Allocated s = builder.Allocate();
+
+  VIXL_CHECK(IsAligned<1024>(s.GetBase()));
+  VIXL_CHECK(IsAligned<1024>(s.GetLimit() + 1));
+
+  // The stack is accessible for (limit, base), both exclusive.
+  // This is checked precisely, using the base and limit modified to respect
+  // alignment, so we can test the exact boundary condition.
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetBase(), 1));
+  VIXL_CHECK(!s.IsAccessInGuardRegion(s.GetBase() - 1, 1));
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetLimit(), 1));
+  VIXL_CHECK(!s.IsAccessInGuardRegion(s.GetLimit() + 1, 1));
+  VIXL_CHECK((s.GetBase() - s.GetLimit() - 1) == 2048);
+
+  // We can access the whole range (limit, base), both exclusive.
+  VIXL_CHECK(!s.IsAccessInGuardRegion(s.GetLimit() + 1, 2048));
+  // Off-by-one.
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetLimit(), 2048));
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetLimit() + 1, 2049));
+  // Accesses spanning whole guard regions.
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetBase() - 42, 4096));
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetLimit() - 1280, 2048));
+  VIXL_CHECK(s.IsAccessInGuardRegion(s.GetLimit() - 1280, 10000));
+}
+#endif
+
 }  // namespace aarch64
 }  // namespace vixl
diff --git a/test/aarch64/test-api-movprfx-aarch64.cc b/test/aarch64/test-api-movprfx-aarch64.cc
new file mode 100644
index 00000000..1c1bceec
--- /dev/null
+++ b/test/aarch64/test-api-movprfx-aarch64.cc
@@ -0,0 +1,1859 @@
+// Copyright 2017, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include <cstdio>
+#include <cstring>
+#include <string>
+
+#include "test-runner.h"
+#include "test-utils.h"
+#include "aarch64/test-utils-aarch64.h"
+
+#include "aarch64/assembler-aarch64.h"
+#include "aarch64/instructions-aarch64.h"
+
+#define __ assm.
+#define TEST(name) TEST_(AARCH64_API_##name)
+
+namespace vixl {
+namespace aarch64 {
+
+static void CheckAndMaybeDisassembleMovprfxPairs(const CodeBuffer* buffer,
+                                                 bool can_take_movprfx) {
+  const Instruction* pair = buffer->GetStartAddress<Instruction*>();
+  const Instruction* end = buffer->GetEndAddress<Instruction*>();
+  bool any_failures = false;
+  PrintDisassembler print_disasm(stdout);
+  while (pair < end) {
+    const Instruction* movprfx = pair;
+    const Instruction* candidate = pair->GetNextInstruction();
+    const Instruction* next_pair = candidate->GetNextInstruction();
+    VIXL_ASSERT(candidate < end);
+
+    bool failed = can_take_movprfx != candidate->CanTakeSVEMovprfx(movprfx);
+    any_failures = any_failures || failed;
+
+    if (failed || Test::disassemble()) {
+      printf("----\n");
+      if (failed) {
+        printf("# ERROR: Expected %sCanTakeSVEMovprfx(movprfx):\n",
+               can_take_movprfx ? "" : "!");
+      }
+      print_disasm.DisassembleBuffer(pair, next_pair);
+    }
+
+    pair = next_pair;
+  }
+  // Abort only at the end, so we can see the individual failures.
+  VIXL_CHECK(!any_failures);
+}
+
+TEST(movprfx_negative_aliasing) {
+  // Test that CanTakeSVEMovprfx() checks that the movprfx destination does not
+  // alias an input to the prefixed instruction.
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 73;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z0.VnB(), p0.Merging(), z9.VnB());
+    __ abs(z0.VnB(), p0.Merging(), z0.VnB());
+
+    __ movprfx(z1, z17);
+    __ add(z1.VnH(), p2.Merging(), z1.VnH(), z1.VnH());
+
+    __ movprfx(z12, z13);
+    __ and_(z12.VnD(), p5.Merging(), z12.VnD(), z12.VnD());
+
+    __ movprfx(z2, z4);
+    __ asr(z2.VnS(), p2.Merging(), z2.VnS(), z2.VnS());
+
+    __ movprfx(z10, z18);
+    __ asr(z10.VnH(), p2.Merging(), z10.VnH(), z10.VnD());
+
+    __ movprfx(z17.VnD(), p5.Zeroing(), z20.VnD());
+    __ asr(z17.VnD(), p5.Merging(), z17.VnD(), z17.VnD());
+
+    __ movprfx(z22, z9);
+    __ asrr(z22.VnH(), p1.Merging(), z22.VnH(), z22.VnH());
+
+    __ movprfx(z0.VnS(), p6.Zeroing(), z6.VnS());
+    __ bic(z0.VnS(), p6.Merging(), z0.VnS(), z0.VnS());
+
+    __ movprfx(z12, z16);
+    __ clasta(z12.VnD(), p5, z12.VnD(), z12.VnD());
+
+    __ movprfx(z7, z15);
+    __ clastb(z7.VnS(), p7, z7.VnS(), z7.VnS());
+
+    __ movprfx(z10, z29);
+    __ cls(z10.VnH(), p2.Merging(), z10.VnH());
+
+    __ movprfx(z6, z13);
+    __ clz(z6.VnB(), p4.Merging(), z6.VnB());
+
+    __ movprfx(z14.VnS(), p6.Zeroing(), z3.VnS());
+    __ cnot(z14.VnS(), p6.Merging(), z14.VnS());
+
+    __ movprfx(z5.VnD(), p6.Merging(), z4.VnD());
+    __ cnt(z5.VnD(), p6.Merging(), z5.VnD());
+
+    __ movprfx(z19.VnB(), p6.Zeroing(), z4.VnB());
+    __ eor(z19.VnB(), p6.Merging(), z19.VnB(), z19.VnB());
+
+    __ movprfx(z27, z2);
+    __ ext(z27.VnB(), z27.VnB(), z27.VnB(), 42);
+
+    __ movprfx(z4.VnS(), p1.Zeroing(), z22.VnS());
+    __ lsl(z4.VnS(), p1.Merging(), z4.VnS(), z4.VnS());
+
+    __ movprfx(z4, z5);
+    __ lsl(z4.VnB(), p5.Merging(), z4.VnB(), z4.VnD());
+
+    __ movprfx(z11.VnD(), p4.Merging(), z29.VnD());
+    __ lsl(z11.VnD(), p4.Merging(), z11.VnD(), z11.VnD());
+
+    __ movprfx(z12.VnD(), p6.Merging(), z3.VnD());
+    __ lslr(z12.VnD(), p6.Merging(), z12.VnD(), z12.VnD());
+
+    __ movprfx(z7, z2);
+    __ lsr(z7.VnB(), p4.Merging(), z7.VnB(), z7.VnB());
+
+    __ movprfx(z25.VnH(), p6.Merging(), z28.VnH());
+    __ lsr(z25.VnH(), p6.Merging(), z25.VnH(), z25.VnD());
+
+    __ movprfx(z14.VnD(), p6.Merging(), z6.VnD());
+    __ lsr(z14.VnD(), p6.Merging(), z14.VnD(), z14.VnD());
+
+    __ movprfx(z26.VnH(), p6.Zeroing(), z27.VnH());
+    __ lsrr(z26.VnH(), p6.Merging(), z26.VnH(), z26.VnH());
+
+    __ movprfx(z17.VnS(), p4.Zeroing(), z29.VnS());
+    __ mad(z17.VnS(), p4.Merging(), z17.VnS(), z23.VnS());
+
+    __ movprfx(z7, z17);
+    __ mad(z7.VnD(), p5.Merging(), z4.VnD(), z7.VnD());
+
+    __ movprfx(z11, z7);
+    __ mla(z11.VnS(), p1.Merging(), z11.VnS(), z27.VnS());
+
+    __ movprfx(z7, z5);
+    __ mla(z7.VnH(), p0.Merging(), z5.VnH(), z7.VnH());
+
+    __ movprfx(z1.VnH(), p0.Merging(), z17.VnH());
+    __ mls(z1.VnH(), p0.Merging(), z1.VnH(), z31.VnH());
+
+    __ movprfx(z22.VnB(), p3.Merging(), z18.VnB());
+    __ mls(z22.VnB(), p3.Merging(), z18.VnB(), z22.VnB());
+
+    __ movprfx(z7.VnS(), p0.Merging(), z10.VnS());
+    __ msb(z7.VnS(), p0.Merging(), z7.VnS(), z10.VnS());
+
+    __ movprfx(z12, z6);
+    __ msb(z12.VnH(), p7.Merging(), z6.VnH(), z12.VnH());
+
+    __ movprfx(z8.VnB(), p4.Merging(), z3.VnB());
+    __ mul(z8.VnB(), p4.Merging(), z8.VnB(), z8.VnB());
+
+    __ movprfx(z9, z26);
+    __ neg(z9.VnS(), p7.Merging(), z9.VnS());
+
+    __ movprfx(z16, z8);
+    __ not_(z16.VnH(), p6.Merging(), z16.VnH());
+
+    __ movprfx(z25.VnH(), p5.Zeroing(), z11.VnH());
+    __ orr(z25.VnH(), p5.Merging(), z25.VnH(), z25.VnH());
+
+    __ movprfx(z17.VnH(), p1.Merging(), z22.VnH());
+    __ rbit(z17.VnH(), p1.Merging(), z17.VnH());
+
+    __ movprfx(z11, z25);
+    __ revb(z11.VnD(), p6.Merging(), z11.VnD());
+
+    __ movprfx(z13, z27);
+    __ revh(z13.VnS(), p2.Merging(), z13.VnS());
+
+    __ movprfx(z30.VnD(), p6.Merging(), z20.VnD());
+    __ revw(z30.VnD(), p6.Merging(), z30.VnD());
+
+    __ movprfx(z2.VnD(), p2.Merging(), z21.VnD());
+    __ sabd(z2.VnD(), p2.Merging(), z2.VnD(), z2.VnD());
+
+    __ movprfx(z0, z7);
+    __ sdiv(z0.VnD(), p0.Merging(), z0.VnD(), z0.VnD());
+
+    __ movprfx(z19, z28);
+    __ sdivr(z19.VnS(), p1.Merging(), z19.VnS(), z19.VnS());
+
+    __ movprfx(z5, z18);
+    __ sdot(z5.VnS(), z18.VnB(), z5.VnB(), 1);
+
+    __ movprfx(z15, z11);
+    __ sdot(z15.VnD(), z2.VnH(), z15.VnH(), 1);
+
+    __ movprfx(z30, z13);
+    __ sdot(z30.VnD(), z30.VnH(), z13.VnH(), 1);
+
+    __ movprfx(z8, z9);
+    __ sdot(z8.VnS(), z8.VnB(), z9.VnB());
+
+    __ movprfx(z23, z14);
+    __ sdot(z23.VnS(), z14.VnB(), z23.VnB());
+
+    __ movprfx(z26, z5);
+    __ sdot(z26.VnS(), z26.VnB(), z5.VnB(), 1);
+
+    __ movprfx(z14, z15);
+    __ smax(z14.VnB(), p2.Merging(), z14.VnB(), z14.VnB());
+
+    __ movprfx(z26.VnS(), p0.Merging(), z10.VnS());
+    __ smin(z26.VnS(), p0.Merging(), z26.VnS(), z26.VnS());
+
+    __ movprfx(z22, z18);
+    __ smulh(z22.VnB(), p2.Merging(), z22.VnB(), z22.VnB());
+
+    __ movprfx(z8, z19);
+    __ splice(z8.VnD(), p2, z8.VnD(), z8.VnD());
+
+    __ movprfx(z23.VnH(), p6.Zeroing(), z2.VnH());
+    __ sub(z23.VnH(), p6.Merging(), z23.VnH(), z23.VnH());
+
+    __ movprfx(z25.VnS(), p2.Merging(), z21.VnS());
+    __ subr(z25.VnS(), p2.Merging(), z25.VnS(), z25.VnS());
+
+    __ movprfx(z28, z31);
+    __ sxtb(z28.VnS(), p6.Merging(), z28.VnS());
+
+    __ movprfx(z14.VnD(), p6.Merging(), z17.VnD());
+    __ sxth(z14.VnD(), p6.Merging(), z14.VnD());
+
+    __ movprfx(z21.VnD(), p0.Zeroing(), z28.VnD());
+    __ sxtw(z21.VnD(), p0.Merging(), z21.VnD());
+
+    __ movprfx(z25, z30);
+    __ uabd(z25.VnB(), p5.Merging(), z25.VnB(), z25.VnB());
+
+    __ movprfx(z13.VnD(), p2.Merging(), z30.VnD());
+    __ udiv(z13.VnD(), p2.Merging(), z13.VnD(), z13.VnD());
+
+    __ movprfx(z19.VnD(), p4.Zeroing(), z6.VnD());
+    __ udivr(z19.VnD(), p4.Merging(), z19.VnD(), z19.VnD());
+
+    __ movprfx(z1, z20);
+    __ udot(z1.VnS(), z18.VnB(), z1.VnB(), 1);
+
+    __ movprfx(z8, z2);
+    __ udot(z8.VnD(), z2.VnH(), z8.VnH(), 1);
+
+    __ movprfx(z28, z10);
+    __ udot(z28.VnD(), z28.VnH(), z7.VnH(), 1);
+
+    __ movprfx(z21, z11);
+    __ udot(z21.VnD(), z21.VnH(), z11.VnH());
+
+    __ movprfx(z1, z22);
+    __ udot(z1.VnD(), z10.VnH(), z1.VnH());
+
+    __ movprfx(z8, z23);
+    __ udot(z8.VnS(), z8.VnB(), z0.VnB(), 1);
+
+    __ movprfx(z10.VnB(), p5.Zeroing(), z0.VnB());
+    __ umax(z10.VnB(), p5.Merging(), z10.VnB(), z10.VnB());
+
+    __ movprfx(z0.VnS(), p2.Zeroing(), z30.VnS());
+    __ umin(z0.VnS(), p2.Merging(), z0.VnS(), z0.VnS());
+
+    __ movprfx(z26.VnD(), p6.Zeroing(), z29.VnD());
+    __ umulh(z26.VnD(), p6.Merging(), z26.VnD(), z26.VnD());
+
+    __ movprfx(z23, z25);
+    __ uxtb(z23.VnS(), p7.Merging(), z23.VnS());
+
+    __ movprfx(z14.VnS(), p3.Zeroing(), z5.VnS());
+    __ uxth(z14.VnS(), p3.Merging(), z14.VnS());
+
+    __ movprfx(z14, z5);
+    __ uxtw(z14.VnD(), p3.Merging(), z14.VnD());
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), false);
+}
+
+TEST(movprfx_negative_aliasing_fp) {
+  // Test that CanTakeSVEMovprfx() checks that the movprfx destination does not
+  // alias an input to the prefixed instruction.
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 78;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z17.VnS(), p1.Zeroing(), z12.VnS());
+    __ fabd(z17.VnS(), p1.Merging(), z17.VnS(), z17.VnS());
+
+    __ movprfx(z13, z23);
+    __ fabs(z13.VnS(), p4.Merging(), z13.VnS());
+
+    __ movprfx(z24.VnS(), p5.Merging(), z15.VnS());
+    __ fadd(z24.VnS(), p5.Merging(), z24.VnS(), z24.VnS());
+
+    __ movprfx(z28.VnD(), p5.Zeroing(), z14.VnD());
+    __ fcadd(z28.VnD(), p5.Merging(), z28.VnD(), z28.VnD(), 90);
+
+    __ movprfx(z5, z0);
+    __ fcmla(z5.VnH(), z0.VnH(), z5.VnH(), 2, 180);
+
+    __ movprfx(z10, z4);
+    __ fcmla(z10.VnS(), z8.VnS(), z10.VnS(), 1, 270);
+
+    __ movprfx(z12, z26);
+    __ fcmla(z12.VnH(), z12.VnH(), z3.VnH(), 2, 180);
+
+    __ movprfx(z8, z1);
+    __ fcmla(z8.VnS(), z8.VnS(), z1.VnS(), 1, 270);
+
+    __ movprfx(z16.VnD(), p0.Merging(), z13.VnD());
+    __ fcvt(z16.VnD(), p0.Merging(), z16.VnH());
+
+    __ movprfx(z12.VnD(), p7.Zeroing(), z13.VnD());
+    __ fcvt(z12.VnD(), p7.Merging(), z12.VnS());
+
+    __ movprfx(z14, z26);
+    __ fcvt(z14.VnS(), p5.Merging(), z14.VnD());
+
+    __ movprfx(z26, z2);
+    __ fcvt(z26.VnH(), p7.Merging(), z26.VnD());
+
+    __ movprfx(z25.VnD(), p2.Merging(), z13.VnD());
+    __ fcvtzs(z25.VnD(), p2.Merging(), z25.VnH());
+
+    __ movprfx(z31, z2);
+    __ fcvtzs(z31.VnH(), p7.Merging(), z31.VnH());
+
+    __ movprfx(z21.VnD(), p1.Merging(), z7.VnD());
+    __ fcvtzs(z21.VnD(), p1.Merging(), z21.VnS());
+
+    __ movprfx(z5, z17);
+    __ fcvtzs(z5.VnS(), p5.Merging(), z5.VnD());
+
+    __ movprfx(z19.VnD(), p1.Zeroing(), z16.VnD());
+    __ fcvtzu(z19.VnD(), p1.Merging(), z19.VnH());
+
+    __ movprfx(z2.VnH(), p7.Zeroing(), z28.VnH());
+    __ fcvtzu(z2.VnH(), p7.Merging(), z2.VnH());
+
+    __ movprfx(z21.VnD(), p7.Zeroing(), z27.VnD());
+    __ fcvtzu(z21.VnD(), p7.Merging(), z21.VnS());
+
+    __ movprfx(z22.VnD(), p4.Zeroing(), z8.VnD());
+    __ fcvtzu(z22.VnS(), p4.Merging(), z22.VnD());
+
+    __ movprfx(z0.VnS(), p5.Merging(), z5.VnS());
+    __ fdiv(z0.VnS(), p5.Merging(), z0.VnS(), z0.VnS());
+
+    __ movprfx(z12, z24);
+    __ fdivr(z12.VnD(), p7.Merging(), z12.VnD(), z12.VnD());
+
+    __ movprfx(z14.VnD(), p6.Zeroing(), z21.VnD());
+    __ fmad(z14.VnD(), p6.Merging(), z14.VnD(), z3.VnD());
+
+    __ movprfx(z2.VnS(), p5.Zeroing(), z10.VnS());
+    __ fmad(z2.VnS(), p5.Merging(), z14.VnS(), z2.VnS());
+
+    __ movprfx(z24, z5);
+    __ fmax(z24.VnS(), p1.Merging(), z24.VnS(), z24.VnS());
+
+    __ movprfx(z15.VnD(), p2.Merging(), z26.VnD());
+    __ fmaxnm(z15.VnD(), p2.Merging(), z15.VnD(), z15.VnD());
+
+    __ movprfx(z20, z22);
+    __ fmin(z20.VnH(), p0.Merging(), z20.VnH(), z20.VnH());
+
+    __ movprfx(z24.VnS(), p6.Zeroing(), z30.VnS());
+    __ fminnm(z24.VnS(), p6.Merging(), z24.VnS(), z24.VnS());
+
+    __ movprfx(z4, z24);
+    __ fmla(z4.VnH(), z24.VnH(), z4.VnH(), 7);
+
+    __ movprfx(z4, z7);
+    __ fmla(z4.VnS(), z24.VnS(), z4.VnS(), 3);
+
+    __ movprfx(z5, z28);
+    __ fmla(z5.VnD(), z28.VnD(), z5.VnD(), 1);
+
+    __ movprfx(z24, z2);
+    __ fmla(z24.VnD(), z24.VnD(), z2.VnD(), 1);
+
+    __ movprfx(z7, z21);
+    __ fmla(z7.VnH(), p2.Merging(), z7.VnH(), z31.VnH());
+
+    __ movprfx(z25.VnH(), p5.Zeroing(), z29.VnH());
+    __ fmla(z25.VnH(), p5.Merging(), z29.VnH(), z25.VnH());
+
+    __ movprfx(z31, z25);
+    __ fmla(z31.VnH(), z31.VnH(), z2.VnH(), 7);
+
+    __ movprfx(z15, z4);
+    __ fmla(z15.VnS(), z15.VnS(), z4.VnS(), 3);
+
+    __ movprfx(z7, z11);
+    __ fmls(z7.VnH(), z11.VnH(), z7.VnH(), 4);
+
+    __ movprfx(z3, z10);
+    __ fmls(z3.VnS(), z10.VnS(), z3.VnS(), 3);
+
+    __ movprfx(z5, z16);
+    __ fmls(z5.VnD(), z16.VnD(), z5.VnD(), 1);
+
+    __ movprfx(z31, z26);
+    __ fmls(z31.VnD(), z31.VnD(), z8.VnD(), 1);
+
+    __ movprfx(z5.VnH(), p3.Merging(), z2.VnH());
+    __ fmls(z5.VnH(), p3.Merging(), z5.VnH(), z2.VnH());
+
+    __ movprfx(z22.VnS(), p3.Zeroing(), z17.VnS());
+    __ fmls(z22.VnS(), p3.Merging(), z21.VnS(), z22.VnS());
+
+    __ movprfx(z17, z2);
+    __ fmls(z17.VnH(), z17.VnH(), z2.VnH(), 4);
+
+    __ movprfx(z28, z11);
+    __ fmls(z28.VnS(), z28.VnS(), z0.VnS(), 3);
+
+    __ movprfx(z15.VnD(), p1.Merging(), z31.VnD());
+    __ fmsb(z15.VnD(), p1.Merging(), z15.VnD(), z31.VnD());
+
+    __ movprfx(z21.VnD(), p0.Zeroing(), z5.VnD());
+    __ fmsb(z21.VnD(), p0.Merging(), z19.VnD(), z21.VnD());
+
+    __ movprfx(z0.VnH(), p3.Merging(), z31.VnH());
+    __ fmul(z0.VnH(), p3.Merging(), z0.VnH(), z0.VnH());
+
+    __ movprfx(z31.VnH(), p6.Merging(), z8.VnH());
+    __ fmulx(z31.VnH(), p6.Merging(), z31.VnH(), z31.VnH());
+
+    __ movprfx(z17.VnH(), p1.Zeroing(), z10.VnH());
+    __ fneg(z17.VnH(), p1.Merging(), z17.VnH());
+
+    __ movprfx(z22, z31);
+    __ fnmad(z22.VnH(), p1.Merging(), z22.VnH(), z23.VnH());
+
+    __ movprfx(z14.VnD(), p0.Zeroing(), z26.VnD());
+    __ fnmad(z14.VnD(), p0.Merging(), z2.VnD(), z14.VnD());
+
+    __ movprfx(z13.VnH(), p6.Zeroing(), z29.VnH());
+    __ fnmla(z13.VnH(), p6.Merging(), z13.VnH(), z26.VnH());
+
+    __ movprfx(z19.VnH(), p7.Zeroing(), z25.VnH());
+    __ fnmla(z19.VnH(), p7.Merging(), z25.VnH(), z19.VnH());
+
+    __ movprfx(z27.VnH(), p5.Merging(), z24.VnH());
+    __ fnmls(z27.VnH(), p5.Merging(), z27.VnH(), z24.VnH());
+
+    __ movprfx(z6.VnH(), p6.Zeroing(), z21.VnH());
+    __ fnmls(z6.VnH(), p6.Merging(), z21.VnH(), z6.VnH());
+
+    __ movprfx(z7.VnS(), p3.Merging(), z23.VnS());
+    __ fnmsb(z7.VnS(), p3.Merging(), z7.VnS(), z23.VnS());
+
+    __ movprfx(z29.VnH(), p2.Zeroing(), z24.VnH());
+    __ fnmsb(z29.VnH(), p2.Merging(), z24.VnH(), z29.VnH());
+
+    __ movprfx(z7.VnH(), p6.Merging(), z23.VnH());
+    __ frecpx(z7.VnH(), p6.Merging(), z7.VnH());
+
+    __ movprfx(z17.VnS(), p5.Zeroing(), z2.VnS());
+    __ frinta(z17.VnS(), p5.Merging(), z17.VnS());
+
+    __ movprfx(z0.VnS(), p2.Zeroing(), z7.VnS());
+    __ frinti(z0.VnS(), p2.Merging(), z0.VnS());
+
+    __ movprfx(z8.VnH(), p3.Merging(), z20.VnH());
+    __ frintm(z8.VnH(), p3.Merging(), z8.VnH());
+
+    __ movprfx(z3.VnD(), p2.Zeroing(), z20.VnD());
+    __ frintn(z3.VnD(), p2.Merging(), z3.VnD());
+
+    __ movprfx(z11, z3);
+    __ frintp(z11.VnS(), p4.Merging(), z11.VnS());
+
+    __ movprfx(z23, z29);
+    __ frintx(z23.VnD(), p4.Merging(), z23.VnD());
+
+    __ movprfx(z4.VnH(), p4.Zeroing(), z14.VnH());
+    __ frintz(z4.VnH(), p4.Merging(), z4.VnH());
+
+    __ movprfx(z18.VnH(), p3.Zeroing(), z0.VnH());
+    __ fscale(z18.VnH(), p3.Merging(), z18.VnH(), z18.VnH());
+
+    __ movprfx(z2.VnS(), p6.Zeroing(), z4.VnS());
+    __ fsqrt(z2.VnS(), p6.Merging(), z2.VnS());
+
+    __ movprfx(z14.VnD(), p4.Zeroing(), z31.VnD());
+    __ fsub(z14.VnD(), p4.Merging(), z14.VnD(), z14.VnD());
+
+    __ movprfx(z31.VnH(), p2.Merging(), z6.VnH());
+    __ fsubr(z31.VnH(), p2.Merging(), z31.VnH(), z31.VnH());
+
+    __ movprfx(z4, z30);
+    __ ftmad(z4.VnH(), z4.VnH(), z4.VnH(), 2);
+
+    __ movprfx(z25.VnD(), p6.Zeroing(), z2.VnD());
+    __ scvtf(z25.VnD(), p6.Merging(), z25.VnS());
+
+    __ movprfx(z0.VnD(), p3.Merging(), z16.VnD());
+    __ scvtf(z0.VnD(), p3.Merging(), z0.VnD());
+
+    __ movprfx(z19, z23);
+    __ scvtf(z19.VnS(), p7.Merging(), z19.VnD());
+
+    __ movprfx(z19, z4);
+    __ scvtf(z19.VnH(), p4.Merging(), z19.VnD());
+
+    __ movprfx(z13.VnD(), p4.Zeroing(), z6.VnD());
+    __ ucvtf(z13.VnD(), p4.Merging(), z13.VnS());
+
+    __ movprfx(z6.VnH(), p0.Zeroing(), z14.VnH());
+    __ ucvtf(z6.VnH(), p0.Merging(), z6.VnH());
+
+    __ movprfx(z19.VnS(), p4.Merging(), z12.VnS());
+    __ ucvtf(z19.VnH(), p4.Merging(), z19.VnS());
+
+    __ movprfx(z0.VnD(), p5.Zeroing(), z12.VnD());
+    __ ucvtf(z0.VnH(), p5.Merging(), z0.VnD());
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), false);
+}
+
+TEST(movprfx_negative_instructions) {
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 13;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z26, z11);
+    __ add(z26.VnB(), z11.VnB(), z4.VnB());
+
+    // The merging form can take movprfx, but the zeroing form cannot.
+    __ movprfx(z29.VnB(), p3.Zeroing(), z7.VnB());
+    __ cpy(z29.VnB(), p3.Zeroing(), -42);
+
+    // Frecpx can take movprfx, but frecpe and frecps cannot.
+    __ movprfx(z13, z15);
+    __ frecpe(z13.VnD(), z26.VnD());
+
+    __ movprfx(z19, z1);
+    __ frecps(z19.VnD(), z1.VnD(), z12.VnD());
+
+    __ movprfx(z6, z12);
+    __ frsqrte(z6.VnS(), z12.VnS());
+
+    __ movprfx(z29, z5);
+    __ frsqrts(z29.VnH(), z5.VnH(), z20.VnH());
+
+    // Ftmad can take movprfx, but ftsmul and ftssel cannot.
+    __ movprfx(z1, z31);
+    __ ftsmul(z1.VnD(), z31.VnD(), z16.VnD());
+
+    __ movprfx(z8, z27);
+    __ ftssel(z8.VnH(), z27.VnH(), z1.VnH());
+
+    // This looks like a merging unary operation, but it's actually an alias of
+    // sel, which isn't destructive.
+    __ movprfx(z0, z18);
+    __ mov(z0.VnS(), p6.Merging(), z18.VnS());
+
+    // The merging form can take movprfx, but the zeroing form cannot.
+    __ movprfx(z12.VnS(), p2.Merging(), z11.VnS());
+    __ mov(z12.VnS(), p2.Zeroing(), -42);
+
+    __ movprfx(z13, z6);
+    __ movprfx(z13, z2);
+
+    // Movprfx can never prefix itself.
+    __ movprfx(z3.VnD(), p5.Zeroing(), z8.VnD());
+    __ movprfx(z3.VnD(), p5.Merging(), z8.VnD());
+
+    __ movprfx(z1.VnD(), p3.Zeroing(), z14.VnD());
+    __ movprfx(z1.VnD(), p3.Zeroing(), z18.VnD());
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), false);
+}
+
+TEST(movprfx_negative_lane_size) {
+  // Test that CanTakeSVEMovprfx() checks that the (predicated) movprfx lane
+  // size is compatible with the prefixed instruction.
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 63;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z0.VnH(), p2.Zeroing(), z17.VnH());
+    __ abs(z0.VnS(), p2.Merging(), z17.VnS());
+
+    __ movprfx(z10.VnD(), p0.Zeroing(), z4.VnD());
+    __ add(z10.VnS(), p0.Merging(), z10.VnS(), z2.VnS());
+
+    __ movprfx(z25.VnS(), p4.Zeroing(), z26.VnS());
+    __ and_(z25.VnB(), p4.Merging(), z25.VnB(), z27.VnB());
+
+    __ movprfx(z26.VnD(), p5.Merging(), z23.VnD());
+    __ asr(z26.VnB(), p5.Merging(), z26.VnB(), 3);
+
+    __ movprfx(z25.VnS(), p7.Zeroing(), z14.VnS());
+    __ asr(z25.VnH(), p7.Merging(), z25.VnH(), z14.VnH());
+
+    __ movprfx(z12.VnS(), p7.Zeroing(), z23.VnS());
+    __ asr(z12.VnH(), p7.Merging(), z12.VnH(), z23.VnD());
+
+    __ movprfx(z3.VnH(), p4.Zeroing(), z18.VnH());
+    __ asr(z3.VnD(), p4.Merging(), z3.VnD(), z15.VnD());
+
+    __ movprfx(z29.VnH(), p4.Merging(), z31.VnH());
+    __ asrd(z29.VnB(), p4.Merging(), z29.VnB(), 3);
+
+    __ movprfx(z31.VnH(), p5.Zeroing(), z14.VnH());
+    __ asrr(z31.VnB(), p5.Merging(), z31.VnB(), z5.VnB());
+
+    __ movprfx(z0.VnS(), p6.Zeroing(), z18.VnS());
+    __ bic(z0.VnB(), p6.Merging(), z0.VnB(), z23.VnB());
+
+    __ movprfx(z19.VnH(), p2.Zeroing(), z24.VnH());
+    __ cls(z19.VnB(), p2.Merging(), z24.VnB());
+
+    __ movprfx(z14.VnS(), p5.Zeroing(), z4.VnS());
+    __ clz(z14.VnD(), p5.Merging(), z10.VnD());
+
+    __ movprfx(z0.VnD(), p5.Merging(), z2.VnD());
+    __ cnot(z0.VnH(), p5.Merging(), z2.VnH());
+
+    __ movprfx(z0.VnB(), p3.Zeroing(), z19.VnB());
+    __ cnt(z0.VnH(), p3.Merging(), z8.VnH());
+
+    __ movprfx(z29.VnS(), p0.Merging(), z7.VnS());
+    __ cpy(z29.VnD(), p0.Merging(), -42);
+
+    __ movprfx(z13.VnB(), p2.Merging(), z31.VnB());
+    __ cpy(z13.VnS(), p2.Merging(), w13);
+
+    __ movprfx(z0.VnS(), p3.Merging(), z15.VnS());
+    __ cpy(z0.VnH(), p3.Merging(), h0);
+
+    __ movprfx(z2.VnD(), p6.Zeroing(), z26.VnD());
+    __ eor(z2.VnB(), p6.Merging(), z2.VnB(), z26.VnB());
+
+    __ movprfx(z7.VnS(), p7.Zeroing(), z30.VnS());
+    __ lsl(z7.VnD(), p7.Merging(), z7.VnD(), 3);
+
+    __ movprfx(z11.VnH(), p3.Merging(), z23.VnH());
+    __ lsl(z11.VnB(), p3.Merging(), z11.VnB(), z21.VnB());
+
+    __ movprfx(z31.VnS(), p7.Zeroing(), z21.VnS());
+    __ lsl(z31.VnH(), p7.Merging(), z31.VnH(), z21.VnD());
+
+    __ movprfx(z26.VnH(), p0.Merging(), z0.VnH());
+    __ lsl(z26.VnD(), p0.Merging(), z26.VnD(), z24.VnD());
+
+    __ movprfx(z1.VnS(), p2.Zeroing(), z6.VnS());
+    __ lslr(z1.VnB(), p2.Merging(), z1.VnB(), z6.VnB());
+
+    __ movprfx(z4.VnD(), p4.Zeroing(), z6.VnD());
+    __ lsr(z4.VnH(), p4.Merging(), z4.VnH(), 3);
+
+    __ movprfx(z27.VnH(), p0.Zeroing(), z29.VnH());
+    __ lsr(z27.VnS(), p0.Merging(), z27.VnS(), z29.VnS());
+
+    __ movprfx(z5.VnD(), p2.Zeroing(), z16.VnD());
+    __ lsr(z5.VnH(), p2.Merging(), z5.VnH(), z2.VnD());
+
+    __ movprfx(z27.VnB(), p4.Zeroing(), z5.VnB());
+    __ lsr(z27.VnD(), p4.Merging(), z27.VnD(), z5.VnD());
+
+    __ movprfx(z27.VnS(), p3.Merging(), z13.VnS());
+    __ lsrr(z27.VnD(), p3.Merging(), z27.VnD(), z13.VnD());
+
+    __ movprfx(z30.VnS(), p2.Zeroing(), z14.VnS());
+    __ mad(z30.VnB(), p2.Merging(), z20.VnB(), z14.VnB());
+
+    __ movprfx(z14.VnB(), p6.Merging(), z11.VnB());
+    __ mla(z14.VnD(), p6.Merging(), z28.VnD(), z11.VnD());
+
+    __ movprfx(z28.VnH(), p2.Zeroing(), z22.VnH());
+    __ mls(z28.VnS(), p2.Merging(), z3.VnS(), z22.VnS());
+
+    // Aliases of cpy.
+    __ movprfx(z18.VnH(), p6.Zeroing(), z25.VnH());
+    __ mov(z18.VnD(), p6.Merging(), -42);
+
+    __ movprfx(z22.VnD(), p2.Zeroing(), z6.VnD());
+    __ mov(z22.VnS(), p2.Merging(), w22);
+
+    __ movprfx(z3.VnH(), p0.Zeroing(), z13.VnH());
+    __ mov(z3.VnB(), p0.Merging(), b0);
+
+    __ movprfx(z31.VnS(), p7.Zeroing(), z12.VnS());
+    __ msb(z31.VnH(), p7.Merging(), z14.VnH(), z12.VnH());
+
+    __ movprfx(z16.VnS(), p7.Zeroing(), z6.VnS());
+    __ mul(z16.VnB(), p7.Merging(), z16.VnB(), z30.VnB());
+
+    __ movprfx(z17.VnD(), p7.Merging(), z1.VnD());
+    __ neg(z17.VnB(), p7.Merging(), z1.VnB());
+
+    __ movprfx(z31.VnH(), p4.Zeroing(), z12.VnH());
+    __ not_(z31.VnB(), p4.Merging(), z12.VnB());
+
+    __ movprfx(z9.VnH(), p3.Zeroing(), z23.VnH());
+    __ orr(z9.VnS(), p3.Merging(), z9.VnS(), z13.VnS());
+
+    __ movprfx(z25.VnD(), p2.Zeroing(), z21.VnD());
+    __ rbit(z25.VnS(), p2.Merging(), z21.VnS());
+
+    __ movprfx(z26.VnH(), p3.Merging(), z13.VnH());
+    __ revb(z26.VnD(), p3.Merging(), z13.VnD());
+
+    __ movprfx(z8.VnH(), p5.Merging(), z20.VnH());
+    __ revh(z8.VnS(), p5.Merging(), z0.VnS());
+
+    __ movprfx(z22.VnH(), p6.Merging(), z15.VnH());
+    __ revw(z22.VnD(), p6.Merging(), z10.VnD());
+
+    __ movprfx(z1.VnD(), p3.Merging(), z15.VnD());
+    __ sabd(z1.VnB(), p3.Merging(), z1.VnB(), z15.VnB());
+
+    __ movprfx(z25.VnD(), p1.Zeroing(), z30.VnD());
+    __ sdiv(z25.VnS(), p1.Merging(), z25.VnS(), z30.VnS());
+
+    __ movprfx(z19.VnS(), p3.Zeroing(), z11.VnS());
+    __ sdivr(z19.VnD(), p3.Merging(), z19.VnD(), z24.VnD());
+
+    __ movprfx(z12.VnH(), p2.Merging(), z2.VnH());
+    __ smax(z12.VnS(), p2.Merging(), z12.VnS(), z24.VnS());
+
+    __ movprfx(z3.VnD(), p1.Merging(), z15.VnD());
+    __ smin(z3.VnS(), p1.Merging(), z3.VnS(), z20.VnS());
+
+    __ movprfx(z13.VnS(), p5.Merging(), z22.VnS());
+    __ smulh(z13.VnB(), p5.Merging(), z13.VnB(), z27.VnB());
+
+    __ movprfx(z11.VnH(), p5.Zeroing(), z25.VnH());
+    __ sub(z11.VnB(), p5.Merging(), z11.VnB(), z7.VnB());
+
+    __ movprfx(z3.VnB(), p6.Merging(), z13.VnB());
+    __ subr(z3.VnS(), p6.Merging(), z3.VnS(), z13.VnS());
+
+    __ movprfx(z26.VnH(), p5.Merging(), z1.VnH());
+    __ sxtb(z26.VnS(), p5.Merging(), z17.VnS());
+
+    __ movprfx(z11.VnB(), p7.Zeroing(), z26.VnB());
+    __ sxth(z11.VnS(), p7.Merging(), z26.VnS());
+
+    __ movprfx(z1.VnS(), p2.Merging(), z21.VnS());
+    __ sxtw(z1.VnD(), p2.Merging(), z21.VnD());
+
+    __ movprfx(z4.VnS(), p6.Zeroing(), z6.VnS());
+    __ uabd(z4.VnH(), p6.Merging(), z4.VnH(), z6.VnH());
+
+    __ movprfx(z26.VnB(), p2.Zeroing(), z11.VnB());
+    __ udiv(z26.VnD(), p2.Merging(), z26.VnD(), z11.VnD());
+
+    __ movprfx(z19.VnB(), p5.Merging(), z6.VnB());
+    __ udivr(z19.VnS(), p5.Merging(), z19.VnS(), z9.VnS());
+
+    __ movprfx(z16.VnB(), p4.Merging(), z6.VnB());
+    __ umax(z16.VnH(), p4.Merging(), z16.VnH(), z6.VnH());
+
+    __ movprfx(z1.VnD(), p0.Zeroing(), z4.VnD());
+    __ umin(z1.VnS(), p0.Merging(), z1.VnS(), z28.VnS());
+
+    __ movprfx(z25.VnD(), p7.Merging(), z4.VnD());
+    __ umulh(z25.VnB(), p7.Merging(), z25.VnB(), z16.VnB());
+
+    __ movprfx(z29.VnB(), p4.Merging(), z2.VnB());
+    __ uxtb(z29.VnS(), p4.Merging(), z31.VnS());
+
+    __ movprfx(z27.VnH(), p5.Merging(), z21.VnH());
+    __ uxth(z27.VnD(), p5.Merging(), z1.VnD());
+
+    __ movprfx(z29.VnB(), p2.Merging(), z7.VnB());
+    __ uxtw(z29.VnD(), p2.Merging(), z7.VnD());
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), false);
+}
+
+TEST(movprfx_negative_lane_size_fp) {
+  // Test that CanTakeSVEMovprfx() checks that the (predicated) movprfx lane
+  // size is compatible with the prefixed instruction.
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 64;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z29.VnD(), p5.Zeroing(), z8.VnD());
+    __ fabd(z29.VnS(), p5.Merging(), z29.VnS(), z26.VnS());
+
+    __ movprfx(z9.VnB(), p0.Zeroing(), z1.VnB());
+    __ fabs(z9.VnS(), p0.Merging(), z15.VnS());
+
+    __ movprfx(z24.VnD(), p0.Zeroing(), z8.VnD());
+    __ fadd(z24.VnH(), p0.Merging(), z24.VnH(), 0.5);
+
+    __ movprfx(z24.VnB(), p1.Zeroing(), z27.VnB());
+    __ fadd(z24.VnH(), p1.Merging(), z24.VnH(), z27.VnH());
+
+    __ movprfx(z14.VnH(), p7.Merging(), z12.VnH());
+    __ fcadd(z14.VnD(), p7.Merging(), z14.VnD(), z12.VnD(), 90);
+
+    __ movprfx(z10.VnB(), p6.Merging(), z11.VnB());
+    __ fcpy(z10.VnH(), p6.Merging(), 1.25);
+
+    __ movprfx(z12.VnB(), p6.Merging(), z18.VnB());
+    __ fcvt(z12.VnD(), p6.Merging(), z18.VnH());
+
+    __ movprfx(z18.VnH(), p7.Zeroing(), z2.VnH());
+    __ fcvt(z18.VnD(), p7.Merging(), z0.VnS());
+
+    __ movprfx(z3.VnH(), p5.Merging(), z14.VnH());
+    __ fcvt(z3.VnS(), p5.Merging(), z21.VnD());
+
+    __ movprfx(z15.VnH(), p1.Zeroing(), z12.VnH());
+    __ fcvt(z15.VnH(), p1.Merging(), z12.VnD());
+
+    __ movprfx(z3.VnH(), p2.Merging(), z22.VnH());
+    __ fcvtzs(z3.VnD(), p2.Merging(), z7.VnH());
+
+    __ movprfx(z17.VnS(), p3.Merging(), z14.VnS());
+    __ fcvtzs(z17.VnD(), p3.Merging(), z14.VnD());
+
+    __ movprfx(z2.VnH(), p1.Zeroing(), z16.VnH());
+    __ fcvtzs(z2.VnS(), p1.Merging(), z31.VnH());
+
+    __ movprfx(z13.VnB(), p2.Merging(), z9.VnB());
+    __ fcvtzs(z13.VnS(), p2.Merging(), z23.VnD());
+
+    __ movprfx(z19.VnB(), p1.Merging(), z4.VnB());
+    __ fcvtzu(z19.VnD(), p1.Merging(), z14.VnH());
+
+    __ movprfx(z29.VnS(), p2.Merging(), z19.VnS());
+    __ fcvtzu(z29.VnD(), p2.Merging(), z19.VnD());
+
+    __ movprfx(z21.VnS(), p4.Zeroing(), z17.VnS());
+    __ fcvtzu(z21.VnD(), p4.Merging(), z17.VnS());
+
+    __ movprfx(z19.VnH(), p4.Zeroing(), z30.VnH());
+    __ fcvtzu(z19.VnS(), p4.Merging(), z16.VnD());
+
+    __ movprfx(z10.VnS(), p7.Zeroing(), z27.VnS());
+    __ fdiv(z10.VnH(), p7.Merging(), z10.VnH(), z27.VnH());
+
+    __ movprfx(z7.VnD(), p7.Zeroing(), z17.VnD());
+    __ fdivr(z7.VnH(), p7.Merging(), z7.VnH(), z28.VnH());
+
+    __ movprfx(z22.VnB(), p0.Merging(), z27.VnB());
+    __ fmad(z22.VnH(), p0.Merging(), z27.VnH(), z15.VnH());
+
+    __ movprfx(z14.VnD(), p1.Zeroing(), z11.VnD());
+    __ fmax(z14.VnS(), p1.Merging(), z14.VnS(), 0.0);
+
+    __ movprfx(z27.VnB(), p5.Merging(), z14.VnB());
+    __ fmax(z27.VnD(), p5.Merging(), z27.VnD(), z14.VnD());
+
+    __ movprfx(z31.VnH(), p7.Merging(), z24.VnH());
+    __ fmaxnm(z31.VnD(), p7.Merging(), z31.VnD(), 0.0);
+
+    __ movprfx(z11.VnD(), p7.Zeroing(), z25.VnD());
+    __ fmaxnm(z11.VnS(), p7.Merging(), z11.VnS(), z28.VnS());
+
+    __ movprfx(z31.VnD(), p6.Merging(), z19.VnD());
+    __ fmin(z31.VnH(), p6.Merging(), z31.VnH(), 0.0);
+
+    __ movprfx(z20.VnS(), p3.Zeroing(), z15.VnS());
+    __ fmin(z20.VnH(), p3.Merging(), z20.VnH(), z8.VnH());
+
+    __ movprfx(z6.VnS(), p0.Merging(), z30.VnS());
+    __ fminnm(z6.VnH(), p0.Merging(), z6.VnH(), 0.0);
+
+    __ movprfx(z1.VnH(), p1.Zeroing(), z14.VnH());
+    __ fminnm(z1.VnS(), p1.Merging(), z1.VnS(), z14.VnS());
+
+    __ movprfx(z13.VnB(), p3.Zeroing(), z21.VnB());
+    __ fmla(z13.VnD(), p3.Merging(), z12.VnD(), z21.VnD());
+
+    __ movprfx(z15.VnS(), p1.Zeroing(), z20.VnS());
+    __ fmls(z15.VnH(), p1.Merging(), z28.VnH(), z20.VnH());
+
+    __ movprfx(z19.VnD(), p3.Zeroing(), z31.VnD());
+    __ fmov(z19.VnH(), p3.Merging(), 0.0);
+
+    __ movprfx(z16.VnS(), p7.Merging(), z30.VnS());
+    __ fmov(z16.VnH(), p7.Merging(), 2.5);
+
+    __ movprfx(z21.VnB(), p1.Merging(), z28.VnB());
+    __ fmsb(z21.VnH(), p1.Merging(), z30.VnH(), z28.VnH());
+
+    __ movprfx(z21.VnS(), p1.Zeroing(), z19.VnS());
+    __ fmul(z21.VnH(), p1.Merging(), z21.VnH(), 2.0);
+
+    __ movprfx(z28.VnB(), p7.Zeroing(), z8.VnB());
+    __ fmul(z28.VnS(), p7.Merging(), z28.VnS(), z26.VnS());
+
+    __ movprfx(z2.VnB(), p4.Merging(), z31.VnB());
+    __ fmulx(z2.VnH(), p4.Merging(), z2.VnH(), z31.VnH());
+
+    __ movprfx(z6.VnB(), p2.Zeroing(), z0.VnB());
+    __ fneg(z6.VnS(), p2.Merging(), z28.VnS());
+
+    __ movprfx(z26.VnB(), p0.Zeroing(), z21.VnB());
+    __ fnmad(z26.VnH(), p0.Merging(), z21.VnH(), z18.VnH());
+
+    __ movprfx(z15.VnB(), p1.Zeroing(), z26.VnB());
+    __ fnmla(z15.VnH(), p1.Merging(), z26.VnH(), z18.VnH());
+
+    __ movprfx(z16.VnS(), p0.Merging(), z1.VnS());
+    __ fnmls(z16.VnD(), p0.Merging(), z1.VnD(), z13.VnD());
+
+    __ movprfx(z4.VnH(), p0.Zeroing(), z16.VnH());
+    __ fnmsb(z4.VnS(), p0.Merging(), z30.VnS(), z3.VnS());
+
+    // Note that frecpe and frecps _cannot_ take movprfx.
+    __ movprfx(z9.VnH(), p0.Zeroing(), z21.VnH());
+    __ frecpx(z9.VnS(), p0.Merging(), z14.VnS());
+
+    __ movprfx(z6.VnH(), p2.Zeroing(), z28.VnH());
+    __ frinta(z6.VnD(), p2.Merging(), z28.VnD());
+
+    __ movprfx(z12.VnS(), p4.Zeroing(), z7.VnS());
+    __ frinti(z12.VnH(), p4.Merging(), z7.VnH());
+
+    __ movprfx(z6.VnB(), p5.Merging(), z20.VnB());
+    __ frintm(z6.VnD(), p5.Merging(), z20.VnD());
+
+    __ movprfx(z7.VnB(), p6.Merging(), z19.VnB());
+    __ frintn(z7.VnH(), p6.Merging(), z11.VnH());
+
+    __ movprfx(z12.VnD(), p2.Merging(), z31.VnD());
+    __ frintp(z12.VnS(), p2.Merging(), z31.VnS());
+
+    __ movprfx(z1.VnS(), p5.Merging(), z10.VnS());
+    __ frintx(z1.VnD(), p5.Merging(), z0.VnD());
+
+    __ movprfx(z6.VnH(), p0.Merging(), z12.VnH());
+    __ frintz(z6.VnS(), p0.Merging(), z7.VnS());
+
+    __ movprfx(z8.VnH(), p2.Merging(), z6.VnH());
+    __ fscale(z8.VnD(), p2.Merging(), z8.VnD(), z6.VnD());
+
+    __ movprfx(z20.VnH(), p2.Zeroing(), z2.VnH());
+    __ fsqrt(z20.VnD(), p2.Merging(), z15.VnD());
+
+    __ movprfx(z28.VnS(), p6.Zeroing(), z19.VnS());
+    __ fsub(z28.VnD(), p6.Merging(), z28.VnD(), 1.0);
+
+    __ movprfx(z6.VnB(), p0.Zeroing(), z12.VnB());
+    __ fsub(z6.VnD(), p0.Merging(), z6.VnD(), z20.VnD());
+
+    __ movprfx(z6.VnS(), p7.Zeroing(), z11.VnS());
+    __ fsubr(z6.VnH(), p7.Merging(), z6.VnH(), 1.0);
+
+    __ movprfx(z28.VnB(), p3.Merging(), z10.VnB());
+    __ fsubr(z28.VnS(), p3.Merging(), z28.VnS(), z9.VnS());
+
+    __ movprfx(z22.VnB(), p3.Zeroing(), z14.VnB());
+    __ scvtf(z22.VnD(), p3.Merging(), z24.VnS());
+
+    __ movprfx(z20.VnS(), p2.Merging(), z9.VnS());
+    __ scvtf(z20.VnH(), p2.Merging(), z9.VnH());
+
+    __ movprfx(z19.VnH(), p1.Merging(), z21.VnH());
+    __ scvtf(z19.VnS(), p1.Merging(), z6.VnD());
+
+    __ movprfx(z31.VnS(), p3.Merging(), z22.VnS());
+    __ scvtf(z31.VnH(), p3.Merging(), z22.VnD());
+
+    __ movprfx(z8.VnS(), p3.Merging(), z3.VnS());
+    __ ucvtf(z8.VnD(), p3.Merging(), z1.VnS());
+
+    __ movprfx(z0.VnB(), p0.Merging(), z23.VnB());
+    __ ucvtf(z0.VnH(), p0.Merging(), z12.VnH());
+
+    __ movprfx(z8.VnH(), p3.Zeroing(), z4.VnH());
+    __ ucvtf(z8.VnH(), p3.Merging(), z4.VnS());
+
+    __ movprfx(z20.VnH(), p2.Zeroing(), z10.VnH());
+    __ ucvtf(z20.VnH(), p2.Merging(), z11.VnD());
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), false);
+}
+
+TEST(movprfx_negative_predication) {
+  // Test that CanTakeSVEMovprfx() is false when a predicated movprfx appears
+  // before an unpredicated instruction.
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 54;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z27.VnS(), p1.Zeroing(), z12.VnS());
+    __ add(z27.VnS(), z27.VnS(), 42);
+
+    __ movprfx(z31.VnS(), p6.Zeroing(), z1.VnS());
+    __ and_(z31.VnS(), z31.VnS(), 4);
+
+    __ movprfx(z27.VnS(), p5.Merging(), z24.VnS());
+    __ bic(z27.VnS(), z27.VnS(), 4);
+
+    __ movprfx(z6.VnH(), p7.Merging(), z30.VnH());
+    __ clasta(z6.VnH(), p7, z6.VnH(), z14.VnH());
+
+    __ movprfx(z11.VnB(), p6.Merging(), z5.VnB());
+    __ clastb(z11.VnB(), p6, z11.VnB(), z29.VnB());
+
+    __ movprfx(z5.VnD(), p0.Merging(), z1.VnD());
+    __ decd(z5.VnD(), SVE_MUL3);
+
+    __ movprfx(z11.VnH(), p7.Zeroing(), z28.VnH());
+    __ dech(z11.VnH(), SVE_VL2);
+
+    __ movprfx(z14.VnS(), p5.Zeroing(), z6.VnS());
+    __ decp(z14.VnS(), p5);
+
+    __ movprfx(z6.VnS(), p5.Merging(), z10.VnS());
+    __ decw(z6.VnS(), SVE_ALL);
+
+    __ movprfx(z27.VnH(), p7.Zeroing(), z9.VnH());
+    __ eon(z27.VnH(), z27.VnH(), 4);
+
+    __ movprfx(z3.VnS(), p3.Zeroing(), z2.VnS());
+    __ eor(z3.VnS(), z3.VnS(), 4);
+
+    __ movprfx(z30.VnB(), p2.Zeroing(), z25.VnB());
+    __ ext(z30.VnB(), z30.VnB(), z25.VnB(), 42);
+
+    __ movprfx(z22.VnD(), p0.Merging(), z0.VnD());
+    __ incd(z22.VnD(), SVE_MUL3);
+
+    __ movprfx(z7.VnH(), p3.Merging(), z3.VnH());
+    __ inch(z7.VnH(), SVE_VL2);
+
+    __ movprfx(z9.VnD(), p1.Zeroing(), z28.VnD());
+    __ incp(z9.VnD(), p1);
+
+    __ movprfx(z30.VnS(), p3.Merging(), z4.VnS());
+    __ incw(z30.VnS(), SVE_ALL);
+
+    __ movprfx(z30.VnB(), p7.Zeroing(), z21.VnB());
+    __ insr(z30.VnB(), w30);
+
+    __ movprfx(z2.VnB(), p4.Zeroing(), z26.VnB());
+    __ insr(z2.VnB(), b0);
+
+    __ movprfx(z27.VnS(), p5.Zeroing(), z5.VnS());
+    __ mul(z27.VnS(), z27.VnS(), 42);
+
+    __ movprfx(z5.VnS(), p0.Merging(), z26.VnS());
+    __ orn(z5.VnS(), z5.VnS(), 4);
+
+    __ movprfx(z5.VnS(), p0.Merging(), z26.VnS());
+    __ orn(z5.VnS(), z5.VnS(), 4);
+
+    __ movprfx(z16.VnD(), p1.Merging(), z13.VnD());
+    __ sdot(z16.VnD(), z11.VnH(), z7.VnH(), 1);
+
+    __ movprfx(z27.VnD(), p5.Merging(), z18.VnD());
+    __ sdot(z27.VnD(), z18.VnH(), z0.VnH());
+
+    __ movprfx(z20.VnS(), p6.Merging(), z1.VnS());
+    __ sdot(z20.VnS(), z10.VnB(), z1.VnB(), 1);
+
+    __ movprfx(z19.VnD(), p0.Zeroing(), z7.VnD());
+    __ smax(z19.VnD(), z19.VnD(), 42);
+
+    __ movprfx(z15.VnD(), p1.Zeroing(), z7.VnD());
+    __ smin(z15.VnD(), z15.VnD(), 42);
+
+    __ movprfx(z15.VnB(), p5.Merging(), z3.VnB());
+    __ splice(z15.VnB(), p5, z15.VnB(), z3.VnB());
+
+    __ movprfx(z5.VnB(), p6.Zeroing(), z4.VnB());
+    __ sqadd(z5.VnB(), z5.VnB(), 42);
+
+    __ movprfx(z16.VnD(), p0.Zeroing(), z18.VnD());
+    __ sqdecd(z16.VnD(), SVE_MUL3);
+
+    __ movprfx(z7.VnH(), p3.Merging(), z28.VnH());
+    __ sqdech(z7.VnH(), SVE_VL2);
+
+    __ movprfx(z7.VnS(), p2.Merging(), z13.VnS());
+    __ sqdecp(z7.VnS(), p2);
+
+    __ movprfx(z22.VnS(), p7.Zeroing(), z20.VnS());
+    __ sqdecw(z22.VnS(), SVE_ALL);
+
+    __ movprfx(z26.VnD(), p1.Zeroing(), z0.VnD());
+    __ sqincd(z26.VnD(), SVE_MUL3);
+
+    __ movprfx(z15.VnH(), p7.Zeroing(), z27.VnH());
+    __ sqinch(z15.VnH(), SVE_VL2);
+
+    __ movprfx(z4.VnD(), p7.Merging(), z13.VnD());
+    __ sqincp(z4.VnD(), p7);
+
+    __ movprfx(z29.VnS(), p6.Merging(), z14.VnS());
+    __ sqincw(z29.VnS(), SVE_ALL);
+
+    __ movprfx(z17.VnB(), p1.Merging(), z24.VnB());
+    __ sqsub(z17.VnB(), z17.VnB(), 42);
+
+    __ movprfx(z26.VnS(), p5.Zeroing(), z19.VnS());
+    __ sub(z26.VnS(), z26.VnS(), 42);
+
+    __ movprfx(z15.VnD(), p1.Merging(), z3.VnD());
+    __ subr(z15.VnD(), z15.VnD(), 42);
+
+    __ movprfx(z4.VnD(), p2.Zeroing(), z14.VnD());
+    __ udot(z4.VnD(), z15.VnH(), z7.VnH(), 1);
+
+    __ movprfx(z29.VnD(), p4.Zeroing(), z28.VnD());
+    __ udot(z29.VnD(), z2.VnH(), z17.VnH());
+
+    __ movprfx(z7.VnS(), p6.Merging(), z3.VnS());
+    __ udot(z7.VnS(), z14.VnB(), z1.VnB(), 1);
+
+    __ movprfx(z14.VnB(), p3.Merging(), z5.VnB());
+    __ umax(z14.VnB(), z14.VnB(), 42);
+
+    __ movprfx(z4.VnD(), p1.Zeroing(), z2.VnD());
+    __ umin(z4.VnD(), z4.VnD(), 42);
+
+    __ movprfx(z19.VnB(), p0.Zeroing(), z27.VnB());
+    __ uqadd(z19.VnB(), z19.VnB(), 42);
+
+    __ movprfx(z24.VnD(), p7.Zeroing(), z11.VnD());
+    __ uqdecd(z24.VnD(), SVE_MUL3);
+
+    __ movprfx(z24.VnH(), p4.Zeroing(), z18.VnH());
+    __ uqdech(z24.VnH(), SVE_VL2);
+
+    __ movprfx(z31.VnS(), p5.Zeroing(), z2.VnS());
+    __ uqdecp(z31.VnS(), p5);
+
+    __ movprfx(z19.VnS(), p6.Merging(), z21.VnS());
+    __ uqdecw(z19.VnS(), SVE_ALL);
+
+    __ movprfx(z27.VnD(), p0.Merging(), z21.VnD());
+    __ uqincd(z27.VnD(), SVE_MUL3);
+
+    __ movprfx(z13.VnH(), p4.Zeroing(), z12.VnH());
+    __ uqinch(z13.VnH(), SVE_VL2);
+
+    __ movprfx(z0.VnD(), p4.Zeroing(), z1.VnD());
+    __ uqincp(z0.VnD(), p4);
+
+    __ movprfx(z12.VnS(), p4.Merging(), z21.VnS());
+    __ uqincw(z12.VnS(), SVE_ALL);
+
+    __ movprfx(z9.VnD(), p0.Zeroing(), z16.VnD());
+    __ uqsub(z9.VnD(), z9.VnD(), 42);
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), false);
+}
+
+TEST(movprfx_negative_predication_fp) {
+  // Test that CanTakeSVEMovprfx() is false when a predicated movprfx appears
+  // before an unpredicated instruction.
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 9;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z10.VnH(), p3.Zeroing(), z3.VnH());
+    __ fcmla(z10.VnH(), z22.VnH(), z3.VnH(), 2, 180);
+
+    __ movprfx(z12.VnS(), p4.Merging(), z14.VnS());
+    __ fcmla(z12.VnS(), z3.VnS(), z10.VnS(), 1, 270);
+
+    __ movprfx(z16.VnD(), p3.Zeroing(), z24.VnD());
+    __ fmla(z16.VnD(), z24.VnD(), z8.VnD(), 1);
+
+    __ movprfx(z9.VnH(), p7.Zeroing(), z0.VnH());
+    __ fmla(z9.VnH(), z8.VnH(), z0.VnH(), 7);
+
+    __ movprfx(z23.VnS(), p5.Merging(), z5.VnS());
+    __ fmla(z23.VnS(), z7.VnS(), z5.VnS(), 3);
+
+    __ movprfx(z19.VnD(), p6.Zeroing(), z8.VnD());
+    __ fmls(z19.VnD(), z27.VnD(), z13.VnD(), 1);
+
+    __ movprfx(z25.VnH(), p7.Merging(), z24.VnH());
+    __ fmls(z25.VnH(), z24.VnH(), z4.VnH(), 4);
+
+    __ movprfx(z2.VnS(), p1.Zeroing(), z0.VnS());
+    __ fmls(z2.VnS(), z9.VnS(), z0.VnS(), 3);
+
+    // Note that ftsmul and ftssel _cannot_ take movprfx.
+    __ movprfx(z22.VnD(), p6.Merging(), z16.VnD());
+    __ ftmad(z22.VnD(), z22.VnD(), z20.VnD(), 2);
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), false);
+}
+
+TEST(movprfx_positive) {
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 117;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z17, z28);
+    __ abs(z17.VnB(), p6.Merging(), z28.VnB());
+
+    __ movprfx(z9, z7);
+    __ add(z9.VnB(), p5.Merging(), z9.VnB(), z29.VnB());
+
+    __ movprfx(z11, z0);
+    __ add(z11.VnD(), z11.VnD(), 42);
+
+    __ movprfx(z8.VnS(), p3.Zeroing(), z28.VnS());
+    __ and_(z8.VnS(), p3.Merging(), z8.VnS(), z31.VnS());
+
+    __ movprfx(z20, z23);
+    __ and_(z20.VnS(), z20.VnS(), 4);
+
+    __ movprfx(z24.VnD(), p5.Merging(), z11.VnD());
+    __ asr(z24.VnD(), p5.Merging(), z24.VnD(), 3);
+
+    __ movprfx(z1, z13);
+    __ asr(z1.VnH(), p3.Merging(), z1.VnH(), z4.VnH());
+
+    __ movprfx(z0.VnB(), p7.Zeroing(), z28.VnB());
+    __ asr(z0.VnB(), p7.Merging(), z0.VnB(), z28.VnD());
+
+    __ movprfx(z15, z5);
+    __ asr(z15.VnD(), p3.Merging(), z15.VnD(), z5.VnD());
+
+    __ movprfx(z24.VnH(), p3.Merging(), z22.VnH());
+    __ asrd(z24.VnH(), p3.Merging(), z24.VnH(), 3);
+
+    __ movprfx(z2.VnS(), p3.Zeroing(), z20.VnS());
+    __ asrr(z2.VnS(), p3.Merging(), z2.VnS(), z15.VnS());
+
+    __ movprfx(z17.VnB(), p7.Merging(), z6.VnB());
+    __ bic(z17.VnB(), p7.Merging(), z17.VnB(), z25.VnB());
+
+    __ movprfx(z31, z6);
+    __ bic(z31.VnD(), z31.VnD(), 4);
+
+    __ movprfx(z20, z2);
+    __ clasta(z20.VnB(), p4, z20.VnB(), z15.VnB());
+
+    __ movprfx(z27, z11);
+    __ clastb(z27.VnB(), p5, z27.VnB(), z6.VnB());
+
+    __ movprfx(z3.VnS(), p7.Zeroing(), z17.VnS());
+    __ cls(z3.VnS(), p7.Merging(), z0.VnS());
+
+    __ movprfx(z29.VnB(), p0.Zeroing(), z24.VnB());
+    __ clz(z29.VnB(), p0.Merging(), z7.VnB());
+
+    __ movprfx(z2.VnH(), p7.Zeroing(), z29.VnH());
+    __ cnot(z2.VnH(), p7.Merging(), z28.VnH());
+
+    __ movprfx(z23, z5);
+    __ cnt(z23.VnH(), p0.Merging(), z12.VnH());
+
+    __ movprfx(z5, z3);
+    __ cpy(z5.VnD(), p1.Merging(), -42);
+
+    __ movprfx(z0, z12);
+    __ cpy(z0.VnB(), p1.Merging(), w0);
+
+    __ movprfx(z27, z8);
+    __ cpy(z27.VnB(), p0.Merging(), b0);
+
+    __ movprfx(z20, z24);
+    __ decd(z20.VnD(), SVE_MUL3);
+
+    __ movprfx(z5, z28);
+    __ dech(z5.VnH(), SVE_VL2);
+
+    __ movprfx(z7, z3);
+    __ decp(z7.VnD(), p2);
+
+    __ movprfx(z4, z7);
+    __ decw(z4.VnS(), SVE_ALL);
+
+    __ movprfx(z3, z18);
+    __ eon(z3.VnS(), z3.VnS(), 4);
+
+    __ movprfx(z4.VnD(), p0.Merging(), z10.VnD());
+    __ eor(z4.VnD(), p0.Merging(), z4.VnD(), z10.VnD());
+
+    __ movprfx(z15, z18);
+    __ eor(z15.VnH(), z15.VnH(), 4);
+
+    __ movprfx(z30, z11);
+    __ ext(z30.VnB(), z30.VnB(), z11.VnB(), 42);
+
+    __ movprfx(z19, z28);
+    __ incd(z19.VnD(), SVE_MUL3);
+
+    __ movprfx(z13, z7);
+    __ inch(z13.VnH(), SVE_VL2);
+
+    __ movprfx(z14, z21);
+    __ incp(z14.VnD(), p1);
+
+    __ movprfx(z26, z12);
+    __ incw(z26.VnS(), SVE_ALL);
+
+    __ movprfx(z16, z2);
+    __ insr(z16.VnB(), w16);
+
+    __ movprfx(z20, z26);
+    __ insr(z20.VnB(), b0);
+
+    __ movprfx(z30.VnD(), p0.Merging(), z23.VnD());
+    __ lsl(z30.VnD(), p0.Merging(), z30.VnD(), 3);
+
+    __ movprfx(z28.VnS(), p2.Zeroing(), z6.VnS());
+    __ lsl(z28.VnS(), p2.Merging(), z28.VnS(), z6.VnS());
+
+    __ movprfx(z15.VnH(), p6.Zeroing(), z3.VnH());
+    __ lsl(z15.VnH(), p6.Merging(), z15.VnH(), z3.VnD());
+
+    __ movprfx(z13.VnD(), p4.Zeroing(), z14.VnD());
+    __ lsl(z13.VnD(), p4.Merging(), z13.VnD(), z25.VnD());
+
+    __ movprfx(z14, z5);
+    __ lslr(z14.VnS(), p0.Merging(), z14.VnS(), z17.VnS());
+
+    __ movprfx(z21, z1);
+    __ lsr(z21.VnH(), p5.Merging(), z21.VnH(), 3);
+
+    __ movprfx(z11.VnH(), p0.Zeroing(), z13.VnH());
+    __ lsr(z11.VnH(), p0.Merging(), z11.VnH(), z9.VnH());
+
+    __ movprfx(z24, z29);
+    __ lsr(z24.VnS(), p4.Merging(), z24.VnS(), z1.VnD());
+
+    __ movprfx(z1.VnD(), p6.Merging(), z9.VnD());
+    __ lsr(z1.VnD(), p6.Merging(), z1.VnD(), z9.VnD());
+
+    __ movprfx(z22, z3);
+    __ lsrr(z22.VnB(), p3.Merging(), z22.VnB(), z3.VnB());
+
+    __ movprfx(z24.VnB(), p2.Zeroing(), z5.VnB());
+    __ mad(z24.VnB(), p2.Merging(), z5.VnB(), z10.VnB());
+
+    __ movprfx(z8, z4);
+    __ mla(z8.VnS(), p6.Merging(), z4.VnS(), z26.VnS());
+
+    __ movprfx(z10, z8);
+    __ mls(z10.VnS(), p4.Merging(), z23.VnS(), z16.VnS());
+
+    // Aliases of cpy.
+    __ movprfx(z4.VnH(), p5.Zeroing(), z2.VnH());
+    __ mov(z4.VnH(), p5.Merging(), -42);
+
+    __ movprfx(z2.VnB(), p3.Zeroing(), z24.VnB());
+    __ mov(z2.VnB(), p3.Merging(), w2);
+
+    __ movprfx(z27, z13);
+    __ mov(z27.VnD(), p3.Merging(), d0);
+
+    __ movprfx(z18.VnB(), p5.Zeroing(), z11.VnB());
+    __ msb(z18.VnB(), p5.Merging(), z3.VnB(), z11.VnB());
+
+    __ movprfx(z29, z16);
+    __ mul(z29.VnS(), p6.Merging(), z29.VnS(), z9.VnS());
+
+    __ movprfx(z21, z23);
+    __ mul(z21.VnH(), z21.VnH(), 42);
+
+    __ movprfx(z7.VnS(), p4.Merging(), z14.VnS());
+    __ neg(z7.VnS(), p4.Merging(), z14.VnS());
+
+    __ movprfx(z8.VnD(), p4.Zeroing(), z5.VnD());
+    __ not_(z8.VnD(), p4.Merging(), z5.VnD());
+
+    __ movprfx(z14, z13);
+    __ orn(z14.VnS(), z14.VnS(), 4);
+
+    __ movprfx(z14, z13);
+    __ orn(z14.VnS(), z14.VnS(), 4);
+
+    __ movprfx(z27, z17);
+    __ orr(z27.VnD(), p2.Merging(), z27.VnD(), z17.VnD());
+
+    __ movprfx(z13.VnH(), p2.Zeroing(), z27.VnH());
+    __ rbit(z13.VnH(), p2.Merging(), z1.VnH());
+
+    __ movprfx(z1, z29);
+    __ revb(z1.VnS(), p4.Merging(), z6.VnS());
+
+    __ movprfx(z18.VnD(), p2.Zeroing(), z10.VnD());
+    __ revh(z18.VnD(), p2.Merging(), z16.VnD());
+
+    __ movprfx(z2.VnD(), p1.Merging(), z10.VnD());
+    __ revw(z2.VnD(), p1.Merging(), z1.VnD());
+
+    __ movprfx(z28.VnS(), p7.Merging(), z11.VnS());
+    __ sabd(z28.VnS(), p7.Merging(), z28.VnS(), z11.VnS());
+
+    __ movprfx(z22.VnS(), p0.Merging(), z20.VnS());
+    __ sdiv(z22.VnS(), p0.Merging(), z22.VnS(), z6.VnS());
+
+    __ movprfx(z13.VnS(), p7.Merging(), z0.VnS());
+    __ sdivr(z13.VnS(), p7.Merging(), z13.VnS(), z2.VnS());
+
+    __ movprfx(z0, z12);
+    __ sdot(z0.VnD(), z10.VnH(), z12.VnH(), 1);
+
+    __ movprfx(z8, z15);
+    __ sdot(z8.VnS(), z15.VnB(), z12.VnB());
+
+    __ movprfx(z13, z0);
+    __ sdot(z13.VnS(), z10.VnB(), z0.VnB(), 1);
+
+    __ movprfx(z11, z13);
+    __ smax(z11.VnB(), p5.Merging(), z11.VnB(), z24.VnB());
+
+    __ movprfx(z3, z17);
+    __ smax(z3.VnD(), z3.VnD(), 42);
+
+    __ movprfx(z10, z29);
+    __ smin(z10.VnD(), p4.Merging(), z10.VnD(), z29.VnD());
+
+    __ movprfx(z13, z29);
+    __ smin(z13.VnD(), z13.VnD(), 42);
+
+    __ movprfx(z6, z17);
+    __ smulh(z6.VnS(), p7.Merging(), z6.VnS(), z31.VnS());
+
+    __ movprfx(z19, z20);
+    __ splice(z19.VnB(), p3, z19.VnB(), z20.VnB());
+
+    __ movprfx(z0, z3);
+    __ sqadd(z0.VnD(), z0.VnD(), 42);
+
+    __ movprfx(z29, z5);
+    __ sqdecd(z29.VnD(), SVE_MUL3);
+
+    __ movprfx(z25, z11);
+    __ sqdech(z25.VnH(), SVE_VL2);
+
+    __ movprfx(z16, z9);
+    __ sqdecp(z16.VnS(), p1);
+
+    __ movprfx(z8, z17);
+    __ sqdecw(z8.VnS(), SVE_ALL);
+
+    __ movprfx(z4, z5);
+    __ sqincd(z4.VnD(), SVE_MUL3);
+
+    __ movprfx(z0, z17);
+    __ sqinch(z0.VnH(), SVE_VL2);
+
+    __ movprfx(z7, z27);
+    __ sqincp(z7.VnS(), p6);
+
+    __ movprfx(z10, z9);
+    __ sqincw(z10.VnS(), SVE_ALL);
+
+    __ movprfx(z31, z22);
+    __ sqsub(z31.VnB(), z31.VnB(), 42);
+
+    __ movprfx(z12.VnH(), p7.Zeroing(), z23.VnH());
+    __ sub(z12.VnH(), p7.Merging(), z12.VnH(), z23.VnH());
+
+    __ movprfx(z10, z1);
+    __ sub(z10.VnH(), z10.VnH(), 42);
+
+    __ movprfx(z15.VnB(), p0.Merging(), z0.VnB());
+    __ subr(z15.VnB(), p0.Merging(), z15.VnB(), z0.VnB());
+
+    __ movprfx(z17, z2);
+    __ subr(z17.VnH(), z17.VnH(), 42);
+
+    __ movprfx(z5, z3);
+    __ sxtb(z5.VnD(), p6.Merging(), z20.VnD());
+
+    __ movprfx(z11, z17);
+    __ sxth(z11.VnD(), p6.Merging(), z25.VnD());
+
+    __ movprfx(z26, z4);
+    __ sxtw(z26.VnD(), p5.Merging(), z4.VnD());
+
+    __ movprfx(z15.VnD(), p0.Zeroing(), z8.VnD());
+    __ uabd(z15.VnD(), p0.Merging(), z15.VnD(), z20.VnD());
+
+    __ movprfx(z21, z24);
+    __ udiv(z21.VnD(), p3.Merging(), z21.VnD(), z24.VnD());
+
+    __ movprfx(z22, z10);
+    __ udivr(z22.VnD(), p7.Merging(), z22.VnD(), z27.VnD());
+
+    __ movprfx(z27, z25);
+    __ udot(z27.VnD(), z29.VnH(), z3.VnH(), 1);
+
+    __ movprfx(z29, z10);
+    __ udot(z29.VnS(), z10.VnB(), z21.VnB());
+
+    __ movprfx(z18, z0);
+    __ udot(z18.VnS(), z14.VnB(), z0.VnB(), 1);
+
+    __ movprfx(z6, z30);
+    __ umax(z6.VnS(), p2.Merging(), z6.VnS(), z27.VnS());
+
+    __ movprfx(z31, z17);
+    __ umax(z31.VnD(), z31.VnD(), 42);
+
+    __ movprfx(z27.VnS(), p0.Merging(), z20.VnS());
+    __ umin(z27.VnS(), p0.Merging(), z27.VnS(), z8.VnS());
+
+    __ movprfx(z0, z11);
+    __ umin(z0.VnH(), z0.VnH(), 42);
+
+    __ movprfx(z21, z17);
+    __ umulh(z21.VnB(), p0.Merging(), z21.VnB(), z30.VnB());
+
+    __ movprfx(z9, z24);
+    __ uqadd(z9.VnD(), z9.VnD(), 42);
+
+    __ movprfx(z18, z13);
+    __ uqdecd(z18.VnD(), SVE_MUL3);
+
+    __ movprfx(z20, z23);
+    __ uqdech(z20.VnH(), SVE_VL2);
+
+    __ movprfx(z12, z29);
+    __ uqdecp(z12.VnS(), p7);
+
+    __ movprfx(z24, z25);
+    __ uqdecw(z24.VnS(), SVE_ALL);
+
+    __ movprfx(z13, z1);
+    __ uqincd(z13.VnD(), SVE_MUL3);
+
+    __ movprfx(z5, z19);
+    __ uqinch(z5.VnH(), SVE_VL2);
+
+    __ movprfx(z6, z25);
+    __ uqincp(z6.VnS(), p5);
+
+    __ movprfx(z12, z14);
+    __ uqincw(z12.VnS(), SVE_ALL);
+
+    __ movprfx(z13, z6);
+    __ uqsub(z13.VnH(), z13.VnH(), 42);
+
+    __ movprfx(z31, z3);
+    __ uxtb(z31.VnS(), p0.Merging(), z3.VnS());
+
+    __ movprfx(z18.VnD(), p4.Merging(), z25.VnD());
+    __ uxth(z18.VnD(), p4.Merging(), z25.VnD());
+
+    __ movprfx(z18.VnD(), p7.Merging(), z25.VnD());
+    __ uxtw(z18.VnD(), p7.Merging(), z25.VnD());
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), true);
+}
+
+TEST(movprfx_positive_fp) {
+  Assembler assm;
+  assm.GetCPUFeatures()->Combine(CPUFeatures::kSVE);
+  {
+    // We have to use the Assembler directly to generate movprfx, so we need
+    // to manually reserve space for the code we're about to emit.
+    static const size_t kPairCount = 73;
+    CodeBufferCheckScope guard(&assm, kPairCount * 2 * kInstructionSize);
+
+    __ movprfx(z18.VnS(), p6.Zeroing(), z20.VnS());
+    __ fabd(z18.VnS(), p6.Merging(), z18.VnS(), z19.VnS());
+
+    __ movprfx(z28.VnD(), p4.Zeroing(), z24.VnD());
+    __ fabs(z28.VnD(), p4.Merging(), z24.VnD());
+
+    __ movprfx(z12, z8);
+    __ fadd(z12.VnS(), p2.Merging(), z12.VnS(), 0.5);
+
+    __ movprfx(z0.VnS(), p1.Merging(), z9.VnS());
+    __ fadd(z0.VnS(), p1.Merging(), z0.VnS(), z9.VnS());
+
+    __ movprfx(z10.VnH(), p2.Merging(), z2.VnH());
+    __ fcadd(z10.VnH(), p2.Merging(), z10.VnH(), z20.VnH(), 90);
+
+    __ movprfx(z21, z6);
+    __ fcmla(z21.VnH(), z31.VnH(), z6.VnH(), 2, 180);
+
+    __ movprfx(z16, z6);
+    __ fcmla(z16.VnS(), z11.VnS(), z6.VnS(), 1, 270);
+
+    __ movprfx(z15.VnH(), p6.Merging(), z16.VnH());
+    __ fcpy(z15.VnH(), p6.Merging(), 1.25);
+
+    __ movprfx(z1, z14);
+    __ fcvt(z1.VnD(), p2.Merging(), z4.VnH());
+
+    __ movprfx(z25.VnD(), p6.Merging(), z1.VnD());
+    __ fcvt(z25.VnD(), p6.Merging(), z1.VnS());
+
+    __ movprfx(z18.VnS(), p2.Merging(), z2.VnS());
+    __ fcvt(z18.VnH(), p2.Merging(), z7.VnS());
+
+    __ movprfx(z21.VnD(), p5.Zeroing(), z26.VnD());
+    __ fcvt(z21.VnH(), p5.Merging(), z26.VnD());
+
+    __ movprfx(z12.VnD(), p1.Merging(), z18.VnD());
+    __ fcvtzs(z12.VnD(), p1.Merging(), z18.VnH());
+
+    __ movprfx(z3.VnS(), p2.Merging(), z0.VnS());
+    __ fcvtzs(z3.VnS(), p2.Merging(), z26.VnS());
+
+    __ movprfx(z21.VnS(), p4.Merging(), z7.VnS());
+    __ fcvtzs(z21.VnS(), p4.Merging(), z7.VnH());
+
+    __ movprfx(z16.VnD(), p3.Zeroing(), z4.VnD());
+    __ fcvtzs(z16.VnS(), p3.Merging(), z28.VnD());
+
+    __ movprfx(z31.VnD(), p4.Merging(), z1.VnD());
+    __ fcvtzu(z31.VnD(), p4.Merging(), z1.VnH());
+
+    __ movprfx(z23.VnH(), p0.Zeroing(), z28.VnH());
+    __ fcvtzu(z23.VnH(), p0.Merging(), z28.VnH());
+
+    __ movprfx(z2, z12);
+    __ fcvtzu(z2.VnD(), p3.Merging(), z28.VnS());
+
+    __ movprfx(z4, z7);
+    __ fcvtzu(z4.VnS(), p7.Merging(), z16.VnD());
+
+    __ movprfx(z13.VnS(), p3.Zeroing(), z23.VnS());
+    __ fdiv(z13.VnS(), p3.Merging(), z13.VnS(), z23.VnS());
+
+    __ movprfx(z6.VnD(), p1.Zeroing(), z16.VnD());
+    __ fdivr(z6.VnD(), p1.Merging(), z6.VnD(), z5.VnD());
+
+    __ movprfx(z31, z23);
+    __ fmad(z31.VnS(), p5.Merging(), z23.VnS(), z11.VnS());
+
+    __ movprfx(z14.VnH(), p7.Merging(), z21.VnH());
+    __ fmax(z14.VnH(), p7.Merging(), z14.VnH(), 0.0);
+
+    __ movprfx(z17.VnS(), p4.Merging(), z9.VnS());
+    __ fmax(z17.VnS(), p4.Merging(), z17.VnS(), z9.VnS());
+
+    __ movprfx(z1.VnS(), p3.Zeroing(), z30.VnS());
+    __ fmaxnm(z1.VnS(), p3.Merging(), z1.VnS(), 0.0);
+
+    __ movprfx(z10.VnD(), p1.Zeroing(), z17.VnD());
+    __ fmaxnm(z10.VnD(), p1.Merging(), z10.VnD(), z17.VnD());
+
+    __ movprfx(z3, z13);
+    __ fmin(z3.VnS(), p0.Merging(), z3.VnS(), 0.0);
+
+    __ movprfx(z15, z21);
+    __ fmin(z15.VnS(), p4.Merging(), z15.VnS(), z21.VnS());
+
+    __ movprfx(z30.VnH(), p7.Zeroing(), z25.VnH());
+    __ fminnm(z30.VnH(), p7.Merging(), z30.VnH(), 0.0);
+
+    __ movprfx(z31, z15);
+    __ fminnm(z31.VnD(), p5.Merging(), z31.VnD(), z25.VnD());
+
+    __ movprfx(z27, z28);
+    __ fmla(z27.VnD(), z28.VnD(), z12.VnD(), 1);
+
+    __ movprfx(z26.VnH(), p6.Zeroing(), z13.VnH());
+    __ fmla(z26.VnH(), p6.Merging(), z13.VnH(), z7.VnH());
+
+    __ movprfx(z26, z10);
+    __ fmla(z26.VnH(), z10.VnH(), z1.VnH(), 7);
+
+    __ movprfx(z0, z1);
+    __ fmla(z0.VnS(), z25.VnS(), z1.VnS(), 3);
+
+    __ movprfx(z7, z3);
+    __ fmls(z7.VnD(), z30.VnD(), z3.VnD(), 1);
+
+    __ movprfx(z1, z24);
+    __ fmls(z1.VnD(), p5.Merging(), z20.VnD(), z24.VnD());
+
+    __ movprfx(z19, z18);
+    __ fmls(z19.VnH(), z18.VnH(), z7.VnH(), 4);
+
+    __ movprfx(z0, z26);
+    __ fmls(z0.VnS(), z17.VnS(), z4.VnS(), 3);
+
+    __ movprfx(z19.VnS(), p7.Zeroing(), z6.VnS());
+    __ fmov(z19.VnS(), p7.Merging(), 0.0);
+
+    __ movprfx(z21, z15);
+    __ fmov(z21.VnH(), p7.Merging(), 2.5);
+
+    __ movprfx(z23, z18);
+    __ fmsb(z23.VnS(), p4.Merging(), z1.VnS(), z7.VnS());
+
+    __ movprfx(z8, z28);
+    __ fmul(z8.VnS(), p4.Merging(), z8.VnS(), 2.0);
+
+    __ movprfx(z6.VnD(), p6.Merging(), z27.VnD());
+    __ fmul(z6.VnD(), p6.Merging(), z6.VnD(), z27.VnD());
+
+    __ movprfx(z6.VnH(), p0.Merging(), z19.VnH());
+    __ fmulx(z6.VnH(), p0.Merging(), z6.VnH(), z19.VnH());
+
+    __ movprfx(z5.VnH(), p0.Merging(), z1.VnH());
+    __ fneg(z5.VnH(), p0.Merging(), z1.VnH());
+
+    __ movprfx(z22.VnD(), p4.Zeroing(), z24.VnD());
+    __ fnmad(z22.VnD(), p4.Merging(), z24.VnD(), z12.VnD());
+
+    __ movprfx(z5.VnS(), p0.Merging(), z29.VnS());
+    __ fnmla(z5.VnS(), p0.Merging(), z17.VnS(), z29.VnS());
+
+    __ movprfx(z5, z3);
+    __ fnmls(z5.VnD(), p5.Merging(), z3.VnD(), z2.VnD());
+
+    __ movprfx(z9.VnD(), p2.Zeroing(), z7.VnD());
+    __ fnmsb(z9.VnD(), p2.Merging(), z7.VnD(), z23.VnD());
+
+    // Note that frecpe and frecps _cannot_ take movprfx.
+    __ movprfx(z12.VnH(), p1.Zeroing(), z17.VnH());
+    __ frecpx(z12.VnH(), p1.Merging(), z4.VnH());
+
+    __ movprfx(z28.VnS(), p4.Zeroing(), z27.VnS());
+    __ frinta(z28.VnS(), p4.Merging(), z24.VnS());
+
+    __ movprfx(z7.VnD(), p7.Merging(), z25.VnD());
+    __ frinti(z7.VnD(), p7.Merging(), z25.VnD());
+
+    __ movprfx(z10, z21);
+    __ frintm(z10.VnD(), p5.Merging(), z26.VnD());
+
+    __ movprfx(z25, z21);
+    __ frintn(z25.VnH(), p4.Merging(), z1.VnH());
+
+    __ movprfx(z25, z9);
+    __ frintp(z25.VnH(), p1.Merging(), z9.VnH());
+
+    __ movprfx(z30, z16);
+    __ frintx(z30.VnS(), p1.Merging(), z16.VnS());
+
+    __ movprfx(z0.VnD(), p5.Merging(), z9.VnD());
+    __ frintz(z0.VnD(), p5.Merging(), z23.VnD());
+
+    __ movprfx(z11.VnD(), p7.Merging(), z2.VnD());
+    __ fscale(z11.VnD(), p7.Merging(), z11.VnD(), z2.VnD());
+
+    __ movprfx(z23.VnS(), p4.Merging(), z17.VnS());
+    __ fsqrt(z23.VnS(), p4.Merging(), z10.VnS());
+
+    __ movprfx(z0.VnD(), p2.Merging(), z26.VnD());
+    __ fsub(z0.VnD(), p2.Merging(), z0.VnD(), 1.0);
+
+    __ movprfx(z28.VnD(), p1.Zeroing(), z16.VnD());
+    __ fsub(z28.VnD(), p1.Merging(), z28.VnD(), z16.VnD());
+
+    __ movprfx(z22, z27);
+    __ fsubr(z22.VnD(), p4.Merging(), z22.VnD(), 1.0);
+
+    __ movprfx(z4.VnS(), p2.Merging(), z26.VnS());
+    __ fsubr(z4.VnS(), p2.Merging(), z4.VnS(), z26.VnS());
+
+    // Note that ftsmul and ftssel _cannot_ take movprfx.
+    __ movprfx(z10, z4);
+    __ ftmad(z10.VnS(), z10.VnS(), z4.VnS(), 2);
+
+    __ movprfx(z2, z16);
+    __ scvtf(z2.VnD(), p1.Merging(), z16.VnS());
+
+    __ movprfx(z10, z20);
+    __ scvtf(z10.VnD(), p5.Merging(), z20.VnD());
+
+    __ movprfx(z29, z28);
+    __ scvtf(z29.VnS(), p0.Merging(), z31.VnD());
+
+    __ movprfx(z26.VnD(), p3.Merging(), z13.VnD());
+    __ scvtf(z26.VnH(), p3.Merging(), z5.VnD());
+
+    __ movprfx(z7.VnD(), p3.Zeroing(), z26.VnD());
+    __ ucvtf(z7.VnD(), p3.Merging(), z26.VnS());
+
+    __ movprfx(z13, z17);
+    __ ucvtf(z13.VnD(), p7.Merging(), z17.VnD());
+
+    __ movprfx(z24.VnD(), p1.Merging(), z31.VnD());
+    __ ucvtf(z24.VnS(), p1.Merging(), z18.VnD());
+
+    __ movprfx(z17.VnD(), p4.Merging(), z22.VnD());
+    __ ucvtf(z17.VnH(), p4.Merging(), z4.VnD());
+  }
+  assm.FinalizeCode();
+
+  CheckAndMaybeDisassembleMovprfxPairs(assm.GetBuffer(), true);
+}
+
+
+}  // namespace aarch64
+}  // namespace vixl
diff --git a/test/aarch64/test-assembler-aarch64.cc b/test/aarch64/test-assembler-aarch64.cc
index c4696e5a..e23bd8ce 100644
--- a/test/aarch64/test-assembler-aarch64.cc
+++ b/test/aarch64/test-assembler-aarch64.cc
@@ -1531,8 +1531,8 @@ typedef void (MacroAssembler::*TestBranchSignature)(const Register& rt,
 static void TbzRangePoolLimitHelper(TestBranchSignature test_branch) {
   const int kTbzRange = 32768;
   const int kNumLdrLiteral = kTbzRange / 4;
-  const int fuzzRange = 2;
-  for (int n = kNumLdrLiteral - fuzzRange; n <= kNumLdrLiteral + fuzzRange;
+  const int fuzz_range = 2;
+  for (int n = kNumLdrLiteral - fuzz_range; n <= kNumLdrLiteral + fuzz_range;
        ++n) {
     for (int margin = -32; margin < 32; margin += 4) {
       SETUP();
@@ -4113,6 +4113,26 @@ TEST(ldr_literal_custom_shared) {
   }
 }
 
+static const PrefetchOperation kPrfmOperations[] = {PLDL1KEEP,
+                                                    PLDL1STRM,
+                                                    PLDL2KEEP,
+                                                    PLDL2STRM,
+                                                    PLDL3KEEP,
+                                                    PLDL3STRM,
+
+                                                    PLIL1KEEP,
+                                                    PLIL1STRM,
+                                                    PLIL2KEEP,
+                                                    PLIL2STRM,
+                                                    PLIL3KEEP,
+                                                    PLIL3STRM,
+
+                                                    PSTL1KEEP,
+                                                    PSTL1STRM,
+                                                    PSTL2KEEP,
+                                                    PSTL2STRM,
+                                                    PSTL3KEEP,
+                                                    PSTL3STRM};
 
 TEST(prfm_offset) {
   SETUP();
@@ -4121,15 +4141,18 @@ TEST(prfm_offset) {
   // The address used in prfm doesn't have to be valid.
   __ Mov(x0, 0x0123456789abcdef);
 
-  for (int i = 0; i < (1 << ImmPrefetchOperation_width); i++) {
+  for (int op = 0; op < (1 << ImmPrefetchOperation_width); op++) {
     // Unallocated prefetch operations are ignored, so test all of them.
-    PrefetchOperation op = static_cast<PrefetchOperation>(i);
+    // We have to use the Assembler directly for this.
+    ExactAssemblyScope guard(&masm, 3 * kInstructionSize);
+    __ prfm(op, MemOperand(x0));
+    __ prfm(op, MemOperand(x0, 8));
+    __ prfm(op, MemOperand(x0, 32760));
+  }
 
-    __ Prfm(op, MemOperand(x0));
-    __ Prfm(op, MemOperand(x0, 8));
-    __ Prfm(op, MemOperand(x0, 32760));
+  for (PrefetchOperation op : kPrfmOperations) {
+    // Also test named operations.
     __ Prfm(op, MemOperand(x0, 32768));
-
     __ Prfm(op, MemOperand(x0, 1));
     __ Prfm(op, MemOperand(x0, 9));
     __ Prfm(op, MemOperand(x0, 255));
@@ -4167,14 +4190,21 @@ TEST(prfm_regoffset) {
   __ Mov(x17, -255);
   __ Mov(x18, 0xfedcba9876543210);
 
-  for (int i = 0; i < (1 << ImmPrefetchOperation_width); i++) {
+  for (int op = 0; op < (1 << ImmPrefetchOperation_width); op++) {
     // Unallocated prefetch operations are ignored, so test all of them.
-    PrefetchOperation op = static_cast<PrefetchOperation>(i);
+    // We have to use the Assembler directly for this.
+    ExactAssemblyScope guard(&masm, inputs.GetCount() * kInstructionSize);
+    CPURegList loop = inputs;
+    while (!loop.IsEmpty()) {
+      __ prfm(op, MemOperand(x0, Register(loop.PopLowestIndex())));
+    }
+  }
 
+  for (PrefetchOperation op : kPrfmOperations) {
+    // Also test named operations.
     CPURegList loop = inputs;
     while (!loop.IsEmpty()) {
       Register input(loop.PopLowestIndex());
-      __ Prfm(op, MemOperand(x0, input));
       __ Prfm(op, MemOperand(x0, input, UXTW));
       __ Prfm(op, MemOperand(x0, input, UXTW, 3));
       __ Prfm(op, MemOperand(x0, input, LSL));
@@ -4197,15 +4227,19 @@ TEST(prfm_literal_imm19) {
   SETUP();
   START();
 
-  for (int i = 0; i < (1 << ImmPrefetchOperation_width); i++) {
+  for (int op = 0; op < (1 << ImmPrefetchOperation_width); op++) {
     // Unallocated prefetch operations are ignored, so test all of them.
-    PrefetchOperation op = static_cast<PrefetchOperation>(i);
-
-    ExactAssemblyScope scope(&masm, 7 * kInstructionSize);
-    // The address used in prfm doesn't have to be valid.
+    // We have to use the Assembler directly for this.
+    ExactAssemblyScope guard(&masm, 3 * kInstructionSize);
     __ prfm(op, INT64_C(0));
     __ prfm(op, 1);
     __ prfm(op, -1);
+  }
+
+  for (PrefetchOperation op : kPrfmOperations) {
+    // Also test named operations.
+    ExactAssemblyScope guard(&masm, 4 * kInstructionSize);
+    // The address used in prfm doesn't have to be valid.
     __ prfm(op, 1000);
     __ prfm(op, -1000);
     __ prfm(op, 0x3ffff);
@@ -4237,10 +4271,16 @@ TEST(prfm_literal) {
   }
   __ Bind(&end_of_pool_before);
 
-  for (int i = 0; i < (1 << ImmPrefetchOperation_width); i++) {
+  for (int op = 0; op < (1 << ImmPrefetchOperation_width); op++) {
     // Unallocated prefetch operations are ignored, so test all of them.
-    PrefetchOperation op = static_cast<PrefetchOperation>(i);
+    // We have to use the Assembler directly for this.
+    ExactAssemblyScope guard(&masm, 2 * kInstructionSize);
+    __ prfm(op, &before);
+    __ prfm(op, &after);
+  }
 
+  for (PrefetchOperation op : kPrfmOperations) {
+    // Also test named operations.
     ExactAssemblyScope guard(&masm, 2 * kInstructionSize);
     __ prfm(op, &before);
     __ prfm(op, &after);
@@ -4268,10 +4308,7 @@ TEST(prfm_wide) {
   // The address used in prfm doesn't have to be valid.
   __ Mov(x0, 0x0123456789abcdef);
 
-  for (int i = 0; i < (1 << ImmPrefetchOperation_width); i++) {
-    // Unallocated prefetch operations are ignored, so test all of them.
-    PrefetchOperation op = static_cast<PrefetchOperation>(i);
-
+  for (PrefetchOperation op : kPrfmOperations) {
     __ Prfm(op, MemOperand(x0, 0x40000));
     __ Prfm(op, MemOperand(x0, -0x40001));
     __ Prfm(op, MemOperand(x0, UINT64_C(0x5555555555555555)));
@@ -4319,9 +4356,25 @@ TEST(load_prfm_literal) {
   }
   __ Bind(&end_of_pool_before);
 
-  for (int i = 0; i < (1 << ImmPrefetchOperation_width); i++) {
+  for (int op = 0; op < (1 << ImmPrefetchOperation_width); op++) {
     // Unallocated prefetch operations are ignored, so test all of them.
-    PrefetchOperation op = static_cast<PrefetchOperation>(i);
+    ExactAssemblyScope scope(&masm, 10 * kInstructionSize);
+
+    __ prfm(op, &before_x);
+    __ prfm(op, &before_w);
+    __ prfm(op, &before_sx);
+    __ prfm(op, &before_d);
+    __ prfm(op, &before_s);
+
+    __ prfm(op, &after_x);
+    __ prfm(op, &after_w);
+    __ prfm(op, &after_sx);
+    __ prfm(op, &after_d);
+    __ prfm(op, &after_s);
+  }
+
+  for (PrefetchOperation op : kPrfmOperations) {
+    // Also test named operations.
     ExactAssemblyScope scope(&masm, 10 * kInstructionSize);
 
     __ prfm(op, &before_x);
@@ -6681,12 +6734,10 @@ TEST(axflag_xaflag) {
 
 TEST(system_msr) {
   // All FPCR fields that must be implemented: AHP, DN, FZ, RMode
-  const uint64_t fpcr_core = 0x07c00000;
-
-  // All FPCR fields (including fields which may be read-as-zero):
-  //  Stride, Len
-  //  IDE, IXE, UFE, OFE, DZE, IOE
-  const uint64_t fpcr_all = fpcr_core | 0x00379f00;
+  const uint64_t fpcr_core = (0b1 << 26) |  // AHP
+                             (0b1 << 25) |  // DN
+                             (0b1 << 24) |  // FZ
+                             (0b11 << 22);  // RMode
 
   SETUP();
 
@@ -6719,6 +6770,18 @@ TEST(system_msr) {
   __ Msr(FPCR, x8);
   __ Mrs(x8, FPCR);
 
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+  // All FPCR fields that aren't `RES0`:
+  const uint64_t fpcr_all = fpcr_core | (0b11 << 20) |  // Stride
+                            (0b1 << 19) |               // FZ16
+                            (0b111 << 16) |             // Len
+                            (0b1 << 15) |               // IDE
+                            (0b1 << 12) |               // IXE
+                            (0b1 << 11) |               // UFE
+                            (0b1 << 10) |               // OFE
+                            (0b1 << 9) |                // DZE
+                            (0b1 << 8);                 // IOE
+
   // All FPCR fields, including optional ones. This part of the test doesn't
   // achieve much other than ensuring that supported fields can be cleared by
   // the next test.
@@ -6734,6 +6797,7 @@ TEST(system_msr) {
   __ Mov(x10, ~fpcr_all);
   __ Msr(FPCR, x10);
   __ Mrs(x10, FPCR);
+#endif
 
   END();
 
@@ -6744,8 +6808,11 @@ TEST(system_msr) {
     ASSERT_EQUAL_64(8, x7);
 
     ASSERT_EQUAL_64(fpcr_core, x8);
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
     ASSERT_EQUAL_64(fpcr_core, x9);
     ASSERT_EQUAL_64(0, x10);
+#endif
   }
 }
 
@@ -7257,7 +7324,7 @@ TEST(zero_dest) {
   __ Mov(x0, 0);
   __ Mov(x1, literal_base);
   for (unsigned i = 2; i < x30.GetCode(); i++) {
-    __ Add(Register::GetXRegFromCode(i), Register::GetXRegFromCode(i - 1), x1);
+    __ Add(XRegister(i), XRegister(i - 1), x1);
   }
   before.Dump(&masm);
 
@@ -7327,7 +7394,7 @@ TEST(zero_dest_setflags) {
   __ Mov(x0, 0);
   __ Mov(x1, literal_base);
   for (int i = 2; i < 30; i++) {
-    __ Add(Register::GetXRegFromCode(i), Register::GetXRegFromCode(i - 1), x1);
+    __ Add(XRegister(i), XRegister(i - 1), x1);
   }
   before.Dump(&masm);
 
@@ -8625,7 +8692,7 @@ static void PushPopWXOverlapHelper(int reg_count, int claim) {
     if (active_w_slots > requested_w_slots) {
       __ Drop((active_w_slots - requested_w_slots) * kWRegSizeInBytes);
       // Bump the number of active W-sized slots back to where it should be,
-      // and fill the empty space with a dummy value.
+      // and fill the empty space with a placeholder value.
       do {
         stack[active_w_slots--] = 0xdeadbeef;
       } while (active_w_slots > requested_w_slots);
@@ -9746,47 +9813,38 @@ TEST(ldaxr_stlxr_fail) {
 #endif
 
 TEST(cas_casa_casl_casal_w) {
-  uint64_t data1[] = {0x01234567, 0};
-  uint64_t data2[] = {0x01234567, 0};
-  uint64_t data3[] = {0x01234567, 0};
-  uint64_t data4[] = {0x01234567, 0};
-  uint64_t data5[] = {0x01234567, 0};
-  uint64_t data6[] = {0x01234567, 0};
-  uint64_t data7[] = {0x01234567, 0};
-  uint64_t data8[] = {0x01234567, 0};
-
-  uint64_t* data1_aligned = AlignUp(data1, kXRegSizeInBytes * 2);
-  uint64_t* data2_aligned = AlignUp(data2, kXRegSizeInBytes * 2);
-  uint64_t* data3_aligned = AlignUp(data3, kXRegSizeInBytes * 2);
-  uint64_t* data4_aligned = AlignUp(data4, kXRegSizeInBytes * 2);
-  uint64_t* data5_aligned = AlignUp(data5, kXRegSizeInBytes * 2);
-  uint64_t* data6_aligned = AlignUp(data6, kXRegSizeInBytes * 2);
-  uint64_t* data7_aligned = AlignUp(data7, kXRegSizeInBytes * 2);
-  uint64_t* data8_aligned = AlignUp(data8, kXRegSizeInBytes * 2);
+  uint64_t data1 = 0x0123456789abcdef;
+  uint64_t data2 = 0x0123456789abcdef;
+  uint64_t data3 = 0x0123456789abcdef;
+  uint64_t data4 = 0x0123456789abcdef;
+  uint64_t data5 = 0x0123456789abcdef;
+  uint64_t data6 = 0x0123456789abcdef;
+  uint64_t data7 = 0x0123456789abcdef;
+  uint64_t data8 = 0x0123456789abcdef;
 
   SETUP_WITH_FEATURES(CPUFeatures::kAtomics);
 
   START();
 
-  __ Mov(x21, reinterpret_cast<uintptr_t>(data1_aligned));
-  __ Mov(x22, reinterpret_cast<uintptr_t>(data2_aligned));
-  __ Mov(x23, reinterpret_cast<uintptr_t>(data3_aligned));
-  __ Mov(x24, reinterpret_cast<uintptr_t>(data4_aligned));
-  __ Mov(x25, reinterpret_cast<uintptr_t>(data5_aligned));
-  __ Mov(x26, reinterpret_cast<uintptr_t>(data6_aligned));
-  __ Mov(x27, reinterpret_cast<uintptr_t>(data7_aligned));
-  __ Mov(x28, reinterpret_cast<uintptr_t>(data8_aligned));
+  __ Mov(x21, reinterpret_cast<uintptr_t>(&data1) + 0);
+  __ Mov(x22, reinterpret_cast<uintptr_t>(&data2) + 0);
+  __ Mov(x23, reinterpret_cast<uintptr_t>(&data3) + 4);
+  __ Mov(x24, reinterpret_cast<uintptr_t>(&data4) + 4);
+  __ Mov(x25, reinterpret_cast<uintptr_t>(&data5) + 0);
+  __ Mov(x26, reinterpret_cast<uintptr_t>(&data6) + 0);
+  __ Mov(x27, reinterpret_cast<uintptr_t>(&data7) + 4);
+  __ Mov(x28, reinterpret_cast<uintptr_t>(&data8) + 4);
 
   __ Mov(x0, 0xffffffff);
 
-  __ Mov(x1, 0x76543210);
-  __ Mov(x2, 0x01234567);
-  __ Mov(x3, 0x76543210);
-  __ Mov(x4, 0x01234567);
-  __ Mov(x5, 0x76543210);
-  __ Mov(x6, 0x01234567);
-  __ Mov(x7, 0x76543210);
-  __ Mov(x8, 0x01234567);
+  __ Mov(x1, 0xfedcba9876543210);
+  __ Mov(x2, 0x0123456789abcdef);
+  __ Mov(x3, 0xfedcba9876543210);
+  __ Mov(x4, 0x89abcdef01234567);
+  __ Mov(x5, 0xfedcba9876543210);
+  __ Mov(x6, 0x0123456789abcdef);
+  __ Mov(x7, 0xfedcba9876543210);
+  __ Mov(x8, 0x89abcdef01234567);
 
   __ Cas(w1, w0, MemOperand(x21));
   __ Cas(w2, w0, MemOperand(x22));
@@ -9802,57 +9860,48 @@ TEST(cas_casa_casl_casal_w) {
   if (CAN_RUN()) {
     RUN();
 
-    ASSERT_EQUAL_64(0x01234567, x1);
-    ASSERT_EQUAL_64(0x01234567, x2);
+    ASSERT_EQUAL_64(0x89abcdef, x1);
+    ASSERT_EQUAL_64(0x89abcdef, x2);
     ASSERT_EQUAL_64(0x01234567, x3);
     ASSERT_EQUAL_64(0x01234567, x4);
-    ASSERT_EQUAL_64(0x01234567, x5);
-    ASSERT_EQUAL_64(0x01234567, x6);
+    ASSERT_EQUAL_64(0x89abcdef, x5);
+    ASSERT_EQUAL_64(0x89abcdef, x6);
     ASSERT_EQUAL_64(0x01234567, x7);
     ASSERT_EQUAL_64(0x01234567, x8);
 
-    ASSERT_EQUAL_64(0x01234567, data1[0]);
-    ASSERT_EQUAL_64(0xffffffff, data2[0]);
-    ASSERT_EQUAL_64(0x01234567, data3[0]);
-    ASSERT_EQUAL_64(0xffffffff, data4[0]);
-    ASSERT_EQUAL_64(0x01234567, data5[0]);
-    ASSERT_EQUAL_64(0xffffffff, data6[0]);
-    ASSERT_EQUAL_64(0x01234567, data7[0]);
-    ASSERT_EQUAL_64(0xffffffff, data8[0]);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data1);
+    ASSERT_EQUAL_64(0x01234567ffffffff, data2);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data3);
+    ASSERT_EQUAL_64(0xffffffff89abcdef, data4);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data5);
+    ASSERT_EQUAL_64(0x01234567ffffffff, data6);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data7);
+    ASSERT_EQUAL_64(0xffffffff89abcdef, data8);
   }
 }
 
 TEST(cas_casa_casl_casal_x) {
-  uint64_t data1[] = {0x0123456789abcdef, 0};
-  uint64_t data2[] = {0x0123456789abcdef, 0};
-  uint64_t data3[] = {0x0123456789abcdef, 0};
-  uint64_t data4[] = {0x0123456789abcdef, 0};
-  uint64_t data5[] = {0x0123456789abcdef, 0};
-  uint64_t data6[] = {0x0123456789abcdef, 0};
-  uint64_t data7[] = {0x0123456789abcdef, 0};
-  uint64_t data8[] = {0x0123456789abcdef, 0};
-
-  uint64_t* data1_aligned = AlignUp(data1, kXRegSizeInBytes * 2);
-  uint64_t* data2_aligned = AlignUp(data2, kXRegSizeInBytes * 2);
-  uint64_t* data3_aligned = AlignUp(data3, kXRegSizeInBytes * 2);
-  uint64_t* data4_aligned = AlignUp(data4, kXRegSizeInBytes * 2);
-  uint64_t* data5_aligned = AlignUp(data5, kXRegSizeInBytes * 2);
-  uint64_t* data6_aligned = AlignUp(data6, kXRegSizeInBytes * 2);
-  uint64_t* data7_aligned = AlignUp(data7, kXRegSizeInBytes * 2);
-  uint64_t* data8_aligned = AlignUp(data8, kXRegSizeInBytes * 2);
+  uint64_t data1 = 0x0123456789abcdef;
+  uint64_t data2 = 0x0123456789abcdef;
+  uint64_t data3 = 0x0123456789abcdef;
+  uint64_t data4 = 0x0123456789abcdef;
+  uint64_t data5 = 0x0123456789abcdef;
+  uint64_t data6 = 0x0123456789abcdef;
+  uint64_t data7 = 0x0123456789abcdef;
+  uint64_t data8 = 0x0123456789abcdef;
 
   SETUP_WITH_FEATURES(CPUFeatures::kAtomics);
 
   START();
 
-  __ Mov(x21, reinterpret_cast<uintptr_t>(data1_aligned));
-  __ Mov(x22, reinterpret_cast<uintptr_t>(data2_aligned));
-  __ Mov(x23, reinterpret_cast<uintptr_t>(data3_aligned));
-  __ Mov(x24, reinterpret_cast<uintptr_t>(data4_aligned));
-  __ Mov(x25, reinterpret_cast<uintptr_t>(data5_aligned));
-  __ Mov(x26, reinterpret_cast<uintptr_t>(data6_aligned));
-  __ Mov(x27, reinterpret_cast<uintptr_t>(data7_aligned));
-  __ Mov(x28, reinterpret_cast<uintptr_t>(data8_aligned));
+  __ Mov(x21, reinterpret_cast<uintptr_t>(&data1));
+  __ Mov(x22, reinterpret_cast<uintptr_t>(&data2));
+  __ Mov(x23, reinterpret_cast<uintptr_t>(&data3));
+  __ Mov(x24, reinterpret_cast<uintptr_t>(&data4));
+  __ Mov(x25, reinterpret_cast<uintptr_t>(&data5));
+  __ Mov(x26, reinterpret_cast<uintptr_t>(&data6));
+  __ Mov(x27, reinterpret_cast<uintptr_t>(&data7));
+  __ Mov(x28, reinterpret_cast<uintptr_t>(&data8));
 
   __ Mov(x0, 0xffffffffffffffff);
 
@@ -9888,59 +9937,50 @@ TEST(cas_casa_casl_casal_x) {
     ASSERT_EQUAL_64(0x0123456789abcdef, x7);
     ASSERT_EQUAL_64(0x0123456789abcdef, x8);
 
-    ASSERT_EQUAL_64(0x0123456789abcdef, data1[0]);
-    ASSERT_EQUAL_64(0xffffffffffffffff, data2[0]);
-    ASSERT_EQUAL_64(0x0123456789abcdef, data3[0]);
-    ASSERT_EQUAL_64(0xffffffffffffffff, data4[0]);
-    ASSERT_EQUAL_64(0x0123456789abcdef, data5[0]);
-    ASSERT_EQUAL_64(0xffffffffffffffff, data6[0]);
-    ASSERT_EQUAL_64(0x0123456789abcdef, data7[0]);
-    ASSERT_EQUAL_64(0xffffffffffffffff, data8[0]);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data1);
+    ASSERT_EQUAL_64(0xffffffffffffffff, data2);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data3);
+    ASSERT_EQUAL_64(0xffffffffffffffff, data4);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data5);
+    ASSERT_EQUAL_64(0xffffffffffffffff, data6);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data7);
+    ASSERT_EQUAL_64(0xffffffffffffffff, data8);
   }
 }
 
 TEST(casb_casab_caslb_casalb) {
-  uint64_t data1[] = {0x01234567, 0};
-  uint64_t data2[] = {0x01234567, 0};
-  uint64_t data3[] = {0x01234567, 0};
-  uint64_t data4[] = {0x01234567, 0};
-  uint64_t data5[] = {0x01234567, 0};
-  uint64_t data6[] = {0x01234567, 0};
-  uint64_t data7[] = {0x01234567, 0};
-  uint64_t data8[] = {0x01234567, 0};
-
-  uint64_t* data1_aligned = AlignUp(data1, kXRegSizeInBytes * 2);
-  uint64_t* data2_aligned = AlignUp(data2, kXRegSizeInBytes * 2);
-  uint64_t* data3_aligned = AlignUp(data3, kXRegSizeInBytes * 2);
-  uint64_t* data4_aligned = AlignUp(data4, kXRegSizeInBytes * 2);
-  uint64_t* data5_aligned = AlignUp(data5, kXRegSizeInBytes * 2);
-  uint64_t* data6_aligned = AlignUp(data6, kXRegSizeInBytes * 2);
-  uint64_t* data7_aligned = AlignUp(data7, kXRegSizeInBytes * 2);
-  uint64_t* data8_aligned = AlignUp(data8, kXRegSizeInBytes * 2);
+  uint32_t data1 = 0x01234567;
+  uint32_t data2 = 0x01234567;
+  uint32_t data3 = 0x01234567;
+  uint32_t data4 = 0x01234567;
+  uint32_t data5 = 0x01234567;
+  uint32_t data6 = 0x01234567;
+  uint32_t data7 = 0x01234567;
+  uint32_t data8 = 0x01234567;
 
   SETUP_WITH_FEATURES(CPUFeatures::kAtomics);
 
   START();
 
-  __ Mov(x21, reinterpret_cast<uintptr_t>(data1_aligned));
-  __ Mov(x22, reinterpret_cast<uintptr_t>(data2_aligned));
-  __ Mov(x23, reinterpret_cast<uintptr_t>(data3_aligned));
-  __ Mov(x24, reinterpret_cast<uintptr_t>(data4_aligned));
-  __ Mov(x25, reinterpret_cast<uintptr_t>(data5_aligned));
-  __ Mov(x26, reinterpret_cast<uintptr_t>(data6_aligned));
-  __ Mov(x27, reinterpret_cast<uintptr_t>(data7_aligned));
-  __ Mov(x28, reinterpret_cast<uintptr_t>(data8_aligned));
+  __ Mov(x21, reinterpret_cast<uintptr_t>(&data1) + 0);
+  __ Mov(x22, reinterpret_cast<uintptr_t>(&data2) + 0);
+  __ Mov(x23, reinterpret_cast<uintptr_t>(&data3) + 1);
+  __ Mov(x24, reinterpret_cast<uintptr_t>(&data4) + 1);
+  __ Mov(x25, reinterpret_cast<uintptr_t>(&data5) + 2);
+  __ Mov(x26, reinterpret_cast<uintptr_t>(&data6) + 2);
+  __ Mov(x27, reinterpret_cast<uintptr_t>(&data7) + 3);
+  __ Mov(x28, reinterpret_cast<uintptr_t>(&data8) + 3);
 
-  __ Mov(x0, 0xffffffff);
+  __ Mov(x0, 0xff);
 
   __ Mov(x1, 0x76543210);
   __ Mov(x2, 0x01234567);
   __ Mov(x3, 0x76543210);
-  __ Mov(x4, 0x01234567);
+  __ Mov(x4, 0x67012345);
   __ Mov(x5, 0x76543210);
-  __ Mov(x6, 0x01234567);
+  __ Mov(x6, 0x45670123);
   __ Mov(x7, 0x76543210);
-  __ Mov(x8, 0x01234567);
+  __ Mov(x8, 0x23456701);
 
   __ Casb(w1, w0, MemOperand(x21));
   __ Casb(w2, w0, MemOperand(x22));
@@ -9958,66 +9998,57 @@ TEST(casb_casab_caslb_casalb) {
 
     ASSERT_EQUAL_64(0x00000067, x1);
     ASSERT_EQUAL_64(0x00000067, x2);
-    ASSERT_EQUAL_64(0x00000067, x3);
-    ASSERT_EQUAL_64(0x00000067, x4);
-    ASSERT_EQUAL_64(0x00000067, x5);
-    ASSERT_EQUAL_64(0x00000067, x6);
-    ASSERT_EQUAL_64(0x00000067, x7);
-    ASSERT_EQUAL_64(0x00000067, x8);
+    ASSERT_EQUAL_64(0x00000045, x3);
+    ASSERT_EQUAL_64(0x00000045, x4);
+    ASSERT_EQUAL_64(0x00000023, x5);
+    ASSERT_EQUAL_64(0x00000023, x6);
+    ASSERT_EQUAL_64(0x00000001, x7);
+    ASSERT_EQUAL_64(0x00000001, x8);
 
-    ASSERT_EQUAL_64(0x01234567, data1[0]);
-    ASSERT_EQUAL_64(0x012345ff, data2[0]);
-    ASSERT_EQUAL_64(0x01234567, data3[0]);
-    ASSERT_EQUAL_64(0x012345ff, data4[0]);
-    ASSERT_EQUAL_64(0x01234567, data5[0]);
-    ASSERT_EQUAL_64(0x012345ff, data6[0]);
-    ASSERT_EQUAL_64(0x01234567, data7[0]);
-    ASSERT_EQUAL_64(0x012345ff, data8[0]);
+    ASSERT_EQUAL_64(0x01234567, data1);
+    ASSERT_EQUAL_64(0x012345ff, data2);
+    ASSERT_EQUAL_64(0x01234567, data3);
+    ASSERT_EQUAL_64(0x0123ff67, data4);
+    ASSERT_EQUAL_64(0x01234567, data5);
+    ASSERT_EQUAL_64(0x01ff4567, data6);
+    ASSERT_EQUAL_64(0x01234567, data7);
+    ASSERT_EQUAL_64(0xff234567, data8);
   }
 }
 
 TEST(cash_casah_caslh_casalh) {
-  uint64_t data1[] = {0x01234567, 0};
-  uint64_t data2[] = {0x01234567, 0};
-  uint64_t data3[] = {0x01234567, 0};
-  uint64_t data4[] = {0x01234567, 0};
-  uint64_t data5[] = {0x01234567, 0};
-  uint64_t data6[] = {0x01234567, 0};
-  uint64_t data7[] = {0x01234567, 0};
-  uint64_t data8[] = {0x01234567, 0};
-
-  uint64_t* data1_aligned = AlignUp(data1, kXRegSizeInBytes * 2);
-  uint64_t* data2_aligned = AlignUp(data2, kXRegSizeInBytes * 2);
-  uint64_t* data3_aligned = AlignUp(data3, kXRegSizeInBytes * 2);
-  uint64_t* data4_aligned = AlignUp(data4, kXRegSizeInBytes * 2);
-  uint64_t* data5_aligned = AlignUp(data5, kXRegSizeInBytes * 2);
-  uint64_t* data6_aligned = AlignUp(data6, kXRegSizeInBytes * 2);
-  uint64_t* data7_aligned = AlignUp(data7, kXRegSizeInBytes * 2);
-  uint64_t* data8_aligned = AlignUp(data8, kXRegSizeInBytes * 2);
+  uint64_t data1 = 0x0123456789abcdef;
+  uint64_t data2 = 0x0123456789abcdef;
+  uint64_t data3 = 0x0123456789abcdef;
+  uint64_t data4 = 0x0123456789abcdef;
+  uint64_t data5 = 0x0123456789abcdef;
+  uint64_t data6 = 0x0123456789abcdef;
+  uint64_t data7 = 0x0123456789abcdef;
+  uint64_t data8 = 0x0123456789abcdef;
 
   SETUP_WITH_FEATURES(CPUFeatures::kAtomics);
 
   START();
 
-  __ Mov(x21, reinterpret_cast<uintptr_t>(data1_aligned));
-  __ Mov(x22, reinterpret_cast<uintptr_t>(data2_aligned));
-  __ Mov(x23, reinterpret_cast<uintptr_t>(data3_aligned));
-  __ Mov(x24, reinterpret_cast<uintptr_t>(data4_aligned));
-  __ Mov(x25, reinterpret_cast<uintptr_t>(data5_aligned));
-  __ Mov(x26, reinterpret_cast<uintptr_t>(data6_aligned));
-  __ Mov(x27, reinterpret_cast<uintptr_t>(data7_aligned));
-  __ Mov(x28, reinterpret_cast<uintptr_t>(data8_aligned));
+  __ Mov(x21, reinterpret_cast<uintptr_t>(&data1) + 0);
+  __ Mov(x22, reinterpret_cast<uintptr_t>(&data2) + 0);
+  __ Mov(x23, reinterpret_cast<uintptr_t>(&data3) + 2);
+  __ Mov(x24, reinterpret_cast<uintptr_t>(&data4) + 2);
+  __ Mov(x25, reinterpret_cast<uintptr_t>(&data5) + 4);
+  __ Mov(x26, reinterpret_cast<uintptr_t>(&data6) + 4);
+  __ Mov(x27, reinterpret_cast<uintptr_t>(&data7) + 6);
+  __ Mov(x28, reinterpret_cast<uintptr_t>(&data8) + 6);
 
-  __ Mov(x0, 0xffffffff);
+  __ Mov(x0, 0xffff);
 
-  __ Mov(x1, 0x76543210);
-  __ Mov(x2, 0x01234567);
-  __ Mov(x3, 0x76543210);
-  __ Mov(x4, 0x01234567);
-  __ Mov(x5, 0x76543210);
-  __ Mov(x6, 0x01234567);
-  __ Mov(x7, 0x76543210);
-  __ Mov(x8, 0x01234567);
+  __ Mov(x1, 0xfedcba9876543210);
+  __ Mov(x2, 0x0123456789abcdef);
+  __ Mov(x3, 0xfedcba9876543210);
+  __ Mov(x4, 0xcdef0123456789ab);
+  __ Mov(x5, 0xfedcba9876543210);
+  __ Mov(x6, 0x89abcdef01234567);
+  __ Mov(x7, 0xfedcba9876543210);
+  __ Mov(x8, 0x456789abcdef0123);
 
   __ Cash(w1, w0, MemOperand(x21));
   __ Cash(w2, w0, MemOperand(x22));
@@ -10033,80 +10064,71 @@ TEST(cash_casah_caslh_casalh) {
   if (CAN_RUN()) {
     RUN();
 
-    ASSERT_EQUAL_64(0x00004567, x1);
-    ASSERT_EQUAL_64(0x00004567, x2);
-    ASSERT_EQUAL_64(0x00004567, x3);
-    ASSERT_EQUAL_64(0x00004567, x4);
+    ASSERT_EQUAL_64(0x0000cdef, x1);
+    ASSERT_EQUAL_64(0x0000cdef, x2);
+    ASSERT_EQUAL_64(0x000089ab, x3);
+    ASSERT_EQUAL_64(0x000089ab, x4);
     ASSERT_EQUAL_64(0x00004567, x5);
     ASSERT_EQUAL_64(0x00004567, x6);
-    ASSERT_EQUAL_64(0x00004567, x7);
-    ASSERT_EQUAL_64(0x00004567, x8);
-
-    ASSERT_EQUAL_64(0x01234567, data1[0]);
-    ASSERT_EQUAL_64(0x0123ffff, data2[0]);
-    ASSERT_EQUAL_64(0x01234567, data3[0]);
-    ASSERT_EQUAL_64(0x0123ffff, data4[0]);
-    ASSERT_EQUAL_64(0x01234567, data5[0]);
-    ASSERT_EQUAL_64(0x0123ffff, data6[0]);
-    ASSERT_EQUAL_64(0x01234567, data7[0]);
-    ASSERT_EQUAL_64(0x0123ffff, data8[0]);
-  }
-}
-
-TEST(casp_caspa_caspl_caspal) {
-  uint64_t data1[] = {0x89abcdef01234567, 0};
-  uint64_t data2[] = {0x89abcdef01234567, 0};
-  uint64_t data3[] = {0x89abcdef01234567, 0};
-  uint64_t data4[] = {0x89abcdef01234567, 0};
-  uint64_t data5[] = {0x89abcdef01234567, 0};
-  uint64_t data6[] = {0x89abcdef01234567, 0};
-  uint64_t data7[] = {0x89abcdef01234567, 0};
-  uint64_t data8[] = {0x89abcdef01234567, 0};
-
-  uint64_t* data1_aligned = AlignUp(data1, kXRegSizeInBytes * 2);
-  uint64_t* data2_aligned = AlignUp(data2, kXRegSizeInBytes * 2);
-  uint64_t* data3_aligned = AlignUp(data3, kXRegSizeInBytes * 2);
-  uint64_t* data4_aligned = AlignUp(data4, kXRegSizeInBytes * 2);
-  uint64_t* data5_aligned = AlignUp(data5, kXRegSizeInBytes * 2);
-  uint64_t* data6_aligned = AlignUp(data6, kXRegSizeInBytes * 2);
-  uint64_t* data7_aligned = AlignUp(data7, kXRegSizeInBytes * 2);
-  uint64_t* data8_aligned = AlignUp(data8, kXRegSizeInBytes * 2);
+    ASSERT_EQUAL_64(0x00000123, x7);
+    ASSERT_EQUAL_64(0x00000123, x8);
+
+    ASSERT_EQUAL_64(0x0123456789abcdef, data1);
+    ASSERT_EQUAL_64(0x0123456789abffff, data2);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data3);
+    ASSERT_EQUAL_64(0x01234567ffffcdef, data4);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data5);
+    ASSERT_EQUAL_64(0x0123ffff89abcdef, data6);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data7);
+    ASSERT_EQUAL_64(0xffff456789abcdef, data8);
+  }
+}
+
+TEST(casp_caspa_caspl_caspal_w) {
+  uint64_t data1[] = {0x7766554433221100, 0xffeeddccbbaa9988};
+  uint64_t data2[] = {0x7766554433221100, 0xffeeddccbbaa9988};
+  uint64_t data3[] = {0x7766554433221100, 0xffeeddccbbaa9988};
+  uint64_t data4[] = {0x7766554433221100, 0xffeeddccbbaa9988};
+  uint64_t data5[] = {0x7766554433221100, 0xffeeddccbbaa9988};
+  uint64_t data6[] = {0x7766554433221100, 0xffeeddccbbaa9988};
+  uint64_t data7[] = {0x7766554433221100, 0xffeeddccbbaa9988};
+  uint64_t data8[] = {0x7766554433221100, 0xffeeddccbbaa9988};
 
   SETUP_WITH_FEATURES(CPUFeatures::kAtomics);
 
   START();
 
-  __ Mov(x21, reinterpret_cast<uintptr_t>(data1_aligned));
-  __ Mov(x22, reinterpret_cast<uintptr_t>(data2_aligned));
-  __ Mov(x23, reinterpret_cast<uintptr_t>(data3_aligned));
-  __ Mov(x24, reinterpret_cast<uintptr_t>(data4_aligned));
-  __ Mov(x25, reinterpret_cast<uintptr_t>(data5_aligned));
-  __ Mov(x26, reinterpret_cast<uintptr_t>(data6_aligned));
-  __ Mov(x27, reinterpret_cast<uintptr_t>(data7_aligned));
-  __ Mov(x28, reinterpret_cast<uintptr_t>(data8_aligned));
+  __ Mov(x21, reinterpret_cast<uintptr_t>(data1) + 0);
+  __ Mov(x22, reinterpret_cast<uintptr_t>(data2) + 0);
+  __ Mov(x23, reinterpret_cast<uintptr_t>(data3) + 8);
+  __ Mov(x24, reinterpret_cast<uintptr_t>(data4) + 8);
+  __ Mov(x25, reinterpret_cast<uintptr_t>(data5) + 8);
+  __ Mov(x26, reinterpret_cast<uintptr_t>(data6) + 8);
+  __ Mov(x27, reinterpret_cast<uintptr_t>(data7) + 0);
+  __ Mov(x28, reinterpret_cast<uintptr_t>(data8) + 0);
 
-  __ Mov(x0, 0xffffffff);
-  __ Mov(x1, 0xffffffff);
+  __ Mov(x0, 0xfff00fff);
+  __ Mov(x1, 0xfff11fff);
 
-  __ Mov(x2, 0x76543210);
-  __ Mov(x3, 0xfedcba98);
-  __ Mov(x4, 0x89abcdef);
-  __ Mov(x5, 0x01234567);
+  __ Mov(x2, 0x77665544);
+  __ Mov(x3, 0x33221100);
+  __ Mov(x4, 0x33221100);
+  __ Mov(x5, 0x77665544);
 
-  __ Mov(x6, 0x76543210);
-  __ Mov(x7, 0xfedcba98);
-  __ Mov(x8, 0x89abcdef);
-  __ Mov(x9, 0x01234567);
+  __ Mov(x6, 0xffeeddcc);
+  __ Mov(x7, 0xbbaa9988);
+  __ Mov(x8, 0xbbaa9988);
+  __ Mov(x9, 0xffeeddcc);
 
-  __ Mov(x10, 0x76543210);
-  __ Mov(x11, 0xfedcba98);
-  __ Mov(x12, 0x89abcdef);
-  __ Mov(x13, 0x01234567);
+  __ Mov(x10, 0xffeeddcc);
+  __ Mov(x11, 0xbbaa9988);
+  __ Mov(x12, 0xbbaa9988);
+  __ Mov(x13, 0xffeeddcc);
 
-  __ Mov(x14, 0x76543210);
-  __ Mov(x15, 0xfedcba98);
-  __ Mov(x16, 0x89abcdef);
-  __ Mov(x17, 0x01234567);
+  __ Mov(x14, 0x77665544);
+  __ Mov(x15, 0x33221100);
+  __ Mov(x16, 0x33221100);
+  __ Mov(x17, 0x77665544);
 
   __ Casp(w2, w3, w0, w1, MemOperand(x21));
   __ Casp(w4, w5, w0, w1, MemOperand(x22));
@@ -10122,31 +10144,185 @@ TEST(casp_caspa_caspl_caspal) {
   if (CAN_RUN()) {
     RUN();
 
-    ASSERT_EQUAL_64(0x89abcdef, x2);
-    ASSERT_EQUAL_64(0x01234567, x3);
-    ASSERT_EQUAL_64(0x89abcdef, x4);
-    ASSERT_EQUAL_64(0x01234567, x5);
-    ASSERT_EQUAL_64(0x89abcdef, x6);
-    ASSERT_EQUAL_64(0x01234567, x7);
-    ASSERT_EQUAL_64(0x89abcdef, x8);
-    ASSERT_EQUAL_64(0x01234567, x9);
-    ASSERT_EQUAL_64(0x89abcdef, x10);
-    ASSERT_EQUAL_64(0x01234567, x11);
-    ASSERT_EQUAL_64(0x89abcdef, x12);
-    ASSERT_EQUAL_64(0x01234567, x13);
-    ASSERT_EQUAL_64(0x89abcdef, x14);
-    ASSERT_EQUAL_64(0x01234567, x15);
-    ASSERT_EQUAL_64(0x89abcdef, x16);
-    ASSERT_EQUAL_64(0x01234567, x17);
+    ASSERT_EQUAL_64(0x33221100, x2);
+    ASSERT_EQUAL_64(0x77665544, x3);
+    ASSERT_EQUAL_64(0x33221100, x4);
+    ASSERT_EQUAL_64(0x77665544, x5);
+    ASSERT_EQUAL_64(0xbbaa9988, x6);
+    ASSERT_EQUAL_64(0xffeeddcc, x7);
+    ASSERT_EQUAL_64(0xbbaa9988, x8);
+    ASSERT_EQUAL_64(0xffeeddcc, x9);
+    ASSERT_EQUAL_64(0xbbaa9988, x10);
+    ASSERT_EQUAL_64(0xffeeddcc, x11);
+    ASSERT_EQUAL_64(0xbbaa9988, x12);
+    ASSERT_EQUAL_64(0xffeeddcc, x13);
+    ASSERT_EQUAL_64(0x33221100, x14);
+    ASSERT_EQUAL_64(0x77665544, x15);
+    ASSERT_EQUAL_64(0x33221100, x16);
+    ASSERT_EQUAL_64(0x77665544, x17);
+
+    ASSERT_EQUAL_64(0x7766554433221100, data1[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data1[1]);
+    ASSERT_EQUAL_64(0xfff11ffffff00fff, data2[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data2[1]);
+    ASSERT_EQUAL_64(0x7766554433221100, data3[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data3[1]);
+    ASSERT_EQUAL_64(0x7766554433221100, data4[0]);
+    ASSERT_EQUAL_64(0xfff11ffffff00fff, data4[1]);
+    ASSERT_EQUAL_64(0x7766554433221100, data5[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data5[1]);
+    ASSERT_EQUAL_64(0x7766554433221100, data6[0]);
+    ASSERT_EQUAL_64(0xfff11ffffff00fff, data6[1]);
+    ASSERT_EQUAL_64(0x7766554433221100, data7[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data7[1]);
+    ASSERT_EQUAL_64(0xfff11ffffff00fff, data8[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data8[1]);
+  }
+}
+
+TEST(casp_caspa_caspl_caspal_x) {
+  alignas(kXRegSizeInBytes * 2) uint64_t data1[] = {0x7766554433221100,
+                                                    0xffeeddccbbaa9988,
+                                                    0xfedcba9876543210,
+                                                    0x0123456789abcdef};
+  alignas(kXRegSizeInBytes * 2) uint64_t data2[] = {0x7766554433221100,
+                                                    0xffeeddccbbaa9988,
+                                                    0xfedcba9876543210,
+                                                    0x0123456789abcdef};
+  alignas(kXRegSizeInBytes * 2) uint64_t data3[] = {0x7766554433221100,
+                                                    0xffeeddccbbaa9988,
+                                                    0xfedcba9876543210,
+                                                    0x0123456789abcdef};
+  alignas(kXRegSizeInBytes * 2) uint64_t data4[] = {0x7766554433221100,
+                                                    0xffeeddccbbaa9988,
+                                                    0xfedcba9876543210,
+                                                    0x0123456789abcdef};
+  alignas(kXRegSizeInBytes * 2) uint64_t data5[] = {0x7766554433221100,
+                                                    0xffeeddccbbaa9988,
+                                                    0xfedcba9876543210,
+                                                    0x0123456789abcdef};
+  alignas(kXRegSizeInBytes * 2) uint64_t data6[] = {0x7766554433221100,
+                                                    0xffeeddccbbaa9988,
+                                                    0xfedcba9876543210,
+                                                    0x0123456789abcdef};
+  alignas(kXRegSizeInBytes * 2) uint64_t data7[] = {0x7766554433221100,
+                                                    0xffeeddccbbaa9988,
+                                                    0xfedcba9876543210,
+                                                    0x0123456789abcdef};
+  alignas(kXRegSizeInBytes * 2) uint64_t data8[] = {0x7766554433221100,
+                                                    0xffeeddccbbaa9988,
+                                                    0xfedcba9876543210,
+                                                    0x0123456789abcdef};
+
+  SETUP_WITH_FEATURES(CPUFeatures::kAtomics);
+
+  START();
+
+  __ Mov(x21, reinterpret_cast<uintptr_t>(data1) + 0);
+  __ Mov(x22, reinterpret_cast<uintptr_t>(data2) + 0);
+  __ Mov(x23, reinterpret_cast<uintptr_t>(data3) + 16);
+  __ Mov(x24, reinterpret_cast<uintptr_t>(data4) + 16);
+  __ Mov(x25, reinterpret_cast<uintptr_t>(data5) + 16);
+  __ Mov(x26, reinterpret_cast<uintptr_t>(data6) + 16);
+  __ Mov(x27, reinterpret_cast<uintptr_t>(data7) + 0);
+  __ Mov(x28, reinterpret_cast<uintptr_t>(data8) + 0);
+
+  __ Mov(x0, 0xfffffff00fffffff);
+  __ Mov(x1, 0xfffffff11fffffff);
+
+  __ Mov(x2, 0xffeeddccbbaa9988);
+  __ Mov(x3, 0x7766554433221100);
+  __ Mov(x4, 0x7766554433221100);
+  __ Mov(x5, 0xffeeddccbbaa9988);
+
+  __ Mov(x6, 0x0123456789abcdef);
+  __ Mov(x7, 0xfedcba9876543210);
+  __ Mov(x8, 0xfedcba9876543210);
+  __ Mov(x9, 0x0123456789abcdef);
+
+  __ Mov(x10, 0x0123456789abcdef);
+  __ Mov(x11, 0xfedcba9876543210);
+  __ Mov(x12, 0xfedcba9876543210);
+  __ Mov(x13, 0x0123456789abcdef);
+
+  __ Mov(x14, 0xffeeddccbbaa9988);
+  __ Mov(x15, 0x7766554433221100);
+  __ Mov(x16, 0x7766554433221100);
+  __ Mov(x17, 0xffeeddccbbaa9988);
+
+  __ Casp(x2, x3, x0, x1, MemOperand(x21));
+  __ Casp(x4, x5, x0, x1, MemOperand(x22));
+  __ Caspa(x6, x7, x0, x1, MemOperand(x23));
+  __ Caspa(x8, x9, x0, x1, MemOperand(x24));
+  __ Caspl(x10, x11, x0, x1, MemOperand(x25));
+  __ Caspl(x12, x13, x0, x1, MemOperand(x26));
+  __ Caspal(x14, x15, x0, x1, MemOperand(x27));
+  __ Caspal(x16, x17, x0, x1, MemOperand(x28));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_64(0x7766554433221100, x2);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, x3);
+    ASSERT_EQUAL_64(0x7766554433221100, x4);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, x5);
+
+    ASSERT_EQUAL_64(0xfedcba9876543210, x6);
+    ASSERT_EQUAL_64(0x0123456789abcdef, x7);
+    ASSERT_EQUAL_64(0xfedcba9876543210, x8);
+    ASSERT_EQUAL_64(0x0123456789abcdef, x9);
+
+    ASSERT_EQUAL_64(0xfedcba9876543210, x10);
+    ASSERT_EQUAL_64(0x0123456789abcdef, x11);
+    ASSERT_EQUAL_64(0xfedcba9876543210, x12);
+    ASSERT_EQUAL_64(0x0123456789abcdef, x13);
+
+    ASSERT_EQUAL_64(0x7766554433221100, x14);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, x15);
+    ASSERT_EQUAL_64(0x7766554433221100, x16);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, x17);
+
+    ASSERT_EQUAL_64(0x7766554433221100, data1[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data1[1]);
+    ASSERT_EQUAL_64(0xfedcba9876543210, data1[2]);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data1[3]);
+
+    ASSERT_EQUAL_64(0xfffffff00fffffff, data2[0]);
+    ASSERT_EQUAL_64(0xfffffff11fffffff, data2[1]);
+    ASSERT_EQUAL_64(0xfedcba9876543210, data2[2]);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data2[3]);
+
+    ASSERT_EQUAL_64(0x7766554433221100, data3[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data3[1]);
+    ASSERT_EQUAL_64(0xfedcba9876543210, data3[2]);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data3[3]);
+
+    ASSERT_EQUAL_64(0x7766554433221100, data4[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data4[1]);
+    ASSERT_EQUAL_64(0xfffffff00fffffff, data4[2]);
+    ASSERT_EQUAL_64(0xfffffff11fffffff, data4[3]);
+
+    ASSERT_EQUAL_64(0x7766554433221100, data5[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data5[1]);
+    ASSERT_EQUAL_64(0xfedcba9876543210, data5[2]);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data5[3]);
+
+    ASSERT_EQUAL_64(0x7766554433221100, data6[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data6[1]);
+    ASSERT_EQUAL_64(0xfffffff00fffffff, data6[2]);
+    ASSERT_EQUAL_64(0xfffffff11fffffff, data6[3]);
+
+    ASSERT_EQUAL_64(0x7766554433221100, data7[0]);
+    ASSERT_EQUAL_64(0xffeeddccbbaa9988, data7[1]);
+    ASSERT_EQUAL_64(0xfedcba9876543210, data7[2]);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data7[3]);
 
-    ASSERT_EQUAL_64(0x89abcdef01234567, data1[0]);
-    ASSERT_EQUAL_64(0xffffffffffffffff, data2[0]);
-    ASSERT_EQUAL_64(0x89abcdef01234567, data3[0]);
-    ASSERT_EQUAL_64(0xffffffffffffffff, data4[0]);
-    ASSERT_EQUAL_64(0x89abcdef01234567, data5[0]);
-    ASSERT_EQUAL_64(0xffffffffffffffff, data6[0]);
-    ASSERT_EQUAL_64(0x89abcdef01234567, data7[0]);
-    ASSERT_EQUAL_64(0xffffffffffffffff, data8[0]);
+    ASSERT_EQUAL_64(0xfffffff00fffffff, data8[0]);
+    ASSERT_EQUAL_64(0xfffffff11fffffff, data8[1]);
+    ASSERT_EQUAL_64(0xfedcba9876543210, data8[2]);
+    ASSERT_EQUAL_64(0x0123456789abcdef, data8[3]);
   }
 }
 
@@ -13139,7 +13315,7 @@ TEST(runtime_calls) {
   __ Ret();
   __ Bind(&after_function);
 
-  // Call our dummy function, taking care to preserve the link register.
+  // Call our placeholder function, taking care to preserve the link register.
   __ Push(ip0, lr);
   __ Bl(&function);
   __ Pop(lr, ip0);
@@ -13240,26 +13416,6 @@ TEST(nop) {
   masm.FinalizeCode();
 }
 
-TEST(scratch_scope_basic_v) {
-  MacroAssembler masm;
-
-  {
-    UseScratchRegisterScope temps(&masm);
-    VRegister temp = temps.AcquireVRegisterOfSize(kQRegSize);
-    VIXL_CHECK(temp.Aliases(v31));
-  }
-  {
-    UseScratchRegisterScope temps(&masm);
-    VRegister temp = temps.AcquireVRegisterOfSize(kDRegSize);
-    VIXL_CHECK(temp.Aliases(v31));
-  }
-  {
-    UseScratchRegisterScope temps(&masm);
-    VRegister temp = temps.AcquireVRegisterOfSize(kSRegSize);
-    VIXL_CHECK(temp.Aliases(v31));
-  }
-}
-
 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
 // Test the pseudo-instructions that control CPUFeatures dynamically in the
 // Simulator. These are used by the test infrastructure itself, but in a fairly
@@ -13413,7 +13569,122 @@ static void SimulationCPUFeaturesScopeHelper(const CPUFeatures& base,
 TEST(configure_cpu_features_scope) {
   RunHelperWithFeatureCombinations(SimulationCPUFeaturesScopeHelper);
 }
+#endif
+
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+TEST(large_sim_stack) {
+  SimStack builder;
+  builder.SetUsableSize(16 * 1024);  // The default is 8kB.
+  SimStack::Allocated stack = builder.Allocate();
+  uintptr_t base = reinterpret_cast<uintptr_t>(stack.GetBase());
+  uintptr_t limit = reinterpret_cast<uintptr_t>(stack.GetLimit());
+  SETUP_CUSTOM_SIM(std::move(stack));
+  START();
+
+  // Check that we can access the extremes of the stack.
+  __ Mov(x0, base);
+  __ Mov(x1, limit);
+  __ Mov(x2, sp);
+  __ Add(sp, x1, 1);  // Avoid accessing memory below `sp`.
+
+  __ Mov(x10, 42);
+  __ Poke(x10, 0);
+  __ Peek(x10, base - limit - kXRegSizeInBytes - 1);
+
+  __ Mov(sp, x2);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+  }
+}
+
+#ifdef VIXL_NEGATIVE_TESTING
+TEST(sim_stack_limit_guard_read) {
+  SimStack builder;
+  SimStack::Allocated stack = builder.Allocate();
+  uintptr_t limit = reinterpret_cast<uintptr_t>(stack.GetLimit());
+  SETUP_CUSTOM_SIM(std::move(stack));
+  START();
+
+  __ Mov(x1, limit);
+  __ Mov(x2, sp);
+  __ Add(sp, x1, 1);  // Avoid accessing memory below `sp`.
+
+  // `sp` points to the lowest usable byte of the stack.
+  __ Mov(w10, 42);
+  __ Ldrb(w10, MemOperand(sp, -1));
+
+  __ Mov(sp, x2);
+
+  END();
+  if (CAN_RUN()) {
+    MUST_FAIL_WITH_MESSAGE(RUN(), "Attempt to read from stack guard region");
+  }
+}
+
+TEST(sim_stack_limit_guard_write) {
+  SimStack builder;
+  SimStack::Allocated stack = builder.Allocate();
+  uintptr_t limit = reinterpret_cast<uintptr_t>(stack.GetLimit());
+  SETUP_CUSTOM_SIM(std::move(stack));
+  START();
+
+  __ Mov(x1, limit);
+  __ Mov(x2, sp);
+  __ Add(sp, x1, 1);  // Avoid accessing memory below `sp`.
+
+  // `sp` points to the lowest usable byte of the stack.
+  __ Mov(w10, 42);
+  __ Strb(w10, MemOperand(sp, -1));
+
+  __ Mov(sp, x2);
+
+  END();
+  if (CAN_RUN()) {
+    MUST_FAIL_WITH_MESSAGE(RUN(), "Attempt to write to stack guard region");
+  }
+}
+
+TEST(sim_stack_base_guard_read) {
+  SimStack builder;
+  SimStack::Allocated stack = builder.Allocate();
+  uintptr_t base = reinterpret_cast<uintptr_t>(stack.GetBase());
+  SETUP_CUSTOM_SIM(std::move(stack));
+  START();
+
+  __ Mov(x0, base);
+  // `base` (x0) is the byte after the highest usable byte of the stack.
+  // The last byte of this access will hit the guard region.
+  __ Mov(x10, 42);
+  __ Ldr(x10, MemOperand(x0, -static_cast<int64_t>(kXRegSizeInBytes) + 1));
 
+  END();
+  if (CAN_RUN()) {
+    MUST_FAIL_WITH_MESSAGE(RUN(), "Attempt to read from stack guard region");
+  }
+}
+
+TEST(sim_stack_base_guard_write) {
+  SimStack builder;
+  SimStack::Allocated stack = builder.Allocate();
+  uintptr_t base = reinterpret_cast<uintptr_t>(stack.GetBase());
+  SETUP_CUSTOM_SIM(std::move(stack));
+  START();
+
+  __ Mov(x0, base);
+  // `base` (x0) is the byte after the highest usable byte of the stack.
+  // The last byte of this access will hit the guard region.
+  __ Mov(x10, 42);
+  __ Str(x10, MemOperand(x0, -static_cast<int64_t>(kXRegSizeInBytes) + 1));
+
+  END();
+  if (CAN_RUN()) {
+    MUST_FAIL_WITH_MESSAGE(RUN(), "Attempt to write to stack guard region");
+  }
+}
+#endif
 #endif
 
 }  // namespace aarch64
diff --git a/test/aarch64/test-assembler-aarch64.h b/test/aarch64/test-assembler-aarch64.h
index 1462918b..31e926dd 100644
--- a/test/aarch64/test-assembler-aarch64.h
+++ b/test/aarch64/test-assembler-aarch64.h
@@ -80,42 +80,51 @@ namespace aarch64 {
 #define __ masm.
 #define TEST(name) TEST_(AARCH64_ASM_##name)
 
-// PushCalleeSavedRegisters(), PopCalleeSavedRegisters() and Dump() use NEON, so
-// we need to enable it in the infrastructure code for each test.
-static const CPUFeatures kInfrastructureCPUFeatures(CPUFeatures::kNEON);
-
 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
 // Run tests with the simulator.
 
 #define SETUP()        \
   MacroAssembler masm; \
-  SETUP_COMMON()
+  SETUP_COMMON();      \
+  SETUP_COMMON_SIM()
 
 #define SETUP_WITH_FEATURES(...)                 \
   MacroAssembler masm;                           \
   SETUP_COMMON();                                \
+  SETUP_COMMON_SIM();                            \
   masm.SetCPUFeatures(CPUFeatures(__VA_ARGS__)); \
   simulator.SetCPUFeatures(CPUFeatures(__VA_ARGS__))
 
 #define SETUP_CUSTOM(size, pic)                                  \
   MacroAssembler masm(size + CodeBuffer::kDefaultCapacity, pic); \
-  SETUP_COMMON()
+  SETUP_COMMON();                                                \
+  SETUP_COMMON_SIM()
+
+#define SETUP_CUSTOM_SIM(...)                                   \
+  MacroAssembler masm;                                          \
+  SETUP_COMMON();                                               \
+  Simulator simulator(&simulator_decoder, stdout, __VA_ARGS__); \
+  simulator.SetColouredTrace(Test::coloured_trace());           \
+  simulator.SetCPUFeatures(CPUFeatures::None())
 
 #define SETUP_COMMON()                                                   \
   bool queried_can_run = false;                                          \
+  bool printed_sve_lane_warning = false;                                 \
   /* Avoid unused-variable warnings in case a test never calls RUN(). */ \
   USE(queried_can_run);                                                  \
+  USE(printed_sve_lane_warning);                                         \
   masm.SetCPUFeatures(CPUFeatures::None());                              \
   masm.SetGenerateSimulatorCode(true);                                   \
   Decoder simulator_decoder;                                             \
-  Simulator simulator(&simulator_decoder);                               \
-  simulator.SetColouredTrace(Test::coloured_trace());                    \
-  simulator.SetInstructionStats(Test::instruction_stats());              \
-  simulator.SetCPUFeatures(CPUFeatures::None());                         \
   RegisterDump core;                                                     \
   ptrdiff_t offset_after_infrastructure_start;                           \
   ptrdiff_t offset_before_infrastructure_end
 
+#define SETUP_COMMON_SIM()                            \
+  Simulator simulator(&simulator_decoder);            \
+  simulator.SetColouredTrace(Test::coloured_trace()); \
+  simulator.SetCPUFeatures(CPUFeatures::None())
+
 #define START()                                                               \
   masm.Reset();                                                               \
   simulator.ResetState();                                                     \
@@ -133,9 +142,6 @@ static const CPUFeatures kInfrastructureCPUFeatures(CPUFeatures::kNEON);
       __ Trace(static_cast<TraceParameters>(trace_parameters), TRACE_ENABLE); \
     }                                                                         \
   }                                                                           \
-  if (Test::instruction_stats()) {                                            \
-    __ EnableInstrumentation();                                               \
-  }                                                                           \
   offset_after_infrastructure_start = masm.GetCursorOffset();                 \
   /* Avoid unused-variable warnings in case a test never calls RUN(). */      \
   USE(offset_after_infrastructure_start)
@@ -144,9 +150,6 @@ static const CPUFeatures kInfrastructureCPUFeatures(CPUFeatures::kNEON);
   offset_before_infrastructure_end = masm.GetCursorOffset();             \
   /* Avoid unused-variable warnings in case a test never calls RUN(). */ \
   USE(offset_before_infrastructure_end);                                 \
-  if (Test::instruction_stats()) {                                       \
-    __ DisableInstrumentation();                                         \
-  }                                                                      \
   __ Trace(LOG_ALL, TRACE_DISABLE);                                      \
   {                                                                      \
     SimulationCPUFeaturesScope cpu(&masm, kInfrastructureCPUFeatures);   \
@@ -156,14 +159,6 @@ static const CPUFeatures kInfrastructureCPUFeatures(CPUFeatures::kNEON);
   __ Ret();                                                              \
   masm.FinalizeCode()
 
-inline bool CanRun(const CPUFeatures& required, bool* queried_can_run) {
-  // The Simulator can run any test that VIXL can assemble.
-  USE(required);
-  *queried_can_run = true;
-  return true;
-}
-
-
 #define RUN()                                                                  \
   RUN_WITHOUT_SEEN_FEATURE_CHECK();                                            \
   {                                                                            \
@@ -214,8 +209,10 @@ inline bool CanRun(const CPUFeatures& required, bool* queried_can_run) {
 
 #define SETUP_COMMON()                                                   \
   bool queried_can_run = false;                                          \
+  bool printed_sve_lane_warning = false;                                 \
   /* Avoid unused-variable warnings in case a test never calls RUN(). */ \
   USE(queried_can_run);                                                  \
+  USE(printed_sve_lane_warning);                                         \
   masm.SetCPUFeatures(CPUFeatures::None());                              \
   masm.SetGenerateSimulatorCode(false);                                  \
   RegisterDump core;                                                     \
@@ -259,32 +256,6 @@ inline bool CanRun(const CPUFeatures& required, bool* queried_can_run) {
 // We cannot run seen-feature checks when running natively.
 #define RUN_WITHOUT_SEEN_FEATURE_CHECK() RUN()
 
-inline bool CanRun(const CPUFeatures& required, bool* queried_can_run) {
-  CPUFeatures cpu = CPUFeatures::InferFromOS();
-  // If InferFromOS fails, assume that basic features are present.
-  if (cpu.HasNoFeatures()) cpu = CPUFeatures::AArch64LegacyBaseline();
-
-  VIXL_ASSERT(cpu.Has(kInfrastructureCPUFeatures));
-
-  if (cpu.Has(required)) {
-    *queried_can_run = true;
-    return true;
-  }
-
-  // Only warn if we haven't already checked CanRun(...).
-  if (!*queried_can_run) {
-    *queried_can_run = true;
-    CPUFeatures missing = required.Without(cpu);
-    // Note: This message needs to match REGEXP_MISSING_FEATURES from
-    // tools/threaded_test.py.
-    std::cout << "SKIPPED: Missing features: { " << missing << " }\n";
-    std::cout << "This test requires the following features to run its "
-                 "generated code on this CPU: "
-              << required << "\n";
-  }
-  return false;
-}
-
 #endif  // ifdef VIXL_INCLUDE_SIMULATOR_AARCH64.
 
 #define CAN_RUN() CanRun(*masm.GetCPUFeatures(), &queried_can_run)
@@ -349,6 +320,21 @@ inline bool CanRun(const CPUFeatures& required, bool* queried_can_run) {
 #define ASSERT_LITERAL_POOL_SIZE(expected) \
   VIXL_CHECK((expected + kInstructionSize) == (masm.GetLiteralPoolSize()))
 
+#define ASSERT_EQUAL_SVE_LANE(expected, result, lane) \
+  VIXL_CHECK(EqualSVELane(expected, &core, result, lane));
+
+// If `expected` is scalar, check that every lane of `result` matches it.
+// If `expected` is an array of N expected values, check that the first N
+// lanes on `result` match. The rightmost (highest-indexed) array element maps
+// to the lowest-numbered lane.
+#define ASSERT_EQUAL_SVE(expected, result) \
+  VIXL_CHECK(EqualSVE(expected, &core, result, &printed_sve_lane_warning))
+
+#define ASSERT_EQUAL_MEMORY(expected, result, ...)          \
+  VIXL_CHECK(EqualMemory(reinterpret_cast<void*>(expected), \
+                         reinterpret_cast<void*>(result),   \
+                         __VA_ARGS__))
+
 #define MUST_FAIL_WITH_MESSAGE(code, message)                     \
   {                                                               \
     bool aborted = false;                                         \
diff --git a/test/aarch64/test-assembler-fp-aarch64.cc b/test/aarch64/test-assembler-fp-aarch64.cc
index e4c9b594..b9a581e7 100644
--- a/test/aarch64/test-assembler-fp-aarch64.cc
+++ b/test/aarch64/test-assembler-fp-aarch64.cc
@@ -285,7 +285,7 @@ void LoadFPValueHelper(T values[], int card) {
   SETUP_WITH_FEATURES(CPUFeatures::kFP);
 
   const bool is_32bits = (sizeof(T) == 4);
-  const VRegister& fp_tgt = is_32bits ? s2 : d2;
+  const VRegister& fp_tgt = is_32bits ? VRegister(s2) : VRegister(d2);
   const Register& tgt1 = is_32bits ? Register(w1) : Register(x1);
   const Register& tgt2 = is_32bits ? Register(w2) : Register(x2);
 
@@ -2029,9 +2029,9 @@ TEST(frint32x_s) {
   __ Fmov(s24, -0.2);
   __ Fmov(s25, kFP32DefaultNaN);
   __ Fmov(s26, INT32_MIN);
-  __ Fmov(s27, INT32_MIN + 1);
-  __ Fmov(s28, INT32_MAX);
-  __ Fmov(s29, INT32_MAX - 1);
+  __ Fmov(s27, INT32_MIN + 0x80);  // The next representable FP32.
+  __ Fmov(s28, 0x80000000);
+  __ Fmov(s29, 0x7fffff80);  // The largest int32_t representable as FP32.
   __ Fmov(s30, FLT_MIN);
   __ Fmov(s31, FLT_MAX);
 
@@ -2072,11 +2072,11 @@ TEST(frint32x_s) {
     ASSERT_EQUAL_FP32(0.0, s9);
     ASSERT_EQUAL_FP32(-0.0, s10);
     ASSERT_EQUAL_FP32(-0.0, s11);
-    ASSERT_EQUAL_FP32(INT32_MIN, s12);
+    ASSERT_EQUAL_FP32(INT32_MIN, s12);  // NaN.
     ASSERT_EQUAL_FP32(INT32_MIN, s13);
-    ASSERT_EQUAL_FP32(INT32_MIN + 1, s14);
-    ASSERT_EQUAL_FP32(INT32_MIN, s15);
-    ASSERT_EQUAL_FP32(INT32_MIN, s16);
+    ASSERT_EQUAL_FP32(INT32_MIN + 0x80, s14);
+    ASSERT_EQUAL_FP32(INT32_MIN, s15);  // Out of range.
+    ASSERT_EQUAL_FP32(0x7fffff80, s16);
     ASSERT_EQUAL_FP32(0, s17);
     ASSERT_EQUAL_FP32(INT32_MIN, s18);
   }
@@ -2173,9 +2173,9 @@ TEST(frint32z_s) {
   __ Fmov(s24, -0.2);
   __ Fmov(s25, kFP32DefaultNaN);
   __ Fmov(s26, INT32_MIN);
-  __ Fmov(s27, INT32_MIN + 1);
-  __ Fmov(s28, INT32_MAX);
-  __ Fmov(s29, INT32_MAX - 1);
+  __ Fmov(s27, INT32_MIN + 0x80);  // The next representable FP32.
+  __ Fmov(s28, 0x80000000);
+  __ Fmov(s29, 0x7fffff80);  // The largest int32_t representable as FP32.
   __ Fmov(s30, FLT_MIN);
   __ Fmov(s31, FLT_MAX);
 
@@ -2216,11 +2216,11 @@ TEST(frint32z_s) {
     ASSERT_EQUAL_FP32(0.0, s9);
     ASSERT_EQUAL_FP32(-0.0, s10);
     ASSERT_EQUAL_FP32(-0.0, s11);
-    ASSERT_EQUAL_FP32(INT32_MIN, s12);
+    ASSERT_EQUAL_FP32(INT32_MIN, s12);  // NaN.
     ASSERT_EQUAL_FP32(INT32_MIN, s13);
-    ASSERT_EQUAL_FP32(INT32_MIN + 1, s14);
-    ASSERT_EQUAL_FP32(INT32_MIN, s15);
-    ASSERT_EQUAL_FP32(INT32_MIN, s16);
+    ASSERT_EQUAL_FP32(INT32_MIN + 0x80, s14);
+    ASSERT_EQUAL_FP32(INT32_MIN, s15);  // Out of range.
+    ASSERT_EQUAL_FP32(0x7fffff80, s16);
     ASSERT_EQUAL_FP32(0, s17);
     ASSERT_EQUAL_FP32(INT32_MIN, s18);
   }
@@ -2317,9 +2317,10 @@ TEST(frint64x_s) {
   __ Fmov(s24, -0.2);
   __ Fmov(s25, kFP64DefaultNaN);
   __ Fmov(s26, INT64_MIN);
-  __ Fmov(s27, INT64_MIN + 1);
-  __ Fmov(s28, INT64_MAX);
-  __ Fmov(s29, INT64_MAX - 1);
+  __ Fmov(s27, INT64_MIN + 0x80'00000000);  // The next representable FP32.
+  __ Fmov(s28, 0x80000000'00000000);
+  // The largest int64_t representable as FP32.
+  __ Fmov(s29, 0x7fffff80'00000000);
   __ Fmov(s30, FLT_MIN);
   __ Fmov(s31, FLT_MAX);
 
@@ -2360,11 +2361,11 @@ TEST(frint64x_s) {
     ASSERT_EQUAL_FP32(0.0, s9);
     ASSERT_EQUAL_FP32(-0.0, s10);
     ASSERT_EQUAL_FP32(-0.0, s11);
-    ASSERT_EQUAL_FP32(INT64_MIN, s12);
+    ASSERT_EQUAL_FP32(INT64_MIN, s12);  // Nan.
     ASSERT_EQUAL_FP32(INT64_MIN, s13);
-    ASSERT_EQUAL_FP32(INT64_MIN + 1, s14);
-    ASSERT_EQUAL_FP32(INT64_MAX, s15);
-    ASSERT_EQUAL_FP32(INT64_MAX - 1, s16);
+    ASSERT_EQUAL_FP32(INT64_MIN + 0x80'00000000, s14);
+    ASSERT_EQUAL_FP32(INT64_MIN, s15);  // Out of range.
+    ASSERT_EQUAL_FP32(0x7fffff80'00000000, s16);
     ASSERT_EQUAL_FP32(0, s17);
     ASSERT_EQUAL_FP32(INT64_MIN, s18);
   }
@@ -2389,9 +2390,10 @@ TEST(frint64x_d) {
   __ Fmov(d24, -0.2);
   __ Fmov(d25, kFP64DefaultNaN);
   __ Fmov(d26, INT64_MIN);
-  __ Fmov(d27, INT64_MIN + 1);
-  __ Fmov(d28, INT64_MAX);
-  __ Fmov(d29, INT64_MAX - 1);
+  __ Fmov(d27, INT64_MIN + 0x400);  // The next representable FP64.
+  __ Fmov(d28, 0x80000000'00000000);
+  // The largest int64_t representable as FP64.
+  __ Fmov(d29, 0x7fffffff'fffffc00);
   __ Fmov(d30, FLT_MIN);
   __ Fmov(d31, FLT_MAX);
 
@@ -2432,11 +2434,11 @@ TEST(frint64x_d) {
     ASSERT_EQUAL_FP64(0.0, d9);
     ASSERT_EQUAL_FP64(-0.0, d10);
     ASSERT_EQUAL_FP64(-0.0, d11);
-    ASSERT_EQUAL_FP64(INT64_MIN, d12);
+    ASSERT_EQUAL_FP64(INT64_MIN, d12);  // NaN.
     ASSERT_EQUAL_FP64(INT64_MIN, d13);
-    ASSERT_EQUAL_FP64(INT64_MIN, d14);
-    ASSERT_EQUAL_FP64(INT64_MAX, d15);
-    ASSERT_EQUAL_FP64(INT64_MAX, d16);
+    ASSERT_EQUAL_FP64(INT64_MIN + 0x400, d14);
+    ASSERT_EQUAL_FP64(INT64_MIN, d15);  // Out of range.
+    ASSERT_EQUAL_FP64(0x7fffffff'fffffc00, d16);
     ASSERT_EQUAL_FP64(0, d17);
     ASSERT_EQUAL_FP64(INT64_MIN, d18);
   }
@@ -2461,9 +2463,10 @@ TEST(frint64z_s) {
   __ Fmov(s24, -0.2);
   __ Fmov(s25, kFP64DefaultNaN);
   __ Fmov(s26, INT64_MIN);
-  __ Fmov(s27, INT64_MIN + 1);
-  __ Fmov(s28, INT64_MAX);
-  __ Fmov(s29, INT64_MAX - 1);
+  __ Fmov(s27, INT64_MIN + 0x80'00000000);  // The next representable FP32.
+  __ Fmov(s28, 0x80000000'00000000);
+  // The largest int64_t representable as FP32.
+  __ Fmov(s29, 0x7fffff80'00000000);
   __ Fmov(s30, FLT_MIN);
   __ Fmov(s31, FLT_MAX);
 
@@ -2504,11 +2507,11 @@ TEST(frint64z_s) {
     ASSERT_EQUAL_FP32(0.0, s9);
     ASSERT_EQUAL_FP32(-0.0, s10);
     ASSERT_EQUAL_FP32(-0.0, s11);
-    ASSERT_EQUAL_FP32(INT64_MIN, s12);
+    ASSERT_EQUAL_FP32(INT64_MIN, s12);  // Nan.
     ASSERT_EQUAL_FP32(INT64_MIN, s13);
-    ASSERT_EQUAL_FP32(INT64_MIN + 1, s14);
-    ASSERT_EQUAL_FP32(INT64_MAX, s15);
-    ASSERT_EQUAL_FP32(INT64_MAX - 1, s16);
+    ASSERT_EQUAL_FP32(INT64_MIN + 0x80'00000000, s14);
+    ASSERT_EQUAL_FP32(INT64_MIN, s15);  // Out of range.
+    ASSERT_EQUAL_FP32(0x7fffff80'00000000, s16);
     ASSERT_EQUAL_FP32(0, s17);
     ASSERT_EQUAL_FP32(INT64_MIN, s18);
   }
@@ -2533,9 +2536,10 @@ TEST(frint64z_d) {
   __ Fmov(d24, -0.2);
   __ Fmov(d25, kFP64DefaultNaN);
   __ Fmov(d26, INT64_MIN);
-  __ Fmov(d27, INT64_MIN + 1);
-  __ Fmov(d28, INT64_MAX);
-  __ Fmov(d29, INT64_MAX - 1);
+  __ Fmov(d27, INT64_MIN + 0x400);  // The next representable FP64.
+  __ Fmov(d28, 0x80000000'00000000);
+  // The largest int64_t representable as FP64.
+  __ Fmov(d29, 0x7fffffff'fffffc00);
   __ Fmov(d30, FLT_MIN);
   __ Fmov(d31, FLT_MAX);
 
@@ -2576,11 +2580,11 @@ TEST(frint64z_d) {
     ASSERT_EQUAL_FP64(0.0, d9);
     ASSERT_EQUAL_FP64(-0.0, d10);
     ASSERT_EQUAL_FP64(-0.0, d11);
-    ASSERT_EQUAL_FP64(INT64_MIN, d12);
+    ASSERT_EQUAL_FP64(INT64_MIN, d12);  // NaN.
     ASSERT_EQUAL_FP64(INT64_MIN, d13);
-    ASSERT_EQUAL_FP64(INT64_MIN, d14);
-    ASSERT_EQUAL_FP64(INT64_MAX, d15);
-    ASSERT_EQUAL_FP64(INT64_MAX, d16);
+    ASSERT_EQUAL_FP64(INT64_MIN + 0x400, d14);
+    ASSERT_EQUAL_FP64(INT64_MIN, d15);  // Out of range.
+    ASSERT_EQUAL_FP64(0x7fffffff'fffffc00, d16);
     ASSERT_EQUAL_FP64(0, d17);
     ASSERT_EQUAL_FP64(INT64_MIN, d18);
   }
diff --git a/test/aarch64/test-assembler-neon-aarch64.cc b/test/aarch64/test-assembler-neon-aarch64.cc
index c3643eed..d2e04052 100644
--- a/test/aarch64/test-assembler-neon-aarch64.cc
+++ b/test/aarch64/test-assembler-neon-aarch64.cc
@@ -9482,7 +9482,7 @@ TEST(neon_byelement_fhm) {
   __ Movi(v31.V8H(), 0x3bff3c013bff3c01, 0x3bff3c013bff3c01);
   // Set up [v8,v15] as vm inputs.
   for (int i = 0; i <= 7; i++) {
-    VRegister vm = VRegister::GetVRegFromCode(i + 8);
+    VRegister vm(i + 8);
     __ Mov(vm, poison);
     __ Ins(vm.V8H(), i, v31.V8H(), i);
   }
diff --git a/test/aarch64/test-assembler-sve-aarch64.cc b/test/aarch64/test-assembler-sve-aarch64.cc
new file mode 100644
index 00000000..7f0c178b
--- /dev/null
+++ b/test/aarch64/test-assembler-sve-aarch64.cc
@@ -0,0 +1,18692 @@
+// Copyright 2019, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include <sys/mman.h>
+#include <unistd.h>
+
+#include <cfloat>
+#include <cmath>
+#include <cstdio>
+#include <cstdlib>
+#include <cstring>
+#include <functional>
+
+#include "test-runner.h"
+#include "test-utils.h"
+#include "aarch64/test-utils-aarch64.h"
+
+#include "aarch64/cpu-aarch64.h"
+#include "aarch64/disasm-aarch64.h"
+#include "aarch64/macro-assembler-aarch64.h"
+#include "aarch64/simulator-aarch64.h"
+#include "test-assembler-aarch64.h"
+
+namespace vixl {
+namespace aarch64 {
+
+Test* MakeSVETest(int vl, const char* name, Test::TestFunctionWithConfig* fn) {
+  // We never free this memory, but we need it to live for as long as the static
+  // linked list of tests, and this is the easiest way to do it.
+  Test* test = new Test(name, fn);
+  test->set_sve_vl_in_bits(vl);
+  return test;
+}
+
+// The TEST_SVE macro works just like the usual TEST macro, but the resulting
+// function receives a `const Test& config` argument, to allow it to query the
+// vector length.
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+// On the Simulator, run SVE tests with several vector lengths, including the
+// extreme values and an intermediate value that isn't a power of two.
+
+#define TEST_SVE(name)                                                  \
+  void Test##name(Test* config);                                        \
+  Test* test_##name##_list[] =                                          \
+      {MakeSVETest(128, "AARCH64_ASM_" #name "_vl128", &Test##name),    \
+       MakeSVETest(384, "AARCH64_ASM_" #name "_vl384", &Test##name),    \
+       MakeSVETest(2048, "AARCH64_ASM_" #name "_vl2048", &Test##name)}; \
+  void Test##name(Test* config)
+
+#define SVE_SETUP_WITH_FEATURES(...) \
+  SETUP_WITH_FEATURES(__VA_ARGS__);  \
+  simulator.SetVectorLengthInBits(config->sve_vl_in_bits())
+
+#else
+// Otherwise, just use whatever the hardware provides.
+static const int kSVEVectorLengthInBits =
+    CPUFeatures::InferFromOS().Has(CPUFeatures::kSVE)
+        ? CPU::ReadSVEVectorLengthInBits()
+        : kZRegMinSize;
+
+#define TEST_SVE(name)                                                     \
+  void Test##name(Test* config);                                           \
+  Test* test_##name##_vlauto = MakeSVETest(kSVEVectorLengthInBits,         \
+                                           "AARCH64_ASM_" #name "_vlauto", \
+                                           &Test##name);                   \
+  void Test##name(Test* config)
+
+#define SVE_SETUP_WITH_FEATURES(...) \
+  SETUP_WITH_FEATURES(__VA_ARGS__);  \
+  USE(config)
+
+#endif
+
+// Call masm->Insr repeatedly to allow test inputs to be set up concisely. This
+// is optimised for call-site clarity, not generated code quality, so it doesn't
+// exist in the MacroAssembler itself.
+//
+// Usage:
+//
+//    int values[] = { 42, 43, 44 };
+//    InsrHelper(&masm, z0.VnS(), values);    // Sets z0.S = { ..., 42, 43, 44 }
+//
+// The rightmost (highest-indexed) array element maps to the lowest-numbered
+// lane.
+template <typename T, size_t N>
+void InsrHelper(MacroAssembler* masm,
+                const ZRegister& zdn,
+                const T (&values)[N]) {
+  for (size_t i = 0; i < N; i++) {
+    masm->Insr(zdn, values[i]);
+  }
+}
+
+// Conveniently initialise P registers with scalar bit patterns. The destination
+// lane size is ignored. This is optimised for call-site clarity, not generated
+// code quality.
+//
+// Usage:
+//
+//    Initialise(&masm, p0, 0x1234);  // Sets p0 = 0b'0001'0010'0011'0100
+void Initialise(MacroAssembler* masm,
+                const PRegister& pd,
+                uint64_t value3,
+                uint64_t value2,
+                uint64_t value1,
+                uint64_t value0) {
+  // Generate a literal pool, as in the array form.
+  UseScratchRegisterScope temps(masm);
+  Register temp = temps.AcquireX();
+  Label data;
+  Label done;
+
+  masm->Adr(temp, &data);
+  masm->Ldr(pd, SVEMemOperand(temp));
+  masm->B(&done);
+  {
+    ExactAssemblyScope total(masm, kPRegMaxSizeInBytes);
+    masm->bind(&data);
+    masm->dc64(value0);
+    masm->dc64(value1);
+    masm->dc64(value2);
+    masm->dc64(value3);
+  }
+  masm->Bind(&done);
+}
+void Initialise(MacroAssembler* masm,
+                const PRegister& pd,
+                uint64_t value2,
+                uint64_t value1,
+                uint64_t value0) {
+  Initialise(masm, pd, 0, value2, value1, value0);
+}
+void Initialise(MacroAssembler* masm,
+                const PRegister& pd,
+                uint64_t value1,
+                uint64_t value0) {
+  Initialise(masm, pd, 0, 0, value1, value0);
+}
+void Initialise(MacroAssembler* masm, const PRegister& pd, uint64_t value0) {
+  Initialise(masm, pd, 0, 0, 0, value0);
+}
+
+// Conveniently initialise P registers by lane. This is optimised for call-site
+// clarity, not generated code quality.
+//
+// Usage:
+//
+//     int values[] = { 0x0, 0x1, 0x2 };
+//     Initialise(&masm, p0.VnS(), values);  // Sets p0 = 0b'0000'0001'0010
+//
+// The rightmost (highest-indexed) array element maps to the lowest-numbered
+// lane. Unspecified lanes are set to 0 (inactive).
+//
+// Each element of the `values` array is mapped onto a lane in `pd`. The
+// architecture only respects the lower bit, and writes zero the upper bits, but
+// other (encodable) values can be specified if required by the test.
+template <typename T, size_t N>
+void Initialise(MacroAssembler* masm,
+                const PRegisterWithLaneSize& pd,
+                const T (&values)[N]) {
+  // Turn the array into 64-bit chunks.
+  uint64_t chunks[4] = {0, 0, 0, 0};
+  VIXL_STATIC_ASSERT(sizeof(chunks) == kPRegMaxSizeInBytes);
+
+  int p_bits_per_lane = pd.GetLaneSizeInBits() / kZRegBitsPerPRegBit;
+  VIXL_ASSERT((64 % p_bits_per_lane) == 0);
+  VIXL_ASSERT((N * p_bits_per_lane) <= kPRegMaxSize);
+
+  uint64_t p_lane_mask = GetUintMask(p_bits_per_lane);
+
+  VIXL_STATIC_ASSERT(N <= kPRegMaxSize);
+  size_t bit = 0;
+  for (int n = static_cast<int>(N - 1); n >= 0; n--) {
+    VIXL_ASSERT(bit < (sizeof(chunks) * kBitsPerByte));
+    uint64_t value = values[n] & p_lane_mask;
+    chunks[bit / 64] |= value << (bit % 64);
+    bit += p_bits_per_lane;
+  }
+
+  Initialise(masm, pd, chunks[3], chunks[2], chunks[1], chunks[0]);
+}
+
+// Ensure that basic test infrastructure works.
+TEST_SVE(sve_test_infrastructure_z) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Mov(x0, 0x0123456789abcdef);
+
+  // Test basic `Insr` behaviour.
+  __ Insr(z0.VnB(), 1);
+  __ Insr(z0.VnB(), 2);
+  __ Insr(z0.VnB(), x0);
+  __ Insr(z0.VnB(), -42);
+  __ Insr(z0.VnB(), 0);
+
+  // Test array inputs.
+  int z1_inputs[] = {3, 4, 5, -42, 0};
+  InsrHelper(&masm, z1.VnH(), z1_inputs);
+
+  // Test that sign-extension works as intended for various lane sizes.
+  __ Dup(z2.VnD(), 0);            // Clear the register first.
+  __ Insr(z2.VnB(), -42);         //                       0xd6
+  __ Insr(z2.VnB(), 0xfe);        //                       0xfe
+  __ Insr(z2.VnH(), -42);         //                     0xffd6
+  __ Insr(z2.VnH(), 0xfedc);      //                     0xfedc
+  __ Insr(z2.VnS(), -42);         //                 0xffffffd6
+  __ Insr(z2.VnS(), 0xfedcba98);  //                 0xfedcba98
+  // Use another register for VnD(), so we can support 128-bit Z registers.
+  __ Insr(z3.VnD(), -42);                 // 0xffffffffffffffd6
+  __ Insr(z3.VnD(), 0xfedcba9876543210);  // 0xfedcba9876543210
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Test that array checks work properly on a register initialised
+    // lane-by-lane.
+    int z0_inputs_b[] = {0x01, 0x02, 0xef, 0xd6, 0x00};
+    ASSERT_EQUAL_SVE(z0_inputs_b, z0.VnB());
+
+    // Test that lane-by-lane checks work properly on a register initialised
+    // by array.
+    for (size_t i = 0; i < ArrayLength(z1_inputs); i++) {
+      // The rightmost (highest-indexed) array element maps to the
+      // lowest-numbered lane.
+      int lane = static_cast<int>(ArrayLength(z1_inputs) - i - 1);
+      ASSERT_EQUAL_SVE_LANE(z1_inputs[i], z1.VnH(), lane);
+    }
+
+    uint64_t z2_inputs_d[] = {0x0000d6feffd6fedc, 0xffffffd6fedcba98};
+    ASSERT_EQUAL_SVE(z2_inputs_d, z2.VnD());
+    uint64_t z3_inputs_d[] = {0xffffffffffffffd6, 0xfedcba9876543210};
+    ASSERT_EQUAL_SVE(z3_inputs_d, z3.VnD());
+  }
+}
+
+// Ensure that basic test infrastructure works.
+TEST_SVE(sve_test_infrastructure_p) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Simple cases: move boolean (0 or 1) values.
+
+  int p0_inputs[] = {0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0};
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  int p1_inputs[] = {1, 0, 1, 1, 0, 1, 1, 1};
+  Initialise(&masm, p1.VnH(), p1_inputs);
+
+  int p2_inputs[] = {1, 1, 0, 1};
+  Initialise(&masm, p2.VnS(), p2_inputs);
+
+  int p3_inputs[] = {0, 1};
+  Initialise(&masm, p3.VnD(), p3_inputs);
+
+  // Advanced cases: move numeric value into architecturally-ignored bits.
+
+  // B-sized lanes get one bit in a P register, so there are no ignored bits.
+
+  // H-sized lanes get two bits in a P register.
+  int p4_inputs[] = {0x3, 0x2, 0x1, 0x0, 0x1, 0x2, 0x3};
+  Initialise(&masm, p4.VnH(), p4_inputs);
+
+  // S-sized lanes get four bits in a P register.
+  int p5_inputs[] = {0xc, 0x7, 0x9, 0x6, 0xf};
+  Initialise(&masm, p5.VnS(), p5_inputs);
+
+  // D-sized lanes get eight bits in a P register.
+  int p6_inputs[] = {0x81, 0xcc, 0x55};
+  Initialise(&masm, p6.VnD(), p6_inputs);
+
+  // The largest possible P register has 32 bytes.
+  int p7_inputs[] = {0x80, 0x81, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+                     0x88, 0x89, 0x8a, 0x8b, 0x8c, 0x8d, 0x8e, 0x8f,
+                     0x90, 0x91, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97,
+                     0x98, 0x99, 0x9a, 0x9b, 0x9c, 0x9d, 0x9e, 0x9f};
+  Initialise(&masm, p7.VnD(), p7_inputs);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Test that lane-by-lane checks work properly. The rightmost
+    // (highest-indexed) array element maps to the lowest-numbered lane.
+    for (size_t i = 0; i < ArrayLength(p0_inputs); i++) {
+      int lane = static_cast<int>(ArrayLength(p0_inputs) - i - 1);
+      ASSERT_EQUAL_SVE_LANE(p0_inputs[i], p0.VnB(), lane);
+    }
+    for (size_t i = 0; i < ArrayLength(p1_inputs); i++) {
+      int lane = static_cast<int>(ArrayLength(p1_inputs) - i - 1);
+      ASSERT_EQUAL_SVE_LANE(p1_inputs[i], p1.VnH(), lane);
+    }
+    for (size_t i = 0; i < ArrayLength(p2_inputs); i++) {
+      int lane = static_cast<int>(ArrayLength(p2_inputs) - i - 1);
+      ASSERT_EQUAL_SVE_LANE(p2_inputs[i], p2.VnS(), lane);
+    }
+    for (size_t i = 0; i < ArrayLength(p3_inputs); i++) {
+      int lane = static_cast<int>(ArrayLength(p3_inputs) - i - 1);
+      ASSERT_EQUAL_SVE_LANE(p3_inputs[i], p3.VnD(), lane);
+    }
+
+    // Test that array checks work properly on predicates initialised with a
+    // possibly-different lane size.
+    // 0b...11'10'01'00'01'10'11
+    int p4_expected[] = {0x39, 0x1b};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnD());
+
+    ASSERT_EQUAL_SVE(p5_inputs, p5.VnS());
+
+    // 0b...10000001'11001100'01010101
+    int p6_expected[] = {2, 0, 0, 1, 3, 0, 3, 0, 1, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnH());
+
+    // 0b...10011100'10011101'10011110'10011111
+    int p7_expected[] = {1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1,
+                         1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, 1, 1, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnB());
+  }
+}
+
+// Test that writes to V registers clear the high bits of the corresponding Z
+// register.
+TEST_SVE(sve_v_write_clear) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kNEON,
+                          CPUFeatures::kFP,
+                          CPUFeatures::kSVE);
+  START();
+
+  // The Simulator has two mechansisms for writing V registers:
+  //  - Write*Register, calling through to SimRegisterBase::Write.
+  //  - LogicVRegister::ClearForWrite followed by one or more lane updates.
+  // Try to cover both variants.
+
+  // Prepare some known inputs.
+  uint8_t data[kQRegSizeInBytes];
+  for (size_t i = 0; i < kQRegSizeInBytes; i++) {
+    data[i] = 42 + i;
+  }
+  __ Mov(x10, reinterpret_cast<uintptr_t>(data));
+  __ Fmov(d30, 42.0);
+
+  // Use Index to label the lane indices, so failures are easy to detect and
+  // diagnose.
+  __ Index(z0.VnB(), 0, 1);
+  __ Index(z1.VnB(), 0, 1);
+  __ Index(z2.VnB(), 0, 1);
+  __ Index(z3.VnB(), 0, 1);
+  __ Index(z4.VnB(), 0, 1);
+
+  __ Index(z10.VnB(), 0, -1);
+  __ Index(z11.VnB(), 0, -1);
+  __ Index(z12.VnB(), 0, -1);
+  __ Index(z13.VnB(), 0, -1);
+  __ Index(z14.VnB(), 0, -1);
+
+  // Instructions using Write*Register (and SimRegisterBase::Write).
+  __ Ldr(b0, MemOperand(x10));
+  __ Fcvt(h1, d30);
+  __ Fmov(s2, 1.5f);
+  __ Fmov(d3, d30);
+  __ Ldr(q4, MemOperand(x10));
+
+  // Instructions using LogicVRegister::ClearForWrite.
+  // These also (incidentally) test that across-lane instructions correctly
+  // ignore the high-order Z register lanes.
+  __ Sminv(b10, v10.V16B());
+  __ Addv(h11, v11.V4H());
+  __ Saddlv(s12, v12.V8H());
+  __ Dup(v13.V8B(), b13, kDRegSizeInBytes);
+  __ Uaddl(v14.V8H(), v14.V8B(), v14.V8B());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Check the Q part first.
+    ASSERT_EQUAL_128(0x0000000000000000, 0x000000000000002a, v0);
+    ASSERT_EQUAL_128(0x0000000000000000, 0x0000000000005140, v1);  // 42.0 (f16)
+    ASSERT_EQUAL_128(0x0000000000000000, 0x000000003fc00000, v2);  // 1.5 (f32)
+    ASSERT_EQUAL_128(0x0000000000000000, 0x4045000000000000, v3);  // 42.0 (f64)
+    ASSERT_EQUAL_128(0x3938373635343332, 0x31302f2e2d2c2b2a, v4);
+    ASSERT_EQUAL_128(0x0000000000000000, 0x00000000000000f1, v10);  // -15
+    //  0xf9fa + 0xfbfc + 0xfdfe + 0xff00 -> 0xf2f4
+    ASSERT_EQUAL_128(0x0000000000000000, 0x000000000000f2f4, v11);
+    //  0xfffff1f2 + 0xfffff3f4 + ... + 0xfffffdfe + 0xffffff00 -> 0xffffc6c8
+    ASSERT_EQUAL_128(0x0000000000000000, 0x00000000ffffc6c8, v12);
+    ASSERT_EQUAL_128(0x0000000000000000, 0xf8f8f8f8f8f8f8f8, v13);  // [-8] x 8
+    //    [0x00f9, 0x00fa, 0x00fb, 0x00fc, 0x00fd, 0x00fe, 0x00ff, 0x0000]
+    //  + [0x00f9, 0x00fa, 0x00fb, 0x00fc, 0x00fd, 0x00fe, 0x00ff, 0x0000]
+    // -> [0x01f2, 0x01f4, 0x01f6, 0x01f8, 0x01fa, 0x01fc, 0x01fe, 0x0000]
+    ASSERT_EQUAL_128(0x01f201f401f601f8, 0x01fa01fc01fe0000, v14);
+
+    // Check that the upper lanes are all clear.
+    for (int i = kQRegSizeInBytes; i < core.GetSVELaneCount(kBRegSize); i++) {
+      ASSERT_EQUAL_SVE_LANE(0x00, z0.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z1.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z2.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z3.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z4.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z10.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z11.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z12.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z13.VnB(), i);
+      ASSERT_EQUAL_SVE_LANE(0x00, z14.VnB(), i);
+    }
+  }
+}
+
+static void MlaMlsHelper(Test* config, unsigned lane_size_in_bits) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int zd_inputs[] = {0xbb, 0xcc, 0xdd, 0xee};
+  int za_inputs[] = {-39, 1, -3, 2};
+  int zn_inputs[] = {-5, -20, 9, 8};
+  int zm_inputs[] = {9, -5, 4, 5};
+
+  ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
+  ZRegister za = z1.WithLaneSize(lane_size_in_bits);
+  ZRegister zn = z2.WithLaneSize(lane_size_in_bits);
+  ZRegister zm = z3.WithLaneSize(lane_size_in_bits);
+
+  // TODO: Use a simple `Dup` once it accepts arbitrary immediates.
+  InsrHelper(&masm, zd, zd_inputs);
+  InsrHelper(&masm, za, za_inputs);
+  InsrHelper(&masm, zn, zn_inputs);
+  InsrHelper(&masm, zm, zm_inputs);
+
+  int p0_inputs[] = {1, 1, 0, 1};
+  int p1_inputs[] = {1, 0, 1, 1};
+  int p2_inputs[] = {0, 1, 1, 1};
+  int p3_inputs[] = {1, 1, 1, 0};
+
+  Initialise(&masm, p0.WithLaneSize(lane_size_in_bits), p0_inputs);
+  Initialise(&masm, p1.WithLaneSize(lane_size_in_bits), p1_inputs);
+  Initialise(&masm, p2.WithLaneSize(lane_size_in_bits), p2_inputs);
+  Initialise(&masm, p3.WithLaneSize(lane_size_in_bits), p3_inputs);
+
+  // The Mla macro automatically selects between mla, mad and movprfx + mla
+  // based on what registers are aliased.
+  ZRegister mla_da_result = z10.WithLaneSize(lane_size_in_bits);
+  ZRegister mla_dn_result = z11.WithLaneSize(lane_size_in_bits);
+  ZRegister mla_dm_result = z12.WithLaneSize(lane_size_in_bits);
+  ZRegister mla_d_result = z13.WithLaneSize(lane_size_in_bits);
+
+  __ Mov(mla_da_result, za);
+  __ Mla(mla_da_result, p0.Merging(), mla_da_result, zn, zm);
+
+  __ Mov(mla_dn_result, zn);
+  __ Mla(mla_dn_result, p1.Merging(), za, mla_dn_result, zm);
+
+  __ Mov(mla_dm_result, zm);
+  __ Mla(mla_dm_result, p2.Merging(), za, zn, mla_dm_result);
+
+  __ Mov(mla_d_result, zd);
+  __ Mla(mla_d_result, p3.Merging(), za, zn, zm);
+
+  // The Mls macro automatically selects between mls, msb and movprfx + mls
+  // based on what registers are aliased.
+  ZRegister mls_da_result = z20.WithLaneSize(lane_size_in_bits);
+  ZRegister mls_dn_result = z21.WithLaneSize(lane_size_in_bits);
+  ZRegister mls_dm_result = z22.WithLaneSize(lane_size_in_bits);
+  ZRegister mls_d_result = z23.WithLaneSize(lane_size_in_bits);
+
+  __ Mov(mls_da_result, za);
+  __ Mls(mls_da_result, p0.Merging(), mls_da_result, zn, zm);
+
+  __ Mov(mls_dn_result, zn);
+  __ Mls(mls_dn_result, p1.Merging(), za, mls_dn_result, zm);
+
+  __ Mov(mls_dm_result, zm);
+  __ Mls(mls_dm_result, p2.Merging(), za, zn, mls_dm_result);
+
+  __ Mov(mls_d_result, zd);
+  __ Mls(mls_d_result, p3.Merging(), za, zn, zm);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(za_inputs, z1.WithLaneSize(lane_size_in_bits));
+    ASSERT_EQUAL_SVE(zn_inputs, z2.WithLaneSize(lane_size_in_bits));
+    ASSERT_EQUAL_SVE(zm_inputs, z3.WithLaneSize(lane_size_in_bits));
+
+    int mla[] = {-84, 101, 33, 42};
+    int mls[] = {6, -99, -39, -38};
+
+    int mla_da_expected[] = {mla[0], mla[1], za_inputs[2], mla[3]};
+    ASSERT_EQUAL_SVE(mla_da_expected, mla_da_result);
+
+    int mla_dn_expected[] = {mla[0], zn_inputs[1], mla[2], mla[3]};
+    ASSERT_EQUAL_SVE(mla_dn_expected, mla_dn_result);
+
+    int mla_dm_expected[] = {zm_inputs[0], mla[1], mla[2], mla[3]};
+    ASSERT_EQUAL_SVE(mla_dm_expected, mla_dm_result);
+
+    int mla_d_expected[] = {mla[0], mla[1], mla[2], zd_inputs[3]};
+    ASSERT_EQUAL_SVE(mla_d_expected, mla_d_result);
+
+    int mls_da_expected[] = {mls[0], mls[1], za_inputs[2], mls[3]};
+    ASSERT_EQUAL_SVE(mls_da_expected, mls_da_result);
+
+    int mls_dn_expected[] = {mls[0], zn_inputs[1], mls[2], mls[3]};
+    ASSERT_EQUAL_SVE(mls_dn_expected, mls_dn_result);
+
+    int mls_dm_expected[] = {zm_inputs[0], mls[1], mls[2], mls[3]};
+    ASSERT_EQUAL_SVE(mls_dm_expected, mls_dm_result);
+
+    int mls_d_expected[] = {mls[0], mls[1], mls[2], zd_inputs[3]};
+    ASSERT_EQUAL_SVE(mls_d_expected, mls_d_result);
+  }
+}
+
+TEST_SVE(sve_mla_mls_b) { MlaMlsHelper(config, kBRegSize); }
+TEST_SVE(sve_mla_mls_h) { MlaMlsHelper(config, kHRegSize); }
+TEST_SVE(sve_mla_mls_s) { MlaMlsHelper(config, kSRegSize); }
+TEST_SVE(sve_mla_mls_d) { MlaMlsHelper(config, kDRegSize); }
+
+TEST_SVE(sve_bitwise_unpredicate_logical) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t z8_inputs[] = {0xfedcba9876543210, 0x0123456789abcdef};
+  InsrHelper(&masm, z8.VnD(), z8_inputs);
+  uint64_t z15_inputs[] = {0xffffeeeeddddcccc, 0xccccddddeeeeffff};
+  InsrHelper(&masm, z15.VnD(), z15_inputs);
+
+  __ And(z1.VnD(), z8.VnD(), z15.VnD());
+  __ Bic(z2.VnD(), z8.VnD(), z15.VnD());
+  __ Eor(z3.VnD(), z8.VnD(), z15.VnD());
+  __ Orr(z4.VnD(), z8.VnD(), z15.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t z1_expected[] = {0xfedcaa8854540000, 0x0000454588aacdef};
+    uint64_t z2_expected[] = {0x0000101022003210, 0x0123002201010000};
+    uint64_t z3_expected[] = {0x01235476ab89fedc, 0xcdef98ba67453210};
+    uint64_t z4_expected[] = {0xfffffefeffddfedc, 0xcdefddffefefffff};
+
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+  }
+}
+
+TEST_SVE(sve_last_r) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kNEON);
+  START();
+
+  __ Pfalse(p1.VnB());
+  int p2_inputs[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  int p3_inputs[] = {0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0};
+  Initialise(&masm, p2.VnB(), p2_inputs);
+  Initialise(&masm, p3.VnB(), p3_inputs);
+  __ Ptrue(p4.VnB());
+
+  __ Index(z0.VnB(), 0x10, 1);
+  __ Lasta(x1, p1, z0.VnB());
+  __ Lastb(x2, p1, z0.VnB());
+  __ Lasta(x3, p2, z0.VnB());
+  __ Lastb(x4, p2, z0.VnB());
+  __ Lasta(x5, p3, z0.VnB());
+  __ Lastb(x6, p3, z0.VnB());
+  __ Lasta(x7, p4, z0.VnB());
+
+  __ Punpklo(p3.VnH(), p3.VnB());
+  __ Index(z0.VnH(), 0x1110, 1);
+  __ Lasta(x9, p1, z0.VnH());
+  __ Lastb(x10, p3, z0.VnH());
+  __ Lasta(x12, p4, z0.VnH());
+
+  __ Index(z0.VnS(), 0x11111110, 1);
+  __ Lastb(x13, p1, z0.VnS());
+  __ Lasta(x14, p2, z0.VnS());
+  __ Lastb(x18, p4, z0.VnS());
+
+  __ Index(z0.VnD(), 0x1111111111111110, 1);
+  __ Lasta(x19, p1, z0.VnD());
+  __ Lastb(x20, p3, z0.VnD());
+  __ Lasta(x21, p3, z0.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_64(0x0000000000000010, x1);
+    ASSERT_EQUAL_64(0x0000000000000011, x3);
+    ASSERT_EQUAL_64(0x0000000000000010, x4);
+    ASSERT_EQUAL_64(0x0000000000000019, x5);
+    ASSERT_EQUAL_64(0x0000000000000018, x6);
+    ASSERT_EQUAL_64(0x0000000000000010, x7);
+    ASSERT_EQUAL_64(0x0000000000001110, x9);
+    ASSERT_EQUAL_64(0x0000000000001110, x12);
+    ASSERT_EQUAL_64(0x0000000011111111, x14);
+    ASSERT_EQUAL_64(0x1111111111111110, x19);
+
+    int vl = core.GetSVELaneCount(kBRegSize) * 8;
+    switch (vl) {
+      case 128:
+        ASSERT_EQUAL_64(0x000000000000001f, x2);
+        ASSERT_EQUAL_64(0x0000000000001116, x10);
+        ASSERT_EQUAL_64(0x0000000011111113, x13);
+        ASSERT_EQUAL_64(0x0000000011111113, x18);
+        ASSERT_EQUAL_64(0x1111111111111111, x20);
+        ASSERT_EQUAL_64(0x1111111111111110, x21);
+        break;
+      case 384:
+        ASSERT_EQUAL_64(0x000000000000003f, x2);
+        ASSERT_EQUAL_64(0x0000000000001118, x10);
+        ASSERT_EQUAL_64(0x000000001111111b, x13);
+        ASSERT_EQUAL_64(0x000000001111111b, x18);
+        ASSERT_EQUAL_64(0x1111111111111112, x20);
+        ASSERT_EQUAL_64(0x1111111111111113, x21);
+        break;
+      case 2048:
+        ASSERT_EQUAL_64(0x000000000000000f, x2);
+        ASSERT_EQUAL_64(0x0000000000001118, x10);
+        ASSERT_EQUAL_64(0x000000001111114f, x13);
+        ASSERT_EQUAL_64(0x000000001111114f, x18);
+        ASSERT_EQUAL_64(0x1111111111111112, x20);
+        ASSERT_EQUAL_64(0x1111111111111113, x21);
+        break;
+      default:
+        printf("WARNING: Some tests skipped due to unexpected VL.\n");
+        break;
+    }
+  }
+}
+
+TEST_SVE(sve_last_v) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kNEON);
+  START();
+
+  __ Pfalse(p1.VnB());
+  int p2_inputs[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  int p3_inputs[] = {0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0};
+  Initialise(&masm, p2.VnB(), p2_inputs);
+  Initialise(&masm, p3.VnB(), p3_inputs);
+  __ Ptrue(p4.VnB());
+
+  __ Index(z0.VnB(), 0x10, 1);
+  __ Lasta(b1, p1, z0.VnB());
+  __ Lastb(b2, p1, z0.VnB());
+  __ Lasta(b3, p2, z0.VnB());
+  __ Lastb(b4, p2, z0.VnB());
+  __ Lasta(b5, p3, z0.VnB());
+  __ Lastb(b6, p3, z0.VnB());
+  __ Lasta(b7, p4, z0.VnB());
+
+  __ Punpklo(p3.VnH(), p3.VnB());
+  __ Index(z0.VnH(), 0x1110, 1);
+  __ Lasta(h9, p1, z0.VnH());
+  __ Lastb(h10, p3, z0.VnH());
+  __ Lasta(h12, p4, z0.VnH());
+
+  __ Index(z0.VnS(), 0x11111110, 1);
+  __ Lastb(s13, p1, z0.VnS());
+  __ Lasta(s14, p2, z0.VnS());
+  __ Lastb(s18, p4, z0.VnS());
+
+  __ Index(z0.VnD(), 0x1111111111111110, 1);
+  __ Lasta(d19, p1, z0.VnD());
+  __ Lastb(d20, p3, z0.VnD());
+  __ Lasta(d21, p3, z0.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_128(0, 0x0000000000000010, q1);
+    ASSERT_EQUAL_128(0, 0x0000000000000011, q3);
+    ASSERT_EQUAL_128(0, 0x0000000000000010, q4);
+    ASSERT_EQUAL_128(0, 0x0000000000000019, q5);
+    ASSERT_EQUAL_128(0, 0x0000000000000018, q6);
+    ASSERT_EQUAL_128(0, 0x0000000000000010, q7);
+    ASSERT_EQUAL_128(0, 0x0000000000001110, q9);
+    ASSERT_EQUAL_128(0, 0x0000000000001110, q12);
+    ASSERT_EQUAL_128(0, 0x0000000011111111, q14);
+    ASSERT_EQUAL_128(0, 0x1111111111111110, q19);
+
+    int vl = core.GetSVELaneCount(kBRegSize) * 8;
+    switch (vl) {
+      case 128:
+        ASSERT_EQUAL_128(0, 0x000000000000001f, q2);
+        ASSERT_EQUAL_128(0, 0x0000000000001116, q10);
+        ASSERT_EQUAL_128(0, 0x0000000011111113, q13);
+        ASSERT_EQUAL_128(0, 0x0000000011111113, q18);
+        ASSERT_EQUAL_128(0, 0x1111111111111111, q20);
+        ASSERT_EQUAL_128(0, 0x1111111111111110, q21);
+        break;
+      case 384:
+        ASSERT_EQUAL_128(0, 0x000000000000003f, q2);
+        ASSERT_EQUAL_128(0, 0x0000000000001118, q10);
+        ASSERT_EQUAL_128(0, 0x000000001111111b, q13);
+        ASSERT_EQUAL_128(0, 0x000000001111111b, q18);
+        ASSERT_EQUAL_128(0, 0x1111111111111112, q20);
+        ASSERT_EQUAL_128(0, 0x1111111111111113, q21);
+        break;
+      case 2048:
+        ASSERT_EQUAL_128(0, 0x000000000000000f, q2);
+        ASSERT_EQUAL_128(0, 0x0000000000001118, q10);
+        ASSERT_EQUAL_128(0, 0x000000001111114f, q13);
+        ASSERT_EQUAL_128(0, 0x000000001111114f, q18);
+        ASSERT_EQUAL_128(0, 0x1111111111111112, q20);
+        ASSERT_EQUAL_128(0, 0x1111111111111113, q21);
+        break;
+      default:
+        printf("WARNING: Some tests skipped due to unexpected VL.\n");
+        break;
+    }
+  }
+}
+
+TEST_SVE(sve_clast_r) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kNEON);
+  START();
+
+  __ Pfalse(p1.VnB());
+  int p2_inputs[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  int p3_inputs[] = {0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0};
+  Initialise(&masm, p2.VnB(), p2_inputs);
+  Initialise(&masm, p3.VnB(), p3_inputs);
+  __ Ptrue(p4.VnB());
+
+  __ Index(z0.VnB(), 0x10, 1);
+  __ Mov(x1, -1);
+  __ Mov(x2, -1);
+  __ Clasta(x1, p1, x1, z0.VnB());
+  __ Clastb(x2, p1, x2, z0.VnB());
+  __ Clasta(x3, p2, x3, z0.VnB());
+  __ Clastb(x4, p2, x4, z0.VnB());
+  __ Clasta(x5, p3, x5, z0.VnB());
+  __ Clastb(x6, p3, x6, z0.VnB());
+  __ Clasta(x7, p4, x7, z0.VnB());
+
+  __ Punpklo(p3.VnH(), p3.VnB());
+  __ Index(z0.VnH(), 0x1110, 1);
+  __ Mov(x9, -1);
+  __ Clasta(x9, p1, x9, z0.VnH());
+  __ Clastb(x10, p3, x10, z0.VnH());
+  __ Clasta(x12, p4, x12, z0.VnH());
+
+  __ Index(z0.VnS(), 0x11111110, 1);
+  __ Mov(x13, -1);
+  __ Clasta(x13, p1, x13, z0.VnS());
+  __ Clastb(x14, p2, x14, z0.VnS());
+  __ Clasta(x18, p4, x18, z0.VnS());
+
+  __ Index(z0.VnD(), 0x1111111111111110, 1);
+  __ Mov(x19, -1);
+  __ Clasta(x19, p1, x19, z0.VnD());
+  __ Clastb(x20, p2, x20, z0.VnD());
+  __ Clasta(x21, p4, x21, z0.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_64(0x00000000000000ff, x1);
+    ASSERT_EQUAL_64(0x00000000000000ff, x2);
+    ASSERT_EQUAL_64(0x0000000000000011, x3);
+    ASSERT_EQUAL_64(0x0000000000000010, x4);
+    ASSERT_EQUAL_64(0x0000000000000019, x5);
+    ASSERT_EQUAL_64(0x0000000000000018, x6);
+    ASSERT_EQUAL_64(0x0000000000000010, x7);
+    ASSERT_EQUAL_64(0x000000000000ffff, x9);
+    ASSERT_EQUAL_64(0x0000000000001110, x12);
+    ASSERT_EQUAL_64(0x00000000ffffffff, x13);
+    ASSERT_EQUAL_64(0x0000000011111110, x14);
+    ASSERT_EQUAL_64(0x0000000011111110, x18);
+    ASSERT_EQUAL_64(0xffffffffffffffff, x19);
+    ASSERT_EQUAL_64(0x1111111111111110, x20);
+    ASSERT_EQUAL_64(0x1111111111111110, x21);
+
+    int vl = core.GetSVELaneCount(kBRegSize) * 8;
+    switch (vl) {
+      case 128:
+        ASSERT_EQUAL_64(0x0000000000001116, x10);
+        break;
+      case 384:
+        ASSERT_EQUAL_64(0x0000000000001118, x10);
+        break;
+      case 2048:
+        ASSERT_EQUAL_64(0x0000000000001118, x10);
+        break;
+      default:
+        printf("WARNING: Some tests skipped due to unexpected VL.\n");
+        break;
+    }
+  }
+}
+
+TEST_SVE(sve_clast_v) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kNEON);
+  START();
+
+  __ Pfalse(p1.VnB());
+  int p2_inputs[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  int p3_inputs[] = {0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0};
+  Initialise(&masm, p2.VnB(), p2_inputs);
+  Initialise(&masm, p3.VnB(), p3_inputs);
+  __ Ptrue(p4.VnB());
+
+  __ Index(z0.VnB(), 0x10, 1);
+  __ Dup(z1.VnB(), -1);
+  __ Dup(z2.VnB(), -1);
+  __ Clasta(b1, p1, b1, z0.VnB());
+  __ Clastb(b2, p1, b2, z0.VnB());
+  __ Clasta(b3, p2, b3, z0.VnB());
+  __ Clastb(b4, p2, b4, z0.VnB());
+  __ Clasta(b5, p3, b5, z0.VnB());
+  __ Clastb(b6, p3, b6, z0.VnB());
+  __ Clasta(b7, p4, b7, z0.VnB());
+
+  __ Punpklo(p3.VnH(), p3.VnB());
+  __ Index(z0.VnH(), 0x1110, 1);
+  __ Dup(z9.VnB(), -1);
+  __ Clasta(h9, p1, h9, z0.VnH());
+  __ Clastb(h10, p3, h10, z0.VnH());
+  __ Clasta(h12, p4, h12, z0.VnH());
+
+  __ Index(z0.VnS(), 0x11111110, 1);
+  __ Dup(z13.VnB(), -1);
+  __ Clasta(s13, p1, s13, z0.VnS());
+  __ Clastb(s14, p2, s14, z0.VnS());
+  __ Clasta(s18, p4, s18, z0.VnS());
+
+  __ Index(z0.VnD(), 0x1111111111111110, 1);
+  __ Dup(z19.VnB(), -1);
+  __ Clasta(d19, p1, d19, z0.VnD());
+  __ Clastb(d20, p2, d20, z0.VnD());
+  __ Clasta(d21, p4, d21, z0.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_128(0, 0x00000000000000ff, q1);
+    ASSERT_EQUAL_128(0, 0x00000000000000ff, q2);
+    ASSERT_EQUAL_128(0, 0x0000000000000011, q3);
+    ASSERT_EQUAL_128(0, 0x0000000000000010, q4);
+    ASSERT_EQUAL_128(0, 0x0000000000000019, q5);
+    ASSERT_EQUAL_128(0, 0x0000000000000018, q6);
+    ASSERT_EQUAL_128(0, 0x0000000000000010, q7);
+    ASSERT_EQUAL_128(0, 0x000000000000ffff, q9);
+    ASSERT_EQUAL_128(0, 0x0000000000001110, q12);
+    ASSERT_EQUAL_128(0, 0x00000000ffffffff, q13);
+    ASSERT_EQUAL_128(0, 0x0000000011111110, q14);
+    ASSERT_EQUAL_128(0, 0x0000000011111110, q18);
+    ASSERT_EQUAL_128(0, 0xffffffffffffffff, q19);
+    ASSERT_EQUAL_128(0, 0x1111111111111110, q20);
+    ASSERT_EQUAL_128(0, 0x1111111111111110, q21);
+
+    int vl = core.GetSVELaneCount(kBRegSize) * 8;
+    switch (vl) {
+      case 128:
+        ASSERT_EQUAL_128(0, 0x0000000000001116, q10);
+        break;
+      case 384:
+        ASSERT_EQUAL_128(0, 0x0000000000001118, q10);
+        break;
+      case 2048:
+        ASSERT_EQUAL_128(0, 0x0000000000001118, q10);
+        break;
+      default:
+        printf("WARNING: Some tests skipped due to unexpected VL.\n");
+        break;
+    }
+  }
+}
+
+TEST_SVE(sve_clast_z) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kNEON);
+  START();
+
+  __ Pfalse(p1.VnB());
+  int p2_inputs[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  int p3_inputs[] = {0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0};
+  Initialise(&masm, p2.VnB(), p2_inputs);
+  Initialise(&masm, p3.VnB(), p3_inputs);
+  __ Ptrue(p4.VnB());
+
+  __ Index(z0.VnB(), 0x10, 1);
+  __ Dup(z1.VnB(), 0xff);
+  __ Dup(z2.VnB(), 0xff);
+  __ Clasta(z1.VnB(), p1, z1.VnB(), z0.VnB());
+  __ Clastb(z2.VnB(), p1, z2.VnB(), z0.VnB());
+  __ Clasta(z3.VnB(), p2, z3.VnB(), z0.VnB());
+  __ Clastb(z4.VnB(), p2, z4.VnB(), z0.VnB());
+  __ Clasta(z5.VnB(), p3, z5.VnB(), z0.VnB());
+  __ Clastb(z6.VnB(), p3, z6.VnB(), z0.VnB());
+  __ Clasta(z7.VnB(), p4, z7.VnB(), z0.VnB());
+
+  __ Punpklo(p3.VnH(), p3.VnB());
+  __ Index(z0.VnH(), 0x1110, 1);
+  __ Dup(z9.VnB(), 0xff);
+  __ Clasta(z9.VnH(), p1, z9.VnH(), z0.VnH());
+  __ Clastb(z10.VnH(), p3, z10.VnH(), z0.VnH());
+  __ Clasta(z12.VnH(), p4, z12.VnH(), z0.VnH());
+
+  __ Index(z0.VnS(), 0x11111110, 1);
+  __ Dup(z13.VnB(), 0xff);
+  __ Clasta(z13.VnS(), p1, z13.VnS(), z0.VnS());
+  __ Clastb(z14.VnS(), p2, z14.VnS(), z0.VnS());
+  __ Clasta(z16.VnS(), p4, z16.VnS(), z0.VnS());
+
+  __ Index(z0.VnD(), 0x1111111111111110, 1);
+  __ Dup(z17.VnB(), 0xff);
+  __ Clasta(z17.VnD(), p1, z17.VnD(), z0.VnD());
+  __ Clastb(z18.VnD(), p2, z18.VnD(), z0.VnD());
+  __ Clasta(z20.VnD(), p4, z20.VnD(), z0.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t z1_expected[] = {0xffffffffffffffff, 0xffffffffffffffff};
+    uint64_t z2_expected[] = {0xffffffffffffffff, 0xffffffffffffffff};
+    uint64_t z3_expected[] = {0x1111111111111111, 0x1111111111111111};
+    uint64_t z4_expected[] = {0x1010101010101010, 0x1010101010101010};
+    uint64_t z5_expected[] = {0x1919191919191919, 0x1919191919191919};
+    uint64_t z6_expected[] = {0x1818181818181818, 0x1818181818181818};
+    uint64_t z7_expected[] = {0x1010101010101010, 0x1010101010101010};
+    uint64_t z9_expected[] = {0xffffffffffffffff, 0xffffffffffffffff};
+    uint64_t z12_expected[] = {0x1110111011101110, 0x1110111011101110};
+    uint64_t z13_expected[] = {0xffffffffffffffff, 0xffffffffffffffff};
+    uint64_t z14_expected[] = {0x1111111011111110, 0x1111111011111110};
+    uint64_t z16_expected[] = {0x1111111011111110, 0x1111111011111110};
+    uint64_t z17_expected[] = {0xffffffffffffffff, 0xffffffffffffffff};
+    uint64_t z18_expected[] = {0x1111111111111110, 0x1111111111111110};
+    uint64_t z20_expected[] = {0x1111111111111110, 0x1111111111111110};
+
+    uint64_t z10_expected_vl128[] = {0x1116111611161116, 0x1116111611161116};
+    uint64_t z10_expected_vl_long[] = {0x1118111811181118, 0x1118111811181118};
+
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnD());
+    ASSERT_EQUAL_SVE(z7_expected, z7.VnD());
+    ASSERT_EQUAL_SVE(z9_expected, z9.VnD());
+    ASSERT_EQUAL_SVE(z12_expected, z12.VnD());
+    ASSERT_EQUAL_SVE(z13_expected, z13.VnD());
+    ASSERT_EQUAL_SVE(z14_expected, z14.VnD());
+    ASSERT_EQUAL_SVE(z16_expected, z16.VnD());
+    ASSERT_EQUAL_SVE(z17_expected, z17.VnD());
+    ASSERT_EQUAL_SVE(z18_expected, z18.VnD());
+    ASSERT_EQUAL_SVE(z20_expected, z20.VnD());
+
+    int vl = core.GetSVELaneCount(kBRegSize) * 8;
+    switch (vl) {
+      case 128:
+        ASSERT_EQUAL_SVE(z10_expected_vl128, z10.VnD());
+        break;
+      case 384:
+      case 2048:
+        ASSERT_EQUAL_SVE(z10_expected_vl_long, z10.VnD());
+        break;
+      default:
+        printf("WARNING: Some tests skipped due to unexpected VL.\n");
+        break;
+    }
+  }
+}
+
+TEST_SVE(sve_compact) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kNEON);
+  START();
+
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p2.VnS(), p0.VnS(), p1.VnS());
+  __ Zip1(p3.VnS(), p1.VnS(), p0.VnS());
+  __ Zip1(p4.VnD(), p0.VnD(), p1.VnD());
+
+  __ Index(z0.VnS(), 0x11111111, 0x11111111);
+  __ Mov(q0, q0);
+  __ Compact(z1.VnS(), p0, z0.VnS());
+  __ Compact(z2.VnS(), p2, z0.VnS());
+  __ Compact(z0.VnS(), p3, z0.VnS());
+
+  __ Index(z3.VnD(), 0x1111111111111111, 0x1111111111111111);
+  __ Mov(q3, q3);
+  __ Compact(z4.VnD(), p0, z3.VnD());
+  __ Compact(z5.VnD(), p1, z3.VnD());
+  __ Compact(z6.VnD(), p4, z3.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t z1_expected[] = {0x4444444433333333, 0x2222222211111111};
+    uint64_t z2_expected[] = {0x0000000000000000, 0x3333333311111111};
+    uint64_t z0_expected[] = {0x0000000000000000, 0x4444444422222222};
+    uint64_t z4_expected[] = {0x2222222222222222, 0x1111111111111111};
+    uint64_t z5_expected[] = {0x0000000000000000, 0x0000000000000000};
+    uint64_t z6_expected[] = {0x0000000000000000, 0x1111111111111111};
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+    ASSERT_EQUAL_SVE(z0_expected, z0.VnD());
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnD());
+  }
+}
+
+TEST_SVE(sve_splice) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  int p2b_inputs[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  int p3b_inputs[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0};
+  int p4b_inputs[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int p5b_inputs[] = {0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0};
+  int p6b_inputs[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0};
+  Initialise(&masm, p2.VnB(), p2b_inputs);
+  Initialise(&masm, p3.VnB(), p3b_inputs);
+  Initialise(&masm, p4.VnB(), p4b_inputs);
+  Initialise(&masm, p5.VnB(), p5b_inputs);
+  Initialise(&masm, p6.VnB(), p6b_inputs);
+
+  __ Index(z30.VnB(), 1, 1);
+
+  __ Index(z0.VnB(), -1, -1);
+  __ Splice(z0.VnB(), p0, z0.VnB(), z30.VnB());
+  __ Index(z1.VnB(), -1, -1);
+  __ Splice(z1.VnB(), p1, z1.VnB(), z30.VnB());
+  __ Index(z2.VnB(), -1, -1);
+  __ Splice(z2.VnB(), p2, z2.VnB(), z30.VnB());
+  __ Index(z3.VnB(), -1, -1);
+  __ Splice(z3.VnB(), p3, z3.VnB(), z30.VnB());
+  __ Index(z4.VnB(), -1, -1);
+  __ Splice(z4.VnB(), p4, z4.VnB(), z30.VnB());
+  __ Index(z5.VnB(), -1, -1);
+  __ Splice(z5.VnB(), p5, z5.VnB(), z30.VnB());
+  __ Index(z6.VnB(), -1, -1);
+  __ Splice(z6.VnB(), p6, z6.VnB(), z30.VnB());
+
+  int p2h_inputs[] = {0, 0, 0, 0, 0, 0, 1, 0};
+  int p3h_inputs[] = {0, 0, 1, 0, 0, 0, 1, 0};
+  Initialise(&masm, p2.VnH(), p2h_inputs);
+  Initialise(&masm, p3.VnH(), p3h_inputs);
+
+  __ Index(z30.VnH(), 1, 1);
+  __ Index(z29.VnH(), -1, -1);
+  __ Splice(z7.VnH(), p2, z29.VnH(), z30.VnH());
+  __ Splice(z8.VnH(), p3, z29.VnH(), z30.VnH());
+
+  int p2s_inputs[] = {0, 0, 1, 0};
+  int p3s_inputs[] = {1, 0, 1, 0};
+  Initialise(&masm, p2.VnS(), p2s_inputs);
+  Initialise(&masm, p3.VnS(), p3s_inputs);
+
+  __ Index(z30.VnS(), 1, 1);
+  __ Index(z29.VnS(), -1, -1);
+  __ Splice(z9.VnS(), p2, z29.VnS(), z30.VnS());
+  __ Splice(z10.VnS(), p3, z29.VnS(), z30.VnS());
+
+  int p2d_inputs[] = {0, 1};
+  int p3d_inputs[] = {1, 0};
+  Initialise(&masm, p2.VnD(), p2d_inputs);
+  Initialise(&masm, p3.VnD(), p3d_inputs);
+
+  __ Index(z30.VnD(), 1, 1);
+  __ Index(z29.VnD(), -1, -1);
+  __ Splice(z11.VnD(), p2, z29.VnD(), z30.VnD());
+  __ Splice(z30.VnD(), p3, z29.VnD(), z30.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t z0_expected[] = {0xf0f1f2f3f4f5f6f7, 0xf8f9fafbfcfdfeff};
+    uint64_t z1_expected[] = {0x100f0e0d0c0b0a09, 0x0807060504030201};
+    uint64_t z2_expected[] = {0x0f0e0d0c0b0a0908, 0x07060504030201ff};
+    uint64_t z3_expected[] = {0x0f0e0d0c0b0a0908, 0x07060504030201fe};
+    uint64_t z4_expected[] = {0x0f0e0d0c0b0a0908, 0x07060504030201f0};
+    uint64_t z5_expected[] = {0x0c0b0a0908070605, 0x04030201f6f7f8f9};
+    uint64_t z6_expected[] = {0x01f0f1f2f3f4f5f6, 0xf7f8f9fafbfcfdfe};
+    uint64_t z7_expected[] = {0x0007000600050004, 0x000300020001fffe};
+    uint64_t z8_expected[] = {0x000300020001fffa, 0xfffbfffcfffdfffe};
+    uint64_t z9_expected[] = {0x0000000300000002, 0x00000001fffffffe};
+    uint64_t z10_expected[] = {0x00000001fffffffc, 0xfffffffdfffffffe};
+    uint64_t z11_expected[] = {0x0000000000000001, 0xffffffffffffffff};
+    uint64_t z30_expected[] = {0x0000000000000001, 0xfffffffffffffffe};
+
+    ASSERT_EQUAL_SVE(z0_expected, z0.VnD());
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnD());
+    ASSERT_EQUAL_SVE(z7_expected, z7.VnD());
+    ASSERT_EQUAL_SVE(z8_expected, z8.VnD());
+    ASSERT_EQUAL_SVE(z9_expected, z9.VnD());
+    ASSERT_EQUAL_SVE(z10_expected, z10.VnD());
+    ASSERT_EQUAL_SVE(z11_expected, z11.VnD());
+    ASSERT_EQUAL_SVE(z30_expected, z30.VnD());
+  }
+}
+
+TEST_SVE(sve_predicate_logical) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // 0b...01011010'10110111
+  int p10_inputs[] = {0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, 1};  // Pm
+  // 0b...11011001'01010010
+  int p11_inputs[] = {1, 1, 0, 1, 1, 0, 0, 1, 0, 1, 0, 1, 0, 0, 1, 0};  // Pn
+  // 0b...01010101'10110010
+  int p12_inputs[] = {0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0};  // pg
+
+  Initialise(&masm, p10.VnB(), p10_inputs);
+  Initialise(&masm, p11.VnB(), p11_inputs);
+  Initialise(&masm, p12.VnB(), p12_inputs);
+
+  __ Ands(p0.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
+  __ Mrs(x0, NZCV);
+  __ Bics(p1.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
+  __ Mrs(x1, NZCV);
+  __ Eor(p2.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
+  __ Nand(p3.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
+  __ Nor(p4.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
+  __ Orn(p5.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
+  __ Orr(p6.VnB(), p12.Zeroing(), p11.VnB(), p10.VnB());
+  __ Sel(p7.VnB(), p12, p11.VnB(), p10.VnB());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // 0b...01010000'00010010
+    int p0_expected[] = {0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0};
+    // 0b...00000001'00000000
+    int p1_expected[] = {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0};
+    // 0b...00000001'10100000
+    int p2_expected[] = {0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0};
+    // 0b...00000101'10100000
+    int p3_expected[] = {0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0};
+    // 0b...00000100'00000000
+    int p4_expected[] = {0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+    // 0b...01010101'00010010
+    int p5_expected[] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0};
+    // 0b...01010001'10110010
+    int p6_expected[] = {0, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 1, 0};
+    // 0b...01011011'00010111
+    int p7_expected[] = {0, 1, 0, 1, 1, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1};
+
+    ASSERT_EQUAL_SVE(p0_expected, p0.VnB());
+    ASSERT_EQUAL_SVE(p1_expected, p1.VnB());
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnB());
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnB());
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnB());
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnB());
+
+    ASSERT_EQUAL_32(SVEFirstFlag, w0);
+    ASSERT_EQUAL_32(SVENotLastFlag, w1);
+  }
+}
+
+TEST_SVE(sve_int_compare_vectors) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int z10_inputs[] = {0x00, 0x80, 0xff, 0x7f, 0x00, 0x00, 0x00, 0xff};
+  int z11_inputs[] = {0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 0xfe};
+  int p0_inputs[] = {1, 0, 1, 1, 1, 1, 1, 1};
+  InsrHelper(&masm, z10.VnB(), z10_inputs);
+  InsrHelper(&masm, z11.VnB(), z11_inputs);
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  __ Cmphs(p6.VnB(), p0.Zeroing(), z10.VnB(), z11.VnB());
+  __ Mrs(x6, NZCV);
+
+  uint64_t z12_inputs[] = {0xffffffffffffffff, 0x8000000000000000};
+  uint64_t z13_inputs[] = {0x0000000000000000, 0x8000000000000000};
+  int p1_inputs[] = {1, 1};
+  InsrHelper(&masm, z12.VnD(), z12_inputs);
+  InsrHelper(&masm, z13.VnD(), z13_inputs);
+  Initialise(&masm, p1.VnD(), p1_inputs);
+
+  __ Cmphi(p7.VnD(), p1.Zeroing(), z12.VnD(), z13.VnD());
+  __ Mrs(x7, NZCV);
+
+  int z14_inputs[] = {0, 32767, -1, -32767, 0, 0, 0, 32766};
+  int z15_inputs[] = {0, 0, 0, 0, 32767, -1, -32767, 32767};
+
+  int p2_inputs[] = {1, 0, 1, 1, 1, 1, 1, 1};
+  InsrHelper(&masm, z14.VnH(), z14_inputs);
+  InsrHelper(&masm, z15.VnH(), z15_inputs);
+  Initialise(&masm, p2.VnH(), p2_inputs);
+
+  __ Cmpge(p8.VnH(), p2.Zeroing(), z14.VnH(), z15.VnH());
+  __ Mrs(x8, NZCV);
+
+  __ Cmpeq(p9.VnH(), p2.Zeroing(), z14.VnH(), z15.VnH());
+  __ Mrs(x9, NZCV);
+
+  int z16_inputs[] = {0, -1, 0, 0};
+  int z17_inputs[] = {0, 0, 2147483647, -2147483648};
+  int p3_inputs[] = {1, 1, 1, 1};
+  InsrHelper(&masm, z16.VnS(), z16_inputs);
+  InsrHelper(&masm, z17.VnS(), z17_inputs);
+  Initialise(&masm, p3.VnS(), p3_inputs);
+
+  __ Cmpgt(p10.VnS(), p3.Zeroing(), z16.VnS(), z17.VnS());
+  __ Mrs(x10, NZCV);
+
+  __ Cmpne(p11.VnS(), p3.Zeroing(), z16.VnS(), z17.VnS());
+  __ Mrs(x11, NZCV);
+
+  // Architectural aliases testing.
+  __ Cmpls(p12.VnB(), p0.Zeroing(), z11.VnB(), z10.VnB());  // HS
+  __ Cmplo(p13.VnD(), p1.Zeroing(), z13.VnD(), z12.VnD());  // HI
+  __ Cmple(p14.VnH(), p2.Zeroing(), z15.VnH(), z14.VnH());  // GE
+  __ Cmplt(p15.VnS(), p3.Zeroing(), z17.VnS(), z16.VnS());  // GT
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int p6_expected[] = {1, 0, 1, 1, 0, 0, 0, 1};
+    for (size_t i = 0; i < ArrayLength(p6_expected); i++) {
+      int lane = static_cast<int>(ArrayLength(p6_expected) - i - 1);
+      ASSERT_EQUAL_SVE_LANE(p6_expected[i], p6.VnB(), lane);
+    }
+
+    int p7_expected[] = {1, 0};
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnD());
+
+    int p8_expected[] = {1, 0, 0, 0, 0, 1, 1, 0};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnH());
+
+    int p9_expected[] = {1, 0, 0, 0, 0, 0, 0, 0};
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnH());
+
+    int p10_expected[] = {0, 0, 0, 1};
+    ASSERT_EQUAL_SVE(p10_expected, p10.VnS());
+
+    int p11_expected[] = {0, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p11_expected, p11.VnS());
+
+    // Reuse the expected results to verify the architectural aliases.
+    ASSERT_EQUAL_SVE(p6_expected, p12.VnB());
+    ASSERT_EQUAL_SVE(p7_expected, p13.VnD());
+    ASSERT_EQUAL_SVE(p8_expected, p14.VnH());
+    ASSERT_EQUAL_SVE(p10_expected, p15.VnS());
+
+    ASSERT_EQUAL_32(SVEFirstFlag, w6);
+    ASSERT_EQUAL_32(NoFlag, w7);
+    ASSERT_EQUAL_32(NoFlag, w8);
+    ASSERT_EQUAL_32(NoFlag, w9);
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w10);
+  }
+}
+
+TEST_SVE(sve_int_compare_vectors_wide_elements) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int src1_inputs_1[] = {0, 1, -1, -128, 127, 100, -66};
+  int src2_inputs_1[] = {0, -1};
+  int mask_inputs_1[] = {1, 1, 1, 1, 1, 0, 1};
+  InsrHelper(&masm, z13.VnB(), src1_inputs_1);
+  InsrHelper(&masm, z19.VnD(), src2_inputs_1);
+  Initialise(&masm, p0.VnB(), mask_inputs_1);
+
+  __ Cmpge(p2.VnB(), p0.Zeroing(), z13.VnB(), z19.VnD());
+  __ Mrs(x2, NZCV);
+  __ Cmpgt(p3.VnB(), p0.Zeroing(), z13.VnB(), z19.VnD());
+  __ Mrs(x3, NZCV);
+
+  int src1_inputs_2[] = {0, 32767, -1, -32767, 1, 1234, 0, 32766};
+  int src2_inputs_2[] = {0, -32767};
+  int mask_inputs_2[] = {1, 0, 1, 1, 1, 1, 1, 1};
+  InsrHelper(&masm, z13.VnH(), src1_inputs_2);
+  InsrHelper(&masm, z19.VnD(), src2_inputs_2);
+  Initialise(&masm, p0.VnH(), mask_inputs_2);
+
+  __ Cmple(p4.VnH(), p0.Zeroing(), z13.VnH(), z19.VnD());
+  __ Mrs(x4, NZCV);
+  __ Cmplt(p5.VnH(), p0.Zeroing(), z13.VnH(), z19.VnD());
+  __ Mrs(x5, NZCV);
+
+  int src1_inputs_3[] = {0, -1, 2147483647, -2147483648};
+  int src2_inputs_3[] = {0, -2147483648};
+  int mask_inputs_3[] = {1, 1, 1, 1};
+  InsrHelper(&masm, z13.VnS(), src1_inputs_3);
+  InsrHelper(&masm, z19.VnD(), src2_inputs_3);
+  Initialise(&masm, p0.VnS(), mask_inputs_3);
+
+  __ Cmpeq(p6.VnS(), p0.Zeroing(), z13.VnS(), z19.VnD());
+  __ Mrs(x6, NZCV);
+  __ Cmpne(p7.VnS(), p0.Zeroing(), z13.VnS(), z19.VnD());
+  __ Mrs(x7, NZCV);
+
+  int src1_inputs_4[] = {0x00, 0x80, 0x7f, 0xff, 0x7f, 0xf0, 0x0f, 0x55};
+  int src2_inputs_4[] = {0x00, 0x7f};
+  int mask_inputs_4[] = {1, 1, 1, 1, 0, 1, 1, 1};
+  InsrHelper(&masm, z13.VnB(), src1_inputs_4);
+  InsrHelper(&masm, z19.VnD(), src2_inputs_4);
+  Initialise(&masm, p0.VnB(), mask_inputs_4);
+
+  __ Cmplo(p8.VnB(), p0.Zeroing(), z13.VnB(), z19.VnD());
+  __ Mrs(x8, NZCV);
+  __ Cmpls(p9.VnB(), p0.Zeroing(), z13.VnB(), z19.VnD());
+  __ Mrs(x9, NZCV);
+
+  int src1_inputs_5[] = {0x0000, 0x8000, 0x7fff, 0xffff};
+  int src2_inputs_5[] = {0x8000, 0xffff};
+  int mask_inputs_5[] = {1, 1, 1, 1};
+  InsrHelper(&masm, z13.VnS(), src1_inputs_5);
+  InsrHelper(&masm, z19.VnD(), src2_inputs_5);
+  Initialise(&masm, p0.VnS(), mask_inputs_5);
+
+  __ Cmphi(p10.VnS(), p0.Zeroing(), z13.VnS(), z19.VnD());
+  __ Mrs(x10, NZCV);
+  __ Cmphs(p11.VnS(), p0.Zeroing(), z13.VnS(), z19.VnD());
+  __ Mrs(x11, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    int p2_expected[] = {1, 1, 1, 0, 1, 0, 0};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+
+    int p3_expected[] = {1, 1, 0, 0, 1, 0, 0};
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+
+    int p4_expected[] = {0x1, 0x0, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnH());
+
+    int p5_expected[] = {0x0, 0x0, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0};
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnH());
+
+    int p6_expected[] = {0x1, 0x0, 0x0, 0x1};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnS());
+
+    int p7_expected[] = {0x0, 0x1, 0x1, 0x0};
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnS());
+
+    int p8_expected[] = {1, 0, 0, 0, 0, 0, 1, 1};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnB());
+
+    int p9_expected[] = {1, 0, 1, 0, 0, 0, 1, 1};
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnB());
+
+    int p10_expected[] = {0x0, 0x0, 0x0, 0x0};
+    ASSERT_EQUAL_SVE(p10_expected, p10.VnS());
+
+    int p11_expected[] = {0x0, 0x1, 0x0, 0x1};
+    ASSERT_EQUAL_SVE(p11_expected, p11.VnS());
+
+    ASSERT_EQUAL_32(NoFlag, w2);
+    ASSERT_EQUAL_32(NoFlag, w3);
+    ASSERT_EQUAL_32(NoFlag, w4);
+    ASSERT_EQUAL_32(SVENotLastFlag, w5);
+    ASSERT_EQUAL_32(SVEFirstFlag, w6);
+    ASSERT_EQUAL_32(SVENotLastFlag, w7);
+    ASSERT_EQUAL_32(SVEFirstFlag, w8);
+    ASSERT_EQUAL_32(SVEFirstFlag, w9);
+    ASSERT_EQUAL_32(SVENotLastFlag | SVENoneFlag, w10);
+    ASSERT_EQUAL_32(SVENotLastFlag | SVEFirstFlag, w11);
+  }
+}
+
+TEST_SVE(sve_bitwise_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // clang-format off
+  uint64_t z21_inputs[] = {0xfedcba9876543210, 0x0123456789abcdef};
+  uint32_t z22_inputs[] = {0xfedcba98, 0x76543210, 0x01234567, 0x89abcdef};
+  uint16_t z23_inputs[] = {0xfedc, 0xba98, 0x7654, 0x3210,
+                           0x0123, 0x4567, 0x89ab, 0xcdef};
+  uint8_t z24_inputs[] = {0xfe, 0xdc, 0xba, 0x98, 0x76, 0x54, 0x32, 0x10,
+                          0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef};
+  // clang-format on
+
+  InsrHelper(&masm, z1.VnD(), z21_inputs);
+  InsrHelper(&masm, z2.VnS(), z22_inputs);
+  InsrHelper(&masm, z3.VnH(), z23_inputs);
+  InsrHelper(&masm, z4.VnB(), z24_inputs);
+
+  __ And(z1.VnD(), z1.VnD(), 0x0000ffff0000ffff);
+  __ And(z2.VnS(), z2.VnS(), 0xff0000ff);
+  __ And(z3.VnH(), z3.VnH(), 0x0ff0);
+  __ And(z4.VnB(), z4.VnB(), 0x3f);
+
+  InsrHelper(&masm, z5.VnD(), z21_inputs);
+  InsrHelper(&masm, z6.VnS(), z22_inputs);
+  InsrHelper(&masm, z7.VnH(), z23_inputs);
+  InsrHelper(&masm, z8.VnB(), z24_inputs);
+
+  __ Eor(z5.VnD(), z5.VnD(), 0x0000ffff0000ffff);
+  __ Eor(z6.VnS(), z6.VnS(), 0xff0000ff);
+  __ Eor(z7.VnH(), z7.VnH(), 0x0ff0);
+  __ Eor(z8.VnB(), z8.VnB(), 0x3f);
+
+  InsrHelper(&masm, z9.VnD(), z21_inputs);
+  InsrHelper(&masm, z10.VnS(), z22_inputs);
+  InsrHelper(&masm, z11.VnH(), z23_inputs);
+  InsrHelper(&masm, z12.VnB(), z24_inputs);
+
+  __ Orr(z9.VnD(), z9.VnD(), 0x0000ffff0000ffff);
+  __ Orr(z10.VnS(), z10.VnS(), 0xff0000ff);
+  __ Orr(z11.VnH(), z11.VnH(), 0x0ff0);
+  __ Orr(z12.VnB(), z12.VnB(), 0x3f);
+
+  {
+    // The `Dup` macro maps onto either `dup` or `dupm`, but has its own test,
+    // so here we test `dupm` directly.
+    ExactAssemblyScope guard(&masm, 4 * kInstructionSize);
+    __ dupm(z13.VnD(), 0x7ffffff800000000);
+    __ dupm(z14.VnS(), 0x7ffc7ffc);
+    __ dupm(z15.VnH(), 0x3ffc);
+    __ dupm(z16.VnB(), 0xc3);
+  }
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // clang-format off
+    uint64_t z1_expected[] = {0x0000ba9800003210, 0x000045670000cdef};
+    uint32_t z2_expected[] = {0xfe000098, 0x76000010, 0x01000067, 0x890000ef};
+    uint16_t z3_expected[] = {0x0ed0, 0x0a90, 0x0650, 0x0210,
+                              0x0120, 0x0560, 0x09a0, 0x0de0};
+    uint8_t z4_expected[] = {0x3e, 0x1c, 0x3a, 0x18, 0x36, 0x14, 0x32, 0x10,
+                             0x01, 0x23, 0x05, 0x27, 0x09, 0x2b, 0x0d, 0x2f};
+
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnS());
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnH());
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnB());
+
+    uint64_t z5_expected[] = {0xfedc45677654cdef, 0x0123ba9889ab3210};
+    uint32_t z6_expected[] = {0x01dcba67, 0x895432ef, 0xfe234598, 0x76abcd10};
+    uint16_t z7_expected[] = {0xf12c, 0xb568, 0x79a4, 0x3de0,
+                              0x0ed3, 0x4a97, 0x865b, 0xc21f};
+    uint8_t z8_expected[] = {0xc1, 0xe3, 0x85, 0xa7, 0x49, 0x6b, 0x0d, 0x2f,
+                             0x3e, 0x1c, 0x7a, 0x58, 0xb6, 0x94, 0xf2, 0xd0};
+
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnS());
+    ASSERT_EQUAL_SVE(z7_expected, z7.VnH());
+    ASSERT_EQUAL_SVE(z8_expected, z8.VnB());
+
+    uint64_t z9_expected[] = {0xfedcffff7654ffff, 0x0123ffff89abffff};
+    uint32_t z10_expected[] = {0xffdcbaff, 0xff5432ff,  0xff2345ff, 0xffabcdff};
+    uint16_t z11_expected[] = {0xfffc, 0xbff8, 0x7ff4, 0x3ff0,
+                               0x0ff3, 0x4ff7, 0x8ffb, 0xcfff};
+    uint8_t z12_expected[] = {0xff, 0xff, 0xbf, 0xbf, 0x7f, 0x7f, 0x3f, 0x3f,
+                              0x3f, 0x3f, 0x7f, 0x7f, 0xbf, 0xbf, 0xff, 0xff};
+
+    ASSERT_EQUAL_SVE(z9_expected, z9.VnD());
+    ASSERT_EQUAL_SVE(z10_expected, z10.VnS());
+    ASSERT_EQUAL_SVE(z11_expected, z11.VnH());
+    ASSERT_EQUAL_SVE(z12_expected, z12.VnB());
+
+    uint64_t z13_expected[] = {0x7ffffff800000000, 0x7ffffff800000000};
+    uint32_t z14_expected[] = {0x7ffc7ffc, 0x7ffc7ffc, 0x7ffc7ffc, 0x7ffc7ffc};
+    uint16_t z15_expected[] = {0x3ffc, 0x3ffc, 0x3ffc, 0x3ffc,
+                               0x3ffc, 0x3ffc, 0x3ffc ,0x3ffc};
+    ASSERT_EQUAL_SVE(z13_expected, z13.VnD());
+    ASSERT_EQUAL_SVE(z14_expected, z14.VnS());
+    ASSERT_EQUAL_SVE(z15_expected, z15.VnH());
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_dup_imm) {
+  // The `Dup` macro can generate `dup`, `dupm`, and it can synthesise
+  // unencodable immediates.
+
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Encodable with `dup` (shift 0).
+  __ Dup(z0.VnD(), -1);
+  __ Dup(z1.VnS(), 0x7f);
+  __ Dup(z2.VnH(), -0x80);
+  __ Dup(z3.VnB(), 42);
+
+  // Encodable with `dup` (shift 8).
+  __ Dup(z4.VnD(), -42 * 256);
+  __ Dup(z5.VnS(), -0x8000);
+  __ Dup(z6.VnH(), 0x7f00);
+  // B-sized lanes cannot take a shift of 8.
+
+  // Encodable with `dupm` (but not `dup`).
+  __ Dup(z10.VnD(), 0x3fc);
+  __ Dup(z11.VnS(), -516097);  // 0xfff81fff, as a signed int.
+  __ Dup(z12.VnH(), 0x0001);
+  // All values that fit B-sized lanes are encodable with `dup`.
+
+  // Cases that require immediate synthesis.
+  __ Dup(z20.VnD(), 0x1234);
+  __ Dup(z21.VnD(), -4242);
+  __ Dup(z22.VnD(), 0xfedcba9876543210);
+  __ Dup(z23.VnS(), 0x01020304);
+  __ Dup(z24.VnS(), -0x01020304);
+  __ Dup(z25.VnH(), 0x3c38);
+  // All values that fit B-sized lanes are directly encodable.
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(0xffffffffffffffff, z0.VnD());
+    ASSERT_EQUAL_SVE(0x0000007f, z1.VnS());
+    ASSERT_EQUAL_SVE(0xff80, z2.VnH());
+    ASSERT_EQUAL_SVE(0x2a, z3.VnB());
+
+    ASSERT_EQUAL_SVE(0xffffffffffffd600, z4.VnD());
+    ASSERT_EQUAL_SVE(0xffff8000, z5.VnS());
+    ASSERT_EQUAL_SVE(0x7f00, z6.VnH());
+
+    ASSERT_EQUAL_SVE(0x00000000000003fc, z10.VnD());
+    ASSERT_EQUAL_SVE(0xfff81fff, z11.VnS());
+    ASSERT_EQUAL_SVE(0x0001, z12.VnH());
+
+    ASSERT_EQUAL_SVE(0x1234, z20.VnD());
+    ASSERT_EQUAL_SVE(0xffffffffffffef6e, z21.VnD());
+    ASSERT_EQUAL_SVE(0xfedcba9876543210, z22.VnD());
+    ASSERT_EQUAL_SVE(0x01020304, z23.VnS());
+    ASSERT_EQUAL_SVE(0xfefdfcfc, z24.VnS());
+    ASSERT_EQUAL_SVE(0x3c38, z25.VnH());
+  }
+}
+
+TEST_SVE(sve_inc_dec_p_scalar) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int p0_inputs[] = {0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1};
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  int p0_b_count = 9;
+  int p0_h_count = 5;
+  int p0_s_count = 3;
+  int p0_d_count = 2;
+
+  // 64-bit operations preserve their high bits.
+  __ Mov(x0, 0x123456780000002a);
+  __ Decp(x0, p0.VnB());
+
+  __ Mov(x1, 0x123456780000002a);
+  __ Incp(x1, p0.VnH());
+
+  // Check that saturation does not occur.
+  __ Mov(x10, 1);
+  __ Decp(x10, p0.VnS());
+
+  __ Mov(x11, UINT64_MAX);
+  __ Incp(x11, p0.VnD());
+
+  __ Mov(x12, INT64_MAX);
+  __ Incp(x12, p0.VnB());
+
+  // With an all-true predicate, these instructions increment or decrement by
+  // the vector length.
+  __ Ptrue(p15.VnB());
+
+  __ Mov(x20, 0x4000000000000000);
+  __ Decp(x20, p15.VnB());
+
+  __ Mov(x21, 0x4000000000000000);
+  __ Incp(x21, p15.VnH());
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_64(0x123456780000002a - p0_b_count, x0);
+    ASSERT_EQUAL_64(0x123456780000002a + p0_h_count, x1);
+
+    ASSERT_EQUAL_64(UINT64_C(1) - p0_s_count, x10);
+    ASSERT_EQUAL_64(UINT64_MAX + p0_d_count, x11);
+    ASSERT_EQUAL_64(static_cast<uint64_t>(INT64_MAX) + p0_b_count, x12);
+
+    ASSERT_EQUAL_64(0x4000000000000000 - core.GetSVELaneCount(kBRegSize), x20);
+    ASSERT_EQUAL_64(0x4000000000000000 + core.GetSVELaneCount(kHRegSize), x21);
+  }
+}
+
+TEST_SVE(sve_sqinc_sqdec_p_scalar) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int p0_inputs[] = {0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1};
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  int p0_b_count = 9;
+  int p0_h_count = 5;
+  int p0_s_count = 3;
+  int p0_d_count = 2;
+
+  uint64_t placeholder_high = 0x1234567800000000;
+
+  // 64-bit operations preserve their high bits.
+  __ Mov(x0, placeholder_high + 42);
+  __ Sqdecp(x0, p0.VnB());
+
+  __ Mov(x1, placeholder_high + 42);
+  __ Sqincp(x1, p0.VnH());
+
+  // 32-bit operations sign-extend into their high bits.
+  __ Mov(x2, placeholder_high + 42);
+  __ Sqdecp(x2, p0.VnS(), w2);
+
+  __ Mov(x3, placeholder_high + 42);
+  __ Sqincp(x3, p0.VnD(), w3);
+
+  __ Mov(x4, placeholder_high + 1);
+  __ Sqdecp(x4, p0.VnS(), w4);
+
+  __ Mov(x5, placeholder_high - 1);
+  __ Sqincp(x5, p0.VnD(), w5);
+
+  // Check that saturation behaves correctly.
+  __ Mov(x10, 0x8000000000000001);  // INT64_MIN + 1
+  __ Sqdecp(x10, p0.VnB());
+
+  __ Mov(x11, placeholder_high + 0x80000001);  // INT32_MIN + 1
+  __ Sqdecp(x11, p0.VnH(), w11);
+
+  __ Mov(x12, 1);
+  __ Sqdecp(x12, p0.VnS());
+
+  __ Mov(x13, placeholder_high + 1);
+  __ Sqdecp(x13, p0.VnD(), w13);
+
+  __ Mov(x14, 0x7ffffffffffffffe);  // INT64_MAX - 1
+  __ Sqincp(x14, p0.VnB());
+
+  __ Mov(x15, placeholder_high + 0x7ffffffe);  // INT32_MAX - 1
+  __ Sqincp(x15, p0.VnH(), w15);
+
+  // Don't use x16 and x17 since they are scratch registers by default.
+
+  __ Mov(x18, 0xffffffffffffffff);
+  __ Sqincp(x18, p0.VnS());
+
+  __ Mov(x19, placeholder_high + 0xffffffff);
+  __ Sqincp(x19, p0.VnD(), w19);
+
+  __ Mov(x20, placeholder_high + 0xffffffff);
+  __ Sqdecp(x20, p0.VnB(), w20);
+
+  // With an all-true predicate, these instructions increment or decrement by
+  // the vector length.
+  __ Ptrue(p15.VnB());
+
+  __ Mov(x21, 0);
+  __ Sqdecp(x21, p15.VnB());
+
+  __ Mov(x22, 0);
+  __ Sqincp(x22, p15.VnH());
+
+  __ Mov(x23, placeholder_high);
+  __ Sqdecp(x23, p15.VnS(), w23);
+
+  __ Mov(x24, placeholder_high);
+  __ Sqincp(x24, p15.VnD(), w24);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    // 64-bit operations preserve their high bits.
+    ASSERT_EQUAL_64(placeholder_high + 42 - p0_b_count, x0);
+    ASSERT_EQUAL_64(placeholder_high + 42 + p0_h_count, x1);
+
+    // 32-bit operations sign-extend into their high bits.
+    ASSERT_EQUAL_64(42 - p0_s_count, x2);
+    ASSERT_EQUAL_64(42 + p0_d_count, x3);
+    ASSERT_EQUAL_64(0xffffffff00000000 | (1 - p0_s_count), x4);
+    ASSERT_EQUAL_64(p0_d_count - 1, x5);
+
+    // Check that saturation behaves correctly.
+    ASSERT_EQUAL_64(INT64_MIN, x10);
+    ASSERT_EQUAL_64(INT32_MIN, x11);
+    ASSERT_EQUAL_64(1 - p0_s_count, x12);
+    ASSERT_EQUAL_64(1 - p0_d_count, x13);
+    ASSERT_EQUAL_64(INT64_MAX, x14);
+    ASSERT_EQUAL_64(INT32_MAX, x15);
+    ASSERT_EQUAL_64(p0_s_count - 1, x18);
+    ASSERT_EQUAL_64(p0_d_count - 1, x19);
+    ASSERT_EQUAL_64(-1 - p0_b_count, x20);
+
+    // Check all-true predicates.
+    ASSERT_EQUAL_64(-core.GetSVELaneCount(kBRegSize), x21);
+    ASSERT_EQUAL_64(core.GetSVELaneCount(kHRegSize), x22);
+    ASSERT_EQUAL_64(-core.GetSVELaneCount(kSRegSize), x23);
+    ASSERT_EQUAL_64(core.GetSVELaneCount(kDRegSize), x24);
+  }
+}
+
+TEST_SVE(sve_uqinc_uqdec_p_scalar) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int p0_inputs[] = {0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1};
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  int p0_b_count = 9;
+  int p0_h_count = 5;
+  int p0_s_count = 3;
+  int p0_d_count = 2;
+
+  uint64_t placeholder_high = 0x1234567800000000;
+
+  // 64-bit operations preserve their high bits.
+  __ Mov(x0, placeholder_high + 42);
+  __ Uqdecp(x0, p0.VnB());
+
+  __ Mov(x1, placeholder_high + 42);
+  __ Uqincp(x1, p0.VnH());
+
+  // 32-bit operations zero-extend into their high bits.
+  __ Mov(x2, placeholder_high + 42);
+  __ Uqdecp(x2, p0.VnS(), w2);
+
+  __ Mov(x3, placeholder_high + 42);
+  __ Uqincp(x3, p0.VnD(), w3);
+
+  __ Mov(x4, placeholder_high + 0x80000001);
+  __ Uqdecp(x4, p0.VnS(), w4);
+
+  __ Mov(x5, placeholder_high + 0x7fffffff);
+  __ Uqincp(x5, p0.VnD(), w5);
+
+  // Check that saturation behaves correctly.
+  __ Mov(x10, 1);
+  __ Uqdecp(x10, p0.VnB(), x10);
+
+  __ Mov(x11, placeholder_high + 1);
+  __ Uqdecp(x11, p0.VnH(), w11);
+
+  __ Mov(x12, 0x8000000000000000);  // INT64_MAX + 1
+  __ Uqdecp(x12, p0.VnS(), x12);
+
+  __ Mov(x13, placeholder_high + 0x80000000);  // INT32_MAX + 1
+  __ Uqdecp(x13, p0.VnD(), w13);
+
+  __ Mov(x14, 0xfffffffffffffffe);  // UINT64_MAX - 1
+  __ Uqincp(x14, p0.VnB(), x14);
+
+  __ Mov(x15, placeholder_high + 0xfffffffe);  // UINT32_MAX - 1
+  __ Uqincp(x15, p0.VnH(), w15);
+
+  // Don't use x16 and x17 since they are scratch registers by default.
+
+  __ Mov(x18, 0x7ffffffffffffffe);  // INT64_MAX - 1
+  __ Uqincp(x18, p0.VnS(), x18);
+
+  __ Mov(x19, placeholder_high + 0x7ffffffe);  // INT32_MAX - 1
+  __ Uqincp(x19, p0.VnD(), w19);
+
+  // With an all-true predicate, these instructions increment or decrement by
+  // the vector length.
+  __ Ptrue(p15.VnB());
+
+  __ Mov(x20, 0x4000000000000000);
+  __ Uqdecp(x20, p15.VnB(), x20);
+
+  __ Mov(x21, 0x4000000000000000);
+  __ Uqincp(x21, p15.VnH(), x21);
+
+  __ Mov(x22, placeholder_high + 0x40000000);
+  __ Uqdecp(x22, p15.VnS(), w22);
+
+  __ Mov(x23, placeholder_high + 0x40000000);
+  __ Uqincp(x23, p15.VnD(), w23);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    // 64-bit operations preserve their high bits.
+    ASSERT_EQUAL_64(placeholder_high + 42 - p0_b_count, x0);
+    ASSERT_EQUAL_64(placeholder_high + 42 + p0_h_count, x1);
+
+    // 32-bit operations zero-extend into their high bits.
+    ASSERT_EQUAL_64(42 - p0_s_count, x2);
+    ASSERT_EQUAL_64(42 + p0_d_count, x3);
+    ASSERT_EQUAL_64(UINT64_C(0x80000001) - p0_s_count, x4);
+    ASSERT_EQUAL_64(UINT64_C(0x7fffffff) + p0_d_count, x5);
+
+    // Check that saturation behaves correctly.
+    ASSERT_EQUAL_64(0, x10);
+    ASSERT_EQUAL_64(0, x11);
+    ASSERT_EQUAL_64(0x8000000000000000 - p0_s_count, x12);
+    ASSERT_EQUAL_64(UINT64_C(0x80000000) - p0_d_count, x13);
+    ASSERT_EQUAL_64(UINT64_MAX, x14);
+    ASSERT_EQUAL_64(UINT32_MAX, x15);
+    ASSERT_EQUAL_64(0x7ffffffffffffffe + p0_s_count, x18);
+    ASSERT_EQUAL_64(UINT64_C(0x7ffffffe) + p0_d_count, x19);
+
+    // Check all-true predicates.
+    ASSERT_EQUAL_64(0x4000000000000000 - core.GetSVELaneCount(kBRegSize), x20);
+    ASSERT_EQUAL_64(0x4000000000000000 + core.GetSVELaneCount(kHRegSize), x21);
+    ASSERT_EQUAL_64(0x40000000 - core.GetSVELaneCount(kSRegSize), x22);
+    ASSERT_EQUAL_64(0x40000000 + core.GetSVELaneCount(kDRegSize), x23);
+  }
+}
+
+TEST_SVE(sve_inc_dec_p_vector) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // There are {5, 3, 2} active {H, S, D} lanes. B-sized lanes are ignored.
+  int p0_inputs[] = {0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1};
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  // Check that saturation does not occur.
+
+  int64_t z0_inputs[] = {0x1234567800000042, 0, 1, INT64_MIN};
+  InsrHelper(&masm, z0.VnD(), z0_inputs);
+
+  int64_t z1_inputs[] = {0x12345678ffffff2a, 0, -1, INT64_MAX};
+  InsrHelper(&masm, z1.VnD(), z1_inputs);
+
+  int32_t z2_inputs[] = {0x12340042, 0, -1, 1, INT32_MAX, INT32_MIN};
+  InsrHelper(&masm, z2.VnS(), z2_inputs);
+
+  int16_t z3_inputs[] = {0x122a, 0, 1, -1, INT16_MIN, INT16_MAX};
+  InsrHelper(&masm, z3.VnH(), z3_inputs);
+
+  // The MacroAssembler implements non-destructive operations using movprfx.
+  __ Decp(z10.VnD(), p0, z0.VnD());
+  __ Decp(z11.VnD(), p0, z1.VnD());
+  __ Decp(z12.VnS(), p0, z2.VnS());
+  __ Decp(z13.VnH(), p0, z3.VnH());
+
+  __ Incp(z14.VnD(), p0, z0.VnD());
+  __ Incp(z15.VnD(), p0, z1.VnD());
+  __ Incp(z16.VnS(), p0, z2.VnS());
+  __ Incp(z17.VnH(), p0, z3.VnH());
+
+  // Also test destructive forms.
+  __ Mov(z4, z0);
+  __ Mov(z5, z1);
+  __ Mov(z6, z2);
+  __ Mov(z7, z3);
+
+  __ Decp(z0.VnD(), p0);
+  __ Decp(z1.VnD(), p0);
+  __ Decp(z2.VnS(), p0);
+  __ Decp(z3.VnH(), p0);
+
+  __ Incp(z4.VnD(), p0);
+  __ Incp(z5.VnD(), p0);
+  __ Incp(z6.VnS(), p0);
+  __ Incp(z7.VnH(), p0);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    // z0_inputs[...] - number of active D lanes (2)
+    int64_t z0_expected[] = {0x1234567800000040, -2, -1, 0x7ffffffffffffffe};
+    ASSERT_EQUAL_SVE(z0_expected, z0.VnD());
+
+    // z1_inputs[...] - number of active D lanes (2)
+    int64_t z1_expected[] = {0x12345678ffffff28, -2, -3, 0x7ffffffffffffffd};
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+
+    // z2_inputs[...] - number of active S lanes (3)
+    int32_t z2_expected[] = {0x1234003f, -3, -4, -2, 0x7ffffffc, 0x7ffffffd};
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnS());
+
+    // z3_inputs[...] - number of active H lanes (5)
+    int16_t z3_expected[] = {0x1225, -5, -4, -6, 0x7ffb, 0x7ffa};
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnH());
+
+    // z0_inputs[...] + number of active D lanes (2)
+    uint64_t z4_expected[] = {0x1234567800000044, 2, 3, 0x8000000000000002};
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+
+    // z1_inputs[...] + number of active D lanes (2)
+    uint64_t z5_expected[] = {0x12345678ffffff2c, 2, 1, 0x8000000000000001};
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+
+    // z2_inputs[...] + number of active S lanes (3)
+    uint32_t z6_expected[] = {0x12340045, 3, 2, 4, 0x80000002, 0x80000003};
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnS());
+
+    // z3_inputs[...] + number of active H lanes (5)
+    uint16_t z7_expected[] = {0x122f, 5, 6, 4, 0x8005, 0x8004};
+    ASSERT_EQUAL_SVE(z7_expected, z7.VnH());
+
+    // Check that the non-destructive macros produced the same results.
+    ASSERT_EQUAL_SVE(z0_expected, z10.VnD());
+    ASSERT_EQUAL_SVE(z1_expected, z11.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z12.VnS());
+    ASSERT_EQUAL_SVE(z3_expected, z13.VnH());
+    ASSERT_EQUAL_SVE(z4_expected, z14.VnD());
+    ASSERT_EQUAL_SVE(z5_expected, z15.VnD());
+    ASSERT_EQUAL_SVE(z6_expected, z16.VnS());
+    ASSERT_EQUAL_SVE(z7_expected, z17.VnH());
+  }
+}
+
+TEST_SVE(sve_inc_dec_ptrue_vector) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // With an all-true predicate, these instructions increment or decrement by
+  // the vector length.
+  __ Ptrue(p15.VnB());
+
+  __ Dup(z0.VnD(), 0);
+  __ Decp(z0.VnD(), p15);
+
+  __ Dup(z1.VnS(), 0);
+  __ Decp(z1.VnS(), p15);
+
+  __ Dup(z2.VnH(), 0);
+  __ Decp(z2.VnH(), p15);
+
+  __ Dup(z3.VnD(), 0);
+  __ Incp(z3.VnD(), p15);
+
+  __ Dup(z4.VnS(), 0);
+  __ Incp(z4.VnS(), p15);
+
+  __ Dup(z5.VnH(), 0);
+  __ Incp(z5.VnH(), p15);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    int d_lane_count = core.GetSVELaneCount(kDRegSize);
+    int s_lane_count = core.GetSVELaneCount(kSRegSize);
+    int h_lane_count = core.GetSVELaneCount(kHRegSize);
+
+    for (int i = 0; i < d_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(-d_lane_count, z0.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(d_lane_count, z3.VnD(), i);
+    }
+
+    for (int i = 0; i < s_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(-s_lane_count, z1.VnS(), i);
+      ASSERT_EQUAL_SVE_LANE(s_lane_count, z4.VnS(), i);
+    }
+
+    for (int i = 0; i < h_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(-h_lane_count, z2.VnH(), i);
+      ASSERT_EQUAL_SVE_LANE(h_lane_count, z5.VnH(), i);
+    }
+  }
+}
+
+TEST_SVE(sve_sqinc_sqdec_p_vector) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // There are {5, 3, 2} active {H, S, D} lanes. B-sized lanes are ignored.
+  int p0_inputs[] = {0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1};
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  // Check that saturation behaves correctly.
+
+  int64_t z0_inputs[] = {0x1234567800000042, 0, 1, INT64_MIN};
+  InsrHelper(&masm, z0.VnD(), z0_inputs);
+
+  int64_t z1_inputs[] = {0x12345678ffffff2a, 0, -1, INT64_MAX};
+  InsrHelper(&masm, z1.VnD(), z1_inputs);
+
+  int32_t z2_inputs[] = {0x12340042, 0, -1, 1, INT32_MAX, INT32_MIN};
+  InsrHelper(&masm, z2.VnS(), z2_inputs);
+
+  int16_t z3_inputs[] = {0x122a, 0, 1, -1, INT16_MIN, INT16_MAX};
+  InsrHelper(&masm, z3.VnH(), z3_inputs);
+
+  // The MacroAssembler implements non-destructive operations using movprfx.
+  __ Sqdecp(z10.VnD(), p0, z0.VnD());
+  __ Sqdecp(z11.VnD(), p0, z1.VnD());
+  __ Sqdecp(z12.VnS(), p0, z2.VnS());
+  __ Sqdecp(z13.VnH(), p0, z3.VnH());
+
+  __ Sqincp(z14.VnD(), p0, z0.VnD());
+  __ Sqincp(z15.VnD(), p0, z1.VnD());
+  __ Sqincp(z16.VnS(), p0, z2.VnS());
+  __ Sqincp(z17.VnH(), p0, z3.VnH());
+
+  // Also test destructive forms.
+  __ Mov(z4, z0);
+  __ Mov(z5, z1);
+  __ Mov(z6, z2);
+  __ Mov(z7, z3);
+
+  __ Sqdecp(z0.VnD(), p0);
+  __ Sqdecp(z1.VnD(), p0);
+  __ Sqdecp(z2.VnS(), p0);
+  __ Sqdecp(z3.VnH(), p0);
+
+  __ Sqincp(z4.VnD(), p0);
+  __ Sqincp(z5.VnD(), p0);
+  __ Sqincp(z6.VnS(), p0);
+  __ Sqincp(z7.VnH(), p0);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    // z0_inputs[...] - number of active D lanes (2)
+    int64_t z0_expected[] = {0x1234567800000040, -2, -1, INT64_MIN};
+    ASSERT_EQUAL_SVE(z0_expected, z0.VnD());
+
+    // z1_inputs[...] - number of active D lanes (2)
+    int64_t z1_expected[] = {0x12345678ffffff28, -2, -3, 0x7ffffffffffffffd};
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+
+    // z2_inputs[...] - number of active S lanes (3)
+    int32_t z2_expected[] = {0x1234003f, -3, -4, -2, 0x7ffffffc, INT32_MIN};
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnS());
+
+    // z3_inputs[...] - number of active H lanes (5)
+    int16_t z3_expected[] = {0x1225, -5, -4, -6, INT16_MIN, 0x7ffa};
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnH());
+
+    // z0_inputs[...] + number of active D lanes (2)
+    uint64_t z4_expected[] = {0x1234567800000044, 2, 3, 0x8000000000000002};
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+
+    // z1_inputs[...] + number of active D lanes (2)
+    uint64_t z5_expected[] = {0x12345678ffffff2c, 2, 1, INT64_MAX};
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+
+    // z2_inputs[...] + number of active S lanes (3)
+    uint32_t z6_expected[] = {0x12340045, 3, 2, 4, INT32_MAX, 0x80000003};
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnS());
+
+    // z3_inputs[...] + number of active H lanes (5)
+    uint16_t z7_expected[] = {0x122f, 5, 6, 4, 0x8005, INT16_MAX};
+    ASSERT_EQUAL_SVE(z7_expected, z7.VnH());
+
+    // Check that the non-destructive macros produced the same results.
+    ASSERT_EQUAL_SVE(z0_expected, z10.VnD());
+    ASSERT_EQUAL_SVE(z1_expected, z11.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z12.VnS());
+    ASSERT_EQUAL_SVE(z3_expected, z13.VnH());
+    ASSERT_EQUAL_SVE(z4_expected, z14.VnD());
+    ASSERT_EQUAL_SVE(z5_expected, z15.VnD());
+    ASSERT_EQUAL_SVE(z6_expected, z16.VnS());
+    ASSERT_EQUAL_SVE(z7_expected, z17.VnH());
+  }
+}
+
+TEST_SVE(sve_sqinc_sqdec_ptrue_vector) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // With an all-true predicate, these instructions increment or decrement by
+  // the vector length.
+  __ Ptrue(p15.VnB());
+
+  __ Dup(z0.VnD(), 0);
+  __ Sqdecp(z0.VnD(), p15);
+
+  __ Dup(z1.VnS(), 0);
+  __ Sqdecp(z1.VnS(), p15);
+
+  __ Dup(z2.VnH(), 0);
+  __ Sqdecp(z2.VnH(), p15);
+
+  __ Dup(z3.VnD(), 0);
+  __ Sqincp(z3.VnD(), p15);
+
+  __ Dup(z4.VnS(), 0);
+  __ Sqincp(z4.VnS(), p15);
+
+  __ Dup(z5.VnH(), 0);
+  __ Sqincp(z5.VnH(), p15);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    int d_lane_count = core.GetSVELaneCount(kDRegSize);
+    int s_lane_count = core.GetSVELaneCount(kSRegSize);
+    int h_lane_count = core.GetSVELaneCount(kHRegSize);
+
+    for (int i = 0; i < d_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(-d_lane_count, z0.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(d_lane_count, z3.VnD(), i);
+    }
+
+    for (int i = 0; i < s_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(-s_lane_count, z1.VnS(), i);
+      ASSERT_EQUAL_SVE_LANE(s_lane_count, z4.VnS(), i);
+    }
+
+    for (int i = 0; i < h_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(-h_lane_count, z2.VnH(), i);
+      ASSERT_EQUAL_SVE_LANE(h_lane_count, z5.VnH(), i);
+    }
+  }
+}
+
+TEST_SVE(sve_uqinc_uqdec_p_vector) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // There are {5, 3, 2} active {H, S, D} lanes. B-sized lanes are ignored.
+  int p0_inputs[] = {0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1};
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  // Check that saturation behaves correctly.
+
+  uint64_t z0_inputs[] = {0x1234567800000042, 0, 1, 0x8000000000000000};
+  InsrHelper(&masm, z0.VnD(), z0_inputs);
+
+  uint64_t z1_inputs[] = {0x12345678ffffff2a, 0, UINT64_MAX, INT64_MAX};
+  InsrHelper(&masm, z1.VnD(), z1_inputs);
+
+  uint32_t z2_inputs[] = {0x12340042, 0, UINT32_MAX, 1, INT32_MAX, 0x80000000};
+  InsrHelper(&masm, z2.VnS(), z2_inputs);
+
+  uint16_t z3_inputs[] = {0x122a, 0, 1, UINT16_MAX, 0x8000, INT16_MAX};
+  InsrHelper(&masm, z3.VnH(), z3_inputs);
+
+  // The MacroAssembler implements non-destructive operations using movprfx.
+  __ Uqdecp(z10.VnD(), p0, z0.VnD());
+  __ Uqdecp(z11.VnD(), p0, z1.VnD());
+  __ Uqdecp(z12.VnS(), p0, z2.VnS());
+  __ Uqdecp(z13.VnH(), p0, z3.VnH());
+
+  __ Uqincp(z14.VnD(), p0, z0.VnD());
+  __ Uqincp(z15.VnD(), p0, z1.VnD());
+  __ Uqincp(z16.VnS(), p0, z2.VnS());
+  __ Uqincp(z17.VnH(), p0, z3.VnH());
+
+  // Also test destructive forms.
+  __ Mov(z4, z0);
+  __ Mov(z5, z1);
+  __ Mov(z6, z2);
+  __ Mov(z7, z3);
+
+  __ Uqdecp(z0.VnD(), p0);
+  __ Uqdecp(z1.VnD(), p0);
+  __ Uqdecp(z2.VnS(), p0);
+  __ Uqdecp(z3.VnH(), p0);
+
+  __ Uqincp(z4.VnD(), p0);
+  __ Uqincp(z5.VnD(), p0);
+  __ Uqincp(z6.VnS(), p0);
+  __ Uqincp(z7.VnH(), p0);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    // z0_inputs[...] - number of active D lanes (2)
+    uint64_t z0_expected[] = {0x1234567800000040, 0, 0, 0x7ffffffffffffffe};
+    ASSERT_EQUAL_SVE(z0_expected, z0.VnD());
+
+    // z1_inputs[...] - number of active D lanes (2)
+    uint64_t z1_expected[] = {0x12345678ffffff28,
+                              0,
+                              0xfffffffffffffffd,
+                              0x7ffffffffffffffd};
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+
+    // z2_inputs[...] - number of active S lanes (3)
+    uint32_t z2_expected[] =
+        {0x1234003f, 0, 0xfffffffc, 0, 0x7ffffffc, 0x7ffffffd};
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnS());
+
+    // z3_inputs[...] - number of active H lanes (5)
+    uint16_t z3_expected[] = {0x1225, 0, 0, 0xfffa, 0x7ffb, 0x7ffa};
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnH());
+
+    // z0_inputs[...] + number of active D lanes (2)
+    uint64_t z4_expected[] = {0x1234567800000044, 2, 3, 0x8000000000000002};
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+
+    // z1_inputs[...] + number of active D lanes (2)
+    uint64_t z5_expected[] = {0x12345678ffffff2c,
+                              2,
+                              UINT64_MAX,
+                              0x8000000000000001};
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+
+    // z2_inputs[...] + number of active S lanes (3)
+    uint32_t z6_expected[] =
+        {0x12340045, 3, UINT32_MAX, 4, 0x80000002, 0x80000003};
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnS());
+
+    // z3_inputs[...] + number of active H lanes (5)
+    uint16_t z7_expected[] = {0x122f, 5, 6, UINT16_MAX, 0x8005, 0x8004};
+    ASSERT_EQUAL_SVE(z7_expected, z7.VnH());
+
+    // Check that the non-destructive macros produced the same results.
+    ASSERT_EQUAL_SVE(z0_expected, z10.VnD());
+    ASSERT_EQUAL_SVE(z1_expected, z11.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z12.VnS());
+    ASSERT_EQUAL_SVE(z3_expected, z13.VnH());
+    ASSERT_EQUAL_SVE(z4_expected, z14.VnD());
+    ASSERT_EQUAL_SVE(z5_expected, z15.VnD());
+    ASSERT_EQUAL_SVE(z6_expected, z16.VnS());
+    ASSERT_EQUAL_SVE(z7_expected, z17.VnH());
+  }
+}
+
+TEST_SVE(sve_uqinc_uqdec_ptrue_vector) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // With an all-true predicate, these instructions increment or decrement by
+  // the vector length.
+  __ Ptrue(p15.VnB());
+
+  __ Mov(x0, 0x1234567800000000);
+  __ Mov(x1, 0x12340000);
+  __ Mov(x2, 0x1200);
+
+  __ Dup(z0.VnD(), x0);
+  __ Uqdecp(z0.VnD(), p15);
+
+  __ Dup(z1.VnS(), x1);
+  __ Uqdecp(z1.VnS(), p15);
+
+  __ Dup(z2.VnH(), x2);
+  __ Uqdecp(z2.VnH(), p15);
+
+  __ Dup(z3.VnD(), x0);
+  __ Uqincp(z3.VnD(), p15);
+
+  __ Dup(z4.VnS(), x1);
+  __ Uqincp(z4.VnS(), p15);
+
+  __ Dup(z5.VnH(), x2);
+  __ Uqincp(z5.VnH(), p15);
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+
+    int d_lane_count = core.GetSVELaneCount(kDRegSize);
+    int s_lane_count = core.GetSVELaneCount(kSRegSize);
+    int h_lane_count = core.GetSVELaneCount(kHRegSize);
+
+    for (int i = 0; i < d_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(0x1234567800000000 - d_lane_count, z0.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0x1234567800000000 + d_lane_count, z3.VnD(), i);
+    }
+
+    for (int i = 0; i < s_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(0x12340000 - s_lane_count, z1.VnS(), i);
+      ASSERT_EQUAL_SVE_LANE(0x12340000 + s_lane_count, z4.VnS(), i);
+    }
+
+    for (int i = 0; i < h_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(0x1200 - h_lane_count, z2.VnH(), i);
+      ASSERT_EQUAL_SVE_LANE(0x1200 + h_lane_count, z5.VnH(), i);
+    }
+  }
+}
+
+TEST_SVE(sve_index) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Simple cases.
+  __ Index(z0.VnB(), 0, 1);
+  __ Index(z1.VnH(), 1, 1);
+  __ Index(z2.VnS(), 2, 1);
+  __ Index(z3.VnD(), 3, 1);
+
+  // Synthesised immediates.
+  __ Index(z4.VnB(), 42, -1);
+  __ Index(z5.VnH(), -1, 42);
+  __ Index(z6.VnS(), 42, 42);
+
+  // Register arguments.
+  __ Mov(x0, 42);
+  __ Mov(x1, -3);
+  __ Index(z10.VnD(), x0, x1);
+  __ Index(z11.VnB(), w0, w1);
+  // The register size should correspond to the lane size, but VIXL allows any
+  // register at least as big as the lane size.
+  __ Index(z12.VnB(), x0, x1);
+  __ Index(z13.VnH(), w0, x1);
+  __ Index(z14.VnS(), x0, w1);
+
+  // Integer overflow.
+  __ Index(z20.VnB(), UINT8_MAX - 2, 2);
+  __ Index(z21.VnH(), 7, -3);
+  __ Index(z22.VnS(), INT32_MAX - 2, 1);
+  __ Index(z23.VnD(), INT64_MIN + 6, -7);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int b_lane_count = core.GetSVELaneCount(kBRegSize);
+    int h_lane_count = core.GetSVELaneCount(kHRegSize);
+    int s_lane_count = core.GetSVELaneCount(kSRegSize);
+    int d_lane_count = core.GetSVELaneCount(kDRegSize);
+
+    uint64_t b_mask = GetUintMask(kBRegSize);
+    uint64_t h_mask = GetUintMask(kHRegSize);
+    uint64_t s_mask = GetUintMask(kSRegSize);
+    uint64_t d_mask = GetUintMask(kDRegSize);
+
+    // Simple cases.
+    for (int i = 0; i < b_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((0 + i) & b_mask, z0.VnB(), i);
+    }
+    for (int i = 0; i < h_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((1 + i) & h_mask, z1.VnH(), i);
+    }
+    for (int i = 0; i < s_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((2 + i) & s_mask, z2.VnS(), i);
+    }
+    for (int i = 0; i < d_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((3 + i) & d_mask, z3.VnD(), i);
+    }
+
+    // Synthesised immediates.
+    for (int i = 0; i < b_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((42 - i) & b_mask, z4.VnB(), i);
+    }
+    for (int i = 0; i < h_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((-1 + (42 * i)) & h_mask, z5.VnH(), i);
+    }
+    for (int i = 0; i < s_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((42 + (42 * i)) & s_mask, z6.VnS(), i);
+    }
+
+    // Register arguments.
+    for (int i = 0; i < d_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((42 - (3 * i)) & d_mask, z10.VnD(), i);
+    }
+    for (int i = 0; i < b_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((42 - (3 * i)) & b_mask, z11.VnB(), i);
+    }
+    for (int i = 0; i < b_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((42 - (3 * i)) & b_mask, z12.VnB(), i);
+    }
+    for (int i = 0; i < h_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((42 - (3 * i)) & h_mask, z13.VnH(), i);
+    }
+    for (int i = 0; i < s_lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE((42 - (3 * i)) & s_mask, z14.VnS(), i);
+    }
+
+    // Integer overflow.
+    uint8_t expected_z20[] = {0x05, 0x03, 0x01, 0xff, 0xfd};
+    ASSERT_EQUAL_SVE(expected_z20, z20.VnB());
+    uint16_t expected_z21[] = {0xfffb, 0xfffe, 0x0001, 0x0004, 0x0007};
+    ASSERT_EQUAL_SVE(expected_z21, z21.VnH());
+    uint32_t expected_z22[] = {0x80000000, 0x7fffffff, 0x7ffffffe, 0x7ffffffd};
+    ASSERT_EQUAL_SVE(expected_z22, z22.VnS());
+    uint64_t expected_z23[] = {0x7fffffffffffffff, 0x8000000000000006};
+    ASSERT_EQUAL_SVE(expected_z23, z23.VnD());
+  }
+}
+
+TEST(sve_int_compare_count_and_limit_scalars) {
+  SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Mov(w20, 0xfffffffd);
+  __ Mov(w21, 0xffffffff);
+
+  __ Whilele(p0.VnB(), w20, w21);
+  __ Mrs(x0, NZCV);
+  __ Whilele(p1.VnH(), w20, w21);
+  __ Mrs(x1, NZCV);
+
+  __ Mov(w20, 0xffffffff);
+  __ Mov(w21, 0x00000000);
+
+  __ Whilelt(p2.VnS(), w20, w21);
+  __ Mrs(x2, NZCV);
+  __ Whilelt(p3.VnD(), w20, w21);
+  __ Mrs(x3, NZCV);
+
+  __ Mov(w20, 0xfffffffd);
+  __ Mov(w21, 0xffffffff);
+
+  __ Whilels(p4.VnB(), w20, w21);
+  __ Mrs(x4, NZCV);
+  __ Whilels(p5.VnH(), w20, w21);
+  __ Mrs(x5, NZCV);
+
+  __ Mov(w20, 0xffffffff);
+  __ Mov(w21, 0x00000000);
+
+  __ Whilelo(p6.VnS(), w20, w21);
+  __ Mrs(x6, NZCV);
+  __ Whilelo(p7.VnD(), w20, w21);
+  __ Mrs(x7, NZCV);
+
+  __ Mov(x20, 0xfffffffffffffffd);
+  __ Mov(x21, 0xffffffffffffffff);
+
+  __ Whilele(p8.VnB(), x20, x21);
+  __ Mrs(x8, NZCV);
+  __ Whilele(p9.VnH(), x20, x21);
+  __ Mrs(x9, NZCV);
+
+  __ Mov(x20, 0xffffffffffffffff);
+  __ Mov(x21, 0x0000000000000000);
+
+  __ Whilelt(p10.VnS(), x20, x21);
+  __ Mrs(x10, NZCV);
+  __ Whilelt(p11.VnD(), x20, x21);
+  __ Mrs(x11, NZCV);
+
+  __ Mov(x20, 0xfffffffffffffffd);
+  __ Mov(x21, 0xffffffffffffffff);
+
+  __ Whilels(p12.VnB(), x20, x21);
+  __ Mrs(x12, NZCV);
+  __ Whilels(p13.VnH(), x20, x21);
+  __ Mrs(x13, NZCV);
+
+  __ Mov(x20, 0xffffffffffffffff);
+  __ Mov(x21, 0x0000000000000000);
+
+  __ Whilelo(p14.VnS(), x20, x21);
+  __ Mrs(x14, NZCV);
+  __ Whilelo(p15.VnD(), x20, x21);
+  __ Mrs(x15, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // 0b...00000000'00000111
+    int p0_expected[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p0_expected, p0.VnB());
+
+    // 0b...00000000'00010101
+    int p1_expected[] = {0, 0, 0, 0, 0, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p1_expected, p1.VnH());
+
+    int p2_expected[] = {0x0, 0x0, 0x0, 0x1};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnS());
+
+    int p3_expected[] = {0x00, 0x01};
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnD());
+
+    // 0b...11111111'11111111
+    int p4_expected[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnB());
+
+    // 0b...01010101'01010101
+    int p5_expected[] = {1, 1, 1, 1, 1, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnH());
+
+    int p6_expected[] = {0x0, 0x0, 0x0, 0x0};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnS());
+
+    int p7_expected[] = {0x00, 0x00};
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnD());
+
+    // 0b...00000000'00000111
+    int p8_expected[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnB());
+
+    // 0b...00000000'00010101
+    int p9_expected[] = {0, 0, 0, 0, 0, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnH());
+
+    int p10_expected[] = {0x0, 0x0, 0x0, 0x1};
+    ASSERT_EQUAL_SVE(p10_expected, p10.VnS());
+
+    int p11_expected[] = {0x00, 0x01};
+    ASSERT_EQUAL_SVE(p11_expected, p11.VnD());
+
+    // 0b...11111111'11111111
+    int p12_expected[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p12_expected, p12.VnB());
+
+    // 0b...01010101'01010101
+    int p13_expected[] = {1, 1, 1, 1, 1, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p13_expected, p13.VnH());
+
+    int p14_expected[] = {0x0, 0x0, 0x0, 0x0};
+    ASSERT_EQUAL_SVE(p14_expected, p14.VnS());
+
+    int p15_expected[] = {0x00, 0x00};
+    ASSERT_EQUAL_SVE(p15_expected, p15.VnD());
+
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w0);
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w1);
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w2);
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w3);
+    ASSERT_EQUAL_32(SVEFirstFlag, w4);
+    ASSERT_EQUAL_32(SVEFirstFlag, w5);
+    ASSERT_EQUAL_32(SVENoneFlag | SVENotLastFlag, w6);
+    ASSERT_EQUAL_32(SVENoneFlag | SVENotLastFlag, w7);
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w8);
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w9);
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w10);
+    ASSERT_EQUAL_32(SVEFirstFlag | SVENotLastFlag, w11);
+    ASSERT_EQUAL_32(SVEFirstFlag, w12);
+    ASSERT_EQUAL_32(SVEFirstFlag, w13);
+    ASSERT_EQUAL_32(SVENoneFlag | SVENotLastFlag, w14);
+    ASSERT_EQUAL_32(SVENoneFlag | SVENotLastFlag, w15);
+  }
+}
+
+TEST(sve_int_compare_vectors_signed_imm) {
+  SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int z13_inputs[] = {0, 1, -1, -15, 126, -127, -126, -15};
+  int mask_inputs1[] = {1, 1, 1, 0, 1, 1, 1, 1};
+  InsrHelper(&masm, z13.VnB(), z13_inputs);
+  Initialise(&masm, p0.VnB(), mask_inputs1);
+
+  __ Cmpeq(p2.VnB(), p0.Zeroing(), z13.VnB(), -15);
+  __ Mrs(x2, NZCV);
+  __ Cmpeq(p3.VnB(), p0.Zeroing(), z13.VnB(), -127);
+
+  int z14_inputs[] = {0, 1, -1, -32767, -32766, 32767, 32766, 0};
+  int mask_inputs2[] = {1, 1, 1, 0, 1, 1, 1, 1};
+  InsrHelper(&masm, z14.VnH(), z14_inputs);
+  Initialise(&masm, p0.VnH(), mask_inputs2);
+
+  __ Cmpge(p4.VnH(), p0.Zeroing(), z14.VnH(), -1);
+  __ Mrs(x4, NZCV);
+  __ Cmpge(p5.VnH(), p0.Zeroing(), z14.VnH(), -32767);
+
+  int z15_inputs[] = {0, 1, -1, INT_MIN};
+  int mask_inputs3[] = {0, 1, 1, 1};
+  InsrHelper(&masm, z15.VnS(), z15_inputs);
+  Initialise(&masm, p0.VnS(), mask_inputs3);
+
+  __ Cmpgt(p6.VnS(), p0.Zeroing(), z15.VnS(), 0);
+  __ Mrs(x6, NZCV);
+  __ Cmpgt(p7.VnS(), p0.Zeroing(), z15.VnS(), INT_MIN + 1);
+
+  __ Cmplt(p8.VnS(), p0.Zeroing(), z15.VnS(), 0);
+  __ Mrs(x8, NZCV);
+  __ Cmplt(p9.VnS(), p0.Zeroing(), z15.VnS(), INT_MIN + 1);
+
+  int64_t z16_inputs[] = {0, -1};
+  int mask_inputs4[] = {1, 1};
+  InsrHelper(&masm, z16.VnD(), z16_inputs);
+  Initialise(&masm, p0.VnD(), mask_inputs4);
+
+  __ Cmple(p10.VnD(), p0.Zeroing(), z16.VnD(), -1);
+  __ Mrs(x10, NZCV);
+  __ Cmple(p11.VnD(), p0.Zeroing(), z16.VnD(), LLONG_MIN);
+
+  __ Cmpne(p12.VnD(), p0.Zeroing(), z16.VnD(), -1);
+  __ Mrs(x12, NZCV);
+  __ Cmpne(p13.VnD(), p0.Zeroing(), z16.VnD(), LLONG_MAX);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int p2_expected[] = {0, 0, 0, 0, 0, 0, 0, 1};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+
+    int p3_expected[] = {0, 0, 0, 0, 0, 1, 0, 0};
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+
+    int p4_expected[] = {0x1, 0x1, 0x1, 0x0, 0x0, 0x1, 0x1, 0x1};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnH());
+
+    int p5_expected[] = {0x1, 0x1, 0x1, 0x0, 0x1, 0x1, 0x1, 0x1};
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnH());
+
+    int p6_expected[] = {0x0, 0x1, 0x0, 0x0};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnS());
+
+    int p7_expected[] = {0x0, 0x1, 0x1, 0x0};
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnS());
+
+    int p8_expected[] = {0x0, 0x0, 0x1, 0x1};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnS());
+
+    int p9_expected[] = {0x0, 0x0, 0x0, 0x1};
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnS());
+
+    int p10_expected[] = {0x00, 0x01};
+    ASSERT_EQUAL_SVE(p10_expected, p10.VnD());
+
+    int p11_expected[] = {0x00, 0x00};
+    ASSERT_EQUAL_SVE(p11_expected, p11.VnD());
+
+    int p12_expected[] = {0x01, 0x00};
+    ASSERT_EQUAL_SVE(p12_expected, p12.VnD());
+
+    int p13_expected[] = {0x01, 0x01};
+    ASSERT_EQUAL_SVE(p13_expected, p13.VnD());
+
+    ASSERT_EQUAL_32(SVENotLastFlag | SVEFirstFlag, w2);
+    ASSERT_EQUAL_32(SVEFirstFlag, w4);
+    ASSERT_EQUAL_32(NoFlag, w6);
+    ASSERT_EQUAL_32(SVENotLastFlag | SVEFirstFlag, w8);
+    ASSERT_EQUAL_32(SVENotLastFlag | SVEFirstFlag, w10);
+    ASSERT_EQUAL_32(NoFlag, w12);
+  }
+}
+
+TEST(sve_int_compare_vectors_unsigned_imm) {
+  SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint32_t src1_inputs[] = {0xf7, 0x0f, 0x8f, 0x1f, 0x83, 0x12, 0x00, 0xf1};
+  int mask_inputs1[] = {1, 1, 1, 0, 1, 1, 0, 1};
+  InsrHelper(&masm, z13.VnB(), src1_inputs);
+  Initialise(&masm, p0.VnB(), mask_inputs1);
+
+  __ Cmphi(p2.VnB(), p0.Zeroing(), z13.VnB(), 0x0f);
+  __ Mrs(x2, NZCV);
+  __ Cmphi(p3.VnB(), p0.Zeroing(), z13.VnB(), 0xf0);
+
+  uint32_t src2_inputs[] = {0xffff, 0x8000, 0x1fff, 0x0000, 0x1234};
+  int mask_inputs2[] = {1, 1, 1, 1, 0};
+  InsrHelper(&masm, z13.VnH(), src2_inputs);
+  Initialise(&masm, p0.VnH(), mask_inputs2);
+
+  __ Cmphs(p4.VnH(), p0.Zeroing(), z13.VnH(), 0x1f);
+  __ Mrs(x4, NZCV);
+  __ Cmphs(p5.VnH(), p0.Zeroing(), z13.VnH(), 0x1fff);
+
+  uint32_t src3_inputs[] = {0xffffffff, 0xfedcba98, 0x0000ffff, 0x00000000};
+  int mask_inputs3[] = {1, 1, 1, 1};
+  InsrHelper(&masm, z13.VnS(), src3_inputs);
+  Initialise(&masm, p0.VnS(), mask_inputs3);
+
+  __ Cmplo(p6.VnS(), p0.Zeroing(), z13.VnS(), 0x3f);
+  __ Mrs(x6, NZCV);
+  __ Cmplo(p7.VnS(), p0.Zeroing(), z13.VnS(), 0x3f3f3f3f);
+
+  uint64_t src4_inputs[] = {0xffffffffffffffff, 0x0000000000000000};
+  int mask_inputs4[] = {1, 1};
+  InsrHelper(&masm, z13.VnD(), src4_inputs);
+  Initialise(&masm, p0.VnD(), mask_inputs4);
+
+  __ Cmpls(p8.VnD(), p0.Zeroing(), z13.VnD(), 0x2f);
+  __ Mrs(x8, NZCV);
+  __ Cmpls(p9.VnD(), p0.Zeroing(), z13.VnD(), 0x800000000000000);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int p2_expected[] = {1, 0, 1, 0, 1, 1, 0, 1};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+
+    int p3_expected[] = {1, 0, 0, 0, 0, 0, 0, 1};
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+
+    int p4_expected[] = {0x1, 0x1, 0x1, 0x0, 0x0};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnH());
+
+    int p5_expected[] = {0x1, 0x1, 0x1, 0x0, 0x0};
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnH());
+
+    int p6_expected[] = {0x0, 0x0, 0x0, 0x1};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnS());
+
+    int p7_expected[] = {0x0, 0x0, 0x1, 0x1};
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnS());
+
+    int p8_expected[] = {0x00, 0x01};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnD());
+
+    int p9_expected[] = {0x00, 0x01};
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnD());
+
+    ASSERT_EQUAL_32(SVEFirstFlag, w2);
+    ASSERT_EQUAL_32(NoFlag, w4);
+    ASSERT_EQUAL_32(SVENotLastFlag | SVEFirstFlag, w6);
+    ASSERT_EQUAL_32(SVENotLastFlag | SVEFirstFlag, w8);
+  }
+}
+
+TEST(sve_int_compare_conditionally_terminate_scalars) {
+  SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Mov(x0, 0xfedcba9887654321);
+  __ Mov(x1, 0x1000100010001000);
+
+  // Initialise Z and C. These are preserved by cterm*, and the V flag is set to
+  // !C if the condition does not hold.
+  __ Mov(x10, NoFlag);
+  __ Msr(NZCV, x10);
+
+  __ Ctermeq(w0, w0);
+  __ Mrs(x2, NZCV);
+  __ Ctermeq(x0, x1);
+  __ Mrs(x3, NZCV);
+  __ Ctermne(x0, x0);
+  __ Mrs(x4, NZCV);
+  __ Ctermne(w0, w1);
+  __ Mrs(x5, NZCV);
+
+  // As above, but with all flags initially set.
+  __ Mov(x10, NZCVFlag);
+  __ Msr(NZCV, x10);
+
+  __ Ctermeq(w0, w0);
+  __ Mrs(x6, NZCV);
+  __ Ctermeq(x0, x1);
+  __ Mrs(x7, NZCV);
+  __ Ctermne(x0, x0);
+  __ Mrs(x8, NZCV);
+  __ Ctermne(w0, w1);
+  __ Mrs(x9, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_32(SVEFirstFlag, w2);
+    ASSERT_EQUAL_32(VFlag, w3);
+    ASSERT_EQUAL_32(VFlag, w4);
+    ASSERT_EQUAL_32(SVEFirstFlag, w5);
+
+    ASSERT_EQUAL_32(SVEFirstFlag | ZCFlag, w6);
+    ASSERT_EQUAL_32(ZCFlag, w7);
+    ASSERT_EQUAL_32(ZCFlag, w8);
+    ASSERT_EQUAL_32(SVEFirstFlag | ZCFlag, w9);
+  }
+}
+
+// Work out what the architectural `PredTest` pseudocode should produce for the
+// given result and governing predicate.
+template <typename Tg, typename Td, int N>
+static StatusFlags GetPredTestFlags(const Td (&pd)[N],
+                                    const Tg (&pg)[N],
+                                    int vl) {
+  int first = -1;
+  int last = -1;
+  bool any_active = false;
+
+  // Only consider potentially-active lanes.
+  int start = (N > vl) ? (N - vl) : 0;
+  for (int i = start; i < N; i++) {
+    if ((pg[i] & 1) == 1) {
+      // Look for the first and last active lanes.
+      // Note that the 'first' lane is the one with the highest index.
+      if (last < 0) last = i;
+      first = i;
+      // Look for any active lanes that are also active in pd.
+      if ((pd[i] & 1) == 1) any_active = true;
+    }
+  }
+
+  uint32_t flags = 0;
+  if ((first >= 0) && ((pd[first] & 1) == 1)) flags |= SVEFirstFlag;
+  if (!any_active) flags |= SVENoneFlag;
+  if ((last < 0) || ((pd[last] & 1) == 0)) flags |= SVENotLastFlag;
+  return static_cast<StatusFlags>(flags);
+}
+
+typedef void (MacroAssembler::*PfirstPnextFn)(const PRegisterWithLaneSize& pd,
+                                              const PRegister& pg,
+                                              const PRegisterWithLaneSize& pn);
+template <typename Tg, typename Tn, typename Td>
+static void PfirstPnextHelper(Test* config,
+                              PfirstPnextFn macro,
+                              unsigned lane_size_in_bits,
+                              const Tg& pg_inputs,
+                              const Tn& pn_inputs,
+                              const Td& pd_expected) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  PRegister pg = p15;
+  PRegister pn = p14;
+  Initialise(&masm, pg.WithLaneSize(lane_size_in_bits), pg_inputs);
+  Initialise(&masm, pn.WithLaneSize(lane_size_in_bits), pn_inputs);
+
+  // Initialise NZCV to an impossible value, to check that we actually write it.
+  __ Mov(x10, NZCVFlag);
+
+  // If pd.Is(pn), the MacroAssembler simply passes the arguments directly to
+  // the Assembler.
+  __ Msr(NZCV, x10);
+  __ Mov(p0, pn);
+  (masm.*macro)(p0.WithLaneSize(lane_size_in_bits),
+                pg,
+                p0.WithLaneSize(lane_size_in_bits));
+  __ Mrs(x0, NZCV);
+
+  // The MacroAssembler supports non-destructive use.
+  __ Msr(NZCV, x10);
+  (masm.*macro)(p1.WithLaneSize(lane_size_in_bits),
+                pg,
+                pn.WithLaneSize(lane_size_in_bits));
+  __ Mrs(x1, NZCV);
+
+  // If pd.Aliases(pg) the macro requires a scratch register.
+  {
+    UseScratchRegisterScope temps(&masm);
+    temps.Include(p13);
+    __ Msr(NZCV, x10);
+    __ Mov(p2, p15);
+    (masm.*macro)(p2.WithLaneSize(lane_size_in_bits),
+                  p2,
+                  pn.WithLaneSize(lane_size_in_bits));
+    __ Mrs(x2, NZCV);
+  }
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Check that the inputs weren't modified.
+    ASSERT_EQUAL_SVE(pn_inputs, pn.WithLaneSize(lane_size_in_bits));
+    ASSERT_EQUAL_SVE(pg_inputs, pg.WithLaneSize(lane_size_in_bits));
+
+    // Check the primary operation.
+    ASSERT_EQUAL_SVE(pd_expected, p0.WithLaneSize(lane_size_in_bits));
+    ASSERT_EQUAL_SVE(pd_expected, p1.WithLaneSize(lane_size_in_bits));
+    ASSERT_EQUAL_SVE(pd_expected, p2.WithLaneSize(lane_size_in_bits));
+
+    // Check that the flags were properly set.
+    StatusFlags nzcv_expected =
+        GetPredTestFlags(pd_expected,
+                         pg_inputs,
+                         core.GetSVELaneCount(kBRegSize));
+    ASSERT_EQUAL_64(nzcv_expected, x0);
+    ASSERT_EQUAL_64(nzcv_expected, x1);
+    ASSERT_EQUAL_64(nzcv_expected, x2);
+  }
+}
+
+template <typename Tg, typename Tn, typename Td>
+static void PfirstHelper(Test* config,
+                         const Tg& pg_inputs,
+                         const Tn& pn_inputs,
+                         const Td& pd_expected) {
+  PfirstPnextHelper(config,
+                    &MacroAssembler::Pfirst,
+                    kBRegSize,  // pfirst only accepts B-sized lanes.
+                    pg_inputs,
+                    pn_inputs,
+                    pd_expected);
+}
+
+template <typename Tg, typename Tn, typename Td>
+static void PnextHelper(Test* config,
+                        unsigned lane_size_in_bits,
+                        const Tg& pg_inputs,
+                        const Tn& pn_inputs,
+                        const Td& pd_expected) {
+  PfirstPnextHelper(config,
+                    &MacroAssembler::Pnext,
+                    lane_size_in_bits,
+                    pg_inputs,
+                    pn_inputs,
+                    pd_expected);
+}
+
+TEST_SVE(sve_pfirst) {
+  // Provide more lanes than kPRegMinSize (to check propagation if we have a
+  // large VL), but few enough to make the test easy to read.
+  int in0[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int in1[] = {1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0};
+  int in2[] = {0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+  int in3[] = {0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1};
+  int in4[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  VIXL_ASSERT(ArrayLength(in0) > kPRegMinSize);
+
+  // Pfirst finds the first active lane in pg, and activates the corresponding
+  // lane in pn (if it isn't already active).
+
+  //                             The first active lane in in1 is here. |
+  //                                                                   v
+  int exp10[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0};
+  int exp12[] = {0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0};
+  int exp13[] = {0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1};
+  int exp14[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0};
+  PfirstHelper(config, in1, in0, exp10);
+  PfirstHelper(config, in1, in2, exp12);
+  PfirstHelper(config, in1, in3, exp13);
+  PfirstHelper(config, in1, in4, exp14);
+
+  //                          The first active lane in in2 is here. |
+  //                                                                v
+  int exp20[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0};
+  int exp21[] = {1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0};
+  int exp23[] = {0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1};
+  int exp24[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0};
+  PfirstHelper(config, in2, in0, exp20);
+  PfirstHelper(config, in2, in1, exp21);
+  PfirstHelper(config, in2, in3, exp23);
+  PfirstHelper(config, in2, in4, exp24);
+
+  //                                   The first active lane in in3 is here. |
+  //                                                                         v
+  int exp30[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  int exp31[] = {1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1};
+  int exp32[] = {0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1};
+  int exp34[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  PfirstHelper(config, in3, in0, exp30);
+  PfirstHelper(config, in3, in1, exp31);
+  PfirstHelper(config, in3, in2, exp32);
+  PfirstHelper(config, in3, in4, exp34);
+
+  //             | The first active lane in in4 is here.
+  //             v
+  int exp40[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp41[] = {1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0};
+  int exp42[] = {1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+  int exp43[] = {1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1};
+  PfirstHelper(config, in4, in0, exp40);
+  PfirstHelper(config, in4, in1, exp41);
+  PfirstHelper(config, in4, in2, exp42);
+  PfirstHelper(config, in4, in3, exp43);
+
+  // If pg is all inactive, the input is passed through unchanged.
+  PfirstHelper(config, in0, in0, in0);
+  PfirstHelper(config, in0, in1, in1);
+  PfirstHelper(config, in0, in2, in2);
+  PfirstHelper(config, in0, in3, in3);
+
+  // If the values of pg and pn match, the value is passed through unchanged.
+  PfirstHelper(config, in0, in0, in0);
+  PfirstHelper(config, in1, in1, in1);
+  PfirstHelper(config, in2, in2, in2);
+  PfirstHelper(config, in3, in3, in3);
+}
+
+TEST_SVE(sve_pfirst_alias) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Check that the Simulator behaves correctly when all arguments are aliased.
+  int in_b[] = {0, 0, 1, 1, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0, 0};
+  int in_h[] = {0, 0, 0, 0, 1, 1, 0, 0};
+  int in_s[] = {0, 1, 1, 0};
+  int in_d[] = {1, 1};
+
+  Initialise(&masm, p0.VnB(), in_b);
+  Initialise(&masm, p1.VnH(), in_h);
+  Initialise(&masm, p2.VnS(), in_s);
+  Initialise(&masm, p3.VnD(), in_d);
+
+  // Initialise NZCV to an impossible value, to check that we actually write it.
+  __ Mov(x10, NZCVFlag);
+
+  __ Msr(NZCV, x10);
+  __ Pfirst(p0.VnB(), p0, p0.VnB());
+  __ Mrs(x0, NZCV);
+
+  __ Msr(NZCV, x10);
+  __ Pfirst(p1.VnB(), p1, p1.VnB());
+  __ Mrs(x1, NZCV);
+
+  __ Msr(NZCV, x10);
+  __ Pfirst(p2.VnB(), p2, p2.VnB());
+  __ Mrs(x2, NZCV);
+
+  __ Msr(NZCV, x10);
+  __ Pfirst(p3.VnB(), p3, p3.VnB());
+  __ Mrs(x3, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // The first lane from pg is already active in pdn, so the P register should
+    // be unchanged.
+    ASSERT_EQUAL_SVE(in_b, p0.VnB());
+    ASSERT_EQUAL_SVE(in_h, p1.VnH());
+    ASSERT_EQUAL_SVE(in_s, p2.VnS());
+    ASSERT_EQUAL_SVE(in_d, p3.VnD());
+
+    ASSERT_EQUAL_64(SVEFirstFlag, x0);
+    ASSERT_EQUAL_64(SVEFirstFlag, x1);
+    ASSERT_EQUAL_64(SVEFirstFlag, x2);
+    ASSERT_EQUAL_64(SVEFirstFlag, x3);
+  }
+}
+
+TEST_SVE(sve_pnext_b) {
+  // TODO: Once we have the infrastructure, provide more lanes than kPRegMinSize
+  // (to check propagation if we have a large VL), but few enough to make the
+  // test easy to read.
+  // For now, we just use kPRegMinSize so that the test works anywhere.
+  int in0[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int in1[] = {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0};
+  int in2[] = {0, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+  int in3[] = {0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 1, 1};
+  int in4[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  // Pnext activates the next element that is true in pg, after the last-active
+  // element in pn. If all pn elements are false (as in in0), it starts looking
+  // at element 0.
+
+  // There are no active lanes in in0, so the result is simply the first active
+  // lane from pg.
+  int exp00[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp10[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0};
+  int exp20[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0};
+  int exp30[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  int exp40[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  //      The last active lane in in1 is here. |
+  //                                           v
+  int exp01[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp11[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp21[] = {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp31[] = {0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp41[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  //                | The last active lane in in2 is here.
+  //                v
+  int exp02[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp12[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp22[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp32[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp42[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  //                               | The last active lane in in3 is here.
+  //                               v
+  int exp03[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp13[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp23[] = {0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp33[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp43[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  //             | The last active lane in in4 is here.
+  //             v
+  int exp04[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp14[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp24[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp34[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp44[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  PnextHelper(config, kBRegSize, in0, in0, exp00);
+  PnextHelper(config, kBRegSize, in1, in0, exp10);
+  PnextHelper(config, kBRegSize, in2, in0, exp20);
+  PnextHelper(config, kBRegSize, in3, in0, exp30);
+  PnextHelper(config, kBRegSize, in4, in0, exp40);
+
+  PnextHelper(config, kBRegSize, in0, in1, exp01);
+  PnextHelper(config, kBRegSize, in1, in1, exp11);
+  PnextHelper(config, kBRegSize, in2, in1, exp21);
+  PnextHelper(config, kBRegSize, in3, in1, exp31);
+  PnextHelper(config, kBRegSize, in4, in1, exp41);
+
+  PnextHelper(config, kBRegSize, in0, in2, exp02);
+  PnextHelper(config, kBRegSize, in1, in2, exp12);
+  PnextHelper(config, kBRegSize, in2, in2, exp22);
+  PnextHelper(config, kBRegSize, in3, in2, exp32);
+  PnextHelper(config, kBRegSize, in4, in2, exp42);
+
+  PnextHelper(config, kBRegSize, in0, in3, exp03);
+  PnextHelper(config, kBRegSize, in1, in3, exp13);
+  PnextHelper(config, kBRegSize, in2, in3, exp23);
+  PnextHelper(config, kBRegSize, in3, in3, exp33);
+  PnextHelper(config, kBRegSize, in4, in3, exp43);
+
+  PnextHelper(config, kBRegSize, in0, in4, exp04);
+  PnextHelper(config, kBRegSize, in1, in4, exp14);
+  PnextHelper(config, kBRegSize, in2, in4, exp24);
+  PnextHelper(config, kBRegSize, in3, in4, exp34);
+  PnextHelper(config, kBRegSize, in4, in4, exp44);
+}
+
+TEST_SVE(sve_pnext_h) {
+  // TODO: Once we have the infrastructure, provide more lanes than kPRegMinSize
+  // (to check propagation if we have a large VL), but few enough to make the
+  // test easy to read.
+  // For now, we just use kPRegMinSize so that the test works anywhere.
+  int in0[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int in1[] = {0, 0, 0, 1, 0, 2, 1, 0};
+  int in2[] = {0, 1, 2, 0, 2, 0, 2, 0};
+  int in3[] = {0, 0, 0, 3, 0, 0, 0, 3};
+  int in4[] = {3, 0, 0, 0, 0, 0, 0, 0};
+
+  // Pnext activates the next element that is true in pg, after the last-active
+  // element in pn. If all pn elements are false (as in in0), it starts looking
+  // at element 0.
+  //
+  // As for other SVE instructions, elements are only considered to be active if
+  // the _first_ bit in each field is one. Other bits are ignored.
+
+  // There are no active lanes in in0, so the result is simply the first active
+  // lane from pg.
+  int exp00[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp10[] = {0, 0, 0, 0, 0, 0, 1, 0};
+  int exp20[] = {0, 1, 0, 0, 0, 0, 0, 0};
+  int exp30[] = {0, 0, 0, 0, 0, 0, 0, 1};
+  int exp40[] = {1, 0, 0, 0, 0, 0, 0, 0};
+
+  //                      | The last active lane in in1 is here.
+  //                      v
+  int exp01[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp11[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp21[] = {0, 1, 0, 0, 0, 0, 0, 0};
+  int exp31[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp41[] = {1, 0, 0, 0, 0, 0, 0, 0};
+
+  //                | The last active lane in in2 is here.
+  //                v
+  int exp02[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp12[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp22[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp32[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp42[] = {1, 0, 0, 0, 0, 0, 0, 0};
+
+  //                      | The last active lane in in3 is here.
+  //                      v
+  int exp03[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp13[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp23[] = {0, 1, 0, 0, 0, 0, 0, 0};
+  int exp33[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp43[] = {1, 0, 0, 0, 0, 0, 0, 0};
+
+  //             | The last active lane in in4 is here.
+  //             v
+  int exp04[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp14[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp24[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp34[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int exp44[] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+  PnextHelper(config, kHRegSize, in0, in0, exp00);
+  PnextHelper(config, kHRegSize, in1, in0, exp10);
+  PnextHelper(config, kHRegSize, in2, in0, exp20);
+  PnextHelper(config, kHRegSize, in3, in0, exp30);
+  PnextHelper(config, kHRegSize, in4, in0, exp40);
+
+  PnextHelper(config, kHRegSize, in0, in1, exp01);
+  PnextHelper(config, kHRegSize, in1, in1, exp11);
+  PnextHelper(config, kHRegSize, in2, in1, exp21);
+  PnextHelper(config, kHRegSize, in3, in1, exp31);
+  PnextHelper(config, kHRegSize, in4, in1, exp41);
+
+  PnextHelper(config, kHRegSize, in0, in2, exp02);
+  PnextHelper(config, kHRegSize, in1, in2, exp12);
+  PnextHelper(config, kHRegSize, in2, in2, exp22);
+  PnextHelper(config, kHRegSize, in3, in2, exp32);
+  PnextHelper(config, kHRegSize, in4, in2, exp42);
+
+  PnextHelper(config, kHRegSize, in0, in3, exp03);
+  PnextHelper(config, kHRegSize, in1, in3, exp13);
+  PnextHelper(config, kHRegSize, in2, in3, exp23);
+  PnextHelper(config, kHRegSize, in3, in3, exp33);
+  PnextHelper(config, kHRegSize, in4, in3, exp43);
+
+  PnextHelper(config, kHRegSize, in0, in4, exp04);
+  PnextHelper(config, kHRegSize, in1, in4, exp14);
+  PnextHelper(config, kHRegSize, in2, in4, exp24);
+  PnextHelper(config, kHRegSize, in3, in4, exp34);
+  PnextHelper(config, kHRegSize, in4, in4, exp44);
+}
+
+TEST_SVE(sve_pnext_s) {
+  // TODO: Once we have the infrastructure, provide more lanes than kPRegMinSize
+  // (to check propagation if we have a large VL), but few enough to make the
+  // test easy to read.
+  // For now, we just use kPRegMinSize so that the test works anywhere.
+  int in0[] = {0xe, 0xc, 0x8, 0x0};
+  int in1[] = {0x0, 0x2, 0x0, 0x1};
+  int in2[] = {0x0, 0x1, 0xf, 0x0};
+  int in3[] = {0xf, 0x0, 0x0, 0x0};
+
+  // Pnext activates the next element that is true in pg, after the last-active
+  // element in pn. If all pn elements are false (as in in0), it starts looking
+  // at element 0.
+  //
+  // As for other SVE instructions, elements are only considered to be active if
+  // the _first_ bit in each field is one. Other bits are ignored.
+
+  // There are no active lanes in in0, so the result is simply the first active
+  // lane from pg.
+  int exp00[] = {0, 0, 0, 0};
+  int exp10[] = {0, 0, 0, 1};
+  int exp20[] = {0, 0, 1, 0};
+  int exp30[] = {1, 0, 0, 0};
+
+  //                      | The last active lane in in1 is here.
+  //                      v
+  int exp01[] = {0, 0, 0, 0};
+  int exp11[] = {0, 0, 0, 0};
+  int exp21[] = {0, 0, 1, 0};
+  int exp31[] = {1, 0, 0, 0};
+
+  //                | The last active lane in in2 is here.
+  //                v
+  int exp02[] = {0, 0, 0, 0};
+  int exp12[] = {0, 0, 0, 0};
+  int exp22[] = {0, 0, 0, 0};
+  int exp32[] = {1, 0, 0, 0};
+
+  //             | The last active lane in in3 is here.
+  //             v
+  int exp03[] = {0, 0, 0, 0};
+  int exp13[] = {0, 0, 0, 0};
+  int exp23[] = {0, 0, 0, 0};
+  int exp33[] = {0, 0, 0, 0};
+
+  PnextHelper(config, kSRegSize, in0, in0, exp00);
+  PnextHelper(config, kSRegSize, in1, in0, exp10);
+  PnextHelper(config, kSRegSize, in2, in0, exp20);
+  PnextHelper(config, kSRegSize, in3, in0, exp30);
+
+  PnextHelper(config, kSRegSize, in0, in1, exp01);
+  PnextHelper(config, kSRegSize, in1, in1, exp11);
+  PnextHelper(config, kSRegSize, in2, in1, exp21);
+  PnextHelper(config, kSRegSize, in3, in1, exp31);
+
+  PnextHelper(config, kSRegSize, in0, in2, exp02);
+  PnextHelper(config, kSRegSize, in1, in2, exp12);
+  PnextHelper(config, kSRegSize, in2, in2, exp22);
+  PnextHelper(config, kSRegSize, in3, in2, exp32);
+
+  PnextHelper(config, kSRegSize, in0, in3, exp03);
+  PnextHelper(config, kSRegSize, in1, in3, exp13);
+  PnextHelper(config, kSRegSize, in2, in3, exp23);
+  PnextHelper(config, kSRegSize, in3, in3, exp33);
+}
+
+TEST_SVE(sve_pnext_d) {
+  // TODO: Once we have the infrastructure, provide more lanes than kPRegMinSize
+  // (to check propagation if we have a large VL), but few enough to make the
+  // test easy to read.
+  // For now, we just use kPRegMinSize so that the test works anywhere.
+  int in0[] = {0xfe, 0xf0};
+  int in1[] = {0x00, 0x55};
+  int in2[] = {0x33, 0xff};
+
+  // Pnext activates the next element that is true in pg, after the last-active
+  // element in pn. If all pn elements are false (as in in0), it starts looking
+  // at element 0.
+  //
+  // As for other SVE instructions, elements are only considered to be active if
+  // the _first_ bit in each field is one. Other bits are ignored.
+
+  // There are no active lanes in in0, so the result is simply the first active
+  // lane from pg.
+  int exp00[] = {0, 0};
+  int exp10[] = {0, 1};
+  int exp20[] = {0, 1};
+
+  //                | The last active lane in in1 is here.
+  //                v
+  int exp01[] = {0, 0};
+  int exp11[] = {0, 0};
+  int exp21[] = {1, 0};
+
+  //             | The last active lane in in2 is here.
+  //             v
+  int exp02[] = {0, 0};
+  int exp12[] = {0, 0};
+  int exp22[] = {0, 0};
+
+  PnextHelper(config, kDRegSize, in0, in0, exp00);
+  PnextHelper(config, kDRegSize, in1, in0, exp10);
+  PnextHelper(config, kDRegSize, in2, in0, exp20);
+
+  PnextHelper(config, kDRegSize, in0, in1, exp01);
+  PnextHelper(config, kDRegSize, in1, in1, exp11);
+  PnextHelper(config, kDRegSize, in2, in1, exp21);
+
+  PnextHelper(config, kDRegSize, in0, in2, exp02);
+  PnextHelper(config, kDRegSize, in1, in2, exp12);
+  PnextHelper(config, kDRegSize, in2, in2, exp22);
+}
+
+TEST_SVE(sve_pnext_alias) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Check that the Simulator behaves correctly when all arguments are aliased.
+  int in_b[] = {0, 0, 1, 1, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 0, 0};
+  int in_h[] = {0, 0, 0, 0, 1, 1, 0, 0};
+  int in_s[] = {0, 1, 1, 0};
+  int in_d[] = {1, 1};
+
+  Initialise(&masm, p0.VnB(), in_b);
+  Initialise(&masm, p1.VnH(), in_h);
+  Initialise(&masm, p2.VnS(), in_s);
+  Initialise(&masm, p3.VnD(), in_d);
+
+  // Initialise NZCV to an impossible value, to check that we actually write it.
+  __ Mov(x10, NZCVFlag);
+
+  __ Msr(NZCV, x10);
+  __ Pnext(p0.VnB(), p0, p0.VnB());
+  __ Mrs(x0, NZCV);
+
+  __ Msr(NZCV, x10);
+  __ Pnext(p1.VnB(), p1, p1.VnB());
+  __ Mrs(x1, NZCV);
+
+  __ Msr(NZCV, x10);
+  __ Pnext(p2.VnB(), p2, p2.VnB());
+  __ Mrs(x2, NZCV);
+
+  __ Msr(NZCV, x10);
+  __ Pnext(p3.VnB(), p3, p3.VnB());
+  __ Mrs(x3, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Since pg.Is(pdn), there can be no active lanes in pg above the last
+    // active lane in pdn, so the result should always be zero.
+    ASSERT_EQUAL_SVE(0, p0.VnB());
+    ASSERT_EQUAL_SVE(0, p1.VnH());
+    ASSERT_EQUAL_SVE(0, p2.VnS());
+    ASSERT_EQUAL_SVE(0, p3.VnD());
+
+    ASSERT_EQUAL_64(SVENoneFlag | SVENotLastFlag, x0);
+    ASSERT_EQUAL_64(SVENoneFlag | SVENotLastFlag, x1);
+    ASSERT_EQUAL_64(SVENoneFlag | SVENotLastFlag, x2);
+    ASSERT_EQUAL_64(SVENoneFlag | SVENotLastFlag, x3);
+  }
+}
+
+static void PtrueHelper(Test* config,
+                        unsigned lane_size_in_bits,
+                        FlagsUpdate s = LeaveFlags) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  PRegisterWithLaneSize p[kNumberOfPRegisters];
+  for (unsigned i = 0; i < kNumberOfPRegisters; i++) {
+    p[i] = PRegister(i).WithLaneSize(lane_size_in_bits);
+  }
+
+  // Initialise NZCV to an impossible value, to check that we actually write it.
+  StatusFlags nzcv_unmodified = NZCVFlag;
+  __ Mov(x20, nzcv_unmodified);
+
+  // We don't have enough registers to conveniently test every pattern, so take
+  // samples from each group.
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[0], SVE_POW2, s);
+  __ Mrs(x0, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[1], SVE_VL1, s);
+  __ Mrs(x1, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[2], SVE_VL2, s);
+  __ Mrs(x2, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[3], SVE_VL5, s);
+  __ Mrs(x3, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[4], SVE_VL6, s);
+  __ Mrs(x4, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[5], SVE_VL8, s);
+  __ Mrs(x5, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[6], SVE_VL16, s);
+  __ Mrs(x6, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[7], SVE_VL64, s);
+  __ Mrs(x7, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[8], SVE_VL256, s);
+  __ Mrs(x8, NZCV);
+
+  {
+    // We have to use the Assembler to use values not defined by
+    // SVEPredicateConstraint, so call `ptrues` directly..
+    typedef void (
+        MacroAssembler::*AssemblePtrueFn)(const PRegisterWithLaneSize& pd,
+                                          int pattern);
+    AssemblePtrueFn assemble =
+        (s == SetFlags) ? &MacroAssembler::ptrues : &MacroAssembler::ptrue;
+
+    ExactAssemblyScope guard(&masm, 12 * kInstructionSize);
+    __ msr(NZCV, x20);
+    (masm.*assemble)(p[9], 0xe);
+    __ mrs(x9, NZCV);
+
+    __ msr(NZCV, x20);
+    (masm.*assemble)(p[10], 0x16);
+    __ mrs(x10, NZCV);
+
+    __ msr(NZCV, x20);
+    (masm.*assemble)(p[11], 0x1a);
+    __ mrs(x11, NZCV);
+
+    __ msr(NZCV, x20);
+    (masm.*assemble)(p[12], 0x1c);
+    __ mrs(x12, NZCV);
+  }
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[13], SVE_MUL4, s);
+  __ Mrs(x13, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[14], SVE_MUL3, s);
+  __ Mrs(x14, NZCV);
+
+  __ Msr(NZCV, x20);
+  __ Ptrue(p[15], SVE_ALL, s);
+  __ Mrs(x15, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int all = core.GetSVELaneCount(lane_size_in_bits);
+    int pow2 = 1 << HighestSetBitPosition(all);
+    int mul4 = all - (all % 4);
+    int mul3 = all - (all % 3);
+
+    // Check P register results.
+    for (int i = 0; i < all; i++) {
+      ASSERT_EQUAL_SVE_LANE(i < pow2, p[0], i);
+      ASSERT_EQUAL_SVE_LANE((all >= 1) && (i < 1), p[1], i);
+      ASSERT_EQUAL_SVE_LANE((all >= 2) && (i < 2), p[2], i);
+      ASSERT_EQUAL_SVE_LANE((all >= 5) && (i < 5), p[3], i);
+      ASSERT_EQUAL_SVE_LANE((all >= 6) && (i < 6), p[4], i);
+      ASSERT_EQUAL_SVE_LANE((all >= 8) && (i < 8), p[5], i);
+      ASSERT_EQUAL_SVE_LANE((all >= 16) && (i < 16), p[6], i);
+      ASSERT_EQUAL_SVE_LANE((all >= 64) && (i < 64), p[7], i);
+      ASSERT_EQUAL_SVE_LANE((all >= 256) && (i < 256), p[8], i);
+      ASSERT_EQUAL_SVE_LANE(false, p[9], i);
+      ASSERT_EQUAL_SVE_LANE(false, p[10], i);
+      ASSERT_EQUAL_SVE_LANE(false, p[11], i);
+      ASSERT_EQUAL_SVE_LANE(false, p[12], i);
+      ASSERT_EQUAL_SVE_LANE(i < mul4, p[13], i);
+      ASSERT_EQUAL_SVE_LANE(i < mul3, p[14], i);
+      ASSERT_EQUAL_SVE_LANE(true, p[15], i);
+    }
+
+    // Check NZCV results.
+    if (s == LeaveFlags) {
+      // No flags should have been updated.
+      for (int i = 0; i <= 15; i++) {
+        ASSERT_EQUAL_64(nzcv_unmodified, XRegister(i));
+      }
+    } else {
+      StatusFlags zero = static_cast<StatusFlags>(SVENoneFlag | SVENotLastFlag);
+      StatusFlags nonzero = SVEFirstFlag;
+
+      // POW2
+      ASSERT_EQUAL_64(nonzero, x0);
+      // VL*
+      ASSERT_EQUAL_64((all >= 1) ? nonzero : zero, x1);
+      ASSERT_EQUAL_64((all >= 2) ? nonzero : zero, x2);
+      ASSERT_EQUAL_64((all >= 5) ? nonzero : zero, x3);
+      ASSERT_EQUAL_64((all >= 6) ? nonzero : zero, x4);
+      ASSERT_EQUAL_64((all >= 8) ? nonzero : zero, x5);
+      ASSERT_EQUAL_64((all >= 16) ? nonzero : zero, x6);
+      ASSERT_EQUAL_64((all >= 64) ? nonzero : zero, x7);
+      ASSERT_EQUAL_64((all >= 256) ? nonzero : zero, x8);
+      // #uimm5
+      ASSERT_EQUAL_64(zero, x9);
+      ASSERT_EQUAL_64(zero, x10);
+      ASSERT_EQUAL_64(zero, x11);
+      ASSERT_EQUAL_64(zero, x12);
+      // MUL*
+      ASSERT_EQUAL_64((all >= 4) ? nonzero : zero, x13);
+      ASSERT_EQUAL_64((all >= 3) ? nonzero : zero, x14);
+      // ALL
+      ASSERT_EQUAL_64(nonzero, x15);
+    }
+  }
+}
+
+TEST_SVE(sve_ptrue_b) { PtrueHelper(config, kBRegSize, LeaveFlags); }
+TEST_SVE(sve_ptrue_h) { PtrueHelper(config, kHRegSize, LeaveFlags); }
+TEST_SVE(sve_ptrue_s) { PtrueHelper(config, kSRegSize, LeaveFlags); }
+TEST_SVE(sve_ptrue_d) { PtrueHelper(config, kDRegSize, LeaveFlags); }
+
+TEST_SVE(sve_ptrues_b) { PtrueHelper(config, kBRegSize, SetFlags); }
+TEST_SVE(sve_ptrues_h) { PtrueHelper(config, kHRegSize, SetFlags); }
+TEST_SVE(sve_ptrues_s) { PtrueHelper(config, kSRegSize, SetFlags); }
+TEST_SVE(sve_ptrues_d) { PtrueHelper(config, kDRegSize, SetFlags); }
+
+TEST_SVE(sve_pfalse) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Initialise non-zero inputs.
+  __ Ptrue(p0.VnB());
+  __ Ptrue(p1.VnH());
+  __ Ptrue(p2.VnS());
+  __ Ptrue(p3.VnD());
+
+  // The instruction only supports B-sized lanes, but the lane size has no
+  // logical effect, so the MacroAssembler accepts anything.
+  __ Pfalse(p0.VnB());
+  __ Pfalse(p1.VnH());
+  __ Pfalse(p2.VnS());
+  __ Pfalse(p3.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(0, p0.VnB());
+    ASSERT_EQUAL_SVE(0, p1.VnB());
+    ASSERT_EQUAL_SVE(0, p2.VnB());
+    ASSERT_EQUAL_SVE(0, p3.VnB());
+  }
+}
+
+TEST_SVE(sve_ptest) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Initialise NZCV to a known (impossible) value.
+  StatusFlags nzcv_unmodified = NZCVFlag;
+  __ Mov(x0, nzcv_unmodified);
+  __ Msr(NZCV, x0);
+
+  // Construct some test inputs.
+  int in2[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0};
+  int in3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0};
+  int in4[] = {0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0};
+  __ Pfalse(p0.VnB());
+  __ Ptrue(p1.VnB());
+  Initialise(&masm, p2.VnB(), in2);
+  Initialise(&masm, p3.VnB(), in3);
+  Initialise(&masm, p4.VnB(), in4);
+
+  // All-inactive pg.
+  __ Ptest(p0, p0.VnB());
+  __ Mrs(x0, NZCV);
+  __ Ptest(p0, p1.VnB());
+  __ Mrs(x1, NZCV);
+  __ Ptest(p0, p2.VnB());
+  __ Mrs(x2, NZCV);
+  __ Ptest(p0, p3.VnB());
+  __ Mrs(x3, NZCV);
+  __ Ptest(p0, p4.VnB());
+  __ Mrs(x4, NZCV);
+
+  // All-active pg.
+  __ Ptest(p1, p0.VnB());
+  __ Mrs(x5, NZCV);
+  __ Ptest(p1, p1.VnB());
+  __ Mrs(x6, NZCV);
+  __ Ptest(p1, p2.VnB());
+  __ Mrs(x7, NZCV);
+  __ Ptest(p1, p3.VnB());
+  __ Mrs(x8, NZCV);
+  __ Ptest(p1, p4.VnB());
+  __ Mrs(x9, NZCV);
+
+  // Combinations of other inputs.
+  __ Ptest(p2, p2.VnB());
+  __ Mrs(x20, NZCV);
+  __ Ptest(p2, p3.VnB());
+  __ Mrs(x21, NZCV);
+  __ Ptest(p2, p4.VnB());
+  __ Mrs(x22, NZCV);
+  __ Ptest(p3, p2.VnB());
+  __ Mrs(x23, NZCV);
+  __ Ptest(p3, p3.VnB());
+  __ Mrs(x24, NZCV);
+  __ Ptest(p3, p4.VnB());
+  __ Mrs(x25, NZCV);
+  __ Ptest(p4, p2.VnB());
+  __ Mrs(x26, NZCV);
+  __ Ptest(p4, p3.VnB());
+  __ Mrs(x27, NZCV);
+  __ Ptest(p4, p4.VnB());
+  __ Mrs(x28, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    StatusFlags zero = static_cast<StatusFlags>(SVENoneFlag | SVENotLastFlag);
+
+    // If pg is all inactive, the value of pn is irrelevant.
+    ASSERT_EQUAL_64(zero, x0);
+    ASSERT_EQUAL_64(zero, x1);
+    ASSERT_EQUAL_64(zero, x2);
+    ASSERT_EQUAL_64(zero, x3);
+    ASSERT_EQUAL_64(zero, x4);
+
+    // All-active pg.
+    ASSERT_EQUAL_64(zero, x5);          // All-inactive pn.
+    ASSERT_EQUAL_64(SVEFirstFlag, x6);  // All-active pn.
+    // Other pn inputs are non-zero, but the first and last lanes are inactive.
+    ASSERT_EQUAL_64(SVENotLastFlag, x7);
+    ASSERT_EQUAL_64(SVENotLastFlag, x8);
+    ASSERT_EQUAL_64(SVENotLastFlag, x9);
+
+    // Other inputs.
+    ASSERT_EQUAL_64(SVEFirstFlag, x20);  // pg: in2, pn: in2
+    ASSERT_EQUAL_64(NoFlag, x21);        // pg: in2, pn: in3
+    ASSERT_EQUAL_64(zero, x22);          // pg: in2, pn: in4
+    ASSERT_EQUAL_64(static_cast<StatusFlags>(SVEFirstFlag | SVENotLastFlag),
+                    x23);                // pg: in3, pn: in2
+    ASSERT_EQUAL_64(SVEFirstFlag, x24);  // pg: in3, pn: in3
+    ASSERT_EQUAL_64(zero, x25);          // pg: in3, pn: in4
+    ASSERT_EQUAL_64(zero, x26);          // pg: in4, pn: in2
+    ASSERT_EQUAL_64(zero, x27);          // pg: in4, pn: in3
+    ASSERT_EQUAL_64(SVEFirstFlag, x28);  // pg: in4, pn: in4
+  }
+}
+
+TEST_SVE(sve_cntp) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // There are {7, 5, 2, 1} active {B, H, S, D} lanes.
+  int p0_inputs[] = {0, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0};
+  Initialise(&masm, p0.VnB(), p0_inputs);
+
+  // With an all-true predicate, these instructions measure the vector length.
+  __ Ptrue(p10.VnB());
+  __ Ptrue(p11.VnH());
+  __ Ptrue(p12.VnS());
+  __ Ptrue(p13.VnD());
+
+  // `ptrue p10.b` provides an all-active pg.
+  __ Cntp(x10, p10, p10.VnB());
+  __ Cntp(x11, p10, p11.VnH());
+  __ Cntp(x12, p10, p12.VnS());
+  __ Cntp(x13, p10, p13.VnD());
+
+  // Check that the predicate mask is applied properly.
+  __ Cntp(x14, p10, p10.VnB());
+  __ Cntp(x15, p11, p10.VnB());
+  __ Cntp(x16, p12, p10.VnB());
+  __ Cntp(x17, p13, p10.VnB());
+
+  // Check other patterns (including some ignored bits).
+  __ Cntp(x0, p10, p0.VnB());
+  __ Cntp(x1, p10, p0.VnH());
+  __ Cntp(x2, p10, p0.VnS());
+  __ Cntp(x3, p10, p0.VnD());
+  __ Cntp(x4, p0, p10.VnB());
+  __ Cntp(x5, p0, p10.VnH());
+  __ Cntp(x6, p0, p10.VnS());
+  __ Cntp(x7, p0, p10.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int vl_b = core.GetSVELaneCount(kBRegSize);
+    int vl_h = core.GetSVELaneCount(kHRegSize);
+    int vl_s = core.GetSVELaneCount(kSRegSize);
+    int vl_d = core.GetSVELaneCount(kDRegSize);
+
+    // Check all-active predicates in various combinations.
+    ASSERT_EQUAL_64(vl_b, x10);
+    ASSERT_EQUAL_64(vl_h, x11);
+    ASSERT_EQUAL_64(vl_s, x12);
+    ASSERT_EQUAL_64(vl_d, x13);
+
+    ASSERT_EQUAL_64(vl_b, x14);
+    ASSERT_EQUAL_64(vl_h, x15);
+    ASSERT_EQUAL_64(vl_s, x16);
+    ASSERT_EQUAL_64(vl_d, x17);
+
+    // Check that irrelevant bits are properly ignored.
+    ASSERT_EQUAL_64(7, x0);
+    ASSERT_EQUAL_64(5, x1);
+    ASSERT_EQUAL_64(2, x2);
+    ASSERT_EQUAL_64(1, x3);
+
+    ASSERT_EQUAL_64(7, x4);
+    ASSERT_EQUAL_64(5, x5);
+    ASSERT_EQUAL_64(2, x6);
+    ASSERT_EQUAL_64(1, x7);
+  }
+}
+
+typedef void (MacroAssembler::*CntFn)(const Register& dst,
+                                      int pattern,
+                                      int multiplier);
+
+template <typename T>
+void GenerateCntSequence(MacroAssembler* masm,
+                         CntFn cnt,
+                         T acc_value,
+                         int multiplier) {
+  // Initialise accumulators.
+  masm->Mov(x0, acc_value);
+  masm->Mov(x1, acc_value);
+  masm->Mov(x2, acc_value);
+  masm->Mov(x3, acc_value);
+  masm->Mov(x4, acc_value);
+  masm->Mov(x5, acc_value);
+  masm->Mov(x6, acc_value);
+  masm->Mov(x7, acc_value);
+  masm->Mov(x8, acc_value);
+  masm->Mov(x9, acc_value);
+  masm->Mov(x10, acc_value);
+  masm->Mov(x11, acc_value);
+  masm->Mov(x12, acc_value);
+  masm->Mov(x13, acc_value);
+  masm->Mov(x14, acc_value);
+  masm->Mov(x15, acc_value);
+  masm->Mov(x18, acc_value);
+  masm->Mov(x19, acc_value);
+  masm->Mov(x20, acc_value);
+  masm->Mov(x21, acc_value);
+
+  (masm->*cnt)(Register(0, sizeof(T) * kBitsPerByte), SVE_POW2, multiplier);
+  (masm->*cnt)(Register(1, sizeof(T) * kBitsPerByte), SVE_VL1, multiplier);
+  (masm->*cnt)(Register(2, sizeof(T) * kBitsPerByte), SVE_VL2, multiplier);
+  (masm->*cnt)(Register(3, sizeof(T) * kBitsPerByte), SVE_VL3, multiplier);
+  (masm->*cnt)(Register(4, sizeof(T) * kBitsPerByte), SVE_VL4, multiplier);
+  (masm->*cnt)(Register(5, sizeof(T) * kBitsPerByte), SVE_VL5, multiplier);
+  (masm->*cnt)(Register(6, sizeof(T) * kBitsPerByte), SVE_VL6, multiplier);
+  (masm->*cnt)(Register(7, sizeof(T) * kBitsPerByte), SVE_VL7, multiplier);
+  (masm->*cnt)(Register(8, sizeof(T) * kBitsPerByte), SVE_VL8, multiplier);
+  (masm->*cnt)(Register(9, sizeof(T) * kBitsPerByte), SVE_VL16, multiplier);
+  (masm->*cnt)(Register(10, sizeof(T) * kBitsPerByte), SVE_VL32, multiplier);
+  (masm->*cnt)(Register(11, sizeof(T) * kBitsPerByte), SVE_VL64, multiplier);
+  (masm->*cnt)(Register(12, sizeof(T) * kBitsPerByte), SVE_VL128, multiplier);
+  (masm->*cnt)(Register(13, sizeof(T) * kBitsPerByte), SVE_VL256, multiplier);
+  (masm->*cnt)(Register(14, sizeof(T) * kBitsPerByte), 16, multiplier);
+  (masm->*cnt)(Register(15, sizeof(T) * kBitsPerByte), 23, multiplier);
+  (masm->*cnt)(Register(18, sizeof(T) * kBitsPerByte), 28, multiplier);
+  (masm->*cnt)(Register(19, sizeof(T) * kBitsPerByte), SVE_MUL4, multiplier);
+  (masm->*cnt)(Register(20, sizeof(T) * kBitsPerByte), SVE_MUL3, multiplier);
+  (masm->*cnt)(Register(21, sizeof(T) * kBitsPerByte), SVE_ALL, multiplier);
+}
+
+int FixedVL(int fixed, int length) {
+  VIXL_ASSERT(((fixed >= 1) && (fixed <= 8)) || (fixed == 16) ||
+              (fixed == 32) || (fixed == 64) || (fixed == 128) ||
+              (fixed = 256));
+  return (length >= fixed) ? fixed : 0;
+}
+
+static void CntHelper(Test* config,
+                      CntFn cnt,
+                      int multiplier,
+                      int lane_size_in_bits,
+                      int64_t acc_value = 0,
+                      bool is_increment = true) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+  GenerateCntSequence(&masm, cnt, acc_value, multiplier);
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int all = core.GetSVELaneCount(lane_size_in_bits);
+    int pow2 = 1 << HighestSetBitPosition(all);
+    int mul4 = all - (all % 4);
+    int mul3 = all - (all % 3);
+
+    multiplier = is_increment ? multiplier : -multiplier;
+
+    ASSERT_EQUAL_64(acc_value + (multiplier * pow2), x0);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(1, all)), x1);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(2, all)), x2);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(3, all)), x3);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(4, all)), x4);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(5, all)), x5);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(6, all)), x6);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(7, all)), x7);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(8, all)), x8);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(16, all)), x9);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(32, all)), x10);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(64, all)), x11);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(128, all)), x12);
+    ASSERT_EQUAL_64(acc_value + (multiplier * FixedVL(256, all)), x13);
+    ASSERT_EQUAL_64(acc_value, x14);
+    ASSERT_EQUAL_64(acc_value, x15);
+    ASSERT_EQUAL_64(acc_value, x18);
+    ASSERT_EQUAL_64(acc_value + (multiplier * mul4), x19);
+    ASSERT_EQUAL_64(acc_value + (multiplier * mul3), x20);
+    ASSERT_EQUAL_64(acc_value + (multiplier * all), x21);
+  }
+}
+
+static void IncHelper(Test* config,
+                      CntFn cnt,
+                      int multiplier,
+                      int lane_size_in_bits,
+                      int64_t acc_value) {
+  CntHelper(config, cnt, multiplier, lane_size_in_bits, acc_value, true);
+}
+
+static void DecHelper(Test* config,
+                      CntFn cnt,
+                      int multiplier,
+                      int lane_size_in_bits,
+                      int64_t acc_value) {
+  CntHelper(config, cnt, multiplier, lane_size_in_bits, acc_value, false);
+}
+
+TEST_SVE(sve_cntb) {
+  CntHelper(config, &MacroAssembler::Cntb, 1, kBRegSize);
+  CntHelper(config, &MacroAssembler::Cntb, 2, kBRegSize);
+  CntHelper(config, &MacroAssembler::Cntb, 15, kBRegSize);
+  CntHelper(config, &MacroAssembler::Cntb, 16, kBRegSize);
+}
+
+TEST_SVE(sve_cnth) {
+  CntHelper(config, &MacroAssembler::Cnth, 1, kHRegSize);
+  CntHelper(config, &MacroAssembler::Cnth, 2, kHRegSize);
+  CntHelper(config, &MacroAssembler::Cnth, 15, kHRegSize);
+  CntHelper(config, &MacroAssembler::Cnth, 16, kHRegSize);
+}
+
+TEST_SVE(sve_cntw) {
+  CntHelper(config, &MacroAssembler::Cntw, 1, kWRegSize);
+  CntHelper(config, &MacroAssembler::Cntw, 2, kWRegSize);
+  CntHelper(config, &MacroAssembler::Cntw, 15, kWRegSize);
+  CntHelper(config, &MacroAssembler::Cntw, 16, kWRegSize);
+}
+
+TEST_SVE(sve_cntd) {
+  CntHelper(config, &MacroAssembler::Cntd, 1, kDRegSize);
+  CntHelper(config, &MacroAssembler::Cntd, 2, kDRegSize);
+  CntHelper(config, &MacroAssembler::Cntd, 15, kDRegSize);
+  CntHelper(config, &MacroAssembler::Cntd, 16, kDRegSize);
+}
+
+TEST_SVE(sve_decb) {
+  DecHelper(config, &MacroAssembler::Decb, 1, kBRegSize, 42);
+  DecHelper(config, &MacroAssembler::Decb, 2, kBRegSize, -1);
+  DecHelper(config, &MacroAssembler::Decb, 15, kBRegSize, INT64_MIN);
+  DecHelper(config, &MacroAssembler::Decb, 16, kBRegSize, -42);
+}
+
+TEST_SVE(sve_dech) {
+  DecHelper(config, &MacroAssembler::Dech, 1, kHRegSize, 42);
+  DecHelper(config, &MacroAssembler::Dech, 2, kHRegSize, -1);
+  DecHelper(config, &MacroAssembler::Dech, 15, kHRegSize, INT64_MIN);
+  DecHelper(config, &MacroAssembler::Dech, 16, kHRegSize, -42);
+}
+
+TEST_SVE(sve_decw) {
+  DecHelper(config, &MacroAssembler::Decw, 1, kWRegSize, 42);
+  DecHelper(config, &MacroAssembler::Decw, 2, kWRegSize, -1);
+  DecHelper(config, &MacroAssembler::Decw, 15, kWRegSize, INT64_MIN);
+  DecHelper(config, &MacroAssembler::Decw, 16, kWRegSize, -42);
+}
+
+TEST_SVE(sve_decd) {
+  DecHelper(config, &MacroAssembler::Decd, 1, kDRegSize, 42);
+  DecHelper(config, &MacroAssembler::Decd, 2, kDRegSize, -1);
+  DecHelper(config, &MacroAssembler::Decd, 15, kDRegSize, INT64_MIN);
+  DecHelper(config, &MacroAssembler::Decd, 16, kDRegSize, -42);
+}
+
+TEST_SVE(sve_incb) {
+  IncHelper(config, &MacroAssembler::Incb, 1, kBRegSize, 42);
+  IncHelper(config, &MacroAssembler::Incb, 2, kBRegSize, -1);
+  IncHelper(config, &MacroAssembler::Incb, 15, kBRegSize, INT64_MAX);
+  IncHelper(config, &MacroAssembler::Incb, 16, kBRegSize, -42);
+}
+
+TEST_SVE(sve_inch) {
+  IncHelper(config, &MacroAssembler::Inch, 1, kHRegSize, 42);
+  IncHelper(config, &MacroAssembler::Inch, 2, kHRegSize, -1);
+  IncHelper(config, &MacroAssembler::Inch, 15, kHRegSize, INT64_MAX);
+  IncHelper(config, &MacroAssembler::Inch, 16, kHRegSize, -42);
+}
+
+TEST_SVE(sve_incw) {
+  IncHelper(config, &MacroAssembler::Incw, 1, kWRegSize, 42);
+  IncHelper(config, &MacroAssembler::Incw, 2, kWRegSize, -1);
+  IncHelper(config, &MacroAssembler::Incw, 15, kWRegSize, INT64_MAX);
+  IncHelper(config, &MacroAssembler::Incw, 16, kWRegSize, -42);
+}
+
+TEST_SVE(sve_incd) {
+  IncHelper(config, &MacroAssembler::Incd, 1, kDRegSize, 42);
+  IncHelper(config, &MacroAssembler::Incd, 2, kDRegSize, -1);
+  IncHelper(config, &MacroAssembler::Incd, 15, kDRegSize, INT64_MAX);
+  IncHelper(config, &MacroAssembler::Incd, 16, kDRegSize, -42);
+}
+
+template <typename T>
+static T QAdd(T x, int y) {
+  VIXL_ASSERT(y > INT_MIN);
+  T result;
+  T min = std::numeric_limits<T>::min();
+  T max = std::numeric_limits<T>::max();
+  if ((x >= 0) && (y >= 0)) {
+    // For positive a and b, saturate at max.
+    result = (max - x) < static_cast<T>(y) ? max : x + y;
+  } else if ((y < 0) && ((x < 0) || (min == 0))) {
+    // For negative b, where either a negative or T unsigned.
+    result = (x - min) < static_cast<T>(-y) ? min : x + y;
+  } else {
+    result = x + y;
+  }
+  return result;
+}
+
+template <typename T>
+static void QIncDecHelper(Test* config,
+                          CntFn cnt,
+                          int multiplier,
+                          int lane_size_in_bits,
+                          T acc_value,
+                          bool is_increment) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+  GenerateCntSequence(&masm, cnt, acc_value, multiplier);
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int all = core.GetSVELaneCount(lane_size_in_bits);
+    int pow2 = 1 << HighestSetBitPosition(all);
+    int mul4 = all - (all % 4);
+    int mul3 = all - (all % 3);
+
+    multiplier = is_increment ? multiplier : -multiplier;
+
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * pow2), x0);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(1, all)), x1);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(2, all)), x2);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(3, all)), x3);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(4, all)), x4);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(5, all)), x5);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(6, all)), x6);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(7, all)), x7);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(8, all)), x8);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(16, all)), x9);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(32, all)), x10);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(64, all)), x11);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(128, all)), x12);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(256, all)), x13);
+    ASSERT_EQUAL_64(acc_value, x14);
+    ASSERT_EQUAL_64(acc_value, x15);
+    ASSERT_EQUAL_64(acc_value, x18);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * mul4), x19);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * mul3), x20);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * all), x21);
+  }
+}
+
+template <typename T>
+static void QIncHelper(Test* config,
+                       CntFn cnt,
+                       int multiplier,
+                       int lane_size_in_bits,
+                       T acc_value) {
+  QIncDecHelper<T>(config, cnt, multiplier, lane_size_in_bits, acc_value, true);
+}
+
+template <typename T>
+static void QDecHelper(Test* config,
+                       CntFn cnt,
+                       int multiplier,
+                       int lane_size_in_bits,
+                       T acc_value) {
+  QIncDecHelper<T>(config,
+                   cnt,
+                   multiplier,
+                   lane_size_in_bits,
+                   acc_value,
+                   false);
+}
+
+TEST_SVE(sve_sqdecb) {
+  int64_t bigneg = INT64_MIN + 42;
+  int64_t bigpos = INT64_MAX - 42;
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecb, 1, kBRegSize, 1);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecb, 2, kBRegSize, bigneg);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecb, 15, kBRegSize, 999);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecb, 16, kBRegSize, bigpos);
+}
+
+TEST_SVE(sve_sqdech) {
+  int64_t bigneg = INT64_MIN + 42;
+  int64_t bigpos = INT64_MAX - 42;
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdech, 1, kHRegSize, 1);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdech, 2, kHRegSize, bigneg);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdech, 15, kHRegSize, 999);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdech, 16, kHRegSize, bigpos);
+}
+
+TEST_SVE(sve_sqdecw) {
+  int64_t bigneg = INT64_MIN + 42;
+  int64_t bigpos = INT64_MAX - 42;
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecw, 1, kWRegSize, 1);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecw, 2, kWRegSize, bigneg);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecw, 15, kWRegSize, 999);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecw, 16, kWRegSize, bigpos);
+}
+
+TEST_SVE(sve_sqdecd) {
+  int64_t bigneg = INT64_MIN + 42;
+  int64_t bigpos = INT64_MAX - 42;
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecd, 1, kDRegSize, 1);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecd, 2, kDRegSize, bigneg);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecd, 15, kDRegSize, 999);
+  QDecHelper<int64_t>(config, &MacroAssembler::Sqdecd, 16, kDRegSize, bigpos);
+}
+
+TEST_SVE(sve_sqincb) {
+  int64_t bigneg = INT64_MIN + 42;
+  int64_t bigpos = INT64_MAX - 42;
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincb, 1, kBRegSize, 1);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincb, 2, kBRegSize, bigneg);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincb, 15, kBRegSize, 999);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincb, 16, kBRegSize, bigpos);
+}
+
+TEST_SVE(sve_sqinch) {
+  int64_t bigneg = INT64_MIN + 42;
+  int64_t bigpos = INT64_MAX - 42;
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqinch, 1, kHRegSize, 1);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqinch, 2, kHRegSize, bigneg);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqinch, 15, kHRegSize, 999);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqinch, 16, kHRegSize, bigpos);
+}
+
+TEST_SVE(sve_sqincw) {
+  int64_t bigneg = INT64_MIN + 42;
+  int64_t bigpos = INT64_MAX - 42;
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincw, 1, kWRegSize, 1);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincw, 2, kWRegSize, bigneg);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincw, 15, kWRegSize, 999);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincw, 16, kWRegSize, bigpos);
+}
+
+TEST_SVE(sve_sqincd) {
+  int64_t bigneg = INT64_MIN + 42;
+  int64_t bigpos = INT64_MAX - 42;
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincd, 1, kDRegSize, 1);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincd, 2, kDRegSize, bigneg);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincd, 15, kDRegSize, 999);
+  QIncHelper<int64_t>(config, &MacroAssembler::Sqincd, 16, kDRegSize, bigpos);
+}
+
+TEST_SVE(sve_uqdecb) {
+  int32_t big32 = UINT32_MAX - 42;
+  int64_t big64 = UINT64_MAX - 42;
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecb, 1, kBRegSize, 1);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecb, 2, kBRegSize, 42);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecb, 15, kBRegSize, 999);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecb, 16, kBRegSize, big32);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecb, 1, kBRegSize, 1);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecb, 2, kBRegSize, 42);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecb, 15, kBRegSize, 999);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecb, 16, kBRegSize, big64);
+}
+
+TEST_SVE(sve_uqdech) {
+  int32_t big32 = UINT32_MAX - 42;
+  int64_t big64 = UINT64_MAX - 42;
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdech, 1, kHRegSize, 1);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdech, 2, kHRegSize, 42);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdech, 15, kHRegSize, 999);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdech, 16, kHRegSize, big32);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdech, 1, kHRegSize, 1);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdech, 2, kHRegSize, 42);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdech, 15, kHRegSize, 999);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdech, 16, kHRegSize, big64);
+}
+
+TEST_SVE(sve_uqdecw) {
+  int32_t big32 = UINT32_MAX - 42;
+  int64_t big64 = UINT64_MAX - 42;
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecw, 1, kWRegSize, 1);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecw, 2, kWRegSize, 42);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecw, 15, kWRegSize, 999);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecw, 16, kWRegSize, big32);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecw, 1, kWRegSize, 1);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecw, 2, kWRegSize, 42);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecw, 15, kWRegSize, 999);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecw, 16, kWRegSize, big64);
+}
+
+TEST_SVE(sve_uqdecd) {
+  int32_t big32 = UINT32_MAX - 42;
+  int64_t big64 = UINT64_MAX - 42;
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecd, 1, kDRegSize, 1);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecd, 2, kDRegSize, 42);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecd, 15, kDRegSize, 999);
+  QDecHelper<uint32_t>(config, &MacroAssembler::Uqdecd, 16, kDRegSize, big32);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecd, 1, kDRegSize, 1);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecd, 2, kDRegSize, 42);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecd, 15, kDRegSize, 999);
+  QDecHelper<uint64_t>(config, &MacroAssembler::Uqdecd, 16, kDRegSize, big64);
+}
+
+TEST_SVE(sve_uqincb) {
+  int32_t big32 = UINT32_MAX - 42;
+  int64_t big64 = UINT64_MAX - 42;
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincb, 1, kBRegSize, 1);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincb, 2, kBRegSize, 42);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincb, 15, kBRegSize, 999);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincb, 16, kBRegSize, big32);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincb, 1, kBRegSize, 1);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincb, 2, kBRegSize, 42);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincb, 15, kBRegSize, 999);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincb, 16, kBRegSize, big64);
+}
+
+TEST_SVE(sve_uqinch) {
+  int32_t big32 = UINT32_MAX - 42;
+  int64_t big64 = UINT64_MAX - 42;
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqinch, 1, kHRegSize, 1);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqinch, 2, kHRegSize, 42);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqinch, 15, kHRegSize, 999);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqinch, 16, kHRegSize, big32);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqinch, 1, kHRegSize, 1);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqinch, 2, kHRegSize, 42);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqinch, 15, kHRegSize, 999);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqinch, 16, kHRegSize, big64);
+}
+
+TEST_SVE(sve_uqincw) {
+  int32_t big32 = UINT32_MAX - 42;
+  int64_t big64 = UINT64_MAX - 42;
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincw, 1, kWRegSize, 1);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincw, 2, kWRegSize, 42);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincw, 15, kWRegSize, 999);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincw, 16, kWRegSize, big32);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincw, 1, kWRegSize, 1);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincw, 2, kWRegSize, 42);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincw, 15, kWRegSize, 999);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincw, 16, kWRegSize, big64);
+}
+
+TEST_SVE(sve_uqincd) {
+  int32_t big32 = UINT32_MAX - 42;
+  int64_t big64 = UINT64_MAX - 42;
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincd, 1, kDRegSize, 1);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincd, 2, kDRegSize, 42);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincd, 15, kDRegSize, 999);
+  QIncHelper<uint32_t>(config, &MacroAssembler::Uqincd, 16, kDRegSize, big32);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincd, 1, kDRegSize, 1);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincd, 2, kDRegSize, 42);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincd, 15, kDRegSize, 999);
+  QIncHelper<uint64_t>(config, &MacroAssembler::Uqincd, 16, kDRegSize, big64);
+}
+
+typedef void (MacroAssembler::*QIncDecXWFn)(const Register& dst,
+                                            const Register& src,
+                                            int pattern,
+                                            int multiplier);
+
+static void QIncDecXWHelper(Test* config,
+                            QIncDecXWFn cnt,
+                            int multiplier,
+                            int lane_size_in_bits,
+                            int32_t acc_value,
+                            bool is_increment) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Initialise accumulators.
+  __ Mov(x0, acc_value);
+  __ Mov(x1, acc_value);
+  __ Mov(x2, acc_value);
+  __ Mov(x3, acc_value);
+  __ Mov(x4, acc_value);
+  __ Mov(x5, acc_value);
+  __ Mov(x6, acc_value);
+  __ Mov(x7, acc_value);
+  __ Mov(x8, acc_value);
+  __ Mov(x9, acc_value);
+  __ Mov(x10, acc_value);
+  __ Mov(x11, acc_value);
+  __ Mov(x12, acc_value);
+  __ Mov(x13, acc_value);
+  __ Mov(x14, acc_value);
+  __ Mov(x15, acc_value);
+  __ Mov(x18, acc_value);
+  __ Mov(x19, acc_value);
+  __ Mov(x20, acc_value);
+  __ Mov(x21, acc_value);
+
+  (masm.*cnt)(x0, w0, SVE_POW2, multiplier);
+  (masm.*cnt)(x1, w1, SVE_VL1, multiplier);
+  (masm.*cnt)(x2, w2, SVE_VL2, multiplier);
+  (masm.*cnt)(x3, w3, SVE_VL3, multiplier);
+  (masm.*cnt)(x4, w4, SVE_VL4, multiplier);
+  (masm.*cnt)(x5, w5, SVE_VL5, multiplier);
+  (masm.*cnt)(x6, w6, SVE_VL6, multiplier);
+  (masm.*cnt)(x7, w7, SVE_VL7, multiplier);
+  (masm.*cnt)(x8, w8, SVE_VL8, multiplier);
+  (masm.*cnt)(x9, w9, SVE_VL16, multiplier);
+  (masm.*cnt)(x10, w10, SVE_VL32, multiplier);
+  (masm.*cnt)(x11, w11, SVE_VL64, multiplier);
+  (masm.*cnt)(x12, w12, SVE_VL128, multiplier);
+  (masm.*cnt)(x13, w13, SVE_VL256, multiplier);
+  (masm.*cnt)(x14, w14, 16, multiplier);
+  (masm.*cnt)(x15, w15, 23, multiplier);
+  (masm.*cnt)(x18, w18, 28, multiplier);
+  (masm.*cnt)(x19, w19, SVE_MUL4, multiplier);
+  (masm.*cnt)(x20, w20, SVE_MUL3, multiplier);
+  (masm.*cnt)(x21, w21, SVE_ALL, multiplier);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int all = core.GetSVELaneCount(lane_size_in_bits);
+    int pow2 = 1 << HighestSetBitPosition(all);
+    int mul4 = all - (all % 4);
+    int mul3 = all - (all % 3);
+
+    multiplier = is_increment ? multiplier : -multiplier;
+
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * pow2), x0);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(1, all)), x1);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(2, all)), x2);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(3, all)), x3);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(4, all)), x4);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(5, all)), x5);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(6, all)), x6);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(7, all)), x7);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(8, all)), x8);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(16, all)), x9);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(32, all)), x10);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(64, all)), x11);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(128, all)), x12);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * FixedVL(256, all)), x13);
+    ASSERT_EQUAL_64(acc_value, x14);
+    ASSERT_EQUAL_64(acc_value, x15);
+    ASSERT_EQUAL_64(acc_value, x18);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * mul4), x19);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * mul3), x20);
+    ASSERT_EQUAL_64(QAdd(acc_value, multiplier * all), x21);
+  }
+}
+
+static void QIncXWHelper(Test* config,
+                         QIncDecXWFn cnt,
+                         int multiplier,
+                         int lane_size_in_bits,
+                         int32_t acc_value) {
+  QIncDecXWHelper(config, cnt, multiplier, lane_size_in_bits, acc_value, true);
+}
+
+static void QDecXWHelper(Test* config,
+                         QIncDecXWFn cnt,
+                         int multiplier,
+                         int lane_size_in_bits,
+                         int32_t acc_value) {
+  QIncDecXWHelper(config, cnt, multiplier, lane_size_in_bits, acc_value, false);
+}
+
+TEST_SVE(sve_sqdecb_xw) {
+  QDecXWHelper(config, &MacroAssembler::Sqdecb, 1, kBRegSize, 1);
+  QDecXWHelper(config, &MacroAssembler::Sqdecb, 2, kBRegSize, INT32_MIN + 42);
+  QDecXWHelper(config, &MacroAssembler::Sqdecb, 15, kBRegSize, 999);
+  QDecXWHelper(config, &MacroAssembler::Sqdecb, 16, kBRegSize, INT32_MAX - 42);
+}
+
+TEST_SVE(sve_sqdech_xw) {
+  QDecXWHelper(config, &MacroAssembler::Sqdech, 1, kHRegSize, 1);
+  QDecXWHelper(config, &MacroAssembler::Sqdech, 2, kHRegSize, INT32_MIN + 42);
+  QDecXWHelper(config, &MacroAssembler::Sqdech, 15, kHRegSize, 999);
+  QDecXWHelper(config, &MacroAssembler::Sqdech, 16, kHRegSize, INT32_MAX - 42);
+}
+
+TEST_SVE(sve_sqdecw_xw) {
+  QDecXWHelper(config, &MacroAssembler::Sqdecw, 1, kWRegSize, 1);
+  QDecXWHelper(config, &MacroAssembler::Sqdecw, 2, kWRegSize, INT32_MIN + 42);
+  QDecXWHelper(config, &MacroAssembler::Sqdecw, 15, kWRegSize, 999);
+  QDecXWHelper(config, &MacroAssembler::Sqdecw, 16, kWRegSize, INT32_MAX - 42);
+}
+
+TEST_SVE(sve_sqdecd_xw) {
+  QDecXWHelper(config, &MacroAssembler::Sqdecd, 1, kDRegSize, 1);
+  QDecXWHelper(config, &MacroAssembler::Sqdecd, 2, kDRegSize, INT32_MIN + 42);
+  QDecXWHelper(config, &MacroAssembler::Sqdecd, 15, kDRegSize, 999);
+  QDecXWHelper(config, &MacroAssembler::Sqdecd, 16, kDRegSize, INT32_MAX - 42);
+}
+
+TEST_SVE(sve_sqincb_xw) {
+  QIncXWHelper(config, &MacroAssembler::Sqincb, 1, kBRegSize, 1);
+  QIncXWHelper(config, &MacroAssembler::Sqincb, 2, kBRegSize, INT32_MIN + 42);
+  QIncXWHelper(config, &MacroAssembler::Sqincb, 15, kBRegSize, 999);
+  QIncXWHelper(config, &MacroAssembler::Sqincb, 16, kBRegSize, INT32_MAX - 42);
+}
+
+TEST_SVE(sve_sqinch_xw) {
+  QIncXWHelper(config, &MacroAssembler::Sqinch, 1, kHRegSize, 1);
+  QIncXWHelper(config, &MacroAssembler::Sqinch, 2, kHRegSize, INT32_MIN + 42);
+  QIncXWHelper(config, &MacroAssembler::Sqinch, 15, kHRegSize, 999);
+  QIncXWHelper(config, &MacroAssembler::Sqinch, 16, kHRegSize, INT32_MAX - 42);
+}
+
+TEST_SVE(sve_sqincw_xw) {
+  QIncXWHelper(config, &MacroAssembler::Sqincw, 1, kWRegSize, 1);
+  QIncXWHelper(config, &MacroAssembler::Sqincw, 2, kWRegSize, INT32_MIN + 42);
+  QIncXWHelper(config, &MacroAssembler::Sqincw, 15, kWRegSize, 999);
+  QIncXWHelper(config, &MacroAssembler::Sqincw, 16, kWRegSize, INT32_MAX - 42);
+}
+
+TEST_SVE(sve_sqincd_xw) {
+  QIncXWHelper(config, &MacroAssembler::Sqincd, 1, kDRegSize, 1);
+  QIncXWHelper(config, &MacroAssembler::Sqincd, 2, kDRegSize, INT32_MIN + 42);
+  QIncXWHelper(config, &MacroAssembler::Sqincd, 15, kDRegSize, 999);
+  QIncXWHelper(config, &MacroAssembler::Sqincd, 16, kDRegSize, INT32_MAX - 42);
+}
+
+typedef void (MacroAssembler::*IncDecZFn)(const ZRegister& dst,
+                                          int pattern,
+                                          int multiplier);
+typedef void (MacroAssembler::*AddSubFn)(const ZRegister& dst,
+                                         const ZRegister& src1,
+                                         const ZRegister& src2);
+
+static void IncDecZHelper(Test* config,
+                          IncDecZFn fn,
+                          CntFn cnt,
+                          AddSubFn addsub,
+                          int multiplier,
+                          int lane_size_in_bits) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t acc_inputs[] = {0x7766554433221100,
+                           0xffffffffffffffff,
+                           0x0000000000000000,
+                           0xffffffff0000ffff,
+                           0x7fffffffffffffff,
+                           0x8000000000000000,
+                           0x7fffffff7fff7fff,
+                           0x8000000080008000};
+
+  for (unsigned i = 0; i < kNumberOfZRegisters; i++) {
+    for (int j = 0; j < 4; j++) {
+      InsrHelper(&masm, ZRegister(i, kDRegSize), acc_inputs);
+    }
+  }
+  for (unsigned i = 0; i < 15; i++) {
+    __ Mov(XRegister(i), 0);
+  }
+
+  (masm.*fn)(z16.WithLaneSize(lane_size_in_bits), SVE_POW2, multiplier);
+  (masm.*fn)(z17.WithLaneSize(lane_size_in_bits), SVE_VL1, multiplier);
+  (masm.*fn)(z18.WithLaneSize(lane_size_in_bits), SVE_VL2, multiplier);
+  (masm.*fn)(z19.WithLaneSize(lane_size_in_bits), SVE_VL3, multiplier);
+  (masm.*fn)(z20.WithLaneSize(lane_size_in_bits), SVE_VL4, multiplier);
+  (masm.*fn)(z21.WithLaneSize(lane_size_in_bits), SVE_VL7, multiplier);
+  (masm.*fn)(z22.WithLaneSize(lane_size_in_bits), SVE_VL8, multiplier);
+  (masm.*fn)(z23.WithLaneSize(lane_size_in_bits), SVE_VL16, multiplier);
+  (masm.*fn)(z24.WithLaneSize(lane_size_in_bits), SVE_VL64, multiplier);
+  (masm.*fn)(z25.WithLaneSize(lane_size_in_bits), SVE_VL256, multiplier);
+  (masm.*fn)(z26.WithLaneSize(lane_size_in_bits), 16, multiplier);
+  (masm.*fn)(z27.WithLaneSize(lane_size_in_bits), 28, multiplier);
+  (masm.*fn)(z28.WithLaneSize(lane_size_in_bits), SVE_MUL3, multiplier);
+  (masm.*fn)(z29.WithLaneSize(lane_size_in_bits), SVE_MUL4, multiplier);
+  (masm.*fn)(z30.WithLaneSize(lane_size_in_bits), SVE_ALL, multiplier);
+
+  // Perform computation using alternative instructions.
+  (masm.*cnt)(x0, SVE_POW2, multiplier);
+  (masm.*cnt)(x1, SVE_VL1, multiplier);
+  (masm.*cnt)(x2, SVE_VL2, multiplier);
+  (masm.*cnt)(x3, SVE_VL3, multiplier);
+  (masm.*cnt)(x4, SVE_VL4, multiplier);
+  (masm.*cnt)(x5, SVE_VL7, multiplier);
+  (masm.*cnt)(x6, SVE_VL8, multiplier);
+  (masm.*cnt)(x7, SVE_VL16, multiplier);
+  (masm.*cnt)(x8, SVE_VL64, multiplier);
+  (masm.*cnt)(x9, SVE_VL256, multiplier);
+  (masm.*cnt)(x10, 16, multiplier);
+  (masm.*cnt)(x11, 28, multiplier);
+  (masm.*cnt)(x12, SVE_MUL3, multiplier);
+  (masm.*cnt)(x13, SVE_MUL4, multiplier);
+  (masm.*cnt)(x14, SVE_ALL, multiplier);
+
+  ZRegister zscratch = z15.WithLaneSize(lane_size_in_bits);
+  for (unsigned i = 0; i < 15; i++) {
+    ZRegister zsrcdst = ZRegister(i, lane_size_in_bits);
+    Register x = Register(i, kXRegSize);
+    __ Dup(zscratch, x);
+    (masm.*addsub)(zsrcdst, zsrcdst, zscratch);
+  }
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(z0, z16);
+    ASSERT_EQUAL_SVE(z1, z17);
+    ASSERT_EQUAL_SVE(z2, z18);
+    ASSERT_EQUAL_SVE(z3, z19);
+    ASSERT_EQUAL_SVE(z4, z20);
+    ASSERT_EQUAL_SVE(z5, z21);
+    ASSERT_EQUAL_SVE(z6, z22);
+    ASSERT_EQUAL_SVE(z7, z23);
+    ASSERT_EQUAL_SVE(z8, z24);
+    ASSERT_EQUAL_SVE(z9, z25);
+    ASSERT_EQUAL_SVE(z10, z26);
+    ASSERT_EQUAL_SVE(z11, z27);
+    ASSERT_EQUAL_SVE(z12, z28);
+    ASSERT_EQUAL_SVE(z13, z29);
+    ASSERT_EQUAL_SVE(z14, z30);
+  }
+}
+
+TEST_SVE(sve_inc_dec_vec) {
+  CntFn cnth = &MacroAssembler::Cnth;
+  CntFn cntw = &MacroAssembler::Cntw;
+  CntFn cntd = &MacroAssembler::Cntd;
+  AddSubFn sub = &MacroAssembler::Sub;
+  AddSubFn add = &MacroAssembler::Add;
+  for (int mult = 1; mult <= 16; mult += 5) {
+    IncDecZHelper(config, &MacroAssembler::Dech, cnth, sub, mult, kHRegSize);
+    IncDecZHelper(config, &MacroAssembler::Decw, cntw, sub, mult, kSRegSize);
+    IncDecZHelper(config, &MacroAssembler::Decd, cntd, sub, mult, kDRegSize);
+    IncDecZHelper(config, &MacroAssembler::Inch, cnth, add, mult, kHRegSize);
+    IncDecZHelper(config, &MacroAssembler::Incw, cntw, add, mult, kSRegSize);
+    IncDecZHelper(config, &MacroAssembler::Incd, cntd, add, mult, kDRegSize);
+  }
+}
+
+TEST_SVE(sve_unsigned_sat_inc_dec_vec) {
+  CntFn cnth = &MacroAssembler::Cnth;
+  CntFn cntw = &MacroAssembler::Cntw;
+  CntFn cntd = &MacroAssembler::Cntd;
+  AddSubFn sub = &MacroAssembler::Uqsub;
+  AddSubFn add = &MacroAssembler::Uqadd;
+  for (int mult = 1; mult <= 16; mult += 5) {
+    IncDecZHelper(config, &MacroAssembler::Uqdech, cnth, sub, mult, kHRegSize);
+    IncDecZHelper(config, &MacroAssembler::Uqdecw, cntw, sub, mult, kSRegSize);
+    IncDecZHelper(config, &MacroAssembler::Uqdecd, cntd, sub, mult, kDRegSize);
+    IncDecZHelper(config, &MacroAssembler::Uqinch, cnth, add, mult, kHRegSize);
+    IncDecZHelper(config, &MacroAssembler::Uqincw, cntw, add, mult, kSRegSize);
+    IncDecZHelper(config, &MacroAssembler::Uqincd, cntd, add, mult, kDRegSize);
+  }
+}
+
+TEST_SVE(sve_signed_sat_inc_dec_vec) {
+  CntFn cnth = &MacroAssembler::Cnth;
+  CntFn cntw = &MacroAssembler::Cntw;
+  CntFn cntd = &MacroAssembler::Cntd;
+  AddSubFn sub = &MacroAssembler::Sqsub;
+  AddSubFn add = &MacroAssembler::Sqadd;
+  for (int mult = 1; mult <= 16; mult += 5) {
+    IncDecZHelper(config, &MacroAssembler::Sqdech, cnth, sub, mult, kHRegSize);
+    IncDecZHelper(config, &MacroAssembler::Sqdecw, cntw, sub, mult, kSRegSize);
+    IncDecZHelper(config, &MacroAssembler::Sqdecd, cntd, sub, mult, kDRegSize);
+    IncDecZHelper(config, &MacroAssembler::Sqinch, cnth, add, mult, kHRegSize);
+    IncDecZHelper(config, &MacroAssembler::Sqincw, cntw, add, mult, kSRegSize);
+    IncDecZHelper(config, &MacroAssembler::Sqincd, cntd, add, mult, kDRegSize);
+  }
+}
+
+typedef void (MacroAssembler::*ArithPredicatedFn)(const ZRegister& zd,
+                                                  const PRegisterM& pg,
+                                                  const ZRegister& zn,
+                                                  const ZRegister& zm);
+
+template <typename Td, typename Tg, typename Tn>
+static void IntBinArithHelper(Test* config,
+                              ArithPredicatedFn macro,
+                              unsigned lane_size_in_bits,
+                              const Tg& pg_inputs,
+                              const Tn& zn_inputs,
+                              const Tn& zm_inputs,
+                              const Td& zd_expected) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  ZRegister src_a = z31.WithLaneSize(lane_size_in_bits);
+  ZRegister src_b = z27.WithLaneSize(lane_size_in_bits);
+  InsrHelper(&masm, src_a, zn_inputs);
+  InsrHelper(&masm, src_b, zm_inputs);
+
+  Initialise(&masm, p0.WithLaneSize(lane_size_in_bits), pg_inputs);
+
+  ZRegister zd_1 = z0.WithLaneSize(lane_size_in_bits);
+  ZRegister zd_2 = z1.WithLaneSize(lane_size_in_bits);
+  ZRegister zd_3 = z2.WithLaneSize(lane_size_in_bits);
+
+  // `instr` zd(dst), zd(src_a), zn(src_b)
+  __ Mov(zd_1, src_a);
+  (masm.*macro)(zd_1, p0.Merging(), zd_1, src_b);
+
+  // `instr` zd(dst), zm(src_a), zd(src_b)
+  // Based on whether zd and zm registers are aliased, the macro of instructions
+  // (`Instr`) swaps the order of operands if it has the commutative property,
+  // otherwise, transfer to the reversed `Instr`, such as subr and divr.
+  __ Mov(zd_2, src_b);
+  (masm.*macro)(zd_2, p0.Merging(), src_a, zd_2);
+
+  // `instr` zd(dst), zm(src_a), zn(src_b)
+  // The macro of instructions (`Instr`) automatically selects between `instr`
+  // and movprfx + `instr` based on whether zd and zn registers are aliased.
+  // A generated movprfx instruction is predicated that using the same
+  // governing predicate register. In order to keep the result constant,
+  // initialize the destination register first.
+  __ Mov(zd_3, src_a);
+  (masm.*macro)(zd_3, p0.Merging(), src_a, src_b);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(zd_expected, zd_1);
+
+    for (size_t i = 0; i < ArrayLength(zd_expected); i++) {
+      int lane = static_cast<int>(ArrayLength(zd_expected) - i - 1);
+      if (!core.HasSVELane(zd_1, lane)) break;
+      if ((pg_inputs[i] & 1) != 0) {
+        ASSERT_EQUAL_SVE_LANE(zd_expected[i], zd_1, lane);
+      } else {
+        ASSERT_EQUAL_SVE_LANE(zn_inputs[i], zd_1, lane);
+      }
+    }
+
+    ASSERT_EQUAL_SVE(zd_expected, zd_3);
+  }
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_add) {
+  // clang-format off
+  unsigned zn_b[] = {0x00, 0x01, 0x10, 0x81, 0xff, 0x0f, 0x01, 0x7f};
+
+  unsigned zm_b[] = {0x00, 0x01, 0x10, 0x00, 0x81, 0x80, 0xff, 0xff};
+
+  unsigned zn_h[] = {0x0000, 0x0123, 0x1010, 0x8181, 0xffff, 0x0f0f, 0x0101, 0x7f7f};
+
+  unsigned zm_h[] = {0x0000, 0x0123, 0x1010, 0x0000, 0x8181, 0x8080, 0xffff, 0xffff};
+
+  unsigned zn_s[] = {0x00000000, 0x01234567, 0x10101010, 0x81818181,
+                     0xffffffff, 0x0f0f0f0f, 0x01010101, 0x7f7f7f7f};
+
+  unsigned zm_s[] = {0x00000000, 0x01234567, 0x10101010, 0x00000000,
+                     0x81818181, 0x80808080, 0xffffffff, 0xffffffff};
+
+  uint64_t zn_d[] = {0x0000000000000000, 0x0123456789abcdef,
+                     0x1010101010101010, 0x8181818181818181,
+                     0xffffffffffffffff, 0x0f0f0f0f0f0f0f0f,
+                     0x0101010101010101, 0x7f7f7f7fffffffff};
+
+  uint64_t zm_d[] = {0x0000000000000000, 0x0123456789abcdef,
+                     0x1010101010101010, 0x0000000000000000,
+                     0x8181818181818181, 0x8080808080808080,
+                     0xffffffffffffffff, 0xffffffffffffffff};
+
+  int pg_b[] = {1, 1, 1, 0, 1, 1, 1, 0};
+  int pg_h[] = {1, 1, 0, 1, 1, 1, 0, 1};
+  int pg_s[] = {1, 0, 1, 1, 1, 0, 1, 1};
+  int pg_d[] = {0, 1, 1, 1, 0, 1, 1, 1};
+
+  unsigned add_exp_b[] = {0x00, 0x02, 0x20, 0x81, 0x80, 0x8f, 0x00, 0x7f};
+
+  unsigned add_exp_h[] = {0x0000, 0x0246, 0x1010, 0x8181,
+                          0x8180, 0x8f8f, 0x0101, 0x7f7e};
+
+  unsigned add_exp_s[] = {0x00000000, 0x01234567, 0x20202020, 0x81818181,
+                          0x81818180, 0x0f0f0f0f, 0x01010100, 0x7f7f7f7e};
+
+  uint64_t add_exp_d[] = {0x0000000000000000, 0x02468acf13579bde,
+                          0x2020202020202020, 0x8181818181818181,
+                          0xffffffffffffffff, 0x8f8f8f8f8f8f8f8f,
+                          0x0101010101010100, 0x7f7f7f7ffffffffe};
+
+  ArithPredicatedFn fn = &MacroAssembler::Add;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, add_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, add_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, add_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, add_exp_d);
+
+  unsigned sub_exp_b[] = {0x00, 0x00, 0x00, 0x81, 0x7e, 0x8f, 0x02, 0x7f};
+
+  unsigned sub_exp_h[] = {0x0000, 0x0000, 0x1010, 0x8181,
+                          0x7e7e, 0x8e8f, 0x0101, 0x7f80};
+
+  unsigned sub_exp_s[] = {0x00000000, 0x01234567, 0x00000000, 0x81818181,
+                          0x7e7e7e7e, 0x0f0f0f0f, 0x01010102, 0x7f7f7f80};
+
+  uint64_t sub_exp_d[] = {0x0000000000000000, 0x0000000000000000,
+                          0x0000000000000000, 0x8181818181818181,
+                          0xffffffffffffffff, 0x8e8e8e8e8e8e8e8f,
+                          0x0101010101010102, 0x7f7f7f8000000000};
+
+  fn = &MacroAssembler::Sub;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, sub_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, sub_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, sub_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, sub_exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_umin_umax_uabd) {
+  // clang-format off
+  unsigned zn_b[] = {0x00, 0xff, 0x0f, 0xff, 0xf0, 0x98, 0x55, 0x67};
+
+  unsigned zm_b[] = {0x01, 0x00, 0x0e, 0xfe, 0xfe, 0xab, 0xcd, 0x78};
+
+  unsigned zn_h[] = {0x0000, 0xffff, 0x00ff, 0xffff,
+                     0xff00, 0xba98, 0x5555, 0x4567};
+
+  unsigned zm_h[] = {0x0001, 0x0000, 0x00ee, 0xfffe,
+                     0xfe00, 0xabab, 0xcdcd, 0x5678};
+
+  unsigned zn_s[] = {0x00000000, 0xffffffff, 0x0000ffff, 0xffffffff,
+                     0xffff0000, 0xfedcba98, 0x55555555, 0x01234567};
+
+  unsigned zm_s[] = {0x00000001, 0x00000000, 0x0000eeee, 0xfffffffe,
+                     0xfffe0000, 0xabababab, 0xcdcdcdcd, 0x12345678};
+
+  uint64_t zn_d[] = {0x0000000000000000, 0xffffffffffffffff,
+                     0x5555555555555555, 0x0000000001234567};
+
+  uint64_t zm_d[] = {0x0000000000000001, 0x0000000000000000,
+                     0xcdcdcdcdcdcdcdcd, 0x0000000012345678};
+
+  int pg_b[] = {1, 1, 1, 0, 1, 1, 1, 0};
+  int pg_h[] = {1, 1, 0, 1, 1, 1, 0, 1};
+  int pg_s[] = {1, 0, 1, 1, 1, 0, 1, 1};
+  int pg_d[] = {1, 0, 1, 1};
+
+  unsigned umax_exp_b[] = {0x01, 0xff, 0x0f, 0xff, 0xfe, 0xab, 0xcd, 0x67};
+
+  unsigned umax_exp_h[] = {0x0001, 0xffff, 0x00ff, 0xffff,
+                           0xff00, 0xba98, 0x5555, 0x5678};
+
+  unsigned umax_exp_s[] = {0x00000001, 0xffffffff, 0x0000ffff, 0xffffffff,
+                           0xffff0000, 0xfedcba98, 0xcdcdcdcd, 0x12345678};
+
+  uint64_t umax_exp_d[] = {0x0000000000000001, 0xffffffffffffffff,
+                           0xcdcdcdcdcdcdcdcd, 0x0000000012345678};
+
+  ArithPredicatedFn fn = &MacroAssembler::Umax;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, umax_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, umax_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, umax_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, umax_exp_d);
+
+  unsigned umin_exp_b[] = {0x00, 0x00, 0x0e, 0xff, 0xf0, 0x98, 0x55, 0x67};
+
+  unsigned umin_exp_h[] = {0x0000, 0x0000, 0x00ff, 0xfffe,
+                           0xfe00, 0xabab, 0x5555, 0x4567};
+
+  unsigned umin_exp_s[] = {0x00000000, 0xffffffff, 0x0000eeee, 0xfffffffe,
+                           0xfffe0000, 0xfedcba98, 0x55555555, 0x01234567};
+
+  uint64_t umin_exp_d[] = {0x0000000000000000, 0xffffffffffffffff,
+                           0x5555555555555555, 0x0000000001234567};
+  fn = &MacroAssembler::Umin;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, umin_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, umin_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, umin_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, umin_exp_d);
+
+  unsigned uabd_exp_b[] = {0x01, 0xff, 0x01, 0xff, 0x0e, 0x13, 0x78, 0x67};
+
+  unsigned uabd_exp_h[] = {0x0001, 0xffff, 0x00ff, 0x0001,
+                           0x0100, 0x0eed, 0x5555, 0x1111};
+
+  unsigned uabd_exp_s[] = {0x00000001, 0xffffffff, 0x00001111, 0x00000001,
+                           0x00010000, 0xfedcba98, 0x78787878, 0x11111111};
+
+  uint64_t uabd_exp_d[] = {0x0000000000000001, 0xffffffffffffffff,
+                           0x7878787878787878, 0x0000000011111111};
+
+  fn = &MacroAssembler::Uabd;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, uabd_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, uabd_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, uabd_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, uabd_exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_smin_smax_sabd) {
+  // clang-format off
+  int zn_b[] = {0, -128, -128, -128, -128, 127, 127, 1};
+
+  int zm_b[] = {-1, 0, -1, -127, 127, 126, -1, 0};
+
+  int zn_h[] = {0, INT16_MIN, INT16_MIN, INT16_MIN,
+                INT16_MIN, INT16_MAX, INT16_MAX, 1};
+
+  int zm_h[] = {-1, 0, -1, INT16_MIN + 1,
+                INT16_MAX, INT16_MAX - 1, -1, 0};
+
+  int zn_s[] = {0, INT32_MIN, INT32_MIN, INT32_MIN,
+                INT32_MIN, INT32_MAX, INT32_MAX, 1};
+
+  int zm_s[] = {-1, 0, -1, -INT32_MAX,
+                INT32_MAX, INT32_MAX - 1, -1, 0};
+
+  int64_t zn_d[] = {0, INT64_MIN, INT64_MIN, INT64_MIN,
+                    INT64_MIN, INT64_MAX, INT64_MAX, 1};
+
+  int64_t zm_d[] = {-1, 0, -1, INT64_MIN + 1,
+                    INT64_MAX, INT64_MAX - 1, -1, 0};
+
+  int pg_b[] = {1, 1, 1, 0, 1, 1, 1, 0};
+  int pg_h[] = {1, 1, 0, 1, 1, 1, 0, 1};
+  int pg_s[] = {1, 0, 1, 1, 1, 0, 1, 1};
+  int pg_d[] = {0, 1, 1, 1, 0, 1, 1, 1};
+
+  int smax_exp_b[] = {0, 0, -1, -128, 127, 127, 127, 1};
+
+  int smax_exp_h[] = {0, 0, INT16_MIN, INT16_MIN + 1,
+                      INT16_MAX, INT16_MAX, INT16_MAX, 1};
+
+  int smax_exp_s[] = {0, INT32_MIN, -1, INT32_MIN + 1,
+                      INT32_MAX, INT32_MAX, INT32_MAX, 1};
+
+  int64_t smax_exp_d[] = {0, 0, -1, INT64_MIN + 1,
+                          INT64_MIN, INT64_MAX, INT64_MAX, 1};
+
+  ArithPredicatedFn fn = &MacroAssembler::Smax;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, smax_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, smax_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, smax_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, smax_exp_d);
+
+  int smin_exp_b[] = {-1, -128, -128, -128, -128, 126, -1, 1};
+
+  int smin_exp_h[] = {-1, INT16_MIN, INT16_MIN, INT16_MIN,
+                      INT16_MIN, INT16_MAX - 1, INT16_MAX, 0};
+
+  int smin_exp_s[] = {-1, INT32_MIN, INT32_MIN, INT32_MIN,
+                      INT32_MIN, INT32_MAX, -1, 0};
+
+  int64_t smin_exp_d[] = {0, INT64_MIN, INT64_MIN, INT64_MIN,
+                          INT64_MIN, INT64_MAX - 1, -1, 0};
+
+  fn = &MacroAssembler::Smin;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, smin_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, smin_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, smin_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, smin_exp_d);
+
+  unsigned sabd_exp_b[] = {1, 128, 127, 128, 255, 1, 128, 1};
+
+  unsigned sabd_exp_h[] = {1, 0x8000, 0x8000, 1, 0xffff, 1, 0x7fff, 1};
+
+  unsigned sabd_exp_s[] = {1, 0x80000000, 0x7fffffff, 1,
+                           0xffffffff, 0x7fffffff, 0x80000000, 1};
+
+  uint64_t sabd_exp_d[] = {0, 0x8000000000000000, 0x7fffffffffffffff, 1,
+                           0x8000000000000000, 1, 0x8000000000000000, 1};
+
+  fn = &MacroAssembler::Sabd;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, sabd_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, sabd_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, sabd_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, sabd_exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_mul_umulh) {
+  // clang-format off
+  unsigned zn_b[] = {0x00, 0x01, 0x20, 0x08, 0x80, 0xff, 0x55, 0xaa};
+
+  unsigned zm_b[] = {0x7f, 0xcd, 0x80, 0xff, 0x55, 0xaa, 0x00, 0x08};
+
+  unsigned zn_h[] = {0x0000, 0x0001, 0x0020, 0x0800,
+                     0x8000, 0xff00, 0x5555, 0xaaaa};
+
+  unsigned zm_h[] = {0x007f, 0x00cd, 0x0800, 0xffff,
+                     0x5555, 0xaaaa, 0x0001, 0x1234};
+
+  unsigned zn_s[] = {0x00000000, 0x00000001, 0x00200020, 0x08000800,
+                     0x12345678, 0xffffffff, 0x55555555, 0xaaaaaaaa};
+
+  unsigned zm_s[] = {0x00000000, 0x00000001, 0x00200020, 0x08000800,
+                     0x12345678, 0x22223333, 0x55556666, 0x77778888};
+
+  uint64_t zn_d[] = {0x0000000000000000, 0x5555555555555555,
+                     0xffffffffffffffff, 0xaaaaaaaaaaaaaaaa};
+
+  uint64_t zm_d[] = {0x0000000000000000, 0x1111111133333333,
+                     0xddddddddeeeeeeee, 0xaaaaaaaaaaaaaaaa};
+
+  int pg_b[] = {0, 1, 1, 1, 0, 1, 1, 1};
+  int pg_h[] = {1, 0, 1, 1, 1, 0, 1, 1};
+  int pg_s[] = {1, 1, 0, 1, 1, 1, 0, 1};
+  int pg_d[] = {1, 1, 0, 1};
+
+  unsigned mul_exp_b[] = {0x00, 0xcd, 0x00, 0xf8, 0x80, 0x56, 0x00, 0x50};
+
+  unsigned mul_exp_h[] = {0x0000, 0x0001, 0x0000, 0xf800,
+                          0x8000, 0xff00, 0x5555, 0x9e88};
+
+  unsigned mul_exp_s[] = {0x00000000, 0x00000001, 0x00200020, 0x00400000,
+                          0x1df4d840, 0xddddcccd, 0x55555555, 0xb05afa50};
+
+  uint64_t mul_exp_d[] = {0x0000000000000000, 0xa4fa4fa4eeeeeeef,
+                          0xffffffffffffffff, 0x38e38e38e38e38e4};
+
+  ArithPredicatedFn fn = &MacroAssembler::Mul;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, mul_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, mul_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, mul_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, mul_exp_d);
+
+  unsigned umulh_exp_b[] = {0x00, 0x00, 0x10, 0x07, 0x80, 0xa9, 0x00, 0x05};
+
+  unsigned umulh_exp_h[] = {0x0000, 0x0001, 0x0001, 0x07ff,
+                            0x2aaa, 0xff00, 0x0000, 0x0c22};
+
+  unsigned umulh_exp_s[] = {0x00000000, 0x00000000, 0x00200020, 0x00400080,
+                            0x014b66dc, 0x22223332, 0x55555555, 0x4fa505af};
+
+  uint64_t umulh_exp_d[] = {0x0000000000000000, 0x05b05b05bbbbbbbb,
+                            0xffffffffffffffff, 0x71c71c71c71c71c6};
+
+  fn = &MacroAssembler::Umulh;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, umulh_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, umulh_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, umulh_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, umulh_exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_smulh) {
+  // clang-format off
+  int zn_b[] = {0, 1, -1, INT8_MIN, INT8_MAX, -1, 100, -3};
+
+  int zm_b[] = {0, INT8_MIN, INT8_MIN, INT8_MAX, INT8_MAX, -1, 2, 66};
+
+  int zn_h[] = {0, 1, -1, INT16_MIN, INT16_MAX, -1, 10000, -3};
+
+  int zm_h[] = {0, INT16_MIN, INT16_MIN, INT16_MAX, INT16_MAX, -1, 2, 6666};
+
+  int zn_s[] = {0, 1, -1, INT32_MIN, INT32_MAX, -1, 100000000, -3};
+
+  int zm_s[] = {0, INT32_MIN, INT32_MIN, INT32_MAX, INT32_MAX, -1, 2, 66666666};
+
+  int64_t zn_d[] = {0, -1, INT64_MIN, INT64_MAX};
+
+  int64_t zm_d[] = {INT64_MIN, INT64_MAX, INT64_MIN, INT64_MAX};
+
+  int pg_b[] = {0, 1, 1, 1, 0, 1, 1, 1};
+  int pg_h[] = {1, 0, 1, 1, 1, 0, 1, 1};
+  int pg_s[] = {1, 1, 0, 1, 1, 1, 0, 1};
+  int pg_d[] = {1, 1, 0, 1};
+
+  int exp_b[] = {0, -1, 0, -64, INT8_MAX, 0, 0, -1};
+
+  int exp_h[] = {0, 1, 0, -16384, 16383, -1, 0, -1};
+
+  int exp_s[] = {0, -1, -1, -1073741824, 1073741823, 0, 100000000, -1};
+
+  int64_t exp_d[] = {0, -1, INT64_MIN, 4611686018427387903};
+
+  ArithPredicatedFn fn = &MacroAssembler::Smulh;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_logical) {
+  // clang-format off
+  unsigned zn_b[] = {0x00, 0x01, 0x20, 0x08, 0x80, 0xff, 0x55, 0xaa};
+  unsigned zm_b[] = {0x7f, 0xcd, 0x80, 0xff, 0x55, 0xaa, 0x00, 0x08};
+
+  unsigned zn_h[] = {0x0000, 0x0001, 0x2020, 0x0008,
+                     0x8000, 0xffff, 0x5555, 0xaaaa};
+  unsigned zm_h[] = {0x7fff, 0xabcd, 0x8000, 0xffff,
+                     0x5555, 0xaaaa, 0x0000, 0x0800};
+
+  unsigned zn_s[] = {0x00000001, 0x20200008, 0x8000ffff, 0x5555aaaa};
+  unsigned zm_s[] = {0x7fffabcd, 0x8000ffff, 0x5555aaaa, 0x00000800};
+
+  uint64_t zn_d[] = {0xfedcba9876543210, 0x0123456789abcdef,
+                     0x0001200880ff55aa, 0x0022446688aaccee};
+  uint64_t zm_d[] = {0xffffeeeeddddcccc, 0xccccddddeeeeffff,
+                     0x7fcd80ff55aa0008, 0x1133557799bbddff};
+
+  int pg_b[] = {0, 1, 1, 1, 0, 1, 1, 1};
+  int pg_h[] = {1, 0, 1, 1, 1, 0, 1, 1};
+  int pg_s[] = {1, 1, 1, 0};
+  int pg_d[] = {1, 1, 0, 1};
+
+  unsigned and_exp_b[] = {0x00, 0x01, 0x00, 0x08, 0x80, 0xaa, 0x00, 0x08};
+
+  unsigned and_exp_h[] = {0x0000, 0x0001, 0x0000, 0x0008,
+                          0x0000, 0xffff, 0x0000, 0x0800};
+
+  unsigned and_exp_s[] = {0x00000001, 0x00000008, 0x0000aaaa, 0x5555aaaa};
+
+  uint64_t and_exp_d[] = {0xfedcaa8854540000, 0x0000454588aacdef,
+                          0x0001200880ff55aa, 0x0022446688aaccee};
+
+  ArithPredicatedFn fn = &MacroAssembler::And;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, and_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, and_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, and_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, and_exp_d);
+
+  unsigned bic_exp_b[] = {0x00, 0x00, 0x20, 0x00, 0x80, 0x55, 0x55, 0xa2};
+
+  unsigned bic_exp_h[] = {0x0000, 0x0001, 0x2020, 0x0000,
+                          0x8000, 0xffff, 0x5555, 0xa2aa};
+
+  unsigned bic_exp_s[] = {0x00000000, 0x20200000, 0x80005555, 0x5555aaaa};
+
+  uint64_t bic_exp_d[] = {0x0000101022003210, 0x0123002201010000,
+                          0x0001200880ff55aa, 0x0000000000000000};
+
+  fn = &MacroAssembler::Bic;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, bic_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, bic_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, bic_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, bic_exp_d);
+
+  unsigned eor_exp_b[] = {0x00, 0xcc, 0xa0, 0xf7, 0x80, 0x55, 0x55, 0xa2};
+
+  unsigned eor_exp_h[] = {0x7fff, 0x0001, 0xa020, 0xfff7,
+                          0xd555, 0xffff, 0x5555, 0xa2aa};
+
+  unsigned eor_exp_s[] = {0x7fffabcc, 0xa020fff7, 0xd5555555, 0x5555aaaa};
+
+  uint64_t eor_exp_d[] = {0x01235476ab89fedc, 0xcdef98ba67453210,
+                          0x0001200880ff55aa, 0x1111111111111111};
+
+  fn = &MacroAssembler::Eor;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, eor_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, eor_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, eor_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, eor_exp_d);
+
+  unsigned orr_exp_b[] = {0x00, 0xcd, 0xa0, 0xff, 0x80, 0xff, 0x55, 0xaa};
+
+  unsigned orr_exp_h[] = {0x7fff, 0x0001, 0xa020, 0xffff,
+                          0xd555, 0xffff, 0x5555, 0xaaaa};
+
+  unsigned orr_exp_s[] = {0x7fffabcd, 0xa020ffff, 0xd555ffff, 0x5555aaaa};
+
+  uint64_t orr_exp_d[] = {0xfffffefeffddfedc, 0xcdefddffefefffff,
+                          0x0001200880ff55aa, 0x1133557799bbddff};
+
+  fn = &MacroAssembler::Orr;
+  IntBinArithHelper(config, fn, kBRegSize, pg_b, zn_b, zm_b, orr_exp_b);
+  IntBinArithHelper(config, fn, kHRegSize, pg_h, zn_h, zm_h, orr_exp_h);
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, orr_exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, orr_exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_sdiv) {
+  // clang-format off
+  int zn_s[] = {0, 1, -1, 2468,
+                INT32_MIN, INT32_MAX, INT32_MIN, INT32_MAX,
+                -11111111, 87654321, 0, 0};
+
+  int zm_s[] = {1, -1, 1, 1234,
+                -1, INT32_MIN, 1, -1,
+                22222222, 80000000, -1, 0};
+
+  int64_t zn_d[] = {0, 1, -1, 2468,
+                    INT64_MIN, INT64_MAX, INT64_MIN, INT64_MAX,
+                    -11111111, 87654321, 0, 0};
+
+  int64_t zm_d[] = {1, -1, 1, 1234,
+                    -1, INT64_MIN, 1, -1,
+                    22222222, 80000000, -1, 0};
+
+  int pg_s[] = {1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0};
+  int pg_d[] = {0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1};
+
+  int exp_s[] = {0, 1, -1, 2,
+                 INT32_MIN, 0, INT32_MIN, -INT32_MAX,
+                 0, 1, 0, 0};
+
+  int64_t exp_d[] = {0, -1, -1, 2,
+                     INT64_MIN, INT64_MAX, INT64_MIN, -INT64_MAX,
+                     0, 1, 0, 0};
+
+  ArithPredicatedFn fn = &MacroAssembler::Sdiv;
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_udiv) {
+  // clang-format off
+  unsigned zn_s[] = {0x00000000, 0x00000001, 0xffffffff, 0x80000000,
+                     0xffffffff, 0x80000000, 0xffffffff, 0x0000f000};
+
+  unsigned zm_s[] = {0x00000001, 0xffffffff, 0x80000000, 0x00000002,
+                     0x00000000, 0x00000001, 0x00008000, 0xf0000000};
+
+  uint64_t zn_d[] = {0x0000000000000000, 0x0000000000000001,
+                     0xffffffffffffffff, 0x8000000000000000,
+                     0xffffffffffffffff, 0x8000000000000000,
+                     0xffffffffffffffff, 0xf0000000f0000000};
+
+  uint64_t zm_d[] = {0x0000000000000001, 0xffffffff00000000,
+                     0x8000000000000000, 0x0000000000000002,
+                     0x8888888888888888, 0x0000000000000001,
+                     0x0000000080000000, 0x00000000f0000000};
+
+  int pg_s[] = {1, 1, 0, 1, 1, 0, 1, 1};
+  int pg_d[] = {1, 0, 1, 1, 1, 1, 0, 1};
+
+  unsigned exp_s[] = {0x00000000, 0x00000000, 0xffffffff, 0x40000000,
+                      0x00000000, 0x80000000, 0x0001ffff, 0x00000000};
+
+  uint64_t exp_d[] = {0x0000000000000000, 0x0000000000000001,
+                      0x0000000000000001, 0x4000000000000000,
+                      0x0000000000000001, 0x8000000000000000,
+                      0xffffffffffffffff, 0x0000000100000001};
+
+  ArithPredicatedFn fn = &MacroAssembler::Udiv;
+  IntBinArithHelper(config, fn, kSRegSize, pg_s, zn_s, zm_s, exp_s);
+  IntBinArithHelper(config, fn, kDRegSize, pg_d, zn_d, zm_d, exp_d);
+  // clang-format on
+}
+
+typedef void (MacroAssembler::*ArithFn)(const ZRegister& zd,
+                                        const ZRegister& zn,
+                                        const ZRegister& zm);
+
+template <typename T>
+static void IntArithHelper(Test* config,
+                           ArithFn macro,
+                           unsigned lane_size_in_bits,
+                           const T& zn_inputs,
+                           const T& zm_inputs,
+                           const T& zd_expected) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  ZRegister zn = z31.WithLaneSize(lane_size_in_bits);
+  ZRegister zm = z27.WithLaneSize(lane_size_in_bits);
+  InsrHelper(&masm, zn, zn_inputs);
+  InsrHelper(&masm, zm, zm_inputs);
+
+  ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
+  (masm.*macro)(zd, zn, zm);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(zd_expected, zd);
+  }
+}
+
+TEST_SVE(sve_arithmetic_unpredicated_add_sqadd_uqadd) {
+  // clang-format off
+  unsigned in_b[] = {0x81, 0x7f, 0x10, 0xaa, 0x55, 0xff, 0xf0};
+  unsigned in_h[] = {0x8181, 0x7f7f, 0x1010, 0xaaaa, 0x5555, 0xffff, 0xf0f0};
+  unsigned in_s[] = {0x80018181, 0x7fff7f7f, 0x10001010, 0xaaaaaaaa, 0xf000f0f0};
+  uint64_t in_d[] = {0x8000000180018181, 0x7fffffff7fff7f7f,
+                      0x1000000010001010, 0xf0000000f000f0f0};
+
+  ArithFn fn = &MacroAssembler::Add;
+
+  unsigned add_exp_b[] = {0x02, 0xfe, 0x20, 0x54, 0xaa, 0xfe, 0xe0};
+  unsigned add_exp_h[] = {0x0302, 0xfefe, 0x2020, 0x5554, 0xaaaa, 0xfffe, 0xe1e0};
+  unsigned add_exp_s[] = {0x00030302, 0xfffefefe, 0x20002020, 0x55555554, 0xe001e1e0};
+  uint64_t add_exp_d[] = {0x0000000300030302, 0xfffffffefffefefe,
+                          0x2000000020002020, 0xe0000001e001e1e0};
+
+  IntArithHelper(config, fn, kBRegSize, in_b, in_b, add_exp_b);
+  IntArithHelper(config, fn, kHRegSize, in_h, in_h, add_exp_h);
+  IntArithHelper(config, fn, kSRegSize, in_s, in_s, add_exp_s);
+  IntArithHelper(config, fn, kDRegSize, in_d, in_d, add_exp_d);
+
+  fn = &MacroAssembler::Sqadd;
+
+  unsigned sqadd_exp_b[] = {0x80, 0x7f, 0x20, 0x80, 0x7f, 0xfe, 0xe0};
+  unsigned sqadd_exp_h[] = {0x8000, 0x7fff, 0x2020, 0x8000, 0x7fff, 0xfffe, 0xe1e0};
+  unsigned sqadd_exp_s[] = {0x80000000, 0x7fffffff, 0x20002020, 0x80000000, 0xe001e1e0};
+  uint64_t sqadd_exp_d[] = {0x8000000000000000, 0x7fffffffffffffff,
+                            0x2000000020002020, 0xe0000001e001e1e0};
+
+  IntArithHelper(config, fn, kBRegSize, in_b, in_b, sqadd_exp_b);
+  IntArithHelper(config, fn, kHRegSize, in_h, in_h, sqadd_exp_h);
+  IntArithHelper(config, fn, kSRegSize, in_s, in_s, sqadd_exp_s);
+  IntArithHelper(config, fn, kDRegSize, in_d, in_d, sqadd_exp_d);
+
+  fn = &MacroAssembler::Uqadd;
+
+  unsigned uqadd_exp_b[] = {0xff, 0xfe, 0x20, 0xff, 0xaa, 0xff, 0xff};
+  unsigned uqadd_exp_h[] = {0xffff, 0xfefe, 0x2020, 0xffff, 0xaaaa, 0xffff, 0xffff};
+  unsigned uqadd_exp_s[] = {0xffffffff, 0xfffefefe, 0x20002020, 0xffffffff, 0xffffffff};
+  uint64_t uqadd_exp_d[] = {0xffffffffffffffff, 0xfffffffefffefefe,
+                            0x2000000020002020, 0xffffffffffffffff};
+
+  IntArithHelper(config, fn, kBRegSize, in_b, in_b, uqadd_exp_b);
+  IntArithHelper(config, fn, kHRegSize, in_h, in_h, uqadd_exp_h);
+  IntArithHelper(config, fn, kSRegSize, in_s, in_s, uqadd_exp_s);
+  IntArithHelper(config, fn, kDRegSize, in_d, in_d, uqadd_exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_arithmetic_unpredicated_sub_sqsub_uqsub) {
+  // clang-format off
+
+  unsigned ins1_b[] = {0x81, 0x7f, 0x7e, 0xaa};
+  unsigned ins2_b[] = {0x10, 0xf0, 0xf0, 0x55};
+
+  unsigned ins1_h[] = {0x8181, 0x7f7f, 0x7e7e, 0xaaaa};
+  unsigned ins2_h[] = {0x1010, 0xf0f0, 0xf0f0, 0x5555};
+
+  unsigned ins1_s[] = {0x80018181, 0x7fff7f7f, 0x7eee7e7e, 0xaaaaaaaa};
+  unsigned ins2_s[] = {0x10001010, 0xf000f0f0, 0xf000f0f0, 0x55555555};
+
+  uint64_t ins1_d[] = {0x8000000180018181, 0x7fffffff7fff7f7f,
+                       0x7eeeeeee7eee7e7e, 0xaaaaaaaaaaaaaaaa};
+  uint64_t ins2_d[] = {0x1000000010001010, 0xf0000000f000f0f0,
+                       0xf0000000f000f0f0, 0x5555555555555555};
+
+  ArithFn fn = &MacroAssembler::Sub;
+
+  unsigned ins1_sub_ins2_exp_b[] = {0x71, 0x8f, 0x8e, 0x55};
+  unsigned ins1_sub_ins2_exp_h[] = {0x7171, 0x8e8f, 0x8d8e, 0x5555};
+  unsigned ins1_sub_ins2_exp_s[] = {0x70017171, 0x8ffe8e8f, 0x8eed8d8e, 0x55555555};
+  uint64_t ins1_sub_ins2_exp_d[] = {0x7000000170017171, 0x8ffffffe8ffe8e8f,
+                                    0x8eeeeeed8eed8d8e, 0x5555555555555555};
+
+  IntArithHelper(config, fn, kBRegSize, ins1_b, ins2_b, ins1_sub_ins2_exp_b);
+  IntArithHelper(config, fn, kHRegSize, ins1_h, ins2_h, ins1_sub_ins2_exp_h);
+  IntArithHelper(config, fn, kSRegSize, ins1_s, ins2_s, ins1_sub_ins2_exp_s);
+  IntArithHelper(config, fn, kDRegSize, ins1_d, ins2_d, ins1_sub_ins2_exp_d);
+
+  unsigned ins2_sub_ins1_exp_b[] = {0x8f, 0x71, 0x72, 0xab};
+  unsigned ins2_sub_ins1_exp_h[] = {0x8e8f, 0x7171, 0x7272, 0xaaab};
+  unsigned ins2_sub_ins1_exp_s[] = {0x8ffe8e8f, 0x70017171, 0x71127272, 0xaaaaaaab};
+  uint64_t ins2_sub_ins1_exp_d[] = {0x8ffffffe8ffe8e8f, 0x7000000170017171,
+                                    0x7111111271127272, 0xaaaaaaaaaaaaaaab};
+
+  IntArithHelper(config, fn, kBRegSize, ins2_b, ins1_b, ins2_sub_ins1_exp_b);
+  IntArithHelper(config, fn, kHRegSize, ins2_h, ins1_h, ins2_sub_ins1_exp_h);
+  IntArithHelper(config, fn, kSRegSize, ins2_s, ins1_s, ins2_sub_ins1_exp_s);
+  IntArithHelper(config, fn, kDRegSize, ins2_d, ins1_d, ins2_sub_ins1_exp_d);
+
+  fn = &MacroAssembler::Sqsub;
+
+  unsigned ins1_sqsub_ins2_exp_b[] = {0x80, 0x7f, 0x7f, 0x80};
+  unsigned ins1_sqsub_ins2_exp_h[] = {0x8000, 0x7fff, 0x7fff, 0x8000};
+  unsigned ins1_sqsub_ins2_exp_s[] = {0x80000000, 0x7fffffff, 0x7fffffff, 0x80000000};
+  uint64_t ins1_sqsub_ins2_exp_d[] = {0x8000000000000000, 0x7fffffffffffffff,
+                                      0x7fffffffffffffff, 0x8000000000000000};
+
+  IntArithHelper(config, fn, kBRegSize, ins1_b, ins2_b, ins1_sqsub_ins2_exp_b);
+  IntArithHelper(config, fn, kHRegSize, ins1_h, ins2_h, ins1_sqsub_ins2_exp_h);
+  IntArithHelper(config, fn, kSRegSize, ins1_s, ins2_s, ins1_sqsub_ins2_exp_s);
+  IntArithHelper(config, fn, kDRegSize, ins1_d, ins2_d, ins1_sqsub_ins2_exp_d);
+
+  unsigned ins2_sqsub_ins1_exp_b[] = {0x7f, 0x80, 0x80, 0x7f};
+  unsigned ins2_sqsub_ins1_exp_h[] = {0x7fff, 0x8000, 0x8000, 0x7fff};
+  unsigned ins2_sqsub_ins1_exp_s[] = {0x7fffffff, 0x80000000, 0x80000000, 0x7fffffff};
+  uint64_t ins2_sqsub_ins1_exp_d[] = {0x7fffffffffffffff, 0x8000000000000000,
+                                      0x8000000000000000, 0x7fffffffffffffff};
+
+  IntArithHelper(config, fn, kBRegSize, ins2_b, ins1_b, ins2_sqsub_ins1_exp_b);
+  IntArithHelper(config, fn, kHRegSize, ins2_h, ins1_h, ins2_sqsub_ins1_exp_h);
+  IntArithHelper(config, fn, kSRegSize, ins2_s, ins1_s, ins2_sqsub_ins1_exp_s);
+  IntArithHelper(config, fn, kDRegSize, ins2_d, ins1_d, ins2_sqsub_ins1_exp_d);
+
+  fn = &MacroAssembler::Uqsub;
+
+  unsigned ins1_uqsub_ins2_exp_b[] = {0x71, 0x00, 0x00, 0x55};
+  unsigned ins1_uqsub_ins2_exp_h[] = {0x7171, 0x0000, 0x0000, 0x5555};
+  unsigned ins1_uqsub_ins2_exp_s[] = {0x70017171, 0x00000000, 0x00000000, 0x55555555};
+  uint64_t ins1_uqsub_ins2_exp_d[] = {0x7000000170017171, 0x0000000000000000,
+                                      0x0000000000000000, 0x5555555555555555};
+
+  IntArithHelper(config, fn, kBRegSize, ins1_b, ins2_b, ins1_uqsub_ins2_exp_b);
+  IntArithHelper(config, fn, kHRegSize, ins1_h, ins2_h, ins1_uqsub_ins2_exp_h);
+  IntArithHelper(config, fn, kSRegSize, ins1_s, ins2_s, ins1_uqsub_ins2_exp_s);
+  IntArithHelper(config, fn, kDRegSize, ins1_d, ins2_d, ins1_uqsub_ins2_exp_d);
+
+  unsigned ins2_uqsub_ins1_exp_b[] = {0x00, 0x71, 0x72, 0x00};
+  unsigned ins2_uqsub_ins1_exp_h[] = {0x0000, 0x7171, 0x7272, 0x0000};
+  unsigned ins2_uqsub_ins1_exp_s[] = {0x00000000, 0x70017171, 0x71127272, 0x00000000};
+  uint64_t ins2_uqsub_ins1_exp_d[] = {0x0000000000000000, 0x7000000170017171,
+                                      0x7111111271127272, 0x0000000000000000};
+
+  IntArithHelper(config, fn, kBRegSize, ins2_b, ins1_b, ins2_uqsub_ins1_exp_b);
+  IntArithHelper(config, fn, kHRegSize, ins2_h, ins1_h, ins2_uqsub_ins1_exp_h);
+  IntArithHelper(config, fn, kSRegSize, ins2_s, ins1_s, ins2_uqsub_ins1_exp_s);
+  IntArithHelper(config, fn, kDRegSize, ins2_d, ins1_d, ins2_uqsub_ins1_exp_d);
+  // clang-format on
+}
+
+TEST_SVE(sve_rdvl) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Encodable multipliers.
+  __ Rdvl(x0, 0);
+  __ Rdvl(x1, 1);
+  __ Rdvl(x2, 2);
+  __ Rdvl(x3, 31);
+  __ Rdvl(x4, -1);
+  __ Rdvl(x5, -2);
+  __ Rdvl(x6, -32);
+
+  // For unencodable multipliers, the MacroAssembler uses a sequence of
+  // instructions.
+  __ Rdvl(x10, 32);
+  __ Rdvl(x11, -33);
+  __ Rdvl(x12, 42);
+  __ Rdvl(x13, -42);
+
+  // The maximum value of VL is 256 (bytes), so the multiplier is limited to the
+  // range [INT64_MIN/256, INT64_MAX/256], to ensure that no signed overflow
+  // occurs in the macro.
+  __ Rdvl(x14, 0x007fffffffffffff);
+  __ Rdvl(x15, -0x0080000000000000);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t vl = config->sve_vl_in_bytes();
+
+    ASSERT_EQUAL_64(vl * 0, x0);
+    ASSERT_EQUAL_64(vl * 1, x1);
+    ASSERT_EQUAL_64(vl * 2, x2);
+    ASSERT_EQUAL_64(vl * 31, x3);
+    ASSERT_EQUAL_64(vl * -1, x4);
+    ASSERT_EQUAL_64(vl * -2, x5);
+    ASSERT_EQUAL_64(vl * -32, x6);
+
+    ASSERT_EQUAL_64(vl * 32, x10);
+    ASSERT_EQUAL_64(vl * -33, x11);
+    ASSERT_EQUAL_64(vl * 42, x12);
+    ASSERT_EQUAL_64(vl * -42, x13);
+
+    ASSERT_EQUAL_64(vl * 0x007fffffffffffff, x14);
+    ASSERT_EQUAL_64(vl * 0xff80000000000000, x15);
+  }
+}
+
+TEST_SVE(sve_rdpl) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // There is no `rdpl` instruction, so the MacroAssembler maps `Rdpl` onto
+  // Addpl(xd, xzr, ...).
+
+  // Encodable multipliers (as `addvl`).
+  __ Rdpl(x0, 0);
+  __ Rdpl(x1, 8);
+  __ Rdpl(x2, 248);
+  __ Rdpl(x3, -8);
+  __ Rdpl(x4, -256);
+
+  // Encodable multipliers (as `movz` + `addpl`).
+  __ Rdpl(x7, 31);
+  __ Rdpl(x8, -31);
+
+  // For unencodable multipliers, the MacroAssembler uses a sequence of
+  // instructions.
+  __ Rdpl(x10, 42);
+  __ Rdpl(x11, -42);
+
+  // The maximum value of VL is 256 (bytes), so the multiplier is limited to the
+  // range [INT64_MIN/256, INT64_MAX/256], to ensure that no signed overflow
+  // occurs in the macro.
+  __ Rdpl(x12, 0x007fffffffffffff);
+  __ Rdpl(x13, -0x0080000000000000);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t vl = config->sve_vl_in_bytes();
+    VIXL_ASSERT((vl % kZRegBitsPerPRegBit) == 0);
+    uint64_t pl = vl / kZRegBitsPerPRegBit;
+
+    ASSERT_EQUAL_64(pl * 0, x0);
+    ASSERT_EQUAL_64(pl * 8, x1);
+    ASSERT_EQUAL_64(pl * 248, x2);
+    ASSERT_EQUAL_64(pl * -8, x3);
+    ASSERT_EQUAL_64(pl * -256, x4);
+
+    ASSERT_EQUAL_64(pl * 31, x7);
+    ASSERT_EQUAL_64(pl * -31, x8);
+
+    ASSERT_EQUAL_64(pl * 42, x10);
+    ASSERT_EQUAL_64(pl * -42, x11);
+
+    ASSERT_EQUAL_64(pl * 0x007fffffffffffff, x12);
+    ASSERT_EQUAL_64(pl * 0xff80000000000000, x13);
+  }
+}
+
+TEST_SVE(sve_addvl) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t base = 0x1234567800000000;
+  __ Mov(x30, base);
+
+  // Encodable multipliers.
+  __ Addvl(x0, x30, 0);
+  __ Addvl(x1, x30, 1);
+  __ Addvl(x2, x30, 31);
+  __ Addvl(x3, x30, -1);
+  __ Addvl(x4, x30, -32);
+
+  // For unencodable multipliers, the MacroAssembler uses `Rdvl` and `Add`.
+  __ Addvl(x5, x30, 32);
+  __ Addvl(x6, x30, -33);
+
+  // Test the limits of the multiplier supported by the `Rdvl` macro.
+  __ Addvl(x7, x30, 0x007fffffffffffff);
+  __ Addvl(x8, x30, -0x0080000000000000);
+
+  // Check that xzr behaves correctly.
+  __ Addvl(x9, xzr, 8);
+  __ Addvl(x10, xzr, 42);
+
+  // Check that sp behaves correctly with encodable and unencodable multipliers.
+  __ Addvl(sp, sp, -5);
+  __ Addvl(sp, sp, -37);
+  __ Addvl(x11, sp, -2);
+  __ Addvl(sp, x11, 2);
+  __ Addvl(x12, sp, -42);
+
+  // Restore the value of sp.
+  __ Addvl(sp, x11, 39);
+  __ Addvl(sp, sp, 5);
+
+  // Adjust x11 and x12 to make the test sp-agnostic.
+  __ Sub(x11, sp, x11);
+  __ Sub(x12, sp, x12);
+
+  // Check cases where xd.Is(xn). This stresses scratch register allocation.
+  __ Mov(x20, x30);
+  __ Mov(x21, x30);
+  __ Mov(x22, x30);
+  __ Addvl(x20, x20, 4);
+  __ Addvl(x21, x21, 42);
+  __ Addvl(x22, x22, -0x0080000000000000);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t vl = config->sve_vl_in_bytes();
+
+    ASSERT_EQUAL_64(base + (vl * 0), x0);
+    ASSERT_EQUAL_64(base + (vl * 1), x1);
+    ASSERT_EQUAL_64(base + (vl * 31), x2);
+    ASSERT_EQUAL_64(base + (vl * -1), x3);
+    ASSERT_EQUAL_64(base + (vl * -32), x4);
+
+    ASSERT_EQUAL_64(base + (vl * 32), x5);
+    ASSERT_EQUAL_64(base + (vl * -33), x6);
+
+    ASSERT_EQUAL_64(base + (vl * 0x007fffffffffffff), x7);
+    ASSERT_EQUAL_64(base + (vl * 0xff80000000000000), x8);
+
+    ASSERT_EQUAL_64(vl * 8, x9);
+    ASSERT_EQUAL_64(vl * 42, x10);
+
+    ASSERT_EQUAL_64(vl * 44, x11);
+    ASSERT_EQUAL_64(vl * 84, x12);
+
+    ASSERT_EQUAL_64(base + (vl * 4), x20);
+    ASSERT_EQUAL_64(base + (vl * 42), x21);
+    ASSERT_EQUAL_64(base + (vl * 0xff80000000000000), x22);
+
+    ASSERT_EQUAL_64(base, x30);
+  }
+}
+
+TEST_SVE(sve_addpl) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t base = 0x1234567800000000;
+  __ Mov(x30, base);
+
+  // Encodable multipliers.
+  __ Addpl(x0, x30, 0);
+  __ Addpl(x1, x30, 1);
+  __ Addpl(x2, x30, 31);
+  __ Addpl(x3, x30, -1);
+  __ Addpl(x4, x30, -32);
+
+  // For unencodable multipliers, the MacroAssembler uses `Addvl` if it can, or
+  // it falls back to `Rdvl` and `Add`.
+  __ Addpl(x5, x30, 32);
+  __ Addpl(x6, x30, -33);
+
+  // Test the limits of the multiplier supported by the `Rdvl` macro.
+  __ Addpl(x7, x30, 0x007fffffffffffff);
+  __ Addpl(x8, x30, -0x0080000000000000);
+
+  // Check that xzr behaves correctly.
+  __ Addpl(x9, xzr, 8);
+  __ Addpl(x10, xzr, 42);
+
+  // Check that sp behaves correctly with encodable and unencodable multipliers.
+  __ Addpl(sp, sp, -5);
+  __ Addpl(sp, sp, -37);
+  __ Addpl(x11, sp, -2);
+  __ Addpl(sp, x11, 2);
+  __ Addpl(x12, sp, -42);
+
+  // Restore the value of sp.
+  __ Addpl(sp, x11, 39);
+  __ Addpl(sp, sp, 5);
+
+  // Adjust x11 and x12 to make the test sp-agnostic.
+  __ Sub(x11, sp, x11);
+  __ Sub(x12, sp, x12);
+
+  // Check cases where xd.Is(xn). This stresses scratch register allocation.
+  __ Mov(x20, x30);
+  __ Mov(x21, x30);
+  __ Mov(x22, x30);
+  __ Addpl(x20, x20, 4);
+  __ Addpl(x21, x21, 42);
+  __ Addpl(x22, x22, -0x0080000000000000);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t vl = config->sve_vl_in_bytes();
+    VIXL_ASSERT((vl % kZRegBitsPerPRegBit) == 0);
+    uint64_t pl = vl / kZRegBitsPerPRegBit;
+
+    ASSERT_EQUAL_64(base + (pl * 0), x0);
+    ASSERT_EQUAL_64(base + (pl * 1), x1);
+    ASSERT_EQUAL_64(base + (pl * 31), x2);
+    ASSERT_EQUAL_64(base + (pl * -1), x3);
+    ASSERT_EQUAL_64(base + (pl * -32), x4);
+
+    ASSERT_EQUAL_64(base + (pl * 32), x5);
+    ASSERT_EQUAL_64(base + (pl * -33), x6);
+
+    ASSERT_EQUAL_64(base + (pl * 0x007fffffffffffff), x7);
+    ASSERT_EQUAL_64(base + (pl * 0xff80000000000000), x8);
+
+    ASSERT_EQUAL_64(pl * 8, x9);
+    ASSERT_EQUAL_64(pl * 42, x10);
+
+    ASSERT_EQUAL_64(pl * 44, x11);
+    ASSERT_EQUAL_64(pl * 84, x12);
+
+    ASSERT_EQUAL_64(base + (pl * 4), x20);
+    ASSERT_EQUAL_64(base + (pl * 42), x21);
+    ASSERT_EQUAL_64(base + (pl * 0xff80000000000000), x22);
+
+    ASSERT_EQUAL_64(base, x30);
+  }
+}
+
+TEST_SVE(sve_calculate_sve_address) {
+  // Shadow the `MacroAssembler` type so that the test macros work without
+  // modification.
+  typedef CalculateSVEAddressMacroAssembler MacroAssembler;
+
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();  // NOLINT(clang-diagnostic-local-type-template-args)
+
+  uint64_t base = 0x1234567800000000;
+  __ Mov(x28, base);
+  __ Mov(x29, 48);
+  __ Mov(x30, -48);
+
+  // Simple scalar (or equivalent) cases.
+
+  __ CalculateSVEAddress(x0, SVEMemOperand(x28));
+  __ CalculateSVEAddress(x1, SVEMemOperand(x28, 0));
+  __ CalculateSVEAddress(x2, SVEMemOperand(x28, 0, SVE_MUL_VL));
+  __ CalculateSVEAddress(x3, SVEMemOperand(x28, 0, SVE_MUL_VL), 3);
+  __ CalculateSVEAddress(x4, SVEMemOperand(x28, xzr));
+  __ CalculateSVEAddress(x5, SVEMemOperand(x28, xzr, LSL, 42));
+
+  // scalar-plus-immediate
+
+  // Unscaled immediates, handled with `Add`.
+  __ CalculateSVEAddress(x6, SVEMemOperand(x28, 42));
+  __ CalculateSVEAddress(x7, SVEMemOperand(x28, -42));
+  // Scaled immediates, handled with `Addvl` or `Addpl`.
+  __ CalculateSVEAddress(x8, SVEMemOperand(x28, 31, SVE_MUL_VL), 0);
+  __ CalculateSVEAddress(x9, SVEMemOperand(x28, -32, SVE_MUL_VL), 0);
+  // Out of `addvl` or `addpl` range.
+  __ CalculateSVEAddress(x10, SVEMemOperand(x28, 42, SVE_MUL_VL), 0);
+  __ CalculateSVEAddress(x11, SVEMemOperand(x28, -42, SVE_MUL_VL), 0);
+  // As above, for VL-based accesses smaller than a Z register.
+  VIXL_STATIC_ASSERT(kZRegBitsPerPRegBitLog2 == 3);
+  __ CalculateSVEAddress(x12, SVEMemOperand(x28, -32 * 8, SVE_MUL_VL), 3);
+  __ CalculateSVEAddress(x13, SVEMemOperand(x28, -42 * 8, SVE_MUL_VL), 3);
+  __ CalculateSVEAddress(x14, SVEMemOperand(x28, -32 * 4, SVE_MUL_VL), 2);
+  __ CalculateSVEAddress(x15, SVEMemOperand(x28, -42 * 4, SVE_MUL_VL), 2);
+  __ CalculateSVEAddress(x18, SVEMemOperand(x28, -32 * 2, SVE_MUL_VL), 1);
+  __ CalculateSVEAddress(x19, SVEMemOperand(x28, -42 * 2, SVE_MUL_VL), 1);
+
+  // scalar-plus-scalar
+
+  __ CalculateSVEAddress(x20, SVEMemOperand(x28, x29));
+  __ CalculateSVEAddress(x21, SVEMemOperand(x28, x30));
+  __ CalculateSVEAddress(x22, SVEMemOperand(x28, x29, LSL, 8));
+  __ CalculateSVEAddress(x23, SVEMemOperand(x28, x30, LSL, 8));
+
+  // In-place updates, to stress scratch register allocation.
+
+  __ Mov(x24, 0xabcd000000000000);
+  __ Mov(x25, 0xabcd101100000000);
+  __ Mov(x26, 0xabcd202200000000);
+  __ Mov(x27, 0xabcd303300000000);
+  __ Mov(x28, 0xabcd404400000000);
+  __ Mov(x29, 0xabcd505500000000);
+
+  __ CalculateSVEAddress(x24, SVEMemOperand(x24));
+  __ CalculateSVEAddress(x25, SVEMemOperand(x25, 0x42));
+  __ CalculateSVEAddress(x26, SVEMemOperand(x26, 3, SVE_MUL_VL), 0);
+  __ CalculateSVEAddress(x27, SVEMemOperand(x27, 0x42, SVE_MUL_VL), 3);
+  __ CalculateSVEAddress(x28, SVEMemOperand(x28, x30));
+  __ CalculateSVEAddress(x29, SVEMemOperand(x29, x30, LSL, 4));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t vl = config->sve_vl_in_bytes();
+    VIXL_ASSERT((vl % kZRegBitsPerPRegBit) == 0);
+    uint64_t pl = vl / kZRegBitsPerPRegBit;
+
+    // Simple scalar (or equivalent) cases.
+    ASSERT_EQUAL_64(base, x0);
+    ASSERT_EQUAL_64(base, x1);
+    ASSERT_EQUAL_64(base, x2);
+    ASSERT_EQUAL_64(base, x3);
+    ASSERT_EQUAL_64(base, x4);
+    ASSERT_EQUAL_64(base, x5);
+
+    // scalar-plus-immediate
+    ASSERT_EQUAL_64(base + 42, x6);
+    ASSERT_EQUAL_64(base - 42, x7);
+    ASSERT_EQUAL_64(base + (31 * vl), x8);
+    ASSERT_EQUAL_64(base - (32 * vl), x9);
+    ASSERT_EQUAL_64(base + (42 * vl), x10);
+    ASSERT_EQUAL_64(base - (42 * vl), x11);
+    ASSERT_EQUAL_64(base - (32 * vl), x12);
+    ASSERT_EQUAL_64(base - (42 * vl), x13);
+    ASSERT_EQUAL_64(base - (32 * vl), x14);
+    ASSERT_EQUAL_64(base - (42 * vl), x15);
+    ASSERT_EQUAL_64(base - (32 * vl), x18);
+    ASSERT_EQUAL_64(base - (42 * vl), x19);
+
+    // scalar-plus-scalar
+    ASSERT_EQUAL_64(base + 48, x20);
+    ASSERT_EQUAL_64(base - 48, x21);
+    ASSERT_EQUAL_64(base + (48 << 8), x22);
+    ASSERT_EQUAL_64(base - (48 << 8), x23);
+
+    // In-place updates.
+    ASSERT_EQUAL_64(0xabcd000000000000, x24);
+    ASSERT_EQUAL_64(0xabcd101100000000 + 0x42, x25);
+    ASSERT_EQUAL_64(0xabcd202200000000 + (3 * vl), x26);
+    ASSERT_EQUAL_64(0xabcd303300000000 + (0x42 * pl), x27);
+    ASSERT_EQUAL_64(0xabcd404400000000 - 48, x28);
+    ASSERT_EQUAL_64(0xabcd505500000000 - (48 << 4), x29);
+  }
+}
+
+TEST_SVE(sve_permute_vector_unpredicated) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kNEON);
+  START();
+
+  // Initialise registers with known values first.
+  __ Dup(z1.VnB(), 0x11);
+  __ Dup(z2.VnB(), 0x22);
+  __ Dup(z3.VnB(), 0x33);
+  __ Dup(z4.VnB(), 0x44);
+
+  __ Mov(x0, 0x0123456789abcdef);
+  __ Fmov(d0, RawbitsToDouble(0x7ffaaaaa22223456));
+  __ Insr(z1.VnS(), w0);
+  __ Insr(z2.VnD(), x0);
+  __ Insr(z3.VnH(), h0);
+  __ Insr(z4.VnD(), d0);
+
+  uint64_t inputs[] = {0xfedcba9876543210,
+                       0x0123456789abcdef,
+                       0x8f8e8d8c8b8a8988,
+                       0x8786858483828180};
+
+  // Initialize a distinguishable value throughout the register first.
+  __ Dup(z9.VnB(), 0xff);
+  InsrHelper(&masm, z9.VnD(), inputs);
+
+  __ Rev(z5.VnB(), z9.VnB());
+  __ Rev(z6.VnH(), z9.VnH());
+  __ Rev(z7.VnS(), z9.VnS());
+  __ Rev(z8.VnD(), z9.VnD());
+
+  int index[7] = {22, 7, 7, 3, 1, 1, 63};
+  // Broadcasting an data within the input array.
+  __ Dup(z10.VnB(), z9.VnB(), index[0]);
+  __ Dup(z11.VnH(), z9.VnH(), index[1]);
+  __ Dup(z12.VnS(), z9.VnS(), index[2]);
+  __ Dup(z13.VnD(), z9.VnD(), index[3]);
+  __ Dup(z14.VnQ(), z9.VnQ(), index[4]);
+  // Test dst == src
+  __ Mov(z15, z9);
+  __ Dup(z15.VnS(), z15.VnS(), index[5]);
+  // Selecting an data beyond the input array.
+  __ Dup(z16.VnB(), z9.VnB(), index[6]);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Insr
+    uint64_t z1_expected[] = {0x1111111111111111, 0x1111111189abcdef};
+    uint64_t z2_expected[] = {0x2222222222222222, 0x0123456789abcdef};
+    uint64_t z3_expected[] = {0x3333333333333333, 0x3333333333333456};
+    uint64_t z4_expected[] = {0x4444444444444444, 0x7ffaaaaa22223456};
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+
+    // Rev
+    int lane_count = core.GetSVELaneCount(kBRegSize);
+    for (int i = 0; i < lane_count; i++) {
+      uint64_t expected =
+          core.zreg_lane(z5.GetCode(), kBRegSize, lane_count - i - 1);
+      uint64_t input = core.zreg_lane(z9.GetCode(), kBRegSize, i);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kHRegSize);
+    for (int i = 0; i < lane_count; i++) {
+      uint64_t expected =
+          core.zreg_lane(z6.GetCode(), kHRegSize, lane_count - i - 1);
+      uint64_t input = core.zreg_lane(z9.GetCode(), kHRegSize, i);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kSRegSize);
+    for (int i = 0; i < lane_count; i++) {
+      uint64_t expected =
+          core.zreg_lane(z7.GetCode(), kSRegSize, lane_count - i - 1);
+      uint64_t input = core.zreg_lane(z9.GetCode(), kSRegSize, i);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kDRegSize);
+    for (int i = 0; i < lane_count; i++) {
+      uint64_t expected =
+          core.zreg_lane(z8.GetCode(), kDRegSize, lane_count - i - 1);
+      uint64_t input = core.zreg_lane(z9.GetCode(), kDRegSize, i);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    // Dup
+    unsigned vl = config->sve_vl_in_bits();
+    lane_count = core.GetSVELaneCount(kBRegSize);
+    uint64_t expected_z10 = (vl > (index[0] * kBRegSize)) ? 0x23 : 0;
+    for (int i = 0; i < lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(expected_z10, z10.VnB(), i);
+    }
+
+    lane_count = core.GetSVELaneCount(kHRegSize);
+    uint64_t expected_z11 = (vl > (index[1] * kHRegSize)) ? 0x8f8e : 0;
+    for (int i = 0; i < lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(expected_z11, z11.VnH(), i);
+    }
+
+    lane_count = core.GetSVELaneCount(kSRegSize);
+    uint64_t expected_z12 = (vl > (index[2] * kSRegSize)) ? 0xfedcba98 : 0;
+    for (int i = 0; i < lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(expected_z12, z12.VnS(), i);
+    }
+
+    lane_count = core.GetSVELaneCount(kDRegSize);
+    uint64_t expected_z13 =
+        (vl > (index[3] * kDRegSize)) ? 0xfedcba9876543210 : 0;
+    for (int i = 0; i < lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(expected_z13, z13.VnD(), i);
+    }
+
+    lane_count = core.GetSVELaneCount(kDRegSize);
+    uint64_t expected_z14_lo = 0;
+    uint64_t expected_z14_hi = 0;
+    if (vl > (index[4] * kQRegSize)) {
+      expected_z14_lo = 0x0123456789abcdef;
+      expected_z14_hi = 0xfedcba9876543210;
+    }
+    for (int i = 0; i < lane_count; i += 2) {
+      ASSERT_EQUAL_SVE_LANE(expected_z14_lo, z14.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(expected_z14_hi, z14.VnD(), i + 1);
+    }
+
+    lane_count = core.GetSVELaneCount(kSRegSize);
+    uint64_t expected_z15 = (vl > (index[5] * kSRegSize)) ? 0x87868584 : 0;
+    for (int i = 0; i < lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(expected_z15, z15.VnS(), i);
+    }
+
+    lane_count = core.GetSVELaneCount(kBRegSize);
+    uint64_t expected_z16 = (vl > (index[6] * kBRegSize)) ? 0xff : 0;
+    for (int i = 0; i < lane_count; i++) {
+      ASSERT_EQUAL_SVE_LANE(expected_z16, z16.VnB(), i);
+    }
+  }
+}
+
+TEST_SVE(sve_permute_vector_unpredicated_unpack_vector_elements) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t z9_inputs[] = {0xfedcba9876543210,
+                          0x0123456789abcdef,
+                          0x8f8e8d8c8b8a8988,
+                          0x8786858483828180};
+  InsrHelper(&masm, z9.VnD(), z9_inputs);
+
+  __ Sunpkhi(z10.VnH(), z9.VnB());
+  __ Sunpkhi(z11.VnS(), z9.VnH());
+  __ Sunpkhi(z12.VnD(), z9.VnS());
+
+  __ Sunpklo(z13.VnH(), z9.VnB());
+  __ Sunpklo(z14.VnS(), z9.VnH());
+  __ Sunpklo(z15.VnD(), z9.VnS());
+
+  __ Uunpkhi(z16.VnH(), z9.VnB());
+  __ Uunpkhi(z17.VnS(), z9.VnH());
+  __ Uunpkhi(z18.VnD(), z9.VnS());
+
+  __ Uunpklo(z19.VnH(), z9.VnB());
+  __ Uunpklo(z20.VnS(), z9.VnH());
+  __ Uunpklo(z21.VnD(), z9.VnS());
+
+  // Test unpacking with same source and destination.
+  __ Mov(z22, z9);
+  __ Sunpklo(z22.VnH(), z22.VnB());
+  __ Mov(z23, z9);
+  __ Uunpklo(z23.VnH(), z23.VnB());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Suunpkhi
+    int lane_count = core.GetSVELaneCount(kHRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint16_t expected = core.zreg_lane<uint16_t>(z10.GetCode(), i);
+      uint8_t b_lane = core.zreg_lane<uint8_t>(z9.GetCode(), i + lane_count);
+      uint16_t input = SignExtend<int16_t>(b_lane, kBRegSize);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kSRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint32_t expected = core.zreg_lane<uint32_t>(z11.GetCode(), i);
+      uint16_t h_lane = core.zreg_lane<uint16_t>(z9.GetCode(), i + lane_count);
+      uint32_t input = SignExtend<int32_t>(h_lane, kHRegSize);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kDRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint64_t expected = core.zreg_lane<uint64_t>(z12.GetCode(), i);
+      uint32_t s_lane = core.zreg_lane<uint32_t>(z9.GetCode(), i + lane_count);
+      uint64_t input = SignExtend<int64_t>(s_lane, kSRegSize);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    // Suunpklo
+    lane_count = core.GetSVELaneCount(kHRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint16_t expected = core.zreg_lane<uint16_t>(z13.GetCode(), i);
+      uint8_t b_lane = core.zreg_lane<uint8_t>(z9.GetCode(), i);
+      uint16_t input = SignExtend<int16_t>(b_lane, kBRegSize);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kSRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint32_t expected = core.zreg_lane<uint32_t>(z14.GetCode(), i);
+      uint16_t h_lane = core.zreg_lane<uint16_t>(z9.GetCode(), i);
+      uint32_t input = SignExtend<int32_t>(h_lane, kHRegSize);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kDRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint64_t expected = core.zreg_lane<uint64_t>(z15.GetCode(), i);
+      uint32_t s_lane = core.zreg_lane<uint32_t>(z9.GetCode(), i);
+      uint64_t input = SignExtend<int64_t>(s_lane, kSRegSize);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    // Uuunpkhi
+    lane_count = core.GetSVELaneCount(kHRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint16_t expected = core.zreg_lane<uint16_t>(z16.GetCode(), i);
+      uint16_t input = core.zreg_lane<uint8_t>(z9.GetCode(), i + lane_count);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kSRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint32_t expected = core.zreg_lane<uint32_t>(z17.GetCode(), i);
+      uint32_t input = core.zreg_lane<uint16_t>(z9.GetCode(), i + lane_count);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kDRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint64_t expected = core.zreg_lane<uint64_t>(z18.GetCode(), i);
+      uint64_t input = core.zreg_lane<uint32_t>(z9.GetCode(), i + lane_count);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    // Uuunpklo
+    lane_count = core.GetSVELaneCount(kHRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint16_t expected = core.zreg_lane<uint16_t>(z19.GetCode(), i);
+      uint16_t input = core.zreg_lane<uint8_t>(z9.GetCode(), i);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kSRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint32_t expected = core.zreg_lane<uint32_t>(z20.GetCode(), i);
+      uint32_t input = core.zreg_lane<uint16_t>(z9.GetCode(), i);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    lane_count = core.GetSVELaneCount(kDRegSize);
+    for (int i = lane_count - 1; i >= 0; i--) {
+      uint64_t expected = core.zreg_lane<uint64_t>(z21.GetCode(), i);
+      uint64_t input = core.zreg_lane<uint32_t>(z9.GetCode(), i);
+      ASSERT_EQUAL_64(expected, input);
+    }
+
+    ASSERT_EQUAL_SVE(z13, z22);
+    ASSERT_EQUAL_SVE(z19, z23);
+  }
+}
+
+TEST_SVE(sve_cnot_not) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0x0000000000000000, 0x00000000e1c30000, 0x123456789abcdef0};
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+  PRegisterM pg = p0.Merging();
+
+  // These are merging operations, so we have to initialise the result register.
+  // We use a mixture of constructive and destructive operations.
+
+  InsrHelper(&masm, z31.VnD(), in);
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z30, z31);
+
+  // For constructive operations, use a different initial result value.
+  __ Index(z29.VnB(), 0, -1);
+
+  __ Mov(z0, z31);
+  __ Cnot(z0.VnB(), pg, z0.VnB());  // destructive
+  __ Mov(z1, z29);
+  __ Cnot(z1.VnH(), pg, z31.VnH());
+  __ Mov(z2, z31);
+  __ Cnot(z2.VnS(), pg, z2.VnS());  // destructive
+  __ Mov(z3, z29);
+  __ Cnot(z3.VnD(), pg, z31.VnD());
+
+  __ Mov(z4, z29);
+  __ Not(z4.VnB(), pg, z31.VnB());
+  __ Mov(z5, z31);
+  __ Not(z5.VnH(), pg, z5.VnH());  // destructive
+  __ Mov(z6, z29);
+  __ Not(z6.VnS(), pg, z31.VnS());
+  __ Mov(z7, z31);
+  __ Not(z7.VnD(), pg, z7.VnD());  // destructive
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Check that constructive operations preserve their inputs.
+    ASSERT_EQUAL_SVE(z30, z31);
+
+    // clang-format off
+
+    // Cnot (B) destructive
+    uint64_t expected_z0[] =
+    // pg:  0 0 0 0 1 0 1 1     1 0 0 1 0 1 1 1     0 0 1 0 1 1 1 0
+        {0x0000000001000101, 0x01000001e1000101, 0x12340078000000f0};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+
+    // Cnot (H)
+    uint64_t expected_z1[] =
+    // pg:    0   0   0   1       0   1   1   1       0   0   1   0
+        {0xe9eaebecedee0001, 0xf1f2000100000001, 0xf9fafbfc0000ff00};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+
+    // Cnot (S) destructive
+    uint64_t expected_z2[] =
+    // pg:        0       1           1       1           0       0
+        {0x0000000000000001, 0x0000000100000000, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+
+    // Cnot (D)
+    uint64_t expected_z3[] =
+    // pg:                1                   1                   0
+        {0x0000000000000001, 0x0000000000000000, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+
+    // Not (B)
+    uint64_t expected_z4[] =
+    // pg:  0 0 0 0 1 0 1 1     1 0 0 1 0 1 1 1     0 0 1 0 1 1 1 0
+        {0xe9eaebecffeeffff, 0xfff2f3fff53cffff, 0xf9faa9fc65432100};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+
+    // Not (H) destructive
+    uint64_t expected_z5[] =
+    // pg:    0   0   0   1       0   1   1   1       0   0   1   0
+        {0x000000000000ffff, 0x0000ffff1e3cffff, 0x123456786543def0};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+
+    // Not (S)
+    uint64_t expected_z6[] =
+    // pg:        0       1           1       1           0       0
+        {0xe9eaebecffffffff, 0xffffffff1e3cffff, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+
+    // Not (D) destructive
+    uint64_t expected_z7[] =
+    // pg:                1                   1                   0
+        {0xffffffffffffffff, 0xffffffff1e3cffff, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_fabs_fneg) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Include FP64, FP32 and FP16 signalling NaNs. Most FP operations quieten
+  // NaNs, but fabs and fneg do not.
+  uint64_t in[] = {0xc04500004228d140,  // Recognisable (+/-42) values.
+                   0xfff00000ff80fc01,  // Signalling NaNs.
+                   0x123456789abcdef0};
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+  PRegisterM pg = p0.Merging();
+
+  // These are merging operations, so we have to initialise the result register.
+  // We use a mixture of constructive and destructive operations.
+
+  InsrHelper(&masm, z31.VnD(), in);
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z30, z31);
+
+  // For constructive operations, use a different initial result value.
+  __ Index(z29.VnB(), 0, -1);
+
+  __ Mov(z0, z29);
+  __ Fabs(z0.VnH(), pg, z31.VnH());
+  __ Mov(z1, z31);
+  __ Fabs(z1.VnS(), pg, z1.VnS());  // destructive
+  __ Mov(z2, z29);
+  __ Fabs(z2.VnD(), pg, z31.VnD());
+
+  __ Mov(z3, z31);
+  __ Fneg(z3.VnH(), pg, z3.VnH());  // destructive
+  __ Mov(z4, z29);
+  __ Fneg(z4.VnS(), pg, z31.VnS());
+  __ Mov(z5, z31);
+  __ Fneg(z5.VnD(), pg, z5.VnD());  // destructive
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Check that constructive operations preserve their inputs.
+    ASSERT_EQUAL_SVE(z30, z31);
+
+    // clang-format off
+
+    // Fabs (H)
+    uint64_t expected_z0[] =
+    // pg:    0   0   0   1       0   1   1   1       0   0   1   0
+        {0xe9eaebecedee5140, 0xf1f200007f807c01, 0xf9fafbfc1abcff00};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+
+    // Fabs (S) destructive
+    uint64_t expected_z1[] =
+    // pg:        0       1           1       1           0       0
+        {0xc04500004228d140, 0x7ff000007f80fc01, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+
+    // Fabs (D)
+    uint64_t expected_z2[] =
+    // pg:                1                   1                   0
+        {0x404500004228d140, 0x7ff00000ff80fc01, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+
+    // Fneg (H) destructive
+    uint64_t expected_z3[] =
+    // pg:    0   0   0   1       0   1   1   1       0   0   1   0
+        {0xc045000042285140, 0xfff080007f807c01, 0x123456781abcdef0};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+
+    // Fneg (S)
+    uint64_t expected_z4[] =
+    // pg:        0       1           1       1           0       0
+        {0xe9eaebecc228d140, 0x7ff000007f80fc01, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+
+    // Fneg (D) destructive
+    uint64_t expected_z5[] =
+    // pg:                1                   1                   0
+        {0x404500004228d140, 0x7ff00000ff80fc01, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_cls_clz_cnt) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0x0000000000000000, 0xfefcf8f0e1c3870f, 0x123456789abcdef0};
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+  PRegisterM pg = p0.Merging();
+
+  // These are merging operations, so we have to initialise the result register.
+  // We use a mixture of constructive and destructive operations.
+
+  InsrHelper(&masm, z31.VnD(), in);
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z30, z31);
+
+  // For constructive operations, use a different initial result value.
+  __ Index(z29.VnB(), 0, -1);
+
+  __ Mov(z0, z29);
+  __ Cls(z0.VnB(), pg, z31.VnB());
+  __ Mov(z1, z31);
+  __ Clz(z1.VnH(), pg, z1.VnH());  // destructive
+  __ Mov(z2, z29);
+  __ Cnt(z2.VnS(), pg, z31.VnS());
+  __ Mov(z3, z31);
+  __ Cnt(z3.VnD(), pg, z3.VnD());  // destructive
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    // Check that non-destructive operations preserve their inputs.
+    ASSERT_EQUAL_SVE(z30, z31);
+
+    // clang-format off
+
+    // cls (B)
+    uint8_t expected_z0[] =
+    // pg:  0     0     0     0     1     0     1     1
+    // pg:  1     0     0     1     0     1     1     1
+    // pg:  0     0     1     0     1     1     1     0
+        {0xe9, 0xea, 0xeb, 0xec,    7, 0xee,    7,    7,
+            6, 0xf2, 0xf3,    3, 0xf5,    1,    0,    3,
+         0xf9, 0xfa,    0, 0xfc,    0,    0,    1, 0x00};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnB());
+
+    // clz (H) destructive
+    uint16_t expected_z1[] =
+    // pg:    0       0       0       1
+    // pg:    0       1       1       1
+    // pg:    0       0       1       0
+        {0x0000, 0x0000, 0x0000,     16,
+         0xfefc,      0,      0,      0,
+         0x1234, 0x5678,      0, 0xdef0};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnH());
+
+    // cnt (S)
+    uint32_t expected_z2[] =
+    // pg:        0           1
+    // pg:        1           1
+    // pg:        0           0
+        {0xe9eaebec,          0,
+                 22,         16,
+         0xf9fafbfc, 0xfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnS());
+
+    // cnt (D) destructive
+    uint64_t expected_z3[] =
+    // pg:                1                   1                   0
+        {                 0,                 38, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_sxt) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0x01f203f405f607f8, 0xfefcf8f0e1c3870f, 0x123456789abcdef0};
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+  PRegisterM pg = p0.Merging();
+
+  // These are merging operations, so we have to initialise the result register.
+  // We use a mixture of constructive and destructive operations.
+
+  InsrHelper(&masm, z31.VnD(), in);
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z30, z31);
+
+  // For constructive operations, use a different initial result value.
+  __ Index(z29.VnB(), 0, -1);
+
+  __ Mov(z0, z31);
+  __ Sxtb(z0.VnH(), pg, z0.VnH());  // destructive
+  __ Mov(z1, z29);
+  __ Sxtb(z1.VnS(), pg, z31.VnS());
+  __ Mov(z2, z31);
+  __ Sxtb(z2.VnD(), pg, z2.VnD());  // destructive
+  __ Mov(z3, z29);
+  __ Sxth(z3.VnS(), pg, z31.VnS());
+  __ Mov(z4, z31);
+  __ Sxth(z4.VnD(), pg, z4.VnD());  // destructive
+  __ Mov(z5, z29);
+  __ Sxtw(z5.VnD(), pg, z31.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    // Check that constructive operations preserve their inputs.
+    ASSERT_EQUAL_SVE(z30, z31);
+
+    // clang-format off
+
+    // Sxtb (H) destructive
+    uint64_t expected_z0[] =
+    // pg:    0   0   0   1       0   1   1   1       0   0   1   0
+        {0x01f203f405f6fff8, 0xfefcfff0ffc3000f, 0x12345678ffbcdef0};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+
+    // Sxtb (S)
+    uint64_t expected_z1[] =
+    // pg:        0       1           1       1           0       0
+        {0xe9eaebecfffffff8, 0xfffffff00000000f, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+
+    // Sxtb (D) destructive
+    uint64_t expected_z2[] =
+    // pg:                1                   1                   0
+        {0xfffffffffffffff8, 0x000000000000000f, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+
+    // Sxth (S)
+    uint64_t expected_z3[] =
+    // pg:        0       1           1       1           0       0
+        {0xe9eaebec000007f8, 0xfffff8f0ffff870f, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+
+    // Sxth (D) destructive
+    uint64_t expected_z4[] =
+    // pg:                1                   1                   0
+        {0x00000000000007f8, 0xffffffffffff870f, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+
+    // Sxtw (D)
+    uint64_t expected_z5[] =
+    // pg:                1                   1                   0
+        {0x0000000005f607f8, 0xffffffffe1c3870f, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_uxt) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0x01f203f405f607f8, 0xfefcf8f0e1c3870f, 0x123456789abcdef0};
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+  PRegisterM pg = p0.Merging();
+
+  // These are merging operations, so we have to initialise the result register.
+  // We use a mixture of constructive and destructive operations.
+
+  InsrHelper(&masm, z31.VnD(), in);
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z30, z31);
+
+  // For constructive operations, use a different initial result value.
+  __ Index(z29.VnB(), 0, -1);
+
+  __ Mov(z0, z29);
+  __ Uxtb(z0.VnH(), pg, z31.VnH());
+  __ Mov(z1, z31);
+  __ Uxtb(z1.VnS(), pg, z1.VnS());  // destructive
+  __ Mov(z2, z29);
+  __ Uxtb(z2.VnD(), pg, z31.VnD());
+  __ Mov(z3, z31);
+  __ Uxth(z3.VnS(), pg, z3.VnS());  // destructive
+  __ Mov(z4, z29);
+  __ Uxth(z4.VnD(), pg, z31.VnD());
+  __ Mov(z5, z31);
+  __ Uxtw(z5.VnD(), pg, z5.VnD());  // destructive
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    // clang-format off
+
+    // Uxtb (H)
+    uint64_t expected_z0[] =
+    // pg:    0   0   0   1       0   1   1   1       0   0   1   0
+        {0xe9eaebecedee00f8, 0xf1f200f000c3000f, 0xf9fafbfc00bcff00};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+
+    // Uxtb (S) destructive
+    uint64_t expected_z1[] =
+    // pg:        0       1           1       1           0       0
+        {0x01f203f4000000f8, 0x000000f00000000f, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+
+    // Uxtb (D)
+    uint64_t expected_z2[] =
+    // pg:                1                   1                   0
+        {0x00000000000000f8, 0x000000000000000f, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+
+    // Uxth (S) destructive
+    uint64_t expected_z3[] =
+    // pg:        0       1           1       1           0       0
+        {0x01f203f4000007f8, 0x0000f8f00000870f, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+
+    // Uxth (D)
+    uint64_t expected_z4[] =
+    // pg:                1                   1                   0
+        {0x00000000000007f8, 0x000000000000870f, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+
+    // Uxtw (D) destructive
+    uint64_t expected_z5[] =
+    // pg:                1                   1                   0
+        {0x0000000005f607f8, 0x00000000e1c3870f, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_abs_neg) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0x01f203f405f607f8, 0xfefcf8f0e1c3870f, 0x123456789abcdef0};
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+  PRegisterM pg = p0.Merging();
+
+  InsrHelper(&masm, z31.VnD(), in);
+
+  // These are merging operations, so we have to initialise the result register.
+  // We use a mixture of constructive and destructive operations.
+
+  InsrHelper(&masm, z31.VnD(), in);
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z30, z31);
+
+  // For constructive operations, use a different initial result value.
+  __ Index(z29.VnB(), 0, -1);
+
+  __ Mov(z0, z31);
+  __ Abs(z0.VnD(), pg, z0.VnD());  // destructive
+  __ Mov(z1, z29);
+  __ Abs(z1.VnB(), pg, z31.VnB());
+
+  __ Mov(z2, z31);
+  __ Neg(z2.VnH(), pg, z2.VnH());  // destructive
+  __ Mov(z3, z29);
+  __ Neg(z3.VnS(), pg, z31.VnS());
+
+  // The unpredicated form of `Neg` is implemented using `subr`.
+  __ Mov(z4, z31);
+  __ Neg(z4.VnB(), z4.VnB());  // destructive
+  __ Mov(z5, z29);
+  __ Neg(z5.VnD(), z31.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(z30, z31);
+
+    // clang-format off
+
+    // Abs (D) destructive
+    uint64_t expected_z0[] =
+    // pg:                1                   1                   0
+        {0x01f203f405f607f8, 0x0103070f1e3c78f1, 0x123456789abcdef0};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+
+    // Abs (B)
+    uint64_t expected_z1[] =
+    // pg:  0 0 0 0 1 0 1 1     1 0 0 1 0 1 1 1     0 0 1 0 1 1 1 0
+        {0xe9eaebec05ee0708, 0x02f2f310f53d790f, 0xf9fa56fc66442200};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+
+    // Neg (H) destructive
+    uint64_t expected_z2[] =
+    // pg:    0   0   0   1       0   1   1   1       0   0   1   0
+        {0x01f203f405f6f808, 0xfefc07101e3d78f1, 0x123456786544def0};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+
+    // Neg (S)
+    uint64_t expected_z3[] =
+    // pg:        0       1           1       1           0       0
+        {0xe9eaebecfa09f808, 0x010307101e3c78f1, 0xf9fafbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+
+    // Neg (B) destructive, unpredicated
+    uint64_t expected_z4[] =
+        {0xff0efd0cfb0af908, 0x020408101f3d79f1, 0xeeccaa8866442210};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+
+    // Neg (D) unpredicated
+    uint64_t expected_z5[] =
+        {0xfe0dfc0bfa09f808, 0x0103070f1e3c78f1, 0xedcba98765432110};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_cpy) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE, CPUFeatures::kNEON);
+  START();
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         0,                      1,                      1
+  // For S lanes:         0,          1,          1,          0,          1
+  // For H lanes:   1,    0,    0,    1,    0,    1,    1,    0,    0,    1
+  int pg_in[] = {1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1};
+
+  PRegisterM pg = p7.Merging();
+  Initialise(&masm, pg.VnB(), pg_in);
+
+  // These are merging operations, so we have to initialise the result registers
+  // for each operation.
+  for (unsigned i = 0; i < kNumberOfZRegisters; i++) {
+    __ Index(ZRegister(i, kBRegSize), 0, -1);
+  }
+
+  // Recognisable values to copy.
+  __ Mov(x0, 0xdeadbeefdeadbe42);
+  __ Mov(x1, 0xdeadbeefdead8421);
+  __ Mov(x2, 0xdeadbeef80042001);
+  __ Mov(x3, 0x8000000420000001);
+
+  // Use NEON moves, to avoid testing SVE `cpy` against itself.
+  __ Dup(v28.V2D(), x0);
+  __ Dup(v29.V2D(), x1);
+  __ Dup(v30.V2D(), x2);
+  __ Dup(v31.V2D(), x3);
+
+  // Register forms (CPY_z_p_r)
+  __ Cpy(z0.VnB(), pg, w0);
+  __ Cpy(z1.VnH(), pg, x1);  // X registers are accepted for small lanes.
+  __ Cpy(z2.VnS(), pg, w2);
+  __ Cpy(z3.VnD(), pg, x3);
+
+  // VRegister forms (CPY_z_p_v)
+  __ Cpy(z4.VnB(), pg, b28);
+  __ Cpy(z5.VnH(), pg, h29);
+  __ Cpy(z6.VnS(), pg, s30);
+  __ Cpy(z7.VnD(), pg, d31);
+
+  // Check that we can copy the stack pointer.
+  __ Mov(x10, sp);
+  __ Mov(sp, 0xabcabcabcabcabca);  // Set sp to a known value.
+  __ Cpy(z16.VnB(), pg, sp);
+  __ Cpy(z17.VnH(), pg, wsp);
+  __ Cpy(z18.VnS(), pg, wsp);
+  __ Cpy(z19.VnD(), pg, sp);
+  __ Mov(sp, x10);  // Restore sp.
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    // clang-format off
+
+    uint64_t expected_b[] =
+    // pg:  0 0 0 0 1 1 1 0     1 0 0 1 1 0 1 1     0 1 0 0 0 0 0 1
+        {0xe9eaebec424242f0, 0x42f2f34242f64242, 0xf942fbfcfdfeff42};
+    ASSERT_EQUAL_SVE(expected_b, z0.VnD());
+    ASSERT_EQUAL_SVE(expected_b, z4.VnD());
+
+    uint64_t expected_h[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebec8421eff0, 0xf1f28421f5f68421, 0x8421fbfcfdfe8421};
+    ASSERT_EQUAL_SVE(expected_h, z1.VnD());
+    ASSERT_EQUAL_SVE(expected_h, z5.VnD());
+
+    uint64_t expected_s[] =
+    // pg:        0       0           1       1           0       1
+        {0xe9eaebecedeeeff0, 0x8004200180042001, 0xf9fafbfc80042001};
+    ASSERT_EQUAL_SVE(expected_s, z2.VnD());
+    ASSERT_EQUAL_SVE(expected_s, z6.VnD());
+
+    uint64_t expected_d[] =
+    // pg:                0                   1                   1
+        {0xe9eaebecedeeeff0, 0x8000000420000001, 0x8000000420000001};
+    ASSERT_EQUAL_SVE(expected_d, z3.VnD());
+    ASSERT_EQUAL_SVE(expected_d, z7.VnD());
+
+
+    uint64_t expected_b_sp[] =
+    // pg:  0 0 0 0 1 1 1 0     1 0 0 1 1 0 1 1     0 1 0 0 0 0 0 1
+        {0xe9eaebeccacacaf0, 0xcaf2f3cacaf6caca, 0xf9cafbfcfdfeffca};
+    ASSERT_EQUAL_SVE(expected_b_sp, z16.VnD());
+
+    uint64_t expected_h_sp[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebecabcaeff0, 0xf1f2abcaf5f6abca, 0xabcafbfcfdfeabca};
+    ASSERT_EQUAL_SVE(expected_h_sp, z17.VnD());
+
+    uint64_t expected_s_sp[] =
+    // pg:        0       0           1       1           0       1
+        {0xe9eaebecedeeeff0, 0xcabcabcacabcabca, 0xf9fafbfccabcabca};
+    ASSERT_EQUAL_SVE(expected_s_sp, z18.VnD());
+
+    uint64_t expected_d_sp[] =
+    // pg:                0                   1                   1
+        {0xe9eaebecedeeeff0, 0xabcabcabcabcabca, 0xabcabcabcabcabca};
+    ASSERT_EQUAL_SVE(expected_d_sp, z19.VnD());
+
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_cpy_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         0,                      1,                      1
+  // For S lanes:         0,          1,          1,          0,          1
+  // For H lanes:   1,    0,    0,    1,    0,    1,    1,    0,    0,    1
+  int pg_in[] = {1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1};
+
+  PRegister pg = p7;
+  Initialise(&masm, pg.VnB(), pg_in);
+
+  // These are (mostly) merging operations, so we have to initialise the result
+  // registers for each operation.
+  for (unsigned i = 0; i < kNumberOfZRegisters; i++) {
+    __ Index(ZRegister(i, kBRegSize), 0, -1);
+  }
+
+  // Encodable integer forms (CPY_z_p_i)
+  __ Cpy(z0.VnB(), pg.Merging(), 0);
+  __ Cpy(z1.VnB(), pg.Zeroing(), 42);
+  __ Cpy(z2.VnB(), pg.Merging(), -42);
+  __ Cpy(z3.VnB(), pg.Zeroing(), 0xff);
+  __ Cpy(z4.VnH(), pg.Merging(), 127);
+  __ Cpy(z5.VnS(), pg.Zeroing(), -128);
+  __ Cpy(z6.VnD(), pg.Merging(), -1);
+
+  // Forms encodable using fcpy.
+  __ Cpy(z7.VnH(), pg.Merging(), Float16ToRawbits(Float16(-31.0)));
+  __ Cpy(z8.VnS(), pg.Zeroing(), FloatToRawbits(2.0f));
+  __ Cpy(z9.VnD(), pg.Merging(), DoubleToRawbits(-4.0));
+
+  // Other forms use a scratch register.
+  __ Cpy(z10.VnH(), pg.Merging(), 0xff);
+  __ Cpy(z11.VnD(), pg.Zeroing(), 0x0123456789abcdef);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    // clang-format off
+
+    uint64_t expected_z0[] =
+    // pg:  0 0 0 0 1 1 1 0     1 0 0 1 1 0 1 1     0 1 0 0 0 0 0 1
+        {0xe9eaebec000000f0, 0x00f2f30000f60000, 0xf900fbfcfdfeff00};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+
+    uint64_t expected_z1[] =
+    // pg:  0 0 0 0 1 1 1 0     1 0 0 1 1 0 1 1     0 1 0 0 0 0 0 1
+        {0x000000002a2a2a00, 0x2a00002a2a002a2a, 0x002a00000000002a};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+
+    uint64_t expected_z2[] =
+    // pg:  0 0 0 0 1 1 1 0     1 0 0 1 1 0 1 1     0 1 0 0 0 0 0 1
+        {0xe9eaebecd6d6d6f0, 0xd6f2f3d6d6f6d6d6, 0xf9d6fbfcfdfeffd6};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+
+    uint64_t expected_z3[] =
+    // pg:  0 0 0 0 1 1 1 0     1 0 0 1 1 0 1 1     0 1 0 0 0 0 0 1
+        {0x00000000ffffff00, 0xff0000ffff00ffff, 0x00ff0000000000ff};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+
+    uint64_t expected_z4[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebec007feff0, 0xf1f2007ff5f6007f, 0x007ffbfcfdfe007f};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+
+    uint64_t expected_z5[] =
+    // pg:        0       0           1       1           0       1
+        {0x0000000000000000, 0xffffff80ffffff80, 0x00000000ffffff80};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+
+    uint64_t expected_z6[] =
+    // pg:                0                   1                   1
+        {0xe9eaebecedeeeff0, 0xffffffffffffffff, 0xffffffffffffffff};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+
+    uint64_t expected_z7[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebeccfc0eff0, 0xf1f2cfc0f5f6cfc0, 0xcfc0fbfcfdfecfc0};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+
+    uint64_t expected_z8[] =
+    // pg:        0       0           1       1           0       1
+        {0x0000000000000000, 0x4000000040000000, 0x0000000040000000};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+
+    uint64_t expected_z9[] =
+    // pg:                0                   1                   1
+        {0xe9eaebecedeeeff0, 0xc010000000000000, 0xc010000000000000};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+
+    uint64_t expected_z10[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebec00ffeff0, 0xf1f200fff5f600ff, 0x00fffbfcfdfe00ff};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+
+    uint64_t expected_z11[] =
+    // pg:                0                   1                   1
+        {0x0000000000000000, 0x0123456789abcdef, 0x0123456789abcdef};
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_fcpy_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         0,                      1,                      1
+  // For S lanes:         0,          1,          1,          0,          1
+  // For H lanes:   1,    0,    0,    1,    0,    1,    1,    0,    0,    1
+  int pg_in[] = {1, 1, 1, 0, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 1};
+
+  PRegister pg = p7;
+  Initialise(&masm, pg.VnB(), pg_in);
+
+  // These are (mostly) merging operations, so we have to initialise the result
+  // registers for each operation.
+  for (unsigned i = 0; i < kNumberOfZRegisters; i++) {
+    __ Index(ZRegister(i, kBRegSize), 0, -1);
+  }
+
+  // Encodable floating-point forms (FCPY_z_p_i)
+  __ Fcpy(z1.VnH(), pg.Merging(), Float16(1.0));
+  __ Fcpy(z2.VnH(), pg.Merging(), -2.0f);
+  __ Fcpy(z3.VnH(), pg.Merging(), 3.0);
+  __ Fcpy(z4.VnS(), pg.Merging(), Float16(-4.0));
+  __ Fcpy(z5.VnS(), pg.Merging(), 5.0f);
+  __ Fcpy(z6.VnS(), pg.Merging(), 6.0);
+  __ Fcpy(z7.VnD(), pg.Merging(), Float16(7.0));
+  __ Fcpy(z8.VnD(), pg.Merging(), 8.0f);
+  __ Fmov(z9.VnD(), pg.Merging(), -9.0);
+
+  // Unencodable immediates.
+  __ Fcpy(z10.VnS(), pg.Merging(), 0.0);
+  __ Fcpy(z11.VnH(), pg.Merging(), Float16(42.0));
+  __ Fcpy(z12.VnD(), pg.Merging(), RawbitsToDouble(0x7ff0000012340000));  // NaN
+  __ Fcpy(z13.VnH(), pg.Merging(), kFP64NegativeInfinity);
+
+  // Fmov alias.
+  __ Fmov(z14.VnS(), pg.Merging(), 0.0);
+  __ Fmov(z15.VnH(), pg.Merging(), Float16(42.0));
+  __ Fmov(z16.VnD(), pg.Merging(), RawbitsToDouble(0x7ff0000012340000));  // NaN
+  __ Fmov(z17.VnH(), pg.Merging(), kFP64NegativeInfinity);
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    // clang-format off
+
+    // 1.0 as FP16: 0x3c00
+    uint64_t expected_z1[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebec3c00eff0, 0xf1f23c00f5f63c00, 0x3c00fbfcfdfe3c00};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+
+    // -2.0 as FP16: 0xc000
+    uint64_t expected_z2[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebecc000eff0, 0xf1f2c000f5f6c000, 0xc000fbfcfdfec000};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+
+    // 3.0 as FP16: 0x4200
+    uint64_t expected_z3[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebec4200eff0, 0xf1f24200f5f64200, 0x4200fbfcfdfe4200};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+
+    // -4.0 as FP32: 0xc0800000
+    uint64_t expected_z4[] =
+    // pg:        0       0           1       1           0       1
+        {0xe9eaebecedeeeff0, 0xc0800000c0800000, 0xf9fafbfcc0800000};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+
+    // 5.0 as FP32: 0x40a00000
+    uint64_t expected_z5[] =
+    // pg:        0       0           1       1           0       1
+        {0xe9eaebecedeeeff0, 0x40a0000040a00000, 0xf9fafbfc40a00000};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+
+    // 6.0 as FP32: 0x40c00000
+    uint64_t expected_z6[] =
+    // pg:        0       0           1       1           0       1
+        {0xe9eaebecedeeeff0, 0x40c0000040c00000, 0xf9fafbfc40c00000};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+
+    // 7.0 as FP64: 0x401c000000000000
+    uint64_t expected_z7[] =
+    // pg:                0                   1                   1
+        {0xe9eaebecedeeeff0, 0x401c000000000000, 0x401c000000000000};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+
+    // 8.0 as FP64: 0x4020000000000000
+    uint64_t expected_z8[] =
+    // pg:                0                   1                   1
+        {0xe9eaebecedeeeff0, 0x4020000000000000, 0x4020000000000000};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+
+    // -9.0 as FP64: 0xc022000000000000
+    uint64_t expected_z9[] =
+    // pg:                0                   1                   1
+        {0xe9eaebecedeeeff0, 0xc022000000000000, 0xc022000000000000};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+
+    // 0.0 as FP32: 0x00000000
+    uint64_t expected_z10[] =
+    // pg:        0       0           1       1           0       1
+        {0xe9eaebecedeeeff0, 0x0000000000000000, 0xf9fafbfc00000000};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+
+    // 42.0 as FP16: 0x5140
+    uint64_t expected_z11[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebec5140eff0, 0xf1f25140f5f65140, 0x5140fbfcfdfe5140};
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+
+    // Signalling NaN (with payload): 0x7ff0000012340000
+    uint64_t expected_z12[] =
+    // pg:                0                   1                   1
+        {0xe9eaebecedeeeff0, 0x7ff0000012340000, 0x7ff0000012340000};
+    ASSERT_EQUAL_SVE(expected_z12, z12.VnD());
+
+    // -infinity as FP16: 0xfc00
+    uint64_t expected_z13[] =
+    // pg:    0   0   1   0       0   1   0   1       1   0   0   1
+        {0xe9eaebecfc00eff0, 0xf1f2fc00f5f6fc00, 0xfc00fbfcfdfefc00};
+    ASSERT_EQUAL_SVE(expected_z13, z13.VnD());
+
+    ASSERT_EQUAL_SVE(z10.VnD(), z14.VnD());
+    ASSERT_EQUAL_SVE(z11.VnD(), z15.VnD());
+    ASSERT_EQUAL_SVE(z12.VnD(), z16.VnD());
+    ASSERT_EQUAL_SVE(z13.VnD(), z17.VnD());
+    // clang-format on
+  }
+}
+
+TEST_SVE(sve_permute_vector_unpredicated_table_lookup) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t table_inputs[] = {0xffeeddccbbaa9988, 0x7766554433221100};
+
+  int index_b[] = {255, 255, 11, 10, 15, 14, 13, 12, 1, 0, 4, 3, 7, 6, 5, 4};
+
+  int index_h[] = {5, 6, 7, 8, 2, 3, 6, 4};
+
+  int index_s[] = {1, 3, 2, 31, -1};
+
+  int index_d[] = {31, 1};
+
+  // Initialize the register with a value that doesn't existed in the table.
+  __ Dup(z9.VnB(), 0x1f);
+  InsrHelper(&masm, z9.VnD(), table_inputs);
+
+  ZRegister ind_b = z0.WithLaneSize(kBRegSize);
+  ZRegister ind_h = z1.WithLaneSize(kHRegSize);
+  ZRegister ind_s = z2.WithLaneSize(kSRegSize);
+  ZRegister ind_d = z3.WithLaneSize(kDRegSize);
+
+  InsrHelper(&masm, ind_b, index_b);
+  InsrHelper(&masm, ind_h, index_h);
+  InsrHelper(&masm, ind_s, index_s);
+  InsrHelper(&masm, ind_d, index_d);
+
+  __ Tbl(z26.VnB(), z9.VnB(), ind_b);
+
+  __ Tbl(z27.VnH(), z9.VnH(), ind_h);
+
+  __ Tbl(z28.VnS(), z9.VnS(), ind_s);
+
+  __ Tbl(z29.VnD(), z9.VnD(), ind_d);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // clang-format off
+    unsigned z26_expected[] = {0x1f, 0x1f, 0xbb, 0xaa, 0xff, 0xee, 0xdd, 0xcc,
+                               0x11, 0x00, 0x44, 0x33, 0x77, 0x66, 0x55, 0x44};
+
+    unsigned z27_expected[] = {0xbbaa, 0xddcc, 0xffee, 0x1f1f,
+                               0x5544, 0x7766, 0xddcc, 0x9988};
+
+    unsigned z28_expected[] =
+       {0x77665544, 0xffeeddcc, 0xbbaa9988, 0x1f1f1f1f, 0x1f1f1f1f};
+
+    uint64_t z29_expected[] = {0x1f1f1f1f1f1f1f1f, 0xffeeddccbbaa9988};
+    // clang-format on
+
+    unsigned vl = config->sve_vl_in_bits();
+    for (size_t i = 0; i < ArrayLength(index_b); i++) {
+      int lane = static_cast<int>(ArrayLength(index_b) - i - 1);
+      if (!core.HasSVELane(z26.VnB(), lane)) break;
+      uint64_t expected = (vl > (index_b[i] * kBRegSize)) ? z26_expected[i] : 0;
+      ASSERT_EQUAL_SVE_LANE(expected, z26.VnB(), lane);
+    }
+
+    for (size_t i = 0; i < ArrayLength(index_h); i++) {
+      int lane = static_cast<int>(ArrayLength(index_h) - i - 1);
+      if (!core.HasSVELane(z27.VnH(), lane)) break;
+      uint64_t expected = (vl > (index_h[i] * kHRegSize)) ? z27_expected[i] : 0;
+      ASSERT_EQUAL_SVE_LANE(expected, z27.VnH(), lane);
+    }
+
+    for (size_t i = 0; i < ArrayLength(index_s); i++) {
+      int lane = static_cast<int>(ArrayLength(index_s) - i - 1);
+      if (!core.HasSVELane(z28.VnS(), lane)) break;
+      uint64_t expected = (vl > (index_s[i] * kSRegSize)) ? z28_expected[i] : 0;
+      ASSERT_EQUAL_SVE_LANE(expected, z28.VnS(), lane);
+    }
+
+    for (size_t i = 0; i < ArrayLength(index_d); i++) {
+      int lane = static_cast<int>(ArrayLength(index_d) - i - 1);
+      if (!core.HasSVELane(z29.VnD(), lane)) break;
+      uint64_t expected = (vl > (index_d[i] * kDRegSize)) ? z29_expected[i] : 0;
+      ASSERT_EQUAL_SVE_LANE(expected, z29.VnD(), lane);
+    }
+  }
+}
+
+TEST_SVE(ldr_str_z_bi) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+
+  // The immediate can address [-256, 255] times the VL, so allocate enough
+  // space to exceed that in both directions.
+  int data_size = vl * 1024;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indices.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  __ Index(z1.VnB(), 1, 3);
+  __ Index(z2.VnB(), 2, 5);
+  __ Index(z3.VnB(), 3, 7);
+  __ Index(z4.VnB(), 4, 11);
+  __ Index(z5.VnB(), 5, 13);
+  __ Index(z6.VnB(), 6, 2);
+  __ Index(z7.VnB(), 7, 3);
+  __ Index(z8.VnB(), 8, 5);
+  __ Index(z9.VnB(), 9, 7);
+
+  // Encodable cases.
+  __ Str(z1, SVEMemOperand(x0));
+  __ Str(z2, SVEMemOperand(x0, 2, SVE_MUL_VL));
+  __ Str(z3, SVEMemOperand(x0, -3, SVE_MUL_VL));
+  __ Str(z4, SVEMemOperand(x0, 255, SVE_MUL_VL));
+  __ Str(z5, SVEMemOperand(x0, -256, SVE_MUL_VL));
+
+  // Cases that fall back on `CalculateSVEAddress`.
+  __ Str(z6, SVEMemOperand(x0, 6 * vl));
+  __ Str(z7, SVEMemOperand(x0, -7 * vl));
+  __ Str(z8, SVEMemOperand(x0, 314, SVE_MUL_VL));
+  __ Str(z9, SVEMemOperand(x0, -314, SVE_MUL_VL));
+
+  // Corresponding loads.
+  __ Ldr(z11, SVEMemOperand(x0, xzr));  // Test xzr operand.
+  __ Ldr(z12, SVEMemOperand(x0, 2, SVE_MUL_VL));
+  __ Ldr(z13, SVEMemOperand(x0, -3, SVE_MUL_VL));
+  __ Ldr(z14, SVEMemOperand(x0, 255, SVE_MUL_VL));
+  __ Ldr(z15, SVEMemOperand(x0, -256, SVE_MUL_VL));
+
+  __ Ldr(z16, SVEMemOperand(x0, 6 * vl));
+  __ Ldr(z17, SVEMemOperand(x0, -7 * vl));
+  __ Ldr(z18, SVEMemOperand(x0, 314, SVE_MUL_VL));
+  __ Ldr(z19, SVEMemOperand(x0, -314, SVE_MUL_VL));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    for (int i = 0; i < vl; i++) {
+      middle[i] = (1 + (3 * i)) & 0xff;                 // z1
+      middle[(2 * vl) + i] = (2 + (5 * i)) & 0xff;      // z2
+      middle[(-3 * vl) + i] = (3 + (7 * i)) & 0xff;     // z3
+      middle[(255 * vl) + i] = (4 + (11 * i)) & 0xff;   // z4
+      middle[(-256 * vl) + i] = (5 + (13 * i)) & 0xff;  // z5
+      middle[(6 * vl) + i] = (6 + (2 * i)) & 0xff;      // z6
+      middle[(-7 * vl) + i] = (7 + (3 * i)) & 0xff;     // z7
+      middle[(314 * vl) + i] = (8 + (5 * i)) & 0xff;    // z8
+      middle[(-314 * vl) + i] = (9 + (7 * i)) & 0xff;   // z9
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    ASSERT_EQUAL_SVE(z1, z11);
+    ASSERT_EQUAL_SVE(z2, z12);
+    ASSERT_EQUAL_SVE(z3, z13);
+    ASSERT_EQUAL_SVE(z4, z14);
+    ASSERT_EQUAL_SVE(z5, z15);
+    ASSERT_EQUAL_SVE(z6, z16);
+    ASSERT_EQUAL_SVE(z7, z17);
+    ASSERT_EQUAL_SVE(z8, z18);
+    ASSERT_EQUAL_SVE(z9, z19);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+TEST_SVE(ldr_str_p_bi) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+  VIXL_ASSERT((vl % kZRegBitsPerPRegBit) == 0);
+  int pl = vl / kZRegBitsPerPRegBit;
+
+  // The immediate can address [-256, 255] times the PL, so allocate enough
+  // space to exceed that in both directions.
+  int data_size = pl * 1024;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indices.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  uint64_t pattern[4] = {0x1010101011101111,
+                         0x0010111011000101,
+                         0x1001101110010110,
+                         0x1010110101100011};
+  for (int i = 8; i <= 15; i++) {
+    // Initialise p8-p15 with a conveniently-recognisable, non-zero pattern.
+    Initialise(&masm,
+               PRegister(i),
+               pattern[3] * i,
+               pattern[2] * i,
+               pattern[1] * i,
+               pattern[0] * i);
+  }
+
+  // Encodable cases.
+  __ Str(p8, SVEMemOperand(x0));
+  __ Str(p9, SVEMemOperand(x0, 2, SVE_MUL_VL));
+  __ Str(p10, SVEMemOperand(x0, -3, SVE_MUL_VL));
+  __ Str(p11, SVEMemOperand(x0, 255, SVE_MUL_VL));
+
+  // Cases that fall back on `CalculateSVEAddress`.
+  __ Str(p12, SVEMemOperand(x0, 6 * pl));
+  __ Str(p13, SVEMemOperand(x0, -7 * pl));
+  __ Str(p14, SVEMemOperand(x0, 314, SVE_MUL_VL));
+  __ Str(p15, SVEMemOperand(x0, -314, SVE_MUL_VL));
+
+  // Corresponding loads.
+  __ Ldr(p0, SVEMemOperand(x0));
+  __ Ldr(p1, SVEMemOperand(x0, 2, SVE_MUL_VL));
+  __ Ldr(p2, SVEMemOperand(x0, -3, SVE_MUL_VL));
+  __ Ldr(p3, SVEMemOperand(x0, 255, SVE_MUL_VL));
+
+  __ Ldr(p4, SVEMemOperand(x0, 6 * pl));
+  __ Ldr(p5, SVEMemOperand(x0, -7 * pl));
+  __ Ldr(p6, SVEMemOperand(x0, 314, SVE_MUL_VL));
+  __ Ldr(p7, SVEMemOperand(x0, -314, SVE_MUL_VL));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    for (int i = 0; i < pl; i++) {
+      int bit_index = (i % sizeof(pattern[0])) * kBitsPerByte;
+      size_t index = i / sizeof(pattern[0]);
+      VIXL_ASSERT(index < ArrayLength(pattern));
+      uint64_t byte = (pattern[index] >> bit_index) & 0xff;
+      // Each byte of `pattern` can be multiplied by 15 without carry.
+      VIXL_ASSERT((byte * 15) <= 0xff);
+
+      middle[i] = byte * 8;                 // p8
+      middle[(2 * pl) + i] = byte * 9;      // p9
+      middle[(-3 * pl) + i] = byte * 10;    // p10
+      middle[(255 * pl) + i] = byte * 11;   // p11
+      middle[(6 * pl) + i] = byte * 12;     // p12
+      middle[(-7 * pl) + i] = byte * 13;    // p13
+      middle[(314 * pl) + i] = byte * 14;   // p14
+      middle[(-314 * pl) + i] = byte * 15;  // p15
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    ASSERT_EQUAL_SVE(p0, p8);
+    ASSERT_EQUAL_SVE(p1, p9);
+    ASSERT_EQUAL_SVE(p2, p10);
+    ASSERT_EQUAL_SVE(p3, p11);
+    ASSERT_EQUAL_SVE(p4, p12);
+    ASSERT_EQUAL_SVE(p5, p13);
+    ASSERT_EQUAL_SVE(p6, p14);
+    ASSERT_EQUAL_SVE(p7, p15);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+template <typename T>
+static void MemoryWrite(uint8_t* base, int64_t offset, int64_t index, T data) {
+  memcpy(base + offset + (index * sizeof(data)), &data, sizeof(data));
+}
+
+TEST_SVE(sve_ld1_st1_contiguous) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+
+  // The immediate can address [-8, 7] times the VL, so allocate enough space to
+  // exceed that in both directions.
+  int data_size = vl * 128;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indices.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  // Encodable scalar-plus-immediate cases.
+  __ Index(z1.VnB(), 1, -3);
+  __ Ptrue(p1.VnB());
+  __ St1b(z1.VnB(), p1, SVEMemOperand(x0));
+
+  __ Index(z2.VnH(), -2, 5);
+  __ Ptrue(p2.VnH(), SVE_MUL3);
+  __ St1b(z2.VnH(), p2, SVEMemOperand(x0, 7, SVE_MUL_VL));
+
+  __ Index(z3.VnS(), 3, -7);
+  __ Ptrue(p3.VnS(), SVE_POW2);
+  __ St1h(z3.VnS(), p3, SVEMemOperand(x0, -8, SVE_MUL_VL));
+
+  // Encodable scalar-plus-scalar cases.
+  __ Index(z4.VnD(), -4, 11);
+  __ Ptrue(p4.VnD(), SVE_VL3);
+  __ Addvl(x1, x0, 8);  // Try not to overlap with VL-dependent cases.
+  __ Mov(x2, 17);
+  __ St1b(z4.VnD(), p4, SVEMemOperand(x1, x2));
+
+  __ Index(z5.VnD(), 6, -2);
+  __ Ptrue(p5.VnD(), SVE_VL16);
+  __ Addvl(x3, x0, 10);  // Try not to overlap with VL-dependent cases.
+  __ Mov(x4, 6);
+  __ St1d(z5.VnD(), p5, SVEMemOperand(x3, x4, LSL, 3));
+
+  // Unencodable cases fall back on `CalculateSVEAddress`.
+  __ Index(z6.VnS(), -7, 3);
+  // Setting SVE_ALL on B lanes checks that the Simulator ignores irrelevant
+  // predicate bits when handling larger lanes.
+  __ Ptrue(p6.VnB(), SVE_ALL);
+  __ St1w(z6.VnS(), p6, SVEMemOperand(x0, 42, SVE_MUL_VL));
+
+  __ Index(z7.VnD(), 32, -11);
+  __ Ptrue(p7.VnD(), SVE_MUL4);
+  __ St1w(z7.VnD(), p7, SVEMemOperand(x0, 22, SVE_MUL_VL));
+
+  // Corresponding loads.
+  __ Ld1b(z8.VnB(), p1.Zeroing(), SVEMemOperand(x0));
+  __ Ld1b(z9.VnH(), p2.Zeroing(), SVEMemOperand(x0, 7, SVE_MUL_VL));
+  __ Ld1h(z10.VnS(), p3.Zeroing(), SVEMemOperand(x0, -8, SVE_MUL_VL));
+  __ Ld1b(z11.VnD(), p4.Zeroing(), SVEMemOperand(x1, x2));
+  __ Ld1d(z12.VnD(), p5.Zeroing(), SVEMemOperand(x3, x4, LSL, 3));
+  __ Ld1w(z13.VnS(), p6.Zeroing(), SVEMemOperand(x0, 42, SVE_MUL_VL));
+
+  __ Ld1sb(z14.VnH(), p2.Zeroing(), SVEMemOperand(x0, 7, SVE_MUL_VL));
+  __ Ld1sh(z15.VnS(), p3.Zeroing(), SVEMemOperand(x0, -8, SVE_MUL_VL));
+  __ Ld1sb(z16.VnD(), p4.Zeroing(), SVEMemOperand(x1, x2));
+  __ Ld1sw(z17.VnD(), p7.Zeroing(), SVEMemOperand(x0, 22, SVE_MUL_VL));
+
+  // We can test ld1 by comparing the value loaded with the value stored. In
+  // most cases, there are two complications:
+  //  - Loads have zeroing predication, so we have to clear the inactive
+  //    elements on our reference.
+  //  - We have to replicate any sign- or zero-extension.
+
+  // Ld1b(z8.VnB(), ...)
+  __ Dup(z18.VnB(), 0);
+  __ Mov(z18.VnB(), p1.Merging(), z1.VnB());
+
+  // Ld1b(z9.VnH(), ...)
+  __ Dup(z19.VnH(), 0);
+  __ Uxtb(z19.VnH(), p2.Merging(), z2.VnH());
+
+  // Ld1h(z10.VnS(), ...)
+  __ Dup(z20.VnS(), 0);
+  __ Uxth(z20.VnS(), p3.Merging(), z3.VnS());
+
+  // Ld1b(z11.VnD(), ...)
+  __ Dup(z21.VnD(), 0);
+  __ Uxtb(z21.VnD(), p4.Merging(), z4.VnD());
+
+  // Ld1d(z12.VnD(), ...)
+  __ Dup(z22.VnD(), 0);
+  __ Mov(z22.VnD(), p5.Merging(), z5.VnD());
+
+  // Ld1w(z13.VnS(), ...)
+  __ Dup(z23.VnS(), 0);
+  __ Mov(z23.VnS(), p6.Merging(), z6.VnS());
+
+  // Ld1sb(z14.VnH(), ...)
+  __ Dup(z24.VnH(), 0);
+  __ Sxtb(z24.VnH(), p2.Merging(), z2.VnH());
+
+  // Ld1sh(z15.VnS(), ...)
+  __ Dup(z25.VnS(), 0);
+  __ Sxth(z25.VnS(), p3.Merging(), z3.VnS());
+
+  // Ld1sb(z16.VnD(), ...)
+  __ Dup(z26.VnD(), 0);
+  __ Sxtb(z26.VnD(), p4.Merging(), z4.VnD());
+
+  // Ld1sw(z17.VnD(), ...)
+  __ Dup(z27.VnD(), 0);
+  __ Sxtw(z27.VnD(), p7.Merging(), z7.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    int vl_b = vl / kBRegSizeInBytes;
+    int vl_h = vl / kHRegSizeInBytes;
+    int vl_s = vl / kSRegSizeInBytes;
+    int vl_d = vl / kDRegSizeInBytes;
+
+    // Encodable cases.
+
+    // st1b { z1.b }, SVE_ALL
+    for (int i = 0; i < vl_b; i++) {
+      MemoryWrite(middle, 0, i, static_cast<uint8_t>(1 - (3 * i)));
+    }
+
+    // st1b { z2.h }, SVE_MUL3
+    int vl_h_mul3 = vl_h - (vl_h % 3);
+    for (int i = 0; i < vl_h_mul3; i++) {
+      int64_t offset = 7 * static_cast<int>(vl / (kHRegSize / kBRegSize));
+      MemoryWrite(middle, offset, i, static_cast<uint8_t>(-2 + (5 * i)));
+    }
+
+    // st1h { z3.s }, SVE_POW2
+    int vl_s_pow2 = 1 << HighestSetBitPosition(vl_s);
+    for (int i = 0; i < vl_s_pow2; i++) {
+      int64_t offset = -8 * static_cast<int>(vl / (kSRegSize / kHRegSize));
+      MemoryWrite(middle, offset, i, static_cast<uint16_t>(3 - (7 * i)));
+    }
+
+    // st1b { z4.d }, SVE_VL3
+    if (vl_d >= 3) {
+      for (int i = 0; i < 3; i++) {
+        MemoryWrite(middle,
+                    (8 * vl) + 17,
+                    i,
+                    static_cast<uint8_t>(-4 + (11 * i)));
+      }
+    }
+
+    // st1d { z5.d }, SVE_VL16
+    if (vl_d >= 16) {
+      for (int i = 0; i < 16; i++) {
+        MemoryWrite(middle,
+                    (10 * vl) + (6 * kDRegSizeInBytes),
+                    i,
+                    static_cast<uint64_t>(6 - (2 * i)));
+      }
+    }
+
+    // Unencodable cases.
+
+    // st1w { z6.s }, SVE_ALL
+    for (int i = 0; i < vl_s; i++) {
+      MemoryWrite(middle, 42 * vl, i, static_cast<uint32_t>(-7 + (3 * i)));
+    }
+
+    // st1w { z7.d }, SVE_MUL4
+    int vl_d_mul4 = vl_d - (vl_d % 4);
+    for (int i = 0; i < vl_d_mul4; i++) {
+      int64_t offset = 22 * static_cast<int>(vl / (kDRegSize / kWRegSize));
+      MemoryWrite(middle, offset, i, static_cast<uint32_t>(32 + (-11 * i)));
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    // Check that we loaded back the expected values.
+
+    ASSERT_EQUAL_SVE(z18, z8);
+    ASSERT_EQUAL_SVE(z19, z9);
+    ASSERT_EQUAL_SVE(z20, z10);
+    ASSERT_EQUAL_SVE(z21, z11);
+    ASSERT_EQUAL_SVE(z22, z12);
+    ASSERT_EQUAL_SVE(z23, z13);
+    ASSERT_EQUAL_SVE(z24, z14);
+    ASSERT_EQUAL_SVE(z25, z15);
+    ASSERT_EQUAL_SVE(z26, z16);
+    ASSERT_EQUAL_SVE(z27, z17);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+TEST_SVE(sve_ld2_st2_scalar_plus_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+
+  // The immediate can address [-16, 14] times the VL, so allocate enough space
+  // to exceed that in both directions.
+  int data_size = vl * 128;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indeces.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  __ Index(z14.VnB(), 1, -3);
+  __ Index(z15.VnB(), 2, -3);
+  __ Ptrue(p0.VnB());
+  __ St2b(z14.VnB(), z15.VnB(), p0, SVEMemOperand(x0));
+
+  __ Index(z16.VnH(), -2, 5);
+  __ Index(z17.VnH(), -3, 5);
+  __ Ptrue(p1.VnH(), SVE_MUL3);
+  __ St2h(z16.VnH(), z17.VnH(), p1, SVEMemOperand(x0, 8, SVE_MUL_VL));
+
+  // Wrap around from z31 to z0.
+  __ Index(z31.VnS(), 3, -7);
+  __ Index(z0.VnS(), 4, -7);
+  __ Ptrue(p2.VnS(), SVE_POW2);
+  __ St2w(z31.VnS(), z0.VnS(), p2, SVEMemOperand(x0, -12, SVE_MUL_VL));
+
+  __ Index(z18.VnD(), -7, 3);
+  __ Index(z19.VnD(), -8, 3);
+  // Sparse predication, including some irrelevant bits (0xe). To make the
+  // results easy to check, activate each lane <n> where n is a multiple of 5.
+  Initialise(&masm,
+             p3,
+             0xeee10000000001ee,
+             0xeeeeeee100000000,
+             0x01eeeeeeeee10000,
+             0x000001eeeeeeeee1);
+  __ St2d(z18.VnD(), z19.VnD(), p3, SVEMemOperand(x0, 14, SVE_MUL_VL));
+
+  // We can test ld2 by comparing the values loaded with the values stored.
+  // There are two complications:
+  //  - Loads have zeroing predication, so we have to clear the inactive
+  //    elements on our reference.
+  //  - We want to test both loads and stores that span { z31, z0 }, so we have
+  //    to move some values around.
+  //
+  // Registers z4-z11 will hold as-stored values (with inactive elements
+  // cleared). Registers z20-z27 will hold the values that were loaded.
+
+  // Ld2b(z14.VnB(), z15.VnB(), ...)
+  __ Dup(z4.VnB(), 0);
+  __ Dup(z5.VnB(), 0);
+  __ Mov(z4.VnB(), p0.Merging(), z14.VnB());
+  __ Mov(z5.VnB(), p0.Merging(), z15.VnB());
+
+  // Ld2h(z16.VnH(), z17.VnH(), ...)
+  __ Dup(z6.VnH(), 0);
+  __ Dup(z7.VnH(), 0);
+  __ Mov(z6.VnH(), p1.Merging(), z16.VnH());
+  __ Mov(z7.VnH(), p1.Merging(), z17.VnH());
+
+  // Ld2w(z31.VnS(), z0.VnS(), ...)
+  __ Dup(z8.VnS(), 0);
+  __ Dup(z9.VnS(), 0);
+  __ Mov(z8.VnS(), p2.Merging(), z31.VnS());
+  __ Mov(z9.VnS(), p2.Merging(), z0.VnS());
+
+  // Ld2d(z18.VnD(), z19.VnD(), ...)
+  __ Dup(z10.VnD(), 0);
+  __ Dup(z11.VnD(), 0);
+  __ Mov(z10.VnD(), p3.Merging(), z18.VnD());
+  __ Mov(z11.VnD(), p3.Merging(), z19.VnD());
+
+  // Wrap around from z31 to z0, moving the results elsewhere to avoid overlap.
+  __ Ld2b(z31.VnB(), z0.VnB(), p0.Zeroing(), SVEMemOperand(x0));
+  __ Mov(z20, z31);
+  __ Mov(z21, z0);
+
+  __ Ld2h(z22.VnH(), z23.VnH(), p1.Zeroing(), SVEMemOperand(x0, 8, SVE_MUL_VL));
+  __ Ld2w(z24.VnS(),
+          z25.VnS(),
+          p2.Zeroing(),
+          SVEMemOperand(x0, -12, SVE_MUL_VL));
+  __ Ld2d(z26.VnD(),
+          z27.VnD(),
+          p3.Zeroing(),
+          SVEMemOperand(x0, 14, SVE_MUL_VL));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    int vl_b = vl / kBRegSizeInBytes;
+    int vl_h = vl / kHRegSizeInBytes;
+    int vl_s = vl / kSRegSizeInBytes;
+    int vl_d = vl / kDRegSizeInBytes;
+
+    int reg_count = 2;
+
+    // st2b { z14.b, z15.b }, SVE_ALL
+    for (int i = 0; i < vl_b; i++) {
+      uint8_t lane0 = 1 - (3 * i);
+      uint8_t lane1 = 2 - (3 * i);
+      MemoryWrite(middle, 0, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, 0, (i * reg_count) + 1, lane1);
+    }
+
+    // st2h { z16.h, z17.h }, SVE_MUL3
+    int vl_h_mul3 = vl_h - (vl_h % 3);
+    for (int i = 0; i < vl_h_mul3; i++) {
+      int64_t offset = 8 * vl;
+      uint16_t lane0 = -2 + (5 * i);
+      uint16_t lane1 = -3 + (5 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+    }
+
+    // st2w { z31.s, z0.s }, SVE_POW2
+    int vl_s_pow2 = 1 << HighestSetBitPosition(vl_s);
+    for (int i = 0; i < vl_s_pow2; i++) {
+      int64_t offset = -12 * vl;
+      uint32_t lane0 = 3 - (7 * i);
+      uint32_t lane1 = 4 - (7 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+    }
+
+    // st2d { z18.d, z19.d }, ((i % 5) == 0)
+    for (int i = 0; i < vl_d; i++) {
+      if ((i % 5) == 0) {
+        int64_t offset = 14 * vl;
+        uint64_t lane0 = -7 + (3 * i);
+        uint64_t lane1 = -8 + (3 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      }
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    // Check that we loaded back the expected values.
+
+    // st2b/ld2b
+    ASSERT_EQUAL_SVE(z4, z20);
+    ASSERT_EQUAL_SVE(z5, z21);
+
+    // st2h/ld2h
+    ASSERT_EQUAL_SVE(z6, z22);
+    ASSERT_EQUAL_SVE(z7, z23);
+
+    // st2w/ld2w
+    ASSERT_EQUAL_SVE(z8, z24);
+    ASSERT_EQUAL_SVE(z9, z25);
+
+    // st2d/ld2d
+    ASSERT_EQUAL_SVE(z10, z26);
+    ASSERT_EQUAL_SVE(z11, z27);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+TEST_SVE(sve_ld2_st2_scalar_plus_scalar) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+
+  // Allocate plenty of space to enable indexing in both directions.
+  int data_size = vl * 128;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indeces.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  __ Index(z10.VnB(), -4, 11);
+  __ Index(z11.VnB(), -5, 11);
+  __ Ptrue(p7.VnB(), SVE_MUL4);
+  __ Mov(x1, 0);
+  __ St2b(z10.VnB(), z11.VnB(), p7, SVEMemOperand(x0, x1));
+
+  __ Index(z12.VnH(), 6, -2);
+  __ Index(z13.VnH(), 7, -2);
+  __ Ptrue(p6.VnH(), SVE_VL16);
+  __ Rdvl(x2, 3);  // Make offsets VL-dependent so we can avoid overlap.
+  __ St2h(z12.VnH(), z13.VnH(), p6, SVEMemOperand(x0, x2, LSL, 1));
+
+  __ Index(z14.VnS(), -7, 3);
+  __ Index(z15.VnS(), -8, 3);
+  // Sparse predication, including some irrelevant bits (0xe). To make the
+  // results easy to check, activate each lane <n> where n is a multiple of 5.
+  Initialise(&masm,
+             p5,
+             0xeee1000010000100,
+             0x001eeee100001000,
+             0x0100001eeee10000,
+             0x10000100001eeee1);
+  __ Rdvl(x3, -3);
+  __ St2w(z14.VnS(), z15.VnS(), p5, SVEMemOperand(x0, x3, LSL, 2));
+
+  // Wrap around from z31 to z0.
+  __ Index(z31.VnD(), 32, -11);
+  __ Index(z0.VnD(), 33, -11);
+  __ Ptrue(p4.VnD(), SVE_MUL3);
+  __ Rdvl(x4, 1);
+  __ St2d(z31.VnD(), z0.VnD(), p4, SVEMemOperand(x0, x4, LSL, 3));
+
+  // We can test ld2 by comparing the values loaded with the values stored.
+  // There are two complications:
+  //  - Loads have zeroing predication, so we have to clear the inactive
+  //    elements on our reference.
+  //  - We want to test both loads and stores that span { z31, z0 }, so we have
+  //    to move some values around.
+  //
+  // Registers z4-z11 will hold as-stored values (with inactive elements
+  // cleared). Registers z20-z27 will hold the values that were loaded.
+
+  // Ld2b(z20.VnB(), z21.VnB(), ...)
+  __ Dup(z4.VnB(), 0);
+  __ Dup(z5.VnB(), 0);
+  __ Mov(z4.VnB(), p7.Merging(), z10.VnB());
+  __ Mov(z5.VnB(), p7.Merging(), z11.VnB());
+
+  // Ld2h(z22.VnH(), z23.VnH(), ...)
+  __ Dup(z6.VnH(), 0);
+  __ Dup(z7.VnH(), 0);
+  __ Mov(z6.VnH(), p6.Merging(), z12.VnH());
+  __ Mov(z7.VnH(), p6.Merging(), z13.VnH());
+
+  // Ld2w(z24.VnS(), z25.VnS(), ...)
+  __ Dup(z8.VnS(), 0);
+  __ Dup(z9.VnS(), 0);
+  __ Mov(z8.VnS(), p5.Merging(), z14.VnS());
+  __ Mov(z9.VnS(), p5.Merging(), z15.VnS());
+
+  // Ld2d(z31.VnD(), z0.VnD(), ...)
+  __ Dup(z10.VnD(), 0);
+  __ Dup(z11.VnD(), 0);
+  __ Mov(z10.VnD(), p4.Merging(), z31.VnD());
+  __ Mov(z11.VnD(), p4.Merging(), z0.VnD());
+
+  // Wrap around from z31 to z0, moving the results elsewhere to avoid overlap.
+  __ Ld2b(z31.VnB(), z0.VnB(), p7.Zeroing(), SVEMemOperand(x0, x1));
+  __ Mov(z20, z31);
+  __ Mov(z21, z0);
+
+  __ Ld2h(z22.VnH(), z23.VnH(), p6.Zeroing(), SVEMemOperand(x0, x2, LSL, 1));
+  __ Ld2w(z24.VnS(), z25.VnS(), p5.Zeroing(), SVEMemOperand(x0, x3, LSL, 2));
+  __ Ld2d(z26.VnD(), z27.VnD(), p4.Zeroing(), SVEMemOperand(x0, x4, LSL, 3));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    int vl_b = vl / kBRegSizeInBytes;
+    int vl_h = vl / kHRegSizeInBytes;
+    int vl_s = vl / kSRegSizeInBytes;
+    int vl_d = vl / kDRegSizeInBytes;
+
+    int reg_count = 2;
+
+    // st2b { z10.b, z11.b }, SVE_MUL4
+    int vl_b_mul4 = vl_b - (vl_b % 4);
+    for (int i = 0; i < vl_b_mul4; i++) {
+      uint8_t lane0 = -4 + (11 * i);
+      uint8_t lane1 = -5 + (11 * i);
+      MemoryWrite(middle, 0, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, 0, (i * reg_count) + 1, lane1);
+    }
+
+    // st2h { z12.h, z13.h }, SVE_VL16
+    if (vl_h >= 16) {
+      for (int i = 0; i < 16; i++) {
+        int64_t offset = (3 << kHRegSizeInBytesLog2) * vl;
+        uint16_t lane0 = 6 - (2 * i);
+        uint16_t lane1 = 7 - (2 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      }
+    }
+
+    // st2w { z14.s, z15.s }, ((i % 5) == 0)
+    for (int i = 0; i < vl_s; i++) {
+      if ((i % 5) == 0) {
+        int64_t offset = -(3 << kSRegSizeInBytesLog2) * vl;
+        uint32_t lane0 = -7 + (3 * i);
+        uint32_t lane1 = -8 + (3 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      }
+    }
+
+    // st2d { z31.b, z0.b }, SVE_MUL3
+    int vl_d_mul3 = vl_d - (vl_d % 3);
+    for (int i = 0; i < vl_d_mul3; i++) {
+      int64_t offset = (1 << kDRegSizeInBytesLog2) * vl;
+      uint64_t lane0 = 32 - (11 * i);
+      uint64_t lane1 = 33 - (11 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    // Check that we loaded back the expected values.
+
+    // st2b/ld2b
+    ASSERT_EQUAL_SVE(z4, z20);
+    ASSERT_EQUAL_SVE(z5, z21);
+
+    // st2h/ld2h
+    ASSERT_EQUAL_SVE(z6, z22);
+    ASSERT_EQUAL_SVE(z7, z23);
+
+    // st2w/ld2w
+    ASSERT_EQUAL_SVE(z8, z24);
+    ASSERT_EQUAL_SVE(z9, z25);
+
+    // st2d/ld2d
+    ASSERT_EQUAL_SVE(z10, z26);
+    ASSERT_EQUAL_SVE(z11, z27);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+TEST_SVE(sve_ld3_st3_scalar_plus_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+
+  // The immediate can address [-24, 21] times the VL, so allocate enough space
+  // to exceed that in both directions.
+  int data_size = vl * 128;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indeces.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  // We can test ld3 by comparing the values loaded with the values stored.
+  // There are two complications:
+  //  - Loads have zeroing predication, so we have to clear the inactive
+  //    elements on our reference.
+  //  - We want to test both loads and stores that span { z31, z0 }, so we have
+  //    to move some values around.
+  //
+  // Registers z4-z15 will hold as-stored values (with inactive elements
+  // cleared). Registers z16-z27 will hold the values that were loaded.
+
+  __ Index(z10.VnB(), 1, -3);
+  __ Index(z11.VnB(), 2, -3);
+  __ Index(z12.VnB(), 3, -3);
+  __ Ptrue(p0.VnB());
+  __ St3b(z10.VnB(), z11.VnB(), z12.VnB(), p0, SVEMemOperand(x0));
+  // Save the stored values for ld3 tests.
+  __ Dup(z4.VnB(), 0);
+  __ Dup(z5.VnB(), 0);
+  __ Dup(z6.VnB(), 0);
+  __ Mov(z4.VnB(), p0.Merging(), z10.VnB());
+  __ Mov(z5.VnB(), p0.Merging(), z11.VnB());
+  __ Mov(z6.VnB(), p0.Merging(), z12.VnB());
+
+  // Wrap around from z31 to z0.
+  __ Index(z31.VnH(), -2, 5);
+  __ Index(z0.VnH(), -3, 5);
+  __ Index(z1.VnH(), -4, 5);
+  __ Ptrue(p1.VnH(), SVE_MUL3);
+  __ St3h(z31.VnH(), z0.VnH(), z1.VnH(), p1, SVEMemOperand(x0, 9, SVE_MUL_VL));
+  // Save the stored values for ld3 tests.
+  __ Dup(z7.VnH(), 0);
+  __ Dup(z8.VnH(), 0);
+  __ Dup(z9.VnH(), 0);
+  __ Mov(z7.VnH(), p1.Merging(), z31.VnH());
+  __ Mov(z8.VnH(), p1.Merging(), z0.VnH());
+  __ Mov(z9.VnH(), p1.Merging(), z1.VnH());
+
+  __ Index(z30.VnS(), 3, -7);
+  __ Index(z31.VnS(), 4, -7);
+  __ Index(z0.VnS(), 5, -7);
+  __ Ptrue(p2.VnS(), SVE_POW2);
+  __ St3w(z30.VnS(),
+          z31.VnS(),
+          z0.VnS(),
+          p2,
+          SVEMemOperand(x0, -12, SVE_MUL_VL));
+  // Save the stored values for ld3 tests.
+  __ Dup(z10.VnS(), 0);
+  __ Dup(z11.VnS(), 0);
+  __ Dup(z12.VnS(), 0);
+  __ Mov(z10.VnS(), p2.Merging(), z30.VnS());
+  __ Mov(z11.VnS(), p2.Merging(), z31.VnS());
+  __ Mov(z12.VnS(), p2.Merging(), z0.VnS());
+
+  __ Index(z0.VnD(), -7, 3);
+  __ Index(z1.VnD(), -8, 3);
+  __ Index(z2.VnD(), -9, 3);
+  // Sparse predication, including some irrelevant bits (0xee). To make the
+  // results easy to check, activate each lane <n> where n is a multiple of 5.
+  Initialise(&masm,
+             p3,
+             0xeee10000000001ee,
+             0xeeeeeee100000000,
+             0x01eeeeeeeee10000,
+             0x000001eeeeeeeee1);
+  __ St3d(z0.VnD(), z1.VnD(), z2.VnD(), p3, SVEMemOperand(x0, 15, SVE_MUL_VL));
+  // Save the stored values for ld3 tests.
+  __ Dup(z13.VnD(), 0);
+  __ Dup(z14.VnD(), 0);
+  __ Dup(z15.VnD(), 0);
+  __ Mov(z13.VnD(), p3.Merging(), z0.VnD());
+  __ Mov(z14.VnD(), p3.Merging(), z1.VnD());
+  __ Mov(z15.VnD(), p3.Merging(), z2.VnD());
+
+  // Corresponding loads.
+  // Wrap around from z31 to z0, moving the results elsewhere to avoid overlap.
+  __ Ld3b(z31.VnB(), z0.VnB(), z1.VnB(), p0.Zeroing(), SVEMemOperand(x0));
+  __ Mov(z16, z31);
+  __ Mov(z17, z0);
+  __ Mov(z18, z1);
+  __ Ld3h(z30.VnH(),
+          z31.VnH(),
+          z0.VnH(),
+          p1.Zeroing(),
+          SVEMemOperand(x0, 9, SVE_MUL_VL));
+  __ Mov(z19, z30);
+  __ Mov(z20, z31);
+  __ Mov(z21, z0);
+  __ Ld3w(z22.VnS(),
+          z23.VnS(),
+          z24.VnS(),
+          p2.Zeroing(),
+          SVEMemOperand(x0, -12, SVE_MUL_VL));
+  __ Ld3d(z25.VnD(),
+          z26.VnD(),
+          z27.VnD(),
+          p3.Zeroing(),
+          SVEMemOperand(x0, 15, SVE_MUL_VL));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    int vl_b = vl / kBRegSizeInBytes;
+    int vl_h = vl / kHRegSizeInBytes;
+    int vl_s = vl / kSRegSizeInBytes;
+    int vl_d = vl / kDRegSizeInBytes;
+
+    int reg_count = 3;
+
+    // st3b { z10.b, z11.b, z12.b }, SVE_ALL
+    for (int i = 0; i < vl_b; i++) {
+      uint8_t lane0 = 1 - (3 * i);
+      uint8_t lane1 = 2 - (3 * i);
+      uint8_t lane2 = 3 - (3 * i);
+      MemoryWrite(middle, 0, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, 0, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, 0, (i * reg_count) + 2, lane2);
+    }
+
+    // st3h { z31.h, z0.h, z1.h }, SVE_MUL3
+    int vl_h_mul3 = vl_h - (vl_h % 3);
+    for (int i = 0; i < vl_h_mul3; i++) {
+      int64_t offset = 9 * vl;
+      uint16_t lane0 = -2 + (5 * i);
+      uint16_t lane1 = -3 + (5 * i);
+      uint16_t lane2 = -4 + (5 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+    }
+
+    // st3w { z30.s, z31.s, z0.s }, SVE_POW2
+    int vl_s_pow2 = 1 << HighestSetBitPosition(vl_s);
+    for (int i = 0; i < vl_s_pow2; i++) {
+      int64_t offset = -12 * vl;
+      uint32_t lane0 = 3 - (7 * i);
+      uint32_t lane1 = 4 - (7 * i);
+      uint32_t lane2 = 5 - (7 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+    }
+
+    // st3d { z0.d, z1.d, z2.d }, ((i % 5) == 0)
+    for (int i = 0; i < vl_d; i++) {
+      if ((i % 5) == 0) {
+        int64_t offset = 15 * vl;
+        uint64_t lane0 = -7 + (3 * i);
+        uint64_t lane1 = -8 + (3 * i);
+        uint64_t lane2 = -9 + (3 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+        MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+      }
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    // Check that we loaded back the expected values.
+
+    // st3b/ld3b
+    ASSERT_EQUAL_SVE(z4, z16);
+    ASSERT_EQUAL_SVE(z5, z17);
+    ASSERT_EQUAL_SVE(z6, z18);
+
+    // st3h/ld3h
+    ASSERT_EQUAL_SVE(z7, z19);
+    ASSERT_EQUAL_SVE(z8, z20);
+    ASSERT_EQUAL_SVE(z9, z21);
+
+    // st3w/ld3w
+    ASSERT_EQUAL_SVE(z10, z22);
+    ASSERT_EQUAL_SVE(z11, z23);
+    ASSERT_EQUAL_SVE(z12, z24);
+
+    // st3d/ld3d
+    ASSERT_EQUAL_SVE(z13, z25);
+    ASSERT_EQUAL_SVE(z14, z26);
+    ASSERT_EQUAL_SVE(z15, z27);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+TEST_SVE(sve_ld3_st3_scalar_plus_scalar) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+
+  // Allocate plenty of space to enable indexing in both directions.
+  int data_size = vl * 128;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indeces.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  // We can test ld3 by comparing the values loaded with the values stored.
+  // There are two complications:
+  //  - Loads have zeroing predication, so we have to clear the inactive
+  //    elements on our reference.
+  //  - We want to test both loads and stores that span { z31, z0 }, so we have
+  //    to move some values around.
+  //
+  // Registers z4-z15 will hold as-stored values (with inactive elements
+  // cleared). Registers z16-z27 will hold the values that were loaded.
+
+  __ Index(z10.VnB(), -4, 11);
+  __ Index(z11.VnB(), -5, 11);
+  __ Index(z12.VnB(), -6, 11);
+  __ Ptrue(p7.VnB(), SVE_MUL4);
+  __ Rdvl(x1, -1);  // Make offsets VL-dependent so we can avoid overlap.
+  __ St3b(z10.VnB(), z11.VnB(), z12.VnB(), p7, SVEMemOperand(x0, x1, LSL, 0));
+  // Save the stored values for ld3 tests.
+  __ Dup(z4.VnB(), 0);
+  __ Dup(z5.VnB(), 0);
+  __ Dup(z6.VnB(), 0);
+  __ Mov(z4.VnB(), p7.Merging(), z10.VnB());
+  __ Mov(z5.VnB(), p7.Merging(), z11.VnB());
+  __ Mov(z6.VnB(), p7.Merging(), z12.VnB());
+
+  __ Index(z13.VnH(), 6, -2);
+  __ Index(z14.VnH(), 7, -2);
+  __ Index(z15.VnH(), 8, -2);
+  __ Ptrue(p6.VnH(), SVE_VL16);
+  __ Rdvl(x2, 5);  // (5 * vl) << 1 = 10 * vl
+  __ St3h(z13.VnH(), z14.VnH(), z15.VnH(), p6, SVEMemOperand(x0, x2, LSL, 1));
+  // Save the stored values for ld3 tests.
+  __ Dup(z7.VnH(), 0);
+  __ Dup(z8.VnH(), 0);
+  __ Dup(z9.VnH(), 0);
+  __ Mov(z7.VnH(), p6.Merging(), z13.VnH());
+  __ Mov(z8.VnH(), p6.Merging(), z14.VnH());
+  __ Mov(z9.VnH(), p6.Merging(), z15.VnH());
+
+  // Wrap around from z31 to z0.
+  __ Index(z30.VnS(), -7, 3);
+  __ Index(z31.VnS(), -8, 3);
+  __ Index(z0.VnS(), -9, 3);
+  // Sparse predication, including some irrelevant bits (0xe). To make the
+  // results easy to check, activate each lane <n> where n is a multiple of 5.
+  Initialise(&masm,
+             p5,
+             0xeee1000010000100,
+             0x001eeee100001000,
+             0x0100001eeee10000,
+             0x10000100001eeee1);
+  __ Rdvl(x3, -5);  // -(5 * vl) << 2 = -20 * vl
+  __ St3w(z30.VnS(), z31.VnS(), z0.VnS(), p5, SVEMemOperand(x0, x3, LSL, 2));
+  // Save the stored values for ld3 tests.
+  __ Dup(z10.VnS(), 0);
+  __ Dup(z11.VnS(), 0);
+  __ Dup(z12.VnS(), 0);
+  __ Mov(z10.VnS(), p5.Merging(), z30.VnS());
+  __ Mov(z11.VnS(), p5.Merging(), z31.VnS());
+  __ Mov(z12.VnS(), p5.Merging(), z0.VnS());
+
+  __ Index(z31.VnD(), 32, -11);
+  __ Index(z0.VnD(), 33, -11);
+  __ Index(z1.VnD(), 34, -11);
+  __ Ptrue(p4.VnD(), SVE_MUL3);
+  __ Rdvl(x4, -1);  // -(1 * vl) << 3 = -8 * vl
+  __ St3d(z31.VnD(), z0.VnD(), z1.VnD(), p4, SVEMemOperand(x0, x4, LSL, 3));
+  // Save the stored values for ld3 tests.
+  __ Dup(z13.VnD(), 0);
+  __ Dup(z14.VnD(), 0);
+  __ Dup(z15.VnD(), 0);
+  __ Mov(z13.VnD(), p4.Merging(), z31.VnD());
+  __ Mov(z14.VnD(), p4.Merging(), z0.VnD());
+  __ Mov(z15.VnD(), p4.Merging(), z1.VnD());
+
+  // Corresponding loads.
+  // Wrap around from z31 to z0, moving the results elsewhere to avoid overlap.
+  __ Ld3b(z31.VnB(),
+          z0.VnB(),
+          z1.VnB(),
+          p7.Zeroing(),
+          SVEMemOperand(x0, x1, LSL, 0));
+  __ Mov(z16, z31);
+  __ Mov(z17, z0);
+  __ Mov(z18, z1);
+  __ Ld3h(z30.VnH(),
+          z31.VnH(),
+          z0.VnH(),
+          p6.Zeroing(),
+          SVEMemOperand(x0, x2, LSL, 1));
+  __ Mov(z19, z30);
+  __ Mov(z20, z31);
+  __ Mov(z21, z0);
+  __ Ld3w(z22.VnS(),
+          z23.VnS(),
+          z24.VnS(),
+          p5.Zeroing(),
+          SVEMemOperand(x0, x3, LSL, 2));
+  __ Ld3d(z25.VnD(),
+          z26.VnD(),
+          z27.VnD(),
+          p4.Zeroing(),
+          SVEMemOperand(x0, x4, LSL, 3));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    int vl_b = vl / kBRegSizeInBytes;
+    int vl_h = vl / kHRegSizeInBytes;
+    int vl_s = vl / kSRegSizeInBytes;
+    int vl_d = vl / kDRegSizeInBytes;
+
+    int reg_count = 3;
+
+    // st3b { z10.b, z11.b, z12.b }, SVE_MUL4
+    int vl_b_mul4 = vl_b - (vl_b % 4);
+    for (int i = 0; i < vl_b_mul4; i++) {
+      int64_t offset = -(1 << kBRegSizeInBytesLog2) * vl;
+      uint8_t lane0 = -4 + (11 * i);
+      uint8_t lane1 = -5 + (11 * i);
+      uint8_t lane2 = -6 + (11 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+    }
+
+    // st3h { z13.h, z14.h, z15.h }, SVE_VL16
+    if (vl_h >= 16) {
+      for (int i = 0; i < 16; i++) {
+        int64_t offset = (5 << kHRegSizeInBytesLog2) * vl;
+        uint16_t lane0 = 6 - (2 * i);
+        uint16_t lane1 = 7 - (2 * i);
+        uint16_t lane2 = 8 - (2 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+        MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+      }
+    }
+
+    // st3w { z30.s, z31.s, z0.s }, ((i % 5) == 0)
+    for (int i = 0; i < vl_s; i++) {
+      if ((i % 5) == 0) {
+        int64_t offset = -(5 << kSRegSizeInBytesLog2) * vl;
+        uint32_t lane0 = -7 + (3 * i);
+        uint32_t lane1 = -8 + (3 * i);
+        uint32_t lane2 = -9 + (3 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+        MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+      }
+    }
+
+    // st3d { z31.d, z0.d, z1.d }, SVE_MUL3
+    int vl_d_mul3 = vl_d - (vl_d % 3);
+    for (int i = 0; i < vl_d_mul3; i++) {
+      int64_t offset = -(1 << kDRegSizeInBytesLog2) * vl;
+      uint64_t lane0 = 32 - (11 * i);
+      uint64_t lane1 = 33 - (11 * i);
+      uint64_t lane2 = 34 - (11 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    // Check that we loaded back the expected values.
+
+    // st3b/ld3b
+    ASSERT_EQUAL_SVE(z4, z16);
+    ASSERT_EQUAL_SVE(z5, z17);
+    ASSERT_EQUAL_SVE(z6, z18);
+
+    // st3h/ld3h
+    ASSERT_EQUAL_SVE(z7, z19);
+    ASSERT_EQUAL_SVE(z8, z20);
+    ASSERT_EQUAL_SVE(z9, z21);
+
+    // st3w/ld3w
+    ASSERT_EQUAL_SVE(z10, z22);
+    ASSERT_EQUAL_SVE(z11, z23);
+    ASSERT_EQUAL_SVE(z12, z24);
+
+    // st3d/ld3d
+    ASSERT_EQUAL_SVE(z13, z25);
+    ASSERT_EQUAL_SVE(z14, z26);
+    ASSERT_EQUAL_SVE(z15, z27);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+TEST_SVE(sve_ld4_st4_scalar_plus_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+
+  // The immediate can address [-24, 21] times the VL, so allocate enough space
+  // to exceed that in both directions.
+  int data_size = vl * 128;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indeces.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  // We can test ld4 by comparing the values loaded with the values stored.
+  // There are two complications:
+  //  - Loads have zeroing predication, so we have to clear the inactive
+  //    elements on our reference.
+  //  - We want to test both loads and stores that span { z31, z0 }, so we have
+  //    to move some values around.
+  //
+  // Registers z3-z18 will hold as-stored values (with inactive elements
+  // cleared). Registers z19-z31 and z0-z2 will hold the values that were
+  // loaded.
+
+  __ Index(z10.VnB(), 1, -7);
+  __ Index(z11.VnB(), 2, -7);
+  __ Index(z12.VnB(), 3, -7);
+  __ Index(z13.VnB(), 4, -7);
+  __ Ptrue(p0.VnB());
+  __ St4b(z10.VnB(), z11.VnB(), z12.VnB(), z13.VnB(), p0, SVEMemOperand(x0));
+  // Save the stored values for ld4 tests.
+  __ Dup(z3.VnB(), 0);
+  __ Dup(z4.VnB(), 0);
+  __ Dup(z5.VnB(), 0);
+  __ Dup(z6.VnB(), 0);
+  __ Mov(z3.VnB(), p0.Merging(), z10.VnB());
+  __ Mov(z4.VnB(), p0.Merging(), z11.VnB());
+  __ Mov(z5.VnB(), p0.Merging(), z12.VnB());
+  __ Mov(z6.VnB(), p0.Merging(), z13.VnB());
+
+  // Wrap around from z31 to z0.
+  __ Index(z31.VnH(), -2, 5);
+  __ Index(z0.VnH(), -3, 5);
+  __ Index(z1.VnH(), -4, 5);
+  __ Index(z2.VnH(), -5, 5);
+  __ Ptrue(p1.VnH(), SVE_MUL3);
+  __ St4h(z31.VnH(),
+          z0.VnH(),
+          z1.VnH(),
+          z2.VnH(),
+          p1,
+          SVEMemOperand(x0, 4, SVE_MUL_VL));
+  // Save the stored values for ld4 tests.
+  __ Dup(z7.VnH(), 0);
+  __ Dup(z8.VnH(), 0);
+  __ Dup(z9.VnH(), 0);
+  __ Dup(z10.VnH(), 0);
+  __ Mov(z7.VnH(), p1.Merging(), z31.VnH());
+  __ Mov(z8.VnH(), p1.Merging(), z0.VnH());
+  __ Mov(z9.VnH(), p1.Merging(), z1.VnH());
+  __ Mov(z10.VnH(), p1.Merging(), z2.VnH());
+
+  // Wrap around from z31 to z0.
+  __ Index(z29.VnS(), 2, -7);
+  __ Index(z30.VnS(), 3, -7);
+  __ Index(z31.VnS(), 4, -7);
+  __ Index(z0.VnS(), 5, -7);
+  __ Ptrue(p2.VnS(), SVE_POW2);
+  __ St4w(z29.VnS(),
+          z30.VnS(),
+          z31.VnS(),
+          z0.VnS(),
+          p2,
+          SVEMemOperand(x0, -12, SVE_MUL_VL));
+  // Save the stored values for ld4 tests.
+  __ Dup(z11.VnS(), 0);
+  __ Dup(z12.VnS(), 0);
+  __ Dup(z13.VnS(), 0);
+  __ Dup(z14.VnS(), 0);
+  __ Mov(z11.VnS(), p2.Merging(), z29.VnS());
+  __ Mov(z12.VnS(), p2.Merging(), z30.VnS());
+  __ Mov(z13.VnS(), p2.Merging(), z31.VnS());
+  __ Mov(z14.VnS(), p2.Merging(), z0.VnS());
+
+  __ Index(z20.VnD(), -7, 8);
+  __ Index(z21.VnD(), -8, 8);
+  __ Index(z22.VnD(), -9, 8);
+  __ Index(z23.VnD(), -10, 8);
+  // Sparse predication, including some irrelevant bits (0xee). To make the
+  // results easy to check, activate each lane <n> where n is a multiple of 5.
+  Initialise(&masm,
+             p3,
+             0xeee10000000001ee,
+             0xeeeeeee100000000,
+             0x01eeeeeeeee10000,
+             0x000001eeeeeeeee1);
+  __ St4d(z20.VnD(),
+          z21.VnD(),
+          z22.VnD(),
+          z23.VnD(),
+          p3,
+          SVEMemOperand(x0, 16, SVE_MUL_VL));
+  // Save the stored values for ld4 tests.
+  __ Dup(z15.VnD(), 0);
+  __ Dup(z16.VnD(), 0);
+  __ Dup(z17.VnD(), 0);
+  __ Dup(z18.VnD(), 0);
+  __ Mov(z15.VnD(), p3.Merging(), z20.VnD());
+  __ Mov(z16.VnD(), p3.Merging(), z21.VnD());
+  __ Mov(z17.VnD(), p3.Merging(), z22.VnD());
+  __ Mov(z18.VnD(), p3.Merging(), z23.VnD());
+
+  // Corresponding loads.
+  // Wrap around from z31 to z0, moving the results elsewhere to avoid overlap.
+  __ Ld4b(z31.VnB(),
+          z0.VnB(),
+          z1.VnB(),
+          z2.VnB(),
+          p0.Zeroing(),
+          SVEMemOperand(x0));
+  __ Mov(z19, z31);
+  __ Mov(z20, z0);
+  __ Mov(z21, z1);
+  __ Mov(z22, z2);
+  __ Ld4h(z23.VnH(),
+          z24.VnH(),
+          z25.VnH(),
+          z26.VnH(),
+          p1.Zeroing(),
+          SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ Ld4w(z27.VnS(),
+          z28.VnS(),
+          z29.VnS(),
+          z30.VnS(),
+          p2.Zeroing(),
+          SVEMemOperand(x0, -12, SVE_MUL_VL));
+  // Wrap around from z31 to z0.
+  __ Ld4d(z31.VnD(),
+          z0.VnD(),
+          z1.VnD(),
+          z2.VnD(),
+          p3.Zeroing(),
+          SVEMemOperand(x0, 16, SVE_MUL_VL));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    int vl_b = vl / kBRegSizeInBytes;
+    int vl_h = vl / kHRegSizeInBytes;
+    int vl_s = vl / kSRegSizeInBytes;
+    int vl_d = vl / kDRegSizeInBytes;
+
+    int reg_count = 4;
+
+    // st2b { z10.b, z11.b, z12.b, z13.b }, SVE_ALL
+    for (int i = 0; i < vl_b; i++) {
+      uint8_t lane0 = 1 - (7 * i);
+      uint8_t lane1 = 2 - (7 * i);
+      uint8_t lane2 = 3 - (7 * i);
+      uint8_t lane3 = 4 - (7 * i);
+      MemoryWrite(middle, 0, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, 0, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, 0, (i * reg_count) + 2, lane2);
+      MemoryWrite(middle, 0, (i * reg_count) + 3, lane3);
+    }
+
+    // st4h { z31.h, z0.h, z1.h, z2.h }, SVE_MUL3
+    int vl_h_mul3 = vl_h - (vl_h % 3);
+    for (int i = 0; i < vl_h_mul3; i++) {
+      int64_t offset = 4 * vl;
+      uint16_t lane0 = -2 + (5 * i);
+      uint16_t lane1 = -3 + (5 * i);
+      uint16_t lane2 = -4 + (5 * i);
+      uint16_t lane3 = -5 + (5 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+      MemoryWrite(middle, offset, (i * reg_count) + 3, lane3);
+    }
+
+    // st4w { z29.s, z30.s, z31.s, z0.s }, SVE_POW2
+    int vl_s_pow2 = 1 << HighestSetBitPosition(vl_s);
+    for (int i = 0; i < vl_s_pow2; i++) {
+      int64_t offset = -12 * vl;
+      uint32_t lane0 = 2 - (7 * i);
+      uint32_t lane1 = 3 - (7 * i);
+      uint32_t lane2 = 4 - (7 * i);
+      uint32_t lane3 = 5 - (7 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+      MemoryWrite(middle, offset, (i * reg_count) + 3, lane3);
+    }
+
+    // st4d { z20.d, z21.d, z22.d, z23.d }, ((i % 5) == 0)
+    for (int i = 0; i < vl_d; i++) {
+      if ((i % 5) == 0) {
+        int64_t offset = 16 * vl;
+        uint64_t lane0 = -7 + (8 * i);
+        uint64_t lane1 = -8 + (8 * i);
+        uint64_t lane2 = -9 + (8 * i);
+        uint64_t lane3 = -10 + (8 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+        MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+        MemoryWrite(middle, offset, (i * reg_count) + 3, lane3);
+      }
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    // Check that we loaded back the expected values.
+
+    // st4b/ld4b
+    ASSERT_EQUAL_SVE(z3, z19);
+    ASSERT_EQUAL_SVE(z4, z20);
+    ASSERT_EQUAL_SVE(z5, z21);
+    ASSERT_EQUAL_SVE(z6, z22);
+
+    // st4h/ld4h
+    ASSERT_EQUAL_SVE(z7, z23);
+    ASSERT_EQUAL_SVE(z8, z24);
+    ASSERT_EQUAL_SVE(z9, z25);
+    ASSERT_EQUAL_SVE(z10, z26);
+
+    // st4w/ld4w
+    ASSERT_EQUAL_SVE(z11, z27);
+    ASSERT_EQUAL_SVE(z12, z28);
+    ASSERT_EQUAL_SVE(z13, z29);
+    ASSERT_EQUAL_SVE(z14, z30);
+
+    // st4d/ld4d
+    ASSERT_EQUAL_SVE(z15, z31);
+    ASSERT_EQUAL_SVE(z16, z0);
+    ASSERT_EQUAL_SVE(z17, z1);
+    ASSERT_EQUAL_SVE(z18, z2);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+TEST_SVE(sve_ld4_st4_scalar_plus_scalar) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+
+  // Allocate plenty of space to enable indexing in both directions.
+  int data_size = vl * 128;
+
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+
+  // Set the base half-way through the buffer so we can use negative indeces.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  // We can test ld4 by comparing the values loaded with the values stored.
+  // There are two complications:
+  //  - Loads have zeroing predication, so we have to clear the inactive
+  //    elements on our reference.
+  //  - We want to test both loads and stores that span { z31, z0 }, so we have
+  //    to move some values around.
+  //
+  // Registers z3-z18 will hold as-stored values (with inactive elements
+  // cleared). Registers z19-z31 and z0-z2 will hold the values that were
+  // loaded.
+
+  __ Index(z19.VnB(), -4, 11);
+  __ Index(z20.VnB(), -5, 11);
+  __ Index(z21.VnB(), -6, 11);
+  __ Index(z22.VnB(), -7, 11);
+  __ Ptrue(p7.VnB(), SVE_MUL4);
+  __ Rdvl(x1, -1);  // Make offsets VL-dependent so we can avoid overlap.
+  __ St4b(z19.VnB(),
+          z20.VnB(),
+          z21.VnB(),
+          z22.VnB(),
+          p7,
+          SVEMemOperand(x0, x1, LSL, 0));
+  // Save the stored values for ld4 tests.
+  __ Dup(z3.VnB(), 0);
+  __ Dup(z4.VnB(), 0);
+  __ Dup(z5.VnB(), 0);
+  __ Dup(z6.VnB(), 0);
+  __ Mov(z3.VnB(), p7.Merging(), z19.VnB());
+  __ Mov(z4.VnB(), p7.Merging(), z20.VnB());
+  __ Mov(z5.VnB(), p7.Merging(), z21.VnB());
+  __ Mov(z6.VnB(), p7.Merging(), z22.VnB());
+
+  __ Index(z23.VnH(), 6, -2);
+  __ Index(z24.VnH(), 7, -2);
+  __ Index(z25.VnH(), 8, -2);
+  __ Index(z26.VnH(), 9, -2);
+  __ Ptrue(p6.VnH(), SVE_VL16);
+  __ Rdvl(x2, 7);  // (7 * vl) << 1 = 14 * vl
+  __ St4h(z23.VnH(),
+          z24.VnH(),
+          z25.VnH(),
+          z26.VnH(),
+          p6,
+          SVEMemOperand(x0, x2, LSL, 1));
+  // Save the stored values for ld4 tests.
+  __ Dup(z7.VnH(), 0);
+  __ Dup(z8.VnH(), 0);
+  __ Dup(z9.VnH(), 0);
+  __ Dup(z10.VnH(), 0);
+  __ Mov(z7.VnH(), p6.Merging(), z23.VnH());
+  __ Mov(z8.VnH(), p6.Merging(), z24.VnH());
+  __ Mov(z9.VnH(), p6.Merging(), z25.VnH());
+  __ Mov(z10.VnH(), p6.Merging(), z26.VnH());
+
+  // Wrap around from z31 to z0.
+  __ Index(z29.VnS(), -6, 7);
+  __ Index(z30.VnS(), -7, 7);
+  __ Index(z31.VnS(), -8, 7);
+  __ Index(z0.VnS(), -9, 7);
+  // Sparse predication, including some irrelevant bits (0xe). To make the
+  // results easy to check, activate each lane <n> where n is a multiple of 5.
+  Initialise(&masm,
+             p5,
+             0xeee1000010000100,
+             0x001eeee100001000,
+             0x0100001eeee10000,
+             0x10000100001eeee1);
+  __ Rdvl(x3, -5);  // -(5 * vl) << 2 = -20 * vl
+  __ St4w(z29.VnS(),
+          z30.VnS(),
+          z31.VnS(),
+          z0.VnS(),
+          p5,
+          SVEMemOperand(x0, x3, LSL, 2));
+  // Save the stored values for ld4 tests.
+  __ Dup(z11.VnS(), 0);
+  __ Dup(z12.VnS(), 0);
+  __ Dup(z13.VnS(), 0);
+  __ Dup(z14.VnS(), 0);
+  __ Mov(z11.VnS(), p5.Merging(), z29.VnS());
+  __ Mov(z12.VnS(), p5.Merging(), z30.VnS());
+  __ Mov(z13.VnS(), p5.Merging(), z31.VnS());
+  __ Mov(z14.VnS(), p5.Merging(), z0.VnS());
+
+  __ Index(z31.VnD(), 32, -11);
+  __ Index(z0.VnD(), 33, -11);
+  __ Index(z1.VnD(), 34, -11);
+  __ Index(z2.VnD(), 35, -11);
+  __ Ptrue(p4.VnD(), SVE_MUL3);
+  __ Rdvl(x4, -1);  // -(1 * vl) << 3 = -8 *vl
+  __ St4d(z31.VnD(),
+          z0.VnD(),
+          z1.VnD(),
+          z2.VnD(),
+          p4,
+          SVEMemOperand(x0, x4, LSL, 3));
+  // Save the stored values for ld4 tests.
+  __ Dup(z15.VnD(), 0);
+  __ Dup(z16.VnD(), 0);
+  __ Dup(z17.VnD(), 0);
+  __ Dup(z18.VnD(), 0);
+  __ Mov(z15.VnD(), p4.Merging(), z31.VnD());
+  __ Mov(z16.VnD(), p4.Merging(), z0.VnD());
+  __ Mov(z17.VnD(), p4.Merging(), z1.VnD());
+  __ Mov(z18.VnD(), p4.Merging(), z2.VnD());
+
+  // Corresponding loads.
+  // Wrap around from z31 to z0, moving the results elsewhere to avoid overlap.
+  __ Ld4b(z31.VnB(),
+          z0.VnB(),
+          z1.VnB(),
+          z2.VnB(),
+          p7.Zeroing(),
+          SVEMemOperand(x0, x1, LSL, 0));
+  __ Mov(z19, z31);
+  __ Mov(z20, z0);
+  __ Mov(z21, z1);
+  __ Mov(z22, z2);
+  __ Ld4h(z23.VnH(),
+          z24.VnH(),
+          z25.VnH(),
+          z26.VnH(),
+          p6.Zeroing(),
+          SVEMemOperand(x0, x2, LSL, 1));
+  __ Ld4w(z27.VnS(),
+          z28.VnS(),
+          z29.VnS(),
+          z30.VnS(),
+          p5.Zeroing(),
+          SVEMemOperand(x0, x3, LSL, 2));
+  // Wrap around from z31 to z0.
+  __ Ld4d(z31.VnD(),
+          z0.VnD(),
+          z1.VnD(),
+          z2.VnD(),
+          p4.Zeroing(),
+          SVEMemOperand(x0, x4, LSL, 3));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint8_t* expected = new uint8_t[data_size];
+    memset(expected, 0, data_size);
+    uint8_t* middle = &expected[data_size / 2];
+
+    int vl_b = vl / kBRegSizeInBytes;
+    int vl_h = vl / kHRegSizeInBytes;
+    int vl_s = vl / kSRegSizeInBytes;
+    int vl_d = vl / kDRegSizeInBytes;
+
+    int reg_count = 4;
+
+    // st4b { z19.b, z20.b, z21.b, z22.b }, SVE_MUL4
+    int vl_b_mul4 = vl_b - (vl_b % 4);
+    for (int i = 0; i < vl_b_mul4; i++) {
+      int64_t offset = -(1 << kBRegSizeInBytesLog2) * vl;
+      uint8_t lane0 = -4 + (11 * i);
+      uint8_t lane1 = -5 + (11 * i);
+      uint8_t lane2 = -6 + (11 * i);
+      uint8_t lane3 = -7 + (11 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+      MemoryWrite(middle, offset, (i * reg_count) + 3, lane3);
+    }
+
+    // st4h { z22.h, z23.h, z24.h, z25.h }, SVE_VL16
+    if (vl_h >= 16) {
+      for (int i = 0; i < 16; i++) {
+        int64_t offset = (7 << kHRegSizeInBytesLog2) * vl;
+        uint16_t lane0 = 6 - (2 * i);
+        uint16_t lane1 = 7 - (2 * i);
+        uint16_t lane2 = 8 - (2 * i);
+        uint16_t lane3 = 9 - (2 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+        MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+        MemoryWrite(middle, offset, (i * reg_count) + 3, lane3);
+      }
+    }
+
+    // st4w { z29.s, z30.s, z31.s, z0.s }, ((i % 5) == 0)
+    for (int i = 0; i < vl_s; i++) {
+      if ((i % 5) == 0) {
+        int64_t offset = -(5 << kSRegSizeInBytesLog2) * vl;
+        uint32_t lane0 = -6 + (7 * i);
+        uint32_t lane1 = -7 + (7 * i);
+        uint32_t lane2 = -8 + (7 * i);
+        uint32_t lane3 = -9 + (7 * i);
+        MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+        MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+        MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+        MemoryWrite(middle, offset, (i * reg_count) + 3, lane3);
+      }
+    }
+
+    // st4d { z31.d, z0.d, z1.d, z2.d }, SVE_MUL3
+    int vl_d_mul3 = vl_d - (vl_d % 3);
+    for (int i = 0; i < vl_d_mul3; i++) {
+      int64_t offset = -(1 << kDRegSizeInBytesLog2) * vl;
+      uint64_t lane0 = 32 - (11 * i);
+      uint64_t lane1 = 33 - (11 * i);
+      uint64_t lane2 = 34 - (11 * i);
+      uint64_t lane3 = 35 - (11 * i);
+      MemoryWrite(middle, offset, (i * reg_count) + 0, lane0);
+      MemoryWrite(middle, offset, (i * reg_count) + 1, lane1);
+      MemoryWrite(middle, offset, (i * reg_count) + 2, lane2);
+      MemoryWrite(middle, offset, (i * reg_count) + 3, lane3);
+    }
+
+    ASSERT_EQUAL_MEMORY(expected, data, data_size, middle - expected);
+
+    // Check that we loaded back the expected values.
+
+    // st4b/ld4b
+    ASSERT_EQUAL_SVE(z3, z19);
+    ASSERT_EQUAL_SVE(z4, z20);
+    ASSERT_EQUAL_SVE(z5, z21);
+    ASSERT_EQUAL_SVE(z6, z22);
+
+    // st4h/ld4h
+    ASSERT_EQUAL_SVE(z7, z23);
+    ASSERT_EQUAL_SVE(z8, z24);
+    ASSERT_EQUAL_SVE(z9, z25);
+    ASSERT_EQUAL_SVE(z10, z26);
+
+    // st4w/ld4w
+    ASSERT_EQUAL_SVE(z11, z27);
+    ASSERT_EQUAL_SVE(z12, z28);
+    ASSERT_EQUAL_SVE(z13, z29);
+    ASSERT_EQUAL_SVE(z14, z30);
+
+    // st4d/ld4d
+    ASSERT_EQUAL_SVE(z15, z31);
+    ASSERT_EQUAL_SVE(z16, z0);
+    ASSERT_EQUAL_SVE(z17, z1);
+    ASSERT_EQUAL_SVE(z18, z2);
+
+    delete[] expected;
+  }
+  delete[] data;
+}
+
+TEST_SVE(sve_ld234_st234_scalar_plus_scalar_sp) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Check that the simulator correctly interprets rn == 31 as sp.
+  // The indexing logic is the same regardless so we just check one load and
+  // store of each type.
+
+  // There are no pre- or post-indexing modes, so reserve space first.
+  __ ClaimVL(2 + 3 + 4);
+
+  __ Index(z0.VnB(), 42, 2);
+  __ Index(z1.VnB(), 43, 2);
+  __ Ptrue(p0.VnB(), SVE_VL7);
+  __ Rdvl(x0, 0);
+  __ St2b(z0.VnB(), z1.VnB(), p0, SVEMemOperand(sp, x0));
+
+  __ Index(z4.VnH(), 42, 3);
+  __ Index(z5.VnH(), 43, 3);
+  __ Index(z6.VnH(), 44, 3);
+  __ Ptrue(p1.VnH(), SVE_POW2);
+  __ Rdvl(x1, 2);
+  __ Lsr(x1, x1, 1);
+  __ St3h(z4.VnH(), z5.VnH(), z6.VnH(), p1, SVEMemOperand(sp, x1, LSL, 1));
+
+  __ Index(z8.VnS(), 42, 4);
+  __ Index(z9.VnS(), 43, 4);
+  __ Index(z10.VnS(), 44, 4);
+  __ Index(z11.VnS(), 45, 4);
+  __ Ptrue(p2.VnS());
+  __ Rdvl(x2, 2 + 3);
+  __ Lsr(x2, x2, 2);
+  __ St4w(z8.VnS(),
+          z9.VnS(),
+          z10.VnS(),
+          z11.VnS(),
+          p2,
+          SVEMemOperand(sp, x2, LSL, 2));
+
+  // Corresponding loads.
+  // We have to explicitly zero inactive lanes in the reference values because
+  // loads have zeroing predication.
+  __ Dup(z12.VnB(), 0);
+  __ Dup(z13.VnB(), 0);
+  __ Mov(z12.VnB(), p0.Merging(), z0.VnB());
+  __ Mov(z13.VnB(), p0.Merging(), z1.VnB());
+  __ Ld2b(z0.VnB(), z1.VnB(), p0.Zeroing(), SVEMemOperand(sp, x0));
+
+  __ Dup(z16.VnH(), 0);
+  __ Dup(z17.VnH(), 0);
+  __ Dup(z18.VnH(), 0);
+  __ Mov(z16.VnH(), p1.Merging(), z4.VnH());
+  __ Mov(z17.VnH(), p1.Merging(), z5.VnH());
+  __ Mov(z18.VnH(), p1.Merging(), z6.VnH());
+  __ Ld3h(z4.VnH(),
+          z5.VnH(),
+          z6.VnH(),
+          p1.Zeroing(),
+          SVEMemOperand(sp, x1, LSL, 1));
+
+  __ Dup(z20.VnS(), 0);
+  __ Dup(z21.VnS(), 0);
+  __ Dup(z22.VnS(), 0);
+  __ Dup(z23.VnS(), 0);
+  __ Mov(z20.VnS(), p2.Merging(), z8.VnS());
+  __ Mov(z21.VnS(), p2.Merging(), z9.VnS());
+  __ Mov(z22.VnS(), p2.Merging(), z10.VnS());
+  __ Mov(z23.VnS(), p2.Merging(), z11.VnS());
+  __ Ld4w(z8.VnS(),
+          z9.VnS(),
+          z10.VnS(),
+          z11.VnS(),
+          p2.Zeroing(),
+          SVEMemOperand(sp, x2, LSL, 2));
+
+  __ DropVL(2 + 3 + 4);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // The most likely failure mode is the that simulator reads sp as xzr and
+    // crashes on execution. We already test the address calculations separately
+    // and sp doesn't change this, so just test that we load the values we
+    // stored.
+
+    // st2b/ld2b
+    ASSERT_EQUAL_SVE(z0, z12);
+    ASSERT_EQUAL_SVE(z1, z13);
+
+    // st3h/ld3h
+    ASSERT_EQUAL_SVE(z4, z16);
+    ASSERT_EQUAL_SVE(z5, z17);
+    ASSERT_EQUAL_SVE(z6, z18);
+
+    // st4h/ld4h
+    ASSERT_EQUAL_SVE(z8, z20);
+    ASSERT_EQUAL_SVE(z9, z21);
+    ASSERT_EQUAL_SVE(z10, z22);
+    ASSERT_EQUAL_SVE(z11, z23);
+  }
+}
+
+TEST_SVE(sve_ld234_st234_scalar_plus_imm_sp) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Check that the simulator correctly interprets rn == 31 as sp.
+  // The indexing logic is the same regardless so we just check one load and
+  // store of each type.
+
+  // There are no pre- or post-indexing modes, so reserve space first.
+  // Note that the stores fill in an order that allows each immediate to be a
+  // multiple of the number of registers.
+  __ ClaimVL(4 + 2 + 3);
+
+  __ Index(z0.VnB(), 42, 2);
+  __ Index(z1.VnB(), 43, 2);
+  __ Ptrue(p0.VnB(), SVE_POW2);
+  __ St2b(z0.VnB(), z1.VnB(), p0, SVEMemOperand(sp, 4, SVE_MUL_VL));
+
+  __ Index(z4.VnH(), 42, 3);
+  __ Index(z5.VnH(), 43, 3);
+  __ Index(z6.VnH(), 44, 3);
+  __ Ptrue(p1.VnH(), SVE_VL7);
+  __ St3h(z4.VnH(), z5.VnH(), z6.VnH(), p1, SVEMemOperand(sp, 6, SVE_MUL_VL));
+
+  __ Index(z8.VnS(), 42, 4);
+  __ Index(z9.VnS(), 43, 4);
+  __ Index(z10.VnS(), 44, 4);
+  __ Index(z11.VnS(), 45, 4);
+  __ Ptrue(p2.VnS());
+  __ St4w(z8.VnS(), z9.VnS(), z10.VnS(), z11.VnS(), p2, SVEMemOperand(sp));
+
+  // Corresponding loads.
+  // We have to explicitly zero inactive lanes in the reference values because
+  // loads have zeroing predication.
+  __ Dup(z12.VnB(), 0);
+  __ Dup(z13.VnB(), 0);
+  __ Mov(z12.VnB(), p0.Merging(), z0.VnB());
+  __ Mov(z13.VnB(), p0.Merging(), z1.VnB());
+  __ Ld2b(z0.VnB(), z1.VnB(), p0.Zeroing(), SVEMemOperand(sp, 4, SVE_MUL_VL));
+
+  __ Dup(z16.VnH(), 0);
+  __ Dup(z17.VnH(), 0);
+  __ Dup(z18.VnH(), 0);
+  __ Mov(z16.VnH(), p1.Merging(), z4.VnH());
+  __ Mov(z17.VnH(), p1.Merging(), z5.VnH());
+  __ Mov(z18.VnH(), p1.Merging(), z6.VnH());
+  __ Ld3h(z4.VnH(),
+          z5.VnH(),
+          z6.VnH(),
+          p1.Zeroing(),
+          SVEMemOperand(sp, 6, SVE_MUL_VL));
+
+  __ Dup(z20.VnS(), 0);
+  __ Dup(z21.VnS(), 0);
+  __ Dup(z22.VnS(), 0);
+  __ Dup(z23.VnS(), 0);
+  __ Mov(z20.VnS(), p2.Merging(), z8.VnS());
+  __ Mov(z21.VnS(), p2.Merging(), z9.VnS());
+  __ Mov(z22.VnS(), p2.Merging(), z10.VnS());
+  __ Mov(z23.VnS(), p2.Merging(), z11.VnS());
+  __ Ld4w(z8.VnS(),
+          z9.VnS(),
+          z10.VnS(),
+          z11.VnS(),
+          p2.Zeroing(),
+          SVEMemOperand(sp));
+
+  __ DropVL(4 + 2 + 3);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // The most likely failure mode is the that simulator reads sp as xzr and
+    // crashes on execution. We already test the address calculations separately
+    // and sp doesn't change this, so just test that we load the values we
+    // stored.
+    // TODO: Actually do this, once loads are implemented.
+  }
+}
+
+// Fill the input buffer with arbitrary data. Meanwhile, assign random offsets
+// from the base address of the buffer and corresponding addresses to the
+// arguments if provided.
+static void BufferFillingHelper(uint64_t data_ptr,
+                                size_t buffer_size,
+                                unsigned lane_size_in_bytes,
+                                int lane_count,
+                                uint64_t* offsets,
+                                uint64_t* addresses = nullptr,
+                                uint64_t* max_address = nullptr) {
+  // Use a fixed seed for nrand48() so that test runs are reproducible.
+  unsigned short seed[3] = {1, 2, 3};  // NOLINT(runtime/int)
+
+  // Fill a buffer with arbitrary data.
+  for (size_t i = 0; i < buffer_size; i++) {
+    uint8_t byte = nrand48(seed) & 0xff;
+    memcpy(reinterpret_cast<void*>(data_ptr + i), &byte, 1);
+  }
+
+  if (max_address != nullptr) {
+    *max_address = 0;
+  }
+
+  // Vectors of random addresses and offsets into the buffer.
+  for (int i = 0; i < lane_count; i++) {
+    uint64_t rnd = nrand48(seed);
+    // Limit the range to the set of completely-accessible elements in memory.
+    offsets[i] = rnd % (buffer_size - lane_size_in_bytes);
+    if ((addresses != nullptr) && (max_address != nullptr)) {
+      addresses[i] = data_ptr + offsets[i];
+      *max_address = std::max(*max_address, addresses[i]);
+    }
+  }
+}
+
+static void ScalarLoadHelper(MacroAssembler* masm,
+                             Register dst,
+                             Register addr,
+                             int msize_in_bits,
+                             bool is_signed) {
+  if (is_signed) {
+    switch (msize_in_bits) {
+      case kBRegSize:
+        masm->Ldrsb(dst, MemOperand(addr));
+        break;
+      case kHRegSize:
+        masm->Ldrsh(dst, MemOperand(addr));
+        break;
+      case kWRegSize:
+        masm->Ldrsw(dst, MemOperand(addr));
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  } else {
+    switch (msize_in_bits) {
+      case kBRegSize:
+        masm->Ldrb(dst, MemOperand(addr));
+        break;
+      case kHRegSize:
+        masm->Ldrh(dst, MemOperand(addr));
+        break;
+      case kWRegSize:
+        masm->Ldr(dst.W(), MemOperand(addr));
+        break;
+      case kXRegSize:
+        masm->Ldr(dst, MemOperand(addr));
+        break;
+      default:
+        VIXL_UNIMPLEMENTED();
+        break;
+    }
+  }
+}
+
+// Generate a reference result using scalar loads.
+// For now this helper doesn't save and restore the caller registers.
+// Clobber register z30, x28, x29 and p7.
+template <size_t N>
+static void ScalarLoadHelper(MacroAssembler* masm,
+                             int vl,
+                             const uint64_t (&addresses)[N],
+                             const ZRegister& zt_ref,
+                             const PRegisterZ& pg,
+                             unsigned esize_in_bits,
+                             unsigned msize_in_bits,
+                             bool is_signed) {
+  unsigned esize_in_bytes = esize_in_bits / kBitsPerByte;
+  ZRegister lane_numbers = z30.WithLaneSize(esize_in_bits);
+  masm->Index(lane_numbers, 0, 1);
+  masm->Dup(zt_ref, 0);
+  for (unsigned i = 0; i < (vl / esize_in_bytes); i++) {
+    masm->Mov(x29, addresses[N - i - 1]);
+    Register rt(28, std::min(std::max(esize_in_bits, kSRegSize), kDRegSize));
+    ScalarLoadHelper(masm, rt, x29, msize_in_bits, is_signed);
+
+    // Emulate predication.
+    masm->Cmpeq(p7.WithLaneSize(esize_in_bits), pg, lane_numbers, i);
+    masm->Cpy(zt_ref, p7.Merging(), rt);
+  }
+}
+
+typedef void (MacroAssembler::*Ld1Macro)(const ZRegister& zt,
+                                         const PRegisterZ& pg,
+                                         const SVEMemOperand& addr);
+
+template <typename T>
+static void Ldff1Helper(Test* config,
+                        uintptr_t data,
+                        unsigned msize_in_bits,
+                        unsigned esize_in_bits,
+                        CPURegister::RegisterType base_type,
+                        Ld1Macro ldff1,
+                        Ld1Macro ld1,
+                        T mod,
+                        bool scale = false) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+  size_t page_size = sysconf(_SC_PAGE_SIZE);
+  VIXL_ASSERT(page_size > static_cast<size_t>(vl));
+
+  unsigned esize_in_bytes = esize_in_bits / kBitsPerByte;
+  unsigned msize_in_bytes = msize_in_bits / kBitsPerByte;
+  unsigned msize_in_bytes_log2 = std::log2(msize_in_bytes);
+  VIXL_ASSERT(msize_in_bits <= esize_in_bits);
+
+  PRegister all = p7;
+  __ Ptrue(all.VnB());
+
+  size_t offset_modifier = 0;
+
+  // The highest address at which a load stopped. Every FF load should fault at
+  // `data + page_size`, so this value should not exceed that value. However,
+  // the architecture allows fault-tolerant loads to fault arbitrarily, so the
+  // real value may be lower.
+  //
+  // This is used to check that the `mprotect` above really does make the second
+  // page inaccessible, and that the resulting FFR from each load reflects that.
+  Register limit = x22;
+  __ Mov(limit, 0);
+
+  // If the FFR grows unexpectedly, we increment this register by the
+  // difference. FFR should never grow, except when explicitly set.
+  Register ffr_grow_count = x23;
+  __ Mov(ffr_grow_count, 0);
+
+  // Set the offset so that the load is guaranteed to start in the
+  // accessible page, but end in the inaccessible one.
+  VIXL_ASSERT((page_size % msize_in_bytes) == 0);
+  VIXL_ASSERT((vl % msize_in_bytes) == 0);
+  size_t elements_per_page = page_size / msize_in_bytes;
+  size_t elements_per_access = vl / esize_in_bytes;
+  size_t min_offset = (elements_per_page - elements_per_access) + 1;
+  size_t max_offset = elements_per_page - 1;
+  size_t offset =
+      min_offset + (offset_modifier % (max_offset - min_offset + 1));
+  offset_modifier++;
+
+  __ Setffr();
+  __ Mov(x20, data);
+  __ Mov(x21, offset);
+
+  if (base_type == CPURegister::kRegister) {
+    // Scalar-plus-scalar mode.
+    VIXL_ASSERT((std::is_same<T, vixl::aarch64::Shift>::value));
+    VIXL_ASSERT((static_cast<int>(mod) == LSL) ||
+                (static_cast<int>(mod) == NO_SHIFT));
+    (masm.*ldff1)(z0.WithLaneSize(esize_in_bits),
+                  all.Zeroing(),
+                  SVEMemOperand(x20, x21, mod, msize_in_bytes_log2));
+  } else {
+    VIXL_ASSERT(base_type == CPURegister::kZRegister);
+    int offs_size;
+    bool offs_is_unsigned;
+    if (std::is_same<T, vixl::aarch64::Extend>::value) {
+      // Scalar-plus-vector mode with 32-bit optional unpacked or upacked, and
+      // unscaled or scaled offset.
+      VIXL_ASSERT((static_cast<int>(mod) == SXTW) ||
+                  (static_cast<int>(mod) == UXTW));
+      if (scale == true) {
+        // Gather first-fault bytes load doesn't support scaled offset.
+        VIXL_ASSERT(msize_in_bits != kBRegSize);
+      }
+      offs_is_unsigned = (static_cast<int>(mod) == UXTW) ? true : false;
+      offs_size = kSRegSize;
+
+    } else {
+      // Scalar-plus-vector mode with 64-bit unscaled or scaled offset.
+      VIXL_ASSERT((std::is_same<T, vixl::aarch64::Shift>::value));
+      VIXL_ASSERT((static_cast<int>(mod) == LSL) ||
+                  (static_cast<int>(mod) == NO_SHIFT));
+      offs_is_unsigned = false;
+      offs_size = kDRegSize;
+    }
+
+    // For generating the pattern of "base address + index << shift".
+    // In case of unscaled-offset operation, use `msize_in_bytes` be an offset
+    // of each decreasing memory accesses. otherwise, decreases the indexes by 1
+    // and then scale it by the shift value.
+    int shift = (scale == true) ? msize_in_bytes_log2 : 0;
+    int index_offset = msize_in_bytes >> shift;
+    VIXL_ASSERT(index_offset > 0);
+    uint64_t index = 0;
+    uint64_t base_address = 0;
+
+    if (offs_is_unsigned == true) {
+      // Base address.
+      base_address = data;
+      // Maximum unsigned positive index.
+      index = page_size >> shift;
+
+    } else {
+      // Base address.
+      base_address = data + (2 * page_size);
+      // Maximum unsigned positive index.
+      uint64_t uint_e_max =
+          (esize_in_bits == kDRegSize) ? UINT64_MAX : UINT32_MAX;
+      index = uint_e_max - (page_size >> shift) + 1;
+    }
+
+    __ Mov(x19, base_address);
+    if ((offs_size == kSRegSize) && (esize_in_bits == kDRegSize)) {
+      // In this case, the index values are optionally sign or zero-extended
+      // from 32 to 64 bits, assign a convenient value to the top 32 bits to
+      // ensure only the low 32 bits be the index values.
+      index |= 0x1234567800000000;
+    }
+
+    index -= index_offset * (elements_per_access - 1);
+    __ Index(z17.WithLaneSize(esize_in_bits), index, index_offset);
+
+    // Scalar plus vector mode.
+    (masm.*
+     ldff1)(z0.WithLaneSize(esize_in_bits),
+            all.Zeroing(),
+            SVEMemOperand(x19, z17.WithLaneSize(esize_in_bits), mod, shift));
+  }
+
+  __ Rdffrs(p0.VnB(), all.Zeroing());
+
+  // Execute another Ldff1 with no offset, so that every element could be
+  // read. It should respect FFR, and load no more than we loaded the
+  // first time.
+  (masm.*
+   ldff1)(z16.WithLaneSize(esize_in_bits), all.Zeroing(), SVEMemOperand(x20));
+  __ Rdffrs(p1.VnB(), all.Zeroing());
+  __ Cntp(x0, all, p1.VnB());
+  __ Uqdecp(x0, p0.VnB());
+  __ Add(ffr_grow_count, ffr_grow_count, x0);
+
+  // Use the FFR to predicate the normal load. If it wasn't properly set,
+  // the normal load will abort.
+  (masm.*ld1)(z16.WithLaneSize(esize_in_bits),
+              p0.Zeroing(),
+              SVEMemOperand(x20, x21, LSL, msize_in_bytes_log2));
+
+  // Work out the address after the one that was just accessed.
+  __ Incp(x21, p0.WithLaneSize(esize_in_bits));
+  __ Add(x0, x20, Operand(x21, LSL, msize_in_bytes_log2));
+  __ Cmp(limit, x0);
+  __ Csel(limit, limit, x0, hs);
+
+  // Clear lanes inactive in FFR. These have an undefined result.
+  __ Not(p0.VnB(), all.Zeroing(), p0.VnB());
+  __ Mov(z0.WithLaneSize(esize_in_bits), p0.Merging(), 0);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uintptr_t expected_limit = data + page_size;
+    uintptr_t measured_limit = core.xreg(limit.GetCode());
+    VIXL_CHECK(measured_limit <= expected_limit);
+    if (measured_limit < expected_limit) {
+      // We can't fail the test for this case, but a warning is helpful for
+      // manually-run tests.
+      printf(
+          "WARNING: All fault-tolerant loads detected faults before the\n"
+          "expected limit. This is architecturally possible, but improbable,\n"
+          "and could be a symptom of another problem.\n");
+    }
+
+    ASSERT_EQUAL_64(0, ffr_grow_count);
+
+    ASSERT_EQUAL_SVE(z0.WithLaneSize(esize_in_bits),
+                     z16.WithLaneSize(esize_in_bits));
+  }
+}
+
+TEST_SVE(sve_ldff1_scalar_plus_scalar) {
+  size_t page_size = sysconf(_SC_PAGE_SIZE);
+  VIXL_ASSERT(page_size > static_cast<size_t>(config->sve_vl_in_bytes()));
+
+  // Allocate two pages, then mprotect the second one to make it inaccessible.
+  uintptr_t data = reinterpret_cast<uintptr_t>(mmap(NULL,
+                                                    page_size * 2,
+                                                    PROT_READ | PROT_WRITE,
+                                                    MAP_PRIVATE | MAP_ANONYMOUS,
+                                                    -1,
+                                                    0));
+  mprotect(reinterpret_cast<void*>(data + page_size), page_size, PROT_NONE);
+
+  // Fill the accessible page with arbitrary data.
+  for (size_t i = 0; i < page_size; i++) {
+    // Reverse bits so we get a mixture of positive and negative values.
+    uint8_t byte = ReverseBits(static_cast<uint8_t>(i));
+    memcpy(reinterpret_cast<void*>(data + i), &byte, 1);
+  }
+
+  auto ldff1_unscaled_offset_helper = std::bind(&Ldff1Helper<Shift>,
+                                                config,
+                                                data,
+                                                std::placeholders::_1,
+                                                std::placeholders::_2,
+                                                CPURegister::kRegister,
+                                                std::placeholders::_3,
+                                                std::placeholders::_4,
+                                                NO_SHIFT,
+                                                false);
+
+  Ld1Macro ldff1b = &MacroAssembler::Ldff1b;
+  Ld1Macro ld1b = &MacroAssembler::Ld1b;
+  ldff1_unscaled_offset_helper(kBRegSize, kBRegSize, ldff1b, ld1b);
+  ldff1_unscaled_offset_helper(kBRegSize, kHRegSize, ldff1b, ld1b);
+  ldff1_unscaled_offset_helper(kBRegSize, kSRegSize, ldff1b, ld1b);
+  ldff1_unscaled_offset_helper(kBRegSize, kDRegSize, ldff1b, ld1b);
+
+  Ld1Macro ldff1sb = &MacroAssembler::Ldff1sb;
+  Ld1Macro ld1sb = &MacroAssembler::Ld1sb;
+  ldff1_unscaled_offset_helper(kBRegSize, kHRegSize, ldff1sb, ld1sb);
+  ldff1_unscaled_offset_helper(kBRegSize, kSRegSize, ldff1sb, ld1sb);
+  ldff1_unscaled_offset_helper(kBRegSize, kDRegSize, ldff1sb, ld1sb);
+
+  auto ldff1_scaled_offset_helper = std::bind(&Ldff1Helper<Shift>,
+                                              config,
+                                              data,
+                                              std::placeholders::_1,
+                                              std::placeholders::_2,
+                                              CPURegister::kRegister,
+                                              std::placeholders::_3,
+                                              std::placeholders::_4,
+                                              LSL,
+                                              true);
+
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  ldff1_scaled_offset_helper(kHRegSize, kHRegSize, ldff1h, ld1h);
+  ldff1_scaled_offset_helper(kHRegSize, kSRegSize, ldff1h, ld1h);
+  ldff1_scaled_offset_helper(kHRegSize, kDRegSize, ldff1h, ld1h);
+
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  ldff1_scaled_offset_helper(kSRegSize, kSRegSize, ldff1w, ld1w);
+  ldff1_scaled_offset_helper(kSRegSize, kDRegSize, ldff1w, ld1w);
+
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  ldff1_scaled_offset_helper(kDRegSize, kDRegSize, ldff1d, ld1d);
+
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  ldff1_scaled_offset_helper(kHRegSize, kSRegSize, ldff1sh, ld1sh);
+  ldff1_scaled_offset_helper(kHRegSize, kDRegSize, ldff1sh, ld1sh);
+
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  ldff1_scaled_offset_helper(kSRegSize, kDRegSize, ldff1sw, ld1sw);
+
+  munmap(reinterpret_cast<void*>(data), page_size * 2);
+}
+
+static void sve_ldff1_scalar_plus_vector_32_scaled_offset(Test* config,
+                                                          uintptr_t data) {
+  auto ldff1_32_scaled_offset_helper = std::bind(&Ldff1Helper<Extend>,
+                                                 config,
+                                                 data,
+                                                 std::placeholders::_1,
+                                                 kSRegSize,
+                                                 CPURegister::kZRegister,
+                                                 std::placeholders::_2,
+                                                 std::placeholders::_3,
+                                                 std::placeholders::_4,
+                                                 true);
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  ldff1_32_scaled_offset_helper(kHRegSize, ldff1h, ld1h, UXTW);
+  ldff1_32_scaled_offset_helper(kHRegSize, ldff1h, ld1h, SXTW);
+
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  ldff1_32_scaled_offset_helper(kSRegSize, ldff1w, ld1w, UXTW);
+  ldff1_32_scaled_offset_helper(kSRegSize, ldff1w, ld1w, SXTW);
+
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  ldff1_32_scaled_offset_helper(kHRegSize, ldff1sh, ld1sh, UXTW);
+  ldff1_32_scaled_offset_helper(kHRegSize, ldff1sh, ld1sh, SXTW);
+}
+
+static void sve_ldff1_scalar_plus_vector_32_unscaled_offset(Test* config,
+                                                            uintptr_t data) {
+  auto ldff1_32_unscaled_offset_helper = std::bind(&Ldff1Helper<Extend>,
+                                                   config,
+                                                   data,
+                                                   std::placeholders::_1,
+                                                   kSRegSize,
+                                                   CPURegister::kZRegister,
+                                                   std::placeholders::_2,
+                                                   std::placeholders::_3,
+                                                   std::placeholders::_4,
+                                                   false);
+
+  Ld1Macro ldff1b = &MacroAssembler::Ldff1b;
+  Ld1Macro ld1b = &MacroAssembler::Ld1b;
+  ldff1_32_unscaled_offset_helper(kBRegSize, ldff1b, ld1b, UXTW);
+  ldff1_32_unscaled_offset_helper(kBRegSize, ldff1b, ld1b, SXTW);
+
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  ldff1_32_unscaled_offset_helper(kHRegSize, ldff1h, ld1h, UXTW);
+  ldff1_32_unscaled_offset_helper(kHRegSize, ldff1h, ld1h, SXTW);
+
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  ldff1_32_unscaled_offset_helper(kSRegSize, ldff1w, ld1w, UXTW);
+  ldff1_32_unscaled_offset_helper(kSRegSize, ldff1w, ld1w, SXTW);
+
+  Ld1Macro ldff1sb = &MacroAssembler::Ldff1sb;
+  Ld1Macro ld1sb = &MacroAssembler::Ld1sb;
+  ldff1_32_unscaled_offset_helper(kBRegSize, ldff1sb, ld1sb, UXTW);
+  ldff1_32_unscaled_offset_helper(kBRegSize, ldff1sb, ld1sb, SXTW);
+
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  ldff1_32_unscaled_offset_helper(kHRegSize, ldff1sh, ld1sh, UXTW);
+  ldff1_32_unscaled_offset_helper(kHRegSize, ldff1sh, ld1sh, SXTW);
+}
+
+static void sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset(
+    Test* config, uintptr_t data) {
+  auto ldff1_32_unpacked_scaled_offset_helper =
+      std::bind(&Ldff1Helper<Extend>,
+                config,
+                data,
+                std::placeholders::_1,
+                kDRegSize,
+                CPURegister::kZRegister,
+                std::placeholders::_2,
+                std::placeholders::_3,
+                std::placeholders::_4,
+                true);
+
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  ldff1_32_unpacked_scaled_offset_helper(kHRegSize, ldff1h, ld1h, UXTW);
+  ldff1_32_unpacked_scaled_offset_helper(kHRegSize, ldff1h, ld1h, SXTW);
+
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  ldff1_32_unpacked_scaled_offset_helper(kSRegSize, ldff1w, ld1w, UXTW);
+  ldff1_32_unpacked_scaled_offset_helper(kSRegSize, ldff1w, ld1w, SXTW);
+
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  ldff1_32_unpacked_scaled_offset_helper(kDRegSize, ldff1d, ld1d, UXTW);
+  ldff1_32_unpacked_scaled_offset_helper(kDRegSize, ldff1d, ld1d, SXTW);
+
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  ldff1_32_unpacked_scaled_offset_helper(kHRegSize, ldff1sh, ld1sh, UXTW);
+  ldff1_32_unpacked_scaled_offset_helper(kHRegSize, ldff1sh, ld1sh, SXTW);
+
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  ldff1_32_unpacked_scaled_offset_helper(kSRegSize, ldff1sw, ld1sw, UXTW);
+  ldff1_32_unpacked_scaled_offset_helper(kSRegSize, ldff1sw, ld1sw, SXTW);
+}
+
+static void sve_ldff1_scalar_plus_vector_32_unpacked_unscaled_offset(
+    Test* config, uintptr_t data) {
+  auto ldff1_32_unpacked_unscaled_offset_helper =
+      std::bind(&Ldff1Helper<Extend>,
+                config,
+                data,
+                std::placeholders::_1,
+                kDRegSize,
+                CPURegister::kZRegister,
+                std::placeholders::_2,
+                std::placeholders::_3,
+                std::placeholders::_4,
+                false);
+
+  Ld1Macro ldff1b = &MacroAssembler::Ldff1b;
+  Ld1Macro ld1b = &MacroAssembler::Ld1b;
+  ldff1_32_unpacked_unscaled_offset_helper(kBRegSize, ldff1b, ld1b, UXTW);
+  ldff1_32_unpacked_unscaled_offset_helper(kBRegSize, ldff1b, ld1b, SXTW);
+
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  ldff1_32_unpacked_unscaled_offset_helper(kHRegSize, ldff1h, ld1h, UXTW);
+  ldff1_32_unpacked_unscaled_offset_helper(kHRegSize, ldff1h, ld1h, SXTW);
+
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  ldff1_32_unpacked_unscaled_offset_helper(kSRegSize, ldff1w, ld1w, UXTW);
+  ldff1_32_unpacked_unscaled_offset_helper(kSRegSize, ldff1w, ld1w, SXTW);
+
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  ldff1_32_unpacked_unscaled_offset_helper(kDRegSize, ldff1d, ld1d, UXTW);
+  ldff1_32_unpacked_unscaled_offset_helper(kDRegSize, ldff1d, ld1d, SXTW);
+
+  Ld1Macro ldff1sb = &MacroAssembler::Ldff1sb;
+  Ld1Macro ld1sb = &MacroAssembler::Ld1sb;
+  ldff1_32_unpacked_unscaled_offset_helper(kBRegSize, ldff1sb, ld1sb, UXTW);
+  ldff1_32_unpacked_unscaled_offset_helper(kBRegSize, ldff1sb, ld1sb, SXTW);
+
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  ldff1_32_unpacked_unscaled_offset_helper(kHRegSize, ldff1sh, ld1sh, UXTW);
+  ldff1_32_unpacked_unscaled_offset_helper(kHRegSize, ldff1sh, ld1sh, SXTW);
+
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  ldff1_32_unpacked_unscaled_offset_helper(kSRegSize, ldff1sw, ld1sw, UXTW);
+  ldff1_32_unpacked_unscaled_offset_helper(kSRegSize, ldff1sw, ld1sw, SXTW);
+}
+
+static void sve_ldff1_scalar_plus_vector_64_scaled_offset(Test* config,
+                                                          uintptr_t data) {
+  auto ldff1_64_scaled_offset_helper = std::bind(&Ldff1Helper<Shift>,
+                                                 config,
+                                                 data,
+                                                 std::placeholders::_1,
+                                                 kDRegSize,
+                                                 CPURegister::kZRegister,
+                                                 std::placeholders::_2,
+                                                 std::placeholders::_3,
+                                                 LSL,
+                                                 true);
+
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  ldff1_64_scaled_offset_helper(kHRegSize, ldff1h, ld1h);
+
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  ldff1_64_scaled_offset_helper(kSRegSize, ldff1w, ld1w);
+
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  ldff1_64_scaled_offset_helper(kDRegSize, ldff1d, ld1d);
+
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  ldff1_64_scaled_offset_helper(kHRegSize, ldff1sh, ld1sh);
+
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  ldff1_64_scaled_offset_helper(kSRegSize, ldff1sw, ld1sw);
+}
+
+static void sve_ldff1_scalar_plus_vector_64_unscaled_offset(Test* config,
+                                                            uintptr_t data) {
+  auto ldff1_64_unscaled_offset_helper = std::bind(&Ldff1Helper<Shift>,
+                                                   config,
+                                                   data,
+                                                   std::placeholders::_1,
+                                                   kDRegSize,
+                                                   CPURegister::kZRegister,
+                                                   std::placeholders::_2,
+                                                   std::placeholders::_3,
+                                                   NO_SHIFT,
+                                                   false);
+
+  Ld1Macro ldff1b = &MacroAssembler::Ldff1b;
+  Ld1Macro ld1b = &MacroAssembler::Ld1b;
+  ldff1_64_unscaled_offset_helper(kBRegSize, ldff1b, ld1b);
+
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  ldff1_64_unscaled_offset_helper(kHRegSize, ldff1h, ld1h);
+
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  ldff1_64_unscaled_offset_helper(kSRegSize, ldff1w, ld1w);
+
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  ldff1_64_unscaled_offset_helper(kDRegSize, ldff1d, ld1d);
+
+  Ld1Macro ldff1sb = &MacroAssembler::Ldff1sb;
+  Ld1Macro ld1sb = &MacroAssembler::Ld1sb;
+  ldff1_64_unscaled_offset_helper(kBRegSize, ldff1sb, ld1sb);
+
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  ldff1_64_unscaled_offset_helper(kHRegSize, ldff1sh, ld1sh);
+
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  ldff1_64_unscaled_offset_helper(kSRegSize, ldff1sw, ld1sw);
+}
+
+TEST_SVE(sve_ldff1_scalar_plus_vector) {
+  size_t page_size = sysconf(_SC_PAGE_SIZE);
+  VIXL_ASSERT(page_size > static_cast<size_t>(config->sve_vl_in_bytes()));
+
+  // Allocate two pages, then mprotect the second one to make it inaccessible.
+  uintptr_t data = reinterpret_cast<uintptr_t>(mmap(NULL,
+                                                    page_size * 2,
+                                                    PROT_READ | PROT_WRITE,
+                                                    MAP_PRIVATE | MAP_ANONYMOUS,
+                                                    -1,
+                                                    0));
+  mprotect(reinterpret_cast<void*>(data + page_size), page_size, PROT_NONE);
+
+  // Fill the accessible page with arbitrary data.
+  for (size_t i = 0; i < page_size; i++) {
+    // Reverse bits so we get a mixture of positive and negative values.
+    uint8_t byte = ReverseBits(static_cast<uint8_t>(i));
+    memcpy(reinterpret_cast<void*>(data + i), &byte, 1);
+  }
+
+  sve_ldff1_scalar_plus_vector_32_scaled_offset(config, data);
+  sve_ldff1_scalar_plus_vector_32_unscaled_offset(config, data);
+  sve_ldff1_scalar_plus_vector_32_unpacked_scaled_offset(config, data);
+  sve_ldff1_scalar_plus_vector_32_unpacked_unscaled_offset(config, data);
+  sve_ldff1_scalar_plus_vector_64_scaled_offset(config, data);
+  sve_ldff1_scalar_plus_vector_64_unscaled_offset(config, data);
+
+  munmap(reinterpret_cast<void*>(data), page_size * 2);
+}
+
+TEST_SVE(sve_ldnf1) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE,
+                          CPUFeatures::kNEON,
+                          CPUFeatures::kFP);
+  START();
+
+  size_t page_size = sysconf(_SC_PAGE_SIZE);
+  VIXL_ASSERT(page_size > static_cast<size_t>(config->sve_vl_in_bytes()));
+
+  // Allocate two pages, fill them with data, then mprotect the second one to
+  // make it inaccessible.
+  uintptr_t data = reinterpret_cast<uintptr_t>(mmap(NULL,
+                                                    page_size * 2,
+                                                    PROT_READ | PROT_WRITE,
+                                                    MAP_PRIVATE | MAP_ANONYMOUS,
+                                                    -1,
+                                                    0));
+
+  // Fill the pages with arbitrary data.
+  for (size_t i = 0; i < page_size; i++) {
+    // Reverse bits so we get a mixture of positive and negative values.
+    uint8_t byte = ReverseBits(static_cast<uint8_t>(i));
+    memcpy(reinterpret_cast<void*>(data + i), &byte, 1);
+  }
+
+  mprotect(reinterpret_cast<void*>(data + page_size), page_size, PROT_NONE);
+
+  __ Setffr();
+  __ Ptrue(p0.VnB());
+  __ Dup(z10.VnB(), 0);
+
+  // Move an address that points to the last unprotected eight bytes.
+  __ Mov(x0, data + page_size - (kQRegSizeInBytes / kBRegSizeInBytes) / 2);
+
+  // Load, non-faulting, a vector of bytes from x0. At most, eight bytes will be
+  // loaded, the rest being in a protected page.
+  __ Ldnf1b(z0.VnB(), p0.Zeroing(), SVEMemOperand(x0));
+  __ Rdffr(p1.VnB());
+  __ Setffr();
+
+  // Create references using the FFR value in p1 to zero the undefined lanes.
+  __ Sel(z0.VnB(), p1, z0.VnB(), z10.VnB());
+  __ Ld1b(z20.VnB(), p1.Zeroing(), SVEMemOperand(x0));
+
+  // Repeat for larger elements and different addresses, giving different FFR
+  // results.
+  __ Add(x1, x0, 1);
+  __ Ldnf1h(z1.VnH(), p0.Zeroing(), SVEMemOperand(x1));
+  __ Rdffr(p1.VnB());
+  __ Setffr();
+  __ Sel(z1.VnH(), p1, z1.VnH(), z10.VnH());
+  __ Ld1h(z21.VnH(), p1.Zeroing(), SVEMemOperand(x1));
+
+  __ Add(x1, x0, 2);
+  __ Ldnf1w(z2.VnS(), p0.Zeroing(), SVEMemOperand(x1));
+  __ Rdffr(p1.VnB());
+  __ Setffr();
+  __ Sel(z2.VnS(), p1, z2.VnS(), z10.VnS());
+  __ Ld1w(z22.VnS(), p1.Zeroing(), SVEMemOperand(x1));
+
+  __ Sub(x1, x0, 1);
+  __ Ldnf1d(z3.VnD(), p0.Zeroing(), SVEMemOperand(x1));
+  __ Rdffr(p1.VnB());
+  __ Setffr();
+  __ Sel(z3.VnD(), p1, z3.VnD(), z10.VnD());
+  __ Ld1d(z23.VnD(), p1.Zeroing(), SVEMemOperand(x1));
+
+  // Load from previous VL-sized area of memory. All of this should be in the
+  // accessible page.
+  __ Ldnf1b(z4.VnB(), p0.Zeroing(), SVEMemOperand(x0, -1, SVE_MUL_VL));
+  __ Rdffr(p1.VnB());
+  __ Setffr();
+  __ Sel(z4.VnB(), p1, z4.VnB(), z10.VnB());
+  __ Ld1b(z24.VnB(), p1.Zeroing(), SVEMemOperand(x0, -1, SVE_MUL_VL));
+
+  // Repeat partial load for larger element size.
+  __ Mov(x0, data + page_size - (kQRegSizeInBytes / kSRegSizeInBytes) / 2);
+  __ Ldnf1b(z5.VnS(), p0.Zeroing(), SVEMemOperand(x0));
+  __ Rdffr(p1.VnB());
+  __ Setffr();
+  __ Sel(z5.VnS(), p1, z5.VnS(), z10.VnS());
+  __ Ld1b(z25.VnS(), p1.Zeroing(), SVEMemOperand(x0));
+
+  // Repeat for sign extension.
+  __ Mov(x0, data + page_size - (kQRegSizeInBytes / kHRegSizeInBytes) / 2);
+  __ Ldnf1sb(z6.VnH(), p0.Zeroing(), SVEMemOperand(x0));
+  __ Rdffr(p1.VnB());
+  __ Setffr();
+  __ Sel(z6.VnH(), p1, z6.VnH(), z10.VnH());
+  __ Ld1sb(z26.VnH(), p1.Zeroing(), SVEMemOperand(x0));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(z20, z0);
+    ASSERT_EQUAL_SVE(z21, z1);
+    ASSERT_EQUAL_SVE(z22, z2);
+    ASSERT_EQUAL_SVE(z23, z3);
+    ASSERT_EQUAL_SVE(z24, z4);
+    ASSERT_EQUAL_SVE(z25, z5);
+    ASSERT_EQUAL_SVE(z26, z6);
+  }
+
+  munmap(reinterpret_cast<void*>(data), page_size * 2);
+}
+
+// Emphasis on test if the modifiers are propagated and simulated correctly.
+TEST_SVE(sve_ldff1_regression_test) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  size_t page_size = sysconf(_SC_PAGE_SIZE);
+  VIXL_ASSERT(page_size > static_cast<size_t>(config->sve_vl_in_bytes()));
+
+  uintptr_t data = reinterpret_cast<uintptr_t>(mmap(NULL,
+                                                    page_size * 2,
+                                                    PROT_READ | PROT_WRITE,
+                                                    MAP_PRIVATE | MAP_ANONYMOUS,
+                                                    -1,
+                                                    0));
+  uintptr_t middle = data + page_size;
+  // Fill the accessible page with arbitrary data.
+  for (size_t i = 0; i < page_size; i++) {
+    // Reverse bits so we get a mixture of positive and negative values.
+    uint8_t byte = ReverseBits(static_cast<uint8_t>(i));
+    memcpy(reinterpret_cast<void*>(middle + i), &byte, 1);
+    // Make one bit roughly different in every byte and copy the bytes in the
+    // reverse direction that convenient to verifying the loads in negative
+    // indexes.
+    byte += 1;
+    memcpy(reinterpret_cast<void*>(middle - i), &byte, 1);
+  }
+
+  PRegister all = p6;
+  __ Ptrue(all.VnB());
+
+  __ Mov(x0, middle);
+  __ Index(z31.VnS(), 0, 3);
+  __ Neg(z30.VnS(), z31.VnS());
+
+  __ Setffr();
+
+  // Scalar plus vector 32 unscaled offset
+  __ Ldff1b(z1.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
+  __ Ldff1h(z2.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW));
+  __ Ldff1w(z3.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
+  __ Ldff1sb(z4.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW));
+  __ Ldff1sh(z5.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
+
+  // Scalar plus vector 32 scaled offset
+  __ Ldff1h(z6.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW, 1));
+  __ Ldff1w(z7.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW, 2));
+  __ Ldff1sh(z8.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW, 1));
+
+  __ Index(z31.VnD(), 0, 3);
+  __ Neg(z30.VnD(), z31.VnD());
+
+  // Ensure only the low 32 bits are used for the testing with positive index
+  // values. It also test if the indexes are treated as positive in `uxtw` form.
+  __ Mov(x3, 0x8000000080000000);
+  __ Dup(z28.VnD(), x3);
+  __ Sub(x2, x0, 0x80000000);
+  __ Add(z29.VnD(), z31.VnD(), z28.VnD());
+
+  // Scalar plus vector 32 unpacked unscaled offset
+  __ Ldff1b(z9.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
+  __ Ldff1h(z10.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW));
+  __ Ldff1w(z11.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
+  __ Ldff1sb(z12.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
+  __ Ldff1sh(z13.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW));
+  __ Ldff1sw(z14.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
+
+  // Scalar plus vector 32 unpacked scaled offset
+  __ Ldff1h(z15.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 1));
+  __ Ldff1w(z16.VnD(), all.Zeroing(), SVEMemOperand(x0, z31.VnD(), UXTW, 2));
+  __ Ldff1d(z17.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 3));
+  __ Ldff1sh(z18.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 1));
+  __ Ldff1sw(z19.VnD(), all.Zeroing(), SVEMemOperand(x0, z31.VnD(), UXTW, 2));
+
+  __ Sub(x0, x0, x3);
+  // Note that the positive indexes has been added by `0x8000000080000000`. The
+  // wrong address will be accessed if the address is treated as negative.
+
+  // Scalar plus vector 64 unscaled offset
+  __ Ldff1b(z20.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+  __ Ldff1h(z21.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+  __ Ldff1w(z22.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+  __ Ldff1sh(z23.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+  __ Ldff1sw(z24.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+
+  // Scalar plus vector 64 scaled offset
+  __ Lsr(z29.VnD(), z28.VnD(), 1);  // Shift right to 0x4000000040000000
+  __ Add(z30.VnD(), z31.VnD(), z29.VnD());
+  __ Ldff1h(z25.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 1));
+  __ Ldff1sh(z26.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 1));
+
+  __ Lsr(z29.VnD(), z29.VnD(), 1);  // Shift right to 0x2000000020000000
+  __ Add(z30.VnD(), z31.VnD(), z29.VnD());
+  __ Ldff1w(z27.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 2));
+  __ Ldff1sw(z28.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 2));
+
+  __ Lsr(z29.VnD(), z29.VnD(), 1);  // Shift right to 0x1000000010000000
+  __ Add(z30.VnD(), z31.VnD(), z29.VnD());
+  __ Ldff1d(z29.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 3));
+
+  __ Rdffr(p1.VnB());
+  __ Cntp(x10, all, p1.VnB());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int64_t loaded_data_in_bytes = core.xreg(x10.GetCode());
+    // Only check 128 bits in this test.
+    if (loaded_data_in_bytes < kQRegSizeInBytes) {
+      // Report a warning when we hit fault-tolerant loads before all expected
+      // loads performed.
+      printf(
+          "WARNING: Fault-tolerant loads detected faults before the "
+          "expected loads completed.\n");
+      return;
+    }
+
+    // Scalar plus vector 32 unscaled offset
+    uint32_t expected_z1[] = {0x00000090, 0x00000060, 0x000000c0, 0x00000001};
+    uint32_t expected_z2[] = {0x00001191, 0x0000a161, 0x000041c1, 0x00008001};
+    uint32_t expected_z3[] = {0x30d05090, 0x9010e060, 0x60a020c0, 0xc0408001};
+    uint32_t expected_z4[] = {0xffffff91, 0x00000061, 0xffffffc1, 0x00000001};
+    uint32_t expected_z5[] = {0x00005090, 0xffffe060, 0x000020c0, 0xffff8001};
+
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnS());
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnS());
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnS());
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnS());
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnS());
+
+    // Scalar plus vector 32 scaled offset
+    uint32_t expected_z6[] = {0x0000c848, 0x0000b030, 0x0000e060, 0x00008001};
+    uint32_t expected_z7[] = {0xe464a424, 0xd8589818, 0xf070b030, 0xc0408001};
+    uint32_t expected_z8[] = {0xffff8949, 0xffffd131, 0xffffa161, 0xffff8001};
+
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnS());
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnS());
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnS());
+
+    // Scalar plus vector 32 unpacked unscaled offset
+    uint64_t expected_z9[] = {0x00000000000000c0, 0x0000000000000001};
+    uint64_t expected_z10[] = {0x00000000000041c1, 0x0000000000008001};
+    uint64_t expected_z11[] = {0x0000000060a020c0, 0x00000000c0408001};
+    uint64_t expected_z12[] = {0xffffffffffffffc0, 0x0000000000000001};
+    uint64_t expected_z13[] = {0x00000000000041c1, 0xffffffffffff8001};
+    uint64_t expected_z14[] = {0x0000000060a020c0, 0xffffffffc0408001};
+
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+    ASSERT_EQUAL_SVE(expected_z12, z12.VnD());
+    ASSERT_EQUAL_SVE(expected_z13, z13.VnD());
+    ASSERT_EQUAL_SVE(expected_z14, z14.VnD());
+
+    // Scalar plus vector 32 unpacked scaled offset
+    uint64_t expected_z15[] = {0x000000000000a161, 0x0000000000008001};
+    uint64_t expected_z16[] = {0x00000000f070b030, 0x00000000c0408001};
+    uint64_t expected_z17[] = {0x8949c929a969e919, 0xe060a020c0408001};
+    uint64_t expected_z18[] = {0xffffffffffffa161, 0xffffffffffff8001};
+    uint64_t expected_z19[] = {0xfffffffff070b030, 0xffffffffc0408001};
+
+    ASSERT_EQUAL_SVE(expected_z15, z15.VnD());
+    ASSERT_EQUAL_SVE(expected_z16, z16.VnD());
+    ASSERT_EQUAL_SVE(expected_z17, z17.VnD());
+    ASSERT_EQUAL_SVE(expected_z18, z18.VnD());
+    ASSERT_EQUAL_SVE(expected_z19, z19.VnD());
+
+    // Scalar plus vector 64 unscaled offset
+    uint64_t expected_z20[] = {0x00000000000000c0, 0x0000000000000001};
+    uint64_t expected_z21[] = {0x00000000000020c0, 0x0000000000008001};
+    uint64_t expected_z22[] = {0x0000000060a020c0, 0x00000000c0408001};
+    uint64_t expected_z23[] = {0x00000000000020c0, 0xffffffffffff8001};
+    uint64_t expected_z24[] = {0x0000000060a020c0, 0xffffffffc0408001};
+
+    ASSERT_EQUAL_SVE(expected_z20, z20.VnD());
+    ASSERT_EQUAL_SVE(expected_z21, z21.VnD());
+    ASSERT_EQUAL_SVE(expected_z22, z22.VnD());
+    ASSERT_EQUAL_SVE(expected_z23, z23.VnD());
+    ASSERT_EQUAL_SVE(expected_z24, z24.VnD());
+
+    uint64_t expected_z25[] = {0x000000000000e060, 0x0000000000008001};
+    uint64_t expected_z26[] = {0xffffffffffffe060, 0xffffffffffff8001};
+    uint64_t expected_z27[] = {0x00000000f070b030, 0x00000000c0408001};
+    uint64_t expected_z28[] = {0xfffffffff070b030, 0xffffffffc0408001};
+    uint64_t expected_z29[] = {0xf878b838d8589818, 0xe060a020c0408001};
+
+    // Scalar plus vector 64 scaled offset
+    ASSERT_EQUAL_SVE(expected_z25, z25.VnD());
+    ASSERT_EQUAL_SVE(expected_z26, z26.VnD());
+    ASSERT_EQUAL_SVE(expected_z27, z27.VnD());
+    ASSERT_EQUAL_SVE(expected_z28, z28.VnD());
+    ASSERT_EQUAL_SVE(expected_z29, z29.VnD());
+  }
+}
+
+// Emphasis on test if the modifiers are propagated and simulated correctly.
+TEST_SVE(sve_ld1_regression_test) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  size_t page_size = sysconf(_SC_PAGE_SIZE);
+  VIXL_ASSERT(page_size > static_cast<size_t>(config->sve_vl_in_bytes()));
+
+  uintptr_t data = reinterpret_cast<uintptr_t>(mmap(NULL,
+                                                    page_size * 2,
+                                                    PROT_READ | PROT_WRITE,
+                                                    MAP_PRIVATE | MAP_ANONYMOUS,
+                                                    -1,
+                                                    0));
+  uintptr_t middle = data + page_size;
+  // Fill the accessible page with arbitrary data.
+  for (size_t i = 0; i < page_size; i++) {
+    // Reverse bits so we get a mixture of positive and negative values.
+    uint8_t byte = ReverseBits(static_cast<uint8_t>(i));
+    memcpy(reinterpret_cast<void*>(middle + i), &byte, 1);
+    // Make one bit roughly different in every byte and copy the bytes in the
+    // reverse direction that convenient to verifying the loads in negative
+    // indexes.
+    byte += 1;
+    memcpy(reinterpret_cast<void*>(middle - i), &byte, 1);
+  }
+
+  PRegister all = p6;
+  __ Ptrue(all.VnB());
+
+  __ Mov(x0, middle);
+  __ Index(z31.VnS(), 0, 3);
+  __ Neg(z30.VnS(), z31.VnS());
+
+  // Scalar plus vector 32 unscaled offset
+  __ Ld1b(z1.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
+  __ Ld1h(z2.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW));
+  __ Ld1w(z3.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
+  __ Ld1sb(z4.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW));
+  __ Ld1sh(z5.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW));
+
+  // Scalar plus vector 32 scaled offset
+  __ Ld1h(z6.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW, 1));
+  __ Ld1w(z7.VnS(), all.Zeroing(), SVEMemOperand(x0, z31.VnS(), UXTW, 2));
+  __ Ld1sh(z8.VnS(), all.Zeroing(), SVEMemOperand(x0, z30.VnS(), SXTW, 1));
+
+  __ Index(z31.VnD(), 0, 3);
+  __ Neg(z30.VnD(), z31.VnD());
+
+  // Ensure only the low 32 bits are used for the testing with positive index
+  // values. It also test if the indexes are treated as positive in `uxtw` form.
+  __ Mov(x3, 0x8000000080000000);
+  __ Dup(z28.VnD(), x3);
+  __ Sub(x2, x0, 0x80000000);
+  __ Add(z29.VnD(), z31.VnD(), z28.VnD());
+
+  // Scalar plus vector 32 unpacked unscaled offset
+  __ Ld1b(z9.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
+  __ Ld1h(z10.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW));
+  __ Ld1w(z11.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
+  __ Ld1sb(z12.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
+  __ Ld1sh(z13.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW));
+  __ Ld1sw(z14.VnD(), all.Zeroing(), SVEMemOperand(x2, z29.VnD(), UXTW));
+
+  // Scalar plus vector 32 unpacked scaled offset
+  __ Ld1h(z15.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 1));
+  __ Ld1w(z16.VnD(), all.Zeroing(), SVEMemOperand(x0, z31.VnD(), UXTW, 2));
+  __ Ld1d(z17.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 3));
+  __ Ld1sh(z18.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), SXTW, 1));
+  __ Ld1sw(z19.VnD(), all.Zeroing(), SVEMemOperand(x0, z31.VnD(), UXTW, 2));
+
+  __ Sub(x0, x0, x3);
+  // Note that the positive indexes has been added by `0x8000000080000000`. The
+  // wrong address will be accessed if the address is treated as negative.
+
+  // Scalar plus vector 64 unscaled offset
+  __ Ld1b(z20.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+  __ Ld1h(z21.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+  __ Ld1w(z22.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+  __ Ld1sh(z23.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+  __ Ld1sw(z24.VnD(), all.Zeroing(), SVEMemOperand(x0, z29.VnD()));
+
+  // Scalar plus vector 64 scaled offset
+  __ Lsr(z29.VnD(), z28.VnD(), 1);  // Shift right to 0x4000000040000000
+  __ Add(z30.VnD(), z31.VnD(), z29.VnD());
+  __ Ld1h(z25.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 1));
+  __ Ld1sh(z26.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 1));
+
+  __ Lsr(z29.VnD(), z29.VnD(), 1);  // Shift right to 0x2000000020000000
+  __ Add(z30.VnD(), z31.VnD(), z29.VnD());
+  __ Ld1w(z27.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 2));
+  __ Ld1sw(z28.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 2));
+
+  __ Lsr(z29.VnD(), z29.VnD(), 1);  // Shift right to 0x1000000010000000
+  __ Add(z30.VnD(), z31.VnD(), z29.VnD());
+  __ Ld1d(z29.VnD(), all.Zeroing(), SVEMemOperand(x0, z30.VnD(), LSL, 3));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Scalar plus vector 32 unscaled offset
+    uint32_t expected_z1[] = {0x00000090, 0x00000060, 0x000000c0, 0x00000001};
+    uint32_t expected_z2[] = {0x00001191, 0x0000a161, 0x000041c1, 0x00008001};
+    uint32_t expected_z3[] = {0x30d05090, 0x9010e060, 0x60a020c0, 0xc0408001};
+    uint32_t expected_z4[] = {0xffffff91, 0x00000061, 0xffffffc1, 0x00000001};
+    uint32_t expected_z5[] = {0x00005090, 0xffffe060, 0x000020c0, 0xffff8001};
+
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnS());
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnS());
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnS());
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnS());
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnS());
+
+    // Scalar plus vector 32 scaled offset
+    uint32_t expected_z6[] = {0x0000c848, 0x0000b030, 0x0000e060, 0x00008001};
+    uint32_t expected_z7[] = {0xe464a424, 0xd8589818, 0xf070b030, 0xc0408001};
+    uint32_t expected_z8[] = {0xffff8949, 0xffffd131, 0xffffa161, 0xffff8001};
+
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnS());
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnS());
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnS());
+
+    // Scalar plus vector 32 unpacked unscaled offset
+    uint64_t expected_z9[] = {0x00000000000000c0, 0x0000000000000001};
+    uint64_t expected_z10[] = {0x00000000000041c1, 0x0000000000008001};
+    uint64_t expected_z11[] = {0x0000000060a020c0, 0x00000000c0408001};
+    uint64_t expected_z12[] = {0xffffffffffffffc0, 0x0000000000000001};
+    uint64_t expected_z13[] = {0x00000000000041c1, 0xffffffffffff8001};
+    uint64_t expected_z14[] = {0x0000000060a020c0, 0xffffffffc0408001};
+
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+    ASSERT_EQUAL_SVE(expected_z12, z12.VnD());
+    ASSERT_EQUAL_SVE(expected_z13, z13.VnD());
+    ASSERT_EQUAL_SVE(expected_z14, z14.VnD());
+
+    // Scalar plus vector 32 unpacked scaled offset
+    uint64_t expected_z15[] = {0x000000000000a161, 0x0000000000008001};
+    uint64_t expected_z16[] = {0x00000000f070b030, 0x00000000c0408001};
+    uint64_t expected_z17[] = {0x8949c929a969e919, 0xe060a020c0408001};
+    uint64_t expected_z18[] = {0xffffffffffffa161, 0xffffffffffff8001};
+    uint64_t expected_z19[] = {0xfffffffff070b030, 0xffffffffc0408001};
+
+    ASSERT_EQUAL_SVE(expected_z15, z15.VnD());
+    ASSERT_EQUAL_SVE(expected_z16, z16.VnD());
+    ASSERT_EQUAL_SVE(expected_z17, z17.VnD());
+    ASSERT_EQUAL_SVE(expected_z18, z18.VnD());
+    ASSERT_EQUAL_SVE(expected_z19, z19.VnD());
+
+    // Scalar plus vector 64 unscaled offset
+    uint64_t expected_z20[] = {0x00000000000000c0, 0x0000000000000001};
+    uint64_t expected_z21[] = {0x00000000000020c0, 0x0000000000008001};
+    uint64_t expected_z22[] = {0x0000000060a020c0, 0x00000000c0408001};
+    uint64_t expected_z23[] = {0x00000000000020c0, 0xffffffffffff8001};
+    uint64_t expected_z24[] = {0x0000000060a020c0, 0xffffffffc0408001};
+
+    ASSERT_EQUAL_SVE(expected_z20, z20.VnD());
+    ASSERT_EQUAL_SVE(expected_z21, z21.VnD());
+    ASSERT_EQUAL_SVE(expected_z22, z22.VnD());
+    ASSERT_EQUAL_SVE(expected_z23, z23.VnD());
+    ASSERT_EQUAL_SVE(expected_z24, z24.VnD());
+
+    uint64_t expected_z25[] = {0x000000000000e060, 0x0000000000008001};
+    uint64_t expected_z26[] = {0xffffffffffffe060, 0xffffffffffff8001};
+    uint64_t expected_z27[] = {0x00000000f070b030, 0x00000000c0408001};
+    uint64_t expected_z28[] = {0xfffffffff070b030, 0xffffffffc0408001};
+    uint64_t expected_z29[] = {0xf878b838d8589818, 0xe060a020c0408001};
+
+    // Scalar plus vector 64 scaled offset
+    ASSERT_EQUAL_SVE(expected_z25, z25.VnD());
+    ASSERT_EQUAL_SVE(expected_z26, z26.VnD());
+    ASSERT_EQUAL_SVE(expected_z27, z27.VnD());
+    ASSERT_EQUAL_SVE(expected_z28, z28.VnD());
+    ASSERT_EQUAL_SVE(expected_z29, z29.VnD());
+  }
+}
+
+// Test gather loads by comparing them with the result of a set of equivalent
+// scalar loads.
+template <typename T>
+static void GatherLoadScalarPlusVectorHelper(Test* config,
+                                             unsigned msize_in_bits,
+                                             unsigned esize_in_bits,
+                                             Ld1Macro ld1,
+                                             Ld1Macro ldff1,
+                                             T mod,
+                                             bool is_signed,
+                                             bool is_scaled) {
+  // SVE supports 32- and 64-bit addressing for gather loads.
+  VIXL_ASSERT((esize_in_bits == kSRegSize) || (esize_in_bits == kDRegSize));
+  static const unsigned kMaxLaneCount = kZRegMaxSize / kSRegSize;
+
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  unsigned msize_in_bytes = msize_in_bits / kBitsPerByte;
+  int vl = config->sve_vl_in_bytes();
+
+  uint64_t addresses[kMaxLaneCount];
+  uint64_t offsets[kMaxLaneCount];
+  uint64_t max_address = 0;
+  uint64_t buffer_size = vl * 64;
+  uint64_t data = reinterpret_cast<uintptr_t>(malloc(buffer_size));
+  // Fill the buffer with arbitrary data. Meanwhile, create the random addresses
+  // and offsets into the buffer placed in the argument list.
+  BufferFillingHelper(data,
+                      buffer_size,
+                      msize_in_bytes,
+                      kMaxLaneCount,
+                      offsets,
+                      addresses,
+                      &max_address);
+
+  ZRegister zn = z0.WithLaneSize(esize_in_bits);
+  ZRegister zt_ref = z1.WithLaneSize(esize_in_bits);
+  ZRegister zt = z2.WithLaneSize(esize_in_bits);
+  ZRegister zt_ff = z3.WithLaneSize(esize_in_bits);
+  PRegisterWithLaneSize pg_ff = p1.WithLaneSize(esize_in_bits);
+  PRegisterWithLaneSize pg_diff = p2.WithLaneSize(esize_in_bits);
+
+  int shift = 0;
+  if (is_scaled) {
+    shift = std::log2(msize_in_bytes);
+    for (unsigned i = 0; i < kMaxLaneCount; i++) {
+      // Ensure the offsets are the multiple of the scale factor of the
+      // operation.
+      offsets[i] = (offsets[i] >> shift) << shift;
+      addresses[i] = data + offsets[i];
+    }
+  }
+
+  PRegister all = p6;
+  __ Ptrue(all.WithLaneSize(esize_in_bits));
+
+  PRegisterZ pg = p0.Zeroing();
+  Initialise(&masm,
+             pg,
+             0x9abcdef012345678,
+             0xabcdef0123456789,
+             0xf4f3f1f0fefdfcfa,
+             0xf9f8f6f5f3f2f1ff);
+
+  __ Mov(x0, data);
+
+  // Generate a reference result for scalar-plus-scalar form using scalar loads.
+  ScalarLoadHelper(&masm,
+                   vl,
+                   addresses,
+                   zt_ref,
+                   pg,
+                   esize_in_bits,
+                   msize_in_bits,
+                   is_signed);
+
+  InsrHelper(&masm, zn, offsets);
+  if (is_scaled) {
+    // Scale down the offsets if testing scaled-offset operation.
+    __ Lsr(zn, zn, shift);
+  }
+
+  (masm.*ld1)(zt, pg, SVEMemOperand(x0, zn, mod, shift));
+
+  Register ffr_check_count = x17;
+  __ Mov(ffr_check_count, 0);
+
+  // Test the data correctness in which the data gather load from different
+  // addresses. The first-fault behavior test is emphasized in `Ldff1Helper`.
+  __ Setffr();
+  (masm.*ldff1)(zt_ff, pg, SVEMemOperand(x0, zn, mod, shift));
+
+  // Compare these two vector register and place the different to
+  // `ffr_check_count`.
+  __ Rdffrs(pg_ff.VnB(), all.Zeroing());
+  __ Cmpeq(pg_diff, all.Zeroing(), zt_ref, zt_ff);
+  __ Eor(pg_diff.VnB(), all.Zeroing(), pg_diff.VnB(), pg_ff.VnB());
+  __ Incp(ffr_check_count, pg_diff);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(zt_ref, zt);
+    ASSERT_EQUAL_64(0, ffr_check_count);
+  }
+
+  free(reinterpret_cast<void*>(data));
+}
+
+// Test gather loads by comparing them with the result of a set of equivalent
+// scalar loads.
+template <typename F>
+static void GatherLoadScalarPlusScalarOrImmHelper(Test* config,
+                                                  unsigned msize_in_bits,
+                                                  unsigned esize_in_bits,
+                                                  F sve_ld1,
+                                                  bool is_signed) {
+  // SVE supports 32- and 64-bit addressing for gather loads.
+  VIXL_ASSERT((esize_in_bits == kSRegSize) || (esize_in_bits == kDRegSize));
+  static const unsigned kMaxLaneCount = kZRegMaxSize / kSRegSize;
+
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  unsigned msize_in_bytes = msize_in_bits / kBitsPerByte;
+  int vl = config->sve_vl_in_bytes();
+
+  uint64_t addresses[kMaxLaneCount];
+  uint64_t offsets[kMaxLaneCount];
+  uint64_t max_address = 0;
+  uint64_t buffer_size = vl * 64;
+  uint64_t data = reinterpret_cast<uintptr_t>(malloc(buffer_size));
+  BufferFillingHelper(data,
+                      buffer_size,
+                      msize_in_bytes,
+                      kMaxLaneCount,
+                      offsets,
+                      addresses,
+                      &max_address);
+
+  // Maximised offsets, to ensure that the address calculation is modulo-2^64,
+  // and that the vector addresses are not sign-extended.
+  uint64_t uint_e_max = (esize_in_bits == kDRegSize) ? UINT64_MAX : UINT32_MAX;
+  uint64_t maxed_offsets[kMaxLaneCount];
+  uint64_t maxed_offsets_imm = max_address - uint_e_max;
+  for (unsigned i = 0; i < kMaxLaneCount; i++) {
+    maxed_offsets[i] = addresses[i] - maxed_offsets_imm;
+  }
+
+  ZRegister zn = z0.WithLaneSize(esize_in_bits);
+  ZRegister zt_addresses = z1.WithLaneSize(esize_in_bits);
+  ZRegister zt_offsets = z2.WithLaneSize(esize_in_bits);
+  ZRegister zt_maxed = z3.WithLaneSize(esize_in_bits);
+  ZRegister zt_ref = z4.WithLaneSize(esize_in_bits);
+
+  PRegisterZ pg = p0.Zeroing();
+  Initialise(&masm,
+             pg,
+             0x9abcdef012345678,
+             0xabcdef0123456789,
+             0xf4f3f1f0fefdfcfa,
+             0xf9f8f6f5f3f2f0ff);
+
+  // Execute each load.
+
+  if (esize_in_bits == kDRegSize) {
+    // Only test `addresses` if we can use 64-bit pointers. InsrHelper will fail
+    // if any value won't fit in a lane of zn.
+    InsrHelper(&masm, zn, addresses);
+    (masm.*sve_ld1)(zt_addresses, pg, SVEMemOperand(zn));
+  }
+
+  InsrHelper(&masm, zn, offsets);
+  (masm.*sve_ld1)(zt_offsets, pg, SVEMemOperand(zn, data));
+
+  InsrHelper(&masm, zn, maxed_offsets);
+  (masm.*sve_ld1)(zt_maxed, pg, SVEMemOperand(zn, maxed_offsets_imm));
+
+  // Generate a reference result using scalar loads.
+  ScalarLoadHelper(&masm,
+                   vl,
+                   addresses,
+                   zt_ref,
+                   pg,
+                   esize_in_bits,
+                   msize_in_bits,
+                   is_signed);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    if (esize_in_bits == kDRegSize) {
+      ASSERT_EQUAL_SVE(zt_ref, zt_addresses);
+    }
+    ASSERT_EQUAL_SVE(zt_ref, zt_offsets);
+    ASSERT_EQUAL_SVE(zt_ref, zt_maxed);
+  }
+
+  free(reinterpret_cast<void*>(data));
+}
+
+TEST_SVE(sve_ld1b_64bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kBRegSize,
+                                        kDRegSize,
+                                        &MacroAssembler::Ld1b,
+                                        false);
+}
+
+TEST_SVE(sve_ld1h_64bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kHRegSize,
+                                        kDRegSize,
+                                        &MacroAssembler::Ld1h,
+                                        false);
+}
+
+TEST_SVE(sve_ld1w_64bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kSRegSize,
+                                        kDRegSize,
+                                        &MacroAssembler::Ld1w,
+                                        false);
+}
+
+TEST_SVE(sve_ld1d_64bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kDRegSize,
+                                        kDRegSize,
+                                        &MacroAssembler::Ld1d,
+                                        false);
+}
+
+TEST_SVE(sve_ld1sb_64bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kBRegSize,
+                                        kDRegSize,
+                                        &MacroAssembler::Ld1sb,
+                                        true);
+}
+
+TEST_SVE(sve_ld1sh_64bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kHRegSize,
+                                        kDRegSize,
+                                        &MacroAssembler::Ld1sh,
+                                        true);
+}
+
+TEST_SVE(sve_ld1sw_64bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kSRegSize,
+                                        kDRegSize,
+                                        &MacroAssembler::Ld1sw,
+                                        true);
+}
+
+TEST_SVE(sve_ld1b_32bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kBRegSize,
+                                        kSRegSize,
+                                        &MacroAssembler::Ld1b,
+                                        false);
+}
+
+TEST_SVE(sve_ld1h_32bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kHRegSize,
+                                        kSRegSize,
+                                        &MacroAssembler::Ld1h,
+                                        false);
+}
+
+TEST_SVE(sve_ld1w_32bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kSRegSize,
+                                        kSRegSize,
+                                        &MacroAssembler::Ld1w,
+                                        false);
+}
+
+TEST_SVE(sve_ld1sb_32bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kBRegSize,
+                                        kSRegSize,
+                                        &MacroAssembler::Ld1sb,
+                                        true);
+}
+
+TEST_SVE(sve_ld1sh_32bit_vector_plus_immediate) {
+  GatherLoadScalarPlusScalarOrImmHelper(config,
+                                        kHRegSize,
+                                        kSRegSize,
+                                        &MacroAssembler::Ld1sh,
+                                        true);
+}
+
+TEST_SVE(sve_ld1_scalar_plus_vector_32_scaled_offset) {
+  auto ld1_32_scaled_offset_helper =
+      std::bind(&GatherLoadScalarPlusVectorHelper<Extend>,
+                config,
+                std::placeholders::_1,
+                kSRegSize,
+                std::placeholders::_2,
+                std::placeholders::_3,
+                std::placeholders::_4,
+                std::placeholders::_5,
+                true);
+
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  ld1_32_scaled_offset_helper(kHRegSize, ld1h, ldff1h, UXTW, false);
+  ld1_32_scaled_offset_helper(kHRegSize, ld1h, ldff1h, SXTW, false);
+
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  ld1_32_scaled_offset_helper(kSRegSize, ld1w, ldff1w, UXTW, false);
+  ld1_32_scaled_offset_helper(kSRegSize, ld1w, ldff1w, SXTW, false);
+
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  ld1_32_scaled_offset_helper(kHRegSize, ld1sh, ldff1sh, UXTW, true);
+  ld1_32_scaled_offset_helper(kHRegSize, ld1sh, ldff1sh, SXTW, true);
+}
+
+TEST_SVE(sve_ld1_scalar_plus_vector_32_unscaled_offset) {
+  auto ld1_32_unscaled_offset_helper =
+      std::bind(&GatherLoadScalarPlusVectorHelper<Extend>,
+                config,
+                std::placeholders::_1,
+                kSRegSize,
+                std::placeholders::_2,
+                std::placeholders::_3,
+                std::placeholders::_4,
+                std::placeholders::_5,
+                false);
+
+  Ld1Macro ld1b = &MacroAssembler::Ld1b;
+  Ld1Macro ldff1b = &MacroAssembler::Ldff1b;
+  ld1_32_unscaled_offset_helper(kBRegSize, ld1b, ldff1b, UXTW, false);
+  ld1_32_unscaled_offset_helper(kBRegSize, ld1b, ldff1b, SXTW, false);
+
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  ld1_32_unscaled_offset_helper(kHRegSize, ld1h, ldff1h, UXTW, false);
+  ld1_32_unscaled_offset_helper(kHRegSize, ld1h, ldff1h, SXTW, false);
+
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  ld1_32_unscaled_offset_helper(kSRegSize, ld1w, ldff1w, UXTW, false);
+  ld1_32_unscaled_offset_helper(kSRegSize, ld1w, ldff1w, SXTW, false);
+
+  Ld1Macro ld1sb = &MacroAssembler::Ld1sb;
+  Ld1Macro ldff1sb = &MacroAssembler::Ldff1sb;
+  ld1_32_unscaled_offset_helper(kBRegSize, ld1sb, ldff1sb, UXTW, true);
+  ld1_32_unscaled_offset_helper(kBRegSize, ld1sb, ldff1sb, SXTW, true);
+
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  ld1_32_unscaled_offset_helper(kHRegSize, ld1sh, ldff1sh, UXTW, true);
+  ld1_32_unscaled_offset_helper(kHRegSize, ld1sh, ldff1sh, SXTW, true);
+}
+
+TEST_SVE(sve_ld1_scalar_plus_vector_32_unpacked_scaled_offset) {
+  auto ld1_32_unpacked_scaled_offset_helper =
+      std::bind(&GatherLoadScalarPlusVectorHelper<Extend>,
+                config,
+                std::placeholders::_1,
+                kDRegSize,
+                std::placeholders::_2,
+                std::placeholders::_3,
+                std::placeholders::_4,
+                std::placeholders::_5,
+                true);
+
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  ld1_32_unpacked_scaled_offset_helper(kHRegSize, ld1h, ldff1h, UXTW, false);
+  ld1_32_unpacked_scaled_offset_helper(kHRegSize, ld1h, ldff1h, SXTW, false);
+
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  ld1_32_unpacked_scaled_offset_helper(kSRegSize, ld1w, ldff1w, UXTW, false);
+  ld1_32_unpacked_scaled_offset_helper(kSRegSize, ld1w, ldff1w, SXTW, false);
+
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  ld1_32_unpacked_scaled_offset_helper(kDRegSize, ld1d, ldff1d, UXTW, false);
+  ld1_32_unpacked_scaled_offset_helper(kDRegSize, ld1d, ldff1d, SXTW, false);
+
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  ld1_32_unpacked_scaled_offset_helper(kHRegSize, ld1sh, ldff1sh, UXTW, true);
+  ld1_32_unpacked_scaled_offset_helper(kHRegSize, ld1sh, ldff1sh, SXTW, true);
+
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  ld1_32_unpacked_scaled_offset_helper(kSRegSize, ld1sw, ldff1sw, UXTW, true);
+  ld1_32_unpacked_scaled_offset_helper(kSRegSize, ld1sw, ldff1sw, SXTW, true);
+}
+
+TEST_SVE(sve_ld1_scalar_plus_vector_32_unpacked_unscaled_offset) {
+  auto ld1_32_unpacked_unscaled_offset_helper =
+      std::bind(&GatherLoadScalarPlusVectorHelper<Extend>,
+                config,
+                std::placeholders::_1,
+                kDRegSize,
+                std::placeholders::_2,
+                std::placeholders::_3,
+                std::placeholders::_4,
+                std::placeholders::_5,
+                false);
+
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  ld1_32_unpacked_unscaled_offset_helper(kHRegSize, ld1h, ldff1h, UXTW, false);
+  ld1_32_unpacked_unscaled_offset_helper(kHRegSize, ld1h, ldff1h, SXTW, false);
+
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  ld1_32_unpacked_unscaled_offset_helper(kSRegSize, ld1w, ldff1w, UXTW, false);
+  ld1_32_unpacked_unscaled_offset_helper(kSRegSize, ld1w, ldff1w, SXTW, false);
+
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  ld1_32_unpacked_unscaled_offset_helper(kDRegSize, ld1d, ldff1d, UXTW, false);
+  ld1_32_unpacked_unscaled_offset_helper(kDRegSize, ld1d, ldff1d, SXTW, false);
+
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  ld1_32_unpacked_unscaled_offset_helper(kHRegSize, ld1sh, ldff1sh, UXTW, true);
+  ld1_32_unpacked_unscaled_offset_helper(kHRegSize, ld1sh, ldff1sh, SXTW, true);
+
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  ld1_32_unpacked_unscaled_offset_helper(kSRegSize, ld1sw, ldff1sw, UXTW, true);
+  ld1_32_unpacked_unscaled_offset_helper(kSRegSize, ld1sw, ldff1sw, SXTW, true);
+}
+
+TEST_SVE(sve_ld1_scalar_plus_vector_64_scaled_offset) {
+  auto ld1_64_scaled_offset_helper =
+      std::bind(&GatherLoadScalarPlusVectorHelper<Shift>,
+                config,
+                std::placeholders::_1,
+                kDRegSize,
+                std::placeholders::_2,
+                std::placeholders::_3,
+                LSL,
+                std::placeholders::_4,
+                true);
+
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  ld1_64_scaled_offset_helper(kHRegSize, ld1h, ldff1h, false);
+
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  ld1_64_scaled_offset_helper(kSRegSize, ld1w, ldff1w, false);
+
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  ld1_64_scaled_offset_helper(kDRegSize, ld1d, ldff1d, false);
+
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  ld1_64_scaled_offset_helper(kHRegSize, ld1sh, ldff1sh, true);
+
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  ld1_64_scaled_offset_helper(kSRegSize, ld1sw, ldff1sw, true);
+}
+
+TEST_SVE(sve_ld1_scalar_plus_vector_64_unscaled_offset) {
+  auto ld1_64_unscaled_offset_helper =
+      std::bind(&GatherLoadScalarPlusVectorHelper<Shift>,
+                config,
+                std::placeholders::_1,
+                kDRegSize,
+                std::placeholders::_2,
+                std::placeholders::_3,
+                NO_SHIFT,
+                std::placeholders::_4,
+                false);
+
+  Ld1Macro ld1b = &MacroAssembler::Ld1b;
+  Ld1Macro ldff1b = &MacroAssembler::Ldff1b;
+  ld1_64_unscaled_offset_helper(kBRegSize, ld1b, ldff1b, false);
+
+  Ld1Macro ld1h = &MacroAssembler::Ld1h;
+  Ld1Macro ldff1h = &MacroAssembler::Ldff1h;
+  ld1_64_unscaled_offset_helper(kHRegSize, ld1h, ldff1h, false);
+
+  Ld1Macro ld1w = &MacroAssembler::Ld1w;
+  Ld1Macro ldff1w = &MacroAssembler::Ldff1w;
+  ld1_64_unscaled_offset_helper(kSRegSize, ld1w, ldff1w, false);
+
+  Ld1Macro ld1d = &MacroAssembler::Ld1d;
+  Ld1Macro ldff1d = &MacroAssembler::Ldff1d;
+  ld1_64_unscaled_offset_helper(kDRegSize, ld1d, ldff1d, false);
+
+  Ld1Macro ld1sb = &MacroAssembler::Ld1sb;
+  Ld1Macro ldff1sb = &MacroAssembler::Ldff1sb;
+  ld1_64_unscaled_offset_helper(kBRegSize, ld1sb, ldff1sb, true);
+
+  Ld1Macro ld1sh = &MacroAssembler::Ld1sh;
+  Ld1Macro ldff1sh = &MacroAssembler::Ldff1sh;
+  ld1_64_unscaled_offset_helper(kHRegSize, ld1sh, ldff1sh, true);
+
+  Ld1Macro ld1sw = &MacroAssembler::Ld1sw;
+  Ld1Macro ldff1sw = &MacroAssembler::Ldff1sw;
+  ld1_64_unscaled_offset_helper(kSRegSize, ld1sw, ldff1sw, true);
+}
+
+TEST_SVE(sve_ldnt1) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int data_size = kZRegMaxSizeInBytes * 16;
+  uint8_t* data = new uint8_t[data_size];
+  for (int i = 0; i < data_size; i++) {
+    data[i] = i & 0xff;
+  }
+
+  // Set the base half-way through the buffer so we can use negative indices.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+  __ Ptrue(p0.VnB());
+  __ Punpklo(p1.VnH(), p0.VnB());
+  __ Punpklo(p2.VnH(), p1.VnB());
+  __ Punpklo(p3.VnH(), p2.VnB());
+  __ Punpklo(p4.VnH(), p3.VnB());
+
+  __ Mov(x1, 42);
+  __ Ld1b(z0.VnB(), p1.Zeroing(), SVEMemOperand(x0, x1));
+  __ Ldnt1b(z1.VnB(), p1.Zeroing(), SVEMemOperand(x0, x1));
+
+  __ Mov(x1, -21);
+  __ Ld1h(z2.VnH(), p2.Zeroing(), SVEMemOperand(x0, x1, LSL, 1));
+  __ Ldnt1h(z3.VnH(), p2.Zeroing(), SVEMemOperand(x0, x1, LSL, 1));
+
+  __ Mov(x1, 10);
+  __ Ld1w(z4.VnS(), p3.Zeroing(), SVEMemOperand(x0, x1, LSL, 2));
+  __ Ldnt1w(z5.VnS(), p3.Zeroing(), SVEMemOperand(x0, x1, LSL, 2));
+
+  __ Mov(x1, -5);
+  __ Ld1d(z6.VnD(), p4.Zeroing(), SVEMemOperand(x0, x1, LSL, 3));
+  __ Ldnt1d(z7.VnD(), p4.Zeroing(), SVEMemOperand(x0, x1, LSL, 3));
+
+  __ Ld1b(z8.VnB(), p1.Zeroing(), SVEMemOperand(x0, 1, SVE_MUL_VL));
+  __ Ldnt1b(z9.VnB(), p1.Zeroing(), SVEMemOperand(x0, 1, SVE_MUL_VL));
+
+  __ Ld1h(z10.VnH(), p2.Zeroing(), SVEMemOperand(x0, -1, SVE_MUL_VL));
+  __ Ldnt1h(z11.VnH(), p2.Zeroing(), SVEMemOperand(x0, -1, SVE_MUL_VL));
+
+  __ Ld1w(z12.VnS(), p3.Zeroing(), SVEMemOperand(x0, 7, SVE_MUL_VL));
+  __ Ldnt1w(z13.VnS(), p3.Zeroing(), SVEMemOperand(x0, 7, SVE_MUL_VL));
+
+  __ Ld1d(z14.VnD(), p4.Zeroing(), SVEMemOperand(x0, -8, SVE_MUL_VL));
+  __ Ldnt1d(z15.VnD(), p4.Zeroing(), SVEMemOperand(x0, -8, SVE_MUL_VL));
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(z0, z1);
+    ASSERT_EQUAL_SVE(z2, z3);
+    ASSERT_EQUAL_SVE(z4, z5);
+    ASSERT_EQUAL_SVE(z6, z7);
+    ASSERT_EQUAL_SVE(z8, z9);
+    ASSERT_EQUAL_SVE(z10, z11);
+    ASSERT_EQUAL_SVE(z12, z13);
+    ASSERT_EQUAL_SVE(z14, z15);
+  }
+}
+
+TEST_SVE(sve_stnt1) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int data_size = kZRegMaxSizeInBytes * 16;
+  uint8_t* data = new uint8_t[data_size];
+
+  // Set the base half-way through the buffer so we can use negative indices.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+  __ Ptrue(p0.VnB());
+  __ Punpklo(p1.VnH(), p0.VnB());
+  __ Punpklo(p2.VnH(), p1.VnB());
+  __ Punpklo(p3.VnH(), p2.VnB());
+  __ Punpklo(p4.VnH(), p3.VnB());
+  __ Dup(z0.VnB(), 0x55);
+  __ Index(z1.VnB(), 0, 1);
+
+  // Store with all-true and patterned predication, load back, and create a
+  // reference value for later comparison.
+  __ Rdvl(x1, 1);
+  __ Stnt1b(z0.VnB(), p0, SVEMemOperand(x0, x1));
+  __ Stnt1b(z1.VnB(), p1, SVEMemOperand(x0, 1, SVE_MUL_VL));
+  __ Ld1b(z2.VnB(), p0.Zeroing(), SVEMemOperand(x0, x1));
+  __ Sel(z3.VnB(), p1, z1.VnB(), z0.VnB());
+
+  // Repeated, with wider elements and different offsets.
+  __ Rdvl(x1, -1);
+  __ Lsr(x1, x1, 1);
+  __ Stnt1h(z0.VnH(), p0, SVEMemOperand(x0, x1, LSL, 1));
+  __ Stnt1h(z1.VnH(), p2, SVEMemOperand(x0, -1, SVE_MUL_VL));
+  __ Ld1b(z4.VnB(), p0.Zeroing(), SVEMemOperand(x0, x1, LSL, 1));
+  __ Sel(z5.VnH(), p2, z1.VnH(), z0.VnH());
+
+  __ Rdvl(x1, 7);
+  __ Lsr(x1, x1, 2);
+  __ Stnt1w(z0.VnS(), p0, SVEMemOperand(x0, x1, LSL, 2));
+  __ Stnt1w(z1.VnS(), p3, SVEMemOperand(x0, 7, SVE_MUL_VL));
+  __ Ld1b(z6.VnB(), p0.Zeroing(), SVEMemOperand(x0, x1, LSL, 2));
+  __ Sel(z7.VnS(), p3, z1.VnS(), z0.VnS());
+
+  __ Rdvl(x1, -8);
+  __ Lsr(x1, x1, 3);
+  __ Stnt1d(z0.VnD(), p0, SVEMemOperand(x0, x1, LSL, 3));
+  __ Stnt1d(z1.VnD(), p4, SVEMemOperand(x0, -8, SVE_MUL_VL));
+  __ Ld1b(z8.VnB(), p0.Zeroing(), SVEMemOperand(x0, x1, LSL, 3));
+  __ Sel(z9.VnD(), p4, z1.VnD(), z0.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(z2, z3);
+    ASSERT_EQUAL_SVE(z4, z5);
+    ASSERT_EQUAL_SVE(z6, z7);
+    ASSERT_EQUAL_SVE(z8, z9);
+  }
+}
+
+TEST_SVE(sve_ld1rq) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int data_size = (kQRegSizeInBytes + 128) * 2;
+  uint8_t* data = new uint8_t[data_size];
+  for (int i = 0; i < data_size; i++) {
+    data[i] = i & 0xff;
+  }
+
+  // Set the base half-way through the buffer so we can use negative indices.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+
+  __ Index(z0.VnB(), 0, 1);
+  __ Ptrue(p0.VnB());
+  __ Cmplo(p0.VnB(), p0.Zeroing(), z0.VnB(), 4);
+  __ Pfalse(p1.VnB());
+  __ Zip1(p1.VnB(), p0.VnB(), p1.VnB());
+
+  // Load and broadcast using scalar offsets.
+  __ Mov(x1, -42);
+  __ Ld1rqb(z0.VnB(), p1.Zeroing(), SVEMemOperand(x0, x1));
+
+  __ Add(x2, x0, 1);
+  __ Mov(x1, -21);
+  __ Punpklo(p2.VnH(), p1.VnB());
+  __ Ld1rqh(z1.VnH(), p2.Zeroing(), SVEMemOperand(x2, x1, LSL, 1));
+
+  __ Add(x2, x2, 1);
+  __ Mov(x1, -10);
+  __ Punpklo(p3.VnH(), p2.VnB());
+  __ Ld1rqw(z2.VnS(), p3.Zeroing(), SVEMemOperand(x2, x1, LSL, 2));
+
+  __ Add(x2, x2, 1);
+  __ Mov(x1, 5);
+  __ Punpklo(p4.VnH(), p3.VnB());
+  __ Ld1rqd(z3.VnD(), p4.Zeroing(), SVEMemOperand(x2, x1, LSL, 3));
+
+  // Check that all segments match by rotating the vector by one segment,
+  // eoring, and orring across the vector.
+  __ Ext(z4.VnB(), z0.VnB(), z0.VnB(), 16);
+  __ Eor(z4.VnB(), z4.VnB(), z0.VnB());
+  __ Orv(b4, p0, z4.VnB());
+  __ Ext(z5.VnB(), z1.VnB(), z1.VnB(), 16);
+  __ Eor(z5.VnB(), z5.VnB(), z1.VnB());
+  __ Orv(b5, p0, z5.VnB());
+  __ Orr(z4, z4, z5);
+  __ Ext(z5.VnB(), z2.VnB(), z2.VnB(), 16);
+  __ Eor(z5.VnB(), z5.VnB(), z2.VnB());
+  __ Orv(b5, p0, z5.VnB());
+  __ Orr(z4, z4, z5);
+  __ Ext(z5.VnB(), z3.VnB(), z3.VnB(), 16);
+  __ Eor(z5.VnB(), z5.VnB(), z3.VnB());
+  __ Orv(b5, p0, z5.VnB());
+  __ Orr(z4, z4, z5);
+
+  // Load and broadcast the same values, using immediate offsets.
+  __ Add(x1, x0, 6);
+  __ Ld1rqb(z5.VnB(), p1.Zeroing(), SVEMemOperand(x1, -48));
+  __ Add(x1, x0, -9);
+  __ Ld1rqh(z6.VnH(), p2.Zeroing(), SVEMemOperand(x1, -32));
+  __ Add(x1, x0, -70);
+  __ Ld1rqw(z7.VnS(), p3.Zeroing(), SVEMemOperand(x1, 32));
+  __ Add(x1, x0, 27);
+  __ Ld1rqd(z8.VnD(), p4.Zeroing(), SVEMemOperand(x1, 16));
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z0[] = {0x0000000000000000, 0x006c006a00680066};
+    uint64_t expected_z1[] = {0x000074730000706f, 0x00006c6b00006867};
+    uint64_t expected_z2[] = {0x0000000075747372, 0x000000006d6c6b6a};
+    uint64_t expected_z3[] = {0x0000000000000000, 0xc2c1c0bfbebdbcbb};
+    uint64_t expected_z4[] = {0, 0};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    ASSERT_EQUAL_SVE(z0, z5);
+    ASSERT_EQUAL_SVE(z1, z6);
+    ASSERT_EQUAL_SVE(z2, z7);
+    ASSERT_EQUAL_SVE(z3, z8);
+  }
+}
+
+TEST_SVE(sve_st1_vec_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kNEON, CPUFeatures::kSVE);
+  START();
+
+  // TODO: Use mmap() to request a buffer in the low 4GB, which allows testing
+  // 32-bit address vectors.
+  int data_size = kZRegMaxSizeInBytes * 16;
+  uint8_t* data = new uint8_t[data_size];
+
+  // Set the base to 16 bytes from the end of the buffer so we can use negative
+  // indices.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size - 16]));
+  __ Ptrue(p0.VnB());
+
+  // Store a vector of index values in reverse order, using
+  // vector-plus-immediate addressing to begin at byte 15, then storing to
+  // bytes 14, 13, etc.
+  __ Index(z1.VnD(), x0, -1);
+  __ Index(z2.VnD(), 0, 1);
+
+  // Iterate in order to store at least 16 bytes. The number of iterations
+  // depends on VL, eg. VL128 iterates eight times, storing bytes 15 and 14
+  // on the first iteration, 13 and 12 on the next, etc.
+  uint64_t dlanes = config->sve_vl_in_bytes() / kDRegSizeInBytes;
+  for (int i = 15; i >= 0; i -= dlanes * kBRegSizeInBytes) {
+    __ St1b(z2.VnD(), p0, SVEMemOperand(z1.VnD(), i));
+    __ Incd(z2.VnD());
+  }
+
+  // Reload the stored data, and build a reference for comparison. The reference
+  // is truncated to a Q register, as only the least-significant 128 bits are
+  // checked.
+  __ Ldr(q4, MemOperand(x0));
+  __ Index(z5.VnB(), 15, -1);
+  __ Mov(q5, q5);
+
+  // Repeat for wider elements.
+  __ Index(z1.VnD(), x0, -2);  // Stepping by -2 for H-sized elements.
+  __ Index(z2.VnD(), 0, 1);
+  for (int i = 14; i >= 0; i -= dlanes * kHRegSizeInBytes) {
+    __ St1h(z2.VnD(), p0, SVEMemOperand(z1.VnD(), i));
+    __ Incd(z2.VnD());
+  }
+  __ Ldr(q6, MemOperand(x0));
+  __ Index(z7.VnH(), 7, -1);
+  __ Mov(q7, q7);
+
+  __ Index(z1.VnD(), x0, -4);  // Stepping by -4 for S-sized elements.
+  __ Index(z2.VnD(), 0, 1);
+  for (int i = 12; i >= 0; i -= dlanes * kSRegSizeInBytes) {
+    __ St1w(z2.VnD(), p0, SVEMemOperand(z1.VnD(), i));
+    __ Incd(z2.VnD());
+  }
+  __ Ldr(q8, MemOperand(x0));
+  __ Index(z9.VnS(), 3, -1);
+  __ Mov(q9, q9);
+
+  __ Index(z1.VnD(), x0, -8);  // Stepping by -8 for D-sized elements.
+  __ Index(z2.VnD(), 0, 1);
+  for (int i = 8; i >= 0; i -= dlanes * kDRegSizeInBytes) {
+    __ St1d(z2.VnD(), p0, SVEMemOperand(z1.VnD(), i));
+    __ Incd(z2.VnD());
+  }
+  __ Ldr(q10, MemOperand(x0));
+  __ Index(z11.VnD(), 1, -1);
+  __ Mov(q11, q11);
+
+  // Test predication by storing even halfwords to memory (using predication)
+  // at byte-separated addresses. The result should be the same as storing
+  // even halfwords contiguously to memory.
+  __ Pfalse(p1.VnB());
+  __ Zip1(p1.VnD(), p0.VnD(), p1.VnD());
+  __ Mov(x0, reinterpret_cast<uintptr_t>(data));
+  __ Index(z1.VnD(), x0, 1);
+  __ Index(z2.VnD(), 0x1000, 1);
+  for (int i = 0; i < 16; i += dlanes) {
+    __ St1h(z2.VnD(), p1, SVEMemOperand(z1.VnD(), i));
+    __ Incd(z2.VnD());
+  }
+  __ Ldr(q2, MemOperand(x0));
+  __ Index(z3.VnH(), 0x1000, 2);
+  __ Mov(q3, q3);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(z3, z2);
+    ASSERT_EQUAL_SVE(z5, z4);
+    ASSERT_EQUAL_SVE(z7, z6);
+    ASSERT_EQUAL_SVE(z9, z8);
+    ASSERT_EQUAL_SVE(z11, z10);
+  }
+}
+
+template <typename T>
+static void sve_st1_scalar_plus_vector_helper(Test* config,
+                                              int esize_in_bits,
+                                              T mod,
+                                              bool is_scaled) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int vl = config->sve_vl_in_bytes();
+  int data_size = vl * 160;
+  uint8_t* data = new uint8_t[data_size];
+  memset(data, 0, data_size);
+  int vl_per_esize = vl / (esize_in_bits / kBitsPerByte);
+
+  ZRegister zn_b = z0.WithLaneSize(esize_in_bits);
+  ZRegister zn_h = z1.WithLaneSize(esize_in_bits);
+  ZRegister zn_s = z2.WithLaneSize(esize_in_bits);
+  ZRegister zn_d = z3.WithLaneSize(esize_in_bits);
+
+  ZRegister zn_ld_b = z10.WithLaneSize(esize_in_bits);
+  ZRegister zn_ld_h = z11.WithLaneSize(esize_in_bits);
+  ZRegister zn_ld_s = z12.WithLaneSize(esize_in_bits);
+  ZRegister zn_ld_d = z13.WithLaneSize(esize_in_bits);
+  ZRegister offsets = z31.WithLaneSize(esize_in_bits);
+
+  // Set the base half-way through the buffer so we can use negative indices.
+  __ Mov(x0, reinterpret_cast<uintptr_t>(&data[data_size / 2]));
+  __ Ptrue(p6.WithLaneSize(esize_in_bits));
+  __ Pfalse(p7.WithLaneSize(esize_in_bits));
+  __ Zip1(p0.WithLaneSize(esize_in_bits),
+          p6.WithLaneSize(esize_in_bits),
+          p7.WithLaneSize(esize_in_bits));
+  __ Zip1(p1.WithLaneSize(esize_in_bits),
+          p7.WithLaneSize(esize_in_bits),
+          p6.WithLaneSize(esize_in_bits));
+
+  // `st1b` doesn't have the scaled-offset forms.
+  if (is_scaled == false) {
+    // Simply stepping the index by 2 to simulate a scatter memory access.
+    __ Index(offsets, 1, 2);
+    __ St1b(offsets, p0, SVEMemOperand(x0, offsets, mod));
+    __ Ld1b(zn_ld_b, p0.Zeroing(), SVEMemOperand(x0, offsets, mod));
+    __ Dup(zn_b, 0);
+    __ Mov(zn_b, p0.Merging(), offsets);
+  }
+
+  // Store the values to isolated range different with other stores.
+  int scale = is_scaled ? 1 : 0;
+  __ Add(x1, x0, vl_per_esize * 4);
+  __ Index(offsets, 6, 4);
+  __ St1h(offsets, p0, SVEMemOperand(x1, offsets, mod, scale));
+  __ Ld1h(zn_ld_h, p0.Zeroing(), SVEMemOperand(x1, offsets, mod, scale));
+  __ Dup(zn_h, 0);
+  __ Mov(zn_h, p0.Merging(), offsets);
+
+  scale = is_scaled ? 2 : 0;
+  __ Add(x2, x0, UINT64_MAX + (vl_per_esize * -8) + 1);
+  __ Index(offsets, 64, 8);
+  if ((std::is_same<T, vixl::aarch64::Extend>::value) &&
+      (static_cast<int>(mod) == SXTW)) {
+    // Testing negative offsets.
+    __ Neg(offsets, p6.Merging(), offsets);
+  }
+  __ St1w(offsets, p1, SVEMemOperand(x2, offsets, mod, scale));
+  __ Ld1w(zn_ld_s, p1.Zeroing(), SVEMemOperand(x2, offsets, mod, scale));
+  __ Dup(zn_s, 0);
+  __ Mov(zn_s, p1.Merging(), offsets);
+
+  if (esize_in_bits == kDRegSize) {
+    // Test st1w by comparing the 32-bit value loaded correspondingly with the
+    // 32-bit value stored.
+    __ Lsl(zn_s, zn_s, kSRegSize);
+    __ Lsr(zn_s, zn_s, kSRegSize);
+  }
+
+  // `st1d` doesn't have the S-sized lane forms.
+  if (esize_in_bits == kDRegSize) {
+    scale = is_scaled ? 3 : 0;
+    __ Add(x3, x0, UINT64_MAX + (vl_per_esize * -16) + 1);
+    __ Index(offsets, 128, 16);
+    if ((std::is_same<T, vixl::aarch64::Extend>::value) &&
+        (static_cast<int>(mod) == SXTW)) {
+      __ Neg(offsets, p6.Merging(), offsets);
+    }
+    __ St1d(offsets, p1, SVEMemOperand(x3, offsets, mod, scale));
+    __ Ld1d(zn_ld_d, p1.Zeroing(), SVEMemOperand(x3, offsets, mod, scale));
+    __ Dup(zn_d, 0);
+    __ Mov(zn_d, p1.Merging(), offsets);
+  }
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    if (scale == false) {
+      ASSERT_EQUAL_SVE(zn_ld_b, zn_b);
+    }
+
+    ASSERT_EQUAL_SVE(zn_ld_h, zn_h);
+    ASSERT_EQUAL_SVE(zn_ld_s, zn_s);
+
+    if (esize_in_bits == kDRegSize) {
+      ASSERT_EQUAL_SVE(zn_ld_d, zn_d);
+    }
+  }
+
+  delete[] data;
+}
+
+TEST_SVE(sve_st1_sca_vec_32_unpacked_unscaled) {
+  sve_st1_scalar_plus_vector_helper(config, kDRegSize, UXTW, false);
+  sve_st1_scalar_plus_vector_helper(config, kDRegSize, SXTW, false);
+}
+
+TEST_SVE(sve_st1_sca_vec_32_unpacked_scaled) {
+  sve_st1_scalar_plus_vector_helper(config, kDRegSize, UXTW, true);
+  sve_st1_scalar_plus_vector_helper(config, kDRegSize, SXTW, true);
+}
+
+TEST_SVE(sve_st1_sca_vec_32_unscaled) {
+  sve_st1_scalar_plus_vector_helper(config, kSRegSize, UXTW, false);
+  sve_st1_scalar_plus_vector_helper(config, kSRegSize, SXTW, false);
+}
+
+TEST_SVE(sve_st1_sca_vec_32_scaled) {
+  sve_st1_scalar_plus_vector_helper(config, kSRegSize, UXTW, true);
+  sve_st1_scalar_plus_vector_helper(config, kSRegSize, SXTW, true);
+}
+
+TEST_SVE(sve_st1_sca_vec_64_scaled) {
+  sve_st1_scalar_plus_vector_helper(config, kDRegSize, LSL, true);
+}
+
+TEST_SVE(sve_st1_sca_vec_64_unscaled) {
+  sve_st1_scalar_plus_vector_helper(config, kDRegSize, NO_SHIFT, false);
+}
+
+typedef void (MacroAssembler::*IntWideImmFn)(const ZRegister& zd,
+                                             const ZRegister& zn,
+                                             const IntegerOperand imm);
+
+template <typename F, typename Td, typename Tn>
+static void IntWideImmHelper(Test* config,
+                             F macro,
+                             unsigned lane_size_in_bits,
+                             const Tn& zn_inputs,
+                             IntegerOperand imm,
+                             const Td& zd_expected) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  ZRegister zd1 = z0.WithLaneSize(lane_size_in_bits);
+  InsrHelper(&masm, zd1, zn_inputs);
+
+  // Also test with a different zn, to test the movprfx case.
+  ZRegister zn = z1.WithLaneSize(lane_size_in_bits);
+  InsrHelper(&masm, zn, zn_inputs);
+  ZRegister zd2 = z2.WithLaneSize(lane_size_in_bits);
+  ZRegister zn_copy = z3.WithSameLaneSizeAs(zn);
+
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(zn_copy, zn);
+
+  {
+    UseScratchRegisterScope temps(&masm);
+    // The MacroAssembler needs a P scratch register for some of these macros,
+    // and it doesn't have one by default.
+    temps.Include(p3);
+
+    (masm.*macro)(zd1, zd1, imm);
+    (masm.*macro)(zd2, zn, imm);
+  }
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(zd_expected, zd1);
+
+    // Check the result from `instr` with movprfx is the same as
+    // the immediate version.
+    ASSERT_EQUAL_SVE(zd_expected, zd2);
+
+    ASSERT_EQUAL_SVE(zn_copy, zn);
+  }
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_smax) {
+  int in_b[] = {0, -128, 127, -127, 126, 1, -1, 55};
+  int in_h[] = {0, -128, 127, INT16_MIN, INT16_MAX, 1, -1, 5555};
+  int in_s[] = {0, -128, 127, INT32_MIN, INT32_MAX, 1, -1, 555555};
+  int64_t in_d[] = {1, 10, 10000, 1000000};
+
+  IntWideImmFn fn = &MacroAssembler::Smax;
+
+  int exp_b_1[] = {0, -1, 127, -1, 126, 1, -1, 55};
+  int exp_h_1[] = {127, 127, 127, 127, INT16_MAX, 127, 127, 5555};
+  int exp_s_1[] = {0, -128, 127, -128, INT32_MAX, 1, -1, 555555};
+  int64_t exp_d_1[] = {99, 99, 10000, 1000000};
+
+  IntWideImmHelper(config, fn, kBRegSize, in_b, -1, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 127, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, -128, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 99, exp_d_1);
+
+  int exp_h_2[] = {0, -128, 127, -255, INT16_MAX, 1, -1, 5555};
+  int exp_s_2[] = {2048, 2048, 2048, 2048, INT32_MAX, 2048, 2048, 555555};
+  int64_t exp_d_2[] = {INT16_MAX, INT16_MAX, INT16_MAX, 1000000};
+
+  // The immediate is in the range [-128, 127], but the macro is able to
+  // synthesise unencodable immediates.
+  // B-sized lanes cannot take an immediate out of the range [-128, 127].
+  IntWideImmHelper(config, fn, kHRegSize, in_h, -255, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 2048, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, INT16_MAX, exp_d_2);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_smin) {
+  int in_b[] = {0, -128, 127, -127, 126, 1, -1, 55};
+  int in_h[] = {0, -128, 127, INT16_MIN, INT16_MAX, 1, -1, 5555};
+  int in_s[] = {0, -128, 127, INT32_MIN, INT32_MAX, 1, -1, 555555};
+  int64_t in_d[] = {1, 10, 10000, 1000000};
+
+  IntWideImmFn fn = &MacroAssembler::Smin;
+
+  int exp_b_1[] = {-1, -128, -1, -127, -1, -1, -1, -1};
+  int exp_h_1[] = {0, -128, 127, INT16_MIN, 127, 1, -1, 127};
+  int exp_s_1[] = {-128, -128, -128, INT32_MIN, -128, -128, -128, -128};
+  int64_t exp_d_1[] = {1, 10, 99, 99};
+
+  IntWideImmHelper(config, fn, kBRegSize, in_b, -1, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 127, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, -128, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 99, exp_d_1);
+
+  int exp_h_2[] = {-255, -255, -255, INT16_MIN, -255, -255, -255, -255};
+  int exp_s_2[] = {0, -128, 127, INT32_MIN, 2048, 1, -1, 2048};
+  int64_t exp_d_2[] = {1, 10, 10000, INT16_MAX};
+
+  // The immediate is in the range [-128, 127], but the macro is able to
+  // synthesise unencodable immediates.
+  // B-sized lanes cannot take an immediate out of the range [-128, 127].
+  IntWideImmHelper(config, fn, kHRegSize, in_h, -255, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 2048, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, INT16_MAX, exp_d_2);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_umax) {
+  int in_b[] = {0, 255, 127, 0x80, 1, 55};
+  int in_h[] = {0, 255, 127, INT16_MAX, 1, 5555};
+  int in_s[] = {0, 0xff, 0x7f, INT32_MAX, 1, 555555};
+  int64_t in_d[] = {1, 10, 10000, 1000000};
+
+  IntWideImmFn fn = &MacroAssembler::Umax;
+
+  int exp_b_1[] = {17, 255, 127, 0x80, 17, 55};
+  int exp_h_1[] = {127, 255, 127, INT16_MAX, 127, 5555};
+  int exp_s_1[] = {255, 255, 255, INT32_MAX, 255, 555555};
+  int64_t exp_d_1[] = {99, 99, 10000, 1000000};
+
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 17, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 0x7f, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 0xff, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 99, exp_d_1);
+
+  int exp_h_2[] = {511, 511, 511, INT16_MAX, 511, 5555};
+  int exp_s_2[] = {2048, 2048, 2048, INT32_MAX, 2048, 555555};
+  int64_t exp_d_2[] = {INT16_MAX, INT16_MAX, INT16_MAX, 1000000};
+
+  // The immediate is in the range [0, 255], but the macro is able to
+  // synthesise unencodable immediates.
+  // B-sized lanes cannot take an immediate out of the range [0, 255].
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 511, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 2048, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, INT16_MAX, exp_d_2);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_umin) {
+  int in_b[] = {0, 255, 127, 0x80, 1, 55};
+  int in_h[] = {0, 255, 127, INT16_MAX, 1, 5555};
+  int in_s[] = {0, 0xff, 0x7f, INT32_MAX, 1, 555555};
+  int64_t in_d[] = {1, 10, 10000, 1000000};
+
+  IntWideImmFn fn = &MacroAssembler::Umin;
+
+  int exp_b_1[] = {0, 17, 17, 17, 1, 17};
+  int exp_h_1[] = {0, 127, 127, 127, 1, 127};
+  int exp_s_1[] = {0, 255, 127, 255, 1, 255};
+  int64_t exp_d_1[] = {1, 10, 99, 99};
+
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 17, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 0x7f, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 255, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 99, exp_d_1);
+
+  int exp_h_2[] = {0, 255, 127, 511, 1, 511};
+  int exp_s_2[] = {0, 255, 127, 2048, 1, 2048};
+  int64_t exp_d_2[] = {1, 10, 10000, INT16_MAX};
+
+  // The immediate is in the range [0, 255], but the macro is able to
+  // synthesise unencodable immediates.
+  // B-sized lanes cannot take an immediate out of the range [0, 255].
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 511, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 2048, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, INT16_MAX, exp_d_2);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_mul) {
+  int in_b[] = {11, -1, 7, -3};
+  int in_h[] = {111, -1, 17, -123};
+  int in_s[] = {11111, -1, 117, -12345};
+  int64_t in_d[] = {0x7fffffff, 0x80000000};
+
+  IntWideImmFn fn = &MacroAssembler::Mul;
+
+  int exp_b_1[] = {66, -6, 42, -18};
+  int exp_h_1[] = {-14208, 128, -2176, 15744};
+  int exp_s_1[] = {11111 * 127, -127, 117 * 127, -12345 * 127};
+  int64_t exp_d_1[] = {0xfffffffe, 0x100000000};
+
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 6, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, -128, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 2, exp_d_1);
+
+  int exp_h_2[] = {-28305, 255, -4335, 31365};
+  int exp_s_2[] = {22755328, -2048, 239616, -25282560};
+  int64_t exp_d_2[] = {0x00000063ffffff38, 0x0000006400000000};
+
+  // The immediate is in the range [-128, 127], but the macro is able to
+  // synthesise unencodable immediates.
+  // B-sized lanes cannot take an immediate out of the range [0, 255].
+  IntWideImmHelper(config, fn, kHRegSize, in_h, -255, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 2048, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 200, exp_d_2);
+
+  // Integer overflow on multiplication.
+  unsigned exp_b_3[] = {0x75, 0x81, 0x79, 0x83};
+
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 0x7f, exp_b_3);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_add) {
+  unsigned in_b[] = {0x81, 0x7f, 0x10, 0xff};
+  unsigned in_h[] = {0x8181, 0x7f7f, 0x1010, 0xaaaa};
+  unsigned in_s[] = {0x80018181, 0x7fff7f7f, 0xaaaaaaaa, 0xf000f0f0};
+  uint64_t in_d[] = {0x8000000180018181, 0x7fffffff7fff7f7f};
+
+  IntWideImmFn fn = &MacroAssembler::Add;
+
+  unsigned exp_b_1[] = {0x02, 0x00, 0x91, 0x80};
+  unsigned exp_h_1[] = {0x8191, 0x7f8f, 0x1020, 0xaaba};
+  unsigned exp_s_1[] = {0x80018200, 0x7fff7ffe, 0xaaaaab29, 0xf000f16f};
+  uint64_t exp_d_1[] = {0x8000000180018280, 0x7fffffff7fff807e};
+
+  // Encodable with `add` (shift 0).
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 0x81, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff, exp_d_1);
+
+  unsigned exp_h_2[] = {0x9181, 0x8f7f, 0x2010, 0xbaaa};
+  unsigned exp_s_2[] = {0x80020081, 0x7ffffe7f, 0xaaab29aa, 0xf0016ff0};
+  uint64_t exp_d_2[] = {0x8000000180028081, 0x7fffffff80007e7f};
+
+  // Encodable with `add` (shift 8).
+  // B-sized lanes cannot take a shift of 8.
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16 << 8, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127 << 8, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff << 8, exp_d_2);
+
+  unsigned exp_s_3[] = {0x80808181, 0x807e7f7f, 0xab29aaaa, 0xf07ff0f0};
+
+  // The macro is able to synthesise unencodable immediates.
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127 << 16, exp_s_3);
+
+  unsigned exp_b_4[] = {0x61, 0x5f, 0xf0, 0xdf};
+  unsigned exp_h_4[] = {0x6181, 0x5f7f, 0xf010, 0x8aaa};
+  unsigned exp_s_4[] = {0x00018181, 0xffff7f7f, 0x2aaaaaaa, 0x7000f0f0};
+  uint64_t exp_d_4[] = {0x8000000180018180, 0x7fffffff7fff7f7e};
+
+  // Negative immediates use `sub`.
+  IntWideImmHelper(config, fn, kBRegSize, in_b, -0x20, exp_b_4);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, -0x2000, exp_h_4);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, INT32_MIN, exp_s_4);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, -1, exp_d_4);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_sqadd) {
+  unsigned in_b[] = {0x81, 0x7f, 0x10, 0xff};
+  unsigned in_h[] = {0x8181, 0x7f7f, 0x1010, 0xaaaa};
+  unsigned in_s[] = {0x80018181, 0x7fff7f7f, 0xaaaaaaaa, 0xf000f0f0};
+  uint64_t in_d[] = {0x8000000180018181, 0x7fffffff7fff7f7f};
+
+  IntWideImmFn fn = &MacroAssembler::Sqadd;
+
+  unsigned exp_b_1[] = {0x02, 0x7f, 0x7f, 0x7f};
+  unsigned exp_h_1[] = {0x8191, 0x7f8f, 0x1020, 0xaaba};
+  unsigned exp_s_1[] = {0x80018200, 0x7fff7ffe, 0xaaaaab29, 0xf000f16f};
+  uint64_t exp_d_1[] = {0x8000000180018280, 0x7fffffff7fff807e};
+
+  // Encodable with `sqadd` (shift 0).
+  // Note that encodable immediates are unsigned, even for signed saturation.
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 129, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 255, exp_d_1);
+
+  unsigned exp_h_2[] = {0x9181, 0x7fff, 0x2010, 0xbaaa};
+  unsigned exp_s_2[] = {0x80020081, 0x7ffffe7f, 0xaaab29aa, 0xf0016ff0};
+  uint64_t exp_d_2[] = {0x8000000180028081, 0x7fffffff80007e7f};
+
+  // Encodable with `sqadd` (shift 8).
+  // B-sized lanes cannot take a shift of 8.
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16 << 8, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127 << 8, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff << 8, exp_d_2);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_uqadd) {
+  unsigned in_b[] = {0x81, 0x7f, 0x10, 0xff};
+  unsigned in_h[] = {0x8181, 0x7f7f, 0x1010, 0xaaaa};
+  unsigned in_s[] = {0x80018181, 0x7fff7f7f, 0xaaaaaaaa, 0xf000f0f0};
+  uint64_t in_d[] = {0x8000000180018181, 0x7fffffff7fff7f7f};
+
+  IntWideImmFn fn = &MacroAssembler::Uqadd;
+
+  unsigned exp_b_1[] = {0xff, 0xff, 0x91, 0xff};
+  unsigned exp_h_1[] = {0x8191, 0x7f8f, 0x1020, 0xaaba};
+  unsigned exp_s_1[] = {0x80018200, 0x7fff7ffe, 0xaaaaab29, 0xf000f16f};
+  uint64_t exp_d_1[] = {0x8000000180018280, 0x7fffffff7fff807e};
+
+  // Encodable with `uqadd` (shift 0).
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 0x81, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff, exp_d_1);
+
+  unsigned exp_h_2[] = {0x9181, 0x8f7f, 0x2010, 0xbaaa};
+  unsigned exp_s_2[] = {0x80020081, 0x7ffffe7f, 0xaaab29aa, 0xf0016ff0};
+  uint64_t exp_d_2[] = {0x8000000180028081, 0x7fffffff80007e7f};
+
+  // Encodable with `uqadd` (shift 8).
+  // B-sized lanes cannot take a shift of 8.
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16 << 8, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127 << 8, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff << 8, exp_d_2);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_sub) {
+  unsigned in_b[] = {0x81, 0x7f, 0x10, 0xff};
+  unsigned in_h[] = {0x8181, 0x7f7f, 0x1010, 0xaaaa};
+  unsigned in_s[] = {0x80018181, 0x7fff7f7f, 0xaaaaaaaa, 0xf000f0f0};
+  uint64_t in_d[] = {0x8000000180018181, 0x7fffffff7fff7f7f};
+
+  IntWideImmFn fn = &MacroAssembler::Sub;
+
+  unsigned exp_b_1[] = {0x00, 0xfe, 0x8f, 0x7e};
+  unsigned exp_h_1[] = {0x8171, 0x7f6f, 0x1000, 0xaa9a};
+  unsigned exp_s_1[] = {0x80018102, 0x7fff7f00, 0xaaaaaa2b, 0xf000f071};
+  uint64_t exp_d_1[] = {0x8000000180018082, 0x7fffffff7fff7e80};
+
+  // Encodable with `sub` (shift 0).
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 0x81, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff, exp_d_1);
+
+  unsigned exp_h_2[] = {0x7181, 0x6f7f, 0x0010, 0x9aaa};
+  unsigned exp_s_2[] = {0x80010281, 0x7fff007f, 0xaaaa2baa, 0xf00071f0};
+  uint64_t exp_d_2[] = {0x8000000180008281, 0x7fffffff7ffe807f};
+
+  // Encodable with `sub` (shift 8).
+  // B-sized lanes cannot take a shift of 8.
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16 << 8, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127 << 8, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff << 8, exp_d_2);
+
+  unsigned exp_s_3[] = {0x7f828181, 0x7f807f7f, 0xaa2baaaa, 0xef81f0f0};
+
+  // The macro is able to synthesise unencodable immediates.
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127 << 16, exp_s_3);
+
+  unsigned exp_b_4[] = {0xa1, 0x9f, 0x30, 0x1f};
+  unsigned exp_h_4[] = {0xa181, 0x9f7f, 0x3010, 0xcaaa};
+  unsigned exp_s_4[] = {0x00018181, 0xffff7f7f, 0x2aaaaaaa, 0x7000f0f0};
+  uint64_t exp_d_4[] = {0x8000000180018182, 0x7fffffff7fff7f80};
+
+  // Negative immediates use `add`.
+  IntWideImmHelper(config, fn, kBRegSize, in_b, -0x20, exp_b_4);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, -0x2000, exp_h_4);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, INT32_MIN, exp_s_4);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, -1, exp_d_4);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_sqsub) {
+  unsigned in_b[] = {0x81, 0x7f, 0x10, 0xff};
+  unsigned in_h[] = {0x8181, 0x7f7f, 0x1010, 0xaaaa};
+  unsigned in_s[] = {0x80018181, 0x7fff7f7f, 0xaaaaaaaa, 0xf000f0f0};
+  uint64_t in_d[] = {0x8000000180018181, 0x7fffffff7fff7f7f};
+
+  IntWideImmFn fn = &MacroAssembler::Sqsub;
+
+  unsigned exp_b_1[] = {0x80, 0xfe, 0x8f, 0x80};
+  unsigned exp_h_1[] = {0x8171, 0x7f6f, 0x1000, 0xaa9a};
+  unsigned exp_s_1[] = {0x80018102, 0x7fff7f00, 0xaaaaaa2b, 0xf000f071};
+  uint64_t exp_d_1[] = {0x8000000180018082, 0x7fffffff7fff7e80};
+
+  // Encodable with `sqsub` (shift 0).
+  // Note that encodable immediates are unsigned, even for signed saturation.
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 129, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 255, exp_d_1);
+
+  unsigned exp_h_2[] = {0x8000, 0x6f7f, 0x0010, 0x9aaa};
+  unsigned exp_s_2[] = {0x80010281, 0x7fff007f, 0xaaaa2baa, 0xf00071f0};
+  uint64_t exp_d_2[] = {0x8000000180008281, 0x7fffffff7ffe807f};
+
+  // Encodable with `sqsub` (shift 8).
+  // B-sized lanes cannot take a shift of 8.
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16 << 8, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127 << 8, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff << 8, exp_d_2);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_uqsub) {
+  unsigned in_b[] = {0x81, 0x7f, 0x10, 0xff};
+  unsigned in_h[] = {0x8181, 0x7f7f, 0x1010, 0xaaaa};
+  unsigned in_s[] = {0x80018181, 0x7fff7f7f, 0xaaaaaaaa, 0xf000f0f0};
+  uint64_t in_d[] = {0x8000000180018181, 0x7fffffff7fff7f7f};
+
+  IntWideImmFn fn = &MacroAssembler::Uqsub;
+
+  unsigned exp_b_1[] = {0x00, 0x00, 0x00, 0x7e};
+  unsigned exp_h_1[] = {0x8171, 0x7f6f, 0x1000, 0xaa9a};
+  unsigned exp_s_1[] = {0x80018102, 0x7fff7f00, 0xaaaaaa2b, 0xf000f071};
+  uint64_t exp_d_1[] = {0x8000000180018082, 0x7fffffff7fff7e80};
+
+  // Encodable with `uqsub` (shift 0).
+  IntWideImmHelper(config, fn, kBRegSize, in_b, 0x81, exp_b_1);
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16, exp_h_1);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127, exp_s_1);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff, exp_d_1);
+
+  unsigned exp_h_2[] = {0x7181, 0x6f7f, 0x0010, 0x9aaa};
+  unsigned exp_s_2[] = {0x80010281, 0x7fff007f, 0xaaaa2baa, 0xf00071f0};
+  uint64_t exp_d_2[] = {0x8000000180008281, 0x7fffffff7ffe807f};
+
+  // Encodable with `uqsub` (shift 8).
+  // B-sized lanes cannot take a shift of 8.
+  IntWideImmHelper(config, fn, kHRegSize, in_h, 16 << 8, exp_h_2);
+  IntWideImmHelper(config, fn, kSRegSize, in_s, 127 << 8, exp_s_2);
+  IntWideImmHelper(config, fn, kDRegSize, in_d, 0xff << 8, exp_d_2);
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_subr) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Encodable with `subr` (shift 0).
+  __ Index(z0.VnD(), 1, 1);
+  __ Sub(z0.VnD(), 100, z0.VnD());
+  __ Index(z1.VnS(), 0x7f, 1);
+  __ Sub(z1.VnS(), 0xf7, z1.VnS());
+  __ Index(z2.VnH(), 0xaaaa, 0x2222);
+  __ Sub(z2.VnH(), 0x80, z2.VnH());
+  __ Index(z3.VnB(), 133, 1);
+  __ Sub(z3.VnB(), 255, z3.VnB());
+
+  // Encodable with `subr` (shift 8).
+  __ Index(z4.VnD(), 256, -1);
+  __ Sub(z4.VnD(), 42 * 256, z4.VnD());
+  __ Index(z5.VnS(), 0x7878, 1);
+  __ Sub(z5.VnS(), 0x8000, z5.VnS());
+  __ Index(z6.VnH(), 0x30f0, -1);
+  __ Sub(z6.VnH(), 0x7f00, z6.VnH());
+  // B-sized lanes cannot take a shift of 8.
+
+  // Select with movprfx.
+  __ Index(z31.VnD(), 256, 4001);
+  __ Sub(z7.VnD(), 42 * 256, z31.VnD());
+
+  // Out of immediate encodable range of `sub`.
+  __ Index(z30.VnS(), 0x11223344, 1);
+  __ Sub(z8.VnS(), 0x88776655, z30.VnS());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int expected_z0[] = {87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+
+    int expected_z1[] = {0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnS());
+
+    int expected_z2[] = {0xab2c, 0xcd4e, 0xef70, 0x1192, 0x33b4, 0x55d6};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnH());
+
+    int expected_z3[] = {0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnB());
+
+    int expected_z4[] = {10502, 10501, 10500, 10499, 10498, 10497, 10496};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+
+    int expected_z5[] = {0x0783, 0x0784, 0x0785, 0x0786, 0x0787, 0x0788};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnS());
+
+    int expected_z6[] = {0x4e15, 0x4e14, 0x4e13, 0x4e12, 0x4e11, 0x4e10};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnH());
+
+    int expected_z7[] = {-13510, -9509, -5508, -1507, 2494, 6495, 10496};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+
+    int expected_z8[] = {0x7755330e, 0x7755330f, 0x77553310, 0x77553311};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnS());
+  }
+}
+
+TEST_SVE(sve_int_wide_imm_unpredicated_fdup) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Immediates which can be encoded in the instructions.
+  __ Fdup(z0.VnH(), RawbitsToFloat16(0xc500));
+  __ Fdup(z1.VnS(), Float16(2.0));
+  __ Fdup(z2.VnD(), Float16(3.875));
+  __ Fdup(z3.VnH(), 8.0f);
+  __ Fdup(z4.VnS(), -4.75f);
+  __ Fdup(z5.VnD(), 0.5f);
+  __ Fdup(z6.VnH(), 1.0);
+  __ Fdup(z7.VnS(), 2.125);
+  __ Fdup(z8.VnD(), -13.0);
+
+  // Immediates which cannot be encoded in the instructions.
+  __ Fdup(z10.VnH(), Float16(0.0));
+  __ Fdup(z11.VnH(), kFP16PositiveInfinity);
+  __ Fdup(z12.VnS(), 255.0f);
+  __ Fdup(z13.VnS(), kFP32NegativeInfinity);
+  __ Fdup(z14.VnD(), 12.3456);
+  __ Fdup(z15.VnD(), kFP64PositiveInfinity);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(0xc500, z0.VnH());
+    ASSERT_EQUAL_SVE(0x40000000, z1.VnS());
+    ASSERT_EQUAL_SVE(0x400f000000000000, z2.VnD());
+    ASSERT_EQUAL_SVE(0x4800, z3.VnH());
+    ASSERT_EQUAL_SVE(FloatToRawbits(-4.75f), z4.VnS());
+    ASSERT_EQUAL_SVE(DoubleToRawbits(0.5), z5.VnD());
+    ASSERT_EQUAL_SVE(0x3c00, z6.VnH());
+    ASSERT_EQUAL_SVE(FloatToRawbits(2.125f), z7.VnS());
+    ASSERT_EQUAL_SVE(DoubleToRawbits(-13.0), z8.VnD());
+
+    ASSERT_EQUAL_SVE(0x0000, z10.VnH());
+    ASSERT_EQUAL_SVE(Float16ToRawbits(kFP16PositiveInfinity), z11.VnH());
+    ASSERT_EQUAL_SVE(FloatToRawbits(255.0), z12.VnS());
+    ASSERT_EQUAL_SVE(FloatToRawbits(kFP32NegativeInfinity), z13.VnS());
+    ASSERT_EQUAL_SVE(DoubleToRawbits(12.3456), z14.VnD());
+    ASSERT_EQUAL_SVE(DoubleToRawbits(kFP64PositiveInfinity), z15.VnD());
+  }
+}
+
+TEST_SVE(sve_andv_eorv_orv) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0x8899aabbccddeeff, 0x7777555533331111, 0x123456789abcdef0};
+  InsrHelper(&masm, z31.VnD(), in);
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z0, z31);
+  __ Andv(b0, p0, z0.VnB());  // destructive
+  __ Andv(h1, p0, z31.VnH());
+  __ Mov(z2, z31);
+  __ Andv(s2, p0, z2.VnS());  // destructive
+  __ Andv(d3, p0, z31.VnD());
+
+  __ Eorv(b4, p0, z31.VnB());
+  __ Mov(z5, z31);
+  __ Eorv(h5, p0, z5.VnH());  // destructive
+  __ Eorv(s6, p0, z31.VnS());
+  __ Mov(z7, z31);
+  __ Eorv(d7, p0, z7.VnD());  // destructive
+
+  __ Mov(z8, z31);
+  __ Orv(b8, p0, z8.VnB());  // destructive
+  __ Orv(h9, p0, z31.VnH());
+  __ Mov(z10, z31);
+  __ Orv(s10, p0, z10.VnS());  // destructive
+  __ Orv(d11, p0, z31.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    if (static_cast<int>(ArrayLength(pg_in)) >= config->sve_vl_in_bytes()) {
+      ASSERT_EQUAL_64(0x10, d0);
+      ASSERT_EQUAL_64(0x1010, d1);
+      ASSERT_EQUAL_64(0x33331111, d2);
+      ASSERT_EQUAL_64(0x7777555533331111, d3);
+      ASSERT_EQUAL_64(0xbf, d4);
+      ASSERT_EQUAL_64(0xedcb, d5);
+      ASSERT_EQUAL_64(0x44444444, d6);
+      ASSERT_EQUAL_64(0x7777555533331111, d7);
+      ASSERT_EQUAL_64(0xff, d8);
+      ASSERT_EQUAL_64(0xffff, d9);
+      ASSERT_EQUAL_64(0x77775555, d10);
+      ASSERT_EQUAL_64(0x7777555533331111, d11);
+    } else {
+      ASSERT_EQUAL_64(0, d0);
+      ASSERT_EQUAL_64(0x0010, d1);
+      ASSERT_EQUAL_64(0x00110011, d2);
+      ASSERT_EQUAL_64(0x0011001100110011, d3);
+      ASSERT_EQUAL_64(0x62, d4);
+      ASSERT_EQUAL_64(0x0334, d5);
+      ASSERT_EQUAL_64(0x8899aabb, d6);
+      ASSERT_EQUAL_64(0xffeeffeeffeeffee, d7);
+      ASSERT_EQUAL_64(0xff, d8);
+      ASSERT_EQUAL_64(0xffff, d9);
+      ASSERT_EQUAL_64(0xffffffff, d10);
+      ASSERT_EQUAL_64(0xffffffffffffffff, d11);
+    }
+
+    // Check the upper lanes above the top of the V register are all clear.
+    for (int i = 1; i < core.GetSVELaneCount(kDRegSize); i++) {
+      ASSERT_EQUAL_SVE_LANE(0, z0.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z1.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z2.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z3.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z4.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z5.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z6.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z7.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z8.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z9.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z10.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z11.VnD(), i);
+    }
+  }
+}
+
+
+TEST_SVE(sve_saddv_uaddv) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0x8899aabbccddeeff, 0x8182838485868788, 0x0807060504030201};
+  InsrHelper(&masm, z31.VnD(), in);
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z0, z31);
+  __ Saddv(b0, p0, z0.VnB());  // destructive
+  __ Saddv(h1, p0, z31.VnH());
+  __ Mov(z2, z31);
+  __ Saddv(s2, p0, z2.VnS());  // destructive
+
+  __ Uaddv(b4, p0, z31.VnB());
+  __ Mov(z5, z31);
+  __ Uaddv(h5, p0, z5.VnH());  // destructive
+  __ Uaddv(s6, p0, z31.VnS());
+  __ Mov(z7, z31);
+  __ Uaddv(d7, p0, z7.VnD());  // destructive
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    if (static_cast<int>(ArrayLength(pg_in)) >= config->sve_vl_in_bytes()) {
+      // Saddv
+      ASSERT_EQUAL_64(0xfffffffffffffda9, d0);
+      ASSERT_EQUAL_64(0xfffffffffffe9495, d1);
+      ASSERT_EQUAL_64(0xffffffff07090b0c, d2);
+      // Uaddv
+      ASSERT_EQUAL_64(0x00000000000002a9, d4);
+      ASSERT_EQUAL_64(0x0000000000019495, d5);
+      ASSERT_EQUAL_64(0x0000000107090b0c, d6);
+      ASSERT_EQUAL_64(0x8182838485868788, d7);
+    } else {
+      // Saddv
+      ASSERT_EQUAL_64(0xfffffffffffffd62, d0);
+      ASSERT_EQUAL_64(0xfffffffffffe8394, d1);
+      ASSERT_EQUAL_64(0xfffffffed3e6fa0b, d2);
+      // Uaddv
+      ASSERT_EQUAL_64(0x0000000000000562, d4);
+      ASSERT_EQUAL_64(0x0000000000028394, d5);
+      ASSERT_EQUAL_64(0x00000001d3e6fa0b, d6);
+      ASSERT_EQUAL_64(0x0a1c2e4052647687, d7);
+    }
+
+    // Check the upper lanes above the top of the V register are all clear.
+    for (int i = 1; i < core.GetSVELaneCount(kDRegSize); i++) {
+      ASSERT_EQUAL_SVE_LANE(0, z0.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z1.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z2.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z4.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z5.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z6.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z7.VnD(), i);
+    }
+  }
+}
+
+
+TEST_SVE(sve_sminv_uminv) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0xfffa5555aaaaaaaa, 0x0011223344aafe80, 0x00112233aabbfc00};
+  InsrHelper(&masm, z31.VnD(), in);
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      0,                      1
+  // For S lanes:         1,          1,          0,          0,          1
+  // For H lanes:   1,    1,    0,    1,    1,    0,    0,    0,    1,    1
+  int pg_in[] = {1, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1};
+  Initialise(&masm, p0.VnB(), pg_in);
+
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z0, z31);
+  __ Sminv(b0, p0, z0.VnB());  // destructive
+  __ Sminv(h1, p0, z31.VnH());
+  __ Mov(z2, z31);
+  __ Sminv(s2, p0, z2.VnS());  // destructive
+  __ Sminv(d3, p0, z31.VnD());
+
+  __ Uminv(b4, p0, z31.VnB());
+  __ Mov(z5, z31);
+  __ Uminv(h5, p0, z5.VnH());  // destructive
+  __ Uminv(s6, p0, z31.VnS());
+  __ Mov(z7, z31);
+  __ Uminv(d7, p0, z7.VnD());  // destructive
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    if (static_cast<int>(ArrayLength(pg_in)) >= config->sve_vl_in_bytes()) {
+      // Sminv
+      ASSERT_EQUAL_64(0xaa, d0);
+      ASSERT_EQUAL_64(0xaabb, d1);
+      ASSERT_EQUAL_64(0xaabbfc00, d2);
+      ASSERT_EQUAL_64(0x00112233aabbfc00, d3);  // The smaller lane is inactive.
+      // Uminv
+      ASSERT_EQUAL_64(0, d4);
+      ASSERT_EQUAL_64(0x2233, d5);
+      ASSERT_EQUAL_64(0x112233, d6);
+      ASSERT_EQUAL_64(0x00112233aabbfc00, d7);  // The smaller lane is inactive.
+    } else {
+      // Sminv
+      ASSERT_EQUAL_64(0xaa, d0);
+      ASSERT_EQUAL_64(0xaaaa, d1);
+      ASSERT_EQUAL_64(0xaaaaaaaa, d2);
+      ASSERT_EQUAL_64(0xfffa5555aaaaaaaa, d3);
+      // Uminv
+      ASSERT_EQUAL_64(0, d4);
+      ASSERT_EQUAL_64(0x2233, d5);
+      ASSERT_EQUAL_64(0x112233, d6);
+      ASSERT_EQUAL_64(0x00112233aabbfc00, d7);
+    }
+
+    // Check the upper lanes above the top of the V register are all clear.
+    for (int i = 1; i < core.GetSVELaneCount(kDRegSize); i++) {
+      ASSERT_EQUAL_SVE_LANE(0, z0.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z1.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z2.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z3.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z4.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z5.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z6.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z7.VnD(), i);
+    }
+  }
+}
+
+TEST_SVE(sve_smaxv_umaxv) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0xfffa5555aaaaaaaa, 0x0011223344aafe80, 0x00112233aabbfc00};
+  InsrHelper(&masm, z31.VnD(), in);
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      0,                      1
+  // For S lanes:         1,          1,          0,          0,          1
+  // For H lanes:   1,    1,    0,    1,    1,    0,    0,    0,    1,    1
+  int pg_in[] = {1, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 1, 1};
+  Initialise(&masm, p0.VnB(), pg_in);
+
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z0, z31);
+  __ Smaxv(b0, p0, z0.VnB());  // destructive
+  __ Smaxv(h1, p0, z31.VnH());
+  __ Mov(z2, z31);
+  __ Smaxv(s2, p0, z2.VnS());  // destructive
+  __ Smaxv(d3, p0, z31.VnD());
+
+  __ Umaxv(b4, p0, z31.VnB());
+  __ Mov(z5, z31);
+  __ Umaxv(h5, p0, z5.VnH());  // destructive
+  __ Umaxv(s6, p0, z31.VnS());
+  __ Mov(z7, z31);
+  __ Umaxv(d7, p0, z7.VnD());  // destructive
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    if (static_cast<int>(ArrayLength(pg_in)) >= config->sve_vl_in_bytes()) {
+      // Smaxv
+      ASSERT_EQUAL_64(0x33, d0);
+      ASSERT_EQUAL_64(0x44aa, d1);
+      ASSERT_EQUAL_64(0x112233, d2);
+      ASSERT_EQUAL_64(0x112233aabbfc00, d3);
+      // Umaxv
+      ASSERT_EQUAL_64(0xfe, d4);
+      ASSERT_EQUAL_64(0xfc00, d5);
+      ASSERT_EQUAL_64(0xaabbfc00, d6);
+      ASSERT_EQUAL_64(0x112233aabbfc00, d7);
+    } else {
+      // Smaxv
+      ASSERT_EQUAL_64(0x33, d0);
+      ASSERT_EQUAL_64(0x44aa, d1);
+      ASSERT_EQUAL_64(0x112233, d2);
+      ASSERT_EQUAL_64(0x00112233aabbfc00, d3);
+      // Umaxv
+      ASSERT_EQUAL_64(0xfe, d4);
+      ASSERT_EQUAL_64(0xfc00, d5);
+      ASSERT_EQUAL_64(0xaabbfc00, d6);
+      ASSERT_EQUAL_64(0xfffa5555aaaaaaaa, d7);
+    }
+
+    // Check the upper lanes above the top of the V register are all clear.
+    for (int i = 1; i < core.GetSVELaneCount(kDRegSize); i++) {
+      ASSERT_EQUAL_SVE_LANE(0, z0.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z1.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z2.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z3.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z4.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z5.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z6.VnD(), i);
+      ASSERT_EQUAL_SVE_LANE(0, z7.VnD(), i);
+    }
+  }
+}
+
+template <typename T, size_t M, size_t N>
+static void SdotUdotHelper(Test* config,
+                           unsigned lane_size_in_bits,
+                           const T (&zd_inputs)[M],
+                           const T (&za_inputs)[M],
+                           const T (&zn_inputs)[N],
+                           const T (&zm_inputs)[N],
+                           const T (&zd_expected)[M],
+                           const T (&zdnm_expected)[M],
+                           bool is_signed,
+                           int index = -1) {
+  VIXL_STATIC_ASSERT(N == (M * 4));
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  auto dot_fn = [&](const ZRegister& zd,
+                    const ZRegister& za,
+                    const ZRegister& zn,
+                    const ZRegister& zm,
+                    bool is_signed,
+                    int index) {
+    if (is_signed) {
+      if (index < 0) {
+        __ Sdot(zd, za, zn, zm);
+      } else {
+        __ Sdot(zd, za, zn, zm, index);
+      }
+    } else {
+      if (index < 0) {
+        __ Udot(zd, za, zn, zm);
+      } else {
+        __ Udot(zd, za, zn, zm, index);
+      }
+    }
+  };
+
+  ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
+  ZRegister za = z1.WithLaneSize(lane_size_in_bits);
+  ZRegister zn = z2.WithLaneSize(lane_size_in_bits / 4);
+  ZRegister zm = z3.WithLaneSize(lane_size_in_bits / 4);
+
+  InsrHelper(&masm, zd, zd_inputs);
+  InsrHelper(&masm, za, za_inputs);
+  InsrHelper(&masm, zn, zn_inputs);
+  InsrHelper(&masm, zm, zm_inputs);
+
+  // The Dot macro handles arbitrarily-aliased registers in the argument list.
+  ZRegister dm_result = z4.WithLaneSize(lane_size_in_bits);
+  ZRegister dnm_result = z5.WithLaneSize(lane_size_in_bits);
+  ZRegister da_result = z6.WithLaneSize(lane_size_in_bits);
+  ZRegister dn_result = z7.WithLaneSize(lane_size_in_bits);
+  ZRegister d_result = z8.WithLaneSize(lane_size_in_bits);
+
+  __ Mov(da_result, za);
+  // zda = zda + (zn . zm)
+  dot_fn(da_result, da_result, zn, zm, is_signed, index);
+
+  __ Mov(dn_result, zn.WithSameLaneSizeAs(dn_result));
+  // zdn = za + (zdn . zm)
+  dot_fn(dn_result, za, dn_result.WithSameLaneSizeAs(zn), zm, is_signed, index);
+
+  __ Mov(dm_result, zm.WithSameLaneSizeAs(dm_result));
+  // zdm = za + (zn . zdm)
+  dot_fn(dm_result, za, zn, dm_result.WithSameLaneSizeAs(zm), is_signed, index);
+
+  __ Mov(d_result, zd);
+  // zd = za + (zn . zm)
+  dot_fn(d_result, za, zn, zm, is_signed, index);
+
+  __ Mov(dnm_result, zn.WithSameLaneSizeAs(dnm_result));
+  // zdnm = za + (zdmn . zdnm)
+  dot_fn(dnm_result,
+         za,
+         dnm_result.WithSameLaneSizeAs(zn),
+         dnm_result.WithSameLaneSizeAs(zm),
+         is_signed,
+         index);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(za_inputs, z1.WithLaneSize(lane_size_in_bits));
+    ASSERT_EQUAL_SVE(zn_inputs, z2.WithLaneSize(lane_size_in_bits / 4));
+    ASSERT_EQUAL_SVE(zm_inputs, z3.WithLaneSize(lane_size_in_bits / 4));
+
+    ASSERT_EQUAL_SVE(zd_expected, da_result);
+    ASSERT_EQUAL_SVE(zd_expected, dn_result);
+    ASSERT_EQUAL_SVE(zd_expected, dm_result);
+    ASSERT_EQUAL_SVE(zd_expected, d_result);
+
+    ASSERT_EQUAL_SVE(zdnm_expected, dnm_result);
+  }
+}
+
+TEST_SVE(sve_sdot) {
+  int64_t zd_inputs[] = {0x33, 0xee, 0xff};
+  int64_t za_inputs[] = {INT32_MAX, -3, 2};
+  int64_t zn_inputs[] = {-128, -128, -128, -128, 9, -1, 1, 30, -5, -20, 9, 8};
+  int64_t zm_inputs[] = {-128, -128, -128, -128, -19, 15, 6, 0, 9, -5, 4, 5};
+
+  // zd_expected[] = za_inputs[] + (zn_inputs[] . zm_inputs[])
+  int64_t zd_expected_s[] = {-2147418113, -183, 133};  // 0x8000ffff
+  int64_t zd_expected_d[] = {2147549183, -183, 133};   // 0x8000ffff
+
+  // zdnm_expected[] = za_inputs[] + (zn_inputs[] . zn_inputs[])
+  int64_t zdnm_expected_s[] = {-2147418113, 980, 572};
+  int64_t zdnm_expected_d[] = {2147549183, 980, 572};
+
+  SdotUdotHelper(config,
+                 kSRegSize,
+                 zd_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 zd_expected_s,
+                 zdnm_expected_s,
+                 true);
+
+  SdotUdotHelper(config,
+                 kDRegSize,
+                 zd_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 zd_expected_d,
+                 zdnm_expected_d,
+                 true);
+}
+
+TEST_SVE(sve_udot) {
+  int64_t zd_inputs[] = {0x33, 0xee, 0xff};
+  int64_t za_inputs[] = {INT32_MAX, -3, 2};
+  int64_t zn_inputs[] = {-128, -128, -128, -128, 9, -1, 1, 30, -5, -20, 9, 8};
+  int64_t zm_inputs[] = {-128, -128, -128, -128, -19, 15, 6, 0, 9, -5, 4, 5};
+
+  // zd_expected[] = za_inputs[] + (zn_inputs[] . zm_inputs[])
+  int64_t zd_expected_s[] = {0x8000ffff, 0x00001749, 0x0000f085};
+  int64_t zd_expected_d[] = {0x000000047c00ffff,
+                             0x000000000017ff49,
+                             0x00000000fff00085};
+
+  // zdnm_expected[] = za_inputs[] + (zn_inputs[] . zn_inputs[])
+  int64_t zdnm_expected_s[] = {0x8000ffff, 0x000101d4, 0x0001d03c};
+  int64_t zdnm_expected_d[] = {0x000000047c00ffff,
+                               0x00000000fffe03d4,
+                               0x00000001ffce023c};
+
+  SdotUdotHelper(config,
+                 kSRegSize,
+                 zd_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 zd_expected_s,
+                 zdnm_expected_s,
+                 false);
+
+  SdotUdotHelper(config,
+                 kDRegSize,
+                 zd_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 zd_expected_d,
+                 zdnm_expected_d,
+                 false);
+}
+
+TEST_SVE(sve_sdot_indexed_s) {
+  int64_t zd_inputs[] = {0xff, 0xff, 0xff, 0xff};
+  int64_t za_inputs[] = {0, 1, 2, 3};
+  int64_t zn_inputs[] =
+      {-1, -1, -1, -1, -2, -2, -2, -2, -3, -3, -3, -3, -4, -4, -4, -4};
+  int64_t zm_inputs[] =
+      {127, 127, 127, 127, -128, -128, -128, -128, -1, -1, -1, -1, 0, 0, 0, 0};
+
+  constexpr int s = kQRegSize / kSRegSize;
+
+  // zd_expected[] = za_inputs[] + (zn_inputs[] . zm_inputs[])
+  int64_t zd_expected_s[][s] = {{0, 1, 2, 3},  // Generated from zm[0]
+                                {4, 9, 14, 19},
+                                {512, 1025, 1538, 2051},
+                                {-508, -1015, -1522, -2029}};
+
+  // zdnm_expected[] = za_inputs[] + (zn_inputs[] . zn_inputs[])
+  int64_t zdnm_expected_s[][s] = {{16, 33, 50, 67},
+                                  {12, 25, 38, 51},
+                                  {8, 17, 26, 35},
+                                  {4, 9, 14, 19}};
+
+  for (unsigned i = 0; i < s; i++) {
+    SdotUdotHelper(config,
+                   kSRegSize,
+                   zd_inputs,
+                   za_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_s[i],
+                   zdnm_expected_s[i],
+                   true,
+                   i);
+  }
+}
+
+TEST_SVE(sve_sdot_indexed_d) {
+  int64_t zd_inputs[] = {0xff, 0xff};
+  int64_t za_inputs[] = {0, 1};
+  int64_t zn_inputs[] = {-1, -1, -1, -1, -1, -1, -1, -1};
+  int64_t zm_inputs[] = {-128, -128, -128, -128, 127, 127, 127, 127};
+
+  constexpr int d = kQRegSize / kDRegSize;
+
+  // zd_expected[] = za_inputs[] + (zn_inputs[] . zm_inputs[])
+  int64_t zd_expected_d[][d] = {{-508, -507},  // Generated from zm[0]
+                                {512, 513}};
+
+  // zdnm_expected[] = za_inputs[] + (zn_inputs[] . zn_inputs[])
+  int64_t zdnm_expected_d[][d] = {{4, 5}, {4, 5}};
+
+  for (unsigned i = 0; i < d; i++) {
+    SdotUdotHelper(config,
+                   kDRegSize,
+                   zd_inputs,
+                   za_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_d[i],
+                   zdnm_expected_d[i],
+                   true,
+                   i);
+  }
+}
+
+TEST_SVE(sve_udot_indexed_s) {
+  int64_t zd_inputs[] = {0xff, 0xff, 0xff, 0xff};
+  int64_t za_inputs[] = {0, 1, 2, 3};
+  int64_t zn_inputs[] = {1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4};
+  int64_t zm_inputs[] =
+      {127, 127, 127, 127, 255, 255, 255, 255, 1, 1, 1, 1, 0, 0, 0, 0};
+
+  constexpr int s = kQRegSize / kSRegSize;
+
+  // zd_expected[] = za_inputs[] + (zn_inputs[] . zm_inputs[])
+  int64_t zd_expected_s[][s] = {{0, 1, 2, 3},
+                                {4, 9, 14, 19},
+                                {1020, 2041, 3062, 4083},
+                                {508, 1017, 1526, 2035}};
+
+  // zdnm_expected[] = za_inputs[] + (zn_inputs[] . zn_inputs[])
+  int64_t zdnm_expected_s[][s] = {{16, 33, 50, 67},
+                                  {12, 25, 38, 51},
+                                  {8, 17, 26, 35},
+                                  {4, 9, 14, 19}};
+
+  for (unsigned i = 0; i < s; i++) {
+    SdotUdotHelper(config,
+                   kSRegSize,
+                   zd_inputs,
+                   za_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_s[i],
+                   zdnm_expected_s[i],
+                   false,
+                   i);
+  }
+}
+
+TEST_SVE(sve_udot_indexed_d) {
+  int64_t zd_inputs[] = {0xff, 0xff};
+  int64_t za_inputs[] = {0, 1};
+  int64_t zn_inputs[] = {1, 1, 1, 1, 1, 1, 1, 1};
+  int64_t zm_inputs[] = {255, 255, 255, 255, 127, 127, 127, 127};
+
+  constexpr int d = kQRegSize / kDRegSize;
+
+  // zd_expected[] = za_inputs[] + (zn_inputs[] . zm_inputs[])
+  int64_t zd_expected_d[][d] = {{508, 509}, {1020, 1021}};
+
+  // zdnm_expected[] = za_inputs[] + (zn_inputs[] . zn_inputs[])
+  int64_t zdnm_expected_d[][d] = {{4, 5}, {4, 5}};
+
+  for (unsigned i = 0; i < d; i++) {
+    SdotUdotHelper(config,
+                   kDRegSize,
+                   zd_inputs,
+                   za_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_d[i],
+                   zdnm_expected_d[i],
+                   false,
+                   i);
+  }
+}
+
+static void IntSegmentPatternHelper(MacroAssembler* masm,
+                                    const ZRegister& dst,
+                                    const ZRegister& src) {
+  VIXL_ASSERT(AreSameLaneSize(dst, src));
+  UseScratchRegisterScope temps(masm);
+  ZRegister ztmp = temps.AcquireZ().WithSameLaneSizeAs(dst);
+  masm->Index(ztmp, 0, 1);
+  masm->Asr(ztmp, ztmp, kQRegSizeInBytesLog2 - dst.GetLaneSizeInBytesLog2());
+  masm->Add(dst, src, ztmp);
+}
+
+TEST_SVE(sve_sdot_udot_indexed_s) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  const int multiplier = 2;
+  __ Dup(z9.VnS(), multiplier);
+
+  __ Ptrue(p0.VnB());
+  __ Index(z29.VnS(), 4, 1);
+
+  // z29 = [... 3, 2, 1, 0, 3, 2, 1, 0, 3, 2, 1, 0]
+  __ And(z29.VnS(), z29.VnS(), 3);
+
+  // p7 = [... 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1]
+  __ Cmple(p7.VnS(), p0.Zeroing(), z29.VnS(), 0);
+
+  // p6 = [... 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1]
+  __ Cmple(p6.VnS(), p0.Zeroing(), z29.VnS(), 1);
+
+  // p5 = [... 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1]
+  __ Cmple(p5.VnS(), p0.Zeroing(), z29.VnS(), 2);
+
+  __ Index(z28.VnB(), 1, 1);
+  __ Dup(z27.VnS(), z28.VnS(), 0);
+
+  // z27 = [... 3, 2, 4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1]
+  IntSegmentPatternHelper(&masm, z27.VnB(), z27.VnB());
+
+  // z27 = [... 6, 4, 4, 3, 2, 1, 4, 3, 2, 1, 4, 3, 2, 1, 8, 6, 4, 2]
+  __ Mul(z27.VnS(), p7.Merging(), z27.VnS(), z9.VnS());
+
+  // z27 = [... 12, 8, 4, 3, 2, 1, 4, 3, 2, 1, 8, 6, 4, 2, 16, 12, 8, 4]
+  __ Mul(z27.VnS(), p6.Merging(), z27.VnS(), z9.VnS());
+
+  //     2nd segment |                                        1st segment |
+  //                 v                                                    v
+  // z27 = [... 24, 16, 4, 3, 2, 1, 8, 6, 4, 2, 16, 12, 8, 4, 32, 24, 16, 8]
+  __ Mul(z27.VnS(), p5.Merging(), z27.VnS(), z9.VnS());
+
+  __ Dup(z0.VnS(), 0);
+  __ Dup(z1.VnS(), 0);
+  __ Dup(z2.VnS(), 0);
+  __ Dup(z3.VnS(), 0);
+  __ Dup(z4.VnS(), 0);
+  __ Dup(z5.VnS(), 0);
+
+  // Skip the lanes starting from the 129th lane since the value of these lanes
+  // are overflow after the number sequence creation by `index`.
+  __ Cmpls(p3.VnB(), p0.Zeroing(), z28.VnB(), 128);
+  __ Mov(z0.VnB(), p3.Merging(), z27.VnB());
+  __ Mov(z1.VnB(), p3.Merging(), z28.VnB());
+
+  __ Dup(z2.VnS(), 0);
+  __ Dup(z3.VnS(), 0);
+  __ Dup(z4.VnS(), 0);
+  __ Dup(z5.VnS(), 0);
+
+  __ Udot(z2.VnS(), z2.VnS(), z1.VnB(), z0.VnB(), 0);
+
+  __ Udot(z3.VnS(), z3.VnS(), z1.VnB(), z0.VnB(), 1);
+  __ Mul(z3.VnS(), z3.VnS(), 2);
+
+  __ Udot(z4.VnS(), z4.VnS(), z1.VnB(), z0.VnB(), 2);
+  __ Mul(z4.VnS(), z4.VnS(), 4);
+
+  __ Udot(z5.VnS(), z5.VnS(), z1.VnB(), z0.VnB(), 3);
+  __ Mul(z5.VnS(), z5.VnS(), 8);
+
+  __ Dup(z7.VnS(), 0);
+  __ Dup(z8.VnS(), 0);
+  __ Dup(z9.VnS(), 0);
+  __ Dup(z10.VnS(), 0);
+
+  // Negate the all positive vector for testing signed dot.
+  __ Neg(z6.VnB(), p0.Merging(), z0.VnB());
+  __ Sdot(z7.VnS(), z7.VnS(), z1.VnB(), z6.VnB(), 0);
+
+  __ Sdot(z8.VnS(), z8.VnS(), z1.VnB(), z6.VnB(), 1);
+  __ Mul(z8.VnS(), z8.VnS(), 2);
+
+  __ Sdot(z9.VnS(), z9.VnS(), z1.VnB(), z6.VnB(), 2);
+  __ Mul(z9.VnS(), z9.VnS(), 4);
+
+  __ Sdot(z10.VnS(), z10.VnS(), z1.VnB(), z6.VnB(), 3);
+  __ Mul(z10.VnS(), z10.VnS(), 8);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Only compare the first 128-bit segment of destination register, use
+    // another result from generated instructions to check the remaining part.
+    // s_lane[0] = (1 * 8) + (2 * 16) + (3 * 24) + (4 * 32) = 240
+    // ...
+    // s_lane[3] = (13 * 8) + (14 * 16) + (15 * 24) + (16 * 32) = 1200
+    int udot_expected[] = {1200, 880, 560, 240};
+    ASSERT_EQUAL_SVE(udot_expected, z2.VnS());
+    ASSERT_EQUAL_SVE(z2.VnS(), z3.VnS());
+    ASSERT_EQUAL_SVE(z2.VnS(), z4.VnS());
+    ASSERT_EQUAL_SVE(z2.VnS(), z5.VnS());
+
+    int sdot_expected[] = {-1200, -880, -560, -240};
+    ASSERT_EQUAL_SVE(sdot_expected, z7.VnS());
+    ASSERT_EQUAL_SVE(z7.VnS(), z8.VnS());
+    ASSERT_EQUAL_SVE(z7.VnS(), z9.VnS());
+    ASSERT_EQUAL_SVE(z7.VnS(), z10.VnS());
+  }
+}
+
+TEST_SVE(sve_sdot_udot_indexed_d) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  const int multiplier = 2;
+  __ Dup(z9.VnD(), multiplier);
+
+  __ Ptrue(p0.VnD());
+  __ Pfalse(p1.VnD());
+
+  // p2 = [..., 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1]
+  __ Zip1(p2.VnD(), p0.VnD(), p1.VnD());
+
+  __ Index(z1.VnH(), 1, 1);
+  __ Dup(z0.VnD(), z1.VnD(), 0);
+
+  // z0 = [... 5, 4, 3, 2, 5, 4, 3, 2, 4, 3, 2, 1, 4, 3, 2, 1]
+  IntSegmentPatternHelper(&masm, z0.VnH(), z0.VnH());
+
+  //                     2nd segment |           1st segment |
+  //                                 v                       v
+  // z0 = [... 5, 4, 3, 2, 10, 8, 6, 4, 4, 3, 2, 1, 8, 6, 4, 2]
+  __ Mul(z0.VnD(), p2.Merging(), z0.VnD(), z9.VnD());
+
+  __ Dup(z3.VnD(), 0);
+  __ Dup(z4.VnD(), 0);
+
+  __ Udot(z3.VnD(), z3.VnD(), z1.VnH(), z0.VnH(), 0);
+
+  __ Udot(z4.VnD(), z4.VnD(), z1.VnH(), z0.VnH(), 1);
+  __ Mul(z4.VnD(), z4.VnD(), multiplier);
+
+  __ Dup(z12.VnD(), 0);
+  __ Dup(z13.VnD(), 0);
+
+  __ Ptrue(p4.VnH());
+  __ Neg(z10.VnH(), p4.Merging(), z0.VnH());
+
+  __ Sdot(z12.VnD(), z12.VnD(), z1.VnH(), z10.VnH(), 0);
+
+  __ Sdot(z13.VnD(), z13.VnD(), z1.VnH(), z10.VnH(), 1);
+  __ Mul(z13.VnD(), z13.VnD(), multiplier);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Only compare the first 128-bit segment of destination register, use
+    // another result from generated instructions to check the remaining part.
+    // d_lane[0] = (1 * 2) + (2 * 4) + (3 * 6) + (4 * 8) = 60
+    // d_lane[1] = (5 * 2) + (6 * 4) + (7 * 6) + (8 * 8) = 140
+    uint64_t udot_expected[] = {416, 304, 140, 60};
+    ASSERT_EQUAL_SVE(udot_expected, z3.VnD());
+    ASSERT_EQUAL_SVE(z3.VnD(), z4.VnD());
+
+    int64_t sdot_expected[] = {-416, -304, -140, -60};
+    ASSERT_EQUAL_SVE(sdot_expected, z12.VnD());
+    ASSERT_EQUAL_SVE(z12.VnD(), z13.VnD());
+  }
+}
+
+template <typename T, size_t N>
+static void FPToRawbitsWithSize(const T (&inputs)[N],
+                                uint64_t* outputs,
+                                unsigned size_in_bits) {
+  for (size_t i = 0; i < N; i++) {
+    outputs[i] = vixl::FPToRawbitsWithSize(size_in_bits, inputs[i]);
+  }
+}
+
+template <typename Ti, typename Te, size_t N>
+static void FPBinArithHelper(Test* config,
+                             ArithFn macro,
+                             int lane_size_in_bits,
+                             const Ti (&zn_inputs)[N],
+                             const Ti (&zm_inputs)[N],
+                             const Te (&zd_expected)[N]) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+
+  ZRegister zd = z29.WithLaneSize(lane_size_in_bits);
+  ZRegister zn = z30.WithLaneSize(lane_size_in_bits);
+  ZRegister zm = z31.WithLaneSize(lane_size_in_bits);
+
+  uint64_t zn_rawbits[N];
+  uint64_t zm_rawbits[N];
+
+  FPToRawbitsWithSize(zn_inputs, zn_rawbits, lane_size_in_bits);
+  FPToRawbitsWithSize(zm_inputs, zm_rawbits, lane_size_in_bits);
+
+  InsrHelper(&masm, zn, zn_rawbits);
+  InsrHelper(&masm, zm, zm_rawbits);
+
+  (masm.*macro)(zd, zn, zm);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(zd_expected, zd);
+  }
+}
+
+TEST_SVE(sve_fp_arithmetic_unpredicated_fadd) {
+  double zn_inputs[] = {24.0,
+                        5.5,
+                        0.0,
+                        3.875,
+                        2.125,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity};
+
+  double zm_inputs[] = {1024.0, 2048.0, 0.1, -4.75, 12.34, 255.0, -13.0};
+
+  ArithFn fn = &MacroAssembler::Fadd;
+
+  uint16_t expected_h[] = {Float16ToRawbits(Float16(1048.0)),
+                           Float16ToRawbits(Float16(2053.5)),
+                           Float16ToRawbits(Float16(0.1)),
+                           Float16ToRawbits(Float16(-0.875)),
+                           Float16ToRawbits(Float16(14.465)),
+                           Float16ToRawbits(kFP16PositiveInfinity),
+                           Float16ToRawbits(kFP16NegativeInfinity)};
+
+  FPBinArithHelper(config, fn, kHRegSize, zn_inputs, zm_inputs, expected_h);
+
+  uint32_t expected_s[] = {FloatToRawbits(1048.0f),
+                           FloatToRawbits(2053.5f),
+                           FloatToRawbits(0.1f),
+                           FloatToRawbits(-0.875f),
+                           FloatToRawbits(14.465f),
+                           FloatToRawbits(kFP32PositiveInfinity),
+                           FloatToRawbits(kFP32NegativeInfinity)};
+
+  FPBinArithHelper(config, fn, kSRegSize, zn_inputs, zm_inputs, expected_s);
+
+  uint64_t expected_d[] = {DoubleToRawbits(1048.0),
+                           DoubleToRawbits(2053.5),
+                           DoubleToRawbits(0.1),
+                           DoubleToRawbits(-0.875),
+                           DoubleToRawbits(14.465),
+                           DoubleToRawbits(kFP64PositiveInfinity),
+                           DoubleToRawbits(kFP64NegativeInfinity)};
+
+  FPBinArithHelper(config, fn, kDRegSize, zn_inputs, zm_inputs, expected_d);
+}
+
+TEST_SVE(sve_fp_arithmetic_unpredicated_fsub) {
+  double zn_inputs[] = {24.0,
+                        5.5,
+                        0.0,
+                        3.875,
+                        2.125,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity};
+
+  double zm_inputs[] = {1024.0, 2048.0, 0.1, -4.75, 12.34, 255.0, -13.0};
+
+  ArithFn fn = &MacroAssembler::Fsub;
+
+  uint16_t expected_h[] = {Float16ToRawbits(Float16(-1000.0)),
+                           Float16ToRawbits(Float16(-2042.5)),
+                           Float16ToRawbits(Float16(-0.1)),
+                           Float16ToRawbits(Float16(8.625)),
+                           Float16ToRawbits(Float16(-10.215)),
+                           Float16ToRawbits(kFP16PositiveInfinity),
+                           Float16ToRawbits(kFP16NegativeInfinity)};
+
+  FPBinArithHelper(config, fn, kHRegSize, zn_inputs, zm_inputs, expected_h);
+
+  uint32_t expected_s[] = {FloatToRawbits(-1000.0),
+                           FloatToRawbits(-2042.5),
+                           FloatToRawbits(-0.1),
+                           FloatToRawbits(8.625),
+                           FloatToRawbits(-10.215),
+                           FloatToRawbits(kFP32PositiveInfinity),
+                           FloatToRawbits(kFP32NegativeInfinity)};
+
+  FPBinArithHelper(config, fn, kSRegSize, zn_inputs, zm_inputs, expected_s);
+
+  uint64_t expected_d[] = {DoubleToRawbits(-1000.0),
+                           DoubleToRawbits(-2042.5),
+                           DoubleToRawbits(-0.1),
+                           DoubleToRawbits(8.625),
+                           DoubleToRawbits(-10.215),
+                           DoubleToRawbits(kFP64PositiveInfinity),
+                           DoubleToRawbits(kFP64NegativeInfinity)};
+
+  FPBinArithHelper(config, fn, kDRegSize, zn_inputs, zm_inputs, expected_d);
+}
+
+TEST_SVE(sve_fp_arithmetic_unpredicated_fmul) {
+  double zn_inputs[] = {24.0,
+                        5.5,
+                        0.0,
+                        3.875,
+                        2.125,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity};
+
+  double zm_inputs[] = {1024.0, 2048.0, 0.1, -4.75, 12.34, 255.0, -13.0};
+
+  ArithFn fn = &MacroAssembler::Fmul;
+
+  uint16_t expected_h[] = {Float16ToRawbits(Float16(24576.0)),
+                           Float16ToRawbits(Float16(11264.0)),
+                           Float16ToRawbits(Float16(0.0)),
+                           Float16ToRawbits(Float16(-18.4)),
+                           Float16ToRawbits(Float16(26.23)),
+                           Float16ToRawbits(kFP16PositiveInfinity),
+                           Float16ToRawbits(kFP16PositiveInfinity)};
+
+  FPBinArithHelper(config, fn, kHRegSize, zn_inputs, zm_inputs, expected_h);
+
+  uint32_t expected_s[] = {FloatToRawbits(24576.0),
+                           FloatToRawbits(11264.0),
+                           FloatToRawbits(0.0),
+                           FloatToRawbits(-18.40625),
+                           FloatToRawbits(26.2225),
+                           FloatToRawbits(kFP32PositiveInfinity),
+                           FloatToRawbits(kFP32PositiveInfinity)};
+
+  FPBinArithHelper(config, fn, kSRegSize, zn_inputs, zm_inputs, expected_s);
+
+  uint64_t expected_d[] = {DoubleToRawbits(24576.0),
+                           DoubleToRawbits(11264.0),
+                           DoubleToRawbits(0.0),
+                           DoubleToRawbits(-18.40625),
+                           DoubleToRawbits(26.2225),
+                           DoubleToRawbits(kFP64PositiveInfinity),
+                           DoubleToRawbits(kFP64PositiveInfinity)};
+
+  FPBinArithHelper(config, fn, kDRegSize, zn_inputs, zm_inputs, expected_d);
+}
+
+typedef void (MacroAssembler::*FPArithPredicatedFn)(
+    const ZRegister& zd,
+    const PRegisterM& pg,
+    const ZRegister& zn,
+    const ZRegister& zm,
+    FPMacroNaNPropagationOption nan_option);
+
+typedef void (MacroAssembler::*FPArithPredicatedNoNaNOptFn)(
+    const ZRegister& zd,
+    const PRegisterM& pg,
+    const ZRegister& zn,
+    const ZRegister& zm);
+
+template <typename Ti, typename Te, size_t N>
+static void FPBinArithHelper(
+    Test* config,
+    FPArithPredicatedFn macro,
+    FPArithPredicatedNoNaNOptFn macro_nonan,
+    unsigned lane_size_in_bits,
+    const Ti (&zd_inputs)[N],
+    const int (&pg_inputs)[N],
+    const Ti (&zn_inputs)[N],
+    const Ti (&zm_inputs)[N],
+    const Te (&zd_expected)[N],
+    FPMacroNaNPropagationOption nan_option = FastNaNPropagation) {
+  VIXL_ASSERT((macro == NULL) ^ (macro_nonan == NULL));
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Avoid choosing default scratch registers.
+  ZRegister zd = z26.WithLaneSize(lane_size_in_bits);
+  ZRegister zn = z27.WithLaneSize(lane_size_in_bits);
+  ZRegister zm = z28.WithLaneSize(lane_size_in_bits);
+
+  uint64_t zn_inputs_rawbits[N];
+  uint64_t zm_inputs_rawbits[N];
+  uint64_t zd_inputs_rawbits[N];
+
+  FPToRawbitsWithSize(zn_inputs, zn_inputs_rawbits, lane_size_in_bits);
+  FPToRawbitsWithSize(zm_inputs, zm_inputs_rawbits, lane_size_in_bits);
+  FPToRawbitsWithSize(zd_inputs, zd_inputs_rawbits, lane_size_in_bits);
+
+  InsrHelper(&masm, zn, zn_inputs_rawbits);
+  InsrHelper(&masm, zm, zm_inputs_rawbits);
+  InsrHelper(&masm, zd, zd_inputs_rawbits);
+
+  PRegisterWithLaneSize pg = p0.WithLaneSize(lane_size_in_bits);
+  Initialise(&masm, pg, pg_inputs);
+
+  // `instr` zdn, pg, zdn, zm
+  ZRegister dn_result = z0.WithLaneSize(lane_size_in_bits);
+  __ Mov(dn_result, zn);
+  if (macro_nonan == NULL) {
+    (masm.*macro)(dn_result, pg.Merging(), dn_result, zm, nan_option);
+  } else {
+    (masm.*macro_nonan)(dn_result, pg.Merging(), dn_result, zm);
+  }
+
+  // Based on whether zd and zm registers are aliased, the macro of instructions
+  // (`Instr`) swaps the order of operands if it has the commutative property,
+  // otherwise, transfer to the reversed `Instr`, such as fdivr.
+  // `instr` zdm, pg, zn, zdm
+  ZRegister dm_result = z1.WithLaneSize(lane_size_in_bits);
+  __ Mov(dm_result, zm);
+  if (macro_nonan == NULL) {
+    (masm.*macro)(dm_result, pg.Merging(), zn, dm_result, nan_option);
+  } else {
+    (masm.*macro_nonan)(dm_result, pg.Merging(), zn, dm_result);
+  }
+
+  // The macro of instructions (`Instr`) automatically selects between `instr`
+  // and movprfx + `instr` based on whether zd and zn registers are aliased.
+  // A generated movprfx instruction is predicated that using the same
+  // governing predicate register. In order to keep the result constant,
+  // initialize the destination register first.
+  // `instr` zd, pg, zn, zm
+  ZRegister d_result = z2.WithLaneSize(lane_size_in_bits);
+  __ Mov(d_result, zd);
+  if (macro_nonan == NULL) {
+    (masm.*macro)(d_result, pg.Merging(), zn, zm, nan_option);
+  } else {
+    (masm.*macro_nonan)(d_result, pg.Merging(), zn, zm);
+  }
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    for (size_t i = 0; i < ArrayLength(zd_expected); i++) {
+      int lane = static_cast<int>(ArrayLength(zd_expected) - i - 1);
+      if (!core.HasSVELane(dn_result, lane)) break;
+      if ((pg_inputs[i] & 1) != 0) {
+        ASSERT_EQUAL_SVE_LANE(zd_expected[i], dn_result, lane);
+      } else {
+        ASSERT_EQUAL_SVE_LANE(zn_inputs_rawbits[i], dn_result, lane);
+      }
+    }
+
+    for (size_t i = 0; i < ArrayLength(zd_expected); i++) {
+      int lane = static_cast<int>(ArrayLength(zd_expected) - i - 1);
+      if (!core.HasSVELane(dm_result, lane)) break;
+      if ((pg_inputs[i] & 1) != 0) {
+        ASSERT_EQUAL_SVE_LANE(zd_expected[i], dm_result, lane);
+      } else {
+        ASSERT_EQUAL_SVE_LANE(zm_inputs_rawbits[i], dm_result, lane);
+      }
+    }
+
+    ASSERT_EQUAL_SVE(zd_expected, d_result);
+  }
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_fdiv) {
+  // The inputs are shared with different precision tests.
+  double zd_in[] = {0.1, 1.1, 2.2, 3.3, 4.4, 5.5, 6.6, 7.7, 8.8, 9.9};
+
+  double zn_in[] = {24.0,
+                    24.0,
+                    -2.0,
+                    -2.0,
+                    5.5,
+                    5.5,
+                    kFP64PositiveInfinity,
+                    kFP64PositiveInfinity,
+                    kFP64NegativeInfinity,
+                    kFP64NegativeInfinity};
+
+  double zm_in[] = {-2.0, -2.0, 24.0, 24.0, 0.5, 0.5, 0.65, 0.65, 24.0, 24.0};
+
+  int pg_in[] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1};
+
+  uint16_t exp_h[] = {Float16ToRawbits(Float16(0.1)),
+                      Float16ToRawbits(Float16(-12.0)),
+                      Float16ToRawbits(Float16(2.2)),
+                      Float16ToRawbits(Float16(-0.0833)),
+                      Float16ToRawbits(Float16(4.4)),
+                      Float16ToRawbits(Float16(11.0)),
+                      Float16ToRawbits(Float16(6.6)),
+                      Float16ToRawbits(kFP16PositiveInfinity),
+                      Float16ToRawbits(Float16(8.8)),
+                      Float16ToRawbits(kFP16NegativeInfinity)};
+
+  FPBinArithHelper(config,
+                   NULL,
+                   &MacroAssembler::Fdiv,
+                   kHRegSize,
+                   zd_in,
+                   pg_in,
+                   zn_in,
+                   zm_in,
+                   exp_h);
+
+  uint32_t exp_s[] = {FloatToRawbits(0.1),
+                      FloatToRawbits(-12.0),
+                      FloatToRawbits(2.2),
+                      0xbdaaaaab,
+                      FloatToRawbits(4.4),
+                      FloatToRawbits(11.0),
+                      FloatToRawbits(6.6),
+                      FloatToRawbits(kFP32PositiveInfinity),
+                      FloatToRawbits(8.8),
+                      FloatToRawbits(kFP32NegativeInfinity)};
+
+  FPBinArithHelper(config,
+                   NULL,
+                   &MacroAssembler::Fdiv,
+                   kSRegSize,
+                   zd_in,
+                   pg_in,
+                   zn_in,
+                   zm_in,
+                   exp_s);
+
+  uint64_t exp_d[] = {DoubleToRawbits(0.1),
+                      DoubleToRawbits(-12.0),
+                      DoubleToRawbits(2.2),
+                      0xbfb5555555555555,
+                      DoubleToRawbits(4.4),
+                      DoubleToRawbits(11.0),
+                      DoubleToRawbits(6.6),
+                      DoubleToRawbits(kFP64PositiveInfinity),
+                      DoubleToRawbits(8.8),
+                      DoubleToRawbits(kFP64NegativeInfinity)};
+
+  FPBinArithHelper(config,
+                   NULL,
+                   &MacroAssembler::Fdiv,
+                   kDRegSize,
+                   zd_in,
+                   pg_in,
+                   zn_in,
+                   zm_in,
+                   exp_d);
+}
+
+TEST_SVE(sve_select) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in0[] = {0x01f203f405f607f8, 0xfefcf8f0e1c3870f, 0x123456789abcdef0};
+  uint64_t in1[] = {0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa, 0xaaaaaaaaaaaaaaaa};
+
+  // For simplicity, we re-use the same pg for various lane sizes.
+  // For D lanes:         1,                      1,                      0
+  // For S lanes:         1,          1,          1,          0,          0
+  // For H lanes:   0,    1,    0,    1,    1,    1,    0,    0,    1,    0
+  int pg_in[] = {1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0};
+  Initialise(&masm, p0.VnB(), pg_in);
+  PRegisterM pg = p0.Merging();
+
+  InsrHelper(&masm, z30.VnD(), in0);
+  InsrHelper(&masm, z31.VnD(), in1);
+
+  __ Sel(z0.VnB(), pg, z30.VnB(), z31.VnB());
+  __ Sel(z1.VnH(), pg, z30.VnH(), z31.VnH());
+  __ Sel(z2.VnS(), pg, z30.VnS(), z31.VnS());
+  __ Sel(z3.VnD(), pg, z30.VnD(), z31.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t expected_z0[] = {0xaaaaaaaa05aa07f8,
+                              0xfeaaaaf0aac3870f,
+                              0xaaaa56aa9abcdeaa};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+
+    uint64_t expected_z1[] = {0xaaaaaaaaaaaa07f8,
+                              0xaaaaf8f0e1c3870f,
+                              0xaaaaaaaa9abcaaaa};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+
+    uint64_t expected_z2[] = {0xaaaaaaaa05f607f8,
+                              0xfefcf8f0e1c3870f,
+                              0xaaaaaaaaaaaaaaaa};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+
+    uint64_t expected_z3[] = {0x01f203f405f607f8,
+                              0xfefcf8f0e1c3870f,
+                              0xaaaaaaaaaaaaaaaa};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+  }
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_fmax_fmin_h) {
+  double zd_inputs[] = {1.1, 2.2, 3.3, 4.4, 5.5, 6.6, 7.7, 8.8};
+  double zn_inputs[] = {-2.1,
+                        8.5,
+                        225.5,
+                        0.0,
+                        8.8,
+                        -4.75,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity};
+  double zm_inputs[] = {-2.0,
+                        -13.0,
+                        24.0,
+                        0.01,
+                        0.5,
+                        300.75,
+                        kFP64NegativeInfinity,
+                        kFP64PositiveInfinity};
+  int pg_inputs[] = {1, 1, 0, 1, 0, 1, 1, 1};
+
+  uint16_t zd_expected_max[] = {Float16ToRawbits(Float16(-2.0)),
+                                Float16ToRawbits(Float16(8.5)),
+                                Float16ToRawbits(Float16(3.3)),
+                                Float16ToRawbits(Float16(0.01)),
+                                Float16ToRawbits(Float16(5.5)),
+                                Float16ToRawbits(Float16(300.75)),
+                                Float16ToRawbits(kFP16PositiveInfinity),
+                                Float16ToRawbits(kFP16PositiveInfinity)};
+  FPBinArithHelper(config,
+                   &MacroAssembler::Fmax,
+                   NULL,
+                   kHRegSize,
+                   zd_inputs,
+                   pg_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_max);
+
+  uint16_t zd_expected_min[] = {Float16ToRawbits(Float16(-2.1)),
+                                Float16ToRawbits(Float16(-13.0)),
+                                Float16ToRawbits(Float16(3.3)),
+                                Float16ToRawbits(Float16(0.0)),
+                                Float16ToRawbits(Float16(5.5)),
+                                Float16ToRawbits(Float16(-4.75)),
+                                Float16ToRawbits(kFP16NegativeInfinity),
+                                Float16ToRawbits(kFP16NegativeInfinity)};
+  FPBinArithHelper(config,
+                   &MacroAssembler::Fmin,
+                   NULL,
+                   kHRegSize,
+                   zd_inputs,
+                   pg_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_min);
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_fmax_fmin_s) {
+  double zd_inputs[] = {1.1, 2.2, 3.3, 4.4, 5.5, 6.6, 7.7, 8.8};
+  double zn_inputs[] = {-2.1,
+                        8.5,
+                        225.5,
+                        0.0,
+                        8.8,
+                        -4.75,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity};
+  double zm_inputs[] = {-2.0,
+                        -13.0,
+                        24.0,
+                        0.01,
+                        0.5,
+                        300.75,
+                        kFP64NegativeInfinity,
+                        kFP64PositiveInfinity};
+  int pg_inputs[] = {1, 1, 0, 1, 0, 1, 1, 1};
+
+  uint32_t zd_expected_max[] = {FloatToRawbits(-2.0),
+                                FloatToRawbits(8.5),
+                                FloatToRawbits(3.3),
+                                FloatToRawbits(0.01),
+                                FloatToRawbits(5.5),
+                                FloatToRawbits(300.75),
+                                FloatToRawbits(kFP32PositiveInfinity),
+                                FloatToRawbits(kFP32PositiveInfinity)};
+  FPBinArithHelper(config,
+                   &MacroAssembler::Fmax,
+                   NULL,
+                   kSRegSize,
+                   zd_inputs,
+                   pg_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_max);
+
+  uint32_t zd_expected_min[] = {FloatToRawbits(-2.1),
+                                FloatToRawbits(-13.0),
+                                FloatToRawbits(3.3),
+                                FloatToRawbits(0.0),
+                                FloatToRawbits(5.5),
+                                FloatToRawbits(-4.75),
+                                FloatToRawbits(kFP32NegativeInfinity),
+                                FloatToRawbits(kFP32NegativeInfinity)};
+  FPBinArithHelper(config,
+                   &MacroAssembler::Fmin,
+                   NULL,
+                   kSRegSize,
+                   zd_inputs,
+                   pg_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_min);
+}
+
+TEST_SVE(sve_binary_arithmetic_predicated_fmax_fmin_d) {
+  double zd_inputs[] = {1.1, 2.2, 3.3, 4.4, 5.5, 6.6, 7.7, 8.8};
+  double zn_inputs[] = {-2.1,
+                        8.5,
+                        225.5,
+                        0.0,
+                        8.8,
+                        -4.75,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity};
+  double zm_inputs[] = {-2.0,
+                        -13.0,
+                        24.0,
+                        0.01,
+                        0.5,
+                        300.75,
+                        kFP64NegativeInfinity,
+                        kFP64PositiveInfinity};
+  int pg_inputs[] = {1, 1, 0, 1, 0, 1, 1, 1};
+
+  uint64_t zd_expected_max[] = {DoubleToRawbits(-2.0),
+                                DoubleToRawbits(8.5),
+                                DoubleToRawbits(3.3),
+                                DoubleToRawbits(0.01),
+                                DoubleToRawbits(5.5),
+                                DoubleToRawbits(300.75),
+                                DoubleToRawbits(kFP64PositiveInfinity),
+                                DoubleToRawbits(kFP64PositiveInfinity)};
+  FPBinArithHelper(config,
+                   &MacroAssembler::Fmax,
+                   NULL,
+                   kDRegSize,
+                   zd_inputs,
+                   pg_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_max);
+
+  uint64_t zd_expected_min[] = {DoubleToRawbits(-2.1),
+                                DoubleToRawbits(-13.0),
+                                DoubleToRawbits(3.3),
+                                DoubleToRawbits(0.0),
+                                DoubleToRawbits(5.5),
+                                DoubleToRawbits(-4.75),
+                                DoubleToRawbits(kFP64NegativeInfinity),
+                                DoubleToRawbits(kFP64NegativeInfinity)};
+  FPBinArithHelper(config,
+                   &MacroAssembler::Fmin,
+                   NULL,
+                   kDRegSize,
+                   zd_inputs,
+                   pg_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected_min);
+}
+
+template <typename T, size_t N>
+static void BitwiseShiftImmHelper(Test* config,
+                                  int lane_size_in_bits,
+                                  const T (&zn_inputs)[N],
+                                  int shift) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  ZRegister zd_asr = z25.WithLaneSize(lane_size_in_bits);
+  ZRegister zd_lsr = z26.WithLaneSize(lane_size_in_bits);
+  ZRegister zd_lsl = z27.WithLaneSize(lane_size_in_bits);
+  ZRegister zn = z28.WithLaneSize(lane_size_in_bits);
+
+  InsrHelper(&masm, zn, zn_inputs);
+
+  __ Asr(zd_asr, zn, shift);
+  __ Lsr(zd_lsr, zn, shift);
+  __ Lsl(zd_lsl, zn, shift - 1);  // Lsl supports 0 - lane_size-1.
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    const uint64_t mask = GetUintMask(lane_size_in_bits);
+    for (int i = 0; i < static_cast<int>(N); i++) {
+      int lane = N - i - 1;
+      if (!core.HasSVELane(zd_asr, lane)) break;
+      bool is_negative = (zn_inputs[i] & GetSignMask(lane_size_in_bits)) != 0;
+      uint64_t result;
+      if (shift >= lane_size_in_bits) {
+        result = is_negative ? mask : 0;
+      } else {
+        result = zn_inputs[i] >> shift;
+        if (is_negative) {
+          result |= mask << (lane_size_in_bits - shift);
+          result &= mask;
+        }
+      }
+      ASSERT_EQUAL_SVE_LANE(result, zd_asr, lane);
+    }
+
+    for (int i = 0; i < static_cast<int>(N); i++) {
+      int lane = N - i - 1;
+      if (!core.HasSVELane(zd_lsr, lane)) break;
+      uint64_t result =
+          (shift >= lane_size_in_bits) ? 0 : zn_inputs[i] >> shift;
+      ASSERT_EQUAL_SVE_LANE(result, zd_lsr, lane);
+    }
+
+    for (int i = 0; i < static_cast<int>(N); i++) {
+      int lane = N - i - 1;
+      if (!core.HasSVELane(zd_lsl, lane)) break;
+      uint64_t result =
+          (shift > lane_size_in_bits) ? 0 : zn_inputs[i] << (shift - 1);
+      ASSERT_EQUAL_SVE_LANE(result & mask, zd_lsl, lane);
+    }
+  }
+}
+
+TEST_SVE(sve_bitwise_shift_imm_unpredicated) {
+  uint64_t inputs_b[] = {0xfe, 0xdc, 0xba, 0x98, 0xff, 0x55, 0xaa, 0x80};
+  int shift_b[] = {1, 3, 5, 8};
+  for (size_t i = 0; i < ArrayLength(shift_b); i++) {
+    BitwiseShiftImmHelper(config, kBRegSize, inputs_b, shift_b[i]);
+  }
+
+  uint64_t inputs_h[] = {0xfedc, 0xfa55, 0x0011, 0x2233};
+  int shift_h[] = {1, 8, 11, 16};
+  for (size_t i = 0; i < ArrayLength(shift_h); i++) {
+    BitwiseShiftImmHelper(config, kHRegSize, inputs_h, shift_h[i]);
+  }
+
+  uint64_t inputs_s[] = {0xfedcba98, 0xfffa55aa, 0x00112233};
+  int shift_s[] = {1, 9, 17, 32};
+  for (size_t i = 0; i < ArrayLength(shift_s); i++) {
+    BitwiseShiftImmHelper(config, kSRegSize, inputs_s, shift_s[i]);
+  }
+
+  uint64_t inputs_d[] = {0xfedcba98fedcba98,
+                         0xfffa5555aaaaaaaa,
+                         0x0011223344aafe80};
+  int shift_d[] = {1, 23, 45, 64};
+  for (size_t i = 0; i < ArrayLength(shift_d); i++) {
+    BitwiseShiftImmHelper(config, kDRegSize, inputs_d, shift_d[i]);
+  }
+}
+
+template <typename T, typename R, size_t N>
+static void BitwiseShiftWideElementsHelper(Test* config,
+                                           Shift shift_type,
+                                           int lane_size_in_bits,
+                                           const T (&zn_inputs)[N],
+                                           const R& zm_inputs,
+                                           const T (&zd_expected)[N]) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  ArithFn macro;
+  // Since logical shift left and right by the current lane size width is equal
+  // to 0, so initialize the array to 0 for convenience.
+  uint64_t zd_expected_max_shift_amount[N] = {0};
+  switch (shift_type) {
+    case ASR: {
+      macro = &MacroAssembler::Asr;
+      uint64_t mask = GetUintMask(lane_size_in_bits);
+      for (size_t i = 0; i < ArrayLength(zn_inputs); i++) {
+        bool is_negative = (zn_inputs[i] & GetSignMask(lane_size_in_bits)) != 0;
+        zd_expected_max_shift_amount[i] = is_negative ? mask : 0;
+      }
+      break;
+    }
+    case LSR:
+      macro = &MacroAssembler::Lsr;
+      break;
+    case LSL:
+      macro = &MacroAssembler::Lsl;
+      break;
+    default:
+      VIXL_UNIMPLEMENTED();
+      macro = NULL;
+      break;
+  }
+
+  ZRegister zd = z26.WithLaneSize(lane_size_in_bits);
+  ZRegister zn = z27.WithLaneSize(lane_size_in_bits);
+  ZRegister zm = z28.WithLaneSize(kDRegSize);
+
+  InsrHelper(&masm, zn, zn_inputs);
+  InsrHelper(&masm, zm, zm_inputs);
+
+  (masm.*macro)(zd, zn, zm);
+
+  ZRegister zm_max_shift_amount = z25.WithLaneSize(kDRegSize);
+  ZRegister zd_max_shift_amount = z24.WithLaneSize(lane_size_in_bits);
+
+  __ Dup(zm_max_shift_amount, lane_size_in_bits);
+  (masm.*macro)(zd_max_shift_amount, zn, zm_max_shift_amount);
+
+  ZRegister zm_out_of_range = z23.WithLaneSize(kDRegSize);
+  ZRegister zd_out_of_range = z22.WithLaneSize(lane_size_in_bits);
+
+  __ Dup(zm_out_of_range, GetUintMask(lane_size_in_bits));
+  (masm.*macro)(zd_out_of_range, zn, zm_out_of_range);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(zd_expected, zd);
+    ASSERT_EQUAL_SVE(zd_expected_max_shift_amount, zd_max_shift_amount);
+    ASSERT_EQUAL_SVE(zd_max_shift_amount, zd_out_of_range);
+  }
+}
+
+TEST_SVE(sve_bitwise_shift_wide_elements_unpredicated_asr) {
+  // clang-format off
+  uint64_t inputs_b[] = {0xfe, 0xdc, 0xba, 0x98, 0xff, 0x55, 0xaa, 0x80,
+                         0xfe, 0xdc, 0xba, 0x98, 0xff, 0x55, 0xaa, 0x80};
+  int shift_b[] = {1, 3};
+  uint64_t expected_b[] = {0xff, 0xee, 0xdd, 0xcc, 0xff, 0x2a, 0xd5, 0xc0,
+                           0xff, 0xfb, 0xf7, 0xf3, 0xff, 0x0a, 0xf5, 0xf0};
+  BitwiseShiftWideElementsHelper(config,
+                                 ASR,
+                                 kBRegSize,
+                                 inputs_b,
+                                 shift_b,
+                                 expected_b);
+
+  uint64_t inputs_h[] = {0xfedc, 0xfa55, 0x0011, 0x2233,
+                         0xfedc, 0xfa55, 0x0011, 0x2233,
+                         0xfedc, 0xfa55, 0x0011, 0x2233};
+  int shift_h[] = {1, 8, 11};
+  uint64_t expected_h[] = {0xff6e, 0xfd2a, 0x0008, 0x1119,
+                           0xfffe, 0xfffa, 0x0000, 0x0022,
+                           0xffff, 0xffff, 0x0000, 0x0004};
+  BitwiseShiftWideElementsHelper(config,
+                                 ASR,
+                                 kHRegSize,
+                                 inputs_h,
+                                 shift_h,
+                                 expected_h);
+
+  uint64_t inputs_s[] =
+      {0xfedcba98, 0xfffa55aa, 0x00112233, 0x01234567, 0xaaaaaaaa, 0x88888888};
+  int shift_s[] = {1, 9, 23};
+  uint64_t expected_s[] =
+      {0xff6e5d4c, 0xfffd2ad5, 0x00000891, 0x000091a2, 0xffffff55, 0xffffff11};
+  BitwiseShiftWideElementsHelper(config,
+                                 ASR,
+                                 kSRegSize,
+                                 inputs_s,
+                                 shift_s,
+                                 expected_s);
+  // clang-format on
+}
+
+TEST_SVE(sve_bitwise_shift_wide_elements_unpredicated_lsr) {
+  // clang-format off
+  uint64_t inputs_b[] = {0xfe, 0xdc, 0xba, 0x98, 0xff, 0x55, 0xaa, 0x80,
+                         0xfe, 0xdc, 0xba, 0x98, 0xff, 0x55, 0xaa, 0x80};
+  int shift_b[] = {1, 3};
+  uint64_t expected_b[] = {0x7f, 0x6e, 0x5d, 0x4c, 0x7f, 0x2a, 0x55, 0x40,
+                           0x1f, 0x1b, 0x17, 0x13, 0x1f, 0x0a, 0x15, 0x10};
+
+  BitwiseShiftWideElementsHelper(config,
+                                 LSR,
+                                 kBRegSize,
+                                 inputs_b,
+                                 shift_b,
+                                 expected_b);
+
+  uint64_t inputs_h[] = {0xfedc, 0xfa55, 0x0011, 0x2233,
+                         0xfedc, 0xfa55, 0x0011, 0x2233,
+                         0xfedc, 0xfa55, 0x0011, 0x2233};
+  int shift_h[] = {1, 8, 11};
+  uint64_t expected_h[] = {0x7f6e, 0x7d2a, 0x0008, 0x1119,
+                           0x00fe, 0x00fa, 0x0000, 0x0022,
+                           0x001f, 0x001f, 0x0000, 0x0004};
+  BitwiseShiftWideElementsHelper(config,
+                                 LSR,
+                                 kHRegSize,
+                                 inputs_h,
+                                 shift_h,
+                                 expected_h);
+
+  uint64_t inputs_s[] =
+      {0xfedcba98, 0xfffa55aa, 0x00112233, 0x01234567, 0xaaaaaaaa, 0x88888888};
+  int shift_s[] = {1, 9, 23};
+  uint64_t expected_s[] =
+      {0x7f6e5d4c, 0x7ffd2ad5, 0x00000891, 0x000091a2, 0x00000155, 0x00000111};
+  BitwiseShiftWideElementsHelper(config,
+                                 LSR,
+                                 kSRegSize,
+                                 inputs_s,
+                                 shift_s,
+                                 expected_s);
+  // clang-format on
+}
+
+TEST_SVE(sve_bitwise_shift_wide_elements_unpredicated_lsl) {
+  // clang-format off
+  uint64_t inputs_b[] = {0xfe, 0xdc, 0xba, 0x98, 0xff, 0x55, 0xaa, 0x80,
+                         0xfe, 0xdc, 0xba, 0x98, 0xff, 0x55, 0xaa, 0x80};
+  int shift_b[] = {1, 5};
+
+  uint64_t expected_b[] = {0xfc, 0xb8, 0x74, 0x30, 0xfe, 0xaa, 0x54, 0x00,
+                           0xc0, 0x80, 0x40, 0x00, 0xe0, 0xa0, 0x40, 0x00};
+
+  BitwiseShiftWideElementsHelper(config,
+                                 LSL,
+                                 kBRegSize,
+                                 inputs_b,
+                                 shift_b,
+                                 expected_b);
+  uint64_t inputs_h[] = {0xfedc, 0xfa55, 0x0011, 0x2233,
+                         0xfedc, 0xfa55, 0x0011, 0x2233,
+                         0xfedc, 0xfa55, 0x0011, 0x2233};
+  int shift_h[] = {1, 2, 14};
+
+  uint64_t expected_h[] = {0xfdb8, 0xf4aa, 0x0022, 0x4466,
+                           0xfb70, 0xe954, 0x0044, 0x88cc,
+                           0x0000, 0x4000, 0x4000, 0xc000};
+  BitwiseShiftWideElementsHelper(config,
+                                 LSL,
+                                 kHRegSize,
+                                 inputs_h,
+                                 shift_h,
+                                 expected_h);
+  uint64_t inputs_s[] =
+      {0xfedcba98, 0xfffa55aa, 0x00112233, 0x01234567, 0xaaaaaaaa, 0x88888888};
+  int shift_s[] = {1, 19, 26};
+  uint64_t expected_s[] =
+      {0xfdb97530, 0xfff4ab54, 0x11980000, 0x2b380000, 0xa8000000, 0x20000000};
+  BitwiseShiftWideElementsHelper(config,
+                                 LSL,
+                                 kSRegSize,
+                                 inputs_s,
+                                 shift_s,
+                                 expected_s);
+
+  // Test large shifts outside the range of the "unsigned" type.
+  uint64_t inputs_b2[] = {1, 2, 4, 8, 3, 5, 7, 9,
+                          1, 2, 4, 8, 3, 5, 7, 9};
+  uint64_t shift_b2[] = {1, 0x1000000001};
+  uint64_t expected_b2[] = {2, 4, 8, 16, 6, 10, 14, 18,
+                            0, 0, 0, 0, 0, 0, 0, 0};
+  BitwiseShiftWideElementsHelper(config, LSL, kBRegSize, inputs_b2, shift_b2,
+                                 expected_b2);
+
+  // clang-format on
+}
+
+TEST_SVE(sve_shift_by_vector) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p2.VnB(), p0.VnB(), p1.VnB());
+  __ Zip1(p3.VnH(), p0.VnH(), p1.VnH());
+  __ Zip1(p4.VnS(), p0.VnS(), p1.VnS());
+  __ Zip1(p5.VnD(), p0.VnD(), p1.VnD());
+
+  __ Dup(z31.VnD(), 0x8000000080008080);
+  __ Dup(z0.VnB(), -1);
+
+  __ Index(z1.VnB(), 0, 1);
+  __ Dup(z2.VnB(), 0x55);
+  __ Lsr(z2.VnB(), p2.Merging(), z0.VnB(), z1.VnB());
+  __ Lsl(z3.VnB(), p0.Merging(), z0.VnB(), z1.VnB());
+  __ Asr(z4.VnB(), p0.Merging(), z31.VnB(), z1.VnB());
+
+  __ Index(z1.VnH(), 0, 1);
+  __ Dup(z6.VnB(), 0x55);
+  __ Lsr(z5.VnH(), p0.Merging(), z0.VnH(), z1.VnH());
+  __ Lsl(z6.VnH(), p3.Merging(), z0.VnH(), z1.VnH());
+  __ Asr(z7.VnH(), p0.Merging(), z31.VnH(), z1.VnH());
+
+  __ Index(z1.VnS(), 0, 1);
+  __ Dup(z10.VnB(), 0x55);
+  __ Lsr(z8.VnS(), p0.Merging(), z0.VnS(), z1.VnS());
+  __ Lsl(z9.VnS(), p0.Merging(), z0.VnS(), z1.VnS());
+  __ Asr(z10.VnS(), p4.Merging(), z31.VnS(), z1.VnS());
+
+  __ Index(z1.VnD(), 0, 1);
+  __ Lsr(z0.VnD(), p5.Merging(), z0.VnD(), z1.VnD());
+  __ Lsl(z12.VnD(), p0.Merging(), z0.VnD(), z1.VnD());
+  __ Asr(z13.VnD(), p0.Merging(), z31.VnD(), z1.VnD());
+
+  __ Dup(z11.VnD(), 0x100000001);
+  __ Lsl(z14.VnD(), p0.Merging(), z1.VnD(), z11.VnD());
+
+  __ Index(z0.VnH(), 7, -1);
+  __ Lsr(z0.VnH(), p0.Merging(), z31.VnH(), z0.VnH());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t expected_z0[] = {0x8000000020001010, 0x0800000002000101};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+    uint64_t expected_z2[] = {0x5500550055005500, 0x5503550f553f55ff};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0x0000000000000000, 0x80c0e0f0f8fcfeff};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xff000000ff00ffff, 0xff000000f000c080};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x01ff03ff07ff0fff, 0x1fff3fff7fffffff};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x5555ffc05555fff0, 0x5555fffc5555ffff};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0xff000000fc00f808, 0xf0000000c0008080};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0x1fffffff3fffffff, 0x7fffffffffffffff};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0xfffffff8fffffffc, 0xfffffffeffffffff};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x55555555e0002020, 0x5555555580008080};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+    uint64_t expected_z12[] = {0xfffffffffffffffe, 0xffffffffffffffff};
+    ASSERT_EQUAL_SVE(expected_z12, z12.VnD());
+    uint64_t expected_z13[] = {0xc000000040004040, 0x8000000080008080};
+    ASSERT_EQUAL_SVE(expected_z13, z13.VnD());
+    uint64_t expected_z14[] = {0, 0};
+    ASSERT_EQUAL_SVE(expected_z14, z14.VnD());
+  }
+}
+
+TEST_SVE(sve_shift_by_wide_vector) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p2.VnB(), p0.VnB(), p1.VnB());
+  __ Zip1(p3.VnH(), p0.VnH(), p1.VnH());
+  __ Zip1(p4.VnS(), p0.VnS(), p1.VnS());
+
+  __ Dup(z31.VnD(), 0x8000000080008080);
+  __ Dup(z0.VnB(), -1);
+  __ Index(z1.VnD(), 1, 5);
+
+  __ Dup(z2.VnB(), 0x55);
+  __ Lsr(z2.VnB(), p2.Merging(), z2.VnB(), z1.VnD());
+  __ Lsl(z3.VnB(), p0.Merging(), z0.VnB(), z1.VnD());
+  __ Asr(z4.VnB(), p0.Merging(), z31.VnB(), z1.VnD());
+
+  __ Dup(z6.VnB(), 0x55);
+  __ Lsr(z5.VnH(), p0.Merging(), z0.VnH(), z1.VnD());
+  __ Lsl(z6.VnH(), p3.Merging(), z6.VnH(), z1.VnD());
+  __ Asr(z7.VnH(), p0.Merging(), z31.VnH(), z1.VnD());
+
+  __ Dup(z10.VnB(), 0x55);
+  __ Lsr(z8.VnS(), p0.Merging(), z0.VnS(), z1.VnD());
+  __ Lsl(z9.VnS(), p0.Merging(), z0.VnS(), z1.VnD());
+  __ Asr(z10.VnS(), p4.Merging(), z31.VnS(), z1.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t expected_z2[] = {0x5501550155015501, 0x552a552a552a552a};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0xc0c0c0c0c0c0c0c0, 0xfefefefefefefefe};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xfe000000fe00fefe, 0xc0000000c000c0c0};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x03ff03ff03ff03ff, 0x7fff7fff7fff7fff};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x5555554055555540, 0x5555aaaa5555aaaa};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0xfe000000fe00fe02, 0xc0000000c000c040};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0x03ffffff03ffffff, 0x7fffffff7fffffff};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0xffffffc0ffffffc0, 0xfffffffefffffffe};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x55555555fe000202, 0x55555555c0004040};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+  }
+}
+
+TEST_SVE(sve_pred_shift_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p2.VnB(), p0.VnB(), p1.VnB());
+  __ Zip1(p3.VnH(), p0.VnH(), p1.VnH());
+  __ Zip1(p4.VnS(), p0.VnS(), p1.VnS());
+  __ Zip1(p5.VnD(), p0.VnD(), p1.VnD());
+
+  __ Dup(z31.VnD(), 0x8000000080008080);
+  __ Lsr(z0.VnB(), p0.Merging(), z31.VnB(), 1);
+  __ Mov(z1, z0);
+  __ Lsl(z1.VnB(), p2.Merging(), z1.VnB(), 1);
+  __ Asr(z2.VnB(), p0.Merging(), z1.VnB(), 2);
+
+  __ Lsr(z3.VnH(), p0.Merging(), z31.VnH(), 2);
+  __ Mov(z4, z3);
+  __ Lsl(z4.VnH(), p3.Merging(), z4.VnH(), 2);
+  __ Asr(z5.VnH(), p0.Merging(), z4.VnH(), 3);
+
+  __ Lsr(z6.VnS(), p0.Merging(), z31.VnS(), 3);
+  __ Mov(z7, z6);
+  __ Lsl(z7.VnS(), p4.Merging(), z7.VnS(), 3);
+  __ Asr(z8.VnS(), p0.Merging(), z7.VnS(), 4);
+
+  __ Lsr(z9.VnD(), p0.Merging(), z31.VnD(), 4);
+  __ Mov(z10, z9);
+  __ Lsl(z10.VnD(), p5.Merging(), z10.VnD(), 4);
+  __ Asr(z11.VnD(), p0.Merging(), z10.VnD(), 5);
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z0[] = {0x4000000040004040, 0x4000000040004040};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+    uint64_t expected_z1[] = {0x4000000040004080, 0x4000000040004080};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+    uint64_t expected_z2[] = {0x10000000100010e0, 0x10000000100010e0};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0x2000000020002020, 0x2000000020002020};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0x2000000020008080, 0x2000000020008080};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x040000000400f010, 0x040000000400f010};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x1000000010001010, 0x1000000010001010};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0x1000000080008080, 0x1000000080008080};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0x01000000f8000808, 0x01000000f8000808};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0x0800000008000808, 0x0800000008000808};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x0800000008000808, 0x8000000080008080};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+    uint64_t expected_z11[] = {0x0040000000400040, 0xfc00000004000404};
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+  }
+}
+
+TEST_SVE(sve_asrd) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p2.VnB(), p0.VnB(), p1.VnB());
+  __ Zip1(p3.VnH(), p0.VnH(), p1.VnH());
+  __ Zip1(p4.VnS(), p0.VnS(), p1.VnS());
+  __ Zip1(p5.VnD(), p0.VnD(), p1.VnD());
+
+  __ Index(z31.VnB(), 0x7f - 3, 1);
+  __ Asrd(z0.VnB(), p0.Merging(), z31.VnB(), 1);
+  __ Mov(z1, z31);
+  __ Asrd(z1.VnB(), p2.Merging(), z1.VnB(), 2);
+  __ Asrd(z2.VnB(), p0.Merging(), z31.VnB(), 7);
+  __ Asrd(z3.VnB(), p0.Merging(), z31.VnB(), 8);
+
+  __ Index(z31.VnH(), 0x7fff - 3, 1);
+  __ Asrd(z4.VnH(), p0.Merging(), z31.VnH(), 1);
+  __ Mov(z5, z31);
+  __ Asrd(z5.VnH(), p3.Merging(), z5.VnH(), 2);
+  __ Asrd(z6.VnH(), p0.Merging(), z31.VnH(), 15);
+  __ Asrd(z7.VnH(), p0.Merging(), z31.VnH(), 16);
+
+  __ Index(z31.VnS(), 0x7fffffff - 1, 1);
+  __ Asrd(z8.VnS(), p0.Merging(), z31.VnS(), 1);
+  __ Mov(z9, z31);
+  __ Asrd(z9.VnS(), p4.Merging(), z9.VnS(), 2);
+  __ Asrd(z10.VnS(), p0.Merging(), z31.VnS(), 31);
+  __ Asrd(z11.VnS(), p0.Merging(), z31.VnS(), 32);
+
+  __ Index(z31.VnD(), 0x7fffffffffffffff, 1);
+  __ Asrd(z12.VnD(), p0.Merging(), z31.VnD(), 1);
+  __ Mov(z13, z31);
+  __ Asrd(z13.VnD(), p5.Merging(), z13.VnD(), 2);
+  __ Asrd(z14.VnD(), p0.Merging(), z31.VnD(), 63);
+  __ Asrd(z31.VnD(), p0.Merging(), z31.VnD(), 64);
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z0[] = {0xc6c5c5c4c4c3c3c2, 0xc2c1c1c03f3f3e3e};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+    uint64_t expected_z1[] = {0x8be389e287e285e1, 0x83e181e07f1f7d1f};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+    uint64_t expected_z2[] = {0x0000000000000000, 0x000000ff00000000};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0x0000000000000000, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xc002c001c001c000, 0x3fff3fff3ffe3ffe};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x8003e0018001e000, 0x7fff1fff7ffd1fff};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x000000000000ffff, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0x0000000000000000, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0xc0000001c0000000, 0x3fffffff3fffffff};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0x80000001e0000000, 0x7fffffff1fffffff};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x00000000ffffffff, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+    uint64_t expected_z11[] = {0x0000000000000000, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+    uint64_t expected_z12[] = {0xc000000000000000, 0x3fffffffffffffff};
+    ASSERT_EQUAL_SVE(expected_z12, z12.VnD());
+    uint64_t expected_z13[] = {0x8000000000000000, 0x1fffffffffffffff};
+    ASSERT_EQUAL_SVE(expected_z13, z13.VnD());
+    uint64_t expected_z14[] = {0xffffffffffffffff, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z14, z14.VnD());
+    uint64_t expected_z31[] = {0x0000000000000000, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z31, z31.VnD());
+  }
+}
+
+TEST_SVE(sve_setffr) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Ptrue(p15.VnB());
+  __ Setffr();
+  __ Rdffr(p14.VnB());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(p14.VnB(), p15.VnB());
+  }
+}
+
+static void WrffrHelper(Test* config, unsigned active_lanes) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int inputs[kPRegMaxSize] = {0};
+  VIXL_ASSERT(active_lanes <= kPRegMaxSize);
+  for (unsigned i = 0; i < active_lanes; i++) {
+    // The rightmost (highest-indexed) array element maps to the lowest-numbered
+    // lane.
+    inputs[kPRegMaxSize - i - 1] = 1;
+  }
+
+  Initialise(&masm, p1.VnB(), inputs);
+  __ Wrffr(p1.VnB());
+  __ Rdffr(p2.VnB());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(p1.VnB(), p2.VnB());
+  }
+}
+
+TEST_SVE(sve_wrffr) {
+  int active_lanes_inputs[] = {0, 1, 7, 10, 32, 48, kPRegMaxSize};
+  for (size_t i = 0; i < ArrayLength(active_lanes_inputs); i++) {
+    WrffrHelper(config, active_lanes_inputs[i]);
+  }
+}
+
+template <size_t N>
+static void RdffrHelper(Test* config,
+                        size_t active_lanes,
+                        const int (&pg_inputs)[N]) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  VIXL_ASSERT(active_lanes <= kPRegMaxSize);
+
+  // The rightmost (highest-indexed) array element maps to the lowest-numbered
+  // lane.
+  int pd[kPRegMaxSize] = {0};
+  for (unsigned i = 0; i < active_lanes; i++) {
+    pd[kPRegMaxSize - i - 1] = 1;
+  }
+
+  int pg[kPRegMaxSize] = {0};
+  for (unsigned i = 0; i < N; i++) {
+    pg[kPRegMaxSize - i - 1] = pg_inputs[i];
+  }
+
+  int pd_expected[kPRegMaxSize] = {0};
+  for (unsigned i = 0; i < std::min(active_lanes, N); i++) {
+    int lane = kPRegMaxSize - i - 1;
+    pd_expected[lane] = pd[lane] & pg[lane];
+  }
+
+  Initialise(&masm, p0.VnB(), pg);
+  Initialise(&masm, p1.VnB(), pd);
+
+  // The unpredicated form of rdffr has been tested in `WrffrHelper`.
+  __ Wrffr(p1.VnB());
+  __ Rdffr(p14.VnB(), p0.Zeroing());
+  __ Rdffrs(p13.VnB(), p0.Zeroing());
+  __ Mrs(x8, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(pd_expected, p14.VnB());
+    ASSERT_EQUAL_SVE(pd_expected, p13.VnB());
+    StatusFlags nzcv_expected =
+        GetPredTestFlags(pd_expected, pg, core.GetSVELaneCount(kBRegSize));
+    ASSERT_EQUAL_64(nzcv_expected, x8);
+  }
+}
+
+TEST_SVE(sve_rdffr_rdffrs) {
+  // clang-format off
+  int active_lanes_inputs[] = {0, 1, 15, 26, 39, 47, kPRegMaxSize};
+  int pg_inputs_0[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int pg_inputs_1[] = {1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0};
+  int pg_inputs_2[] = {0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+  int pg_inputs_3[] = {0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1};
+  int pg_inputs_4[] = {1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  // clang-format on
+
+  for (size_t i = 0; i < ArrayLength(active_lanes_inputs); i++) {
+    RdffrHelper(config, active_lanes_inputs[i], pg_inputs_0);
+    RdffrHelper(config, active_lanes_inputs[i], pg_inputs_1);
+    RdffrHelper(config, active_lanes_inputs[i], pg_inputs_2);
+    RdffrHelper(config, active_lanes_inputs[i], pg_inputs_3);
+    RdffrHelper(config, active_lanes_inputs[i], pg_inputs_4);
+  }
+}
+
+typedef void (MacroAssembler::*BrkpFn)(const PRegisterWithLaneSize& pd,
+                                       const PRegisterZ& pg,
+                                       const PRegisterWithLaneSize& pn,
+                                       const PRegisterWithLaneSize& pm);
+
+template <typename Tg, typename Tn, typename Td>
+static void BrkpaBrkpbHelper(Test* config,
+                             BrkpFn macro,
+                             BrkpFn macro_set_flags,
+                             const Tg& pg_inputs,
+                             const Tn& pn_inputs,
+                             const Tn& pm_inputs,
+                             const Td& pd_expected) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  PRegister pg = p15;
+  PRegister pn = p14;
+  PRegister pm = p13;
+  Initialise(&masm, pg.VnB(), pg_inputs);
+  Initialise(&masm, pn.VnB(), pn_inputs);
+  Initialise(&masm, pm.VnB(), pm_inputs);
+
+  // Initialise NZCV to an impossible value, to check that we actually write it.
+  __ Mov(x10, NZCVFlag);
+  __ Msr(NZCV, x10);
+
+  (masm.*macro_set_flags)(p0.VnB(), pg.Zeroing(), pn.VnB(), pm.VnB());
+  __ Mrs(x0, NZCV);
+
+  (masm.*macro)(p1.VnB(), pg.Zeroing(), pn.VnB(), pm.VnB());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(pd_expected, p0.VnB());
+
+    // Check that the flags were properly set.
+    StatusFlags nzcv_expected =
+        GetPredTestFlags(pd_expected,
+                         pg_inputs,
+                         core.GetSVELaneCount(kBRegSize));
+    ASSERT_EQUAL_64(nzcv_expected, x0);
+    ASSERT_EQUAL_SVE(p0.VnB(), p1.VnB());
+  }
+}
+
+template <typename Tg, typename Tn, typename Td>
+static void BrkpaHelper(Test* config,
+                        const Tg& pg_inputs,
+                        const Tn& pn_inputs,
+                        const Tn& pm_inputs,
+                        const Td& pd_expected) {
+  BrkpaBrkpbHelper(config,
+                   &MacroAssembler::Brkpa,
+                   &MacroAssembler::Brkpas,
+                   pg_inputs,
+                   pn_inputs,
+                   pm_inputs,
+                   pd_expected);
+}
+
+template <typename Tg, typename Tn, typename Td>
+static void BrkpbHelper(Test* config,
+                        const Tg& pg_inputs,
+                        const Tn& pn_inputs,
+                        const Tn& pm_inputs,
+                        const Td& pd_expected) {
+  BrkpaBrkpbHelper(config,
+                   &MacroAssembler::Brkpb,
+                   &MacroAssembler::Brkpbs,
+                   pg_inputs,
+                   pn_inputs,
+                   pm_inputs,
+                   pd_expected);
+}
+
+TEST_SVE(sve_brkpb) {
+  // clang-format off
+  // The last active element of `pn` are `true` in all vector length configurations.
+  //                                | boundary of 128-bits VL.
+  //                                v
+  int pg_1[] =      {1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+  int pg_2[] =      {1, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+  int pg_3[] =      {1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1};
+
+  //                 | highest-numbered lane                lowest-numbered lane |
+  //                 v                                                           v
+  int pn_1[] =      {1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0};
+  int pn_2[] =      {1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0};
+  int pn_3[] =      {1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1};
+
+  int pm_1[] =      {1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0};
+  int pm_2[] =      {0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int pm_3[] =      {0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+
+  //                                                                    | first active
+  //                                                                    v
+  int exp_1_1_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0};
+  //                                            | first active
+  //                                            v
+  int exp_1_2_2[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+  //                                                                    | first active
+  //                                                                    v
+  int exp_1_3_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0};
+
+  BrkpbHelper(config, pg_1, pn_1, pm_1, exp_1_1_1);
+  BrkpbHelper(config, pg_1, pn_2, pm_2, exp_1_2_2);
+  BrkpbHelper(config, pg_1, pn_3, pm_3, exp_1_3_3);
+
+  //                                               | first active
+  //                                               v
+  int exp_2_1_2[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+  //                                            | first active
+  //                                            v
+  int exp_2_2_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+  //                                                                 | first active
+  //                                                                 v
+  int exp_2_3_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1};
+  BrkpbHelper(config, pg_2, pn_1, pm_2, exp_2_1_2);
+  BrkpbHelper(config, pg_2, pn_2, pm_3, exp_2_2_3);
+  BrkpbHelper(config, pg_2, pn_3, pm_1, exp_2_3_1);
+
+  //                                                                    | first active
+  //                                                                    v
+  int exp_3_1_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1};
+  //                                                                    | first active
+  //                                                                    v
+  int exp_3_2_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1};
+  //                                      | first active
+  //                                      v
+  int exp_3_3_2[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1};
+  BrkpbHelper(config, pg_3, pn_1, pm_3, exp_3_1_3);
+  BrkpbHelper(config, pg_3, pn_2, pm_1, exp_3_2_1);
+  BrkpbHelper(config, pg_3, pn_3, pm_2, exp_3_3_2);
+
+  // The last active element of `pn` are `false` in all vector length configurations.
+  //                       | last active lane when VL > 128 bits.
+  //                       v
+  //                                   | last active lane when VL == 128 bits.
+  //                                   v
+  int pg_4[] =      {0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1};
+  int exp_4_x_x[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  BrkpbHelper(config, pg_4, pn_1, pm_1, exp_4_x_x);
+  BrkpbHelper(config, pg_4, pn_2, pm_2, exp_4_x_x);
+  BrkpbHelper(config, pg_4, pn_3, pm_3, exp_4_x_x);
+  // clang-format on
+}
+
+TEST_SVE(sve_brkpa) {
+  // clang-format off
+  // The last active element of `pn` are `true` in all vector length configurations.
+  //                                | boundary of 128-bits VL.
+  //                                v
+  int pg_1[] =      {1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+  int pg_2[] =      {1, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+  int pg_3[] =      {1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1};
+
+  //                 | highest-numbered lane                lowest-numbered lane |
+  //                 v                                                           v
+  int pn_1[] =      {1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0};
+  int pn_2[] =      {1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0};
+  int pn_3[] =      {1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1};
+
+  int pm_1[] =      {1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0};
+  int pm_2[] =      {0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int pm_3[] =      {0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+
+  //                                                                    | first active
+  //                                                                    v
+  int exp_1_1_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0};
+  //                                            | first active
+  //                                            v
+  int exp_1_2_2[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+  //                                                                    | first active
+  //                                                                    v
+  int exp_1_3_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0};
+
+  BrkpaHelper(config, pg_1, pn_1, pm_1, exp_1_1_1);
+  BrkpaHelper(config, pg_1, pn_2, pm_2, exp_1_2_2);
+  BrkpaHelper(config, pg_1, pn_3, pm_3, exp_1_3_3);
+
+  //                                               | first active
+  //                                               v
+  int exp_2_1_2[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+  //                                            | first active
+  //                                            v
+  int exp_2_2_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+  //                                                                 | first active
+  //                                                                 v
+  int exp_2_3_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1};
+  BrkpaHelper(config, pg_2, pn_1, pm_2, exp_2_1_2);
+  BrkpaHelper(config, pg_2, pn_2, pm_3, exp_2_2_3);
+  BrkpaHelper(config, pg_2, pn_3, pm_1, exp_2_3_1);
+
+  //                                                                    | first active
+  //                                                                    v
+  int exp_3_1_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1};
+  //                                                                    | first active
+  //                                                                    v
+  int exp_3_2_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1};
+  //                                      | first active
+  //                                      v
+  int exp_3_3_2[] = {0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1};
+  BrkpaHelper(config, pg_3, pn_1, pm_3, exp_3_1_3);
+  BrkpaHelper(config, pg_3, pn_2, pm_1, exp_3_2_1);
+  BrkpaHelper(config, pg_3, pn_3, pm_2, exp_3_3_2);
+
+  // The last active element of `pn` are `false` in all vector length configurations.
+  //                       | last active lane when VL > 128 bits.
+  //                       v
+  //                                   | last active lane when VL == 128 bits.
+  //                                   v
+  int pg_4[] =      {0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1};
+  int exp_4_x_x[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  BrkpaHelper(config, pg_4, pn_1, pm_1, exp_4_x_x);
+  BrkpaHelper(config, pg_4, pn_2, pm_2, exp_4_x_x);
+  BrkpaHelper(config, pg_4, pn_3, pm_3, exp_4_x_x);
+  // clang-format on
+}
+
+TEST_SVE(sve_rbit) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t inputs[] = {0xaaaaaaaa55555555, 0xaaaa5555aa55aa55};
+  InsrHelper(&masm, z0.VnD(), inputs);
+
+  __ Ptrue(p1.VnB());
+  int pred[] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 1, 0, 1};
+  Initialise(&masm, p2.VnB(), pred);
+
+  __ Rbit(z0.VnB(), p1.Merging(), z0.VnB());
+  __ Rbit(z0.VnB(), p1.Merging(), z0.VnB());
+
+  __ Rbit(z1.VnB(), p1.Merging(), z0.VnB());
+  __ Rbit(z2.VnH(), p1.Merging(), z0.VnH());
+  __ Rbit(z3.VnS(), p1.Merging(), z0.VnS());
+  __ Rbit(z4.VnD(), p1.Merging(), z0.VnD());
+
+  __ Dup(z5.VnB(), 0x42);
+  __ Rbit(z5.VnB(), p2.Merging(), z0.VnB());
+  __ Dup(z6.VnB(), 0x42);
+  __ Rbit(z6.VnS(), p2.Merging(), z0.VnS());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(inputs, z0.VnD());
+
+    uint64_t expected_z1[] = {0x55555555aaaaaaaa, 0x5555aaaa55aa55aa};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+    uint64_t expected_z2[] = {0x55555555aaaaaaaa, 0x5555aaaaaa55aa55};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0x55555555aaaaaaaa, 0xaaaa5555aa55aa55};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xaaaaaaaa55555555, 0xaa55aa55aaaa5555};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x4255425542aa42aa, 0x4255424242aa42aa};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x55555555aaaaaaaa, 0x42424242aa55aa55};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+  }
+}
+
+TEST_SVE(sve_rev_bhw) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t inputs[] = {0xaaaaaaaa55555555, 0xaaaa5555aa55aa55};
+  InsrHelper(&masm, z0.VnD(), inputs);
+
+  __ Ptrue(p1.VnB());
+  int pred[] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 1, 0, 1};
+  Initialise(&masm, p2.VnB(), pred);
+
+  __ Revb(z1.VnH(), p1.Merging(), z0.VnH());
+  __ Revb(z2.VnS(), p1.Merging(), z0.VnS());
+  __ Revb(z3.VnD(), p1.Merging(), z0.VnD());
+  __ Revh(z4.VnS(), p1.Merging(), z0.VnS());
+  __ Revh(z5.VnD(), p1.Merging(), z0.VnD());
+  __ Revw(z6.VnD(), p1.Merging(), z0.VnD());
+
+  __ Dup(z7.VnB(), 0x42);
+  __ Revb(z7.VnH(), p2.Merging(), z0.VnH());
+  __ Dup(z8.VnB(), 0x42);
+  __ Revh(z8.VnS(), p2.Merging(), z0.VnS());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t expected_z1[] = {0xaaaaaaaa55555555, 0xaaaa555555aa55aa};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+    uint64_t expected_z2[] = {0xaaaaaaaa55555555, 0x5555aaaa55aa55aa};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0x55555555aaaaaaaa, 0x55aa55aa5555aaaa};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xaaaaaaaa55555555, 0x5555aaaaaa55aa55};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x55555555aaaaaaaa, 0xaa55aa555555aaaa};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x55555555aaaaaaaa, 0xaa55aa55aaaa5555};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0xaaaaaaaa55555555, 0xaaaa424255aa55aa};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0xaaaaaaaa55555555, 0x42424242aa55aa55};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+  }
+}
+
+TEST_SVE(sve_ftssel) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in[] = {0x1111777766665555, 0xaaaabbbbccccdddd};
+  uint64_t q[] = {0x0001000300000002, 0x0001000200000003};
+  InsrHelper(&masm, z0.VnD(), in);
+  InsrHelper(&masm, z1.VnD(), q);
+
+  __ Ftssel(z2.VnH(), z0.VnH(), z1.VnH());
+  __ Ftssel(z3.VnS(), z0.VnS(), z1.VnS());
+  __ Ftssel(z4.VnD(), z0.VnD(), z1.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t expected_z2[] = {0x3c00bc006666d555, 0x3c003bbbccccbc00};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0xbf800000e6665555, 0x2aaabbbbbf800000};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0x9111777766665555, 0xbff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+  }
+}
+
+TEST_SVE(sve_fexpa) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in0[] = {0x3ff0000000000000, 0x3ff0000000011001};
+  uint64_t in1[] = {0x3ff000000002200f, 0xbff000000003301f};
+  uint64_t in2[] = {0xbff000000004403f, 0x3ff0000000055040};
+  uint64_t in3[] = {0x3f800000bf800001, 0x3f80000f3f80001f};
+  uint64_t in4[] = {0x3f80002f3f82203f, 0xbf8000403f833041};
+  uint64_t in5[] = {0x3c003c01bc00bc07, 0x3c08bc0f3c1fbc20};
+  InsrHelper(&masm, z0.VnD(), in0);
+  InsrHelper(&masm, z1.VnD(), in1);
+  InsrHelper(&masm, z2.VnD(), in2);
+  InsrHelper(&masm, z3.VnD(), in3);
+  InsrHelper(&masm, z4.VnD(), in4);
+  InsrHelper(&masm, z5.VnD(), in5);
+
+  __ Fexpa(z6.VnD(), z0.VnD());
+  __ Fexpa(z7.VnD(), z1.VnD());
+  __ Fexpa(z8.VnD(), z2.VnD());
+  __ Fexpa(z9.VnS(), z3.VnS());
+  __ Fexpa(z10.VnS(), z4.VnS());
+  __ Fexpa(z11.VnH(), z5.VnH());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z6[] = {0x0000000000000000, 0x44002c9a3e778061};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0x0802d285a6e4030b, 0x4c06623882552225};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0x100fa7c1819e90d8, 0x5410000000000000};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0x00000000000164d2, 0x0016942d003311c4};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x0054f35b407d3e0c, 0x00800000608164d2};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+    uint64_t expected_z11[] = {0x00000016000000a8, 0x00c2018903d40400};
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+  }
+}
+
+TEST_SVE(sve_rev_p) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  Initialise(&masm,
+             p0.VnB(),
+             0xabcdabcdabcdabcd,
+             0xabcdabcdabcdabcd,
+             0xabcdabcdabcdabcd,
+             0xabcdabcdabcdabcd);
+
+  __ Rev(p1.VnB(), p0.VnB());
+  __ Rev(p2.VnH(), p0.VnH());
+  __ Rev(p3.VnS(), p0.VnS());
+  __ Rev(p4.VnD(), p0.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int p1_expected[] = {1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, 0, 1};
+    ASSERT_EQUAL_SVE(p1_expected, p1.VnB());
+    int p2_expected[] = {0, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+    int p3_expected[] = {1, 1, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+    int p4_expected[] = {1, 1, 0, 0, 1, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 1};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnB());
+  }
+}
+
+TEST_SVE(sve_trn_p_bh) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  Initialise(&masm, p0.VnB(), 0xa5a55a5a);
+  __ Pfalse(p1.VnB());
+
+  __ Trn1(p2.VnB(), p0.VnB(), p0.VnB());
+  __ Trn2(p3.VnB(), p0.VnB(), p0.VnB());
+  __ Trn1(p4.VnB(), p1.VnB(), p0.VnB());
+  __ Trn2(p5.VnB(), p1.VnB(), p0.VnB());
+  __ Trn1(p6.VnB(), p0.VnB(), p1.VnB());
+  __ Trn2(p7.VnB(), p0.VnB(), p1.VnB());
+
+  __ Trn1(p8.VnH(), p0.VnH(), p0.VnH());
+  __ Trn2(p9.VnH(), p0.VnH(), p0.VnH());
+  __ Trn1(p10.VnH(), p1.VnH(), p0.VnH());
+  __ Trn2(p11.VnH(), p1.VnH(), p0.VnH());
+  __ Trn1(p12.VnH(), p0.VnH(), p1.VnH());
+  __ Trn2(p13.VnH(), p0.VnH(), p1.VnH());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    int p2_expected[] = {1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0};
+    int p3_expected[] = {0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+
+    int p4_expected[] = {1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0};
+    int p5_expected[] = {0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnB());
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnB());
+
+    int p6_expected[] = {0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0};
+    int p7_expected[] = {0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnB());
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnB());
+
+    int p8_expected[] = {0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+    int p9_expected[] = {0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnB());
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnB());
+
+    int p10_expected[] = {0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+    int p11_expected[] = {0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0};
+    ASSERT_EQUAL_SVE(p10_expected, p10.VnB());
+    ASSERT_EQUAL_SVE(p11_expected, p11.VnB());
+
+    int p12_expected[] = {0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0};
+    int p13_expected[] = {0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p12_expected, p12.VnB());
+    ASSERT_EQUAL_SVE(p13_expected, p13.VnB());
+  }
+}
+
+TEST_SVE(sve_trn_p_sd) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  Initialise(&masm, p0.VnB(), 0x55a55aaa);
+  __ Pfalse(p1.VnB());
+
+  __ Trn1(p2.VnS(), p0.VnS(), p0.VnS());
+  __ Trn2(p3.VnS(), p0.VnS(), p0.VnS());
+  __ Trn1(p4.VnS(), p1.VnS(), p0.VnS());
+  __ Trn2(p5.VnS(), p1.VnS(), p0.VnS());
+  __ Trn1(p6.VnS(), p0.VnS(), p1.VnS());
+  __ Trn2(p7.VnS(), p0.VnS(), p1.VnS());
+
+  __ Trn1(p8.VnD(), p0.VnD(), p0.VnD());
+  __ Trn2(p9.VnD(), p0.VnD(), p0.VnD());
+  __ Trn1(p10.VnD(), p1.VnD(), p0.VnD());
+  __ Trn2(p11.VnD(), p1.VnD(), p0.VnD());
+  __ Trn1(p12.VnD(), p0.VnD(), p1.VnD());
+  __ Trn2(p13.VnD(), p0.VnD(), p1.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    int p2_expected[] = {1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0};
+    int p3_expected[] = {0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+
+    int p4_expected[] = {1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0};
+    int p5_expected[] = {0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnB());
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnB());
+
+    int p6_expected[] = {0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 1, 0};
+    int p7_expected[] = {0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnB());
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnB());
+
+    int p8_expected[] = {1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0};
+    int p9_expected[] = {0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnB());
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnB());
+
+    int p10_expected[] = {1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+    int p11_expected[] = {0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+    ASSERT_EQUAL_SVE(p10_expected, p10.VnB());
+    ASSERT_EQUAL_SVE(p11_expected, p11.VnB());
+
+    int p12_expected[] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0};
+    int p13_expected[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p12_expected, p12.VnB());
+    ASSERT_EQUAL_SVE(p13_expected, p13.VnB());
+  }
+}
+
+TEST_SVE(sve_zip_p_bh) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  Initialise(&masm,
+             p0.VnB(),
+             0x5a5a5a5a5a5a5a5a,
+             0x5a5a5a5a5a5a5a5a,
+             0x5a5a5a5a5a5a5a5a,
+             0x5a5a5a5a5a5a5a5a);
+  __ Pfalse(p1.VnB());
+
+  __ Zip1(p2.VnB(), p0.VnB(), p0.VnB());
+  __ Zip2(p3.VnB(), p0.VnB(), p0.VnB());
+  __ Zip1(p4.VnB(), p1.VnB(), p0.VnB());
+  __ Zip2(p5.VnB(), p1.VnB(), p0.VnB());
+  __ Zip1(p6.VnB(), p0.VnB(), p1.VnB());
+  __ Zip2(p7.VnB(), p0.VnB(), p1.VnB());
+
+  __ Zip1(p8.VnH(), p0.VnH(), p0.VnH());
+  __ Zip2(p9.VnH(), p0.VnH(), p0.VnH());
+  __ Zip1(p10.VnH(), p1.VnH(), p0.VnH());
+  __ Zip2(p11.VnH(), p1.VnH(), p0.VnH());
+  __ Zip1(p12.VnH(), p0.VnH(), p1.VnH());
+  __ Zip2(p13.VnH(), p0.VnH(), p1.VnH());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    int p2_expected[] = {0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0};
+    int p3_expected[] = {0, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+
+    int p4_expected[] = {0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+    int p5_expected[] = {0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnB());
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnB());
+
+    int p6_expected[] = {0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0};
+    int p7_expected[] = {0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnB());
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnB());
+
+    int p8_expected[] = {0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0};
+    int p9_expected[] = {0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnB());
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnB());
+
+    int p10_expected[] = {0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+    int p11_expected[] = {0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0};
+    ASSERT_EQUAL_SVE(p10_expected, p10.VnB());
+    ASSERT_EQUAL_SVE(p11_expected, p11.VnB());
+
+    int p12_expected[] = {0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0};
+    int p13_expected[] = {0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p12_expected, p12.VnB());
+    ASSERT_EQUAL_SVE(p13_expected, p13.VnB());
+  }
+}
+
+TEST_SVE(sve_zip_p_sd) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  Initialise(&masm,
+             p0.VnB(),
+             0x5a5a5a5a5a5a5a5a,
+             0x5a5a5a5a5a5a5a5a,
+             0x5a5a5a5a5a5a5a5a,
+             0x5a5a5a5a5a5a5a5a);
+  __ Pfalse(p1.VnB());
+
+  __ Zip1(p2.VnS(), p0.VnS(), p0.VnS());
+  __ Zip2(p3.VnS(), p0.VnS(), p0.VnS());
+  __ Zip1(p4.VnS(), p1.VnS(), p0.VnS());
+  __ Zip2(p5.VnS(), p1.VnS(), p0.VnS());
+  __ Zip1(p6.VnS(), p0.VnS(), p1.VnS());
+  __ Zip2(p7.VnS(), p0.VnS(), p1.VnS());
+
+  __ Zip1(p8.VnD(), p0.VnD(), p0.VnD());
+  __ Zip2(p9.VnD(), p0.VnD(), p0.VnD());
+  __ Zip1(p10.VnD(), p1.VnD(), p0.VnD());
+  __ Zip2(p11.VnD(), p1.VnD(), p0.VnD());
+  __ Zip1(p12.VnD(), p0.VnD(), p1.VnD());
+  __ Zip2(p13.VnD(), p0.VnD(), p1.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    int p2_expected[] = {0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0};
+    int p3_expected[] = {0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnB());
+    ASSERT_EQUAL_SVE(p3_expected, p3.VnB());
+
+    int p4_expected[] = {0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0};
+    int p5_expected[] = {0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0};
+    ASSERT_EQUAL_SVE(p4_expected, p4.VnB());
+    ASSERT_EQUAL_SVE(p5_expected, p5.VnB());
+
+    int p6_expected[] = {0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0};
+    int p7_expected[] = {0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p6_expected, p6.VnB());
+    ASSERT_EQUAL_SVE(p7_expected, p7.VnB());
+
+    int p8_expected[] = {0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+    int p9_expected[] = {0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p8_expected, p8.VnB());
+    ASSERT_EQUAL_SVE(p9_expected, p9.VnB());
+
+    int p10_expected[] = {0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+    int p11_expected[] = {0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+    ASSERT_EQUAL_SVE(p10_expected, p10.VnB());
+    ASSERT_EQUAL_SVE(p11_expected, p11.VnB());
+
+    int p12_expected[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+    int p13_expected[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+    ASSERT_EQUAL_SVE(p12_expected, p12.VnB());
+    ASSERT_EQUAL_SVE(p13_expected, p13.VnB());
+  }
+}
+
+TEST_SVE(sve_uzp_p) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  Initialise(&masm,
+             p0.VnB(),
+             0xf0f0ff00ffff0000,
+             0x4242424242424242,
+             0x5a5a5a5a5a5a5a5a,
+             0x0123456789abcdef);
+  __ Rev(p1.VnB(), p0.VnB());
+
+  __ Zip1(p2.VnB(), p0.VnB(), p1.VnB());
+  __ Zip2(p3.VnB(), p0.VnB(), p1.VnB());
+  __ Uzp1(p4.VnB(), p2.VnB(), p3.VnB());
+  __ Uzp2(p5.VnB(), p2.VnB(), p3.VnB());
+
+  __ Zip1(p2.VnH(), p0.VnH(), p1.VnH());
+  __ Zip2(p3.VnH(), p0.VnH(), p1.VnH());
+  __ Uzp1(p6.VnH(), p2.VnH(), p3.VnH());
+  __ Uzp2(p7.VnH(), p2.VnH(), p3.VnH());
+
+  __ Zip1(p2.VnS(), p0.VnS(), p1.VnS());
+  __ Zip2(p3.VnS(), p0.VnS(), p1.VnS());
+  __ Uzp1(p8.VnS(), p2.VnS(), p3.VnS());
+  __ Uzp2(p9.VnS(), p2.VnS(), p3.VnS());
+
+  __ Zip1(p2.VnD(), p0.VnD(), p1.VnD());
+  __ Zip2(p3.VnD(), p0.VnD(), p1.VnD());
+  __ Uzp1(p10.VnD(), p2.VnD(), p3.VnD());
+  __ Uzp2(p11.VnD(), p2.VnD(), p3.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(p0, p4);
+    ASSERT_EQUAL_SVE(p1, p5);
+    ASSERT_EQUAL_SVE(p0, p6);
+    ASSERT_EQUAL_SVE(p1, p7);
+    ASSERT_EQUAL_SVE(p0, p8);
+    ASSERT_EQUAL_SVE(p1, p9);
+    ASSERT_EQUAL_SVE(p0, p10);
+    ASSERT_EQUAL_SVE(p1, p11);
+  }
+}
+
+TEST_SVE(sve_punpk) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  auto get_64_bits_at = [](int byte_index) -> uint64_t {
+    // Each 8-bit chunk has the value 0x50 + the byte index of the chunk.
+    return 0x5756555453525150 + (0x0101010101010101 * byte_index);
+  };
+
+  Initialise(&masm,
+             p0.VnB(),
+             get_64_bits_at(24),
+             get_64_bits_at(16),
+             get_64_bits_at(8),
+             get_64_bits_at(0));
+  __ Punpklo(p1.VnH(), p0.VnB());
+  __ Punpkhi(p2.VnH(), p0.VnB());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    int pl = config->sve_vl_in_bits() / kZRegBitsPerPRegBit;
+    // For simplicity, just test the bottom 64 H-sized lanes.
+    uint64_t p1_h_bits = get_64_bits_at(0);
+    uint64_t p2_h_bits = get_64_bits_at(pl / (2 * 8));
+    int p1_expected[64];
+    int p2_expected[64];
+    for (size_t i = 0; i < 64; i++) {
+      p1_expected[63 - i] = (p1_h_bits >> i) & 1;
+      p2_expected[63 - i] = (p2_h_bits >> i) & 1;
+    }
+    // Testing `VnH` ensures that odd-numbered B lanes are zero.
+    ASSERT_EQUAL_SVE(p1_expected, p1.VnH());
+    ASSERT_EQUAL_SVE(p2_expected, p2.VnH());
+  }
+}
+
+typedef void (MacroAssembler::*BrkFn)(const PRegisterWithLaneSize& pd,
+                                      const PRegister& pg,
+                                      const PRegisterWithLaneSize& pn);
+
+typedef void (MacroAssembler::*BrksFn)(const PRegisterWithLaneSize& pd,
+                                       const PRegisterZ& pg,
+                                       const PRegisterWithLaneSize& pn);
+
+template <typename T, size_t N>
+static void BrkaBrkbHelper(Test* config,
+                           BrkFn macro,
+                           BrksFn macro_set_flags,
+                           const T (&pd_inputs)[N],
+                           const T (&pg_inputs)[N],
+                           const T (&pn_inputs)[N],
+                           const T (&pd_z_expected)[N]) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  PRegister pg = p10;
+  PRegister pn = p9;
+  PRegister pd_z = p0;
+  PRegister pd_z_s = p1;
+  PRegister pd_m = p2;
+  Initialise(&masm, pg.VnB(), pg_inputs);
+  Initialise(&masm, pn.VnB(), pn_inputs);
+  Initialise(&masm, pd_m.VnB(), pd_inputs);
+
+  // Initialise NZCV to an impossible value, to check that we actually write it.
+  __ Mov(x10, NZCVFlag);
+  __ Msr(NZCV, x10);
+
+  (masm.*macro)(pd_z.VnB(), pg.Zeroing(), pn.VnB());
+  (masm.*macro_set_flags)(pd_z_s.VnB(), pg.Zeroing(), pn.VnB());
+  __ Mrs(x0, NZCV);
+
+  (masm.*macro)(pd_m.VnB(), pg.Merging(), pn.VnB());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(pd_z_expected, pd_z.VnB());
+
+    // Check that the flags were properly set.
+    StatusFlags nzcv_expected =
+        GetPredTestFlags(pd_z_expected,
+                         pg_inputs,
+                         core.GetSVELaneCount(kBRegSize));
+    ASSERT_EQUAL_64(nzcv_expected, x0);
+    ASSERT_EQUAL_SVE(pd_z.VnB(), pd_z_s.VnB());
+
+    T pd_m_expected[N];
+    // Set expected `pd` result on merging predication.
+    for (size_t i = 0; i < N; i++) {
+      pd_m_expected[i] = pg_inputs[i] ? pd_z_expected[i] : pd_inputs[i];
+    }
+    ASSERT_EQUAL_SVE(pd_m_expected, pd_m.VnB());
+  }
+}
+
+template <typename T>
+static void BrkaHelper(Test* config,
+                       const T& pd_inputs,
+                       const T& pg_inputs,
+                       const T& pn_inputs,
+                       const T& pd_expected) {
+  BrkaBrkbHelper(config,
+                 &MacroAssembler::Brka,
+                 &MacroAssembler::Brkas,
+                 pd_inputs,
+                 pg_inputs,
+                 pn_inputs,
+                 pd_expected);
+}
+
+TEST_SVE(sve_brka) {
+  // clang-format off
+  //                              | boundary of 128-bits VL.
+  //                              v
+  int pd[] =      {1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  //               | highest-numbered lane                lowest-numbered lane |
+  //               v                                                           v
+  int pg_1[] =    {1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+  int pg_2[] =    {1, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+
+  int pn_1[] =    {1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0};
+  int pn_2[] =    {1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int pn_3[] =    {1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 1};
+
+  //                                                                  | first break
+  //                                                                  v
+  int exp_1_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0};
+  //                              | first break
+  //                              v
+  int exp_1_2[] = {0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+  //                                                      | first break
+  //                                                      v
+  int exp_1_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+
+  BrkaHelper(config, pd, pg_1, pn_1, exp_1_1);
+  BrkaHelper(config, pd, pg_1, pn_2, exp_1_2);
+  BrkaHelper(config, pd, pg_1, pn_3, exp_1_3);
+
+  //                                                               | first break
+  //                                                               v
+  int exp_2_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1};
+  //                                       | first break
+  //                                       v
+  int exp_2_2[] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+  //                                                                           | first break
+  //                                                                           v
+  int exp_2_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
+  BrkaHelper(config, pd, pg_2, pn_1, exp_2_1);
+  BrkaHelper(config, pd, pg_2, pn_2, exp_2_2);
+  BrkaHelper(config, pd, pg_2, pn_3, exp_2_3);
+
+  // The all-inactive zeroing predicate sets destination predicate all-false.
+  int pg_3[] =    {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp_3_x[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  BrkaHelper(config, pd, pg_3, pn_1, exp_3_x);
+  BrkaHelper(config, pd, pg_3, pn_2, exp_3_x);
+  BrkaHelper(config, pd, pg_3, pn_3, exp_3_x);
+  // clang-format on
+}
+
+template <typename T>
+static void BrkbHelper(Test* config,
+                       const T& pd_inputs,
+                       const T& pg_inputs,
+                       const T& pn_inputs,
+                       const T& pd_expected) {
+  BrkaBrkbHelper(config,
+                 &MacroAssembler::Brkb,
+                 &MacroAssembler::Brkbs,
+                 pd_inputs,
+                 pg_inputs,
+                 pn_inputs,
+                 pd_expected);
+}
+
+TEST_SVE(sve_brkb) {
+  // clang-format off
+  //                              | boundary of 128-bits VL.
+  //                              v
+  int pd[] =      {1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  //               | highest-numbered lane                lowest-numbered lane |
+  //               v                                                           v
+  int pg_1[] =    {1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+  int pg_2[] =    {1, 0, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+
+  int pn_1[] =    {1, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0};
+  int pn_2[] =    {1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int pn_3[] =    {1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 1};
+
+  //                                                                  | first break
+  //                                                                  v
+  int exp_1_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0};
+  //                              | first break
+  //                              v
+  int exp_1_2[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+  //                                                      | first break
+  //                                                      v
+  int exp_1_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0};
+
+  BrkbHelper(config, pd, pg_1, pn_1, exp_1_1);
+  BrkbHelper(config, pd, pg_1, pn_2, exp_1_2);
+  BrkbHelper(config, pd, pg_1, pn_3, exp_1_3);
+
+  //                                                               | first break
+  //                                                               v
+  int exp_2_1[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1};
+  //                                       | first break
+  //                                       v
+  int exp_2_2[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 0, 0, 1, 1};
+  //                                                                           | first break
+  //                                                                           v
+  int exp_2_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  BrkbHelper(config, pd, pg_2, pn_1, exp_2_1);
+  BrkbHelper(config, pd, pg_2, pn_2, exp_2_2);
+  BrkbHelper(config, pd, pg_2, pn_3, exp_2_3);
+
+  // The all-inactive zeroing predicate sets destination predicate all-false.
+  int pg_3[] =    {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  int exp_3_x[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+  BrkbHelper(config, pd, pg_3, pn_1, exp_3_x);
+  BrkbHelper(config, pd, pg_3, pn_2, exp_3_x);
+  BrkbHelper(config, pd, pg_3, pn_3, exp_3_x);
+  // clang-format on
+}
+
+typedef void (MacroAssembler::*BrknFn)(const PRegisterWithLaneSize& pd,
+                                       const PRegisterZ& pg,
+                                       const PRegisterWithLaneSize& pn,
+                                       const PRegisterWithLaneSize& pm);
+
+typedef void (MacroAssembler::*BrknsFn)(const PRegisterWithLaneSize& pd,
+                                        const PRegisterZ& pg,
+                                        const PRegisterWithLaneSize& pn,
+                                        const PRegisterWithLaneSize& pm);
+
+enum BrknDstPredicateState { kAllFalse, kUnchanged };
+
+template <typename T, size_t N>
+static void BrknHelper(Test* config,
+                       const T (&pd_inputs)[N],
+                       const T (&pg_inputs)[N],
+                       const T (&pn_inputs)[N],
+                       const T (&pm_inputs)[N],
+                       BrknDstPredicateState expected_pd_state) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  PRegister pg = p10;
+  PRegister pn = p9;
+  PRegister pm = p8;
+  PRegister pdm = p0;
+  PRegister pd = p1;
+  PRegister pd_s = p2;
+  Initialise(&masm, pg.VnB(), pg_inputs);
+  Initialise(&masm, pn.VnB(), pn_inputs);
+  Initialise(&masm, pm.VnB(), pm_inputs);
+  Initialise(&masm, pdm.VnB(), pm_inputs);
+  Initialise(&masm, pd.VnB(), pd_inputs);
+  Initialise(&masm, pd_s.VnB(), pd_inputs);
+
+  // Initialise NZCV to an impossible value, to check that we actually write it.
+  __ Mov(x10, NZCVFlag);
+  __ Msr(NZCV, x10);
+
+  __ Brkn(pdm.VnB(), pg.Zeroing(), pn.VnB(), pdm.VnB());
+  // !pd.Aliases(pm).
+  __ Brkn(pd.VnB(), pg.Zeroing(), pn.VnB(), pm.VnB());
+  __ Brkns(pd_s.VnB(), pg.Zeroing(), pn.VnB(), pm.VnB());
+  __ Mrs(x0, NZCV);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    T all_false[N] = {0};
+    if (expected_pd_state == kAllFalse) {
+      ASSERT_EQUAL_SVE(all_false, pd.VnB());
+    } else {
+      ASSERT_EQUAL_SVE(pm_inputs, pd.VnB());
+    }
+    ASSERT_EQUAL_SVE(pm_inputs, pm.VnB());
+
+    T all_true[N];
+    for (size_t i = 0; i < ArrayLength(all_true); i++) {
+      all_true[i] = 1;
+    }
+
+    // Check that the flags were properly set.
+    StatusFlags nzcv_expected =
+        GetPredTestFlags((expected_pd_state == kAllFalse) ? all_false
+                                                          : pm_inputs,
+                         all_true,
+                         core.GetSVELaneCount(kBRegSize));
+    ASSERT_EQUAL_64(nzcv_expected, x0);
+    ASSERT_EQUAL_SVE(pd.VnB(), pdm.VnB());
+    ASSERT_EQUAL_SVE(pd.VnB(), pd_s.VnB());
+  }
+}
+
+TEST_SVE(sve_brkn) {
+  int pd[] = {1, 0, 0, 1, 0, 1, 1, 0, 1, 0};
+  int pm[] = {0, 1, 1, 1, 1, 0, 0, 1, 0, 1};
+
+  int pg_1[] = {1, 1, 0, 0, 1, 0, 1, 1, 0, 0};
+  int pg_2[] = {0, 0, 0, 1, 1, 1, 0, 0, 1, 1};
+  int pg_3[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+  int pn_1[] = {1, 0, 0, 0, 0, 1, 1, 0, 0, 0};
+  int pn_2[] = {0, 1, 0, 1, 0, 0, 0, 0, 0, 0};
+  int pn_3[] = {0, 0, 0, 0, 1, 1, 0, 0, 1, 1};
+
+  BrknHelper(config, pd, pg_1, pn_1, pm, kUnchanged);
+  BrknHelper(config, pd, pg_1, pn_2, pm, kAllFalse);
+  BrknHelper(config, pd, pg_1, pn_3, pm, kAllFalse);
+
+  BrknHelper(config, pd, pg_2, pn_1, pm, kAllFalse);
+  BrknHelper(config, pd, pg_2, pn_2, pm, kUnchanged);
+  BrknHelper(config, pd, pg_2, pn_3, pm, kAllFalse);
+
+  BrknHelper(config, pd, pg_3, pn_1, pm, kAllFalse);
+  BrknHelper(config, pd, pg_3, pn_2, pm, kAllFalse);
+  BrknHelper(config, pd, pg_3, pn_3, pm, kAllFalse);
+}
+
+TEST_SVE(sve_trn) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in0[] = {0xffeeddccbbaa9988, 0x7766554433221100};
+  uint64_t in1[] = {0xaa55aa55aa55aa55, 0x55aa55aa55aa55aa};
+  InsrHelper(&masm, z0.VnD(), in0);
+  InsrHelper(&masm, z1.VnD(), in1);
+
+  __ Trn1(z2.VnB(), z0.VnB(), z1.VnB());
+  __ Trn2(z3.VnB(), z0.VnB(), z1.VnB());
+  __ Trn1(z4.VnH(), z0.VnH(), z1.VnH());
+  __ Trn2(z5.VnH(), z0.VnH(), z1.VnH());
+  __ Trn1(z6.VnS(), z0.VnS(), z1.VnS());
+  __ Trn2(z7.VnS(), z0.VnS(), z1.VnS());
+  __ Trn1(z8.VnD(), z0.VnD(), z1.VnD());
+  __ Trn2(z9.VnD(), z0.VnD(), z1.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z2[] = {0x55ee55cc55aa5588, 0xaa66aa44aa22aa00};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0xaaffaaddaabbaa99, 0x5577555555335511};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xaa55ddccaa559988, 0x55aa554455aa1100};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0xaa55ffeeaa55bbaa, 0x55aa776655aa3322};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0xaa55aa55bbaa9988, 0x55aa55aa33221100};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0xaa55aa55ffeeddcc, 0x55aa55aa77665544};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0x55aa55aa55aa55aa, 0x7766554433221100};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0xaa55aa55aa55aa55, 0xffeeddccbbaa9988};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+  }
+}
+
+TEST_SVE(sve_zip_uzp) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Dup(z0.VnD(), 0xffeeddccbbaa9988);
+  __ Insr(z0.VnD(), 0x7766554433221100);
+  __ Dup(z1.VnD(), 0xaa55aa55aa55aa55);
+  __ Insr(z1.VnD(), 0x55aa55aa55aa55aa);
+
+  __ Zip1(z2.VnB(), z0.VnB(), z1.VnB());
+  __ Zip2(z3.VnB(), z0.VnB(), z1.VnB());
+  __ Zip1(z4.VnH(), z0.VnH(), z1.VnH());
+  __ Zip2(z5.VnH(), z0.VnH(), z1.VnH());
+  __ Zip1(z6.VnS(), z0.VnS(), z1.VnS());
+  __ Zip2(z7.VnS(), z0.VnS(), z1.VnS());
+  __ Zip1(z8.VnD(), z0.VnD(), z1.VnD());
+  __ Zip2(z9.VnD(), z0.VnD(), z1.VnD());
+
+  __ Uzp1(z10.VnB(), z2.VnB(), z3.VnB());
+  __ Uzp2(z11.VnB(), z2.VnB(), z3.VnB());
+  __ Uzp1(z12.VnH(), z4.VnH(), z5.VnH());
+  __ Uzp2(z13.VnH(), z4.VnH(), z5.VnH());
+  __ Uzp1(z14.VnS(), z6.VnS(), z7.VnS());
+  __ Uzp2(z15.VnS(), z6.VnS(), z7.VnS());
+  __ Uzp1(z16.VnD(), z8.VnD(), z9.VnD());
+  __ Uzp2(z17.VnD(), z8.VnD(), z9.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z2[] = {0x5577aa665555aa44, 0x5533aa225511aa00};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0xaaff55eeaadd55cc, 0xaabb55aaaa995588};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0x55aa776655aa5544, 0x55aa332255aa1100};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0xaa55ffeeaa55ddcc, 0xaa55bbaaaa559988};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x55aa55aa77665544, 0x55aa55aa33221100};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0xaa55aa55ffeeddcc, 0xaa55aa55bbaa9988};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0x55aa55aa55aa55aa, 0x7766554433221100};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0xaa55aa55aa55aa55, 0xffeeddccbbaa9988};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+
+    // Check uzp is the opposite of zip.
+    ASSERT_EQUAL_SVE(z0.VnD(), z10.VnD());
+    ASSERT_EQUAL_SVE(z1.VnD(), z11.VnD());
+    ASSERT_EQUAL_SVE(z0.VnD(), z12.VnD());
+    ASSERT_EQUAL_SVE(z1.VnD(), z13.VnD());
+    ASSERT_EQUAL_SVE(z0.VnD(), z14.VnD());
+    ASSERT_EQUAL_SVE(z1.VnD(), z15.VnD());
+    ASSERT_EQUAL_SVE(z0.VnD(), z16.VnD());
+    ASSERT_EQUAL_SVE(z1.VnD(), z17.VnD());
+  }
+}
+
+TEST_SVE(sve_fcadd) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Dup(z30.VnS(), 0);
+
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p2.VnH(), p0.VnH(), p1.VnH());  // Real elements.
+  __ Zip1(p3.VnH(), p1.VnH(), p0.VnH());  // Imaginary elements.
+
+  __ Fdup(z0.VnH(), 10.0);  // 10i + 10
+  __ Fdup(z1.VnH(), 5.0);   // 5i + 5
+  __ Index(z7.VnH(), 1, 1);
+  __ Scvtf(z7.VnH(), p0.Merging(), z7.VnH());  // Ai + B
+
+  __ Sel(z2.VnH(), p3, z1.VnH(), z30.VnH());  // 5i + 0
+  __ Sel(z3.VnH(), p2, z1.VnH(), z30.VnH());  // 0i + 5
+  __ Sel(z7.VnH(), p3, z7.VnH(), z0.VnH());   // Ai + 10
+  __ Ext(z8.VnB(), z7.VnB(), z7.VnB(), 2);
+  __ Sel(z8.VnH(), p2, z8.VnH(), z30.VnH());  // 0i + A
+
+  // (10i + 10) + rotate(5i + 0, 90)
+  //   = (10i + 10) + (0i - 5)
+  //   = 10i + 5
+  __ Fcadd(z4.VnH(), p0.Merging(), z0.VnH(), z2.VnH(), 90);
+
+  // (10i + 5) + rotate(0i + 5, 270)
+  //   = (10i + 5) + (-5i + 0)
+  //   = 5i + 5
+  __ Fcadd(z4.VnH(), p0.Merging(), z4.VnH(), z3.VnH(), 270);
+
+  // The same calculation, but selecting real/imaginary using predication.
+  __ Mov(z5, z0);
+  __ Fcadd(z5.VnH(), p2.Merging(), z5.VnH(), z1.VnH(), 90);
+  __ Fcadd(z5.VnH(), p3.Merging(), z5.VnH(), z1.VnH(), 270);
+
+  // Reference calculation: (10i + 10) - (5i + 5)
+  __ Fsub(z6.VnH(), z0.VnH(), z1.VnH());
+
+  // Calculation using varying imaginary values.
+  // (Ai + 10) + rotate(5i + 0, 90)
+  //   = (Ai + 10) + (0i - 5)
+  //   = Ai + 5
+  __ Fcadd(z7.VnH(), p0.Merging(), z7.VnH(), z2.VnH(), 90);
+
+  // (Ai + 5) + rotate(0i + A, 270)
+  //   = (Ai + 5) + (-Ai + 0)
+  //   = 5
+  __ Fcadd(z7.VnH(), p0.Merging(), z7.VnH(), z8.VnH(), 270);
+
+  // Repeated, but for wider elements.
+  __ Zip1(p2.VnS(), p0.VnS(), p1.VnS());
+  __ Zip1(p3.VnS(), p1.VnS(), p0.VnS());
+  __ Fdup(z0.VnS(), 42.0);
+  __ Fdup(z1.VnS(), 21.0);
+  __ Index(z11.VnS(), 1, 1);
+  __ Scvtf(z11.VnS(), p0.Merging(), z11.VnS());
+  __ Sel(z2.VnS(), p3, z1.VnS(), z30.VnS());
+  __ Sel(z29.VnS(), p2, z1.VnS(), z30.VnS());
+  __ Sel(z11.VnS(), p3, z11.VnS(), z0.VnS());
+  __ Ext(z12.VnB(), z11.VnB(), z11.VnB(), 4);
+  __ Sel(z12.VnS(), p2, z12.VnS(), z30.VnS());
+  __ Fcadd(z8.VnS(), p0.Merging(), z0.VnS(), z2.VnS(), 90);
+  __ Fcadd(z8.VnS(), p0.Merging(), z8.VnS(), z29.VnS(), 270);
+  __ Mov(z9, z0);
+  __ Fcadd(z9.VnS(), p2.Merging(), z9.VnS(), z1.VnS(), 90);
+  __ Fcadd(z9.VnS(), p3.Merging(), z9.VnS(), z1.VnS(), 270);
+  __ Fsub(z10.VnS(), z0.VnS(), z1.VnS());
+  __ Fcadd(z11.VnS(), p0.Merging(), z11.VnS(), z2.VnS(), 90);
+  __ Fcadd(z11.VnS(), p0.Merging(), z11.VnS(), z12.VnS(), 270);
+
+  __ Zip1(p2.VnD(), p0.VnD(), p1.VnD());
+  __ Zip1(p3.VnD(), p1.VnD(), p0.VnD());
+  __ Fdup(z0.VnD(), -42.0);
+  __ Fdup(z1.VnD(), -21.0);
+  __ Index(z15.VnD(), 1, 1);
+  __ Scvtf(z15.VnD(), p0.Merging(), z15.VnD());
+  __ Sel(z2.VnD(), p3, z1.VnD(), z30.VnD());
+  __ Sel(z28.VnD(), p2, z1.VnD(), z30.VnD());
+  __ Sel(z15.VnD(), p3, z15.VnD(), z0.VnD());
+  __ Ext(z16.VnB(), z15.VnB(), z15.VnB(), 8);
+  __ Sel(z16.VnD(), p2, z16.VnD(), z30.VnD());
+  __ Fcadd(z12.VnD(), p0.Merging(), z0.VnD(), z2.VnD(), 90);
+  __ Fcadd(z12.VnD(), p0.Merging(), z12.VnD(), z28.VnD(), 270);
+  __ Mov(z13, z0);
+  __ Fcadd(z13.VnD(), p2.Merging(), z13.VnD(), z1.VnD(), 90);
+  __ Fcadd(z13.VnD(), p3.Merging(), z13.VnD(), z1.VnD(), 270);
+  __ Fsub(z14.VnD(), z0.VnD(), z1.VnD());
+  __ Fcadd(z15.VnD(), p0.Merging(), z15.VnD(), z2.VnD(), 90);
+  __ Fcadd(z15.VnD(), p0.Merging(), z15.VnD(), z16.VnD(), 270);
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(z6.VnH(), z4.VnH());
+    ASSERT_EQUAL_SVE(z6.VnH(), z5.VnH());
+    ASSERT_EQUAL_SVE(z3.VnH(), z7.VnH());
+    ASSERT_EQUAL_SVE(z10.VnS(), z8.VnS());
+    ASSERT_EQUAL_SVE(z10.VnS(), z9.VnS());
+    ASSERT_EQUAL_SVE(z29.VnS(), z11.VnS());
+    ASSERT_EQUAL_SVE(z14.VnD(), z12.VnD());
+    ASSERT_EQUAL_SVE(z14.VnD(), z13.VnD());
+    ASSERT_EQUAL_SVE(z28.VnS(), z15.VnS());
+  }
+}
+
+TEST_SVE(sve_fcmla_index) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Ptrue(p0.VnB());
+
+  __ Fdup(z0.VnH(), 10.0);
+  __ Fdup(z2.VnH(), 2.0);
+  __ Zip1(z0.VnH(), z0.VnH(), z2.VnH());
+
+  // Duplicate complex numbers across z2 segments. First segment has 1i+0,
+  // second has 3i+2, etc.
+  __ Index(z1.VnH(), 0, 1);
+  __ Scvtf(z1.VnH(), p0.Merging(), z1.VnH());
+  __ Zip1(z2.VnS(), z1.VnS(), z1.VnS());
+  __ Zip1(z2.VnS(), z2.VnS(), z2.VnS());
+
+  // Derive a vector from z2 where only the third element in each segment
+  // contains a complex number, with other elements zero.
+  __ Index(z3.VnS(), 0, 1);
+  __ And(z3.VnS(), z3.VnS(), 3);
+  __ Cmpeq(p2.VnS(), p0.Zeroing(), z3.VnS(), 2);
+  __ Dup(z3.VnB(), 0);
+  __ Sel(z3.VnS(), p2, z2.VnS(), z3.VnS());
+
+  // Use indexed complex multiply on this vector, indexing the third element.
+  __ Dup(z4.VnH(), 0);
+  __ Fcmla(z4.VnH(), z0.VnH(), z3.VnH(), 2, 0);
+  __ Fcmla(z4.VnH(), z0.VnH(), z3.VnH(), 2, 90);
+
+  // Rotate the indexed complex number and repeat, negated, and with a different
+  // index.
+  __ Ext(z3.VnH(), z3.VnH(), z3.VnH(), 4);
+  __ Dup(z5.VnH(), 0);
+  __ Fcmla(z5.VnH(), z0.VnH(), z3.VnH(), 1, 180);
+  __ Fcmla(z5.VnH(), z0.VnH(), z3.VnH(), 1, 270);
+  __ Fneg(z5.VnH(), p0.Merging(), z5.VnH());
+
+  // Create a reference result from a vector complex multiply.
+  __ Dup(z6.VnH(), 0);
+  __ Fcmla(z6.VnH(), p0.Merging(), z0.VnH(), z2.VnH(), 0);
+  __ Fcmla(z6.VnH(), p0.Merging(), z0.VnH(), z2.VnH(), 90);
+
+  // Repeated, but for wider elements.
+  __ Fdup(z0.VnS(), 42.0);
+  __ Fdup(z2.VnS(), 24.0);
+  __ Zip1(z0.VnS(), z0.VnS(), z2.VnS());
+  __ Index(z1.VnS(), -42, 13);
+  __ Scvtf(z1.VnS(), p0.Merging(), z1.VnS());
+  __ Zip1(z2.VnD(), z1.VnD(), z1.VnD());
+  __ Zip1(z2.VnD(), z2.VnD(), z2.VnD());
+  __ Index(z3.VnD(), 0, 1);
+  __ And(z3.VnD(), z3.VnD(), 1);
+  __ Cmpeq(p2.VnD(), p0.Zeroing(), z3.VnD(), 1);
+  __ Dup(z3.VnB(), 0);
+  __ Sel(z3.VnD(), p2, z2.VnD(), z3.VnD());
+  __ Dup(z7.VnS(), 0);
+  __ Fcmla(z7.VnS(), z0.VnS(), z3.VnS(), 1, 0);
+  __ Fcmla(z7.VnS(), z0.VnS(), z3.VnS(), 1, 90);
+  __ Ext(z3.VnB(), z3.VnB(), z3.VnB(), 8);
+  __ Dup(z8.VnS(), 0);
+  __ Fcmla(z8.VnS(), z0.VnS(), z3.VnS(), 0, 180);
+  __ Fcmla(z8.VnS(), z0.VnS(), z3.VnS(), 0, 270);
+  __ Fneg(z8.VnS(), p0.Merging(), z8.VnS());
+  __ Dup(z9.VnS(), 0);
+  __ Fcmla(z9.VnS(), p0.Merging(), z0.VnS(), z2.VnS(), 0);
+  __ Fcmla(z9.VnS(), p0.Merging(), z0.VnS(), z2.VnS(), 90);
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(z6.VnH(), z4.VnH());
+    ASSERT_EQUAL_SVE(z6.VnH(), z5.VnH());
+    ASSERT_EQUAL_SVE(z9.VnS(), z7.VnS());
+    ASSERT_EQUAL_SVE(z9.VnS(), z8.VnS());
+  }
+}
+
+TEST_SVE(sve_fcmla) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p2.VnH(), p0.VnH(), p1.VnH());  // Real elements.
+  __ Zip1(p3.VnH(), p1.VnH(), p0.VnH());  // Imaginary elements.
+
+  __ Fdup(z0.VnH(), 10.0);
+  __ Fdup(z2.VnH(), 2.0);
+
+  // Create pairs of complex numbers, Ai + A. A is chosen to be non-zero, as
+  // the later fneg will result in a failed comparison otherwise.
+  __ Index(z1.VnH(), -4, 3);
+  __ Zip1(z1.VnH(), z1.VnH(), z1.VnH());
+  __ Zip1(z1.VnH(), z1.VnH(), z1.VnH());
+  __ Scvtf(z1.VnH(), p0.Merging(), z1.VnH());
+
+  __ Sel(z3.VnH(), p2, z0.VnH(), z1.VnH());  // Ai + 10
+  __ Sel(z4.VnH(), p2, z1.VnH(), z2.VnH());  // 2i + A
+
+  __ Zip1(p2.VnS(), p0.VnS(), p1.VnS());  // Even complex numbers.
+  __ Zip1(p3.VnS(), p1.VnS(), p0.VnS());  // Odd complex numbers.
+
+  // Calculate (Ai + 10) * (2i + A) = (20 + A^2)i + 8A, using predication to
+  // select only the complex numbers in odd-numbered element pairs. This leaves
+  // results in elements 2/3, 6/7, etc. with zero in elements 0/1, 4/5, etc.
+  //   ...      7      6   5   4      3      2   1   0     <-- element
+  //   ... | 20+A^2 | 8A | 0 | 0 | 20+A^2 | 8A | 0 | 0 |   <-- value
+  __ Dup(z5.VnH(), 0);
+  __ Fcmla(z5.VnH(), p3.Merging(), z4.VnH(), z3.VnH(), 0);
+  __ Fcmla(z5.VnH(), p3.Merging(), z4.VnH(), z3.VnH(), 90);
+
+  // Move the odd results to the even result positions.
+  //   ...   7   6      5      4   3   2      1      0     <-- element
+  //   ... | 0 | 0 | 20+A^2 | 8A | 0 | 0 | 20+A^2 | 8A |   <-- value
+  __ Ext(z5.VnB(), z5.VnB(), z5.VnB(), 4);
+
+  // Calculate -(Ai + 10) * (2i + A) = -(20 + A^2)i - 8A for the even complex
+  // numbers.
+  //   ...   7   6       5       4   3   2       1       0     <-- element
+  //   ... | 0 | 0 | -20-A^2 | -8A | 0 | 0 | -20-A^2 | -8A |   <-- value
+  __ Dup(z6.VnH(), 0);
+  __ Fcmla(z6.VnH(), p2.Merging(), z4.VnH(), z3.VnH(), 180);
+  __ Fcmla(z6.VnH(), p2.Merging(), z4.VnH(), z3.VnH(), 270);
+
+  // Negate the even results. The results in z6 should now match the results
+  // computed earlier in z5.
+  //   ...   7   6      5      4   3   2      1      0     <-- element
+  //   ... | 0 | 0 | 20+A^2 | 8A | 0 | 0 | 20+A^2 | 8A |   <-- value
+  __ Fneg(z6.VnH(), p2.Merging(), z6.VnH());
+
+
+  // Similarly, but for wider elements.
+  __ Zip1(p2.VnS(), p0.VnS(), p1.VnS());
+  __ Zip1(p3.VnS(), p1.VnS(), p0.VnS());
+  __ Index(z1.VnS(), -4, 3);
+  __ Zip1(z1.VnS(), z1.VnS(), z1.VnS());
+  __ Zip1(z1.VnS(), z1.VnS(), z1.VnS());
+  __ Scvtf(z1.VnS(), p0.Merging(), z1.VnS());
+  __ Fdup(z0.VnS(), 20.0);
+  __ Fdup(z2.VnS(), 21.0);
+  __ Sel(z3.VnS(), p2, z0.VnS(), z1.VnS());
+  __ Sel(z4.VnS(), p2, z1.VnS(), z2.VnS());
+  __ Punpklo(p2.VnH(), p2.VnB());
+  __ Punpklo(p3.VnH(), p3.VnB());
+  __ Dup(z7.VnS(), 0);
+  __ Fcmla(z7.VnS(), p3.Merging(), z4.VnS(), z3.VnS(), 0);
+  __ Fcmla(z7.VnS(), p3.Merging(), z4.VnS(), z3.VnS(), 90);
+  __ Ext(z7.VnB(), z7.VnB(), z7.VnB(), 8);
+  __ Dup(z8.VnS(), 0);
+  __ Fcmla(z8.VnS(), p2.Merging(), z4.VnS(), z3.VnS(), 180);
+  __ Fcmla(z8.VnS(), p2.Merging(), z4.VnS(), z3.VnS(), 270);
+  __ Fneg(z8.VnS(), p2.Merging(), z8.VnS());
+
+  // Double precision computed for even lanes only.
+  __ Zip1(p2.VnD(), p0.VnD(), p1.VnD());
+  __ Index(z1.VnD(), -4, 3);
+  __ Zip1(z1.VnD(), z1.VnD(), z1.VnD());
+  __ Zip1(z1.VnD(), z1.VnD(), z1.VnD());
+  __ Scvtf(z1.VnD(), p0.Merging(), z1.VnD());
+  __ Fdup(z0.VnD(), 20.0);
+  __ Fdup(z2.VnD(), 21.0);
+  __ Sel(z3.VnD(), p2, z0.VnD(), z1.VnD());
+  __ Sel(z4.VnD(), p2, z1.VnD(), z2.VnD());
+  __ Punpklo(p2.VnH(), p2.VnB());
+  __ Dup(z9.VnD(), 0);
+  __ Fcmla(z9.VnD(), p2.Merging(), z4.VnD(), z3.VnD(), 0);
+  __ Fcmla(z9.VnD(), p2.Merging(), z4.VnD(), z3.VnD(), 90);
+  __ Dup(z10.VnD(), 0);
+  __ Fcmla(z10.VnD(), p2.Merging(), z4.VnD(), z3.VnD(), 180);
+  __ Fcmla(z10.VnD(), p2.Merging(), z4.VnD(), z3.VnD(), 270);
+  __ Fneg(z10.VnD(), p2.Merging(), z10.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(z5.VnH(), z6.VnH());
+    ASSERT_EQUAL_SVE(z7.VnS(), z8.VnS());
+    ASSERT_EQUAL_SVE(z9.VnD(), z10.VnD());
+  }
+}
+
+// Create a pattern in dst where the value of each element in src is incremented
+// by the segment number. This allows varying a short input by a predictable
+// pattern for each segment.
+static void FPSegmentPatternHelper(MacroAssembler* masm,
+                                   const ZRegister& dst,
+                                   const PRegisterM& ptrue,
+                                   const ZRegister& src) {
+  VIXL_ASSERT(AreSameLaneSize(dst, src));
+  UseScratchRegisterScope temps(masm);
+  ZRegister ztmp = temps.AcquireZ().WithSameLaneSizeAs(dst);
+  masm->Index(ztmp, 0, 1);
+  masm->Asr(ztmp, ztmp, kQRegSizeInBytesLog2 - dst.GetLaneSizeInBytesLog2());
+  masm->Scvtf(ztmp, ptrue, ztmp);
+  masm->Fadd(dst, src, ztmp);
+}
+
+TEST_SVE(sve_fpmul_index) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in0[] = {0x3ff000003f803c00, 0xbff00000bf80bc00};
+  uint64_t in1[] = {0x3ff012343ff03c76, 0xbff01234bff0bc76};
+
+  __ Ptrue(p0.VnB());
+  // Repeat indexed vector across up to 2048-bit VL.
+  for (size_t i = 0; i < (kZRegMaxSize / kDRegSize); i++) {
+    InsrHelper(&masm, z25.VnD(), in0);
+  }
+  InsrHelper(&masm, z1.VnD(), in1);
+
+  FPSegmentPatternHelper(&masm, z0.VnH(), p0.Merging(), z25.VnH());
+  __ Fmul(z2.VnH(), z1.VnH(), z0.VnH(), 0);
+  __ Fmul(z3.VnH(), z1.VnH(), z0.VnH(), 1);
+  __ Fmul(z4.VnH(), z1.VnH(), z0.VnH(), 4);
+  __ Fmul(z5.VnH(), z1.VnH(), z0.VnH(), 7);
+
+  __ Fmul(z6.VnS(), z1.VnS(), z0.VnS(), 0);
+  __ Fmul(z7.VnS(), z1.VnS(), z0.VnS(), 1);
+  __ Fmul(z8.VnS(), z1.VnS(), z0.VnS(), 2);
+  __ Fmul(z9.VnS(), z1.VnS(), z0.VnS(), 3);
+
+  __ Fmul(z10.VnD(), z1.VnD(), z0.VnD(), 0);
+  __ Fmul(z11.VnD(), z1.VnD(), z0.VnD(), 1);
+
+  // Compute the results using other instructions.
+  __ Dup(z12.VnH(), z25.VnH(), 0);
+  FPSegmentPatternHelper(&masm, z12.VnH(), p0.Merging(), z12.VnH());
+  __ Fmul(z12.VnH(), z1.VnH(), z12.VnH());
+  __ Dup(z13.VnH(), z25.VnH(), 1);
+  FPSegmentPatternHelper(&masm, z13.VnH(), p0.Merging(), z13.VnH());
+  __ Fmul(z13.VnH(), z1.VnH(), z13.VnH());
+  __ Dup(z14.VnH(), z25.VnH(), 4);
+  FPSegmentPatternHelper(&masm, z14.VnH(), p0.Merging(), z14.VnH());
+  __ Fmul(z14.VnH(), z1.VnH(), z14.VnH());
+  __ Dup(z15.VnH(), z25.VnH(), 7);
+  FPSegmentPatternHelper(&masm, z15.VnH(), p0.Merging(), z15.VnH());
+  __ Fmul(z15.VnH(), z1.VnH(), z15.VnH());
+
+  __ Dup(z16.VnS(), z25.VnS(), 0);
+  FPSegmentPatternHelper(&masm, z16.VnH(), p0.Merging(), z16.VnH());
+  __ Fmul(z16.VnS(), z1.VnS(), z16.VnS());
+  __ Dup(z17.VnS(), z25.VnS(), 1);
+  FPSegmentPatternHelper(&masm, z17.VnH(), p0.Merging(), z17.VnH());
+  __ Fmul(z17.VnS(), z1.VnS(), z17.VnS());
+  __ Dup(z18.VnS(), z25.VnS(), 2);
+  FPSegmentPatternHelper(&masm, z18.VnH(), p0.Merging(), z18.VnH());
+  __ Fmul(z18.VnS(), z1.VnS(), z18.VnS());
+  __ Dup(z19.VnS(), z25.VnS(), 3);
+  FPSegmentPatternHelper(&masm, z19.VnH(), p0.Merging(), z19.VnH());
+  __ Fmul(z19.VnS(), z1.VnS(), z19.VnS());
+
+  __ Dup(z20.VnD(), z25.VnD(), 0);
+  FPSegmentPatternHelper(&masm, z20.VnH(), p0.Merging(), z20.VnH());
+  __ Fmul(z20.VnD(), z1.VnD(), z20.VnD());
+  __ Dup(z21.VnD(), z25.VnD(), 1);
+  FPSegmentPatternHelper(&masm, z21.VnH(), p0.Merging(), z21.VnH());
+  __ Fmul(z21.VnD(), z1.VnD(), z21.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    ASSERT_EQUAL_SVE(z12.VnH(), z2.VnH());
+    ASSERT_EQUAL_SVE(z13.VnH(), z3.VnH());
+    ASSERT_EQUAL_SVE(z14.VnH(), z4.VnH());
+    ASSERT_EQUAL_SVE(z15.VnH(), z5.VnH());
+    ASSERT_EQUAL_SVE(z16.VnS(), z6.VnS());
+    ASSERT_EQUAL_SVE(z17.VnS(), z7.VnS());
+    ASSERT_EQUAL_SVE(z18.VnS(), z8.VnS());
+    ASSERT_EQUAL_SVE(z19.VnS(), z9.VnS());
+    ASSERT_EQUAL_SVE(z20.VnD(), z10.VnD());
+    ASSERT_EQUAL_SVE(z21.VnD(), z11.VnD());
+  }
+}
+
+TEST_SVE(sve_ftmad) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t in_h0[] = {0x7c027e01fc02fe01,
+                      0x3c003c00bc00bc00,
+                      0x3c003c00bc00bc00};
+  uint64_t in_h1[] = {0xfe01fc027e017e01,
+                      0x3c00bc003c00bc00,
+                      0x3c00bc003c00bc00};
+  uint64_t in_s0[] = {0x7f800002ffc00001,
+                      0x3f8000003f800000,
+                      0xbf800000bf800000};
+  uint64_t in_s1[] = {0xffc00001ffc00001,
+                      0x3f800000bf800000,
+                      0x3f800000bf800000};
+  uint64_t in_d0[] = {0x7ff8000000000001,
+                      0x3ff0000000000000,
+                      0xbff0000000000000};
+  uint64_t in_d1[] = {0xfff0000000000002,
+                      0xbff0000000000000,
+                      0x3ff0000000000000};
+  InsrHelper(&masm, z0.VnD(), in_h0);
+  InsrHelper(&masm, z1.VnD(), in_h1);
+  InsrHelper(&masm, z2.VnD(), in_s0);
+  InsrHelper(&masm, z3.VnD(), in_s1);
+  InsrHelper(&masm, z4.VnD(), in_d0);
+  InsrHelper(&masm, z5.VnD(), in_d1);
+
+  __ Mov(z6, z0);
+  __ Ftmad(z6.VnH(), z6.VnH(), z1.VnH(), 0);
+  __ Mov(z7, z0);
+  __ Ftmad(z7.VnH(), z7.VnH(), z1.VnH(), 1);
+  __ Mov(z8, z0);
+  __ Ftmad(z8.VnH(), z8.VnH(), z1.VnH(), 2);
+
+  __ Mov(z9, z2);
+  __ Ftmad(z9.VnS(), z9.VnS(), z3.VnS(), 0);
+  __ Mov(z10, z2);
+  __ Ftmad(z10.VnS(), z10.VnS(), z3.VnS(), 3);
+  __ Mov(z11, z2);
+  __ Ftmad(z11.VnS(), z11.VnS(), z3.VnS(), 4);
+
+  __ Mov(z12, z4);
+  __ Ftmad(z12.VnD(), z12.VnD(), z5.VnD(), 0);
+  __ Mov(z13, z4);
+  __ Ftmad(z13.VnD(), z13.VnD(), z5.VnD(), 5);
+  __ Mov(z14, z4);
+  __ Ftmad(z14.VnD(), z14.VnD(), z5.VnD(), 7);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z6[] = {0x7e027e02fe02fe01,
+                              0x4000400000000000,
+                              0x4000400000000000};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0x7e027e02fe02fe01,
+                              0x3aab3800bcabbe00,
+                              0x3aab3800bcabbe00};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0x7e027e02fe02fe01,
+                              0x3c083c2abbefbbac,
+                              0x3c083c2abbefbbac};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0x7fc00002ffc00001,
+                              0x4000000040000000,
+                              0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x7fc00002ffc00001,
+                               0x3f7ff2ff3f7fa4fc,
+                               0xbf800680bf802d82};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+    uint64_t expected_z11[] = {0x7fc00002ffc00001,
+                               0x3f8000173f8000cd,
+                               0xbf7fffd2bf7ffe66};
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+    uint64_t expected_z12[] = {0x7ff8000000000002,
+                               0x4000000000000000,
+                               0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z12, z12.VnD());
+    uint64_t expected_z13[] = {0x7ff8000000000002,
+                               0x3fefffff6c0d846c,
+                               0xbff0000006b978ae};
+    ASSERT_EQUAL_SVE(expected_z13, z13.VnD());
+    uint64_t expected_z14[] = {0x7ff8000000000002,
+                               0x3feffffffffe708a,
+                               0xbff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z14, z14.VnD());
+  }
+}
+
+static void BasicFPArithHelper(MacroAssembler* masm,
+                               int lane_size_in_bits,
+                               const uint64_t (&inputs)[2],
+                               const uint64_t (&inputs_fmulx)[2],
+                               const uint64_t (&inputs_nans)[2]) {
+  int ls = lane_size_in_bits;
+
+  for (int i = 0; i < 16; i++) {
+    InsrHelper(masm, z0.VnD(), inputs);
+  }
+  ZRegister rvrs = z1.WithLaneSize(ls);
+  masm->Rev(rvrs, z0.WithLaneSize(ls));
+
+  int pred[] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 1, 0, 1};
+  Initialise(masm, p2.VnB(), pred);
+  PRegisterM p2m = p2.Merging();
+
+  masm->Mov(z2, z0);
+  masm->Fadd(z2.WithLaneSize(ls),
+             p2m,
+             z2.WithLaneSize(ls),
+             rvrs,
+             FastNaNPropagation);
+  masm->Mov(z3, z0);
+  masm->Fsub(z3.WithLaneSize(ls), p2m, z3.WithLaneSize(ls), rvrs);
+  masm->Mov(z4, z0);
+  masm->Fsub(z4.WithLaneSize(ls), p2m, rvrs, z4.WithLaneSize(ls));
+  masm->Mov(z5, z0);
+  masm->Fabd(z5.WithLaneSize(ls),
+             p2m,
+             z5.WithLaneSize(ls),
+             rvrs,
+             FastNaNPropagation);
+  masm->Mov(z6, z0);
+  masm->Fmul(z6.WithLaneSize(ls),
+             p2m,
+             z6.WithLaneSize(ls),
+             rvrs,
+             FastNaNPropagation);
+
+  for (int i = 0; i < 16; i++) {
+    InsrHelper(masm, z7.VnD(), inputs_fmulx);
+  }
+  masm->Rev(z8.WithLaneSize(ls), z7.WithLaneSize(ls));
+  masm->Fmulx(z7.WithLaneSize(ls),
+              p2m,
+              z7.WithLaneSize(ls),
+              z8.WithLaneSize(ls),
+              FastNaNPropagation);
+
+  InsrHelper(masm, z8.VnD(), inputs_nans);
+  masm->Mov(z9, z8);
+  masm->Fminnm(z9.WithLaneSize(ls),
+               p2m,
+               z9.WithLaneSize(ls),
+               rvrs,
+               FastNaNPropagation);
+  masm->Mov(z10, z8);
+  masm->Fmaxnm(z10.WithLaneSize(ls),
+               p2m,
+               z10.WithLaneSize(ls),
+               rvrs,
+               FastNaNPropagation);
+}
+
+TEST_SVE(sve_fp_arith_pred_h) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t inputs[] = {0x4800470046004500, 0x4400420040003c00};
+  uint64_t inputs_fmulx[] = {0x7c00fc007c00fc00, 0x0000800000008000};
+  uint64_t inputs_nans[] = {0x7fffffff7fffffff, 0x7bfffbff7fbbfbff};
+
+  BasicFPArithHelper(&masm, kHRegSize, inputs, inputs_fmulx, inputs_nans);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z2[] = {0x4880488048804880, 0x4880420048804880};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0x4700450042003c00, 0xbc004200c500c700};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xc700c500c200bc00, 0x3c00420045004700};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x4700450042003c00, 0x3c00420045004700};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x48004b004c804d00, 0x4d0042004b004800};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0xc000c000c000c000, 0xc0008000c000c000};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z9[] = {0x3c00400042004400, 0x4500fbff4700fbff};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x3c00400042004400, 0x7bfffbff47004800};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+  }
+}
+
+TEST_SVE(sve_fp_arith_pred_s) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t inputs[] = {0x4080000040400000, 0x400000003f800000};
+  uint64_t inputs_fmulx[] = {0x7f800000ff800000, 0x0000000080000000};
+  uint64_t inputs_nans[] = {0x7fffffffffffffff, 0x41000000c1000000};
+
+  BasicFPArithHelper(&masm, kSRegSize, inputs, inputs_fmulx, inputs_nans);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z2[] = {0x40a0000040a00000, 0x4000000040a00000};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0x404000003f800000, 0x40000000c0400000};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xc0400000bf800000, 0x4000000040400000};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x404000003f800000, 0x4000000040400000};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x4080000040c00000, 0x4000000040800000};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0xc0000000c0000000, 0x00000000c0000000};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z9[] = {0x3f80000040000000, 0x41000000c1000000};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x3f80000040000000, 0x4100000040800000};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+  }
+}
+
+TEST_SVE(sve_fp_arith_pred_d) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t inputs[] = {0x4000000000000000, 0x3ff0000000000000};
+  uint64_t inputs_fmulx[] = {0x7ff0000000000000, 0x8000000000000000};
+  uint64_t inputs_nans[] = {0x7fffffffffffffff, 0x4100000000000000};
+
+  BasicFPArithHelper(&masm, kDRegSize, inputs, inputs_fmulx, inputs_nans);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z2[] = {0x4008000000000000, 0x4008000000000000};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0x3ff0000000000000, 0xbff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0xbff0000000000000, 0x3ff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x3ff0000000000000, 0x3ff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x4000000000000000, 0x4000000000000000};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0xc000000000000000, 0xc000000000000000};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z9[] = {0x3ff0000000000000, 0x4000000000000000};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    uint64_t expected_z10[] = {0x3ff0000000000000, 0x4100000000000000};
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+  }
+}
+
+TEST_SVE(sve_fp_arith_pred_imm) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int pred[] = {0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 0, 0, 1, 0, 1};
+  Initialise(&masm, p0.VnB(), pred);
+  PRegisterM p0m = p0.Merging();
+  __ Ptrue(p1.VnB());
+
+  __ Fdup(z0.VnD(), 0.0);
+
+  __ Mov(z1, z0);
+  __ Fdiv(z1.VnH(), p1.Merging(), z1.VnH(), z1.VnH());
+  __ Mov(z2, z0);
+  __ Fadd(z2.VnH(), p0m, z2.VnH(), 0.5);
+  __ Mov(z3, z2);
+  __ Fsub(z3.VnH(), p0m, z3.VnH(), 1.0);
+  __ Mov(z4, z3);
+  __ Fsub(z4.VnH(), p0m, 1.0, z4.VnH());
+  __ Mov(z5, z4);
+  __ Fmul(z5.VnH(), p0m, z5.VnH(), 2.0);
+  __ Mov(z6, z1);
+  __ Fminnm(z6.VnH(), p0m, z6.VnH(), 0.0);
+  __ Mov(z7, z1);
+  __ Fmaxnm(z7.VnH(), p0m, z7.VnH(), 1.0);
+  __ Mov(z8, z5);
+  __ Fmin(z8.VnH(), p0m, z8.VnH(), 1.0);
+  __ Mov(z9, z5);
+  __ Fmax(z9.VnH(), p0m, z9.VnH(), 0.0);
+
+  __ Mov(z11, z0);
+  __ Fdiv(z11.VnS(), p1.Merging(), z11.VnS(), z11.VnS());
+  __ Mov(z12, z0);
+  __ Fadd(z12.VnS(), p0m, z12.VnS(), 0.5);
+  __ Mov(z13, z12);
+  __ Fsub(z13.VnS(), p0m, z13.VnS(), 1.0);
+  __ Mov(z14, z13);
+  __ Fsub(z14.VnS(), p0m, 1.0, z14.VnS());
+  __ Mov(z15, z14);
+  __ Fmul(z15.VnS(), p0m, z15.VnS(), 2.0);
+  __ Mov(z16, z11);
+  __ Fminnm(z16.VnS(), p0m, z16.VnS(), 0.0);
+  __ Mov(z17, z11);
+  __ Fmaxnm(z17.VnS(), p0m, z17.VnS(), 1.0);
+  __ Mov(z18, z15);
+  __ Fmin(z18.VnS(), p0m, z18.VnS(), 1.0);
+  __ Mov(z19, z15);
+  __ Fmax(z19.VnS(), p0m, z19.VnS(), 0.0);
+
+  __ Mov(z21, z0);
+  __ Fdiv(z21.VnD(), p1.Merging(), z21.VnD(), z21.VnD());
+  __ Mov(z22, z0);
+  __ Fadd(z22.VnD(), p0m, z22.VnD(), 0.5);
+  __ Mov(z23, z22);
+  __ Fsub(z23.VnD(), p0m, z23.VnD(), 1.0);
+  __ Mov(z24, z23);
+  __ Fsub(z24.VnD(), p0m, 1.0, z24.VnD());
+  __ Mov(z25, z24);
+  __ Fmul(z25.VnD(), p0m, z25.VnD(), 2.0);
+  __ Mov(z26, z21);
+  __ Fminnm(z26.VnD(), p0m, z26.VnD(), 0.0);
+  __ Mov(z27, z21);
+  __ Fmaxnm(z27.VnD(), p0m, z27.VnD(), 1.0);
+  __ Mov(z28, z25);
+  __ Fmin(z28.VnD(), p0m, z28.VnD(), 1.0);
+  __ Mov(z29, z25);
+  __ Fmax(z29.VnD(), p0m, z29.VnD(), 0.0);
+
+  __ Index(z0.VnH(), -3, 1);
+  __ Scvtf(z0.VnH(), p1.Merging(), z0.VnH());
+  __ Fmax(z0.VnH(), p1.Merging(), z0.VnH(), 0.0);
+  __ Index(z1.VnS(), -4, 2);
+  __ Scvtf(z1.VnS(), p1.Merging(), z1.VnS());
+  __ Fadd(z1.VnS(), p1.Merging(), z1.VnS(), 1.0);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z2[] = {0x3800380038003800, 0x3800000038003800};
+    ASSERT_EQUAL_SVE(expected_z2, z2.VnD());
+    uint64_t expected_z3[] = {0xb800b800b800b800, 0xb8000000b800b800};
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    uint64_t expected_z4[] = {0x3e003e003e003e00, 0x3e0000003e003e00};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x4200420042004200, 0x4200000042004200};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    uint64_t expected_z6[] = {0x0000000000000000, 0x00007e0000000000};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0x3c003c003c003c00, 0x3c007e003c003c00};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    uint64_t expected_z8[] = {0x3c003c003c003c00, 0x3c0000003c003c00};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0x4200420042004200, 0x4200000042004200};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+
+    uint64_t expected_z12[] = {0x3f0000003f000000, 0x000000003f000000};
+    ASSERT_EQUAL_SVE(expected_z12, z12.VnD());
+    uint64_t expected_z13[] = {0xbf000000bf000000, 0x00000000bf000000};
+    ASSERT_EQUAL_SVE(expected_z13, z13.VnD());
+    uint64_t expected_z14[] = {0x3fc000003fc00000, 0x000000003fc00000};
+    ASSERT_EQUAL_SVE(expected_z14, z14.VnD());
+    uint64_t expected_z15[] = {0x4040000040400000, 0x0000000040400000};
+    ASSERT_EQUAL_SVE(expected_z15, z15.VnD());
+    uint64_t expected_z16[] = {0x0000000000000000, 0x7fc0000000000000};
+    ASSERT_EQUAL_SVE(expected_z16, z16.VnD());
+    uint64_t expected_z17[] = {0x3f8000003f800000, 0x7fc000003f800000};
+    ASSERT_EQUAL_SVE(expected_z17, z17.VnD());
+    uint64_t expected_z18[] = {0x3f8000003f800000, 0x000000003f800000};
+    ASSERT_EQUAL_SVE(expected_z18, z18.VnD());
+    uint64_t expected_z19[] = {0x4040000040400000, 0x0000000040400000};
+    ASSERT_EQUAL_SVE(expected_z19, z19.VnD());
+
+    uint64_t expected_z22[] = {0x3fe0000000000000, 0x3fe0000000000000};
+    ASSERT_EQUAL_SVE(expected_z22, z22.VnD());
+    uint64_t expected_z23[] = {0xbfe0000000000000, 0xbfe0000000000000};
+    ASSERT_EQUAL_SVE(expected_z23, z23.VnD());
+    uint64_t expected_z24[] = {0x3ff8000000000000, 0x3ff8000000000000};
+    ASSERT_EQUAL_SVE(expected_z24, z24.VnD());
+    uint64_t expected_z25[] = {0x4008000000000000, 0x4008000000000000};
+    ASSERT_EQUAL_SVE(expected_z25, z25.VnD());
+    uint64_t expected_z26[] = {0x0000000000000000, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z26, z26.VnD());
+    uint64_t expected_z27[] = {0x3ff0000000000000, 0x3ff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z27, z27.VnD());
+    uint64_t expected_z28[] = {0x3ff0000000000000, 0x3ff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z28, z28.VnD());
+    uint64_t expected_z29[] = {0x4008000000000000, 0x4008000000000000};
+    ASSERT_EQUAL_SVE(expected_z29, z29.VnD());
+    uint64_t expected_z0[] = {0x4400420040003c00, 0x0000000000000000};
+    ASSERT_EQUAL_SVE(expected_z0, z0.VnD());
+    uint64_t expected_z1[] = {0x404000003f800000, 0xbf800000c0400000};
+    ASSERT_EQUAL_SVE(expected_z1, z1.VnD());
+  }
+}
+
+TEST_SVE(sve_fscale) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  uint64_t inputs_h[] = {0x4800470046004500, 0x4400420040003c00};
+  InsrHelper(&masm, z0.VnD(), inputs_h);
+  uint64_t inputs_s[] = {0x4080000040400000, 0x400000003f800000};
+  InsrHelper(&masm, z1.VnD(), inputs_s);
+  uint64_t inputs_d[] = {0x40f0000000000000, 0x4000000000000000};
+  InsrHelper(&masm, z2.VnD(), inputs_d);
+
+  uint64_t scales[] = {0x00080002fff8fffe, 0x00100001fff0ffff};
+  InsrHelper(&masm, z3.VnD(), scales);
+
+  __ Ptrue(p0.VnB());
+  int pred[] = {0, 1, 0, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 1};
+  Initialise(&masm, p1.VnB(), pred);
+
+  __ Mov(z4, z0);
+  __ Fscale(z4.VnH(), p0.Merging(), z4.VnH(), z3.VnH());
+  __ Mov(z5, z0);
+  __ Fscale(z5.VnH(), p1.Merging(), z5.VnH(), z3.VnH());
+
+  __ Sunpklo(z3.VnS(), z3.VnH());
+  __ Mov(z6, z1);
+  __ Fscale(z6.VnS(), p0.Merging(), z6.VnS(), z3.VnS());
+  __ Mov(z7, z1);
+  __ Fscale(z7.VnS(), p1.Merging(), z7.VnS(), z3.VnS());
+
+  __ Sunpklo(z3.VnD(), z3.VnS());
+  __ Mov(z8, z2);
+  __ Fscale(z8.VnD(), p0.Merging(), z8.VnD(), z3.VnD());
+  __ Mov(z9, z2);
+  __ Fscale(z9.VnD(), p1.Merging(), z9.VnD(), z3.VnD());
+
+  // Test full double precision range scaling.
+  __ Dup(z10.VnD(), 2045);
+  __ Dup(z11.VnD(), 0x0010000000000000);  // 2^-1022
+  __ Fscale(z11.VnD(), p0.Merging(), z11.VnD(), z10.VnD());
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    uint64_t expected_z4[] = {0x68004f0026003d00, 0x7c00460002003800};
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    uint64_t expected_z5[] = {0x68004f0026004500, 0x7c00420002003800};
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+
+    uint64_t expected_z6[] = {0x4880000040c00000, 0x380000003f000000};
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    uint64_t expected_z7[] = {0x4880000040400000, 0x400000003f000000};
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+
+    uint64_t expected_z8[] = {0x3ff0000000000000, 0x3ff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    uint64_t expected_z9[] = {0x40f0000000000000, 0x3ff0000000000000};
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+
+    uint64_t expected_z11[] = {0x7fe0000000000000, 0x7fe0000000000000};
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+  }
+}
+
+typedef void (MacroAssembler::*FcvtFrintMFn)(const ZRegister& zd,
+                                             const PRegisterM& pg,
+                                             const ZRegister& zn);
+
+typedef void (MacroAssembler::*FcvtFrintZFn)(const ZRegister& zd,
+                                             const PRegisterZ& pg,
+                                             const ZRegister& zn);
+
+template <typename F, size_t N>
+static void TestFcvtFrintHelper(Test* config,
+                                FcvtFrintMFn macro_m,
+                                FcvtFrintZFn macro_z,
+                                int dst_type_size_in_bits,
+                                int src_type_size_in_bits,
+                                const F (&zn_inputs)[N],
+                                const int (&pg_inputs)[N],
+                                const uint64_t (&zd_expected_all_active)[N]) {
+  VIXL_ASSERT(macro_m != NULL);
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // If the input and result types have a different size, the instruction
+  // options on elements of the largest specified type is determined by the
+  // larger type.
+  int lane_size_in_bits =
+      std::max(dst_type_size_in_bits, src_type_size_in_bits);
+
+  ZRegister zd_all_active = z25;
+  ZRegister zd_merging = z26;
+  ZRegister zn = z27;
+
+  uint64_t zn_rawbits[N];
+  FPToRawbitsWithSize(zn_inputs, zn_rawbits, src_type_size_in_bits);
+  InsrHelper(&masm, zn.WithLaneSize(lane_size_in_bits), zn_rawbits);
+
+  PRegisterWithLaneSize pg_all_active = p0.WithLaneSize(lane_size_in_bits);
+  __ Ptrue(pg_all_active);
+
+  // Test floating-point conversions with all lanes actived.
+  (masm.*macro_m)(zd_all_active.WithLaneSize(dst_type_size_in_bits),
+                  pg_all_active.Merging(),
+                  zn.WithLaneSize(src_type_size_in_bits));
+
+  PRegisterWithLaneSize pg_merging = p1.WithLaneSize(lane_size_in_bits);
+  Initialise(&masm, pg_merging, pg_inputs);
+
+  __ Dup(zd_merging.VnD(), 0x0bad0bad0bad0bad);
+
+  // Use the same `zn` inputs to test floating-point conversions but partial
+  // lanes are set inactive.
+  (masm.*macro_m)(zd_merging.WithLaneSize(dst_type_size_in_bits),
+                  pg_merging.Merging(),
+                  zn.WithLaneSize(src_type_size_in_bits));
+
+  ZRegister zd_zeroing = z24;
+  PRegisterWithLaneSize pg_zeroing = p1.WithLaneSize(lane_size_in_bits);
+  Initialise(&masm, pg_zeroing, pg_inputs);
+
+  if (macro_z != NULL) {
+    __ Dup(zd_zeroing.VnD(), 0x0bad0bad0bad0bad);
+    (masm.*macro_z)(zd_zeroing.WithLaneSize(dst_type_size_in_bits),
+                    pg_zeroing.Zeroing(),
+                    zn.WithLaneSize(src_type_size_in_bits));
+  }
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(zd_expected_all_active,
+                     zd_all_active.WithLaneSize(lane_size_in_bits));
+
+    uint64_t zd_expected_merging[N];
+    for (unsigned i = 0; i < N; i++) {
+      zd_expected_merging[i] =
+          pg_inputs[i] ? zd_expected_all_active[i]
+                       : 0x0bad0bad0bad0bad & GetUintMask(lane_size_in_bits);
+    }
+    ASSERT_EQUAL_SVE(zd_expected_merging,
+                     zd_merging.WithLaneSize(lane_size_in_bits));
+
+    if (macro_z != NULL) {
+      uint64_t zd_expected_zeroing[N] = {0};
+      for (unsigned i = 0; i < N; i++) {
+        if (pg_inputs[i]) {
+          zd_expected_zeroing[i] = zd_expected_all_active[i];
+        }
+      }
+      ASSERT_EQUAL_SVE(zd_expected_zeroing,
+                       zd_zeroing.WithLaneSize(lane_size_in_bits));
+    }
+  }
+}
+
+template <typename F, size_t N>
+static void TestFcvtzHelper(Test* config,
+                            FcvtFrintMFn macro_m,
+                            int dst_type_size_in_bits,
+                            int src_type_size_in_bits,
+                            const F (&zn_inputs)[N],
+                            const int (&pg_inputs)[N],
+                            const uint64_t (&zd_expected_all_active)[N]) {
+  TestFcvtFrintHelper(config,
+                      macro_m,
+                      // Fcvt variants have no zeroing predication form.
+                      NULL,
+                      dst_type_size_in_bits,
+                      src_type_size_in_bits,
+                      zn_inputs,
+                      pg_inputs,
+                      zd_expected_all_active);
+}
+
+TEST_SVE(fcvtzs_fcvtzu_float16) {
+  const double h_max_float16 = 0x7ff0;          // Largest float16 == INT16_MAX.
+  const double h_min_float16 = -h_max_float16;  // Smallest float16 > INT16_MIN.
+  const double largest_float16 = 0xffe0;        // 65504
+  const double smallest_float16 = -largest_float16;
+  const double h_max_int_add_one = 0x8000;
+
+  double zn_inputs[] = {1.0,
+                        1.1,
+                        1.5,
+                        -1.5,
+                        h_max_float16,
+                        h_min_float16,
+                        largest_float16,
+                        smallest_float16,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity,
+                        h_max_int_add_one};
+
+  int pg_inputs[] = {0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1};
+
+  uint64_t expected_fcvtzs_fp162h[] =
+      {1, 1, 1, 0xffff, 0x7ff0, 0x8010, 0x7fff, 0x8000, 0x7fff, 0x8000, 0x7fff};
+
+  uint64_t expected_fcvtzu_fp162h[] =
+      {1, 1, 1, 0, 0x7ff0, 0, 0xffe0, 0, 0xffff, 0, 0x8000};
+
+  // Float16 to 16-bit integers.
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzs,
+                  kHRegSize,
+                  kHRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzs_fp162h);
+
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzu,
+                  kHRegSize,
+                  kHRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzu_fp162h);
+
+  uint64_t expected_fcvtzs_fp162w[] = {1,
+                                       1,
+                                       1,
+                                       0xffffffff,
+                                       0x7ff0,
+                                       0xffff8010,
+                                       0xffe0,
+                                       0xffff0020,
+                                       0x7fffffff,
+                                       0x80000000,
+                                       0x8000};
+
+  uint64_t expected_fcvtzu_fp162w[] =
+      {1, 1, 1, 0, 0x7ff0, 0, 0xffe0, 0, 0xffffffff, 0, 0x8000};
+
+  // Float16 to 32-bit integers.
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzs,
+                  kSRegSize,
+                  kHRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzs_fp162w);
+
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzu,
+                  kSRegSize,
+                  kHRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzu_fp162w);
+
+  uint64_t expected_fcvtzs_fp162x[] = {1,
+                                       1,
+                                       1,
+                                       0xffffffffffffffff,
+                                       0x7ff0,
+                                       0xffffffffffff8010,
+                                       0xffe0,
+                                       0xffffffffffff0020,
+                                       0x7fffffffffffffff,
+                                       0x8000000000000000,
+                                       0x8000};
+
+  uint64_t expected_fcvtzu_fp162x[] =
+      {1, 1, 1, 0, 0x7ff0, 0, 0xffe0, 0, 0xffffffffffffffff, 0, 0x8000};
+
+  // Float16 to 64-bit integers.
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzs,
+                  kDRegSize,
+                  kHRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzs_fp162x);
+
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzu,
+                  kDRegSize,
+                  kHRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzu_fp162x);
+}
+
+TEST_SVE(fcvtzs_fcvtzu_float) {
+  const double w_max_float = 0x7fffff80;          // Largest float < INT32_MAX.
+  const double w_min_float = -w_max_float;        // Smallest float > INT32_MIN.
+  const double x_max_float = 0x7fffff8000000000;  // Largest float < INT64_MAX.
+  const double x_min_float = -x_max_float;        // Smallest float > INT64_MIN.
+  const double w_min_int_add_one = 0x80000000;
+  const double x_max_int_add_one = 0x80000000'00000000;
+
+  double zn_inputs[] = {1.0,
+                        1.1,
+                        1.5,
+                        -1.5,
+                        w_max_float,
+                        w_min_float,
+                        x_max_float,
+                        x_min_float,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity,
+                        w_min_int_add_one,
+                        x_max_int_add_one};
+
+  int pg_inputs[] = {0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1};
+
+  uint64_t expected_fcvtzs_s2w[] = {1,
+                                    1,
+                                    1,
+                                    0xffffffff,
+                                    0x7fffff80,
+                                    0x80000080,
+                                    0x7fffffff,
+                                    0x80000000,
+                                    0x7fffffff,
+                                    0x80000000,
+                                    0x7fffffff,
+                                    0x7fffffff};
+
+  uint64_t expected_fcvtzu_s2w[] = {1,
+                                    1,
+                                    1,
+                                    0,
+                                    0x7fffff80,
+                                    0,
+                                    0xffffffff,
+                                    0,
+                                    0xffffffff,
+                                    0,
+                                    0x80000000,
+                                    0xffffffff};
+
+  // Float to 32-bit integers.
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzs,
+                  kSRegSize,
+                  kSRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzs_s2w);
+
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzu,
+                  kSRegSize,
+                  kSRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzu_s2w);
+
+  uint64_t expected_fcvtzs_s2x[] = {1,
+                                    1,
+                                    1,
+                                    0xffffffffffffffff,
+                                    0x7fffff80,
+                                    0xffffffff80000080,
+                                    0x7fffff8000000000,
+                                    0x8000008000000000,
+                                    0x7fffffffffffffff,
+                                    0x8000000000000000,
+                                    0x80000000,
+                                    0x7fffffffffffffff};
+
+  uint64_t expected_fcvtzu_s2x[] = {1,
+                                    1,
+                                    1,
+                                    0,
+                                    0x7fffff80,
+                                    0,
+                                    0x7fffff8000000000,
+                                    0,
+                                    0xffffffffffffffff,
+                                    0,
+                                    0x80000000,
+                                    0x8000000000000000};
+
+  // Float to 64-bit integers.
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzs,
+                  kDRegSize,
+                  kSRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzs_s2x);
+
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzu,
+                  kDRegSize,
+                  kSRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzu_s2x);
+}
+
+TEST_SVE(fcvtzs_fcvtzu_double) {
+  const double w_max_float = 0x7fffff80;          // Largest float < INT32_MAX.
+  const double w_min_float = -w_max_float;        // Smallest float > INT32_MIN.
+  const double x_max_float = 0x7fffff8000000000;  // Largest float < INT64_MAX.
+  const double x_min_float = -x_max_float;        // Smallest float > INT64_MIN.
+  const double w_max_double = kWMaxInt;       // Largest double == INT32_MAX.
+  const double w_min_double = -w_max_double;  // Smallest double > INT32_MIN.
+  const double x_max_double =
+      0x7ffffffffffffc00;                     // Largest double < INT64_MAX.
+  const double x_min_double = -x_max_double;  // Smallest double > INT64_MIN.
+  const double w_max_int_sub_one = kWMaxInt - 1;
+  const double w_min_int_add_one = kWMinInt + 1;
+  const double w_max_int_add_one = 0x80000000;
+  const double x_max_int_add_one = 0x80000000'00000000;
+
+  double zn_inputs[] = {1.0,
+                        1.1,
+                        1.5,
+                        -1.5,
+                        w_max_float,
+                        w_min_float,
+                        x_max_float,
+                        x_min_float,
+                        w_max_double,
+                        w_min_double,
+                        x_max_double,
+                        x_min_double,
+                        kFP64PositiveInfinity,
+                        kFP64NegativeInfinity,
+                        w_max_int_sub_one,
+                        w_min_int_add_one,
+                        w_max_int_add_one,
+                        x_max_int_add_one};
+
+  int pg_inputs[] = {1, 1, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 0};
+
+  uint64_t expected_fcvtzs_d2w[] = {1,
+                                    1,
+                                    1,
+                                    0xffffffffffffffff,
+                                    0x7fffff80,
+                                    0xffffffff80000080,
+                                    0x7fffffff,
+                                    0xffffffff80000000,
+                                    0x7fffffff,
+                                    0xffffffff80000001,
+                                    0x7fffffff,
+                                    0xffffffff80000000,
+                                    0x7fffffff,
+                                    0xffffffff80000000,
+                                    0x7ffffffe,
+                                    0xffffffff80000001,
+                                    0x7fffffff,
+                                    0x7fffffff};
+
+  uint64_t expected_fcvtzu_d2w[] = {1,
+                                    1,
+                                    1,
+                                    0,
+                                    0x7fffff80,
+                                    0,
+                                    0xffffffff,
+                                    0,
+                                    0x7fffffff,
+                                    0,
+                                    0xffffffff,
+                                    0,
+                                    0xffffffff,
+                                    0,
+                                    0x7ffffffe,
+                                    0,
+                                    0x80000000,
+                                    0xffffffff};
+
+  // Double to 32-bit integers.
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzs,
+                  kSRegSize,
+                  kDRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzs_d2w);
+
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzu,
+                  kSRegSize,
+                  kDRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzu_d2w);
+
+  uint64_t expected_fcvtzs_d2x[] = {1,
+                                    1,
+                                    1,
+                                    0xffffffffffffffff,
+                                    0x7fffff80,
+                                    0xffffffff80000080,
+                                    0x7fffff8000000000,
+                                    0x8000008000000000,
+                                    0x7fffffff,
+                                    0xffffffff80000001,
+                                    0x7ffffffffffffc00,
+                                    0x8000000000000400,
+                                    0x7fffffffffffffff,
+                                    0x8000000000000000,
+                                    0x7ffffffe,
+                                    0xffffffff80000001,
+                                    0x80000000,
+                                    0x7fffffffffffffff};
+
+  uint64_t expected_fcvtzu_d2x[] = {1,
+                                    1,
+                                    1,
+                                    0,
+                                    0x7fffff80,
+                                    0,
+                                    0x7fffff8000000000,
+                                    0,
+                                    0x7fffffff,
+                                    0,
+                                    0x7ffffffffffffc00,
+                                    0,
+                                    0xffffffffffffffff,
+                                    0,
+                                    0x000000007ffffffe,
+                                    0,
+                                    0x80000000,
+                                    0x8000000000000000};
+
+  // Double to 64-bit integers.
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzs,
+                  kDRegSize,
+                  kDRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzs_d2x);
+
+  TestFcvtzHelper(config,
+                  &MacroAssembler::Fcvtzu,
+                  kDRegSize,
+                  kDRegSize,
+                  zn_inputs,
+                  pg_inputs,
+                  expected_fcvtzu_d2x);
+}
+
+template <typename F, size_t N>
+static void TestFrintHelper(Test* config,
+                            FcvtFrintMFn macro_m,
+                            FcvtFrintZFn macro_z,
+                            int lane_size_in_bits,
+                            const F (&zn_inputs)[N],
+                            const int (&pg_inputs)[N],
+                            const F (&zd_expected)[N]) {
+  uint64_t zd_expected_rawbits[N];
+  FPToRawbitsWithSize(zd_expected, zd_expected_rawbits, lane_size_in_bits);
+  TestFcvtFrintHelper(config,
+                      macro_m,
+                      macro_z,
+                      lane_size_in_bits,
+                      lane_size_in_bits,
+                      zn_inputs,
+                      pg_inputs,
+                      zd_expected_rawbits);
+}
+
+TEST_SVE(frint) {
+  const double inf_pos = kFP64PositiveInfinity;
+  const double inf_neg = kFP64NegativeInfinity;
+
+  double zn_inputs[] =
+      {1.1, 1.5, 1.9, 2.5, -1.5, -2.5, 0.0, -0.0, -0.2, inf_pos, inf_neg};
+  double zd_expected_a[] =
+      {1.0, 2.0, 2.0, 3.0, -2.0, -3.0, 0.0, -0.0, -0.0, inf_pos, inf_neg};
+  double zd_expected_i[] =
+      {1.0, 2.0, 2.0, 2.0, -2.0, -2.0, 0.0, -0.0, -0.0, inf_pos, inf_neg};
+  double zd_expected_m[] =
+      {1.0, 1.0, 1.0, 2.0, -2.0, -3.0, 0.0, -0.0, -1.0, inf_pos, inf_neg};
+  double zd_expected_n[] =
+      {1.0, 2.0, 2.0, 2.0, -2.0, -2.0, 0.0, -0.0, -0.0, inf_pos, inf_neg};
+  double zd_expected_p[] =
+      {2.0, 2.0, 2.0, 3.0, -1.0, -2.0, 0.0, -0.0, -0.0, inf_pos, inf_neg};
+  double zd_expected_x[] =
+      {1.0, 2.0, 2.0, 2.0, -2.0, -2.0, 0.0, -0.0, -0.0, inf_pos, inf_neg};
+  double zd_expected_z[] =
+      {1.0, 1.0, 1.0, 2.0, -1.0, -2.0, 0.0, -0.0, -0.0, inf_pos, inf_neg};
+
+  int pg_inputs[] = {0, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0};
+
+  struct TestDataSet {
+    FcvtFrintMFn macro_m;  // merging form.
+    FcvtFrintZFn macro_z;  // zeroing form.
+    double (&expected)[11];
+  };
+
+  TestDataSet test_data[] =
+      {{&MacroAssembler::Frinta, &MacroAssembler::Frinta, zd_expected_a},
+       {&MacroAssembler::Frinti, &MacroAssembler::Frinti, zd_expected_i},
+       {&MacroAssembler::Frintm, &MacroAssembler::Frintm, zd_expected_m},
+       {&MacroAssembler::Frintn, &MacroAssembler::Frintn, zd_expected_n},
+       {&MacroAssembler::Frintp, &MacroAssembler::Frintp, zd_expected_p},
+       {&MacroAssembler::Frintx, &MacroAssembler::Frintx, zd_expected_x},
+       {&MacroAssembler::Frintz, &MacroAssembler::Frintz, zd_expected_z}};
+
+  unsigned lane_sizes[] = {kHRegSize, kSRegSize, kDRegSize};
+
+  for (size_t i = 0; i < sizeof(test_data) / sizeof(TestDataSet); i++) {
+    for (size_t j = 0; j < ArrayLength(lane_sizes); j++) {
+      TestFrintHelper(config,
+                      test_data[i].macro_m,
+                      test_data[i].macro_z,
+                      lane_sizes[j],
+                      zn_inputs,
+                      pg_inputs,
+                      test_data[i].expected);
+    }
+  }
+}
+
+struct CvtfTestDataSet {
+  uint64_t int_value;
+  uint64_t scvtf_result;
+  uint64_t ucvtf_result;
+};
+
+template <size_t N>
+static void TestUScvtfHelper(Test* config,
+                             int dst_type_size_in_bits,
+                             int src_type_size_in_bits,
+                             const int (&pg_inputs)[N],
+                             const CvtfTestDataSet (&data_set)[N]) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  // Unpack the data from the array of struct into individual arrays that can
+  // simplify the testing.
+  uint64_t zn_inputs[N];
+  uint64_t expected_zd_scvtf_all_active[N];
+  uint64_t expected_zd_ucvtf_all_active[N];
+  for (size_t i = 0; i < N; i++) {
+    zn_inputs[i] = data_set[i].int_value;
+    expected_zd_scvtf_all_active[i] = data_set[i].scvtf_result;
+    expected_zd_ucvtf_all_active[i] = data_set[i].ucvtf_result;
+  }
+
+  // If the input and result types have a different size, the instruction
+  // operates on elements of the largest specified type.
+  int lane_size_in_bits =
+      std::max(dst_type_size_in_bits, src_type_size_in_bits);
+
+  ZRegister zd_scvtf_all_active = z25;
+  ZRegister zd_ucvtf_all_active = z26;
+  ZRegister zn = z27;
+  InsrHelper(&masm, zn.WithLaneSize(lane_size_in_bits), zn_inputs);
+
+  PRegisterWithLaneSize pg_all_active = p0.WithLaneSize(lane_size_in_bits);
+  __ Ptrue(pg_all_active);
+
+  // Test integer conversions with all lanes actived.
+  __ Scvtf(zd_scvtf_all_active.WithLaneSize(dst_type_size_in_bits),
+           pg_all_active.Merging(),
+           zn.WithLaneSize(src_type_size_in_bits));
+  __ Ucvtf(zd_ucvtf_all_active.WithLaneSize(dst_type_size_in_bits),
+           pg_all_active.Merging(),
+           zn.WithLaneSize(src_type_size_in_bits));
+
+  ZRegister zd_scvtf_merged = z23;
+  ZRegister zd_ucvtf_merged = z24;
+
+  PRegisterWithLaneSize pg_merged = p1.WithLaneSize(lane_size_in_bits);
+  Initialise(&masm, pg_merged, pg_inputs);
+
+  uint64_t snan;
+  switch (lane_size_in_bits) {
+    case kHRegSize:
+      snan = 0x7c11;
+      break;
+    case kSRegSize:
+      snan = 0x7f951111;
+      break;
+    case kDRegSize:
+      snan = 0x7ff5555511111111;
+      break;
+  }
+  __ Dup(zd_scvtf_merged.WithLaneSize(lane_size_in_bits), snan);
+  __ Dup(zd_ucvtf_merged.WithLaneSize(lane_size_in_bits), snan);
+
+  // Use the same `zn` inputs to test integer conversions but some lanes are set
+  // inactive.
+  __ Scvtf(zd_scvtf_merged.WithLaneSize(dst_type_size_in_bits),
+           pg_merged.Merging(),
+           zn.WithLaneSize(src_type_size_in_bits));
+  __ Ucvtf(zd_ucvtf_merged.WithLaneSize(dst_type_size_in_bits),
+           pg_merged.Merging(),
+           zn.WithLaneSize(src_type_size_in_bits));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(expected_zd_scvtf_all_active,
+                     zd_scvtf_all_active.WithLaneSize(lane_size_in_bits));
+    ASSERT_EQUAL_SVE(expected_zd_ucvtf_all_active,
+                     zd_ucvtf_all_active.WithLaneSize(lane_size_in_bits));
+
+    uint64_t expected_zd_scvtf_merged[N];
+    for (size_t i = 0; i < N; i++) {
+      expected_zd_scvtf_merged[i] =
+          pg_inputs[i] ? expected_zd_scvtf_all_active[i] : snan;
+    }
+    ASSERT_EQUAL_SVE(expected_zd_scvtf_merged,
+                     zd_scvtf_merged.WithLaneSize(lane_size_in_bits));
+
+    uint64_t expected_zd_ucvtf_merged[N];
+    for (size_t i = 0; i < N; i++) {
+      expected_zd_ucvtf_merged[i] =
+          pg_inputs[i] ? expected_zd_ucvtf_all_active[i] : snan;
+    }
+    ASSERT_EQUAL_SVE(expected_zd_ucvtf_merged,
+                     zd_ucvtf_merged.WithLaneSize(lane_size_in_bits));
+  }
+}
+
+TEST_SVE(scvtf_ucvtf_h_s_d_to_float16) {
+  // clang-format off
+  CvtfTestDataSet data_set_1[] = {
+    // Simple conversions of positive numbers which require no rounding; the
+    // results should not depened on the rounding mode, and ucvtf and scvtf should
+    // produce the same result.
+    {0x0000, 0x0000, 0x0000},
+    {0x0001, 0x3c00, 0x3c00},
+    {0x0010, 0x4c00, 0x4c00},
+    {0x0080, 0x5800, 0x5800},
+    {0x0400, 0x6400, 0x6400},
+    // Conversions which require rounding.
+    {0x4000, 0x7400, 0x7400},
+    {0x4001, 0x7400, 0x7400},
+    // Round up to produce a result that's too big for the input to represent.
+    {0x7ff0, 0x77ff, 0x77ff},
+    {0x7ff1, 0x77ff, 0x77ff},
+    {0x7ffe, 0x7800, 0x7800},
+    {0x7fff, 0x7800, 0x7800}};
+  int pg_1[] = {1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1};
+  TestUScvtfHelper(config, kHRegSize, kDRegSize, pg_1, data_set_1);
+  TestUScvtfHelper(config, kHRegSize, kSRegSize, pg_1, data_set_1);
+  TestUScvtfHelper(config, kHRegSize, kHRegSize, pg_1, data_set_1);
+
+  CvtfTestDataSet data_set_2[] = {
+    // Test mantissa extremities.
+    {0x0401, 0x6401, 0x6401},
+    {0x4020, 0x7402, 0x7402},
+    // The largest int16_t that fits in a float16.
+    {0xffef, 0xcc40, 0x7bff},
+    // Values that would be negative if treated as an int16_t.
+    {0xff00, 0xdc00, 0x7bf8},
+    {0x8000, 0xf800, 0x7800},
+    {0x8100, 0xf7f0, 0x7808},
+    // Check for bit pattern reproduction.
+    {0x0123, 0x5c8c, 0x5c8c},
+    {0x0cde, 0x6a6f, 0x6a6f},
+    // Simple conversions of negative int64_t values. These require no rounding,
+    // and the results should not depend on the rounding mode.
+    {0xf800, 0xe800, 0x7bc0},
+    {0xfc00, 0xe400, 0x7be0},
+    {0xc000, 0xf400, 0x7a00},
+    // Check rounding of negative int16_t values.
+    {0x8ffe, 0xf700, 0x7880},
+    {0x8fff, 0xf700, 0x7880},
+    {0xffee, 0xcc80, 0x7bff},
+    {0xffef, 0xcc40, 0x7bff}};
+  int pg_2[] = {1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1, 0, 1, 1, 1};
+  // `32-bit to float16` and `64-bit to float16` of above tests has been tested
+  // in `ucvtf` of `16-bit to float16`.
+  TestUScvtfHelper(config, kHRegSize, kHRegSize, pg_2, data_set_2);
+  // clang-format on
+}
+
+TEST_SVE(scvtf_ucvtf_s_to_float) {
+  // clang-format off
+  int dst_lane_size = kSRegSize;
+  int src_lane_size = kSRegSize;
+
+  // Simple conversions of positive numbers which require no rounding; the
+  // results should not depened on the rounding mode, and ucvtf and scvtf should
+  // produce the same result.
+  CvtfTestDataSet data_set_1[] = {
+    {0x00000000, 0x00000000, 0x00000000},
+    {0x00000001, 0x3f800000, 0x3f800000},
+    {0x00004000, 0x46800000, 0x46800000},
+    {0x00010000, 0x47800000, 0x47800000},
+    {0x40000000, 0x4e800000, 0x4e800000}};
+  int pg_1[] = {1, 0, 1, 0, 0};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_1, data_set_1);
+
+  CvtfTestDataSet data_set_2[] = {
+    // Test mantissa extremities.
+    {0x00800001, 0x4b000001, 0x4b000001},
+    {0x40400000, 0x4e808000, 0x4e808000},
+    // The largest int32_t that fits in a double.
+    {0x7fffff80, 0x4effffff, 0x4effffff},
+    // Values that would be negative if treated as an int32_t.
+    {0xffffffff, 0xbf800000, 0x4f800000},
+    {0xffffff00, 0xc3800000, 0x4f7fffff},
+    {0x80000000, 0xcf000000, 0x4f000000},
+    {0x80000001, 0xcf000000, 0x4f000000},
+    // Check for bit pattern reproduction.
+    {0x089abcde, 0x4d09abce, 0x4d09abce},
+    {0x12345678, 0x4d91a2b4, 0x4d91a2b4}};
+  int pg_2[] = {1, 0, 1, 0, 1, 1, 1, 0, 0};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_2, data_set_2);
+
+  // Simple conversions of negative int32_t values. These require no rounding,
+  // and the results should not depend on the rounding mode.
+  CvtfTestDataSet data_set_3[] = {
+    {0xffffc000, 0xc6800000, 0x4f7fffc0},
+    {0xffff0000, 0xc7800000, 0x4f7fff00},
+    {0xc0000000, 0xce800000, 0x4f400000},
+    // Conversions which require rounding.
+    {0x72800000, 0x4ee50000, 0x4ee50000},
+    {0x72800001, 0x4ee50000, 0x4ee50000},
+    {0x73000000, 0x4ee60000, 0x4ee60000},
+    // Check rounding of negative int32_t values.
+    {0x80000140, 0xcefffffe, 0x4f000001},
+    {0x80000141, 0xcefffffd, 0x4f000001},
+    {0x80000180, 0xcefffffd, 0x4f000002},
+    // Round up to produce a result that's too big for the input to represent.
+    {0x7fffffc0, 0x4f000000, 0x4f000000},
+    {0x7fffffff, 0x4f000000, 0x4f000000}};
+  int pg_3[] = {1, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_3, data_set_3);
+  // clang-format on
+}
+
+TEST_SVE(scvtf_ucvtf_d_to_float) {
+  // clang-format off
+  int dst_lane_size = kSRegSize;
+  int src_lane_size = kDRegSize;
+
+  // Simple conversions of positive numbers which require no rounding; the
+  // results should not depened on the rounding mode, and ucvtf and scvtf should
+  // produce the same result.
+  CvtfTestDataSet data_set_1[] = {
+    {0x0000000000000000, 0x00000000, 0x00000000},
+    {0x0000000000000001, 0x3f800000, 0x3f800000},
+    {0x0000000040000000, 0x4e800000, 0x4e800000},
+    {0x0000000100000000, 0x4f800000, 0x4f800000},
+    {0x4000000000000000, 0x5e800000, 0x5e800000}};
+  int pg_1[] = {1, 1, 0, 1, 0};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_1, data_set_1);
+
+  CvtfTestDataSet data_set_2[] = {
+    // Test mantissa extremities.
+    {0x0010000000000001, 0x59800000, 0x59800000},
+    {0x4008000000000000, 0x5e801000, 0x5e801000},
+    // The largest int32_t that fits in a float.
+    {0x000000007fffff80, 0x4effffff, 0x4effffff},
+    // Values that would be negative if treated as an int32_t.
+    {0x00000000ffffffff, 0x4f800000, 0x4f800000},
+    {0x00000000ffffff00, 0x4f7fffff, 0x4f7fffff},
+    {0x0000000080000000, 0x4f000000, 0x4f000000},
+    {0x0000000080000100, 0x4f000001, 0x4f000001},
+    // The largest int64_t that fits in a float.
+    {0x7fffff8000000000, 0x5effffff, 0x5effffff},
+    // Check for bit pattern reproduction.
+    {0x0123456789abcde0, 0x5b91a2b4, 0x5b91a2b4},
+    {0x0000000000876543, 0x4b076543, 0x4b076543}};
+  int pg_2[] = {1, 0, 0, 0, 1, 0, 0, 0, 0, 1};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_2, data_set_2);
+
+  CvtfTestDataSet data_set_3[] = {
+    // Simple conversions of negative int64_t values. These require no rounding,
+    // and the results should not depend on the rounding mode.
+    {0xffffffffc0000000, 0xce800000, 0x5f800000},
+    {0xffffffff00000000, 0xcf800000, 0x5f800000},
+    {0xc000000000000000, 0xde800000, 0x5f400000},
+    // Conversions which require rounding.
+    {0x0000800002800000, 0x57000002, 0x57000002},
+    {0x0000800002800001, 0x57000003, 0x57000003},
+    {0x0000800003000000, 0x57000003, 0x57000003},
+    // Check rounding of negative int64_t values.
+    {0x8000014000000000, 0xdefffffe, 0x5f000001},
+    {0x8000014000000001, 0xdefffffd, 0x5f000001},
+    {0x8000018000000000, 0xdefffffd, 0x5f000002},
+    // Round up to produce a result that's too big for the input to represent.
+    {0x00000000ffffff80, 0x4f800000, 0x4f800000},
+    {0x00000000ffffffff, 0x4f800000, 0x4f800000},
+    {0xffffff8000000000, 0xd3000000, 0x5f800000},
+    {0xffffffffffffffff, 0xbf800000, 0x5f800000}};
+  int pg_3[] = {0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 1};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_3, data_set_3);
+  // clang-format on
+}
+
+TEST_SVE(scvtf_ucvtf_d_to_double) {
+  // clang-format off
+  int dst_lane_size = kDRegSize;
+  int src_lane_size = kDRegSize;
+
+  // Simple conversions of positive numbers which require no rounding; the
+  // results should not depened on the rounding mode, and ucvtf and scvtf should
+  // produce the same result.
+  CvtfTestDataSet data_set_1[] = {
+    {0x0000000000000000, 0x0000000000000000, 0x0000000000000000},
+    {0x0000000000000001, 0x3ff0000000000000, 0x3ff0000000000000},
+    {0x0000000040000000, 0x41d0000000000000, 0x41d0000000000000},
+    {0x0000000100000000, 0x41f0000000000000, 0x41f0000000000000},
+    {0x4000000000000000, 0x43d0000000000000, 0x43d0000000000000}};
+  int pg_1[] = {0, 1, 1, 0, 0};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_1, data_set_1);
+
+  CvtfTestDataSet data_set_2[] = {
+    // Test mantissa extremities.
+    {0x0010000000000001, 0x4330000000000001, 0x4330000000000001},
+    {0x4008000000000000, 0x43d0020000000000, 0x43d0020000000000},
+    // The largest int32_t that fits in a double.
+    {0x000000007fffffff, 0x41dfffffffc00000, 0x41dfffffffc00000},
+    // Values that would be negative if treated as an int32_t.
+    {0x00000000ffffffff, 0x41efffffffe00000, 0x41efffffffe00000},
+    {0x0000000080000000, 0x41e0000000000000, 0x41e0000000000000},
+    {0x0000000080000001, 0x41e0000000200000, 0x41e0000000200000},
+    // The largest int64_t that fits in a double.
+    {0x7ffffffffffffc00, 0x43dfffffffffffff, 0x43dfffffffffffff},
+    // Check for bit pattern reproduction.
+    {0x0123456789abcde0, 0x43723456789abcde, 0x43723456789abcde},
+    {0x0000000012345678, 0x41b2345678000000, 0x41b2345678000000}};
+  int pg_2[] = {1, 1, 1, 1, 1, 0, 0, 0, 0};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_2, data_set_2);
+
+  CvtfTestDataSet data_set_3[] = {
+    // Simple conversions of negative int64_t values. These require no rounding,
+    // and the results should not depend on the rounding mode.
+    {0xffffffffc0000000, 0xc1d0000000000000, 0x43effffffff80000},
+    {0xffffffff00000000, 0xc1f0000000000000, 0x43efffffffe00000},
+    {0xc000000000000000, 0xc3d0000000000000, 0x43e8000000000000},
+    // Conversions which require rounding.
+    {0x1000000000000280, 0x43b0000000000002, 0x43b0000000000002},
+    {0x1000000000000281, 0x43b0000000000003, 0x43b0000000000003},
+    {0x1000000000000300, 0x43b0000000000003, 0x43b0000000000003},
+    // Check rounding of negative int64_t values.
+    {0x8000000000000a00, 0xc3dffffffffffffe, 0x43e0000000000001},
+    {0x8000000000000a01, 0xc3dffffffffffffd, 0x43e0000000000001},
+    {0x8000000000000c00, 0xc3dffffffffffffd, 0x43e0000000000002},
+    // Round up to produce a result that's too big for the input to represent.
+    {0x7ffffffffffffe00, 0x43e0000000000000, 0x43e0000000000000},
+    {0x7fffffffffffffff, 0x43e0000000000000, 0x43e0000000000000},
+    {0xfffffffffffffc00, 0xc090000000000000, 0x43f0000000000000},
+    {0xffffffffffffffff, 0xbff0000000000000, 0x43f0000000000000}};
+  int pg_3[] = {1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_3, data_set_3);
+  // clang-format on
+}
+
+TEST_SVE(scvtf_ucvtf_s_to_double) {
+  // clang-format off
+  int dst_lane_size = kDRegSize;
+  int src_lane_size = kSRegSize;
+
+  // Simple conversions of positive numbers which require no rounding; the
+  // results should not depened on the rounding mode, and ucvtf and scvtf should
+  // produce the same result.
+  CvtfTestDataSet data_set_1[] = {
+    {0x00000000, 0x0000000000000000, 0x0000000000000000},
+    {0x00000001, 0x3ff0000000000000, 0x3ff0000000000000},
+    {0x00004000, 0x40d0000000000000, 0x40d0000000000000},
+    {0x00010000, 0x40f0000000000000, 0x40f0000000000000},
+    {0x40000000, 0x41d0000000000000, 0x41d0000000000000}};
+  int pg_1[] = {1, 0, 0, 0, 1};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_1, data_set_1);
+
+  CvtfTestDataSet data_set_2[] = {
+    // Test mantissa extremities.
+    {0x40000400, 0x41d0000100000000, 0x41d0000100000000},
+    // The largest int32_t that fits in a double.
+    {0x7fffffff, 0x41dfffffffc00000, 0x41dfffffffc00000},
+    // Values that would be negative if treated as an int32_t.
+    {0xffffffff, 0xbff0000000000000, 0x41efffffffe00000},
+    {0x80000000, 0xc1e0000000000000, 0x41e0000000000000},
+    {0x80000001, 0xc1dfffffffc00000, 0x41e0000000200000},
+    // Check for bit pattern reproduction.
+    {0x089abcde, 0x41a13579bc000000, 0x41a13579bc000000},
+    {0x12345678, 0x41b2345678000000, 0x41b2345678000000},
+    // Simple conversions of negative int32_t values. These require no rounding,
+    // and the results should not depend on the rounding mode.
+    {0xffffc000, 0xc0d0000000000000, 0x41effff800000000},
+    {0xffff0000, 0xc0f0000000000000, 0x41efffe000000000},
+    {0xc0000000, 0xc1d0000000000000, 0x41e8000000000000}};
+  int pg_2[] = {1, 0, 1, 0, 0, 1, 1, 0, 1, 1};
+  TestUScvtfHelper(config, dst_lane_size, src_lane_size, pg_2, data_set_2);
+
+  // Note that IEEE 754 double-precision format has 52-bits fraction, so all
+  // 32-bits integers are representable in double.
+  // clang-format on
+}
+
+TEST_SVE(sve_fadda) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE,
+                          CPUFeatures::kFP,
+                          CPUFeatures::kFPHalf);
+  START();
+
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p1.VnH(), p0.VnH(), p1.VnH());
+
+  __ Index(z0.VnS(), 3, 3);
+  __ Scvtf(z0.VnS(), p0.Merging(), z0.VnS());
+  __ Fmov(s2, 2.0);
+  __ Fadda(s2, p0, s2, z0.VnS());
+
+  __ Index(z0.VnD(), -7, -7);
+  __ Scvtf(z0.VnD(), p0.Merging(), z0.VnD());
+  __ Fmov(d3, 3.0);
+  __ Fadda(d3, p0, d3, z0.VnD());
+
+  __ Index(z0.VnH(), 1, 1);
+  __ Scvtf(z0.VnH(), p0.Merging(), z0.VnH());
+  __ Fmov(h4, 0);
+  __ Fadda(h4, p1, h4, z0.VnH());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    // Sum of 1 .. n is n+1 * n/2, ie. n(n+1)/2.
+    int n = core.GetSVELaneCount(kSRegSize);
+    ASSERT_EQUAL_FP32(2 + 3 * ((n + 1) * (n / 2)), s2);
+
+    n /= 2;  // Half as many lanes.
+    ASSERT_EQUAL_FP64(3 + -7 * ((n + 1) * (n / 2)), d3);
+
+    // Sum of first n odd numbers is n^2.
+    n = core.GetSVELaneCount(kHRegSize) / 2;  // Half are odd numbers.
+    ASSERT_EQUAL_FP16(Float16(n * n), h4);
+  }
+}
+
+TEST_SVE(sve_extract) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Index(z0.VnB(), 0, 1);
+
+  __ Mov(z1, z0);
+  __ Mov(z2, z0);
+  __ Mov(z3, z0);
+  __ Mov(z4, z0);
+  __ Mov(z5, z0);
+  __ Mov(z6, z0);
+
+  __ Ext(z1, z1, z0, 0);
+  __ Ext(z2, z2, z0, 1);
+  __ Ext(z3, z3, z0, 15);
+  __ Ext(z4, z4, z0, 31);
+  __ Ext(z5, z5, z0, 47);
+  __ Ext(z6, z6, z0, 255);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(z1, z0);
+
+    int lane_count = core.GetSVELaneCount(kBRegSize);
+    if (lane_count == 16) {
+      uint64_t z2_expected[] = {0x000f0e0d0c0b0a09, 0x0807060504030201};
+      ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+    } else {
+      uint64_t z2_expected[] = {0x100f0e0d0c0b0a09, 0x0807060504030201};
+      ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+    }
+
+    if (lane_count == 16) {
+      uint64_t z3_expected[] = {0x0e0d0c0b0a090807, 0x060504030201000f};
+      ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    } else {
+      uint64_t z3_expected[] = {0x1e1d1c1b1a191817, 0x161514131211100f};
+      ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    }
+
+    if (lane_count < 32) {
+      ASSERT_EQUAL_SVE(z4, z0);
+    } else if (lane_count == 32) {
+      uint64_t z4_expected[] = {0x0e0d0c0b0a090807, 0x060504030201001f};
+      ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+    } else {
+      uint64_t z4_expected[] = {0x2e2d2c2b2a292827, 0x262524232221201f};
+      ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+    }
+
+    if (lane_count < 48) {
+      ASSERT_EQUAL_SVE(z5, z0);
+    } else if (lane_count == 48) {
+      uint64_t z5_expected[] = {0x0e0d0c0b0a090807, 0x060504030201002f};
+      ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    } else {
+      uint64_t z5_expected[] = {0x3e3d3c3b3a393837, 0x363534333231302f};
+      ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    }
+
+    if (lane_count < 256) {
+      ASSERT_EQUAL_SVE(z6, z0);
+    } else {
+      uint64_t z6_expected[] = {0x0e0d0c0b0a090807, 0x06050403020100ff};
+      ASSERT_EQUAL_SVE(z6_expected, z6.VnD());
+    }
+  }
+}
+
+TEST_SVE(sve_fp_paired_across) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+
+  __ Ptrue(p0.VnB());
+  __ Pfalse(p1.VnB());
+  __ Zip1(p2.VnS(), p0.VnS(), p1.VnS());
+  __ Zip1(p3.VnD(), p0.VnD(), p1.VnD());
+  __ Zip1(p4.VnH(), p0.VnH(), p1.VnH());
+
+  __ Index(z0.VnS(), 3, 3);
+  __ Scvtf(z0.VnS(), p0.Merging(), z0.VnS());
+  __ Faddv(s1, p0, z0.VnS());
+  __ Fminv(s2, p2, z0.VnS());
+  __ Fmaxv(s3, p2, z0.VnS());
+
+  __ Index(z0.VnD(), -7, -7);
+  __ Scvtf(z0.VnD(), p0.Merging(), z0.VnD());
+  __ Faddv(d4, p0, z0.VnD());
+  __ Fminv(d5, p3, z0.VnD());
+  __ Fmaxv(d6, p3, z0.VnD());
+
+  __ Index(z0.VnH(), 1, 1);
+  __ Scvtf(z0.VnH(), p0.Merging(), z0.VnH());
+  __ Faddv(h7, p4, z0.VnH());
+  __ Fminv(h8, p4, z0.VnH());
+  __ Fmaxv(h9, p4, z0.VnH());
+
+  __ Dup(z10.VnH(), 0);
+  __ Fdiv(z10.VnH(), p0.Merging(), z10.VnH(), z10.VnH());
+  __ Insr(z10.VnH(), 0x5140);
+  __ Insr(z10.VnH(), 0xd140);
+  __ Ext(z10.VnB(), z10.VnB(), z10.VnB(), 2);
+  __ Fmaxnmv(h11, p0, z10.VnH());
+  __ Fmaxnmv(h12, p4, z10.VnH());
+  __ Fminnmv(h13, p0, z10.VnH());
+  __ Fminnmv(h14, p4, z10.VnH());
+
+  __ Dup(z10.VnS(), 0);
+  __ Fdiv(z10.VnS(), p0.Merging(), z10.VnS(), z10.VnS());
+  __ Insr(z10.VnS(), 0x42280000);
+  __ Insr(z10.VnS(), 0xc2280000);
+  __ Ext(z10.VnB(), z10.VnB(), z10.VnB(), 4);
+  __ Fmaxnmv(s15, p0, z10.VnS());
+  __ Fmaxnmv(s16, p2, z10.VnS());
+  __ Fminnmv(s17, p0, z10.VnS());
+  __ Fminnmv(s18, p2, z10.VnS());
+
+  __ Dup(z10.VnD(), 0);
+  __ Fdiv(z10.VnD(), p0.Merging(), z10.VnD(), z10.VnD());
+  __ Insr(z10.VnD(), 0x4045000000000000);
+  __ Insr(z10.VnD(), 0xc045000000000000);
+  __ Ext(z10.VnB(), z10.VnB(), z10.VnB(), 8);
+  __ Fmaxnmv(d19, p0, z10.VnD());
+  __ Fmaxnmv(d20, p3, z10.VnD());
+  __ Fminnmv(d21, p0, z10.VnD());
+  __ Fminnmv(d22, p3, z10.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    // Sum of 1 .. n is n+1 * n/2, ie. n(n+1)/2.
+    int n = core.GetSVELaneCount(kSRegSize);
+    ASSERT_EQUAL_FP32(3 * ((n + 1) * (n / 2)), s1);
+    ASSERT_EQUAL_FP32(3, s2);
+    ASSERT_EQUAL_FP32(3 * n - 3, s3);
+
+    n /= 2;  // Half as many lanes.
+    ASSERT_EQUAL_FP64(-7 * ((n + 1) * (n / 2)), d4);
+    ASSERT_EQUAL_FP64(-7 * (n - 1), d5);
+    ASSERT_EQUAL_FP64(-7, d6);
+
+    // Sum of first n odd numbers is n^2.
+    n = core.GetSVELaneCount(kHRegSize) / 2;  // Half are odd numbers.
+    ASSERT_EQUAL_FP16(Float16(n * n), h7);
+    ASSERT_EQUAL_FP16(Float16(1), h8);
+
+    n = core.GetSVELaneCount(kHRegSize);
+    ASSERT_EQUAL_FP16(Float16(n - 1), h9);
+
+    ASSERT_EQUAL_FP16(Float16(42), h11);
+    ASSERT_EQUAL_FP16(Float16(42), h12);
+    ASSERT_EQUAL_FP16(Float16(-42), h13);
+    ASSERT_EQUAL_FP16(Float16(42), h14);
+    ASSERT_EQUAL_FP32(42, s15);
+    ASSERT_EQUAL_FP32(42, s16);
+    ASSERT_EQUAL_FP32(-42, s17);
+    ASSERT_EQUAL_FP32(42, s18);
+    ASSERT_EQUAL_FP64(42, d19);
+    ASSERT_EQUAL_FP64(42, d20);
+    ASSERT_EQUAL_FP64(-42, d21);
+    ASSERT_EQUAL_FP64(42, d22);
+  }
+}
+
+TEST_SVE(sve_frecpe_frsqrte) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+
+  __ Ptrue(p0.VnB());
+
+  __ Index(z0.VnH(), 0, 1);
+  __ Fdup(z1.VnH(), Float16(1));
+  __ Fscale(z1.VnH(), p0.Merging(), z1.VnH(), z0.VnH());
+  __ Insr(z1.VnH(), 0);
+  __ Frsqrte(z2.VnH(), z1.VnH());
+  __ Frecpe(z1.VnH(), z1.VnH());
+
+  __ Index(z0.VnS(), 0, 1);
+  __ Fdup(z3.VnS(), Float16(1));
+  __ Fscale(z3.VnS(), p0.Merging(), z3.VnS(), z0.VnS());
+  __ Insr(z3.VnS(), 0);
+  __ Frsqrte(z4.VnS(), z3.VnS());
+  __ Frecpe(z3.VnS(), z3.VnS());
+
+  __ Index(z0.VnD(), 0, 1);
+  __ Fdup(z5.VnD(), Float16(1));
+  __ Fscale(z5.VnD(), p0.Merging(), z5.VnD(), z0.VnD());
+  __ Insr(z5.VnD(), 0);
+  __ Frsqrte(z6.VnD(), z5.VnD());
+  __ Frecpe(z5.VnD(), z5.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t z1_expected[] = {0x23fc27fc2bfc2ffc, 0x33fc37fc3bfc7c00};
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+    uint64_t z2_expected[] = {0x2ffc31a433fc35a4, 0x37fc39a43bfc7c00};
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+
+    uint64_t z3_expected[] = {0x3e7f80003eff8000, 0x3f7f80007f800000};
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    uint64_t z4_expected[] = {0x3eff80003f348000, 0x3f7f80007f800000};
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+
+    uint64_t z5_expected[] = {0x3feff00000000000, 0x7ff0000000000000};
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    uint64_t z6_expected[] = {0x3feff00000000000, 0x7ff0000000000000};
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnD());
+  }
+}
+
+TEST_SVE(sve_frecps_frsqrts) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+  __ Ptrue(p0.VnB());
+
+  __ Index(z0.VnH(), 0, -1);
+  __ Fdup(z1.VnH(), Float16(1));
+  __ Fscale(z1.VnH(), p0.Merging(), z1.VnH(), z0.VnH());
+  __ Scvtf(z0.VnH(), p0.Merging(), z0.VnH());
+  __ Insr(z1.VnH(), 0);
+  __ Frsqrts(z2.VnH(), z1.VnH(), z0.VnH());
+  __ Frecps(z1.VnH(), z1.VnH(), z0.VnH());
+
+  __ Index(z0.VnS(), 0, -1);
+  __ Fdup(z3.VnS(), Float16(1));
+  __ Fscale(z3.VnS(), p0.Merging(), z3.VnS(), z0.VnS());
+  __ Scvtf(z0.VnS(), p0.Merging(), z0.VnS());
+  __ Insr(z3.VnS(), 0);
+  __ Frsqrts(z4.VnS(), z3.VnS(), z0.VnS());
+  __ Frecps(z3.VnS(), z3.VnS(), z0.VnS());
+
+  __ Index(z0.VnD(), 0, -1);
+  __ Fdup(z5.VnD(), Float16(1));
+  __ Fscale(z5.VnD(), p0.Merging(), z5.VnD(), z0.VnD());
+  __ Scvtf(z0.VnD(), p0.Merging(), z0.VnD());
+  __ Insr(z5.VnD(), 0);
+  __ Frsqrts(z6.VnD(), z5.VnD(), z0.VnD());
+  __ Frecps(z5.VnD(), z5.VnD(), z0.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t z1_expected[] = {0x4038406040a04100, 0x4180420042004000};
+    ASSERT_EQUAL_SVE(z1_expected, z1.VnD());
+    uint64_t z2_expected[] = {0x3e383e603ea03f00, 0x3f80400040003e00};
+    ASSERT_EQUAL_SVE(z2_expected, z2.VnD());
+
+    uint64_t z3_expected[] = {0x4030000040400000, 0x4040000040000000};
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    uint64_t z4_expected[] = {0x3ff0000040000000, 0x400000003fc00000};
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+
+    uint64_t z5_expected[] = {0x4008000000000000, 0x4000000000000000};
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    uint64_t z6_expected[] = {0x4000000000000000, 0x3ff8000000000000};
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnD());
+  }
+}
+
+TEST_SVE(sve_ftsmul) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+  __ Ptrue(p0.VnB());
+
+  __ Index(z0.VnH(), 0, 1);
+  __ Rev(z1.VnH(), z0.VnH());
+  __ Scvtf(z0.VnH(), p0.Merging(), z0.VnH());
+  __ Dup(z2.VnH(), 0);
+  __ Fdiv(z2.VnH(), p0.Merging(), z2.VnH(), z2.VnH());
+  __ Ftsmul(z3.VnH(), z0.VnH(), z1.VnH());
+  __ Ftsmul(z4.VnH(), z2.VnH(), z1.VnH());
+
+  __ Index(z0.VnS(), -7, 1);
+  __ Rev(z1.VnS(), z0.VnS());
+  __ Scvtf(z0.VnS(), p0.Merging(), z0.VnS());
+  __ Dup(z2.VnS(), 0);
+  __ Fdiv(z2.VnS(), p0.Merging(), z2.VnS(), z2.VnS());
+  __ Ftsmul(z5.VnS(), z0.VnS(), z1.VnS());
+  __ Ftsmul(z6.VnS(), z2.VnS(), z1.VnS());
+
+  __ Index(z0.VnD(), 2, -1);
+  __ Rev(z1.VnD(), z0.VnD());
+  __ Scvtf(z0.VnD(), p0.Merging(), z0.VnD());
+  __ Dup(z2.VnD(), 0);
+  __ Fdiv(z2.VnD(), p0.Merging(), z2.VnD(), z2.VnD());
+  __ Ftsmul(z7.VnD(), z0.VnD(), z1.VnD());
+  __ Ftsmul(z8.VnD(), z2.VnD(), z1.VnD());
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t z3_expected[] = {0x5220d0804e40cc00, 0x4880c4003c008000};
+    ASSERT_EQUAL_SVE(z3_expected, z3.VnD());
+    uint64_t z4_expected[] = {0x7e007e007e007e00, 0x7e007e007e007e00};
+    ASSERT_EQUAL_SVE(z4_expected, z4.VnD());
+
+    uint64_t z5_expected[] = {0xc180000041c80000, 0xc210000042440000};
+    ASSERT_EQUAL_SVE(z5_expected, z5.VnD());
+    uint64_t z6_expected[] = {0x7fc000007fc00000, 0x7fc000007fc00000};
+    ASSERT_EQUAL_SVE(z6_expected, z6.VnD());
+
+    uint64_t z7_expected[] = {0x3ff0000000000000, 0xc010000000000000};
+    ASSERT_EQUAL_SVE(z7_expected, z7.VnD());
+    uint64_t z8_expected[] = {0x7ff8000000000000, 0x7ff8000000000000};
+    ASSERT_EQUAL_SVE(z8_expected, z8.VnD());
+  }
+}
+
+typedef void (MacroAssembler::*FPMulAccFn)(
+    const ZRegister& zd,
+    const PRegisterM& pg,
+    const ZRegister& za,
+    const ZRegister& zn,
+    const ZRegister& zm,
+    FPMacroNaNPropagationOption nan_option);
+
+// The `pg_inputs` is used for examining the predication correctness internally.
+// It does not imply the value of `result` argument. `result` stands for the
+// expected result on all-true predication.
+template <typename T, size_t N>
+static void FPMulAccHelper(
+    Test* config,
+    FPMulAccFn macro,
+    unsigned lane_size_in_bits,
+    const int (&pg_inputs)[N],
+    const T (&za_inputs)[N],
+    const T (&zn_inputs)[N],
+    const T (&zm_inputs)[N],
+    const uint64_t (&result)[N],
+    FPMacroNaNPropagationOption nan_option = FastNaNPropagation) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  ZRegister zd = z0.WithLaneSize(lane_size_in_bits);
+  ZRegister za = z1.WithLaneSize(lane_size_in_bits);
+  ZRegister zn = z2.WithLaneSize(lane_size_in_bits);
+  ZRegister zm = z3.WithLaneSize(lane_size_in_bits);
+
+  uint64_t za_rawbits[N];
+  uint64_t zn_rawbits[N];
+  uint64_t zm_rawbits[N];
+
+  FPToRawbitsWithSize(za_inputs, za_rawbits, lane_size_in_bits);
+  FPToRawbitsWithSize(zn_inputs, zn_rawbits, lane_size_in_bits);
+  FPToRawbitsWithSize(zm_inputs, zm_rawbits, lane_size_in_bits);
+
+  InsrHelper(&masm, za, za_rawbits);
+  InsrHelper(&masm, zn, zn_rawbits);
+  InsrHelper(&masm, zm, zm_rawbits);
+
+  // Initialize `zd` with a signalling NaN.
+  uint64_t sn = GetSignallingNan(lane_size_in_bits);
+  __ Mov(x29, sn);
+  __ Dup(zd, x29);
+
+  Initialise(&masm, p0.WithLaneSize(lane_size_in_bits), pg_inputs);
+
+  // Fmla  macro automatically selects between fmla,  fmad  and movprfx + fmla
+  // Fmls                 `ditto`              fmls,  fmsb  and movprfx + fmls
+  // Fnmla                `ditto`              fnmla, fnmad and movprfx + fnmla
+  // Fnmls                `ditto`              fnmls, fnmsb and movprfx + fnmls
+  // based on what registers are aliased.
+  ZRegister da_result = z10.WithLaneSize(lane_size_in_bits);
+  ZRegister dn_result = z11.WithLaneSize(lane_size_in_bits);
+  ZRegister dm_result = z12.WithLaneSize(lane_size_in_bits);
+  ZRegister d_result = z13.WithLaneSize(lane_size_in_bits);
+
+  __ Mov(da_result, za);
+  (masm.*macro)(da_result, p0.Merging(), da_result, zn, zm, nan_option);
+
+  __ Mov(dn_result, zn);
+  (masm.*macro)(dn_result, p0.Merging(), za, dn_result, zm, nan_option);
+
+  __ Mov(dm_result, zm);
+  (masm.*macro)(dm_result, p0.Merging(), za, zn, dm_result, nan_option);
+
+  __ Mov(d_result, zd);
+  (masm.*macro)(d_result, p0.Merging(), za, zn, zm, nan_option);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(za_rawbits, za);
+    ASSERT_EQUAL_SVE(zn_rawbits, zn);
+    ASSERT_EQUAL_SVE(zm_rawbits, zm);
+
+    uint64_t da_expected[N];
+    uint64_t dn_expected[N];
+    uint64_t dm_expected[N];
+    uint64_t d_expected[N];
+    for (size_t i = 0; i < N; i++) {
+      da_expected[i] = ((pg_inputs[i] & 1) != 0) ? result[i] : za_rawbits[i];
+      dn_expected[i] = ((pg_inputs[i] & 1) != 0) ? result[i] : zn_rawbits[i];
+      dm_expected[i] = ((pg_inputs[i] & 1) != 0) ? result[i] : zm_rawbits[i];
+      d_expected[i] = ((pg_inputs[i] & 1) != 0) ? result[i] : sn;
+    }
+
+    ASSERT_EQUAL_SVE(da_expected, da_result);
+    ASSERT_EQUAL_SVE(dn_expected, dn_result);
+    ASSERT_EQUAL_SVE(dm_expected, dm_result);
+    ASSERT_EQUAL_SVE(d_expected, d_result);
+  }
+}
+
+TEST_SVE(sve_fmla_fmad) {
+  // fmla : zd = za + zn * zm
+  double za_inputs[] = {-39.0, 1.0, -3.0, 2.0};
+  double zn_inputs[] = {-5.0, -20.0, 9.0, 8.0};
+  double zm_inputs[] = {9.0, -5.0, 4.0, 5.0};
+  int pg_inputs[] = {1, 1, 0, 1};
+
+  uint64_t fmla_result_h[] = {Float16ToRawbits(Float16(-84.0)),
+                              Float16ToRawbits(Float16(101.0)),
+                              Float16ToRawbits(Float16(33.0)),
+                              Float16ToRawbits(Float16(42.0))};
+
+  // `fmad` has been tested in the helper.
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fmla,
+                 kHRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fmla_result_h);
+
+  uint64_t fmla_result_s[] = {FloatToRawbits(-84.0f),
+                              FloatToRawbits(101.0f),
+                              FloatToRawbits(33.0f),
+                              FloatToRawbits(42.0f)};
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fmla,
+                 kSRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fmla_result_s);
+
+  uint64_t fmla_result_d[] = {DoubleToRawbits(-84.0),
+                              DoubleToRawbits(101.0),
+                              DoubleToRawbits(33.0),
+                              DoubleToRawbits(42.0)};
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fmla,
+                 kDRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fmla_result_d);
+}
+
+TEST_SVE(sve_fmls_fmsb) {
+  // fmls : zd = za - zn * zm
+  double za_inputs[] = {-39.0, 1.0, -3.0, 2.0};
+  double zn_inputs[] = {-5.0, -20.0, 9.0, 8.0};
+  double zm_inputs[] = {9.0, -5.0, 4.0, 5.0};
+  int pg_inputs[] = {1, 0, 1, 1};
+
+  uint64_t fmls_result_h[] = {Float16ToRawbits(Float16(6.0)),
+                              Float16ToRawbits(Float16(-99.0)),
+                              Float16ToRawbits(Float16(-39.0)),
+                              Float16ToRawbits(Float16(-38.0))};
+
+  // `fmsb` has been tested in the helper.
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fmls,
+                 kHRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fmls_result_h);
+
+  uint64_t fmls_result_s[] = {FloatToRawbits(6.0f),
+                              FloatToRawbits(-99.0f),
+                              FloatToRawbits(-39.0f),
+                              FloatToRawbits(-38.0f)};
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fmls,
+                 kSRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fmls_result_s);
+
+  uint64_t fmls_result_d[] = {DoubleToRawbits(6.0),
+                              DoubleToRawbits(-99.0),
+                              DoubleToRawbits(-39.0),
+                              DoubleToRawbits(-38.0)};
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fmls,
+                 kDRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fmls_result_d);
+}
+
+TEST_SVE(sve_fnmla_fnmad) {
+  // fnmla : zd = -za - zn * zm
+  double za_inputs[] = {-39.0, 1.0, -3.0, 2.0};
+  double zn_inputs[] = {-5.0, -20.0, 9.0, 8.0};
+  double zm_inputs[] = {9.0, -5.0, 4.0, 5.0};
+  int pg_inputs[] = {0, 1, 1, 1};
+
+  uint64_t fnmla_result_h[] = {Float16ToRawbits(Float16(84.0)),
+                               Float16ToRawbits(Float16(-101.0)),
+                               Float16ToRawbits(Float16(-33.0)),
+                               Float16ToRawbits(Float16(-42.0))};
+
+  // `fnmad` has been tested in the helper.
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fnmla,
+                 kHRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fnmla_result_h);
+
+  uint64_t fnmla_result_s[] = {FloatToRawbits(84.0f),
+                               FloatToRawbits(-101.0f),
+                               FloatToRawbits(-33.0f),
+                               FloatToRawbits(-42.0f)};
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fnmla,
+                 kSRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fnmla_result_s);
+
+  uint64_t fnmla_result_d[] = {DoubleToRawbits(84.0),
+                               DoubleToRawbits(-101.0),
+                               DoubleToRawbits(-33.0),
+                               DoubleToRawbits(-42.0)};
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fnmla,
+                 kDRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fnmla_result_d);
+}
+
+TEST_SVE(sve_fnmls_fnmsb) {
+  // fnmls : zd = -za + zn * zm
+  double za_inputs[] = {-39.0, 1.0, -3.0, 2.0};
+  double zn_inputs[] = {-5.0, -20.0, 9.0, 8.0};
+  double zm_inputs[] = {9.0, -5.0, 4.0, 5.0};
+  int pg_inputs[] = {1, 1, 1, 0};
+
+  uint64_t fnmls_result_h[] = {Float16ToRawbits(Float16(-6.0)),
+                               Float16ToRawbits(Float16(99.0)),
+                               Float16ToRawbits(Float16(39.0)),
+                               Float16ToRawbits(Float16(38.0))};
+
+  // `fnmsb` has been tested in the helper.
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fnmls,
+                 kHRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fnmls_result_h);
+
+  uint64_t fnmls_result_s[] = {FloatToRawbits(-6.0f),
+                               FloatToRawbits(99.0f),
+                               FloatToRawbits(39.0f),
+                               FloatToRawbits(38.0f)};
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fnmls,
+                 kSRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fnmls_result_s);
+
+  uint64_t fnmls_result_d[] = {DoubleToRawbits(-6.0),
+                               DoubleToRawbits(99.0),
+                               DoubleToRawbits(39.0),
+                               DoubleToRawbits(38.0)};
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fnmls,
+                 kDRegSize,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 fnmls_result_d);
+}
+
+typedef void (MacroAssembler::*FPMulAccIdxFn)(const ZRegister& zd,
+                                              const ZRegister& za,
+                                              const ZRegister& zn,
+                                              const ZRegister& zm,
+                                              int index);
+
+template <typename T, size_t N>
+static void FPMulAccIdxHelper(Test* config,
+                              FPMulAccFn macro,
+                              FPMulAccIdxFn macro_idx,
+                              const T (&za_inputs)[N],
+                              const T (&zn_inputs)[N],
+                              const T (&zm_inputs)[N]) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Ptrue(p0.VnB());
+
+  // Repeat indexed vector across up to 2048-bit VL.
+  for (size_t i = 0; i < (kZRegMaxSize / kDRegSize); i += N) {
+    InsrHelper(&masm, z30.VnD(), zm_inputs);
+  }
+
+  FPSegmentPatternHelper(&masm, z0.VnH(), p0.Merging(), z30.VnH());
+
+  InsrHelper(&masm, z1.VnD(), zn_inputs);
+  InsrHelper(&masm, z2.VnD(), za_inputs);
+
+  __ Mov(z3, z0);
+  (masm.*macro_idx)(z3.VnH(), z2.VnH(), z1.VnH(), z3.VnH(), 0);  // zd == zm
+  __ Mov(z4, z1);
+  (masm.*macro_idx)(z4.VnH(), z2.VnH(), z4.VnH(), z0.VnH(), 1);  // zd == zn
+  __ Mov(z5, z2);
+  (masm.*macro_idx)(z5.VnH(), z5.VnH(), z1.VnH(), z0.VnH(), 4);  // zd == za
+  (masm.*macro_idx)(z6.VnH(), z2.VnH(), z1.VnH(), z0.VnH(), 7);
+
+  FPSegmentPatternHelper(&masm, z0.VnS(), p0.Merging(), z30.VnS());
+
+  __ Mov(z7, z0);
+  (masm.*macro_idx)(z7.VnS(), z2.VnS(), z1.VnS(), z7.VnS(), 0);  // zd == zm
+  __ Mov(z8, z1);
+  (masm.*macro_idx)(z8.VnS(), z2.VnS(), z8.VnS(), z0.VnS(), 1);  // zd == zn
+  __ Mov(z9, z2);
+  (masm.*macro_idx)(z9.VnS(), z9.VnS(), z1.VnS(), z0.VnS(), 2);  // zd == za
+  (masm.*macro_idx)(z10.VnS(), z2.VnS(), z1.VnS(), z0.VnS(), 3);
+
+  FPSegmentPatternHelper(&masm, z0.VnD(), p0.Merging(), z30.VnD());
+
+  __ Mov(z11, z0);
+  (masm.*macro_idx)(z11.VnD(), z2.VnD(), z1.VnD(), z11.VnD(), 0);  // zd == zm
+  __ Mov(z12, z1);
+  (masm.*macro_idx)(z12.VnD(), z2.VnD(), z12.VnD(), z0.VnD(), 1);  // zd == zn
+  __ Mov(z13, z2);
+  (masm.*macro_idx)(z13.VnD(), z13.VnD(), z1.VnD(), z0.VnD(), 0);  // zd == za
+  __ Mov(z14, z0);
+  // zd == zn == zm
+  (masm.*macro_idx)(z14.VnD(), z2.VnD(), z14.VnD(), z14.VnD(), 1);
+
+  // Indexed form of Fmla and Fmls won't swap argument, passing strict NaN
+  // propagation mode to ensure the following macros don't swap argument in
+  // any cases.
+  FPMacroNaNPropagationOption option = StrictNaNPropagation;
+  // Compute the results using other instructions.
+  __ Dup(z0.VnH(), z30.VnH(), 0);
+  FPSegmentPatternHelper(&masm, z0.VnH(), p0.Merging(), z0.VnH());
+  (masm.*macro)(z15.VnH(), p0.Merging(), z2.VnH(), z1.VnH(), z0.VnH(), option);
+  __ Dup(z0.VnH(), z30.VnH(), 1);
+  FPSegmentPatternHelper(&masm, z0.VnH(), p0.Merging(), z0.VnH());
+  (masm.*macro)(z16.VnH(), p0.Merging(), z2.VnH(), z1.VnH(), z0.VnH(), option);
+  __ Dup(z0.VnH(), z30.VnH(), 4);
+  FPSegmentPatternHelper(&masm, z0.VnH(), p0.Merging(), z0.VnH());
+  (masm.*macro)(z17.VnH(), p0.Merging(), z2.VnH(), z1.VnH(), z0.VnH(), option);
+  __ Dup(z0.VnH(), z30.VnH(), 7);
+  FPSegmentPatternHelper(&masm, z0.VnH(), p0.Merging(), z0.VnH());
+  (masm.*macro)(z18.VnH(), p0.Merging(), z2.VnH(), z1.VnH(), z0.VnH(), option);
+
+  __ Dup(z0.VnS(), z30.VnS(), 0);
+  FPSegmentPatternHelper(&masm, z0.VnS(), p0.Merging(), z0.VnS());
+  (masm.*macro)(z19.VnS(), p0.Merging(), z2.VnS(), z1.VnS(), z0.VnS(), option);
+  __ Dup(z0.VnS(), z30.VnS(), 1);
+  FPSegmentPatternHelper(&masm, z0.VnS(), p0.Merging(), z0.VnS());
+  (masm.*macro)(z20.VnS(), p0.Merging(), z2.VnS(), z1.VnS(), z0.VnS(), option);
+  __ Dup(z0.VnS(), z30.VnS(), 2);
+  FPSegmentPatternHelper(&masm, z0.VnS(), p0.Merging(), z0.VnS());
+  (masm.*macro)(z21.VnS(), p0.Merging(), z2.VnS(), z1.VnS(), z0.VnS(), option);
+  __ Dup(z0.VnS(), z30.VnS(), 3);
+  FPSegmentPatternHelper(&masm, z0.VnS(), p0.Merging(), z0.VnS());
+  (masm.*macro)(z22.VnS(), p0.Merging(), z2.VnS(), z1.VnS(), z0.VnS(), option);
+
+  __ Dup(z0.VnD(), z30.VnD(), 0);
+  FPSegmentPatternHelper(&masm, z0.VnD(), p0.Merging(), z0.VnD());
+  (masm.*macro)(z23.VnD(), p0.Merging(), z2.VnD(), z1.VnD(), z0.VnD(), option);
+  __ Dup(z0.VnD(), z30.VnD(), 1);
+  FPSegmentPatternHelper(&masm, z0.VnD(), p0.Merging(), z0.VnD());
+  (masm.*macro)(z24.VnD(), p0.Merging(), z2.VnD(), z1.VnD(), z0.VnD(), option);
+  FPSegmentPatternHelper(&masm, z0.VnD(), p0.Merging(), z30.VnD());
+  __ Dup(z29.VnD(), z30.VnD(), 1);
+  FPSegmentPatternHelper(&masm, z29.VnD(), p0.Merging(), z29.VnD());
+  (masm.*macro)(z25.VnD(), p0.Merging(), z2.VnD(), z0.VnD(), z29.VnD(), option);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(z15.VnH(), z3.VnH());
+    ASSERT_EQUAL_SVE(z16.VnH(), z4.VnH());
+    ASSERT_EQUAL_SVE(z17.VnH(), z5.VnH());
+    ASSERT_EQUAL_SVE(z18.VnH(), z6.VnH());
+
+    ASSERT_EQUAL_SVE(z19.VnS(), z7.VnS());
+    ASSERT_EQUAL_SVE(z20.VnS(), z8.VnS());
+    ASSERT_EQUAL_SVE(z21.VnS(), z9.VnS());
+    ASSERT_EQUAL_SVE(z22.VnS(), z10.VnS());
+
+    ASSERT_EQUAL_SVE(z23.VnD(), z11.VnD());
+    ASSERT_EQUAL_SVE(z24.VnD(), z12.VnD());
+    ASSERT_EQUAL_SVE(z11.VnD(), z13.VnD());
+    ASSERT_EQUAL_SVE(z25.VnD(), z14.VnD());
+  }
+}
+
+TEST_SVE(sve_fmla_fmls_index) {
+  uint64_t zm_inputs_1[] = {0x3ff000003f803c00, 0xbff00000bf80bc00};
+  uint64_t zn_inputs_1[] = {0x3ff012343ff03c76, 0xbff01234bff0bc76};
+  uint64_t za_inputs_1[] = {0x3c004000bc00c000, 0x64006800e400e800};
+
+  // Using the vector form of Fmla and Fmls to verify the indexed form.
+  FPMulAccIdxHelper(config,
+                    &MacroAssembler::Fmla,  // vector form
+                    &MacroAssembler::Fmla,  // indexed form
+                    za_inputs_1,
+                    zn_inputs_1,
+                    zm_inputs_1);
+
+  FPMulAccIdxHelper(config,
+                    &MacroAssembler::Fmls,  // vector form
+                    &MacroAssembler::Fmls,  // indexed form
+                    za_inputs_1,
+                    zn_inputs_1,
+                    zm_inputs_1);
+
+  uint64_t zm_inputs_2[] = {0x7ff5555511111111,   // NaN
+                            0xfff0000000000000};  // Infinity
+  uint64_t zn_inputs_2[] = {0x7f9511117fc00000,   // NaN
+                            0x7f800000ff800000};  // Infinity
+  uint64_t za_inputs_2[] = {0x7c11000000007e00,   // NaN
+                            0x000000007c00fc00};  // Infinity
+  FPMulAccIdxHelper(config,
+                    &MacroAssembler::Fmla,  // vector form
+                    &MacroAssembler::Fmla,  // indexed form
+                    za_inputs_2,
+                    zn_inputs_2,
+                    zm_inputs_2);
+
+  FPMulAccIdxHelper(config,
+                    &MacroAssembler::Fmls,  // vector form
+                    &MacroAssembler::Fmls,  // indexed form
+                    za_inputs_2,
+                    zn_inputs_2,
+                    zm_inputs_2);
+}
+
+// Execute a number of instructions which all use ProcessNaNs, and check that
+// they all propagate NaNs correctly.
+template <typename Ti, typename Td, size_t N>
+static void ProcessNaNsHelper(Test* config,
+                              int lane_size_in_bits,
+                              const Ti (&zn_inputs)[N],
+                              const Ti (&zm_inputs)[N],
+                              const Td (&zd_expected)[N],
+                              FPMacroNaNPropagationOption nan_option) {
+  ArithFn arith_unpredicated_macro[] = {&MacroAssembler::Fadd,
+                                        &MacroAssembler::Fsub,
+                                        &MacroAssembler::Fmul};
+
+  for (size_t i = 0; i < ArrayLength(arith_unpredicated_macro); i++) {
+    FPBinArithHelper(config,
+                     arith_unpredicated_macro[i],
+                     lane_size_in_bits,
+                     zn_inputs,
+                     zm_inputs,
+                     zd_expected);
+  }
+
+  FPArithPredicatedFn arith_predicated_macro[] = {&MacroAssembler::Fmax,
+                                                  &MacroAssembler::Fmin};
+  int pg_inputs[N];
+  // With an all-true predicate, this helper aims to compare with special
+  // numbers.
+  for (size_t i = 0; i < N; i++) {
+    pg_inputs[i] = 1;
+  }
+
+  // fdivr propagates the quotient (Zm) preferentially, so we don't actually
+  // need any special handling for StrictNaNPropagation.
+  FPBinArithHelper(config,
+                   NULL,
+                   &MacroAssembler::Fdiv,
+                   lane_size_in_bits,
+                   // With an all-true predicate, the value in zd is
+                   // irrelevant to the operations.
+                   zn_inputs,
+                   pg_inputs,
+                   zn_inputs,
+                   zm_inputs,
+                   zd_expected);
+
+  for (size_t i = 0; i < ArrayLength(arith_predicated_macro); i++) {
+    FPBinArithHelper(config,
+                     arith_predicated_macro[i],
+                     NULL,
+                     lane_size_in_bits,
+                     // With an all-true predicate, the value in zd is
+                     // irrelevant to the operations.
+                     zn_inputs,
+                     pg_inputs,
+                     zn_inputs,
+                     zm_inputs,
+                     zd_expected,
+                     nan_option);
+  }
+}
+
+template <typename Ti, typename Td, size_t N>
+static void ProcessNaNsHelper3(Test* config,
+                               int lane_size_in_bits,
+                               const Ti (&za_inputs)[N],
+                               const Ti (&zn_inputs)[N],
+                               const Ti (&zm_inputs)[N],
+                               const Td (&zd_expected_fmla)[N],
+                               const Td (&zd_expected_fmls)[N],
+                               const Td (&zd_expected_fnmla)[N],
+                               const Td (&zd_expected_fnmls)[N],
+                               FPMacroNaNPropagationOption nan_option) {
+  int pg_inputs[N];
+  // With an all-true predicate, this helper aims to compare with special
+  // numbers.
+  for (size_t i = 0; i < N; i++) {
+    pg_inputs[i] = 1;
+  }
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fmla,
+                 lane_size_in_bits,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 zd_expected_fmla,
+                 nan_option);
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fmls,
+                 lane_size_in_bits,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 zd_expected_fmls,
+                 nan_option);
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fnmla,
+                 lane_size_in_bits,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 zd_expected_fnmla,
+                 nan_option);
+
+  FPMulAccHelper(config,
+                 &MacroAssembler::Fnmls,
+                 lane_size_in_bits,
+                 pg_inputs,
+                 za_inputs,
+                 zn_inputs,
+                 zm_inputs,
+                 zd_expected_fnmls,
+                 nan_option);
+}
+
+TEST_SVE(sve_process_nans_double) {
+  // Use non-standard NaNs to check that the payload bits are preserved.
+  double sa = RawbitsToDouble(0x7ff5555511111111);
+  double sn = RawbitsToDouble(0x7ff5555522222222);
+  double sm = RawbitsToDouble(0x7ff5555533333333);
+  double qa = RawbitsToDouble(0x7ffaaaaa11111111);
+  double qn = RawbitsToDouble(0x7ffaaaaa22222222);
+  double qm = RawbitsToDouble(0x7ffaaaaa33333333);
+  VIXL_ASSERT(IsSignallingNaN(sa));
+  VIXL_ASSERT(IsSignallingNaN(sn));
+  VIXL_ASSERT(IsSignallingNaN(sm));
+  VIXL_ASSERT(IsQuietNaN(qa));
+  VIXL_ASSERT(IsQuietNaN(qn));
+  VIXL_ASSERT(IsQuietNaN(qm));
+
+  // The input NaNs after passing through ProcessNaN.
+  uint64_t sa_proc = 0x7ffd555511111111;
+  uint64_t sn_proc = 0x7ffd555522222222;
+  uint64_t sm_proc = 0x7ffd555533333333;
+  uint64_t qa_proc = DoubleToRawbits(qa);
+  uint64_t qn_proc = DoubleToRawbits(qn);
+  uint64_t qm_proc = DoubleToRawbits(qm);
+  uint64_t sa_proc_n = sa_proc ^ kDSignMask;
+  uint64_t sn_proc_n = sn_proc ^ kDSignMask;
+  uint64_t qa_proc_n = qa_proc ^ kDSignMask;
+  uint64_t qn_proc_n = qn_proc ^ kDSignMask;
+
+  // Quiet NaNs are propagated.
+  double zn_inputs_1[] = {qn, 0.0, 0.0, qm, qn, qm};
+  double zm_inputs_1[] = {0.0, qn, qm, 0.0, qm, qn};
+  uint64_t zd_expected_1[] =
+      {qn_proc, qn_proc, qm_proc, qm_proc, qn_proc, qm_proc};
+
+  ProcessNaNsHelper(config,
+                    kDRegSize,
+                    zn_inputs_1,
+                    zm_inputs_1,
+                    zd_expected_1,
+                    StrictNaNPropagation);
+
+  // Signalling NaNs are propagated.
+  double zn_inputs_2[] = {sn, 0.0, 0.0, sm, sn, sm};
+  double zm_inputs_2[] = {0.0, sn, sm, 0.0, sm, sn};
+  uint64_t zd_expected_2[] =
+      {sn_proc, sn_proc, sm_proc, sm_proc, sn_proc, sm_proc};
+  ProcessNaNsHelper(config,
+                    kDRegSize,
+                    zn_inputs_2,
+                    zm_inputs_2,
+                    zd_expected_2,
+                    StrictNaNPropagation);
+
+  // Signalling NaNs take precedence over quiet NaNs.
+  double zn_inputs_3[] = {sn, qn, sn, sn, qn};
+  double zm_inputs_3[] = {qm, sm, sm, qn, sn};
+  uint64_t zd_expected_3[] = {sn_proc, sm_proc, sn_proc, sn_proc, sn_proc};
+  ProcessNaNsHelper(config,
+                    kDRegSize,
+                    zn_inputs_3,
+                    zm_inputs_3,
+                    zd_expected_3,
+                    StrictNaNPropagation);
+
+  double za_inputs_4[] = {qa, qa, 0.0, 0.0, qa, qa};
+  double zn_inputs_4[] = {qn, 0.0, 0.0, qn, qn, qn};
+  double zm_inputs_4[] = {0.0, qm, qm, qm, qm, 0.0};
+
+  // If `a` is propagated, its sign is inverted by fnmla and fnmls.
+  // If `n` is propagated, its sign is inverted by fmls and fnmla.
+  // If `m` is propagated, its sign is never inverted.
+  uint64_t zd_expected_fmla_4[] =
+      {qa_proc, qa_proc, qm_proc, qn_proc, qa_proc, qa_proc};
+  uint64_t zd_expected_fmls_4[] =
+      {qa_proc, qa_proc, qm_proc, qn_proc_n, qa_proc, qa_proc};
+  uint64_t zd_expected_fnmla_4[] =
+      {qa_proc_n, qa_proc_n, qm_proc, qn_proc_n, qa_proc_n, qa_proc_n};
+  uint64_t zd_expected_fnmls_4[] =
+      {qa_proc_n, qa_proc_n, qm_proc, qn_proc, qa_proc_n, qa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kDRegSize,
+                     za_inputs_4,
+                     zn_inputs_4,
+                     zm_inputs_4,
+                     zd_expected_fmla_4,
+                     zd_expected_fmls_4,
+                     zd_expected_fnmla_4,
+                     zd_expected_fnmls_4,
+                     StrictNaNPropagation);
+
+  // Signalling NaNs take precedence over quiet NaNs.
+  double za_inputs_5[] = {qa, qa, sa, sa, sa};
+  double zn_inputs_5[] = {qn, sn, sn, sn, qn};
+  double zm_inputs_5[] = {sm, qm, sm, qa, sm};
+  uint64_t zd_expected_fmla_5[] = {sm_proc, sn_proc, sa_proc, sa_proc, sa_proc};
+  uint64_t zd_expected_fmls_5[] = {sm_proc,
+                                   sn_proc_n,
+                                   sa_proc,
+                                   sa_proc,
+                                   sa_proc};
+  uint64_t zd_expected_fnmla_5[] = {sm_proc,
+                                    sn_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n};
+  uint64_t zd_expected_fnmls_5[] = {sm_proc,
+                                    sn_proc,
+                                    sa_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kDRegSize,
+                     za_inputs_5,
+                     zn_inputs_5,
+                     zm_inputs_5,
+                     zd_expected_fmla_5,
+                     zd_expected_fmls_5,
+                     zd_expected_fnmla_5,
+                     zd_expected_fnmls_5,
+                     StrictNaNPropagation);
+
+  const double inf = kFP64PositiveInfinity;
+  const double inf_n = kFP64NegativeInfinity;
+  uint64_t inf_proc = DoubleToRawbits(inf);
+  uint64_t inf_proc_n = DoubleToRawbits(inf_n);
+  uint64_t d_inf_proc = DoubleToRawbits(kFP64DefaultNaN);
+
+  double za_inputs_6[] = {qa, qa, 0.0f, -0.0f, qa, sa};
+  double zn_inputs_6[] = {inf, -0.0f, -0.0f, inf, inf_n, inf};
+  double zm_inputs_6[] = {0.0f, inf_n, inf, inf, inf, 0.0f};
+
+  // quiet_nan + (0.0 * inf) produces the default NaN, not quiet_nan. Ditto for
+  // (inf * 0.0). On the other hand, quiet_nan + (inf * inf) propagates the
+  // quiet_nan.
+  uint64_t zd_expected_fmla_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc, qa_proc, sa_proc};
+  uint64_t zd_expected_fmls_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc_n, qa_proc, sa_proc};
+  uint64_t zd_expected_fnmla_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc_n, qa_proc_n, sa_proc_n};
+  uint64_t zd_expected_fnmls_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc, qa_proc_n, sa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kDRegSize,
+                     za_inputs_6,
+                     zn_inputs_6,
+                     zm_inputs_6,
+                     zd_expected_fmla_6,
+                     zd_expected_fmls_6,
+                     zd_expected_fnmla_6,
+                     zd_expected_fnmls_6,
+                     StrictNaNPropagation);
+}
+
+TEST_SVE(sve_process_nans_float) {
+  // Use non-standard NaNs to check that the payload bits are preserved.
+  float sa = RawbitsToFloat(0x7f951111);
+  float sn = RawbitsToFloat(0x7f952222);
+  float sm = RawbitsToFloat(0x7f953333);
+  float qa = RawbitsToFloat(0x7fea1111);
+  float qn = RawbitsToFloat(0x7fea2222);
+  float qm = RawbitsToFloat(0x7fea3333);
+  VIXL_ASSERT(IsSignallingNaN(sa));
+  VIXL_ASSERT(IsSignallingNaN(sn));
+  VIXL_ASSERT(IsSignallingNaN(sm));
+  VIXL_ASSERT(IsQuietNaN(qa));
+  VIXL_ASSERT(IsQuietNaN(qn));
+  VIXL_ASSERT(IsQuietNaN(qm));
+
+  // The input NaNs after passing through ProcessNaN.
+  uint32_t sa_proc = 0x7fd51111;
+  uint32_t sn_proc = 0x7fd52222;
+  uint32_t sm_proc = 0x7fd53333;
+  uint32_t qa_proc = FloatToRawbits(qa);
+  uint32_t qn_proc = FloatToRawbits(qn);
+  uint32_t qm_proc = FloatToRawbits(qm);
+  uint32_t sa_proc_n = sa_proc ^ kSSignMask;
+  uint32_t sn_proc_n = sn_proc ^ kSSignMask;
+  uint32_t qa_proc_n = qa_proc ^ kSSignMask;
+  uint32_t qn_proc_n = qn_proc ^ kSSignMask;
+
+  // Quiet NaNs are propagated.
+  float zn_inputs_1[] = {qn, 0.0f, 0.0f, qm, qn, qm};
+  float zm_inputs_1[] = {0.0f, qn, qm, 0.0f, qm, qn};
+  uint64_t zd_expected_1[] =
+      {qn_proc, qn_proc, qm_proc, qm_proc, qn_proc, qm_proc};
+
+  ProcessNaNsHelper(config,
+                    kSRegSize,
+                    zn_inputs_1,
+                    zm_inputs_1,
+                    zd_expected_1,
+                    StrictNaNPropagation);
+
+  // Signalling NaNs are propagated.
+  float zn_inputs_2[] = {sn, 0.0f, 0.0f, sm, sn, sm};
+  float zm_inputs_2[] = {0.0f, sn, sm, 0.0f, sm, sn};
+  uint64_t zd_expected_2[] =
+      {sn_proc, sn_proc, sm_proc, sm_proc, sn_proc, sm_proc};
+  ProcessNaNsHelper(config,
+                    kSRegSize,
+                    zn_inputs_2,
+                    zm_inputs_2,
+                    zd_expected_2,
+                    StrictNaNPropagation);
+
+  // Signalling NaNs take precedence over quiet NaNs.
+  float zn_inputs_3[] = {sn, qn, sn, sn, qn};
+  float zm_inputs_3[] = {qm, sm, sm, qn, sn};
+  uint64_t zd_expected_3[] = {sn_proc, sm_proc, sn_proc, sn_proc, sn_proc};
+  ProcessNaNsHelper(config,
+                    kSRegSize,
+                    zn_inputs_3,
+                    zm_inputs_3,
+                    zd_expected_3,
+                    StrictNaNPropagation);
+
+  float za_inputs_4[] = {qa, qa, 0.0f, 0.0f, qa, qa};
+  float zn_inputs_4[] = {qn, 0.0f, 0.0f, qn, qn, qn};
+  float zm_inputs_4[] = {0.0f, qm, qm, qm, qm, 0.0f};
+
+  // If `a` is propagated, its sign is inverted by fnmla and fnmls.
+  // If `n` is propagated, its sign is inverted by fmls and fnmla.
+  // If `m` is propagated, its sign is never inverted.
+  uint64_t zd_expected_fmla_4[] =
+      {qa_proc, qa_proc, qm_proc, qn_proc, qa_proc, qa_proc};
+  uint64_t zd_expected_fmls_4[] =
+      {qa_proc, qa_proc, qm_proc, qn_proc_n, qa_proc, qa_proc};
+  uint64_t zd_expected_fnmla_4[] =
+      {qa_proc_n, qa_proc_n, qm_proc, qn_proc_n, qa_proc_n, qa_proc_n};
+  uint64_t zd_expected_fnmls_4[] =
+      {qa_proc_n, qa_proc_n, qm_proc, qn_proc, qa_proc_n, qa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kSRegSize,
+                     za_inputs_4,
+                     zn_inputs_4,
+                     zm_inputs_4,
+                     zd_expected_fmla_4,
+                     zd_expected_fmls_4,
+                     zd_expected_fnmla_4,
+                     zd_expected_fnmls_4,
+                     StrictNaNPropagation);
+
+  // Signalling NaNs take precedence over quiet NaNs.
+  float za_inputs_5[] = {qa, qa, sa, sa, sa};
+  float zn_inputs_5[] = {qn, sn, sn, sn, qn};
+  float zm_inputs_5[] = {sm, qm, sm, qa, sm};
+  uint64_t zd_expected_fmla_5[] = {sm_proc, sn_proc, sa_proc, sa_proc, sa_proc};
+  uint64_t zd_expected_fmls_5[] = {sm_proc,
+                                   sn_proc_n,
+                                   sa_proc,
+                                   sa_proc,
+                                   sa_proc};
+  uint64_t zd_expected_fnmla_5[] = {sm_proc,
+                                    sn_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n};
+  uint64_t zd_expected_fnmls_5[] = {sm_proc,
+                                    sn_proc,
+                                    sa_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kSRegSize,
+                     za_inputs_5,
+                     zn_inputs_5,
+                     zm_inputs_5,
+                     zd_expected_fmla_5,
+                     zd_expected_fmls_5,
+                     zd_expected_fnmla_5,
+                     zd_expected_fnmls_5,
+                     StrictNaNPropagation);
+
+  const float inf = kFP32PositiveInfinity;
+  const float inf_n = kFP32NegativeInfinity;
+  uint32_t inf_proc = FloatToRawbits(inf);
+  uint32_t inf_proc_n = FloatToRawbits(inf_n);
+  uint32_t d_inf_proc = FloatToRawbits(kFP32DefaultNaN);
+
+  float za_inputs_6[] = {qa, qa, 0.0f, 0.0f, qa, sa};
+  float zn_inputs_6[] = {inf, 0.0f, 0.0f, inf, inf_n, inf};
+  float zm_inputs_6[] = {0.0f, inf_n, inf, inf, inf, 0.0f};
+
+  // quiet_nan + (0.0 * inf) produces the default NaN, not quiet_nan. Ditto for
+  // (inf * 0.0). On the other hand, quiet_nan + (inf * inf) propagates the
+  // quiet_nan.
+  uint64_t zd_expected_fmla_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc, qa_proc, sa_proc};
+  uint64_t zd_expected_fmls_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc_n, qa_proc, sa_proc};
+  uint64_t zd_expected_fnmla_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc_n, qa_proc_n, sa_proc_n};
+  uint64_t zd_expected_fnmls_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc, qa_proc_n, sa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kSRegSize,
+                     za_inputs_6,
+                     zn_inputs_6,
+                     zm_inputs_6,
+                     zd_expected_fmla_6,
+                     zd_expected_fmls_6,
+                     zd_expected_fnmla_6,
+                     zd_expected_fnmls_6,
+                     StrictNaNPropagation);
+}
+
+TEST_SVE(sve_process_nans_half) {
+  // Use non-standard NaNs to check that the payload bits are preserved.
+  Float16 sa(RawbitsToFloat16(0x7c11));
+  Float16 sn(RawbitsToFloat16(0x7c22));
+  Float16 sm(RawbitsToFloat16(0x7c33));
+  Float16 qa(RawbitsToFloat16(0x7e44));
+  Float16 qn(RawbitsToFloat16(0x7e55));
+  Float16 qm(RawbitsToFloat16(0x7e66));
+  VIXL_ASSERT(IsSignallingNaN(sa));
+  VIXL_ASSERT(IsSignallingNaN(sn));
+  VIXL_ASSERT(IsSignallingNaN(sm));
+  VIXL_ASSERT(IsQuietNaN(qa));
+  VIXL_ASSERT(IsQuietNaN(qn));
+  VIXL_ASSERT(IsQuietNaN(qm));
+
+  // The input NaNs after passing through ProcessNaN.
+  uint16_t sa_proc = 0x7e11;
+  uint16_t sn_proc = 0x7e22;
+  uint16_t sm_proc = 0x7e33;
+  uint16_t qa_proc = Float16ToRawbits(qa);
+  uint16_t qn_proc = Float16ToRawbits(qn);
+  uint16_t qm_proc = Float16ToRawbits(qm);
+  uint16_t sa_proc_n = sa_proc ^ kHSignMask;
+  uint16_t sn_proc_n = sn_proc ^ kHSignMask;
+  uint16_t qa_proc_n = qa_proc ^ kHSignMask;
+  uint16_t qn_proc_n = qn_proc ^ kHSignMask;
+  Float16 zero(0.0);
+
+  // Quiet NaNs are propagated.
+  Float16 zn_inputs_1[] = {qn, zero, zero, qm, qn, qm};
+  Float16 zm_inputs_1[] = {zero, qn, qm, zero, qm, qn};
+  uint64_t zd_expected_1[] =
+      {qn_proc, qn_proc, qm_proc, qm_proc, qn_proc, qm_proc};
+
+  ProcessNaNsHelper(config,
+                    kHRegSize,
+                    zn_inputs_1,
+                    zm_inputs_1,
+                    zd_expected_1,
+                    StrictNaNPropagation);
+
+  // Signalling NaNs are propagated.
+  Float16 zn_inputs_2[] = {sn, zero, zero, sm, sn, sm};
+  Float16 zm_inputs_2[] = {zero, sn, sm, zero, sm, sn};
+  uint64_t zd_expected_2[] =
+      {sn_proc, sn_proc, sm_proc, sm_proc, sn_proc, sm_proc};
+  ProcessNaNsHelper(config,
+                    kHRegSize,
+                    zn_inputs_2,
+                    zm_inputs_2,
+                    zd_expected_2,
+                    StrictNaNPropagation);
+
+  // Signalling NaNs take precedence over quiet NaNs.
+  Float16 zn_inputs_3[] = {sn, qn, sn, sn, qn};
+  Float16 zm_inputs_3[] = {qm, sm, sm, qn, sn};
+  uint64_t zd_expected_3[] = {sn_proc, sm_proc, sn_proc, sn_proc, sn_proc};
+  ProcessNaNsHelper(config,
+                    kHRegSize,
+                    zn_inputs_3,
+                    zm_inputs_3,
+                    zd_expected_3,
+                    StrictNaNPropagation);
+
+  Float16 za_inputs_4[] = {qa, qa, zero, zero, qa, qa};
+  Float16 zn_inputs_4[] = {qn, zero, zero, qn, qn, qn};
+  Float16 zm_inputs_4[] = {zero, qm, qm, qm, qm, zero};
+
+  // If `a` is propagated, its sign is inverted by fnmla and fnmls.
+  // If `n` is propagated, its sign is inverted by fmls and fnmla.
+  // If `m` is propagated, its sign is never inverted.
+  uint64_t zd_expected_fmla_4[] =
+      {qa_proc, qa_proc, qm_proc, qn_proc, qa_proc, qa_proc};
+  uint64_t zd_expected_fmls_4[] =
+      {qa_proc, qa_proc, qm_proc, qn_proc_n, qa_proc, qa_proc};
+  uint64_t zd_expected_fnmla_4[] =
+      {qa_proc_n, qa_proc_n, qm_proc, qn_proc_n, qa_proc_n, qa_proc_n};
+  uint64_t zd_expected_fnmls_4[] =
+      {qa_proc_n, qa_proc_n, qm_proc, qn_proc, qa_proc_n, qa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kHRegSize,
+                     za_inputs_4,
+                     zn_inputs_4,
+                     zm_inputs_4,
+                     zd_expected_fmla_4,
+                     zd_expected_fmls_4,
+                     zd_expected_fnmla_4,
+                     zd_expected_fnmls_4,
+                     StrictNaNPropagation);
+
+  // Signalling NaNs take precedence over quiet NaNs.
+  Float16 za_inputs_5[] = {qa, qa, sa, sa, sa};
+  Float16 zn_inputs_5[] = {qn, sn, sn, sn, qn};
+  Float16 zm_inputs_5[] = {sm, qm, sm, qa, sm};
+  uint64_t zd_expected_fmla_5[] = {sm_proc, sn_proc, sa_proc, sa_proc, sa_proc};
+  uint64_t zd_expected_fmls_5[] = {sm_proc,
+                                   sn_proc_n,
+                                   sa_proc,
+                                   sa_proc,
+                                   sa_proc};
+  uint64_t zd_expected_fnmla_5[] = {sm_proc,
+                                    sn_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n};
+  uint64_t zd_expected_fnmls_5[] = {sm_proc,
+                                    sn_proc,
+                                    sa_proc_n,
+                                    sa_proc_n,
+                                    sa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kHRegSize,
+                     za_inputs_5,
+                     zn_inputs_5,
+                     zm_inputs_5,
+                     zd_expected_fmla_5,
+                     zd_expected_fmls_5,
+                     zd_expected_fnmla_5,
+                     zd_expected_fnmls_5,
+                     StrictNaNPropagation);
+
+  const Float16 inf = kFP16PositiveInfinity;
+  const Float16 inf_n = kFP16NegativeInfinity;
+  uint64_t inf_proc = Float16ToRawbits(inf);
+  uint64_t inf_proc_n = Float16ToRawbits(inf_n);
+  uint64_t d_inf_proc = Float16ToRawbits(kFP16DefaultNaN);
+
+  Float16 za_inputs_6[] = {qa, qa, zero, zero, qa, sa};
+  Float16 zn_inputs_6[] = {inf, zero, zero, inf, inf_n, inf};
+  Float16 zm_inputs_6[] = {zero, inf_n, inf, inf, inf, zero};
+
+  // quiet_nan + (0.0 * inf) produces the default NaN, not quiet_nan. Ditto for
+  // (inf * 0.0). On the other hand, quiet_nan + (inf * inf) propagates the
+  // quiet_nan.
+  uint64_t zd_expected_fmla_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc, qa_proc, sa_proc};
+  uint64_t zd_expected_fmls_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc_n, qa_proc, sa_proc};
+  uint64_t zd_expected_fnmla_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc_n, qa_proc_n, sa_proc_n};
+  uint64_t zd_expected_fnmls_6[] =
+      {d_inf_proc, d_inf_proc, d_inf_proc, inf_proc, qa_proc_n, sa_proc_n};
+
+  ProcessNaNsHelper3(config,
+                     kHRegSize,
+                     za_inputs_6,
+                     zn_inputs_6,
+                     zm_inputs_6,
+                     zd_expected_fmla_6,
+                     zd_expected_fmls_6,
+                     zd_expected_fnmla_6,
+                     zd_expected_fnmls_6,
+                     StrictNaNPropagation);
+}
+
+typedef void (MacroAssembler::*FCmpFn)(const PRegisterWithLaneSize& pd,
+                                       const PRegisterZ& pg,
+                                       const ZRegister& zn,
+                                       const ZRegister& zm);
+
+typedef void (MacroAssembler::*FCmpZeroFn)(const PRegisterWithLaneSize& pd,
+                                           const PRegisterZ& pg,
+                                           const ZRegister& zn,
+                                           double zero);
+
+typedef void (MacroAssembler::*CmpFn)(const PRegisterWithLaneSize& pd,
+                                      const PRegisterZ& pg,
+                                      const ZRegister& zn,
+                                      const ZRegister& zm);
+
+static FCmpFn GetFpAbsCompareFn(Condition cond) {
+  switch (cond) {
+    case ge:
+      return &MacroAssembler::Facge;
+    case gt:
+      return &MacroAssembler::Facgt;
+    case le:
+      return &MacroAssembler::Facle;
+    case lt:
+      return &MacroAssembler::Faclt;
+    default:
+      VIXL_UNIMPLEMENTED();
+      return NULL;
+  }
+}
+
+static FCmpFn GetFpCompareFn(Condition cond) {
+  switch (cond) {
+    case ge:
+      return &MacroAssembler::Fcmge;
+    case gt:
+      return &MacroAssembler::Fcmgt;
+    case le:
+      return &MacroAssembler::Fcmle;
+    case lt:
+      return &MacroAssembler::Fcmlt;
+    case eq:
+      return &MacroAssembler::Fcmeq;
+    case ne:
+      return &MacroAssembler::Fcmne;
+    case uo:
+      return &MacroAssembler::Fcmuo;
+    default:
+      VIXL_UNIMPLEMENTED();
+      return NULL;
+  }
+}
+
+static FCmpZeroFn GetFpCompareZeroFn(Condition cond) {
+  switch (cond) {
+    case ge:
+      return &MacroAssembler::Fcmge;
+    case gt:
+      return &MacroAssembler::Fcmgt;
+    case le:
+      return &MacroAssembler::Fcmle;
+    case lt:
+      return &MacroAssembler::Fcmlt;
+    case eq:
+      return &MacroAssembler::Fcmeq;
+    case ne:
+      return &MacroAssembler::Fcmne;
+    default:
+      VIXL_UNIMPLEMENTED();
+      return NULL;
+  }
+}
+
+static CmpFn GetIntCompareFn(Condition cond) {
+  switch (cond) {
+    case ge:
+      return &MacroAssembler::Cmpge;
+    case gt:
+      return &MacroAssembler::Cmpgt;
+    case le:
+      return &MacroAssembler::Cmple;
+    case lt:
+      return &MacroAssembler::Cmplt;
+    case eq:
+      return &MacroAssembler::Cmpeq;
+    case ne:
+      return &MacroAssembler::Cmpne;
+    default:
+      VIXL_UNIMPLEMENTED();
+      return NULL;
+  }
+}
+
+template <size_t N>
+static void TestFpCompareHelper(Test* config,
+                                int lane_size_in_bits,
+                                Condition cond,
+                                const double (&zn_inputs)[N],
+                                const double (&zm_inputs)[N],
+                                const int (&pd_expected)[N],
+                                bool is_absolute = false) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  ZRegister zt_int_1 = z1.WithLaneSize(lane_size_in_bits);
+  ZRegister zt_int_2 = z2.WithLaneSize(lane_size_in_bits);
+  ZRegister zt_int_3 = z3.WithLaneSize(lane_size_in_bits);
+  ZRegister zt_fp_1 = z11.WithLaneSize(lane_size_in_bits);
+  ZRegister zt_fp_2 = z12.WithLaneSize(lane_size_in_bits);
+  ZRegister zt_fp_3 = z13.WithLaneSize(lane_size_in_bits);
+  ZRegister fp_one = z31.WithLaneSize(lane_size_in_bits);
+
+  PRegisterWithLaneSize pd_result_int_1 = p15.WithLaneSize(lane_size_in_bits);
+  PRegisterWithLaneSize pd_result_fp_1 = p14.WithLaneSize(lane_size_in_bits);
+  PRegisterWithLaneSize pd_result_int_2 = p13.WithLaneSize(lane_size_in_bits);
+  PRegisterWithLaneSize pd_result_fp_2 = p12.WithLaneSize(lane_size_in_bits);
+
+  FCmpFn fcmp = is_absolute ? GetFpAbsCompareFn(cond) : GetFpCompareFn(cond);
+  __ Ptrue(p1.VnB());
+
+  if (cond != uo) {
+    int pg_inputs[] = {1, 0, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 1};
+    Initialise(&masm, p0.WithLaneSize(lane_size_in_bits), pg_inputs);
+
+    __ Fdup(fp_one, 0.1f);
+
+    __ Index(zt_int_1, 3, 3);
+    __ Scvtf(zt_fp_1, p0.Merging(), zt_int_1);
+    __ Fadd(zt_fp_1, zt_fp_1, fp_one);
+
+    __ Index(zt_int_2, 3, -10);
+    __ Scvtf(zt_fp_2, p0.Merging(), zt_int_2);
+    __ Fadd(zt_fp_2, zt_fp_2, fp_one);
+
+    __ Index(zt_int_3, 3, 2);
+    __ Scvtf(zt_fp_3, p0.Merging(), zt_int_3);
+    __ Fadd(zt_fp_3, zt_fp_3, fp_one);
+
+
+    // There is no absolute comparison in integer type, use `abs` with `cmp<cc>`
+    // to synthesize the expected result for `fac<cc>`.
+    if (is_absolute == true) {
+      __ Abs(zt_int_2, p1.Merging(), zt_int_2);
+    }
+
+    CmpFn cmp = GetIntCompareFn(cond);
+    (masm.*cmp)(pd_result_int_1, p0.Zeroing(), zt_int_1, zt_int_2);
+    (masm.*fcmp)(pd_result_fp_1, p0.Zeroing(), zt_fp_1, zt_fp_2);
+
+    (masm.*cmp)(pd_result_int_2, p0.Zeroing(), zt_int_1, zt_int_3);
+    (masm.*fcmp)(pd_result_fp_2, p0.Zeroing(), zt_fp_1, zt_fp_3);
+  }
+
+  uint64_t zn_inputs_rawbits[N];
+  uint64_t zm_inputs_rawbits[N];
+  FPToRawbitsWithSize(zn_inputs, zn_inputs_rawbits, lane_size_in_bits);
+  FPToRawbitsWithSize(zm_inputs, zm_inputs_rawbits, lane_size_in_bits);
+
+  ZRegister zn_fp = z14.WithLaneSize(lane_size_in_bits);
+  ZRegister zm_fp = z15.WithLaneSize(lane_size_in_bits);
+  InsrHelper(&masm, zn_fp, zn_inputs_rawbits);
+  InsrHelper(&masm, zm_fp, zm_inputs_rawbits);
+
+  PRegisterWithLaneSize pd_result_fp_3 = p11.WithLaneSize(lane_size_in_bits);
+  (masm.*fcmp)(pd_result_fp_3, p1.Zeroing(), zn_fp, zm_fp);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    if (cond != uo) {
+      ASSERT_EQUAL_SVE(pd_result_int_1, pd_result_fp_1);
+      ASSERT_EQUAL_SVE(pd_result_int_2, pd_result_fp_2);
+    }
+    ASSERT_EQUAL_SVE(pd_expected, pd_result_fp_3);
+  }
+}
+
+TEST_SVE(sve_fp_compare_vectors) {
+  double inf_p = kFP64PositiveInfinity;
+  double inf_n = kFP64NegativeInfinity;
+  double nan = kFP64DefaultNaN;
+
+  // Normal floating point comparison has been tested in the helper.
+  double zn[] = {0.0, inf_n, 1.0, inf_p, inf_p, nan, 0.0, nan};
+  double zm[] = {-0.0, inf_n, inf_n, -2.0, inf_n, nan, nan, inf_p};
+
+  int pd_fcm_gt[] = {0, 0, 1, 1, 1, 0, 0, 0};
+  int pd_fcm_lt[] = {0, 0, 0, 0, 0, 0, 0, 0};
+  int pd_fcm_ge[] = {1, 1, 1, 1, 1, 0, 0, 0};
+  int pd_fcm_le[] = {1, 1, 0, 0, 0, 0, 0, 0};
+  int pd_fcm_eq[] = {1, 1, 0, 0, 0, 0, 0, 0};
+  int pd_fcm_ne[] = {0, 0, 1, 1, 1, 1, 1, 1};
+  int pd_fcm_uo[] = {0, 0, 0, 0, 0, 1, 1, 1};
+  int pd_fac_gt[] = {0, 0, 0, 1, 0, 0, 0, 0};
+  int pd_fac_lt[] = {0, 0, 1, 0, 0, 0, 0, 0};
+  int pd_fac_ge[] = {1, 1, 0, 1, 1, 0, 0, 0};
+  int pd_fac_le[] = {1, 1, 1, 0, 1, 0, 0, 0};
+
+  int lane_sizes[] = {kHRegSize, kSRegSize, kDRegSize};
+
+  for (size_t i = 0; i < ArrayLength(lane_sizes); i++) {
+    int lane_size = lane_sizes[i];
+    // Test floating-point compare vectors.
+    TestFpCompareHelper(config, lane_size, gt, zn, zm, pd_fcm_gt);
+    TestFpCompareHelper(config, lane_size, lt, zn, zm, pd_fcm_lt);
+    TestFpCompareHelper(config, lane_size, ge, zn, zm, pd_fcm_ge);
+    TestFpCompareHelper(config, lane_size, le, zn, zm, pd_fcm_le);
+    TestFpCompareHelper(config, lane_size, eq, zn, zm, pd_fcm_eq);
+    TestFpCompareHelper(config, lane_size, ne, zn, zm, pd_fcm_ne);
+    TestFpCompareHelper(config, lane_size, uo, zn, zm, pd_fcm_uo);
+
+    // Test floating-point absolute compare vectors.
+    TestFpCompareHelper(config, lane_size, gt, zn, zm, pd_fac_gt, true);
+    TestFpCompareHelper(config, lane_size, lt, zn, zm, pd_fac_lt, true);
+    TestFpCompareHelper(config, lane_size, ge, zn, zm, pd_fac_ge, true);
+    TestFpCompareHelper(config, lane_size, le, zn, zm, pd_fac_le, true);
+  }
+}
+
+template <size_t N, typename T>
+static void TestFpCompareZeroHelper(Test* config,
+                                    int lane_size_in_bits,
+                                    Condition cond,
+                                    const T (&zn_inputs)[N],
+                                    const int (&pd_expected)[N]) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  ZRegister zn = z28.WithLaneSize(lane_size_in_bits);
+  PRegisterWithLaneSize pd = p14.WithLaneSize(lane_size_in_bits);
+
+  uint64_t zn_rawbits[N];
+  FPToRawbitsWithSize(zn_inputs, zn_rawbits, lane_size_in_bits);
+  InsrHelper(&masm, zn, zn_rawbits);
+
+  __ Ptrue(p0.VnB());
+  (masm.*GetFpCompareZeroFn(cond))(pd, p0.Zeroing(), zn, 0.0);
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(pd_expected, pd);
+  }
+}
+
+TEST_SVE(sve_fp_compare_vector_zero) {
+  Float16 fp16_inf_p = kFP16PositiveInfinity;
+  Float16 fp16_inf_n = kFP16NegativeInfinity;
+  Float16 fp16_dn = kFP16DefaultNaN;
+  Float16 fp16_sn = RawbitsToFloat16(0x7c22);
+  Float16 fp16_qn = RawbitsToFloat16(0x7e55);
+
+  float fp32_inf_p = kFP32PositiveInfinity;
+  float fp32_inf_n = kFP32NegativeInfinity;
+  float fp32_dn = kFP32DefaultNaN;
+  float fp32_sn = RawbitsToFloat(0x7f952222);
+  float fp32_qn = RawbitsToFloat(0x7fea2222);
+
+  double fp64_inf_p = kFP64PositiveInfinity;
+  double fp64_inf_n = kFP64NegativeInfinity;
+  double fp64_dn = kFP64DefaultNaN;
+  double fp64_sn = RawbitsToDouble(0x7ff5555511111111);
+  double fp64_qn = RawbitsToDouble(0x7ffaaaaa11111111);
+
+  // Normal floating point comparison has been tested in the non-zero form.
+  Float16 zn_inputs_h[] = {Float16(0.0),
+                           Float16(-0.0),
+                           fp16_inf_p,
+                           fp16_inf_n,
+                           fp16_dn,
+                           fp16_sn,
+                           fp16_qn};
+  float zn_inputs_s[] =
+      {0.0, -0.0, fp32_inf_p, fp32_inf_n, fp32_dn, fp32_sn, fp32_qn};
+  double zn_inputs_d[] =
+      {0.0, -0.0, fp64_inf_p, fp64_inf_n, fp64_dn, fp64_sn, fp64_qn};
+
+  int pd_expected_gt[] = {0, 0, 1, 0, 0, 0, 0};
+  int pd_expected_lt[] = {0, 0, 0, 1, 0, 0, 0};
+  int pd_expected_ge[] = {1, 1, 1, 0, 0, 0, 0};
+  int pd_expected_le[] = {1, 1, 0, 1, 0, 0, 0};
+  int pd_expected_eq[] = {1, 1, 0, 0, 0, 0, 0};
+  int pd_expected_ne[] = {0, 0, 1, 1, 1, 1, 1};
+
+  TestFpCompareZeroHelper(config, kDRegSize, gt, zn_inputs_d, pd_expected_gt);
+  TestFpCompareZeroHelper(config, kDRegSize, lt, zn_inputs_d, pd_expected_lt);
+  TestFpCompareZeroHelper(config, kDRegSize, ge, zn_inputs_d, pd_expected_ge);
+  TestFpCompareZeroHelper(config, kDRegSize, le, zn_inputs_d, pd_expected_le);
+  TestFpCompareZeroHelper(config, kDRegSize, eq, zn_inputs_d, pd_expected_eq);
+  TestFpCompareZeroHelper(config, kDRegSize, ne, zn_inputs_d, pd_expected_ne);
+
+  TestFpCompareZeroHelper(config, kSRegSize, gt, zn_inputs_s, pd_expected_gt);
+  TestFpCompareZeroHelper(config, kSRegSize, lt, zn_inputs_s, pd_expected_lt);
+  TestFpCompareZeroHelper(config, kSRegSize, ge, zn_inputs_s, pd_expected_ge);
+  TestFpCompareZeroHelper(config, kSRegSize, le, zn_inputs_s, pd_expected_le);
+  TestFpCompareZeroHelper(config, kSRegSize, eq, zn_inputs_s, pd_expected_eq);
+  TestFpCompareZeroHelper(config, kSRegSize, ne, zn_inputs_s, pd_expected_ne);
+
+  TestFpCompareZeroHelper(config, kHRegSize, gt, zn_inputs_h, pd_expected_gt);
+  TestFpCompareZeroHelper(config, kHRegSize, lt, zn_inputs_h, pd_expected_lt);
+  TestFpCompareZeroHelper(config, kHRegSize, ge, zn_inputs_h, pd_expected_ge);
+  TestFpCompareZeroHelper(config, kHRegSize, le, zn_inputs_h, pd_expected_le);
+  TestFpCompareZeroHelper(config, kHRegSize, eq, zn_inputs_h, pd_expected_eq);
+  TestFpCompareZeroHelper(config, kHRegSize, ne, zn_inputs_h, pd_expected_ne);
+}
+
+typedef void (MacroAssembler::*FPUnaryMFn)(const ZRegister& zd,
+                                           const PRegisterM& pg,
+                                           const ZRegister& zn);
+
+typedef void (MacroAssembler::*FPUnaryZFn)(const ZRegister& zd,
+                                           const PRegisterZ& pg,
+                                           const ZRegister& zn);
+
+template <size_t N, size_t M>
+static void TestFPUnaryPredicatedHelper(Test* config,
+                                        int src_size_in_bits,
+                                        int dst_size_in_bits,
+                                        uint64_t (&zn_inputs)[N],
+                                        const uint64_t (&pg_inputs)[M],
+                                        const uint64_t (&zd_expected)[N],
+                                        FPUnaryMFn macro_m,
+                                        FPUnaryZFn macro_z) {
+  // Provide the full predicate input.
+  VIXL_ASSERT(M == (kPRegMaxSize / kDRegSize));
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  int ds = dst_size_in_bits;
+  int ss = src_size_in_bits;
+  int ls = std::max(ss, ds);
+
+  // When destination type is larger than source type, fill the high parts with
+  // noise values, which should be ignored.
+  if (ds > ss) {
+    VIXL_ASSERT(ss < 64);
+    uint64_t zn_inputs_mod[N];
+    uint64_t sn = GetSignallingNan(ss);
+    for (unsigned i = 0; i < N; i++) {
+      zn_inputs_mod[i] = zn_inputs[i] | ((sn + i) << ss);
+    }
+    InsrHelper(&masm, z29.WithLaneSize(ls), zn_inputs_mod);
+  } else {
+    InsrHelper(&masm, z29.WithLaneSize(ls), zn_inputs);
+  }
+
+  // Make a copy so we can check that constructive operations preserve zn.
+  __ Mov(z28, z29);
+
+  // Run the operation on all lanes.
+  __ Ptrue(p0.WithLaneSize(ls));
+  (masm.*macro_m)(z27.WithLaneSize(ds), p0.Merging(), z28.WithLaneSize(ss));
+
+  Initialise(&masm,
+             p1.VnB(),
+             pg_inputs[3],
+             pg_inputs[2],
+             pg_inputs[1],
+             pg_inputs[0]);
+
+  // Clear the irrelevant lanes.
+  __ Index(z31.WithLaneSize(ls), 0, 1);
+  __ Cmplt(p1.WithLaneSize(ls), p1.Zeroing(), z31.WithLaneSize(ls), N);
+
+  // Check merging predication.
+  __ Index(z11.WithLaneSize(ls), 42, 1);
+  // Preserve the base value so we can derive the expected result.
+  __ Mov(z21, z11);
+  __ Mov(z9, z11);
+  (masm.*macro_m)(z11.WithLaneSize(ds), p1.Merging(), z28.WithLaneSize(ss));
+
+  // Generate expected values using explicit merging operations.
+  InsrHelper(&masm, z25.WithLaneSize(ls), zd_expected);
+  __ Mov(z21.WithLaneSize(ls), p1.Merging(), z25.WithLaneSize(ls));
+
+  // Check zeroing predication.
+  __ Index(z12.WithLaneSize(ds), 42, -1);
+  (masm.*macro_z)(z12.WithLaneSize(ds), p1.Zeroing(), z28.WithLaneSize(ss));
+
+  // Generate expected values using explicit zeroing operations.
+  InsrHelper(&masm, z30.WithLaneSize(ls), zd_expected);
+  // Emulate zeroing predication.
+  __ Dup(z22.WithLaneSize(ls), 0);
+  __ Mov(z22.WithLaneSize(ls), p1.Merging(), z30.WithLaneSize(ls));
+
+  // Check an in-place update.
+  __ Mov(z9.WithLaneSize(ls), p1.Merging(), z28.WithLaneSize(ls));
+  (masm.*macro_m)(z9.WithLaneSize(ds), p1.Merging(), z9.WithLaneSize(ss));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    // Check all lanes.
+    ASSERT_EQUAL_SVE(zd_expected, z27.WithLaneSize(ls));
+
+    // Check that constructive operations preserve their inputs.
+    ASSERT_EQUAL_SVE(z28, z29);
+
+    // Check merging predication.
+    ASSERT_EQUAL_SVE(z21.WithLaneSize(ls), z21.WithLaneSize(ls));
+
+    // Check zeroing predication.
+    ASSERT_EQUAL_SVE(z22.WithLaneSize(ls), z12.WithLaneSize(ls));
+
+    // Check in-place operation where zd == zn.
+    ASSERT_EQUAL_SVE(z21.WithLaneSize(ls), z9.WithLaneSize(ls));
+  }
+}
+
+template <size_t N, typename T>
+static void TestFPUnaryPredicatedHelper(Test* config,
+                                        int src_size_in_bits,
+                                        int dst_size_in_bits,
+                                        T (&zn_inputs)[N],
+                                        const T (&zd_expected)[N],
+                                        FPUnaryMFn macro_m,
+                                        FPUnaryZFn macro_z) {
+  uint64_t pg_inputs[] = {0xa55aa55aa55aa55a,
+                          0xa55aa55aa55aa55a,
+                          0xa55aa55aa55aa55a,
+                          0xa55aa55aa55aa55a};
+
+  TestFPUnaryPredicatedHelper(config,
+                              src_size_in_bits,
+                              dst_size_in_bits,
+                              zn_inputs,
+                              pg_inputs,
+                              zd_expected,
+                              macro_m,
+                              macro_z);
+
+  // The complementary of above precicate to get full input coverage.
+  uint64_t pg_c_inputs[] = {0x5aa55aa55aa55aa5,
+                            0x5aa55aa55aa55aa5,
+                            0x5aa55aa55aa55aa5,
+                            0x5aa55aa55aa55aa5};
+
+  TestFPUnaryPredicatedHelper(config,
+                              src_size_in_bits,
+                              dst_size_in_bits,
+                              zn_inputs,
+                              pg_c_inputs,
+                              zd_expected,
+                              macro_m,
+                              macro_z);
+}
+
+template <size_t N, typename T>
+static void TestFcvtHelper(Test* config,
+                           int src_size_in_bits,
+                           int dst_size_in_bits,
+                           T (&zn_inputs)[N],
+                           const T (&zd_expected)[N]) {
+  TestFPUnaryPredicatedHelper(config,
+                              src_size_in_bits,
+                              dst_size_in_bits,
+                              zn_inputs,
+                              zd_expected,
+                              &MacroAssembler::Fcvt,   // Merging form.
+                              &MacroAssembler::Fcvt);  // Zerging form.
+}
+
+TEST_SVE(sve_fcvt) {
+  uint64_t h_vals[] = {0x7c00,
+                       0xfc00,
+                       0,
+                       0x8000,
+                       0x7bff,   // Max half precision.
+                       0x0400,   // Min positive normal.
+                       0x03ff,   // Max subnormal.
+                       0x0001};  // Min positive subnormal.
+
+  uint64_t s_vals[] = {0x7f800000,
+                       0xff800000,
+                       0,
+                       0x80000000,
+                       0x477fe000,
+                       0x38800000,
+                       0x387fc000,
+                       0x33800000};
+
+  uint64_t d_vals[] = {0x7ff0000000000000,
+                       0xfff0000000000000,
+                       0,
+                       0x8000000000000000,
+                       0x40effc0000000000,
+                       0x3f10000000000000,
+                       0x3f0ff80000000000,
+                       0x3e70000000000000};
+
+  TestFcvtHelper(config, kHRegSize, kSRegSize, h_vals, s_vals);
+  TestFcvtHelper(config, kSRegSize, kHRegSize, s_vals, h_vals);
+  TestFcvtHelper(config, kSRegSize, kDRegSize, s_vals, d_vals);
+  TestFcvtHelper(config, kDRegSize, kSRegSize, d_vals, s_vals);
+  TestFcvtHelper(config, kHRegSize, kDRegSize, h_vals, d_vals);
+  TestFcvtHelper(config, kDRegSize, kHRegSize, d_vals, h_vals);
+}
+
+TEST_SVE(sve_fcvt_nan) {
+  uint64_t h_inputs[] = {0x7e55,   // Quiet NaN.
+                         0x7c22};  // Signalling NaN.
+
+  uint64_t h2s_expected[] = {0x7fcaa000, 0x7fc44000};
+
+  uint64_t h2d_expected[] = {0x7ff9540000000000, 0x7ff8880000000000};
+
+  uint64_t s_inputs[] = {0x7fc12345,   // Quiet NaN.
+                         0x7f812345};  // Signalling NaN.
+
+  uint64_t s2h_expected[] = {0x7e09, 0x7e09};
+
+  uint64_t s2d_expected[] = {0x7ff82468a0000000, 0x7ff82468a0000000};
+
+  uint64_t d_inputs[] = {0x7ffaaaaa22222222,   // Quiet NaN.
+                         0x7ff5555511111111};  // Signalling NaN.
+
+  uint64_t d2h_expected[] = {0x7eaa, 0x7f55};
+
+  uint64_t d2s_expected[] = {0x7fd55551, 0x7feaaaa8};
+
+  TestFcvtHelper(config, kHRegSize, kSRegSize, h_inputs, h2s_expected);
+  TestFcvtHelper(config, kSRegSize, kHRegSize, s_inputs, s2h_expected);
+  TestFcvtHelper(config, kHRegSize, kDRegSize, h_inputs, h2d_expected);
+  TestFcvtHelper(config, kDRegSize, kHRegSize, d_inputs, d2h_expected);
+  TestFcvtHelper(config, kSRegSize, kDRegSize, s_inputs, s2d_expected);
+  TestFcvtHelper(config, kDRegSize, kSRegSize, d_inputs, d2s_expected);
+}
+
+template <size_t N, typename T>
+static void TestFrecpxHelper(Test* config,
+                             int lane_size_in_bits,
+                             T (&zn_inputs)[N],
+                             const T (&zd_expected)[N]) {
+  TestFPUnaryPredicatedHelper(config,
+                              lane_size_in_bits,
+                              lane_size_in_bits,
+                              zn_inputs,
+                              zd_expected,
+                              &MacroAssembler::Frecpx,   // Merging form.
+                              &MacroAssembler::Frecpx);  // Zerging form.
+}
+
+TEST_SVE(sve_frecpx_h) {
+  uint64_t zn_inputs[] = {Float16ToRawbits(kFP16PositiveInfinity),
+                          Float16ToRawbits(kFP16NegativeInfinity),
+                          Float16ToRawbits(Float16(0.0)),
+                          Float16ToRawbits(Float16(-0.0)),
+                          0x0001,   // Smallest positive subnormal number.
+                          0x03ff,   // Largest subnormal number.
+                          0x0400,   // Smallest positive normal number.
+                          0x7bff,   // Largest normal number.
+                          0x3bff,   // Largest number less than one.
+                          0x3c01,   // Smallest number larger than one.
+                          0x7c22,   // Signalling NaN.
+                          0x7e55};  // Quiet NaN.
+
+  uint64_t zd_expected[] = {0,
+                            0x8000,
+                            0x7800,
+                            0xf800,
+                            // Exponent of subnormal numbers are zero.
+                            0x7800,
+                            0x7800,
+                            0x7800,
+                            0x0400,
+                            0x4400,
+                            0x4000,
+                            0x7e22,  // To quiet NaN.
+                            0x7e55};
+
+  TestFrecpxHelper(config, kHRegSize, zn_inputs, zd_expected);
+}
+
+TEST_SVE(sve_frecpx_s) {
+  uint64_t zn_inputs[] = {FloatToRawbits(kFP32PositiveInfinity),
+                          FloatToRawbits(kFP32NegativeInfinity),
+                          FloatToRawbits(65504),       // Max half precision.
+                          FloatToRawbits(6.10352e-5),  // Min positive normal.
+                          FloatToRawbits(6.09756e-5),  // Max subnormal.
+                          FloatToRawbits(
+                              5.96046e-8),       // Min positive subnormal.
+                          FloatToRawbits(5e-9),  // Not representable -> zero.
+                          FloatToRawbits(-0.0),
+                          FloatToRawbits(0.0),
+                          0x7f952222,   // Signalling NaN.
+                          0x7fea2222};  // Quiet NaN;
+
+  uint64_t zd_expected[] = {0,           // 0.0
+                            0x80000000,  // -0.0
+                            0x38800000,  // 6.10352e-05
+                            0x47000000,  // 32768
+                            0x47800000,  // 65536
+                            0x4c800000,  // 6.71089e+07
+                            0x4e000000,  // 5.36871e+08
+                            0xff000000,  // -1.70141e+38
+                            0x7f000000,  // 1.70141e+38
+                            0x7fd52222,
+                            0x7fea2222};
+
+  TestFrecpxHelper(config, kSRegSize, zn_inputs, zd_expected);
+}
+
+TEST_SVE(sve_frecpx_d) {
+  uint64_t zn_inputs[] = {DoubleToRawbits(kFP64PositiveInfinity),
+                          DoubleToRawbits(kFP64NegativeInfinity),
+                          DoubleToRawbits(65504),       // Max half precision.
+                          DoubleToRawbits(6.10352e-5),  // Min positive normal.
+                          DoubleToRawbits(6.09756e-5),  // Max subnormal.
+                          DoubleToRawbits(
+                              5.96046e-8),        // Min positive subnormal.
+                          DoubleToRawbits(5e-9),  // Not representable -> zero.
+                          DoubleToRawbits(-0.0),
+                          DoubleToRawbits(0.0),
+                          0x7ff5555511111111,   // Signalling NaN.
+                          0x7ffaaaaa11111111};  // Quiet NaN;
+
+  uint64_t zd_expected[] = {0,                   // 0.0
+                            0x8000000000000000,  // -0.0
+                            0x3f10000000000000,  // 6.10352e-05
+                            0x40e0000000000000,  // 32768
+                            0x40f0000000000000,  // 65536
+                            0x4190000000000000,  // 6.71089e+07
+                            0x41c0000000000000,  // 5.36871e+08
+                            0xffe0000000000000,  // -1.70141e+38
+                            0x7fe0000000000000,  // 1.70141e+38
+                            0x7ffd555511111111,
+                            0x7ffaaaaa11111111};
+
+  TestFrecpxHelper(config, kDRegSize, zn_inputs, zd_expected);
+}
+
+template <size_t N, typename T>
+static void TestFsqrtHelper(Test* config,
+                            int lane_size_in_bits,
+                            T (&zn_inputs)[N],
+                            const T (&zd_expected)[N]) {
+  TestFPUnaryPredicatedHelper(config,
+                              lane_size_in_bits,
+                              lane_size_in_bits,
+                              zn_inputs,
+                              zd_expected,
+                              &MacroAssembler::Fsqrt,   // Merging form.
+                              &MacroAssembler::Fsqrt);  // Zerging form.
+}
+
+TEST_SVE(sve_fsqrt_h) {
+  uint64_t zn_inputs[] =
+      {Float16ToRawbits(Float16(0.0)),
+       Float16ToRawbits(Float16(-0.0)),
+       Float16ToRawbits(Float16(1.0)),
+       Float16ToRawbits(Float16(65025.0)),
+       Float16ToRawbits(kFP16PositiveInfinity),
+       Float16ToRawbits(kFP16NegativeInfinity),
+       Float16ToRawbits(Float16(6.10352e-5)),  // Min normal positive.
+       Float16ToRawbits(Float16(65504.0)),     // Max normal positive float.
+       Float16ToRawbits(Float16(6.09756e-5)),  // Max subnormal.
+       Float16ToRawbits(Float16(5.96046e-8)),  // Min subnormal positive.
+       0x7c22,                                 // Signaling NaN
+       0x7e55};                                // Quiet NaN
+
+  uint64_t zd_expected[] = {Float16ToRawbits(Float16(0.0)),
+                            Float16ToRawbits(Float16(-0.0)),
+                            Float16ToRawbits(Float16(1.0)),
+                            Float16ToRawbits(Float16(255.0)),
+                            Float16ToRawbits(kFP16PositiveInfinity),
+                            Float16ToRawbits(kFP16DefaultNaN),
+                            0x2000,
+                            0x5bff,
+                            0x1fff,
+                            0x0c00,
+                            0x7e22,  // To quiet NaN.
+                            0x7e55};
+
+  TestFsqrtHelper(config, kHRegSize, zn_inputs, zd_expected);
+}
+
+TEST_SVE(sve_fsqrt_s) {
+  uint64_t zn_inputs[] = {FloatToRawbits(0.0f),
+                          FloatToRawbits(-0.0f),
+                          FloatToRawbits(1.0f),
+                          FloatToRawbits(65536.0f),
+                          FloatToRawbits(kFP32PositiveInfinity),
+                          FloatToRawbits(kFP32NegativeInfinity),
+                          0x00800000,   // Min normal positive, ~1.17e−38
+                          0x7f7fffff,   // Max normal positive, ~3.40e+38
+                          0x00000001,   // Min subnormal positive, ~1.40e−45
+                          0x007fffff,   // Max subnormal, ~1.17e−38
+                          0x7f951111,   // Signaling NaN
+                          0x7fea1111};  // Quiet NaN
+
+  uint64_t zd_expected[] = {FloatToRawbits(0.0f),
+                            FloatToRawbits(-0.0f),
+                            FloatToRawbits(1.0f),
+                            FloatToRawbits(256.0f),
+                            FloatToRawbits(kFP32PositiveInfinity),
+                            FloatToRawbits(kFP32DefaultNaN),
+                            0x20000000,  // ~1.08e-19
+                            0x5f7fffff,  // ~1.84e+19
+                            0x1a3504f3,  // ~3.74e-23
+                            0x1fffffff,  // ~1.08e-19
+                            0x7fd51111,  // To quiet NaN.
+                            0x7fea1111};
+
+  TestFsqrtHelper(config, kSRegSize, zn_inputs, zd_expected);
+}
+
+TEST_SVE(sve_fsqrt_d) {
+  uint64_t zn_inputs[] =
+      {DoubleToRawbits(0.0),
+       DoubleToRawbits(-0.0),
+       DoubleToRawbits(1.0),
+       DoubleToRawbits(65536.0),
+       DoubleToRawbits(kFP64PositiveInfinity),
+       DoubleToRawbits(kFP64NegativeInfinity),
+       0x0010000000000000,  // Min normal positive, ~2.22e-308
+       0x7fefffffffffffff,  // Max normal positive, ~1.79e+308
+       0x0000000000000001,  // Min subnormal positive, 5e-324
+       0x000fffffffffffff,  // Max subnormal, ~2.22e-308
+       0x7ff5555511111111,
+       0x7ffaaaaa11111111};
+
+  uint64_t zd_expected[] = {DoubleToRawbits(0.0),
+                            DoubleToRawbits(-0.0),
+                            DoubleToRawbits(1.0),
+                            DoubleToRawbits(256.0),
+                            DoubleToRawbits(kFP64PositiveInfinity),
+                            DoubleToRawbits(kFP64DefaultNaN),
+                            0x2000000000000000,  // ~1.49e-154
+                            0x5fefffffffffffff,  // ~1.34e+154
+                            0x1e60000000000000,  // ~2.22e-162
+                            0x1fffffffffffffff,  // ~1.49e-154
+                            0x7ffd555511111111,  // To quiet NaN.
+                            0x7ffaaaaa11111111};
+
+  TestFsqrtHelper(config, kDRegSize, zn_inputs, zd_expected);
+}
+
+TEST_SVE(sve_adr) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  __ Index(z0.VnD(), 0x10000000f0000000, 0x1000);
+  __ Index(z1.VnD(), 1, 3);
+  __ Index(z2.VnS(), -1, -1);
+  __ Adr(z3.VnD(), SVEMemOperand(z0.VnD(), z1.VnD()));
+  __ Adr(z4.VnD(), SVEMemOperand(z0.VnD(), z1.VnD(), LSL, 1));
+  __ Adr(z5.VnD(), SVEMemOperand(z0.VnD(), z1.VnD(), LSL, 2));
+  __ Adr(z6.VnD(), SVEMemOperand(z0.VnD(), z1.VnD(), LSL, 3));
+  __ Adr(z7.VnD(), SVEMemOperand(z0.VnD(), z2.VnD(), UXTW));
+  __ Adr(z8.VnD(), SVEMemOperand(z0.VnD(), z2.VnD(), UXTW, 1));
+  __ Adr(z9.VnD(), SVEMemOperand(z0.VnD(), z2.VnD(), UXTW, 2));
+  __ Adr(z10.VnD(), SVEMemOperand(z0.VnD(), z2.VnD(), UXTW, 3));
+  __ Adr(z11.VnD(), SVEMemOperand(z0.VnD(), z2.VnD(), SXTW));
+  __ Adr(z12.VnD(), SVEMemOperand(z0.VnD(), z2.VnD(), SXTW, 1));
+  __ Adr(z13.VnD(), SVEMemOperand(z0.VnD(), z2.VnD(), SXTW, 2));
+  __ Adr(z14.VnD(), SVEMemOperand(z0.VnD(), z2.VnD(), SXTW, 3));
+  __ Adr(z15.VnS(), SVEMemOperand(z0.VnS(), z2.VnS()));
+  __ Adr(z16.VnS(), SVEMemOperand(z0.VnS(), z2.VnS(), LSL, 1));
+  __ Adr(z17.VnS(), SVEMemOperand(z0.VnS(), z2.VnS(), LSL, 2));
+  __ Adr(z18.VnS(), SVEMemOperand(z0.VnS(), z2.VnS(), LSL, 3));
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+    uint64_t expected_z3[] = {0x10000000f0001004, 0x10000000f0000001};
+    uint64_t expected_z4[] = {0x10000000f0001008, 0x10000000f0000002};
+    uint64_t expected_z5[] = {0x10000000f0001010, 0x10000000f0000004};
+    uint64_t expected_z6[] = {0x10000000f0001020, 0x10000000f0000008};
+    uint64_t expected_z7[] = {0x10000001f0000ffd, 0x10000001efffffff};
+    uint64_t expected_z8[] = {0x10000002f0000ffa, 0x10000002effffffe};
+    uint64_t expected_z9[] = {0x10000004f0000ff4, 0x10000004effffffc};
+    uint64_t expected_z10[] = {0x10000008f0000fe8, 0x10000008effffff8};
+    uint64_t expected_z11[] = {0x10000000f0000ffd, 0x10000000efffffff};
+    uint64_t expected_z12[] = {0x10000000f0000ffa, 0x10000000effffffe};
+    uint64_t expected_z13[] = {0x10000000f0000ff4, 0x10000000effffffc};
+    uint64_t expected_z14[] = {0x10000000f0000fe8, 0x10000000effffff8};
+    uint64_t expected_z15[] = {0x0ffffffcf0000ffd, 0x0ffffffeefffffff};
+    uint64_t expected_z16[] = {0x0ffffff8f0000ffa, 0x0ffffffceffffffe};
+    uint64_t expected_z17[] = {0x0ffffff0f0000ff4, 0x0ffffff8effffffc};
+    uint64_t expected_z18[] = {0x0fffffe0f0000fe8, 0x0ffffff0effffff8};
+
+    ASSERT_EQUAL_SVE(expected_z3, z3.VnD());
+    ASSERT_EQUAL_SVE(expected_z4, z4.VnD());
+    ASSERT_EQUAL_SVE(expected_z5, z5.VnD());
+    ASSERT_EQUAL_SVE(expected_z6, z6.VnD());
+    ASSERT_EQUAL_SVE(expected_z7, z7.VnD());
+    ASSERT_EQUAL_SVE(expected_z8, z8.VnD());
+    ASSERT_EQUAL_SVE(expected_z9, z9.VnD());
+    ASSERT_EQUAL_SVE(expected_z10, z10.VnD());
+    ASSERT_EQUAL_SVE(expected_z11, z11.VnD());
+    ASSERT_EQUAL_SVE(expected_z12, z12.VnD());
+    ASSERT_EQUAL_SVE(expected_z13, z13.VnD());
+    ASSERT_EQUAL_SVE(expected_z14, z14.VnD());
+    ASSERT_EQUAL_SVE(expected_z15, z15.VnD());
+    ASSERT_EQUAL_SVE(expected_z16, z16.VnD());
+    ASSERT_EQUAL_SVE(expected_z17, z17.VnD());
+    ASSERT_EQUAL_SVE(expected_z18, z18.VnD());
+  }
+}
+
+// Test loads and broadcast by comparing them with the result of a set of
+// equivalent scalar loads.
+template <typename F>
+static void LoadBcastHelper(Test* config,
+                            unsigned msize_in_bits,
+                            unsigned esize_in_bits,
+                            F sve_ld1,
+                            bool is_signed) {
+  VIXL_ASSERT((esize_in_bits == kBRegSize) || (esize_in_bits == kHRegSize) ||
+              (esize_in_bits == kSRegSize) || (esize_in_bits == kDRegSize));
+  static const unsigned kMaxLaneCount = kZRegMaxSize / kBRegSize;
+
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+  START();
+
+  unsigned msize_in_bytes = msize_in_bits / kBitsPerByte;
+  unsigned esize_in_bytes = esize_in_bits / kBitsPerByte;
+  int vl = config->sve_vl_in_bytes();
+
+  uint64_t offsets[kMaxLaneCount];
+  uint64_t buffer_size = vl * 64;
+  uint64_t data = reinterpret_cast<uintptr_t>(malloc(buffer_size));
+  BufferFillingHelper(data,
+                      buffer_size,
+                      msize_in_bytes,
+                      kMaxLaneCount,
+                      offsets);
+
+  for (unsigned i = 0; i < (kMaxLaneCount / 2); i++) {
+    // Assign encodable offsets into the first part of the offset array so
+    // that both encodable and unencodable offset can be tested.
+    // Note that the encoding bit range of immediate offset is 6 bits.
+    offsets[i] = (offsets[i] % (UINT64_C(1) << 6)) * msize_in_bytes;
+  }
+
+  ZRegister zn = z0.WithLaneSize(esize_in_bits);
+  ZRegister zn_ref = z4.WithLaneSize(esize_in_bits);
+
+  PRegisterZ pg = p0.Zeroing();
+  Initialise(&masm,
+             pg,
+             0x9abcdef012345678,
+             0xabcdef0123456789,
+             0xf4f3f1f0fefdfcfa,
+             0xf9f8f6f5f3f2f0ff);
+
+  __ Mov(x2, data);
+  uint64_t enablable_offset = offsets[0];
+  // Simple check if the operation correct in a single offset.
+  (masm.*sve_ld1)(zn, pg, SVEMemOperand(x2, enablable_offset));
+
+  // Generate a reference result using scalar loads.
+  uint64_t address = data + enablable_offset;
+  uint64_t duplicated_addresses[kMaxLaneCount];
+  for (unsigned i = 0; i < kMaxLaneCount; i++) {
+    duplicated_addresses[i] = address;
+  }
+
+  ScalarLoadHelper(&masm,
+                   vl,
+                   duplicated_addresses,
+                   zn_ref,
+                   pg,
+                   esize_in_bits,
+                   msize_in_bits,
+                   is_signed);
+
+  ZRegister zn_agg = z10.WithLaneSize(esize_in_bits);
+  ZRegister zn_agg_ref = z11.WithLaneSize(esize_in_bits);
+  ZRegister zn_temp = z12.WithLaneSize(esize_in_bits);
+
+  __ Dup(zn_agg, 0);
+  __ Dup(zn_agg_ref, 0);
+
+  // Check if the operation correct in different offsets.
+  for (unsigned i = 0; i < (vl / esize_in_bytes); i++) {
+    (masm.*sve_ld1)(zn_temp, pg, SVEMemOperand(x2, offsets[i]));
+    __ Lastb(x1, pg, zn_temp);
+    __ Insr(zn_agg, x1);
+
+    __ Mov(x3, data + offsets[i]);
+    ScalarLoadHelper(&masm, x1, x3, msize_in_bits, is_signed);
+    __ Insr(zn_agg_ref, x1);
+  }
+
+  END();
+
+  if (CAN_RUN()) {
+    RUN();
+
+    ASSERT_EQUAL_SVE(zn_ref, zn);
+    ASSERT_EQUAL_SVE(zn_agg_ref, zn_agg);
+  }
+
+  free(reinterpret_cast<void*>(data));
+}
+
+TEST_SVE(sve_ld1rb) {
+  LoadBcastHelper(config, kBRegSize, kBRegSize, &MacroAssembler::Ld1rb, false);
+  LoadBcastHelper(config, kBRegSize, kHRegSize, &MacroAssembler::Ld1rb, false);
+  LoadBcastHelper(config, kBRegSize, kSRegSize, &MacroAssembler::Ld1rb, false);
+  LoadBcastHelper(config, kBRegSize, kDRegSize, &MacroAssembler::Ld1rb, false);
+}
+
+TEST_SVE(sve_ld1rh) {
+  LoadBcastHelper(config, kHRegSize, kHRegSize, &MacroAssembler::Ld1rh, false);
+  LoadBcastHelper(config, kHRegSize, kSRegSize, &MacroAssembler::Ld1rh, false);
+  LoadBcastHelper(config, kHRegSize, kDRegSize, &MacroAssembler::Ld1rh, false);
+}
+
+TEST_SVE(sve_ld1rw) {
+  LoadBcastHelper(config, kSRegSize, kSRegSize, &MacroAssembler::Ld1rw, false);
+  LoadBcastHelper(config, kSRegSize, kDRegSize, &MacroAssembler::Ld1rw, false);
+}
+
+TEST_SVE(sve_ld1rd) {
+  LoadBcastHelper(config, kDRegSize, kDRegSize, &MacroAssembler::Ld1rd, false);
+}
+
+TEST_SVE(sve_ld1rsb) {
+  LoadBcastHelper(config, kBRegSize, kHRegSize, &MacroAssembler::Ld1rsb, true);
+  LoadBcastHelper(config, kBRegSize, kSRegSize, &MacroAssembler::Ld1rsb, true);
+  LoadBcastHelper(config, kBRegSize, kDRegSize, &MacroAssembler::Ld1rsb, true);
+}
+
+TEST_SVE(sve_ld1rsh) {
+  LoadBcastHelper(config, kHRegSize, kSRegSize, &MacroAssembler::Ld1rsh, true);
+  LoadBcastHelper(config, kHRegSize, kDRegSize, &MacroAssembler::Ld1rsh, true);
+}
+
+TEST_SVE(sve_ld1rsw) {
+  LoadBcastHelper(config, kSRegSize, kDRegSize, &MacroAssembler::Ld1rsw, true);
+}
+
+TEST_SVE(sve_prefetch_offset) {
+  SVE_SETUP_WITH_FEATURES(CPUFeatures::kSVE);
+
+  START();
+
+  __ Prfb(PLDL1KEEP, p5, SVEMemOperand(z30.VnS(), 0));
+  __ Prfb(PLDL1STRM, p5, SVEMemOperand(x28, -11, SVE_MUL_VL));
+  __ Prfb(PLDL2KEEP, p6, SVEMemOperand(x30, x29));
+  __ Prfb(PLDL2STRM, p6, SVEMemOperand(x7, z12.VnS(), UXTW));
+  __ Prfh(PSTL2KEEP, p6, SVEMemOperand(z0.VnS(), 28));
+  __ Prfh(PSTL2STRM, p4, SVEMemOperand(x17, -3, SVE_MUL_VL));
+  __ Prfh(PSTL3KEEP, p3, SVEMemOperand(x0, x0, LSL, 1));
+  __ Prfh(PSTL3STRM, p4, SVEMemOperand(x20, z0.VnD(), LSL, 1));
+  __ Prfw(PLDL1KEEP, p3, SVEMemOperand(z23.VnD(), 5));
+  __ Prfw(PLDL1STRM, p1, SVEMemOperand(x4, 10, SVE_MUL_VL));
+  __ Prfw(PLDL2KEEP, p2, SVEMemOperand(x22, x22, LSL, 2));
+  __ Prfw(PLDL2STRM, p1, SVEMemOperand(x2, z6.VnS(), SXTW, 2));
+  __ Prfd(PLDL3KEEP, p5, SVEMemOperand(z11.VnD(), 9));
+  __ Prfd(PLDL3STRM, p3, SVEMemOperand(x0, -24, SVE_MUL_VL));
+  __ Prfd(PSTL1KEEP, p7, SVEMemOperand(x5, x5, LSL, 3));
+  __ Prfd(PSTL1STRM, p1, SVEMemOperand(x19, z18.VnS(), SXTW, 3));
+
+  END();
+  if (CAN_RUN()) {
+    RUN();
+  }
+}
+
+}  // namespace aarch64
+}  // namespace vixl
diff --git a/test/aarch64/test-disasm-aarch64.cc b/test/aarch64/test-disasm-aarch64.cc
index 065459a7..4c5f5951 100644
--- a/test/aarch64/test-disasm-aarch64.cc
+++ b/test/aarch64/test-disasm-aarch64.cc
@@ -92,6 +92,19 @@ TEST(mov_mvn) {
   CLEANUP();
 }
 
+TEST(mvn_macro) {
+  SETUP();
+
+  // Mvn uses the destination register as a scratch if it can. This only occurs
+  // when `operand.IsExtendedRegister()`.
+  COMPARE_MACRO(Mvn(x0, Operand(w1, SXTW)),
+                "sxtw x0, w1\n"
+                "mvn x0, x0");
+  COMPARE_MACRO(Mvn(x0, Operand(x0, SXTW)),
+                "sxtw x0, w0\n"
+                "mvn x0, x0");
+}
+
 
 TEST(move_immediate) {
   SETUP();
@@ -1955,11 +1968,10 @@ TEST(prfm_operations) {
   const int expected_count = sizeof(expected) / sizeof(expected[0]);
   VIXL_STATIC_ASSERT((1 << ImmPrefetchOperation_width) == expected_count);
 
-  for (int i = 0; i < (1 << ImmPrefetchOperation_width); i++) {
-    PrefetchOperation op = static_cast<PrefetchOperation>(i);
-    COMPARE_PREFIX(prfm(op, INT64_C(0)), expected[i]);
-    COMPARE_PREFIX(prfm(op, MemOperand(x0, 0)), expected[i]);
-    COMPARE_PREFIX(prfm(op, MemOperand(x0, x1)), expected[i]);
+  for (int op = 0; op < (1 << ImmPrefetchOperation_width); op++) {
+    COMPARE_PREFIX(prfm(op, INT64_C(0)), expected[op]);
+    COMPARE_PREFIX(prfm(op, MemOperand(x0, 0)), expected[op]);
+    COMPARE_PREFIX(prfm(op, MemOperand(x0, x1)), expected[op]);
   }
 
   CLEANUP();
@@ -1986,9 +1998,8 @@ TEST(prfum_operations) {
   const int expected_count = sizeof(expected) / sizeof(expected[0]);
   VIXL_STATIC_ASSERT((1 << ImmPrefetchOperation_width) == expected_count);
 
-  for (int i = 0; i < (1 << ImmPrefetchOperation_width); i++) {
-    PrefetchOperation op = static_cast<PrefetchOperation>(i);
-    COMPARE_PREFIX(prfum(op, MemOperand(x0, 0)), expected[i]);
+  for (int op = 0; op < (1 << ImmPrefetchOperation_width); op++) {
+    COMPARE_PREFIX(prfum(op, MemOperand(x0, 0)), expected[op]);
   }
 
   CLEANUP();
@@ -2743,6 +2754,53 @@ TEST(add_sub_negative) {
   CLEANUP();
 }
 
+TEST(add_sub_macro) {
+  SETUP();
+
+  // Add and Sub use their destination register as a scratch if they can.
+  COMPARE_MACRO(Add(x0, x1, 0x4242),
+                "mov x0, #0x4242\n"
+                "add x0, x1, x0");
+  COMPARE_MACRO(Add(x0, x0, 0x4242),
+                "mov x16, #0x4242\n"
+                "add x0, x0, x16");
+  COMPARE_MACRO(Adds(x0, xzr, Operand(w1, SXTW)),
+                "sxtw x0, w1\n"
+                "adds x0, xzr, x0");
+  COMPARE_MACRO(Sub(x0, x1, 0x4242),
+                "mov x0, #0x4242\n"
+                "sub x0, x1, x0");
+  COMPARE_MACRO(Sub(x0, x0, 0x4242),
+                "mov x16, #0x4242\n"
+                "sub x0, x0, x16");
+  COMPARE_MACRO(Subs(x0, xzr, Operand(w1, SXTW)),
+                "sxtw x0, w1\n"
+                "negs x0, x0");
+}
+
+TEST(adc_sbc_macro) {
+  SETUP();
+
+  // Adc and Sbc use their destination register as a scratch if they can.
+  COMPARE_MACRO(Adc(x0, x1, 0x4242),
+                "mov x0, #0x4242\n"
+                "adc x0, x1, x0");
+  COMPARE_MACRO(Adc(x0, x0, 0x4242),
+                "mov x16, #0x4242\n"
+                "adc x0, x0, x16");
+  COMPARE_MACRO(Adcs(x0, xzr, Operand(w1, SXTW)),
+                "sxtw x0, w1\n"
+                "adcs x0, xzr, x0");
+  COMPARE_MACRO(Sbc(x0, x1, 0x4242),
+                "mov x0, #0x4242\n"
+                "sbc x0, x1, x0");
+  COMPARE_MACRO(Sbc(x0, x0, 0x4242),
+                "mov x16, #0x4242\n"
+                "sbc x0, x0, x16");
+  COMPARE_MACRO(Sbcs(x0, xzr, Operand(w1, SXTW)),
+                "sxtw x0, w1\n"
+                "ngcs x0, x0");
+}
 
 TEST(logical_immediate_move) {
   SETUP();
@@ -2793,6 +2851,29 @@ TEST(logical_immediate_move) {
   CLEANUP();
 }
 
+TEST(logical_macro) {
+  SETUP();
+
+  // LogicalMacro uses the destination register as a scratch if it can.
+  COMPARE_MACRO(And(x0, x1, 0x4242),
+                "mov x0, #0x4242\n"
+                "and x0, x1, x0");
+  COMPARE_MACRO(Bic(x0, x0, 0x4242),
+                "mov x16, #0xffffffffffffbdbd\n"
+                "and x0, x0, x16");
+  COMPARE_MACRO(Orn(x0, xzr, Operand(w1, SXTW)),
+                "sxtw x0, w1\n"
+                "mvn x0, x0");
+  COMPARE_MACRO(Orr(x0, x1, 0x4242),
+                "mov x0, #0x4242\n"
+                "orr x0, x1, x0");
+  COMPARE_MACRO(Ands(x0, x0, 0x4242),
+                "mov x16, #0x4242\n"
+                "ands x0, x0, x16");
+  COMPARE_MACRO(Tst(xzr, Operand(w1, SXTW)),
+                "sxtw x16, w1\n"
+                "tst xzr, x16");
+}
 
 TEST(barriers) {
   SETUP();
@@ -2967,11 +3048,11 @@ TEST(bti) {
   COMPARE(hint(BTI_j), "bti j");
   COMPARE(hint(BTI_jc), "bti jc");
 
-  Label dummy1, dummy2, dummy3, dummy4;
-  COMPARE_MACRO(Bind(&dummy1, EmitBTI), "bti");
-  COMPARE_MACRO(Bind(&dummy2, EmitBTI_c), "bti c");
-  COMPARE_MACRO(Bind(&dummy3, EmitBTI_j), "bti j");
-  COMPARE_MACRO(Bind(&dummy4, EmitBTI_jc), "bti jc");
+  Label placeholder1, placeholder2, placeholder3, placeholder4;
+  COMPARE_MACRO(Bind(&placeholder1, EmitBTI), "bti");
+  COMPARE_MACRO(Bind(&placeholder2, EmitBTI_c), "bti c");
+  COMPARE_MACRO(Bind(&placeholder3, EmitBTI_j), "bti j");
+  COMPARE_MACRO(Bind(&placeholder4, EmitBTI_jc), "bti jc");
 
   CLEANUP();
 }
diff --git a/test/aarch64/test-disasm-sve-aarch64.cc b/test/aarch64/test-disasm-sve-aarch64.cc
new file mode 100644
index 00000000..46128d91
--- /dev/null
+++ b/test/aarch64/test-disasm-sve-aarch64.cc
@@ -0,0 +1,6427 @@
+// Copyright 2019, VIXL authors
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+//   * Redistributions of source code must retain the above copyright notice,
+//     this list of conditions and the following disclaimer.
+//   * Redistributions in binary form must reproduce the above copyright notice,
+//     this list of conditions and the following disclaimer in the documentation
+//     and/or other materials provided with the distribution.
+//   * Neither the name of ARM Limited nor the names of its contributors may be
+//     used to endorse or promote products derived from this software without
+//     specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
+// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+#include <cstdio>
+#include <cstring>
+#include <string>
+
+#include "test-runner.h"
+#include "aarch64/test-utils-aarch64.h"
+
+#include "aarch64/disasm-aarch64.h"
+#include "aarch64/macro-assembler-aarch64.h"
+#include "test-disasm-aarch64.h"
+#include "test-utils-aarch64.h"
+
+namespace vixl {
+namespace aarch64 {
+
+TEST(sve) {
+  SETUP();
+
+  // TODO: Replace these tests when the disassembler is more capable.
+  COMPARE_PREFIX(asrr(z0.VnB(), p7.Merging(), z0.VnB(), z1.VnB()),
+                 "asrr z0.b, p7/m, z0.b, z1.b");
+  COMPARE_PREFIX(fcmeq(p6.VnD(), p7.Zeroing(), z0.VnD(), z1.VnD()),
+                 "fcmeq p6.d, p7/z, z0.d, z1.d");
+  COMPARE_PREFIX(mla(z0.VnB(), p7.Merging(), z0.VnB(), z1.VnB()),
+                 "mla z0.b, p7/m, z0.b, z1.b");
+  COMPARE_PREFIX(mla(z1.VnS(), p7.Merging(), z1.VnS(), z0.VnS()),
+                 "mla z1.s, p7/m, z1.s, z0.s");
+  COMPARE_PREFIX(asr(z1.VnB(), z0.VnB(), 8), "asr z1.b, z0.b, #8");
+  COMPARE_PREFIX(lsl(z0.VnH(), z1.VnH(), 15), "lsl z0.h, z1.h, #15");
+  COMPARE_PREFIX(lsr(z1.VnS(), z0.VnS(), 32), "lsr z1.s, z0.s, #32");
+  COMPARE_PREFIX(and_(p6.VnB(), p7.Zeroing(), p6.VnB(), p7.VnB()),
+                 "and p6.b, p7/z, p6.b, p7.b");
+  COMPARE_PREFIX(rev(p7.VnB(), p6.VnB()), "rev p7.b, p6.b");
+  COMPARE_PREFIX(splice(z0.VnH(), p7, z0.VnH(), z1.VnH()),
+                 "splice z0.h, p7, z0.h, z1.h");
+  COMPARE_PREFIX(fnmad(z0.VnD(), p6.Merging(), z1.VnD(), z0.VnD()),
+                 "fnmad z0.d, p6/m, z1.d, z0.d");
+
+  CLEANUP();
+}
+
+TEST(sve_address_generation) {
+  SETUP();
+
+#if 0
+  COMPARE_PREFIX(adr(z19.VnD(), z22.VnD(), z11.VnD()), "adr <Zd>.D, [<Zn>.D, <Zm>.D, SXTW{<amount>}]");
+  COMPARE_PREFIX(adr(z30.VnD(), z14.VnD(), z24.VnD()), "adr <Zd>.D, [<Zn>.D, <Zm>.D, UXTW{<amount>}]");
+  COMPARE_PREFIX(adr(z8.Vn?(), z16.Vn?(), z16.Vn?()), "adr <Zd>.<T>, [<Zn>.<T>, <Zm>.<T>{, <mod> <amount>}]");
+#endif
+  COMPARE_PREFIX(adr(z19.VnD(), SVEMemOperand(z22.VnD(), z11.VnD(), SXTW)),
+                 "adr z19.d, [z22.d, z11.d, sxtw]");
+  COMPARE_PREFIX(adr(z19.VnD(), SVEMemOperand(z22.VnD(), z11.VnD(), SXTW, 1)),
+                 "adr z19.d, [z22.d, z11.d, sxtw #1]");
+  COMPARE_PREFIX(adr(z19.VnD(), SVEMemOperand(z22.VnD(), z11.VnD(), SXTW, 2)),
+                 "adr z19.d, [z22.d, z11.d, sxtw #2]");
+  COMPARE_PREFIX(adr(z19.VnD(), SVEMemOperand(z22.VnD(), z11.VnD(), SXTW, 3)),
+                 "adr z19.d, [z22.d, z11.d, sxtw #3]");
+  COMPARE_PREFIX(adr(z30.VnD(), SVEMemOperand(z14.VnD(), z16.VnD(), UXTW)),
+                 "adr z30.d, [z14.d, z16.d, uxtw]");
+  COMPARE_PREFIX(adr(z30.VnD(), SVEMemOperand(z14.VnD(), z16.VnD(), UXTW, 1)),
+                 "adr z30.d, [z14.d, z16.d, uxtw #1]");
+  COMPARE_PREFIX(adr(z30.VnD(), SVEMemOperand(z14.VnD(), z16.VnD(), UXTW, 2)),
+                 "adr z30.d, [z14.d, z16.d, uxtw #2]");
+  COMPARE_PREFIX(adr(z30.VnD(), SVEMemOperand(z14.VnD(), z16.VnD(), UXTW, 3)),
+                 "adr z30.d, [z14.d, z16.d, uxtw #3]");
+  COMPARE_PREFIX(adr(z8.VnS(), SVEMemOperand(z16.VnS(), z16.VnS())),
+                 "adr z8.s, [z16.s, z16.s]");
+  COMPARE_PREFIX(adr(z8.VnS(), SVEMemOperand(z16.VnS(), z16.VnS(), LSL, 1)),
+                 "adr z8.s, [z16.s, z16.s, lsl #1]");
+  COMPARE_PREFIX(adr(z8.VnS(), SVEMemOperand(z16.VnS(), z16.VnS(), LSL, 2)),
+                 "adr z8.s, [z16.s, z16.s, lsl #2]");
+  COMPARE_PREFIX(adr(z8.VnS(), SVEMemOperand(z16.VnS(), z16.VnS(), LSL, 3)),
+                 "adr z8.s, [z16.s, z16.s, lsl #3]");
+  COMPARE_PREFIX(adr(z9.VnD(), SVEMemOperand(z1.VnD(), z16.VnD())),
+                 "adr z9.d, [z1.d, z16.d]");
+  COMPARE_PREFIX(adr(z9.VnD(), SVEMemOperand(z1.VnD(), z16.VnD(), LSL, 1)),
+                 "adr z9.d, [z1.d, z16.d, lsl #1]");
+  COMPARE_PREFIX(adr(z9.VnD(), SVEMemOperand(z1.VnD(), z16.VnD(), LSL, 2)),
+                 "adr z9.d, [z1.d, z16.d, lsl #2]");
+  COMPARE_PREFIX(adr(z9.VnD(), SVEMemOperand(z1.VnD(), z16.VnD(), LSL, 3)),
+                 "adr z9.d, [z1.d, z16.d, lsl #3]");
+
+
+  CLEANUP();
+}
+
+TEST(sve_calculate_sve_address) {
+  // Shadow the `MacroAssembler` type so that the test macros work without
+  // modification.
+  typedef CalculateSVEAddressMacroAssembler MacroAssembler;
+
+  SETUP();
+
+  // It is important that we cover every branch in this test because most other
+  // tests tend not to check every code path.
+
+  // IsEquivalentToScalar()
+  COMPARE_MACRO(CalculateSVEAddress(x0, SVEMemOperand(x1)), "mov x0, x1");
+  COMPARE_MACRO(CalculateSVEAddress(x4, SVEMemOperand(x2, 0)), "mov x4, x2");
+  COMPARE_MACRO(CalculateSVEAddress(x4, SVEMemOperand(x2, xzr, LSL, 2)),
+                "mov x4, x2");
+
+  // IsScalarPlusImmediate()
+  // Simple immediates just pass through to 'Add'.
+  COMPARE_MACRO(CalculateSVEAddress(x10, SVEMemOperand(x0, 42)),
+                "add x10, x0, #0x2a (42)");
+  COMPARE_MACRO(CalculateSVEAddress(x10, SVEMemOperand(sp, 42)),
+                "add x10, sp, #0x2a (42)");
+  // SVE_MUL_VL variants use `Addpl`, which has its own tests, but
+  // `CalculateSVEAddress` needs to check and handle the access size.
+  COMPARE_MACRO(CalculateSVEAddress(x10, SVEMemOperand(x0, 3, SVE_MUL_VL), 0),
+                "addpl x10, x0, #24");
+  COMPARE_MACRO(CalculateSVEAddress(x10, SVEMemOperand(x0, 3, SVE_MUL_VL), 1),
+                "addpl x10, x0, #12");
+  COMPARE_MACRO(CalculateSVEAddress(x10, SVEMemOperand(x0, 3, SVE_MUL_VL), 2),
+                "addpl x10, x0, #6");
+  COMPARE_MACRO(CalculateSVEAddress(x10, SVEMemOperand(x0, 3, SVE_MUL_VL), 3),
+                "addpl x10, x0, #3");
+
+  // IsScalarPlusScalar()
+  // All forms pass through to `Add`, but SVE_LSL must be handled correctly.
+  COMPARE_MACRO(CalculateSVEAddress(x22, SVEMemOperand(x2, x3)),
+                "add x22, x2, x3");
+  COMPARE_MACRO(CalculateSVEAddress(x22, SVEMemOperand(sp, x3)),
+                "add x22, sp, x3");
+  COMPARE_MACRO(CalculateSVEAddress(x22, SVEMemOperand(x2, x3, LSL, 2)),
+                "add x22, x2, x3, lsl #2");
+  COMPARE_MACRO(CalculateSVEAddress(x22, SVEMemOperand(sp, x3, LSL, 2)),
+                "add x22, sp, x3, lsl #2");
+
+  CLEANUP();
+}
+
+TEST(sve_bitwise_imm) {
+  SETUP();
+
+  // The assembler will necessarily encode an immediate in the simplest bitset.
+  COMPARE_PREFIX(and_(z2.VnD(), z2.VnD(), 0x0000ffff0000ffff),
+                 "and z2.s, z2.s, #0xffff");
+  COMPARE_PREFIX(dupm(z15.VnS(), 0x7f007f00), "dupm z15.h, #0x7f00");
+  COMPARE_PREFIX(eor(z26.VnH(), z26.VnH(), 0x7ff8),
+                 "eor z26.h, z26.h, #0x7ff8");
+  COMPARE_PREFIX(orr(z13.VnB(), z13.VnB(), 0x78), "orr z13.b, z13.b, #0x78");
+
+  // Logical aliases.
+  COMPARE_PREFIX(bic(z21.VnD(), z21.VnD(), 0xffff00000000ffff),
+                 "and z21.d, z21.d, #0xffffffff0000");
+  COMPARE_PREFIX(eon(z31.VnS(), z31.VnS(), 0x1ffe),
+                 "eor z31.s, z31.s, #0xffffe001");
+  COMPARE_PREFIX(orn(z11.VnH(), z11.VnH(), 0x2), "orr z11.h, z11.h, #0xfffd");
+
+  // Mov alias for dupm.
+  COMPARE_PREFIX(mov(z0.VnH(), 0xf00f), "mov z0.h, #0xf00f");
+  COMPARE_MACRO(Mov(z11.VnS(), 0xe0000003), "mov z11.s, #0xe0000003");
+  COMPARE_MACRO(Mov(z22.VnD(), 0x8000), "dupm z22.d, #0x8000");
+
+  // Test dupm versus mov disassembly.
+  COMPARE_PREFIX(dupm(z0.VnH(), 0xfe), "dupm z0.h, #0xfe");
+  COMPARE_PREFIX(dupm(z0.VnH(), 0xff), "dupm z0.h, #0xff");
+  COMPARE_PREFIX(dupm(z0.VnH(), 0x1fe), "mov z0.h, #0x1fe");
+  COMPARE_PREFIX(dupm(z0.VnH(), 0xfe00), "dupm z0.h, #0xfe00");
+  COMPARE_PREFIX(dupm(z0.VnH(), 0xfe01), "mov z0.h, #0xfe01");
+  COMPARE_PREFIX(dupm(z0.VnS(), 0xfe00), "dupm z0.s, #0xfe00");
+  COMPARE_PREFIX(dupm(z0.VnS(), 0xfe000001), "mov z0.s, #0xfe000001");
+  COMPARE_PREFIX(dupm(z0.VnS(), 0xffffff00), "dupm z0.s, #0xffffff00");
+  COMPARE_PREFIX(dupm(z0.VnS(), 0xffffff01), "dupm z0.s, #0xffffff01");
+  COMPARE_PREFIX(dupm(z0.VnS(), 0xfffffe01), "mov z0.s, #0xfffffe01");
+  COMPARE_PREFIX(dupm(z0.VnS(), 0xfff), "mov z0.s, #0xfff");
+  COMPARE_PREFIX(dupm(z0.VnD(), 0xffffffffffffff00),
+                 "dupm z0.d, #0xffffffffffffff00");
+  COMPARE_PREFIX(dupm(z0.VnD(), 0x7fffffffffffff80),
+                 "mov z0.d, #0x7fffffffffffff80");
+  COMPARE_PREFIX(dupm(z0.VnD(), 0x8000), "dupm z0.d, #0x8000");
+  COMPARE_PREFIX(dupm(z0.VnD(), 0x10000), "mov z0.d, #0x10000");
+
+  CLEANUP();
+}
+
+TEST(sve_bitwise_logical_unpredicated) {
+  SETUP();
+
+  COMPARE_PREFIX(and_(z12.VnD(), z5.VnD(), z29.VnD()),
+                 "and z12.d, z5.d, z29.d");
+  COMPARE_PREFIX(bic(z11.VnD(), z15.VnD(), z9.VnD()), "bic z11.d, z15.d, z9.d");
+  COMPARE_PREFIX(eor(z9.VnD(), z31.VnD(), z29.VnD()), "eor z9.d, z31.d, z29.d");
+  COMPARE_PREFIX(orr(z17.VnD(), z8.VnD(), z19.VnD()), "orr z17.d, z8.d, z19.d");
+
+  // Check mov aliases.
+  COMPARE_PREFIX(orr(z17.VnD(), z8.VnD(), z8.VnD()), "mov z17.d, z8.d");
+  COMPARE_PREFIX(mov(z18, z9), "mov z18.d, z9.d");
+  COMPARE_MACRO(Mov(z19, z10), "mov z19.d, z10.d");
+
+  CLEANUP();
+}
+
+TEST(sve_bitwise_shift_predicated) {
+  SETUP();
+
+  COMPARE_PREFIX(asrr(z20.VnB(), p3.Merging(), z20.VnB(), z11.VnB()),
+                 "asrr z20.b, p3/m, z20.b, z11.b");
+  COMPARE_PREFIX(asrr(z20.VnH(), p3.Merging(), z20.VnH(), z11.VnH()),
+                 "asrr z20.h, p3/m, z20.h, z11.h");
+  COMPARE_PREFIX(asrr(z20.VnS(), p3.Merging(), z20.VnS(), z11.VnS()),
+                 "asrr z20.s, p3/m, z20.s, z11.s");
+  COMPARE_PREFIX(asrr(z20.VnD(), p3.Merging(), z20.VnD(), z11.VnD()),
+                 "asrr z20.d, p3/m, z20.d, z11.d");
+  COMPARE_PREFIX(asr(z26.VnB(), p2.Merging(), z26.VnB(), z17.VnB()),
+                 "asr z26.b, p2/m, z26.b, z17.b");
+  COMPARE_PREFIX(asr(z26.VnH(), p2.Merging(), z26.VnH(), z17.VnH()),
+                 "asr z26.h, p2/m, z26.h, z17.h");
+  COMPARE_PREFIX(asr(z26.VnS(), p2.Merging(), z26.VnS(), z17.VnS()),
+                 "asr z26.s, p2/m, z26.s, z17.s");
+  COMPARE_PREFIX(asr(z26.VnD(), p2.Merging(), z26.VnD(), z17.VnD()),
+                 "asr z26.d, p2/m, z26.d, z17.d");
+  COMPARE_PREFIX(lslr(z30.VnB(), p1.Merging(), z30.VnB(), z26.VnB()),
+                 "lslr z30.b, p1/m, z30.b, z26.b");
+  COMPARE_PREFIX(lslr(z30.VnH(), p1.Merging(), z30.VnH(), z26.VnH()),
+                 "lslr z30.h, p1/m, z30.h, z26.h");
+  COMPARE_PREFIX(lslr(z30.VnS(), p1.Merging(), z30.VnS(), z26.VnS()),
+                 "lslr z30.s, p1/m, z30.s, z26.s");
+  COMPARE_PREFIX(lslr(z30.VnD(), p1.Merging(), z30.VnD(), z26.VnD()),
+                 "lslr z30.d, p1/m, z30.d, z26.d");
+  COMPARE_PREFIX(lsl(z14.VnB(), p6.Merging(), z14.VnB(), z25.VnB()),
+                 "lsl z14.b, p6/m, z14.b, z25.b");
+  COMPARE_PREFIX(lsl(z14.VnH(), p6.Merging(), z14.VnH(), z25.VnH()),
+                 "lsl z14.h, p6/m, z14.h, z25.h");
+  COMPARE_PREFIX(lsl(z14.VnS(), p6.Merging(), z14.VnS(), z25.VnS()),
+                 "lsl z14.s, p6/m, z14.s, z25.s");
+  COMPARE_PREFIX(lsl(z14.VnD(), p6.Merging(), z14.VnD(), z25.VnD()),
+                 "lsl z14.d, p6/m, z14.d, z25.d");
+  COMPARE_PREFIX(lsrr(z3.VnB(), p1.Merging(), z3.VnB(), z16.VnB()),
+                 "lsrr z3.b, p1/m, z3.b, z16.b");
+  COMPARE_PREFIX(lsrr(z3.VnH(), p1.Merging(), z3.VnH(), z16.VnH()),
+                 "lsrr z3.h, p1/m, z3.h, z16.h");
+  COMPARE_PREFIX(lsrr(z3.VnS(), p1.Merging(), z3.VnS(), z16.VnS()),
+                 "lsrr z3.s, p1/m, z3.s, z16.s");
+  COMPARE_PREFIX(lsrr(z3.VnD(), p1.Merging(), z3.VnD(), z16.VnD()),
+                 "lsrr z3.d, p1/m, z3.d, z16.d");
+  COMPARE_PREFIX(lsr(z29.VnB(), p7.Merging(), z29.VnB(), z13.VnB()),
+                 "lsr z29.b, p7/m, z29.b, z13.b");
+  COMPARE_PREFIX(lsr(z29.VnH(), p7.Merging(), z29.VnH(), z13.VnH()),
+                 "lsr z29.h, p7/m, z29.h, z13.h");
+  COMPARE_PREFIX(lsr(z29.VnS(), p7.Merging(), z29.VnS(), z13.VnS()),
+                 "lsr z29.s, p7/m, z29.s, z13.s");
+  COMPARE_PREFIX(lsr(z29.VnD(), p7.Merging(), z29.VnD(), z13.VnD()),
+                 "lsr z29.d, p7/m, z29.d, z13.d");
+
+  COMPARE_PREFIX(asr(z4.VnB(), p0.Merging(), z4.VnB(), z30.VnD()),
+                 "asr z4.b, p0/m, z4.b, z30.d");
+  COMPARE_PREFIX(asr(z4.VnH(), p0.Merging(), z4.VnH(), z30.VnD()),
+                 "asr z4.h, p0/m, z4.h, z30.d");
+  COMPARE_PREFIX(asr(z4.VnS(), p0.Merging(), z4.VnS(), z30.VnD()),
+                 "asr z4.s, p0/m, z4.s, z30.d");
+  COMPARE_PREFIX(lsl(z13.VnB(), p7.Merging(), z13.VnB(), z18.VnD()),
+                 "lsl z13.b, p7/m, z13.b, z18.d");
+  COMPARE_PREFIX(lsl(z13.VnH(), p7.Merging(), z13.VnH(), z18.VnD()),
+                 "lsl z13.h, p7/m, z13.h, z18.d");
+  COMPARE_PREFIX(lsl(z13.VnS(), p7.Merging(), z13.VnS(), z18.VnD()),
+                 "lsl z13.s, p7/m, z13.s, z18.d");
+  COMPARE_PREFIX(lsr(z1.VnB(), p4.Merging(), z1.VnB(), z14.VnD()),
+                 "lsr z1.b, p4/m, z1.b, z14.d");
+  COMPARE_PREFIX(lsr(z1.VnH(), p4.Merging(), z1.VnH(), z14.VnD()),
+                 "lsr z1.h, p4/m, z1.h, z14.d");
+  COMPARE_PREFIX(lsr(z1.VnS(), p4.Merging(), z1.VnS(), z14.VnD()),
+                 "lsr z1.s, p4/m, z1.s, z14.d");
+
+  COMPARE_MACRO(Asr(z4.VnB(), p0.Merging(), z4.VnB(), z30.VnB()),
+                "asr z4.b, p0/m, z4.b, z30.b");
+  COMPARE_MACRO(Asr(z4.VnB(), p0.Merging(), z30.VnB(), z4.VnB()),
+                "asrr z4.b, p0/m, z4.b, z30.b");
+  COMPARE_MACRO(Asr(z4.VnB(), p0.Merging(), z10.VnB(), z14.VnB()),
+                "movprfx z4.b, p0/m, z10.b\n"
+                "asr z4.b, p0/m, z4.b, z14.b");
+  COMPARE_MACRO(Lsl(z4.VnB(), p0.Merging(), z4.VnB(), z30.VnB()),
+                "lsl z4.b, p0/m, z4.b, z30.b");
+  COMPARE_MACRO(Lsl(z4.VnB(), p0.Merging(), z30.VnB(), z4.VnB()),
+                "lslr z4.b, p0/m, z4.b, z30.b");
+  COMPARE_MACRO(Lsl(z4.VnB(), p0.Merging(), z10.VnB(), z14.VnB()),
+                "movprfx z4.b, p0/m, z10.b\n"
+                "lsl z4.b, p0/m, z4.b, z14.b");
+  COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z4.VnB(), z30.VnB()),
+                "lsr z4.b, p0/m, z4.b, z30.b");
+  COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z30.VnB(), z4.VnB()),
+                "lsrr z4.b, p0/m, z4.b, z30.b");
+  COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z10.VnB(), z14.VnB()),
+                "movprfx z4.b, p0/m, z10.b\n"
+                "lsr z4.b, p0/m, z4.b, z14.b");
+
+  COMPARE_PREFIX(asrd(z0.VnB(), p4.Merging(), z0.VnB(), 1),
+                 "asrd z0.b, p4/m, z0.b, #1");
+  COMPARE_PREFIX(asrd(z0.VnH(), p4.Merging(), z0.VnH(), 1),
+                 "asrd z0.h, p4/m, z0.h, #1");
+  COMPARE_PREFIX(asrd(z0.VnS(), p4.Merging(), z0.VnS(), 1),
+                 "asrd z0.s, p4/m, z0.s, #1");
+  COMPARE_PREFIX(asrd(z0.VnD(), p4.Merging(), z0.VnD(), 1),
+                 "asrd z0.d, p4/m, z0.d, #1");
+  COMPARE_PREFIX(asr(z8.VnB(), p7.Merging(), z8.VnB(), 3),
+                 "asr z8.b, p7/m, z8.b, #3");
+  COMPARE_PREFIX(asr(z8.VnH(), p7.Merging(), z8.VnH(), 3),
+                 "asr z8.h, p7/m, z8.h, #3");
+  COMPARE_PREFIX(asr(z8.VnS(), p7.Merging(), z8.VnS(), 3),
+                 "asr z8.s, p7/m, z8.s, #3");
+  COMPARE_PREFIX(asr(z8.VnD(), p7.Merging(), z8.VnD(), 3),
+                 "asr z8.d, p7/m, z8.d, #3");
+  COMPARE_PREFIX(lsl(z29.VnB(), p6.Merging(), z29.VnB(), 0),
+                 "lsl z29.b, p6/m, z29.b, #0");
+  COMPARE_PREFIX(lsl(z29.VnH(), p6.Merging(), z29.VnH(), 5),
+                 "lsl z29.h, p6/m, z29.h, #5");
+  COMPARE_PREFIX(lsl(z29.VnS(), p6.Merging(), z29.VnS(), 0),
+                 "lsl z29.s, p6/m, z29.s, #0");
+  COMPARE_PREFIX(lsl(z29.VnD(), p6.Merging(), z29.VnD(), 63),
+                 "lsl z29.d, p6/m, z29.d, #63");
+  COMPARE_PREFIX(lsr(z24.VnB(), p2.Merging(), z24.VnB(), 8),
+                 "lsr z24.b, p2/m, z24.b, #8");
+  COMPARE_PREFIX(lsr(z24.VnH(), p2.Merging(), z24.VnH(), 16),
+                 "lsr z24.h, p2/m, z24.h, #16");
+  COMPARE_PREFIX(lsr(z24.VnS(), p2.Merging(), z24.VnS(), 32),
+                 "lsr z24.s, p2/m, z24.s, #32");
+  COMPARE_PREFIX(lsr(z24.VnD(), p2.Merging(), z24.VnD(), 64),
+                 "lsr z24.d, p2/m, z24.d, #64");
+
+  COMPARE_MACRO(Asrd(z0.VnB(), p4.Merging(), z8.VnB(), 1),
+                "movprfx z0.b, p4/m, z8.b\n"
+                "asrd z0.b, p4/m, z0.b, #1");
+  COMPARE_MACRO(Asr(z8.VnH(), p7.Merging(), z29.VnH(), 3),
+                "movprfx z8.h, p7/m, z29.h\n"
+                "asr z8.h, p7/m, z8.h, #3");
+  COMPARE_MACRO(Lsl(z29.VnS(), p6.Merging(), z24.VnS(), 0),
+                "movprfx z29.s, p6/m, z24.s\n"
+                "lsl z29.s, p6/m, z29.s, #0");
+  COMPARE_MACRO(Lsr(z24.VnD(), p2.Merging(), z0.VnD(), 64),
+                "movprfx z24.d, p2/m, z0.d\n"
+                "lsr z24.d, p2/m, z24.d, #64");
+
+  CLEANUP();
+}
+
+TEST(sve_bitwise_shift_unpredicated) {
+  SETUP();
+
+  // Test lsl with reserved D-sized lane field.
+  COMPARE_PREFIX(dci(0x04ef8e15), "unimplemented");
+  // Test asr with reserved tsz field.
+  COMPARE_PREFIX(dci(0x04209345), "unimplemented");
+
+  COMPARE_PREFIX(asr(z4.VnB(), z27.VnB(), 1), "asr z4.b, z27.b, #1");
+  COMPARE_PREFIX(asr(z5.VnB(), z26.VnB(), 8), "asr z5.b, z26.b, #8");
+  COMPARE_PREFIX(asr(z6.VnH(), z25.VnH(), 1), "asr z6.h, z25.h, #1");
+  COMPARE_PREFIX(asr(z7.VnH(), z24.VnH(), 16), "asr z7.h, z24.h, #16");
+  COMPARE_PREFIX(asr(z8.VnS(), z23.VnS(), 1), "asr z8.s, z23.s, #1");
+  COMPARE_PREFIX(asr(z9.VnS(), z22.VnS(), 32), "asr z9.s, z22.s, #32");
+  COMPARE_PREFIX(asr(z10.VnD(), z21.VnD(), 1), "asr z10.d, z21.d, #1");
+  COMPARE_PREFIX(asr(z11.VnD(), z20.VnD(), 64), "asr z11.d, z20.d, #64");
+  COMPARE_PREFIX(lsr(z4.VnB(), z27.VnB(), 3), "lsr z4.b, z27.b, #3");
+  COMPARE_PREFIX(lsr(z5.VnB(), z26.VnB(), 7), "lsr z5.b, z26.b, #7");
+  COMPARE_PREFIX(lsr(z6.VnH(), z25.VnH(), 8), "lsr z6.h, z25.h, #8");
+  COMPARE_PREFIX(lsr(z7.VnH(), z24.VnH(), 15), "lsr z7.h, z24.h, #15");
+  COMPARE_PREFIX(lsr(z8.VnS(), z23.VnS(), 14), "lsr z8.s, z23.s, #1");
+  COMPARE_PREFIX(lsr(z9.VnS(), z22.VnS(), 31), "lsr z9.s, z22.s, #31");
+  COMPARE_PREFIX(lsr(z10.VnD(), z21.VnD(), 30), "lsr z10.d, z21.d, #30");
+  COMPARE_PREFIX(lsr(z11.VnD(), z20.VnD(), 63), "lsr z11.d, z20.d, #63");
+  COMPARE_PREFIX(lsl(z4.VnB(), z27.VnB(), 4), "lsl z4.b, z27.b, #4");
+  COMPARE_PREFIX(lsl(z5.VnB(), z26.VnB(), 6), "lsl z5.b, z26.b, #6");
+  COMPARE_PREFIX(lsl(z6.VnH(), z25.VnH(), 10), "lsl z6.h, z25.h, #10");
+  COMPARE_PREFIX(lsl(z7.VnH(), z24.VnH(), 14), "lsl z7.h, z24.h, #14");
+  COMPARE_PREFIX(lsl(z8.VnS(), z23.VnS(), 21), "lsl z8.s, z23.s, #21");
+  COMPARE_PREFIX(lsl(z9.VnS(), z22.VnS(), 30), "lsl z9.s, z22.s, #30");
+  COMPARE_PREFIX(lsl(z10.VnD(), z21.VnD(), 44), "lsl z10.d, z21.d, #44");
+  COMPARE_PREFIX(lsl(z11.VnD(), z20.VnD(), 62), "lsl z11.d, z20.d, #62");
+  COMPARE_PREFIX(asr(z12.VnB(), z8.VnB(), z14.VnD()), "asr z12.b, z8.b, z14.d");
+  COMPARE_PREFIX(asr(z14.VnH(), z8.VnH(), z12.VnD()), "asr z14.h, z8.h, z12.d");
+  COMPARE_PREFIX(asr(z16.VnS(), z8.VnS(), z10.VnD()), "asr z16.s, z8.s, z10.d");
+  COMPARE_PREFIX(lsl(z21.VnB(), z16.VnB(), z15.VnD()),
+                 "lsl z21.b, z16.b, z15.d");
+  COMPARE_PREFIX(lsl(z23.VnH(), z16.VnH(), z13.VnD()),
+                 "lsl z23.h, z16.h, z13.d");
+  COMPARE_PREFIX(lsl(z25.VnS(), z16.VnS(), z11.VnD()),
+                 "lsl z25.s, z16.s, z11.d");
+  COMPARE_PREFIX(lsr(z16.VnB(), z19.VnB(), z2.VnD()), "lsr z16.b, z19.b, z2.d");
+  COMPARE_PREFIX(lsr(z18.VnH(), z19.VnH(), z4.VnD()), "lsr z18.h, z19.h, z4.d");
+  COMPARE_PREFIX(lsr(z20.VnS(), z19.VnS(), z6.VnD()), "lsr z20.s, z19.s, z6.d");
+
+  CLEANUP();
+}
+
+
+TEST(sve_element_count) {
+  SETUP();
+
+  COMPARE_MACRO(Cntb(x7), "cntb x7");
+  COMPARE_MACRO(Cntb(x7, SVE_POW2), "cntb x7, pow2");
+  COMPARE_MACRO(Cntb(x7, SVE_VL1), "cntb x7, vl1");
+  COMPARE_MACRO(Cntb(x7, SVE_VL2), "cntb x7, vl2");
+  COMPARE_MACRO(Cntb(x7, SVE_VL16), "cntb x7, vl16");
+  COMPARE_MACRO(Cntb(x7, SVE_VL256), "cntb x7, vl256");
+  COMPARE_MACRO(Cntb(x7, SVE_MUL4), "cntb x7, mul4");
+  COMPARE_MACRO(Cntb(x7, SVE_MUL3), "cntb x7, mul3");
+  COMPARE_MACRO(Cntb(x7, SVE_ALL), "cntb x7");
+
+  COMPARE_MACRO(Cntb(x7, SVE_POW2, 1), "cntb x7, pow2");
+  COMPARE_MACRO(Cntb(x7, SVE_VL1, 16), "cntb x7, vl1, mul #16");
+  COMPARE_MACRO(Cntb(x7, SVE_VL2, 15), "cntb x7, vl2, mul #15");
+  COMPARE_MACRO(Cntb(x7, SVE_VL16, 14), "cntb x7, vl16, mul #14");
+  COMPARE_MACRO(Cntb(x7, SVE_VL256, 8), "cntb x7, vl256, mul #8");
+  COMPARE_MACRO(Cntb(x7, SVE_MUL4, 4), "cntb x7, mul4, mul #4");
+  COMPARE_MACRO(Cntb(x7, SVE_MUL3, 3), "cntb x7, mul3, mul #3");
+  COMPARE_MACRO(Cntb(x7, SVE_ALL, 2), "cntb x7, all, mul #2");
+
+  COMPARE_MACRO(Cntb(x30), "cntb x30");
+  COMPARE_MACRO(Cntd(xzr, SVE_POW2), "cntd xzr, pow2");
+  COMPARE_MACRO(Cntd(xzr, SVE_MUL4, 1), "cntd xzr, mul4");
+  COMPARE_MACRO(Cnth(x29, SVE_MUL3, 4), "cnth x29, mul3, mul #4");
+  COMPARE_MACRO(Cntw(x28, SVE_VL256, 16), "cntw x28, vl256, mul #16");
+
+  CLEANUP();
+}
+
+TEST(sve_incdec_reg_element_count) {
+  SETUP();
+
+  COMPARE_MACRO(Decb(x4), "decb x4");
+  COMPARE_MACRO(Decb(x4, SVE_POW2), "decb x4, pow2");
+  COMPARE_MACRO(Decb(x4, SVE_VL1), "decb x4, vl1");
+  COMPARE_MACRO(Decb(x4, SVE_VL2), "decb x4, vl2");
+  COMPARE_MACRO(Decb(x4, SVE_VL16), "decb x4, vl16");
+  COMPARE_MACRO(Decb(x4, SVE_VL256), "decb x4, vl256");
+  COMPARE_MACRO(Decb(x4, SVE_MUL4), "decb x4, mul4");
+  COMPARE_MACRO(Decb(x4, SVE_MUL3), "decb x4, mul3");
+  COMPARE_MACRO(Decb(x4, SVE_ALL), "decb x4");
+
+  COMPARE_MACRO(Decb(x4, SVE_POW2, 1), "decb x4, pow2");
+  COMPARE_MACRO(Decb(x4, SVE_VL1, 16), "decb x4, vl1, mul #16");
+  COMPARE_MACRO(Decb(x4, SVE_VL2, 15), "decb x4, vl2, mul #15");
+  COMPARE_MACRO(Decb(x4, SVE_VL16, 14), "decb x4, vl16, mul #14");
+  COMPARE_MACRO(Decb(x4, SVE_VL256, 8), "decb x4, vl256, mul #8");
+  COMPARE_MACRO(Decb(x4, SVE_MUL4, 4), "decb x4, mul4, mul #4");
+  COMPARE_MACRO(Decb(x4, SVE_MUL3, 3), "decb x4, mul3, mul #3");
+  COMPARE_MACRO(Decb(x4, SVE_ALL, 2), "decb x4, all, mul #2");
+
+  COMPARE_MACRO(Decb(x30), "decb x30");
+  COMPARE_MACRO(Decd(xzr, SVE_POW2), "decd xzr, pow2");
+  COMPARE_MACRO(Decd(xzr, SVE_MUL4, 1), "decd xzr, mul4");
+  COMPARE_MACRO(Dech(x29, SVE_MUL3, 4), "dech x29, mul3, mul #4");
+  COMPARE_MACRO(Decw(x28, SVE_VL256, 16), "decw x28, vl256, mul #16");
+
+  COMPARE_MACRO(Incb(x17), "incb x17");
+  COMPARE_MACRO(Incb(x17, SVE_POW2), "incb x17, pow2");
+  COMPARE_MACRO(Incb(x17, SVE_VL1), "incb x17, vl1");
+  COMPARE_MACRO(Incb(x17, SVE_VL2), "incb x17, vl2");
+  COMPARE_MACRO(Incb(x17, SVE_VL16), "incb x17, vl16");
+  COMPARE_MACRO(Incb(x17, SVE_VL256), "incb x17, vl256");
+  COMPARE_MACRO(Incb(x17, SVE_MUL4), "incb x17, mul4");
+  COMPARE_MACRO(Incb(x17, SVE_MUL3), "incb x17, mul3");
+  COMPARE_MACRO(Incb(x17, SVE_ALL), "incb x17");
+
+  COMPARE_MACRO(Incb(x17, SVE_POW2, 1), "incb x17, pow2");
+  COMPARE_MACRO(Incb(x17, SVE_VL1, 16), "incb x17, vl1, mul #16");
+  COMPARE_MACRO(Incb(x17, SVE_VL2, 15), "incb x17, vl2, mul #15");
+  COMPARE_MACRO(Incb(x17, SVE_VL16, 14), "incb x17, vl16, mul #14");
+  COMPARE_MACRO(Incb(x17, SVE_VL256, 8), "incb x17, vl256, mul #8");
+  COMPARE_MACRO(Incb(x17, SVE_MUL4, 4), "incb x17, mul4, mul #4");
+  COMPARE_MACRO(Incb(x17, SVE_MUL3, 3), "incb x17, mul3, mul #3");
+  COMPARE_MACRO(Incb(x17, SVE_ALL, 2), "incb x17, all, mul #2");
+
+  COMPARE_MACRO(Incb(x30), "incb x30");
+  COMPARE_MACRO(Incd(xzr, SVE_POW2), "incd xzr, pow2");
+  COMPARE_MACRO(Incd(xzr, SVE_MUL4, 1), "incd xzr, mul4");
+  COMPARE_MACRO(Inch(x29, SVE_MUL3, 4), "inch x29, mul3, mul #4");
+  COMPARE_MACRO(Incw(x28, SVE_VL256, 16), "incw x28, vl256, mul #16");
+
+  CLEANUP();
+}
+
+TEST(sve_signed_sat_incdec_reg_element_count) {
+  SETUP();
+
+  COMPARE_MACRO(Sqdecb(x12, w12), "sqdecb x12, w12");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_POW2), "sqdecb x12, w12, pow2");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_VL1), "sqdecb x12, w12, vl1");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_VL2), "sqdecb x12, w12, vl2");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_VL16), "sqdecb x12, w12, vl16");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_VL256), "sqdecb x12, w12, vl256");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_MUL4), "sqdecb x12, w12, mul4");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_MUL3), "sqdecb x12, w12, mul3");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_ALL), "sqdecb x12, w12");
+
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_POW2, 1), "sqdecb x12, w12, pow2");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_VL1, 16), "sqdecb x12, w12, vl1, mul #16");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_VL2, 15), "sqdecb x12, w12, vl2, mul #15");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_VL16, 14),
+                "sqdecb x12, w12, vl16, mul #14");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_VL256, 8),
+                "sqdecb x12, w12, vl256, mul #8");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_MUL4, 4), "sqdecb x12, w12, mul4, mul #4");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_MUL3, 3), "sqdecb x12, w12, mul3, mul #3");
+  COMPARE_MACRO(Sqdecb(x12, w12, SVE_ALL, 2), "sqdecb x12, w12, all, mul #2");
+
+  COMPARE_MACRO(Sqdecb(xzr, wzr, SVE_POW2), "sqdecb xzr, wzr, pow2");
+  COMPARE_MACRO(Sqdecb(xzr, wzr, SVE_MUL4, 1), "sqdecb xzr, wzr, mul4");
+
+  COMPARE_MACRO(Sqincw(x20, w20, SVE_POW2, 1), "sqincw x20, w20, pow2");
+  COMPARE_MACRO(Sqincd(x20, w20, SVE_VL1, 16), "sqincd x20, w20, vl1, mul #16");
+  COMPARE_MACRO(Sqinch(x20, w20, SVE_VL2, 15), "sqinch x20, w20, vl2, mul #15");
+  COMPARE_MACRO(Sqincw(x20, w20, SVE_VL16, 14),
+                "sqincw x20, w20, vl16, mul #14");
+  COMPARE_MACRO(Sqincd(x20, w20, SVE_VL256, 8),
+                "sqincd x20, w20, vl256, mul #8");
+  COMPARE_MACRO(Sqinch(x20, w20, SVE_MUL4, 4), "sqinch x20, w20, mul4, mul #4");
+  COMPARE_MACRO(Sqincw(x20, w20, SVE_MUL3, 3), "sqincw x20, w20, mul3, mul #3");
+  COMPARE_MACRO(Sqincd(x20, w20, SVE_ALL, 2), "sqincd x20, w20, all, mul #2");
+
+  COMPARE_MACRO(Sqdecb(x5), "sqdecb x5");
+  COMPARE_MACRO(Sqdecb(x5, SVE_POW2), "sqdecb x5, pow2");
+  COMPARE_MACRO(Sqdecb(x5, SVE_VL1), "sqdecb x5, vl1");
+  COMPARE_MACRO(Sqdecb(x5, SVE_VL2), "sqdecb x5, vl2");
+  COMPARE_MACRO(Sqdecb(x5, SVE_VL16), "sqdecb x5, vl16");
+  COMPARE_MACRO(Sqdecb(x5, SVE_VL256), "sqdecb x5, vl256");
+  COMPARE_MACRO(Sqdecb(x5, SVE_MUL4), "sqdecb x5, mul4");
+  COMPARE_MACRO(Sqdecb(x5, SVE_MUL3), "sqdecb x5, mul3");
+  COMPARE_MACRO(Sqdecb(x5, SVE_ALL), "sqdecb x5");
+
+  COMPARE_MACRO(Sqdecb(x5, SVE_POW2, 1), "sqdecb x5, pow2");
+  COMPARE_MACRO(Sqdecb(x5, SVE_VL1, 16), "sqdecb x5, vl1, mul #16");
+  COMPARE_MACRO(Sqdecb(x5, SVE_VL2, 15), "sqdecb x5, vl2, mul #15");
+  COMPARE_MACRO(Sqdecb(x5, SVE_VL16, 14), "sqdecb x5, vl16, mul #14");
+  COMPARE_MACRO(Sqdecb(x5, SVE_VL256, 8), "sqdecb x5, vl256, mul #8");
+  COMPARE_MACRO(Sqdecb(x5, SVE_MUL4, 4), "sqdecb x5, mul4, mul #4");
+  COMPARE_MACRO(Sqdecb(x5, SVE_MUL3, 3), "sqdecb x5, mul3, mul #3");
+  COMPARE_MACRO(Sqdecb(x5, SVE_ALL, 2), "sqdecb x5, all, mul #2");
+
+  COMPARE_MACRO(Sqdecb(xzr, SVE_POW2), "sqdecb xzr, pow2");
+  COMPARE_MACRO(Sqdecb(xzr, SVE_MUL4, 1), "sqdecb xzr, mul4");
+
+  COMPARE_MACRO(Sqincw(x7, SVE_POW2, 1), "sqincw x7, pow2");
+  COMPARE_MACRO(Sqincd(x7, SVE_VL1, 16), "sqincd x7, vl1, mul #16");
+  COMPARE_MACRO(Sqinch(x7, SVE_VL2, 15), "sqinch x7, vl2, mul #15");
+  COMPARE_MACRO(Sqincw(x7, SVE_VL16, 14), "sqincw x7, vl16, mul #14");
+  COMPARE_MACRO(Sqincd(x7, SVE_VL256, 8), "sqincd x7, vl256, mul #8");
+  COMPARE_MACRO(Sqinch(x7, SVE_MUL4, 4), "sqinch x7, mul4, mul #4");
+  COMPARE_MACRO(Sqincw(x7, SVE_MUL3, 3), "sqincw x7, mul3, mul #3");
+  COMPARE_MACRO(Sqincd(x7, SVE_ALL, 2), "sqincd x7, all, mul #2");
+
+  CLEANUP();
+}
+
+TEST(sve_unsigned_sat_incdec_reg_element_count) {
+  SETUP();
+
+  COMPARE_MACRO(Uqdecb(w12), "uqdecb w12");
+  COMPARE_MACRO(Uqdecb(w12, SVE_POW2), "uqdecb w12, pow2");
+  COMPARE_MACRO(Uqdecb(w12, SVE_VL1), "uqdecb w12, vl1");
+  COMPARE_MACRO(Uqdecb(w12, SVE_VL2), "uqdecb w12, vl2");
+  COMPARE_MACRO(Uqdecb(w12, SVE_VL16), "uqdecb w12, vl16");
+  COMPARE_MACRO(Uqdecb(w12, SVE_VL256), "uqdecb w12, vl256");
+  COMPARE_MACRO(Uqdecb(w12, SVE_MUL4), "uqdecb w12, mul4");
+  COMPARE_MACRO(Uqdecb(w12, SVE_MUL3), "uqdecb w12, mul3");
+  COMPARE_MACRO(Uqdecb(w12, SVE_ALL), "uqdecb w12");
+
+  COMPARE_MACRO(Uqdecb(w12, SVE_POW2, 1), "uqdecb w12, pow2");
+  COMPARE_MACRO(Uqdecb(w12, SVE_VL1, 16), "uqdecb w12, vl1, mul #16");
+  COMPARE_MACRO(Uqdecb(w12, SVE_VL2, 15), "uqdecb w12, vl2, mul #15");
+  COMPARE_MACRO(Uqdecb(w12, SVE_VL16, 14), "uqdecb w12, vl16, mul #14");
+  COMPARE_MACRO(Uqdecb(w12, SVE_VL256, 8), "uqdecb w12, vl256, mul #8");
+  COMPARE_MACRO(Uqdecb(w12, SVE_MUL4, 4), "uqdecb w12, mul4, mul #4");
+  COMPARE_MACRO(Uqdecb(w12, SVE_MUL3, 3), "uqdecb w12, mul3, mul #3");
+  COMPARE_MACRO(Uqdecb(w12, SVE_ALL, 2), "uqdecb w12, all, mul #2");
+
+  COMPARE_MACRO(Uqdecb(x30), "uqdecb x30");
+  COMPARE_MACRO(Uqdecb(xzr, SVE_POW2), "uqdecb xzr, pow2");
+  COMPARE_MACRO(Uqdecb(xzr, SVE_MUL4, 1), "uqdecb xzr, mul4");
+
+  COMPARE_MACRO(Uqdecw(w22), "uqdecw w22");
+  COMPARE_MACRO(Uqdecd(w22, SVE_POW2, 1), "uqdecd w22, pow2");
+  COMPARE_MACRO(Uqdech(w22, SVE_VL1, 16), "uqdech w22, vl1, mul #16");
+  COMPARE_MACRO(Uqdecw(x22, SVE_VL2, 15), "uqdecw x22, vl2, mul #15");
+  COMPARE_MACRO(Uqdecd(x22, SVE_VL16, 14), "uqdecd x22, vl16, mul #14");
+  COMPARE_MACRO(Uqdech(x22, SVE_VL256, 8), "uqdech x22, vl256, mul #8");
+  COMPARE_MACRO(Uqdecw(w22, SVE_MUL4, 4), "uqdecw w22, mul4, mul #4");
+  COMPARE_MACRO(Uqdecd(w22, SVE_MUL3, 3), "uqdecd w22, mul3, mul #3");
+  COMPARE_MACRO(Uqdech(w22, SVE_ALL, 2), "uqdech w22, all, mul #2");
+
+  COMPARE_MACRO(Uqincb(w29), "uqincb w29");
+  COMPARE_MACRO(Uqincb(w29, SVE_POW2), "uqincb w29, pow2");
+  COMPARE_MACRO(Uqincb(w29, SVE_VL1), "uqincb w29, vl1");
+  COMPARE_MACRO(Uqincb(w29, SVE_VL2), "uqincb w29, vl2");
+  COMPARE_MACRO(Uqincb(w29, SVE_VL16), "uqincb w29, vl16");
+  COMPARE_MACRO(Uqincb(w29, SVE_VL256), "uqincb w29, vl256");
+  COMPARE_MACRO(Uqincb(w29, SVE_MUL4), "uqincb w29, mul4");
+  COMPARE_MACRO(Uqincb(w29, SVE_MUL3), "uqincb w29, mul3");
+  COMPARE_MACRO(Uqincb(w29, SVE_ALL), "uqincb w29");
+
+  COMPARE_MACRO(Uqincb(w29, SVE_POW2, 1), "uqincb w29, pow2");
+  COMPARE_MACRO(Uqincb(w29, SVE_VL1, 16), "uqincb w29, vl1, mul #16");
+  COMPARE_MACRO(Uqincb(w29, SVE_VL2, 15), "uqincb w29, vl2, mul #15");
+  COMPARE_MACRO(Uqincb(w29, SVE_VL16, 14), "uqincb w29, vl16, mul #14");
+  COMPARE_MACRO(Uqincb(w29, SVE_VL256, 8), "uqincb w29, vl256, mul #8");
+  COMPARE_MACRO(Uqincb(w29, SVE_MUL4, 4), "uqincb w29, mul4, mul #4");
+  COMPARE_MACRO(Uqincb(w29, SVE_MUL3, 3), "uqincb w29, mul3, mul #3");
+  COMPARE_MACRO(Uqincb(w29, SVE_ALL, 2), "uqincb w29, all, mul #2");
+
+  COMPARE_MACRO(Uqincb(x30), "uqincb x30");
+  COMPARE_MACRO(Uqincb(xzr, SVE_POW2), "uqincb xzr, pow2");
+  COMPARE_MACRO(Uqincb(xzr, SVE_MUL4, 1), "uqincb xzr, mul4");
+
+  COMPARE_MACRO(Uqinch(w11), "uqinch w11");
+  COMPARE_MACRO(Uqincw(w11, SVE_POW2), "uqincw w11, pow2");
+  COMPARE_MACRO(Uqincd(w11, SVE_VL1), "uqincd w11, vl1");
+  COMPARE_MACRO(Uqinch(x11, SVE_VL2), "uqinch x11, vl2");
+  COMPARE_MACRO(Uqincw(x11, SVE_VL16), "uqincw x11, vl16");
+  COMPARE_MACRO(Uqincd(x11, SVE_VL256), "uqincd x11, vl256");
+  COMPARE_MACRO(Uqinch(w11, SVE_MUL4), "uqinch w11, mul4");
+  COMPARE_MACRO(Uqincw(w11, SVE_MUL3), "uqincw w11, mul3");
+  COMPARE_MACRO(Uqincd(w11, SVE_ALL), "uqincd w11");
+
+  CLEANUP();
+}
+
+TEST(sve_vector_dec_element_count) {
+  SETUP();
+
+  COMPARE_MACRO(Decd(z14.VnD()), "decd z14.d");
+  COMPARE_MACRO(Decd(z14.VnD(), SVE_POW2), "decd z14.d, pow2");
+  COMPARE_MACRO(Decd(z14.VnD(), SVE_VL1), "decd z14.d, vl1");
+  COMPARE_MACRO(Decd(z14.VnD(), SVE_VL2), "decd z14.d, vl2");
+  COMPARE_MACRO(Decd(z14.VnD(), SVE_VL16), "decd z14.d, vl16");
+  COMPARE_MACRO(Decd(z14.VnD(), SVE_VL256), "decd z14.d, vl256");
+  COMPARE_MACRO(Decd(z14.VnD(), SVE_MUL4), "decd z14.d, mul4");
+  COMPARE_MACRO(Decd(z14.VnD(), SVE_MUL3), "decd z14.d, mul3");
+  COMPARE_MACRO(Decd(z14.VnD(), SVE_ALL), "decd z14.d");
+
+  COMPARE_MACRO(Decd(z19.VnD(), SVE_POW2, 1), "decd z19.d, pow2");
+  COMPARE_MACRO(Decd(z19.VnD(), SVE_VL1, 16), "decd z19.d, vl1, mul #16");
+  COMPARE_MACRO(Decd(z19.VnD(), SVE_VL2, 15), "decd z19.d, vl2, mul #15");
+  COMPARE_MACRO(Decd(z19.VnD(), SVE_VL16, 14), "decd z19.d, vl16, mul #14");
+  COMPARE_MACRO(Decd(z19.VnD(), SVE_VL256, 8), "decd z19.d, vl256, mul #8");
+  COMPARE_MACRO(Decd(z19.VnD(), SVE_MUL4, 4), "decd z19.d, mul4, mul #4");
+  COMPARE_MACRO(Decd(z19.VnD(), SVE_MUL3, 3), "decd z19.d, mul3, mul #3");
+  COMPARE_MACRO(Decd(z19.VnD(), SVE_ALL, 2), "decd z19.d, all, mul #2");
+
+  COMPARE_MACRO(Dech(z27.VnH(), SVE_POW2, 1), "dech z27.h, pow2");
+  COMPARE_MACRO(Decw(z27.VnS(), SVE_VL1, 16), "decw z27.s, vl1, mul #16");
+  COMPARE_MACRO(Dech(z27.VnH(), SVE_VL2, 15), "dech z27.h, vl2, mul #15");
+  COMPARE_MACRO(Decw(z27.VnS(), SVE_VL16, 14), "decw z27.s, vl16, mul #14");
+  COMPARE_MACRO(Dech(z27.VnH(), SVE_VL256, 8), "dech z27.h, vl256, mul #8");
+  COMPARE_MACRO(Decw(z27.VnS(), SVE_MUL4, 4), "decw z27.s, mul4, mul #4");
+  COMPARE_MACRO(Dech(z27.VnH(), SVE_MUL3, 3), "dech z27.h, mul3, mul #3");
+  COMPARE_MACRO(Decw(z27.VnS(), SVE_ALL, 2), "decw z27.s, all, mul #2");
+
+  COMPARE_MACRO(Sqdecd(z13.VnD()), "sqdecd z13.d");
+  COMPARE_MACRO(Sqdecd(z13.VnD(), SVE_POW2), "sqdecd z13.d, pow2");
+  COMPARE_MACRO(Sqdecd(z13.VnD(), SVE_VL1), "sqdecd z13.d, vl1");
+  COMPARE_MACRO(Sqdecd(z13.VnD(), SVE_VL2), "sqdecd z13.d, vl2");
+  COMPARE_MACRO(Sqdecd(z13.VnD(), SVE_VL16), "sqdecd z13.d, vl16");
+  COMPARE_MACRO(Sqdecd(z13.VnD(), SVE_VL256), "sqdecd z13.d, vl256");
+  COMPARE_MACRO(Sqdecd(z13.VnD(), SVE_MUL4), "sqdecd z13.d, mul4");
+  COMPARE_MACRO(Sqdecd(z13.VnD(), SVE_MUL3), "sqdecd z13.d, mul3");
+  COMPARE_MACRO(Sqdecd(z13.VnD(), SVE_ALL), "sqdecd z13.d");
+
+  COMPARE_MACRO(Sqdecd(z9.VnD(), SVE_POW2, 1), "sqdecd z9.d, pow2");
+  COMPARE_MACRO(Sqdecd(z9.VnD(), SVE_VL1, 16), "sqdecd z9.d, vl1, mul #16");
+  COMPARE_MACRO(Sqdecd(z9.VnD(), SVE_VL2, 15), "sqdecd z9.d, vl2, mul #15");
+  COMPARE_MACRO(Sqdecd(z9.VnD(), SVE_VL16, 14), "sqdecd z9.d, vl16, mul #14");
+  COMPARE_MACRO(Sqdecd(z9.VnD(), SVE_VL256, 8), "sqdecd z9.d, vl256, mul #8");
+  COMPARE_MACRO(Sqdecd(z9.VnD(), SVE_MUL4, 4), "sqdecd z9.d, mul4, mul #4");
+  COMPARE_MACRO(Sqdecd(z9.VnD(), SVE_MUL3, 3), "sqdecd z9.d, mul3, mul #3");
+  COMPARE_MACRO(Sqdecd(z9.VnD(), SVE_ALL, 2), "sqdecd z9.d, all, mul #2");
+
+  COMPARE_MACRO(Sqdech(z31.VnH(), SVE_POW2, 1), "sqdech z31.h, pow2");
+  COMPARE_MACRO(Sqdecw(z31.VnS(), SVE_VL1, 16), "sqdecw z31.s, vl1, mul #16");
+  COMPARE_MACRO(Sqdech(z31.VnH(), SVE_VL2, 15), "sqdech z31.h, vl2, mul #15");
+  COMPARE_MACRO(Sqdecw(z31.VnS(), SVE_VL16, 14), "sqdecw z31.s, vl16, mul #14");
+  COMPARE_MACRO(Sqdech(z31.VnH(), SVE_VL256, 8), "sqdech z31.h, vl256, mul #8");
+  COMPARE_MACRO(Sqdecw(z31.VnS(), SVE_MUL4, 4), "sqdecw z31.s, mul4, mul #4");
+  COMPARE_MACRO(Sqdech(z31.VnH(), SVE_MUL3, 3), "sqdech z31.h, mul3, mul #3");
+  COMPARE_MACRO(Sqdecw(z31.VnS(), SVE_ALL, 2), "sqdecw z31.s, all, mul #2");
+
+  COMPARE_MACRO(Uqdecd(z1.VnD()), "uqdecd z1.d");
+  COMPARE_MACRO(Uqdecd(z1.VnD(), SVE_POW2), "uqdecd z1.d, pow2");
+  COMPARE_MACRO(Uqdecd(z1.VnD(), SVE_VL1), "uqdecd z1.d, vl1");
+  COMPARE_MACRO(Uqdecd(z1.VnD(), SVE_VL2), "uqdecd z1.d, vl2");
+  COMPARE_MACRO(Uqdecd(z1.VnD(), SVE_VL16), "uqdecd z1.d, vl16");
+  COMPARE_MACRO(Uqdecd(z1.VnD(), SVE_VL256), "uqdecd z1.d, vl256");
+  COMPARE_MACRO(Uqdecd(z1.VnD(), SVE_MUL4), "uqdecd z1.d, mul4");
+  COMPARE_MACRO(Uqdecd(z1.VnD(), SVE_MUL3), "uqdecd z1.d, mul3");
+  COMPARE_MACRO(Uqdecd(z1.VnD(), SVE_ALL), "uqdecd z1.d");
+
+  COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_POW2, 1), "uqdecd z7.d, pow2");
+  COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_VL1, 16), "uqdecd z7.d, vl1, mul #16");
+  COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_VL2, 15), "uqdecd z7.d, vl2, mul #15");
+  COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_VL16, 14), "uqdecd z7.d, vl16, mul #14");
+  COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_VL256, 8), "uqdecd z7.d, vl256, mul #8");
+  COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_MUL4, 4), "uqdecd z7.d, mul4, mul #4");
+  COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_MUL3, 3), "uqdecd z7.d, mul3, mul #3");
+  COMPARE_MACRO(Uqdecd(z7.VnD(), SVE_ALL, 2), "uqdecd z7.d, all, mul #2");
+
+  COMPARE_MACRO(Uqdech(z26.VnH(), SVE_POW2, 1), "uqdech z26.h, pow2");
+  COMPARE_MACRO(Uqdecw(z26.VnS(), SVE_VL1, 16), "uqdecw z26.s, vl1, mul #16");
+  COMPARE_MACRO(Uqdech(z26.VnH(), SVE_VL2, 15), "uqdech z26.h, vl2, mul #15");
+  COMPARE_MACRO(Uqdecw(z26.VnS(), SVE_VL16, 14), "uqdecw z26.s, vl16, mul #14");
+  COMPARE_MACRO(Uqdech(z26.VnH(), SVE_VL256, 8), "uqdech z26.h, vl256, mul #8");
+  COMPARE_MACRO(Uqdecw(z26.VnS(), SVE_MUL4, 4), "uqdecw z26.s, mul4, mul #4");
+  COMPARE_MACRO(Uqdech(z26.VnH(), SVE_MUL3, 3), "uqdech z26.h, mul3, mul #3");
+  COMPARE_MACRO(Uqdecw(z26.VnS(), SVE_ALL, 2), "uqdecw z26.s, all, mul #2");
+
+  CLEANUP();
+}
+
+TEST(sve_vector_inc_element_count) {
+  SETUP();
+
+  COMPARE_MACRO(Incd(z16.VnD()), "incd z16.d");
+  COMPARE_MACRO(Incd(z16.VnD(), SVE_POW2), "incd z16.d, pow2");
+  COMPARE_MACRO(Incd(z16.VnD(), SVE_VL1), "incd z16.d, vl1");
+  COMPARE_MACRO(Incd(z16.VnD(), SVE_VL2), "incd z16.d, vl2");
+  COMPARE_MACRO(Incd(z16.VnD(), SVE_VL16), "incd z16.d, vl16");
+  COMPARE_MACRO(Incd(z16.VnD(), SVE_VL256), "incd z16.d, vl256");
+  COMPARE_MACRO(Incd(z16.VnD(), SVE_MUL4), "incd z16.d, mul4");
+  COMPARE_MACRO(Incd(z16.VnD(), SVE_MUL3), "incd z16.d, mul3");
+  COMPARE_MACRO(Incd(z16.VnD(), SVE_ALL), "incd z16.d");
+
+  COMPARE_MACRO(Incd(z18.VnD(), SVE_POW2, 1), "incd z18.d, pow2");
+  COMPARE_MACRO(Incd(z18.VnD(), SVE_VL1, 16), "incd z18.d, vl1, mul #16");
+  COMPARE_MACRO(Incd(z18.VnD(), SVE_VL2, 15), "incd z18.d, vl2, mul #15");
+  COMPARE_MACRO(Incd(z18.VnD(), SVE_VL16, 14), "incd z18.d, vl16, mul #14");
+  COMPARE_MACRO(Incd(z18.VnD(), SVE_VL256, 8), "incd z18.d, vl256, mul #8");
+  COMPARE_MACRO(Incd(z18.VnD(), SVE_MUL4, 4), "incd z18.d, mul4, mul #4");
+  COMPARE_MACRO(Incd(z18.VnD(), SVE_MUL3, 3), "incd z18.d, mul3, mul #3");
+  COMPARE_MACRO(Incd(z18.VnD(), SVE_ALL, 2), "incd z18.d, all, mul #2");
+
+  COMPARE_MACRO(Inch(z24.VnH(), SVE_POW2, 1), "inch z24.h, pow2");
+  COMPARE_MACRO(Incw(z24.VnS(), SVE_VL1, 16), "incw z24.s, vl1, mul #16");
+  COMPARE_MACRO(Inch(z24.VnH(), SVE_VL2, 15), "inch z24.h, vl2, mul #15");
+  COMPARE_MACRO(Incw(z24.VnS(), SVE_VL16, 14), "incw z24.s, vl16, mul #14");
+  COMPARE_MACRO(Inch(z24.VnH(), SVE_VL256, 8), "inch z24.h, vl256, mul #8");
+  COMPARE_MACRO(Incw(z24.VnS(), SVE_MUL4, 4), "incw z24.s, mul4, mul #4");
+  COMPARE_MACRO(Inch(z24.VnH(), SVE_MUL3, 3), "inch z24.h, mul3, mul #3");
+  COMPARE_MACRO(Incw(z24.VnS(), SVE_ALL, 2), "incw z24.s, all, mul #2");
+
+  COMPARE_MACRO(Sqincd(z10.VnD()), "sqincd z10.d");
+  COMPARE_MACRO(Sqincd(z10.VnD(), SVE_POW2), "sqincd z10.d, pow2");
+  COMPARE_MACRO(Sqincd(z10.VnD(), SVE_VL1), "sqincd z10.d, vl1");
+  COMPARE_MACRO(Sqincd(z10.VnD(), SVE_VL2), "sqincd z10.d, vl2");
+  COMPARE_MACRO(Sqincd(z10.VnD(), SVE_VL16), "sqincd z10.d, vl16");
+  COMPARE_MACRO(Sqincd(z10.VnD(), SVE_VL256), "sqincd z10.d, vl256");
+  COMPARE_MACRO(Sqincd(z10.VnD(), SVE_MUL4), "sqincd z10.d, mul4");
+  COMPARE_MACRO(Sqincd(z10.VnD(), SVE_MUL3), "sqincd z10.d, mul3");
+  COMPARE_MACRO(Sqincd(z10.VnD(), SVE_ALL), "sqincd z10.d");
+
+  COMPARE_MACRO(Sqincd(z3.VnD(), SVE_POW2, 1), "sqincd z3.d, pow2");
+  COMPARE_MACRO(Sqincd(z3.VnD(), SVE_VL1, 16), "sqincd z3.d, vl1, mul #16");
+  COMPARE_MACRO(Sqincd(z3.VnD(), SVE_VL2, 15), "sqincd z3.d, vl2, mul #15");
+  COMPARE_MACRO(Sqincd(z3.VnD(), SVE_VL16, 14), "sqincd z3.d, vl16, mul #14");
+  COMPARE_MACRO(Sqincd(z3.VnD(), SVE_VL256, 8), "sqincd z3.d, vl256, mul #8");
+  COMPARE_MACRO(Sqincd(z3.VnD(), SVE_MUL4, 4), "sqincd z3.d, mul4, mul #4");
+  COMPARE_MACRO(Sqincd(z3.VnD(), SVE_MUL3, 3), "sqincd z3.d, mul3, mul #3");
+  COMPARE_MACRO(Sqincd(z3.VnD(), SVE_ALL, 2), "sqincd z3.d, all, mul #2");
+
+  COMPARE_MACRO(Sqinch(z24.VnH(), SVE_POW2, 1), "sqinch z24.h, pow2");
+  COMPARE_MACRO(Sqincw(z24.VnS(), SVE_VL1, 16), "sqincw z24.s, vl1, mul #16");
+  COMPARE_MACRO(Sqinch(z24.VnH(), SVE_VL2, 15), "sqinch z24.h, vl2, mul #15");
+  COMPARE_MACRO(Sqincw(z24.VnS(), SVE_VL16, 14), "sqincw z24.s, vl16, mul #14");
+  COMPARE_MACRO(Sqinch(z24.VnH(), SVE_VL256, 8), "sqinch z24.h, vl256, mul #8");
+  COMPARE_MACRO(Sqincw(z24.VnS(), SVE_MUL4, 4), "sqincw z24.s, mul4, mul #4");
+  COMPARE_MACRO(Sqinch(z24.VnH(), SVE_MUL3, 3), "sqinch z24.h, mul3, mul #3");
+  COMPARE_MACRO(Sqincw(z24.VnS(), SVE_ALL, 2), "sqincw z24.s, all, mul #2");
+
+  COMPARE_MACRO(Uqincd(z10.VnD()), "uqincd z10.d");
+  COMPARE_MACRO(Uqincd(z10.VnD(), SVE_POW2), "uqincd z10.d, pow2");
+  COMPARE_MACRO(Uqincd(z10.VnD(), SVE_VL1), "uqincd z10.d, vl1");
+  COMPARE_MACRO(Uqincd(z10.VnD(), SVE_VL2), "uqincd z10.d, vl2");
+  COMPARE_MACRO(Uqincd(z10.VnD(), SVE_VL16), "uqincd z10.d, vl16");
+  COMPARE_MACRO(Uqincd(z10.VnD(), SVE_VL256), "uqincd z10.d, vl256");
+  COMPARE_MACRO(Uqincd(z10.VnD(), SVE_MUL4), "uqincd z10.d, mul4");
+  COMPARE_MACRO(Uqincd(z10.VnD(), SVE_MUL3), "uqincd z10.d, mul3");
+  COMPARE_MACRO(Uqincd(z10.VnD(), SVE_ALL), "uqincd z10.d");
+
+  COMPARE_MACRO(Uqincd(z6.VnD(), SVE_POW2, 1), "uqincd z6.d, pow2");
+  COMPARE_MACRO(Uqincd(z6.VnD(), SVE_VL1, 16), "uqincd z6.d, vl1, mul #16");
+  COMPARE_MACRO(Uqincd(z6.VnD(), SVE_VL2, 15), "uqincd z6.d, vl2, mul #15");
+  COMPARE_MACRO(Uqincd(z6.VnD(), SVE_VL16, 14), "uqincd z6.d, vl16, mul #14");
+  COMPARE_MACRO(Uqincd(z6.VnD(), SVE_VL256, 8), "uqincd z6.d, vl256, mul #8");
+  COMPARE_MACRO(Uqincd(z6.VnD(), SVE_MUL4, 4), "uqincd z6.d, mul4, mul #4");
+  COMPARE_MACRO(Uqincd(z6.VnD(), SVE_MUL3, 3), "uqincd z6.d, mul3, mul #3");
+  COMPARE_MACRO(Uqincd(z6.VnD(), SVE_ALL, 2), "uqincd z6.d, all, mul #2");
+
+  COMPARE_MACRO(Uqinch(z20.VnH(), SVE_POW2, 1), "uqinch z20.h, pow2");
+  COMPARE_MACRO(Uqincw(z20.VnS(), SVE_VL1, 16), "uqincw z20.s, vl1, mul #16");
+  COMPARE_MACRO(Uqinch(z20.VnH(), SVE_VL2, 15), "uqinch z20.h, vl2, mul #15");
+  COMPARE_MACRO(Uqincw(z20.VnS(), SVE_VL16, 14), "uqincw z20.s, vl16, mul #14");
+  COMPARE_MACRO(Uqinch(z20.VnH(), SVE_VL256, 8), "uqinch z20.h, vl256, mul #8");
+  COMPARE_MACRO(Uqincw(z20.VnS(), SVE_MUL4, 4), "uqincw z20.s, mul4, mul #4");
+  COMPARE_MACRO(Uqinch(z20.VnH(), SVE_MUL3, 3), "uqinch z20.h, mul3, mul #3");
+  COMPARE_MACRO(Uqincw(z20.VnS(), SVE_ALL, 2), "uqincw z20.s, all, mul #2");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_accumulating_reduction) {
+  SETUP();
+
+  COMPARE_PREFIX(fadda(h10, p2, h10, z0.VnH()), "fadda h10, p2, h10, z0.h");
+  COMPARE_PREFIX(fadda(s10, p2, s10, z0.VnS()), "fadda s10, p2, s10, z0.s");
+  COMPARE_PREFIX(fadda(d10, p2, d10, z0.VnD()), "fadda d10, p2, d10, z0.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_arithmetic_predicated) {
+  SETUP();
+
+  COMPARE_PREFIX(fdiv(z9.VnH(), p4.Merging(), z9.VnH(), z4.VnH()),
+                 "fdiv z9.h, p4/m, z9.h, z4.h");
+  COMPARE_PREFIX(fdiv(z19.VnS(), p5.Merging(), z19.VnS(), z14.VnS()),
+                 "fdiv z19.s, p5/m, z19.s, z14.s");
+  COMPARE_PREFIX(fdiv(z29.VnD(), p6.Merging(), z29.VnD(), z24.VnD()),
+                 "fdiv z29.d, p6/m, z29.d, z24.d");
+  COMPARE_PREFIX(fdivr(z21.VnH(), p3.Merging(), z21.VnH(), z11.VnH()),
+                 "fdivr z21.h, p3/m, z21.h, z11.h");
+  COMPARE_PREFIX(fdivr(z23.VnS(), p5.Merging(), z23.VnS(), z15.VnS()),
+                 "fdivr z23.s, p5/m, z23.s, z15.s");
+  COMPARE_PREFIX(fdivr(z25.VnD(), p7.Merging(), z25.VnD(), z19.VnD()),
+                 "fdivr z25.d, p7/m, z25.d, z19.d");
+  COMPARE_PREFIX(fmax(z4.VnH(), p1.Merging(), z4.VnH(), z29.VnH()),
+                 "fmax z4.h, p1/m, z4.h, z29.h");
+  COMPARE_PREFIX(fmax(z14.VnS(), p3.Merging(), z14.VnS(), z29.VnS()),
+                 "fmax z14.s, p3/m, z14.s, z29.s");
+  COMPARE_PREFIX(fmax(z24.VnD(), p5.Merging(), z24.VnD(), z29.VnD()),
+                 "fmax z24.d, p5/m, z24.d, z29.d");
+  COMPARE_PREFIX(fmin(z1.VnH(), p2.Merging(), z1.VnH(), z30.VnH()),
+                 "fmin z1.h, p2/m, z1.h, z30.h");
+  COMPARE_PREFIX(fmin(z11.VnS(), p4.Merging(), z11.VnS(), z30.VnS()),
+                 "fmin z11.s, p4/m, z11.s, z30.s");
+  COMPARE_PREFIX(fmin(z21.VnD(), p6.Merging(), z21.VnD(), z30.VnD()),
+                 "fmin z21.d, p6/m, z21.d, z30.d");
+
+  COMPARE_PREFIX(ftmad(z21.VnH(), z21.VnH(), z22.VnH(), 0),
+                 "ftmad z21.h, z21.h, z22.h, #0");
+  COMPARE_PREFIX(ftmad(z21.VnH(), z21.VnH(), z22.VnH(), 2),
+                 "ftmad z21.h, z21.h, z22.h, #2");
+  COMPARE_PREFIX(ftmad(z2.VnH(), z2.VnH(), z21.VnH(), 7),
+                 "ftmad z2.h, z2.h, z21.h, #7");
+  COMPARE_PREFIX(ftmad(z21.VnS(), z21.VnS(), z22.VnS(), 0),
+                 "ftmad z21.s, z21.s, z22.s, #0");
+  COMPARE_PREFIX(ftmad(z21.VnS(), z21.VnS(), z22.VnS(), 2),
+                 "ftmad z21.s, z21.s, z22.s, #2");
+  COMPARE_PREFIX(ftmad(z2.VnS(), z2.VnS(), z21.VnS(), 7),
+                 "ftmad z2.s, z2.s, z21.s, #7");
+  COMPARE_PREFIX(ftmad(z21.VnD(), z21.VnD(), z22.VnD(), 0),
+                 "ftmad z21.d, z21.d, z22.d, #0");
+  COMPARE_PREFIX(ftmad(z21.VnD(), z21.VnD(), z22.VnD(), 2),
+                 "ftmad z21.d, z21.d, z22.d, #2");
+  COMPARE_PREFIX(ftmad(z2.VnD(), z2.VnD(), z21.VnD(), 7),
+                 "ftmad z2.d, z2.d, z21.d, #7");
+
+  COMPARE_MACRO(Ftmad(z3.VnH(), z2.VnH(), z1.VnH(), 1),
+                "movprfx z3, z2\n"
+                "ftmad z3.h, z3.h, z1.h, #1");
+  COMPARE_MACRO(Ftmad(z6.VnS(), z4.VnS(), z6.VnS(), 1),
+                "mov z31.d, z6.d\n"
+                "movprfx z6, z4\n"
+                "ftmad z6.s, z6.s, z31.s, #1");
+
+  COMPARE_PREFIX(fabd(z31.VnH(), p7.Merging(), z31.VnH(), z17.VnH()),
+                 "fabd z31.h, p7/m, z31.h, z17.h");
+  COMPARE_PREFIX(fabd(z31.VnS(), p7.Merging(), z31.VnS(), z17.VnS()),
+                 "fabd z31.s, p7/m, z31.s, z17.s");
+  COMPARE_PREFIX(fabd(z31.VnD(), p7.Merging(), z31.VnD(), z17.VnD()),
+                 "fabd z31.d, p7/m, z31.d, z17.d");
+  COMPARE_PREFIX(fadd(z24.VnH(), p2.Merging(), z24.VnH(), z15.VnH()),
+                 "fadd z24.h, p2/m, z24.h, z15.h");
+  COMPARE_PREFIX(fadd(z24.VnS(), p2.Merging(), z24.VnS(), z15.VnS()),
+                 "fadd z24.s, p2/m, z24.s, z15.s");
+  COMPARE_PREFIX(fadd(z24.VnD(), p2.Merging(), z24.VnD(), z15.VnD()),
+                 "fadd z24.d, p2/m, z24.d, z15.d");
+  COMPARE_PREFIX(fmaxnm(z15.VnH(), p4.Merging(), z15.VnH(), z3.VnH()),
+                 "fmaxnm z15.h, p4/m, z15.h, z3.h");
+  COMPARE_PREFIX(fmaxnm(z15.VnS(), p4.Merging(), z15.VnS(), z3.VnS()),
+                 "fmaxnm z15.s, p4/m, z15.s, z3.s");
+  COMPARE_PREFIX(fmaxnm(z15.VnD(), p4.Merging(), z15.VnD(), z3.VnD()),
+                 "fmaxnm z15.d, p4/m, z15.d, z3.d");
+  COMPARE_PREFIX(fminnm(z19.VnH(), p2.Merging(), z19.VnH(), z29.VnH()),
+                 "fminnm z19.h, p2/m, z19.h, z29.h");
+  COMPARE_PREFIX(fminnm(z19.VnS(), p2.Merging(), z19.VnS(), z29.VnS()),
+                 "fminnm z19.s, p2/m, z19.s, z29.s");
+  COMPARE_PREFIX(fminnm(z19.VnD(), p2.Merging(), z19.VnD(), z29.VnD()),
+                 "fminnm z19.d, p2/m, z19.d, z29.d");
+  COMPARE_PREFIX(fmulx(z30.VnH(), p6.Merging(), z30.VnH(), z20.VnH()),
+                 "fmulx z30.h, p6/m, z30.h, z20.h");
+  COMPARE_PREFIX(fmulx(z30.VnS(), p6.Merging(), z30.VnS(), z20.VnS()),
+                 "fmulx z30.s, p6/m, z30.s, z20.s");
+  COMPARE_PREFIX(fmulx(z30.VnD(), p6.Merging(), z30.VnD(), z20.VnD()),
+                 "fmulx z30.d, p6/m, z30.d, z20.d");
+  COMPARE_PREFIX(fmul(z26.VnH(), p2.Merging(), z26.VnH(), z6.VnH()),
+                 "fmul z26.h, p2/m, z26.h, z6.h");
+  COMPARE_PREFIX(fmul(z26.VnS(), p2.Merging(), z26.VnS(), z6.VnS()),
+                 "fmul z26.s, p2/m, z26.s, z6.s");
+  COMPARE_PREFIX(fmul(z26.VnD(), p2.Merging(), z26.VnD(), z6.VnD()),
+                 "fmul z26.d, p2/m, z26.d, z6.d");
+  COMPARE_PREFIX(fscale(z8.VnH(), p3.Merging(), z8.VnH(), z6.VnH()),
+                 "fscale z8.h, p3/m, z8.h, z6.h");
+  COMPARE_PREFIX(fscale(z8.VnS(), p3.Merging(), z8.VnS(), z6.VnS()),
+                 "fscale z8.s, p3/m, z8.s, z6.s");
+  COMPARE_PREFIX(fscale(z8.VnD(), p3.Merging(), z8.VnD(), z6.VnD()),
+                 "fscale z8.d, p3/m, z8.d, z6.d");
+  COMPARE_PREFIX(fsubr(z16.VnH(), p5.Merging(), z16.VnH(), z15.VnH()),
+                 "fsubr z16.h, p5/m, z16.h, z15.h");
+  COMPARE_PREFIX(fsubr(z16.VnS(), p5.Merging(), z16.VnS(), z15.VnS()),
+                 "fsubr z16.s, p5/m, z16.s, z15.s");
+  COMPARE_PREFIX(fsubr(z16.VnD(), p5.Merging(), z16.VnD(), z15.VnD()),
+                 "fsubr z16.d, p5/m, z16.d, z15.d");
+  COMPARE_PREFIX(fsub(z16.VnH(), p5.Merging(), z16.VnH(), z26.VnH()),
+                 "fsub z16.h, p5/m, z16.h, z26.h");
+  COMPARE_PREFIX(fsub(z16.VnS(), p5.Merging(), z16.VnS(), z26.VnS()),
+                 "fsub z16.s, p5/m, z16.s, z26.s");
+  COMPARE_PREFIX(fsub(z16.VnD(), p5.Merging(), z16.VnD(), z26.VnD()),
+                 "fsub z16.d, p5/m, z16.d, z26.d");
+
+  COMPARE_MACRO(Fsub(z0.VnH(), p0.Merging(), z1.VnH(), z0.VnH()),
+                "fsubr z0.h, p0/m, z0.h, z1.h");
+
+  COMPARE_MACRO(Fadd(z0.VnH(),
+                     p0.Merging(),
+                     z1.VnH(),
+                     z2.VnH(),
+                     FastNaNPropagation),
+                "movprfx z0.h, p0/m, z1.h\n"
+                "fadd z0.h, p0/m, z0.h, z2.h");
+  COMPARE_MACRO(Fadd(z0.VnH(),
+                     p0.Merging(),
+                     z1.VnH(),
+                     z0.VnH(),
+                     FastNaNPropagation),
+                "fadd z0.h, p0/m, z0.h, z1.h");
+  COMPARE_MACRO(Fadd(z0.VnH(),
+                     p0.Merging(),
+                     z1.VnH(),
+                     z0.VnH(),
+                     StrictNaNPropagation),
+                "movprfx z31.h, p0/m, z1.h\n"
+                "fadd z31.h, p0/m, z31.h, z0.h\n"
+                "mov z0.d, z31.d");
+  COMPARE_MACRO(Fmul(z1.VnS(),
+                     p1.Merging(),
+                     z2.VnS(),
+                     z3.VnS(),
+                     FastNaNPropagation),
+                "movprfx z1.s, p1/m, z2.s\n"
+                "fmul z1.s, p1/m, z1.s, z3.s");
+  COMPARE_MACRO(Fmulx(z2.VnD(),
+                      p2.Merging(),
+                      z3.VnD(),
+                      z4.VnD(),
+                      FastNaNPropagation),
+                "movprfx z2.d, p2/m, z3.d\n"
+                "fmulx z2.d, p2/m, z2.d, z4.d");
+  COMPARE_MACRO(Fminnm(z3.VnH(),
+                       p3.Merging(),
+                       z4.VnH(),
+                       z5.VnH(),
+                       FastNaNPropagation),
+                "movprfx z3.h, p3/m, z4.h\n"
+                "fminnm z3.h, p3/m, z3.h, z5.h");
+  COMPARE_MACRO(Fmaxnm(z4.VnS(),
+                       p4.Merging(),
+                       z5.VnS(),
+                       z6.VnS(),
+                       FastNaNPropagation),
+                "movprfx z4.s, p4/m, z5.s\n"
+                "fmaxnm z4.s, p4/m, z4.s, z6.s");
+  COMPARE_MACRO(Fsub(z5.VnD(), p5.Merging(), z6.VnD(), z7.VnD()),
+                "movprfx z5.d, p5/m, z6.d\n"
+                "fsub z5.d, p5/m, z5.d, z7.d");
+  COMPARE_MACRO(Fscale(z6.VnH(), p6.Merging(), z7.VnH(), z8.VnH()),
+                "movprfx z6.h, p6/m, z7.h\n"
+                "fscale z6.h, p6/m, z6.h, z8.h");
+  COMPARE_MACRO(Fscale(z7.VnS(), p7.Merging(), z8.VnS(), z7.VnS()),
+                "mov z31.d, z7.d\n"
+                "movprfx z7.s, p7/m, z8.s\n"
+                "fscale z7.s, p7/m, z7.s, z31.s");
+
+  COMPARE_PREFIX(fadd(z18.VnH(), p0.Merging(), z18.VnH(), 0.5),
+                 "fadd z18.h, p0/m, z18.h, #0.5");
+  COMPARE_PREFIX(fadd(z18.VnS(), p0.Merging(), z18.VnS(), 1.0),
+                 "fadd z18.s, p0/m, z18.s, #1.0");
+  COMPARE_PREFIX(fadd(z18.VnD(), p0.Merging(), z18.VnD(), 1.0),
+                 "fadd z18.d, p0/m, z18.d, #1.0");
+  COMPARE_PREFIX(fmaxnm(z6.VnH(), p1.Merging(), z6.VnH(), 0.0),
+                 "fmaxnm z6.h, p1/m, z6.h, #0.0");
+  COMPARE_PREFIX(fmaxnm(z6.VnS(), p1.Merging(), z6.VnS(), 1.0),
+                 "fmaxnm z6.s, p1/m, z6.s, #1.0");
+  COMPARE_PREFIX(fmaxnm(z6.VnD(), p1.Merging(), z6.VnD(), 1.0),
+                 "fmaxnm z6.d, p1/m, z6.d, #1.0");
+  COMPARE_PREFIX(fmax(z8.VnH(), p6.Merging(), z8.VnH(), 0.0),
+                 "fmax z8.h, p6/m, z8.h, #0.0");
+  COMPARE_PREFIX(fmax(z8.VnS(), p6.Merging(), z8.VnS(), 0.0),
+                 "fmax z8.s, p6/m, z8.s, #0.0");
+  COMPARE_PREFIX(fmax(z8.VnD(), p6.Merging(), z8.VnD(), 1.0),
+                 "fmax z8.d, p6/m, z8.d, #1.0");
+  COMPARE_PREFIX(fminnm(z26.VnH(), p0.Merging(), z26.VnH(), 1.0),
+                 "fminnm z26.h, p0/m, z26.h, #1.0");
+  COMPARE_PREFIX(fminnm(z26.VnS(), p0.Merging(), z26.VnS(), 0.0),
+                 "fminnm z26.s, p0/m, z26.s, #0.0");
+  COMPARE_PREFIX(fminnm(z26.VnD(), p0.Merging(), z26.VnD(), 1.0),
+                 "fminnm z26.d, p0/m, z26.d, #1.0");
+  COMPARE_PREFIX(fmin(z22.VnH(), p0.Merging(), z22.VnH(), 1.0),
+                 "fmin z22.h, p0/m, z22.h, #1.0");
+  COMPARE_PREFIX(fmin(z22.VnS(), p0.Merging(), z22.VnS(), 1.0),
+                 "fmin z22.s, p0/m, z22.s, #1.0");
+  COMPARE_PREFIX(fmin(z22.VnD(), p0.Merging(), z22.VnD(), 0.0),
+                 "fmin z22.d, p0/m, z22.d, #0.0");
+  COMPARE_PREFIX(fmul(z21.VnH(), p3.Merging(), z21.VnH(), 0.5),
+                 "fmul z21.h, p3/m, z21.h, #0.5");
+  COMPARE_PREFIX(fmul(z21.VnS(), p3.Merging(), z21.VnS(), 2.0),
+                 "fmul z21.s, p3/m, z21.s, #2.0");
+  COMPARE_PREFIX(fmul(z21.VnD(), p3.Merging(), z21.VnD(), 2.0),
+                 "fmul z21.d, p3/m, z21.d, #2.0");
+  COMPARE_PREFIX(fsubr(z21.VnH(), p3.Merging(), z21.VnH(), 1.0),
+                 "fsubr z21.h, p3/m, z21.h, #1.0");
+  COMPARE_PREFIX(fsubr(z21.VnS(), p3.Merging(), z21.VnS(), 0.5),
+                 "fsubr z21.s, p3/m, z21.s, #0.5");
+  COMPARE_PREFIX(fsubr(z21.VnD(), p3.Merging(), z21.VnD(), 1.0),
+                 "fsubr z21.d, p3/m, z21.d, #1.0");
+  COMPARE_PREFIX(fsub(z26.VnH(), p4.Merging(), z26.VnH(), 0.5),
+                 "fsub z26.h, p4/m, z26.h, #0.5");
+  COMPARE_PREFIX(fsub(z26.VnS(), p4.Merging(), z26.VnS(), 1.0),
+                 "fsub z26.s, p4/m, z26.s, #1.0");
+  COMPARE_PREFIX(fsub(z26.VnD(), p4.Merging(), z26.VnD(), 0.5),
+                 "fsub z26.d, p4/m, z26.d, #0.5");
+
+  COMPARE_MACRO(Fadd(z18.VnH(), p0.Merging(), z8.VnH(), 1.0),
+                "movprfx z18.h, p0/m, z8.h\n"
+                "fadd z18.h, p0/m, z18.h, #1.0");
+  COMPARE_MACRO(Fsub(z19.VnH(), p1.Merging(), z9.VnH(), 0.5),
+                "movprfx z19.h, p1/m, z9.h\n"
+                "fsub z19.h, p1/m, z19.h, #0.5");
+  COMPARE_MACRO(Fsub(z20.VnH(), p2.Merging(), 1.0, z10.VnH()),
+                "movprfx z20.h, p2/m, z10.h\n"
+                "fsubr z20.h, p2/m, z20.h, #1.0");
+  COMPARE_MACRO(Fmul(z21.VnH(), p3.Merging(), z11.VnH(), 2.0),
+                "movprfx z21.h, p3/m, z11.h\n"
+                "fmul z21.h, p3/m, z21.h, #2.0");
+  COMPARE_MACRO(Fmin(z22.VnH(), p4.Merging(), z12.VnH(), 0.0),
+                "movprfx z22.h, p4/m, z12.h\n"
+                "fmin z22.h, p4/m, z22.h, #0.0");
+  COMPARE_MACRO(Fminnm(z22.VnH(), p4.Merging(), z12.VnH(), 0.0),
+                "movprfx z22.h, p4/m, z12.h\n"
+                "fminnm z22.h, p4/m, z22.h, #0.0");
+  COMPARE_MACRO(Fmax(z23.VnH(), p5.Merging(), z13.VnH(), 1.0),
+                "movprfx z23.h, p5/m, z13.h\n"
+                "fmax z23.h, p5/m, z23.h, #1.0");
+  COMPARE_MACRO(Fmaxnm(z23.VnH(), p5.Merging(), z13.VnH(), 1.0),
+                "movprfx z23.h, p5/m, z13.h\n"
+                "fmaxnm z23.h, p5/m, z23.h, #1.0");
+  CLEANUP();
+}
+
+TEST(sve_fp_arithmetic_predicated_macro_fast_nan_propagation) {
+  // Shadow the `MacroAssembler` type so that the test macros work without
+  // modification.
+  typedef FastNaNPropagationMacroAssembler MacroAssembler;
+
+  SETUP();
+
+  COMPARE_MACRO(Fdiv(z8.VnH(), p4.Merging(), z8.VnH(), z4.VnH()),
+                "fdiv z8.h, p4/m, z8.h, z4.h");
+  COMPARE_MACRO(Fdiv(z18.VnS(), p5.Merging(), z18.VnS(), z14.VnS()),
+                "fdiv z18.s, p5/m, z18.s, z14.s");
+  COMPARE_MACRO(Fdiv(z28.VnD(), p6.Merging(), z28.VnD(), z24.VnD()),
+                "fdiv z28.d, p6/m, z28.d, z24.d");
+  COMPARE_MACRO(Fdiv(z17.VnH(), p2.Merging(), z17.VnH(), z17.VnH()),
+                "fdiv z17.h, p2/m, z17.h, z17.h");
+  COMPARE_MACRO(Fdiv(z20.VnS(), p5.Merging(), z23.VnS(), z20.VnS()),
+                "fdivr z20.s, p5/m, z20.s, z23.s");
+  COMPARE_MACRO(Fdiv(z15.VnD(), p6.Merging(), z30.VnD(), z8.VnD()),
+                "movprfx z15.d, p6/m, z30.d\n"
+                "fdiv z15.d, p6/m, z15.d, z8.d");
+
+  COMPARE_MACRO(Fmax(z8.VnH(), p4.Merging(), z8.VnH(), z4.VnH()),
+                "fmax z8.h, p4/m, z8.h, z4.h");
+  COMPARE_MACRO(Fmax(z18.VnS(), p5.Merging(), z18.VnS(), z14.VnS()),
+                "fmax z18.s, p5/m, z18.s, z14.s");
+  COMPARE_MACRO(Fmax(z28.VnD(), p6.Merging(), z28.VnD(), z24.VnD()),
+                "fmax z28.d, p6/m, z28.d, z24.d");
+  COMPARE_MACRO(Fmax(z17.VnH(), p2.Merging(), z17.VnH(), z17.VnH()),
+                "fmax z17.h, p2/m, z17.h, z17.h");
+  COMPARE_MACRO(Fmax(z20.VnS(), p5.Merging(), z23.VnS(), z20.VnS()),
+                "fmax z20.s, p5/m, z20.s, z23.s");
+  COMPARE_MACRO(Fmax(z15.VnD(), p6.Merging(), z30.VnD(), z8.VnD()),
+                "movprfx z15.d, p6/m, z30.d\n"
+                "fmax z15.d, p6/m, z15.d, z8.d");
+
+  COMPARE_MACRO(Fmin(z8.VnH(), p4.Merging(), z8.VnH(), z4.VnH()),
+                "fmin z8.h, p4/m, z8.h, z4.h");
+  COMPARE_MACRO(Fmin(z18.VnS(), p5.Merging(), z18.VnS(), z14.VnS()),
+                "fmin z18.s, p5/m, z18.s, z14.s");
+  COMPARE_MACRO(Fmin(z28.VnD(), p6.Merging(), z28.VnD(), z24.VnD()),
+                "fmin z28.d, p6/m, z28.d, z24.d");
+  COMPARE_MACRO(Fmin(z17.VnH(), p2.Merging(), z17.VnH(), z17.VnH()),
+                "fmin z17.h, p2/m, z17.h, z17.h");
+  COMPARE_MACRO(Fmin(z20.VnS(), p5.Merging(), z23.VnS(), z20.VnS()),
+                "fmin z20.s, p5/m, z20.s, z23.s");
+  COMPARE_MACRO(Fmin(z15.VnD(), p6.Merging(), z30.VnD(), z8.VnD()),
+                "movprfx z15.d, p6/m, z30.d\n"
+                "fmin z15.d, p6/m, z15.d, z8.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_arithmetic_predicated_macro_strict_nan_propagation) {
+  // Shadow the `MacroAssembler` type so that the test macros work without
+  // modification.
+  typedef StrictNaNPropagationMacroAssembler MacroAssembler;
+
+  SETUP();
+
+  COMPARE_MACRO(Fdiv(z8.VnH(), p4.Merging(), z8.VnH(), z4.VnH()),
+                "fdiv z8.h, p4/m, z8.h, z4.h");
+  COMPARE_MACRO(Fdiv(z18.VnS(), p5.Merging(), z18.VnS(), z14.VnS()),
+                "fdiv z18.s, p5/m, z18.s, z14.s");
+  COMPARE_MACRO(Fdiv(z28.VnD(), p6.Merging(), z28.VnD(), z24.VnD()),
+                "fdiv z28.d, p6/m, z28.d, z24.d");
+  COMPARE_MACRO(Fdiv(z17.VnH(), p2.Merging(), z17.VnH(), z17.VnH()),
+                "fdiv z17.h, p2/m, z17.h, z17.h");
+  COMPARE_MACRO(Fdiv(z20.VnS(), p5.Merging(), z23.VnS(), z20.VnS()),
+                "fdivr z20.s, p5/m, z20.s, z23.s");
+  COMPARE_MACRO(Fdiv(z15.VnD(), p6.Merging(), z30.VnD(), z8.VnD()),
+                "movprfx z15.d, p6/m, z30.d\n"
+                "fdiv z15.d, p6/m, z15.d, z8.d");
+
+  COMPARE_MACRO(Fmax(z8.VnH(), p4.Merging(), z8.VnH(), z4.VnH()),
+                "fmax z8.h, p4/m, z8.h, z4.h");
+  COMPARE_MACRO(Fmax(z18.VnS(), p5.Merging(), z18.VnS(), z14.VnS()),
+                "fmax z18.s, p5/m, z18.s, z14.s");
+  COMPARE_MACRO(Fmax(z28.VnD(), p6.Merging(), z28.VnD(), z24.VnD()),
+                "fmax z28.d, p6/m, z28.d, z24.d");
+  COMPARE_MACRO(Fmax(z17.VnH(), p2.Merging(), z17.VnH(), z17.VnH()),
+                "fmax z17.h, p2/m, z17.h, z17.h");
+  COMPARE_MACRO(Fmax(z20.VnS(), p5.Merging(), z23.VnS(), z20.VnS()),
+                "movprfx z31.s, p5/m, z23.s\n"
+                "fmax z31.s, p5/m, z31.s, z20.s\n"
+                "mov z20.d, z31.d");
+  COMPARE_MACRO(Fmax(z15.VnD(), p6.Merging(), z30.VnD(), z8.VnD()),
+                "movprfx z15.d, p6/m, z30.d\n"
+                "fmax z15.d, p6/m, z15.d, z8.d");
+
+  COMPARE_MACRO(Fmin(z8.VnH(), p4.Merging(), z8.VnH(), z4.VnH()),
+                "fmin z8.h, p4/m, z8.h, z4.h");
+  COMPARE_MACRO(Fmin(z18.VnS(), p5.Merging(), z18.VnS(), z14.VnS()),
+                "fmin z18.s, p5/m, z18.s, z14.s");
+  COMPARE_MACRO(Fmin(z28.VnD(), p6.Merging(), z28.VnD(), z24.VnD()),
+                "fmin z28.d, p6/m, z28.d, z24.d");
+  COMPARE_MACRO(Fmin(z17.VnH(), p2.Merging(), z17.VnH(), z17.VnH()),
+                "fmin z17.h, p2/m, z17.h, z17.h");
+  COMPARE_MACRO(Fmin(z20.VnS(), p5.Merging(), z23.VnS(), z20.VnS()),
+                "movprfx z31.s, p5/m, z23.s\n"
+                "fmin z31.s, p5/m, z31.s, z20.s\n"
+                "mov z20.d, z31.d");
+  COMPARE_MACRO(Fmin(z15.VnD(), p6.Merging(), z30.VnD(), z8.VnD()),
+                "movprfx z15.d, p6/m, z30.d\n"
+                "fmin z15.d, p6/m, z15.d, z8.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_arithmetic_unpredicated) {
+  SETUP();
+
+  COMPARE_PREFIX(fadd(z5.VnH(), z24.VnH(), z11.VnH()),
+                 "fadd z5.h, z24.h, z11.h");
+  COMPARE_PREFIX(fadd(z15.VnS(), z14.VnS(), z12.VnS()),
+                 "fadd z15.s, z14.s, z12.s");
+  COMPARE_PREFIX(fadd(z25.VnD(), z4.VnD(), z13.VnD()),
+                 "fadd z25.d, z4.d, z13.d");
+  COMPARE_PREFIX(fmul(z9.VnH(), z24.VnH(), z10.VnH()),
+                 "fmul z9.h, z24.h, z10.h");
+  COMPARE_PREFIX(fmul(z19.VnS(), z14.VnS(), z0.VnS()),
+                 "fmul z19.s, z14.s, z0.s");
+  COMPARE_PREFIX(fmul(z29.VnD(), z4.VnD(), z20.VnD()),
+                 "fmul z29.d, z4.d, z20.d");
+  COMPARE_PREFIX(fsub(z4.VnH(), z14.VnH(), z29.VnH()),
+                 "fsub z4.h, z14.h, z29.h");
+  COMPARE_PREFIX(fsub(z14.VnS(), z24.VnS(), z9.VnS()),
+                 "fsub z14.s, z24.s, z9.s");
+  COMPARE_PREFIX(fsub(z14.VnD(), z4.VnD(), z19.VnD()),
+                 "fsub z14.d, z4.d, z19.d");
+  COMPARE_PREFIX(frecps(z14.VnH(), z29.VnH(), z18.VnH()),
+                 "frecps z14.h, z29.h, z18.h");
+  COMPARE_PREFIX(frecps(z14.VnS(), z29.VnS(), z18.VnS()),
+                 "frecps z14.s, z29.s, z18.s");
+  COMPARE_PREFIX(frecps(z14.VnD(), z29.VnD(), z18.VnD()),
+                 "frecps z14.d, z29.d, z18.d");
+  COMPARE_PREFIX(frsqrts(z5.VnH(), z6.VnH(), z28.VnH()),
+                 "frsqrts z5.h, z6.h, z28.h");
+  COMPARE_PREFIX(frsqrts(z5.VnS(), z6.VnS(), z28.VnS()),
+                 "frsqrts z5.s, z6.s, z28.s");
+  COMPARE_PREFIX(frsqrts(z5.VnD(), z6.VnD(), z28.VnD()),
+                 "frsqrts z5.d, z6.d, z28.d");
+  COMPARE_PREFIX(ftsmul(z21.VnH(), z17.VnH(), z24.VnH()),
+                 "ftsmul z21.h, z17.h, z24.h");
+  COMPARE_PREFIX(ftsmul(z21.VnS(), z17.VnS(), z24.VnS()),
+                 "ftsmul z21.s, z17.s, z24.s");
+  COMPARE_PREFIX(ftsmul(z21.VnD(), z17.VnD(), z24.VnD()),
+                 "ftsmul z21.d, z17.d, z24.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_compare_vectors) {
+  SETUP();
+
+
+  COMPARE_PREFIX(facge(p1.VnH(), p3.Zeroing(), z22.VnH(), z25.VnH()),
+                 "facge p1.h, p3/z, z22.h, z25.h");
+  COMPARE_PREFIX(facge(p1.VnS(), p3.Zeroing(), z22.VnS(), z25.VnS()),
+                 "facge p1.s, p3/z, z22.s, z25.s");
+  COMPARE_PREFIX(facge(p1.VnD(), p3.Zeroing(), z22.VnD(), z25.VnD()),
+                 "facge p1.d, p3/z, z22.d, z25.d");
+  COMPARE_PREFIX(facgt(p8.VnH(), p7.Zeroing(), z25.VnH(), z17.VnH()),
+                 "facgt p8.h, p7/z, z25.h, z17.h");
+  COMPARE_PREFIX(facgt(p8.VnS(), p7.Zeroing(), z25.VnS(), z17.VnS()),
+                 "facgt p8.s, p7/z, z25.s, z17.s");
+  COMPARE_PREFIX(facgt(p8.VnD(), p7.Zeroing(), z25.VnD(), z17.VnD()),
+                 "facgt p8.d, p7/z, z25.d, z17.d");
+  COMPARE_PREFIX(fcmeq(p10.VnH(), p2.Zeroing(), z1.VnH(), z17.VnH()),
+                 "fcmeq p10.h, p2/z, z1.h, z17.h");
+  COMPARE_PREFIX(fcmeq(p10.VnS(), p2.Zeroing(), z1.VnS(), z17.VnS()),
+                 "fcmeq p10.s, p2/z, z1.s, z17.s");
+  COMPARE_PREFIX(fcmeq(p10.VnD(), p2.Zeroing(), z1.VnD(), z17.VnD()),
+                 "fcmeq p10.d, p2/z, z1.d, z17.d");
+  COMPARE_PREFIX(fcmge(p0.VnH(), p0.Zeroing(), z1.VnH(), z0.VnH()),
+                 "fcmge p0.h, p0/z, z1.h, z0.h");
+  COMPARE_PREFIX(fcmge(p0.VnS(), p0.Zeroing(), z1.VnS(), z0.VnS()),
+                 "fcmge p0.s, p0/z, z1.s, z0.s");
+  COMPARE_PREFIX(fcmge(p0.VnD(), p0.Zeroing(), z1.VnD(), z0.VnD()),
+                 "fcmge p0.d, p0/z, z1.d, z0.d");
+  COMPARE_PREFIX(fcmgt(p15.VnH(), p5.Zeroing(), z26.VnH(), z5.VnH()),
+                 "fcmgt p15.h, p5/z, z26.h, z5.h");
+  COMPARE_PREFIX(fcmgt(p15.VnS(), p5.Zeroing(), z26.VnS(), z5.VnS()),
+                 "fcmgt p15.s, p5/z, z26.s, z5.s");
+  COMPARE_PREFIX(fcmgt(p15.VnD(), p5.Zeroing(), z26.VnD(), z5.VnD()),
+                 "fcmgt p15.d, p5/z, z26.d, z5.d");
+  COMPARE_PREFIX(fcmne(p2.VnH(), p1.Zeroing(), z9.VnH(), z4.VnH()),
+                 "fcmne p2.h, p1/z, z9.h, z4.h");
+  COMPARE_PREFIX(fcmne(p2.VnS(), p1.Zeroing(), z9.VnS(), z4.VnS()),
+                 "fcmne p2.s, p1/z, z9.s, z4.s");
+  COMPARE_PREFIX(fcmne(p2.VnD(), p1.Zeroing(), z9.VnD(), z4.VnD()),
+                 "fcmne p2.d, p1/z, z9.d, z4.d");
+  COMPARE_PREFIX(fcmuo(p6.VnH(), p4.Zeroing(), z10.VnH(), z21.VnH()),
+                 "fcmuo p6.h, p4/z, z10.h, z21.h");
+  COMPARE_PREFIX(fcmuo(p6.VnS(), p4.Zeroing(), z10.VnS(), z21.VnS()),
+                 "fcmuo p6.s, p4/z, z10.s, z21.s");
+  COMPARE_PREFIX(fcmuo(p6.VnD(), p4.Zeroing(), z10.VnD(), z21.VnD()),
+                 "fcmuo p6.d, p4/z, z10.d, z21.d");
+
+  COMPARE_MACRO(Facle(p2.VnH(), p0.Zeroing(), z11.VnH(), z15.VnH()),
+                "facge p2.h, p0/z, z15.h, z11.h");
+  COMPARE_MACRO(Facle(p2.VnS(), p0.Zeroing(), z11.VnS(), z15.VnS()),
+                "facge p2.s, p0/z, z15.s, z11.s");
+  COMPARE_MACRO(Facle(p2.VnD(), p0.Zeroing(), z11.VnD(), z15.VnD()),
+                "facge p2.d, p0/z, z15.d, z11.d");
+  COMPARE_MACRO(Faclt(p9.VnH(), p4.Zeroing(), z27.VnH(), z5.VnH()),
+                "facgt p9.h, p4/z, z5.h, z27.h");
+  COMPARE_MACRO(Faclt(p9.VnS(), p4.Zeroing(), z27.VnS(), z5.VnS()),
+                "facgt p9.s, p4/z, z5.s, z27.s");
+  COMPARE_MACRO(Faclt(p9.VnD(), p4.Zeroing(), z27.VnD(), z5.VnD()),
+                "facgt p9.d, p4/z, z5.d, z27.d");
+
+  COMPARE_MACRO(Fcmle(p12.VnH(), p2.Zeroing(), z21.VnH(), z29.VnH()),
+                "fcmge p12.h, p2/z, z29.h, z21.h");
+  COMPARE_MACRO(Fcmle(p12.VnS(), p2.Zeroing(), z21.VnS(), z29.VnS()),
+                "fcmge p12.s, p2/z, z29.s, z21.s");
+  COMPARE_MACRO(Fcmle(p12.VnD(), p2.Zeroing(), z21.VnD(), z29.VnD()),
+                "fcmge p12.d, p2/z, z29.d, z21.d");
+  COMPARE_MACRO(Fcmlt(p7.VnH(), p3.Zeroing(), z7.VnH(), z14.VnH()),
+                "fcmgt p7.h, p3/z, z14.h, z7.h");
+  COMPARE_MACRO(Fcmlt(p7.VnS(), p3.Zeroing(), z7.VnS(), z14.VnS()),
+                "fcmgt p7.s, p3/z, z14.s, z7.s");
+  COMPARE_MACRO(Fcmlt(p7.VnD(), p3.Zeroing(), z7.VnD(), z14.VnD()),
+                "fcmgt p7.d, p3/z, z14.d, z7.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_compare_with_zero) {
+  SETUP();
+
+  COMPARE_PREFIX(fcmeq(p9.VnH(), p1.Zeroing(), z17.VnH(), 0),
+                 "fcmeq p9.h, p1/z, z17.h, #0.0");
+  COMPARE_PREFIX(fcmeq(p9.VnS(), p1.Zeroing(), z17.VnS(), 0),
+                 "fcmeq p9.s, p1/z, z17.s, #0.0");
+  COMPARE_PREFIX(fcmeq(p9.VnD(), p1.Zeroing(), z17.VnD(), 0),
+                 "fcmeq p9.d, p1/z, z17.d, #0.0");
+  COMPARE_PREFIX(fcmge(p13.VnH(), p3.Zeroing(), z13.VnH(), 0),
+                 "fcmge p13.h, p3/z, z13.h, #0.0");
+  COMPARE_PREFIX(fcmge(p13.VnS(), p3.Zeroing(), z13.VnS(), 0),
+                 "fcmge p13.s, p3/z, z13.s, #0.0");
+  COMPARE_PREFIX(fcmge(p13.VnD(), p3.Zeroing(), z13.VnD(), 0),
+                 "fcmge p13.d, p3/z, z13.d, #0.0");
+  COMPARE_PREFIX(fcmgt(p10.VnH(), p2.Zeroing(), z24.VnH(), 0),
+                 "fcmgt p10.h, p2/z, z24.h, #0.0");
+  COMPARE_PREFIX(fcmgt(p10.VnS(), p2.Zeroing(), z24.VnS(), 0),
+                 "fcmgt p10.s, p2/z, z24.s, #0.0");
+  COMPARE_PREFIX(fcmgt(p10.VnD(), p2.Zeroing(), z24.VnD(), 0),
+                 "fcmgt p10.d, p2/z, z24.d, #0.0");
+  COMPARE_PREFIX(fcmle(p4.VnH(), p7.Zeroing(), z1.VnH(), 0),
+                 "fcmle p4.h, p7/z, z1.h, #0.0");
+  COMPARE_PREFIX(fcmle(p4.VnS(), p7.Zeroing(), z1.VnS(), 0),
+                 "fcmle p4.s, p7/z, z1.s, #0.0");
+  COMPARE_PREFIX(fcmle(p4.VnD(), p7.Zeroing(), z1.VnD(), 0),
+                 "fcmle p4.d, p7/z, z1.d, #0.0");
+  COMPARE_PREFIX(fcmlt(p15.VnH(), p7.Zeroing(), z9.VnH(), 0),
+                 "fcmlt p15.h, p7/z, z9.h, #0.0");
+  COMPARE_PREFIX(fcmlt(p15.VnS(), p7.Zeroing(), z9.VnS(), 0),
+                 "fcmlt p15.s, p7/z, z9.s, #0.0");
+  COMPARE_PREFIX(fcmlt(p15.VnD(), p7.Zeroing(), z9.VnD(), 0),
+                 "fcmlt p15.d, p7/z, z9.d, #0.0");
+  COMPARE_PREFIX(fcmne(p14.VnH(), p7.Zeroing(), z28.VnH(), 0),
+                 "fcmne p14.h, p7/z, z28.h, #0.0");
+  COMPARE_PREFIX(fcmne(p14.VnS(), p7.Zeroing(), z28.VnS(), 0),
+                 "fcmne p14.s, p7/z, z28.s, #0.0");
+  COMPARE_PREFIX(fcmne(p14.VnD(), p7.Zeroing(), z28.VnD(), 0),
+                 "fcmne p14.d, p7/z, z28.d, #0.0");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_complex_addition) {
+  SETUP();
+
+  COMPARE_PREFIX(fcadd(z12.VnH(), p5.Merging(), z12.VnH(), z13.VnH(), 90),
+                 "fcadd z12.h, p5/m, z12.h, z13.h, #90");
+  COMPARE_PREFIX(fcadd(z12.VnS(), p5.Merging(), z12.VnS(), z13.VnS(), 90),
+                 "fcadd z12.s, p5/m, z12.s, z13.s, #90");
+  COMPARE_PREFIX(fcadd(z12.VnD(), p5.Merging(), z12.VnD(), z13.VnD(), 90),
+                 "fcadd z12.d, p5/m, z12.d, z13.d, #90");
+  COMPARE_PREFIX(fcadd(z22.VnH(), p0.Merging(), z22.VnH(), z23.VnH(), 270),
+                 "fcadd z22.h, p0/m, z22.h, z23.h, #270");
+  COMPARE_PREFIX(fcadd(z22.VnS(), p0.Merging(), z22.VnS(), z23.VnS(), 270),
+                 "fcadd z22.s, p0/m, z22.s, z23.s, #270");
+  COMPARE_PREFIX(fcadd(z22.VnD(), p0.Merging(), z22.VnD(), z23.VnD(), 270),
+                 "fcadd z22.d, p0/m, z22.d, z23.d, #270");
+
+  COMPARE_MACRO(Fcadd(z12.VnH(), p5.Merging(), z1.VnH(), z13.VnH(), 90),
+                "movprfx z12.h, p5/m, z1.h\n"
+                "fcadd z12.h, p5/m, z12.h, z13.h, #90");
+  COMPARE_MACRO(Fcadd(z12.VnH(), p5.Merging(), z1.VnH(), z12.VnH(), 90),
+                "movprfx z31.h, p5/m, z1.h\n"
+                "fcadd z31.h, p5/m, z31.h, z12.h, #90\n"
+                "mov z12.d, z31.d");
+  CLEANUP();
+}
+
+TEST(sve_fp_complex_mul_add) {
+  SETUP();
+
+  COMPARE_PREFIX(fcmla(z19.VnH(), p7.Merging(), z16.VnH(), z0.VnH(), 90),
+                 "fcmla z19.h, p7/m, z16.h, z0.h, #90");
+  COMPARE_PREFIX(fcmla(z19.VnS(), p7.Merging(), z16.VnS(), z0.VnS(), 90),
+                 "fcmla z19.s, p7/m, z16.s, z0.s, #90");
+  COMPARE_PREFIX(fcmla(z19.VnD(), p7.Merging(), z16.VnD(), z0.VnD(), 90),
+                 "fcmla z19.d, p7/m, z16.d, z0.d, #90");
+
+  COMPARE_PREFIX(fcmla(z20.VnD(), p6.Merging(), z15.VnD(), z1.VnD(), 0),
+                 "fcmla z20.d, p6/m, z15.d, z1.d, #0");
+  COMPARE_PREFIX(fcmla(z20.VnD(), p6.Merging(), z15.VnD(), z1.VnD(), 180),
+                 "fcmla z20.d, p6/m, z15.d, z1.d, #180");
+  COMPARE_PREFIX(fcmla(z20.VnD(), p6.Merging(), z15.VnD(), z1.VnD(), 270),
+                 "fcmla z20.d, p6/m, z15.d, z1.d, #270");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_complex_mul_add_index) {
+  SETUP();
+
+  COMPARE_PREFIX(fcmla(z30.VnH(), z20.VnH(), z3.VnH(), 0, 0),
+                 "fcmla z30.h, z20.h, z3.h[0], #0");
+  COMPARE_PREFIX(fcmla(z30.VnH(), z20.VnH(), z3.VnH(), 1, 0),
+                 "fcmla z30.h, z20.h, z3.h[1], #0");
+  COMPARE_PREFIX(fcmla(z30.VnH(), z20.VnH(), z3.VnH(), 2, 90),
+                 "fcmla z30.h, z20.h, z3.h[2], #90");
+  COMPARE_PREFIX(fcmla(z30.VnH(), z20.VnH(), z3.VnH(), 0, 270),
+                 "fcmla z30.h, z20.h, z3.h[0], #270");
+  COMPARE_PREFIX(fcmla(z10.VnS(), z20.VnS(), z1.VnS(), 0, 0),
+                 "fcmla z10.s, z20.s, z1.s[0], #0");
+  COMPARE_PREFIX(fcmla(z10.VnS(), z20.VnS(), z1.VnS(), 1, 0),
+                 "fcmla z10.s, z20.s, z1.s[1], #0");
+  COMPARE_PREFIX(fcmla(z10.VnS(), z20.VnS(), z1.VnS(), 1, 90),
+                 "fcmla z10.s, z20.s, z1.s[1], #90");
+  COMPARE_PREFIX(fcmla(z10.VnS(), z20.VnS(), z1.VnS(), 0, 270),
+                 "fcmla z10.s, z20.s, z1.s[0], #270");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_fast_reduction) {
+  SETUP();
+
+  COMPARE_PREFIX(faddv(h26, p6, z16.VnH()), "faddv h26, p6, z16.h");
+  COMPARE_PREFIX(faddv(s26, p6, z16.VnS()), "faddv s26, p6, z16.s");
+  COMPARE_PREFIX(faddv(d26, p6, z16.VnD()), "faddv d26, p6, z16.d");
+  COMPARE_PREFIX(fmaxnmv(h28, p1, z0.VnH()), "fmaxnmv h28, p1, z0.h");
+  COMPARE_PREFIX(fmaxnmv(s28, p1, z0.VnS()), "fmaxnmv s28, p1, z0.s");
+  COMPARE_PREFIX(fmaxnmv(d28, p1, z0.VnD()), "fmaxnmv d28, p1, z0.d");
+  COMPARE_PREFIX(fmaxv(h3, p1, z23.VnH()), "fmaxv h3, p1, z23.h");
+  COMPARE_PREFIX(fmaxv(s3, p1, z23.VnS()), "fmaxv s3, p1, z23.s");
+  COMPARE_PREFIX(fmaxv(d3, p1, z23.VnD()), "fmaxv d3, p1, z23.d");
+  COMPARE_PREFIX(fminnmv(h20, p6, z21.VnH()), "fminnmv h20, p6, z21.h");
+  COMPARE_PREFIX(fminnmv(s20, p6, z21.VnS()), "fminnmv s20, p6, z21.s");
+  COMPARE_PREFIX(fminnmv(d20, p6, z21.VnD()), "fminnmv d20, p6, z21.d");
+  COMPARE_PREFIX(fminv(h10, p4, z27.VnH()), "fminv h10, p4, z27.h");
+  COMPARE_PREFIX(fminv(s10, p4, z27.VnS()), "fminv s10, p4, z27.s");
+  COMPARE_PREFIX(fminv(d10, p4, z27.VnD()), "fminv d10, p4, z27.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_mul_add) {
+  SETUP();
+
+  COMPARE_PREFIX(fmad(z31.VnH(), p2.Merging(), z8.VnH(), z1.VnH()),
+                 "fmad z31.h, p2/m, z8.h, z1.h");
+  COMPARE_PREFIX(fmad(z31.VnS(), p2.Merging(), z8.VnS(), z1.VnS()),
+                 "fmad z31.s, p2/m, z8.s, z1.s");
+  COMPARE_PREFIX(fmad(z31.VnD(), p2.Merging(), z8.VnD(), z1.VnD()),
+                 "fmad z31.d, p2/m, z8.d, z1.d");
+  COMPARE_PREFIX(fmla(z26.VnH(), p7.Merging(), z19.VnH(), z16.VnH()),
+                 "fmla z26.h, p7/m, z19.h, z16.h");
+  COMPARE_PREFIX(fmla(z26.VnS(), p7.Merging(), z19.VnS(), z16.VnS()),
+                 "fmla z26.s, p7/m, z19.s, z16.s");
+  COMPARE_PREFIX(fmla(z26.VnD(), p7.Merging(), z19.VnD(), z16.VnD()),
+                 "fmla z26.d, p7/m, z19.d, z16.d");
+  COMPARE_PREFIX(fmls(z20.VnH(), p6.Merging(), z28.VnH(), z0.VnH()),
+                 "fmls z20.h, p6/m, z28.h, z0.h");
+  COMPARE_PREFIX(fmls(z20.VnS(), p6.Merging(), z28.VnS(), z0.VnS()),
+                 "fmls z20.s, p6/m, z28.s, z0.s");
+  COMPARE_PREFIX(fmls(z20.VnD(), p6.Merging(), z28.VnD(), z0.VnD()),
+                 "fmls z20.d, p6/m, z28.d, z0.d");
+  COMPARE_PREFIX(fmsb(z3.VnH(), p4.Merging(), z8.VnH(), z22.VnH()),
+                 "fmsb z3.h, p4/m, z8.h, z22.h");
+  COMPARE_PREFIX(fmsb(z3.VnS(), p4.Merging(), z8.VnS(), z22.VnS()),
+                 "fmsb z3.s, p4/m, z8.s, z22.s");
+  COMPARE_PREFIX(fmsb(z3.VnD(), p4.Merging(), z8.VnD(), z22.VnD()),
+                 "fmsb z3.d, p4/m, z8.d, z22.d");
+  COMPARE_PREFIX(fnmad(z0.VnH(), p5.Merging(), z20.VnH(), z17.VnH()),
+                 "fnmad z0.h, p5/m, z20.h, z17.h");
+  COMPARE_PREFIX(fnmad(z0.VnS(), p5.Merging(), z20.VnS(), z17.VnS()),
+                 "fnmad z0.s, p5/m, z20.s, z17.s");
+  COMPARE_PREFIX(fnmad(z0.VnD(), p5.Merging(), z20.VnD(), z17.VnD()),
+                 "fnmad z0.d, p5/m, z20.d, z17.d");
+  COMPARE_PREFIX(fnmla(z31.VnH(), p6.Merging(), z14.VnH(), z8.VnH()),
+                 "fnmla z31.h, p6/m, z14.h, z8.h");
+  COMPARE_PREFIX(fnmla(z31.VnS(), p6.Merging(), z14.VnS(), z8.VnS()),
+                 "fnmla z31.s, p6/m, z14.s, z8.s");
+  COMPARE_PREFIX(fnmla(z31.VnD(), p6.Merging(), z14.VnD(), z8.VnD()),
+                 "fnmla z31.d, p6/m, z14.d, z8.d");
+  COMPARE_PREFIX(fnmls(z2.VnH(), p1.Merging(), z23.VnH(), z15.VnH()),
+                 "fnmls z2.h, p1/m, z23.h, z15.h");
+  COMPARE_PREFIX(fnmls(z2.VnS(), p1.Merging(), z23.VnS(), z15.VnS()),
+                 "fnmls z2.s, p1/m, z23.s, z15.s");
+  COMPARE_PREFIX(fnmls(z2.VnD(), p1.Merging(), z23.VnD(), z15.VnD()),
+                 "fnmls z2.d, p1/m, z23.d, z15.d");
+  COMPARE_PREFIX(fnmsb(z28.VnH(), p3.Merging(), z26.VnH(), z11.VnH()),
+                 "fnmsb z28.h, p3/m, z26.h, z11.h");
+  COMPARE_PREFIX(fnmsb(z28.VnS(), p3.Merging(), z26.VnS(), z11.VnS()),
+                 "fnmsb z28.s, p3/m, z26.s, z11.s");
+  COMPARE_PREFIX(fnmsb(z28.VnD(), p3.Merging(), z26.VnD(), z11.VnD()),
+                 "fnmsb z28.d, p3/m, z26.d, z11.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_mul_add_macro_strict_nan_propagation) {
+  // Shadow the `MacroAssembler` type so that the test macros work without
+  // modification.
+  typedef StrictNaNPropagationMacroAssembler MacroAssembler;
+
+  SETUP();
+
+  COMPARE_MACRO(Fmla(z0.VnH(), p1.Merging(), z0.VnH(), z2.VnH(), z4.VnH()),
+                "fmla z0.h, p1/m, z2.h, z4.h");
+  COMPARE_MACRO(Fmla(z3.VnH(), p2.Merging(), z4.VnH(), z3.VnH(), z5.VnH()),
+                "fmad z3.h, p2/m, z5.h, z4.h");
+  COMPARE_MACRO(Fmla(z4.VnS(), p3.Merging(), z5.VnS(), z6.VnS(), z4.VnS()),
+                "movprfx z31.s, p3/m, z5.s\n"
+                "fmla z31.s, p3/m, z6.s, z4.s\n"
+                "mov z4.d, z31.d");
+  COMPARE_MACRO(Fmla(z5.VnD(), p4.Merging(), z6.VnD(), z7.VnD(), z8.VnD()),
+                "movprfx z5.d, p4/m, z6.d\n"
+                "fmla z5.d, p4/m, z7.d, z8.d");
+
+  COMPARE_MACRO(Fmls(z0.VnD(), p1.Merging(), z0.VnD(), z2.VnD(), z4.VnD()),
+                "fmls z0.d, p1/m, z2.d, z4.d");
+  COMPARE_MACRO(Fmls(z3.VnS(), p2.Merging(), z4.VnS(), z3.VnS(), z5.VnS()),
+                "fmsb z3.s, p2/m, z5.s, z4.s");
+  COMPARE_MACRO(Fmls(z4.VnH(), p3.Merging(), z5.VnH(), z6.VnH(), z4.VnH()),
+                "movprfx z31.h, p3/m, z5.h\n"
+                "fmls z31.h, p3/m, z6.h, z4.h\n"
+                "mov z4.d, z31.d");
+  COMPARE_MACRO(Fmls(z5.VnD(), p4.Merging(), z6.VnD(), z7.VnD(), z8.VnD()),
+                "movprfx z5.d, p4/m, z6.d\n"
+                "fmls z5.d, p4/m, z7.d, z8.d");
+
+  COMPARE_MACRO(Fnmla(z10.VnH(), p5.Merging(), z10.VnH(), z12.VnH(), z14.VnH()),
+                "fnmla z10.h, p5/m, z12.h, z14.h");
+  COMPARE_MACRO(Fnmla(z13.VnH(), p6.Merging(), z14.VnH(), z13.VnH(), z15.VnH()),
+                "fnmad z13.h, p6/m, z15.h, z14.h");
+  COMPARE_MACRO(Fnmla(z14.VnS(), p7.Merging(), z15.VnS(), z16.VnS(), z14.VnS()),
+                "movprfx z31.s, p7/m, z15.s\n"
+                "fnmla z31.s, p7/m, z16.s, z14.s\n"
+                "mov z14.d, z31.d");
+  COMPARE_MACRO(Fnmla(z15.VnD(), p0.Merging(), z16.VnD(), z17.VnD(), z18.VnD()),
+                "movprfx z15.d, p0/m, z16.d\n"
+                "fnmla z15.d, p0/m, z17.d, z18.d");
+
+  COMPARE_MACRO(Fnmls(z10.VnD(), p5.Merging(), z10.VnD(), z12.VnD(), z14.VnD()),
+                "fnmls z10.d, p5/m, z12.d, z14.d");
+  COMPARE_MACRO(Fnmls(z13.VnS(), p6.Merging(), z14.VnS(), z13.VnS(), z15.VnS()),
+                "fnmsb z13.s, p6/m, z15.s, z14.s");
+  COMPARE_MACRO(Fnmls(z14.VnH(), p7.Merging(), z15.VnH(), z16.VnH(), z14.VnH()),
+                "movprfx z31.h, p7/m, z15.h\n"
+                "fnmls z31.h, p7/m, z16.h, z14.h\n"
+                "mov z14.d, z31.d");
+  COMPARE_MACRO(Fnmls(z15.VnD(), p0.Merging(), z16.VnD(), z17.VnD(), z18.VnD()),
+                "movprfx z15.d, p0/m, z16.d\n"
+                "fnmls z15.d, p0/m, z17.d, z18.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_mul_add_macro_fast_nan_propagation) {
+  // Shadow the `MacroAssembler` type so that the test macros work without
+  // modification.
+  typedef FastNaNPropagationMacroAssembler MacroAssembler;
+
+  SETUP();
+
+  COMPARE_MACRO(Fmla(z0.VnH(), p1.Merging(), z0.VnH(), z2.VnH(), z4.VnH()),
+                "fmla z0.h, p1/m, z2.h, z4.h");
+  COMPARE_MACRO(Fmla(z3.VnH(), p2.Merging(), z4.VnH(), z3.VnH(), z5.VnH()),
+                "fmad z3.h, p2/m, z5.h, z4.h");
+  COMPARE_MACRO(Fmla(z4.VnS(), p3.Merging(), z5.VnS(), z6.VnS(), z4.VnS()),
+                "fmad z4.s, p3/m, z6.s, z5.s");
+  COMPARE_MACRO(Fmla(z5.VnD(), p4.Merging(), z6.VnD(), z7.VnD(), z8.VnD()),
+                "movprfx z5.d, p4/m, z6.d\n"
+                "fmla z5.d, p4/m, z7.d, z8.d");
+
+  COMPARE_MACRO(Fmls(z0.VnD(), p1.Merging(), z0.VnD(), z2.VnD(), z4.VnD()),
+                "fmls z0.d, p1/m, z2.d, z4.d");
+  COMPARE_MACRO(Fmls(z3.VnS(), p2.Merging(), z4.VnS(), z3.VnS(), z5.VnS()),
+                "fmsb z3.s, p2/m, z5.s, z4.s");
+  COMPARE_MACRO(Fmls(z4.VnH(), p3.Merging(), z5.VnH(), z6.VnH(), z4.VnH()),
+                "fmsb z4.h, p3/m, z6.h, z5.h");
+  COMPARE_MACRO(Fmls(z5.VnD(), p4.Merging(), z6.VnD(), z7.VnD(), z8.VnD()),
+                "movprfx z5.d, p4/m, z6.d\n"
+                "fmls z5.d, p4/m, z7.d, z8.d");
+
+  COMPARE_MACRO(Fnmla(z10.VnH(), p5.Merging(), z10.VnH(), z12.VnH(), z14.VnH()),
+                "fnmla z10.h, p5/m, z12.h, z14.h");
+  COMPARE_MACRO(Fnmla(z13.VnH(), p6.Merging(), z14.VnH(), z13.VnH(), z15.VnH()),
+                "fnmad z13.h, p6/m, z15.h, z14.h");
+  COMPARE_MACRO(Fnmla(z14.VnS(), p7.Merging(), z15.VnS(), z16.VnS(), z14.VnS()),
+                "fnmad z14.s, p7/m, z16.s, z15.s");
+  COMPARE_MACRO(Fnmla(z15.VnD(), p0.Merging(), z16.VnD(), z17.VnD(), z18.VnD()),
+                "movprfx z15.d, p0/m, z16.d\n"
+                "fnmla z15.d, p0/m, z17.d, z18.d");
+
+  COMPARE_MACRO(Fnmls(z10.VnD(), p5.Merging(), z10.VnD(), z12.VnD(), z14.VnD()),
+                "fnmls z10.d, p5/m, z12.d, z14.d");
+  COMPARE_MACRO(Fnmls(z13.VnS(), p6.Merging(), z14.VnS(), z13.VnS(), z15.VnS()),
+                "fnmsb z13.s, p6/m, z15.s, z14.s");
+  COMPARE_MACRO(Fnmls(z14.VnH(), p7.Merging(), z15.VnH(), z16.VnH(), z14.VnH()),
+                "fnmsb z14.h, p7/m, z16.h, z15.h");
+  COMPARE_MACRO(Fnmls(z15.VnD(), p0.Merging(), z16.VnD(), z17.VnD(), z18.VnD()),
+                "movprfx z15.d, p0/m, z16.d\n"
+                "fnmls z15.d, p0/m, z17.d, z18.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_mul_add_index) {
+  SETUP();
+
+  COMPARE_PREFIX(fmla(z25.VnD(), z9.VnD(), z1.VnD(), 0),
+                 "fmla z25.d, z9.d, z1.d[0]");
+  COMPARE_PREFIX(fmla(z25.VnD(), z9.VnD(), z1.VnD(), 1),
+                 "fmla z25.d, z9.d, z1.d[1]");
+
+  COMPARE_PREFIX(fmla(z13.VnH(), z7.VnH(), z7.VnH(), 0),
+                 "fmla z13.h, z7.h, z7.h[0]");
+  COMPARE_PREFIX(fmla(z13.VnH(), z7.VnH(), z7.VnH(), 2),
+                 "fmla z13.h, z7.h, z7.h[2]");
+  COMPARE_PREFIX(fmla(z13.VnH(), z7.VnH(), z7.VnH(), 5),
+                 "fmla z13.h, z7.h, z7.h[5]");
+  COMPARE_PREFIX(fmla(z13.VnH(), z7.VnH(), z7.VnH(), 7),
+                 "fmla z13.h, z7.h, z7.h[7]");
+
+  COMPARE_PREFIX(fmla(z17.VnS(), z27.VnS(), z2.VnS(), 0),
+                 "fmla z17.s, z27.s, z2.s[0]");
+  COMPARE_PREFIX(fmla(z17.VnS(), z27.VnS(), z2.VnS(), 1),
+                 "fmla z17.s, z27.s, z2.s[1]");
+  COMPARE_PREFIX(fmla(z17.VnS(), z27.VnS(), z2.VnS(), 2),
+                 "fmla z17.s, z27.s, z2.s[2]");
+  COMPARE_PREFIX(fmla(z17.VnS(), z27.VnS(), z2.VnS(), 3),
+                 "fmla z17.s, z27.s, z2.s[3]");
+
+  COMPARE_PREFIX(fmls(z28.VnD(), z2.VnD(), z0.VnD(), 0),
+                 "fmls z28.d, z2.d, z0.d[0]");
+  COMPARE_PREFIX(fmls(z28.VnD(), z2.VnD(), z0.VnD(), 1),
+                 "fmls z28.d, z2.d, z0.d[1]");
+
+  COMPARE_PREFIX(fmls(z30.VnH(), z29.VnH(), z7.VnH(), 1),
+                 "fmls z30.h, z29.h, z7.h[1]");
+  COMPARE_PREFIX(fmls(z30.VnH(), z29.VnH(), z7.VnH(), 4),
+                 "fmls z30.h, z29.h, z7.h[4]");
+  COMPARE_PREFIX(fmls(z30.VnH(), z29.VnH(), z7.VnH(), 3),
+                 "fmls z30.h, z29.h, z7.h[3]");
+  COMPARE_PREFIX(fmls(z30.VnH(), z29.VnH(), z7.VnH(), 6),
+                 "fmls z30.h, z29.h, z7.h[6]");
+
+  COMPARE_PREFIX(fmls(z30.VnS(), z1.VnS(), z6.VnS(), 0),
+                 "fmls z30.s, z1.s, z6.s[0]");
+  COMPARE_PREFIX(fmls(z30.VnS(), z1.VnS(), z6.VnS(), 1),
+                 "fmls z30.s, z1.s, z6.s[1]");
+  COMPARE_PREFIX(fmls(z30.VnS(), z1.VnS(), z6.VnS(), 2),
+                 "fmls z30.s, z1.s, z6.s[2]");
+  COMPARE_PREFIX(fmls(z30.VnS(), z1.VnS(), z6.VnS(), 3),
+                 "fmls z30.s, z1.s, z6.s[3]");
+
+  COMPARE_MACRO(Fmla(z10.VnH(), z11.VnH(), z12.VnH(), z4.VnH(), 7),
+                "movprfx z10, z11\n"
+                "fmla z10.h, z12.h, z4.h[7]");
+  COMPARE_MACRO(Fmla(z10.VnH(), z10.VnH(), z12.VnH(), z4.VnH(), 6),
+                "fmla z10.h, z12.h, z4.h[6]");
+  COMPARE_MACRO(Fmla(z11.VnS(), z12.VnS(), z11.VnS(), z5.VnS(), 3),
+                "movprfx z31, z12\n"
+                "fmla z31.s, z11.s, z5.s[3]\n"
+                "mov z11.d, z31.d");
+  COMPARE_MACRO(Fmla(z12.VnD(), z13.VnD(), z14.VnD(), z12.VnD(), 1),
+                "movprfx z31, z13\n"
+                "fmla z31.d, z14.d, z12.d[1]\n"
+                "mov z12.d, z31.d");
+
+  COMPARE_MACRO(Fmls(z10.VnH(), z11.VnH(), z12.VnH(), z4.VnH(), 7),
+                "movprfx z10, z11\n"
+                "fmls z10.h, z12.h, z4.h[7]");
+  COMPARE_MACRO(Fmls(z10.VnH(), z10.VnH(), z12.VnH(), z4.VnH(), 6),
+                "fmls z10.h, z12.h, z4.h[6]");
+  COMPARE_MACRO(Fmls(z11.VnS(), z12.VnS(), z11.VnS(), z5.VnS(), 3),
+                "movprfx z31, z12\n"
+                "fmls z31.s, z11.s, z5.s[3]\n"
+                "mov z11.d, z31.d");
+  COMPARE_MACRO(Fmls(z12.VnD(), z13.VnD(), z14.VnD(), z12.VnD(), 1),
+                "movprfx z31, z13\n"
+                "fmls z31.d, z14.d, z12.d[1]\n"
+                "mov z12.d, z31.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_mul_index) {
+  SETUP();
+
+  COMPARE_PREFIX(fmul(z12.VnD(), z3.VnD(), z4.VnD(), 0),
+                 "fmul z12.d, z3.d, z4.d[0]");
+  COMPARE_PREFIX(fmul(z12.VnD(), z3.VnD(), z4.VnD(), 1),
+                 "fmul z12.d, z3.d, z4.d[1]");
+
+  COMPARE_PREFIX(fmul(z22.VnH(), z2.VnH(), z3.VnH(), 0),
+                 "fmul z22.h, z2.h, z3.h[0]");
+  COMPARE_PREFIX(fmul(z22.VnH(), z2.VnH(), z3.VnH(), 3),
+                 "fmul z22.h, z2.h, z3.h[3]");
+  COMPARE_PREFIX(fmul(z22.VnH(), z2.VnH(), z3.VnH(), 4),
+                 "fmul z22.h, z2.h, z3.h[4]");
+  COMPARE_PREFIX(fmul(z22.VnH(), z2.VnH(), z3.VnH(), 7),
+                 "fmul z22.h, z2.h, z3.h[7]");
+
+  COMPARE_PREFIX(fmul(z2.VnS(), z8.VnS(), z7.VnS(), 0),
+                 "fmul z2.s, z8.s, z7.s[0]");
+  COMPARE_PREFIX(fmul(z2.VnS(), z8.VnS(), z7.VnS(), 1),
+                 "fmul z2.s, z8.s, z7.s[1]");
+  COMPARE_PREFIX(fmul(z2.VnS(), z8.VnS(), z7.VnS(), 2),
+                 "fmul z2.s, z8.s, z7.s[2]");
+  COMPARE_PREFIX(fmul(z2.VnS(), z8.VnS(), z7.VnS(), 3),
+                 "fmul z2.s, z8.s, z7.s[3]");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_unary_op_predicated) {
+  SETUP();
+
+  COMPARE_PREFIX(fcvtzs(z29.VnS(), p5.Merging(), z8.VnD()),
+                 "fcvtzs z29.s, p5/m, z8.d");
+  COMPARE_PREFIX(fcvtzs(z30.VnD(), p5.Merging(), z8.VnD()),
+                 "fcvtzs z30.d, p5/m, z8.d");
+  COMPARE_PREFIX(fcvtzs(z14.VnH(), p1.Merging(), z29.VnH()),
+                 "fcvtzs z14.h, p1/m, z29.h");
+  COMPARE_PREFIX(fcvtzs(z11.VnS(), p3.Merging(), z16.VnH()),
+                 "fcvtzs z11.s, p3/m, z16.h");
+  COMPARE_PREFIX(fcvtzs(z4.VnD(), p7.Merging(), z4.VnH()),
+                 "fcvtzs z4.d, p7/m, z4.h");
+  COMPARE_PREFIX(fcvtzs(z24.VnS(), p1.Merging(), z4.VnS()),
+                 "fcvtzs z24.s, p1/m, z4.s");
+  COMPARE_PREFIX(fcvtzs(z25.VnD(), p4.Merging(), z24.VnS()),
+                 "fcvtzs z25.d, p4/m, z24.s");
+  COMPARE_PREFIX(fcvtzu(z16.VnS(), p7.Merging(), z14.VnD()),
+                 "fcvtzu z16.s, p7/m, z14.d");
+  COMPARE_PREFIX(fcvtzu(z31.VnD(), p1.Merging(), z16.VnD()),
+                 "fcvtzu z31.d, p1/m, z16.d");
+  COMPARE_PREFIX(fcvtzu(z12.VnH(), p2.Merging(), z27.VnH()),
+                 "fcvtzu z12.h, p2/m, z27.h");
+  COMPARE_PREFIX(fcvtzu(z26.VnS(), p6.Merging(), z29.VnH()),
+                 "fcvtzu z26.s, p6/m, z29.h");
+  COMPARE_PREFIX(fcvtzu(z29.VnD(), p5.Merging(), z27.VnH()),
+                 "fcvtzu z29.d, p5/m, z27.h");
+  COMPARE_PREFIX(fcvtzu(z13.VnS(), p2.Merging(), z17.VnS()),
+                 "fcvtzu z13.s, p2/m, z17.s");
+  COMPARE_PREFIX(fcvtzu(z25.VnD(), p7.Merging(), z28.VnS()),
+                 "fcvtzu z25.d, p7/m, z28.s");
+  COMPARE_PREFIX(scvtf(z16.VnH(), p6.Merging(), z5.VnH()),
+                 "scvtf z16.h, p6/m, z5.h");
+  COMPARE_PREFIX(scvtf(z31.VnD(), p5.Merging(), z26.VnS()),
+                 "scvtf z31.d, p5/m, z26.s");
+  COMPARE_PREFIX(scvtf(z0.VnH(), p7.Merging(), z0.VnS()),
+                 "scvtf z0.h, p7/m, z0.s");
+  COMPARE_PREFIX(scvtf(z12.VnS(), p7.Merging(), z0.VnS()),
+                 "scvtf z12.s, p7/m, z0.s");
+  COMPARE_PREFIX(scvtf(z17.VnD(), p1.Merging(), z17.VnD()),
+                 "scvtf z17.d, p1/m, z17.d");
+  COMPARE_PREFIX(scvtf(z2.VnH(), p0.Merging(), z9.VnD()),
+                 "scvtf z2.h, p0/m, z9.d");
+  COMPARE_PREFIX(scvtf(z26.VnS(), p5.Merging(), z4.VnD()),
+                 "scvtf z26.s, p5/m, z4.d");
+  COMPARE_PREFIX(ucvtf(z27.VnH(), p4.Merging(), z25.VnH()),
+                 "ucvtf z27.h, p4/m, z25.h");
+  COMPARE_PREFIX(ucvtf(z3.VnD(), p4.Merging(), z3.VnS()),
+                 "ucvtf z3.d, p4/m, z3.s");
+  COMPARE_PREFIX(ucvtf(z24.VnH(), p2.Merging(), z29.VnS()),
+                 "ucvtf z24.h, p2/m, z29.s");
+  COMPARE_PREFIX(ucvtf(z29.VnS(), p5.Merging(), z14.VnS()),
+                 "ucvtf z29.s, p5/m, z14.s");
+  COMPARE_PREFIX(ucvtf(z7.VnD(), p2.Merging(), z14.VnD()),
+                 "ucvtf z7.d, p2/m, z14.d");
+  COMPARE_PREFIX(ucvtf(z20.VnH(), p2.Merging(), z14.VnD()),
+                 "ucvtf z20.h, p2/m, z14.d");
+  COMPARE_PREFIX(ucvtf(z26.VnS(), p1.Merging(), z18.VnD()),
+                 "ucvtf z26.s, p1/m, z18.d");
+  COMPARE_PREFIX(frinta(z11.VnH(), p0.Merging(), z3.VnH()),
+                 "frinta z11.h, p0/m, z3.h");
+  COMPARE_PREFIX(frinta(z11.VnS(), p0.Merging(), z3.VnS()),
+                 "frinta z11.s, p0/m, z3.s");
+  COMPARE_PREFIX(frinta(z11.VnD(), p0.Merging(), z3.VnD()),
+                 "frinta z11.d, p0/m, z3.d");
+  COMPARE_PREFIX(frinti(z17.VnH(), p0.Merging(), z16.VnH()),
+                 "frinti z17.h, p0/m, z16.h");
+  COMPARE_PREFIX(frinti(z17.VnS(), p0.Merging(), z16.VnS()),
+                 "frinti z17.s, p0/m, z16.s");
+  COMPARE_PREFIX(frinti(z17.VnD(), p0.Merging(), z16.VnD()),
+                 "frinti z17.d, p0/m, z16.d");
+  COMPARE_PREFIX(frintm(z2.VnH(), p7.Merging(), z15.VnH()),
+                 "frintm z2.h, p7/m, z15.h");
+  COMPARE_PREFIX(frintm(z2.VnS(), p7.Merging(), z15.VnS()),
+                 "frintm z2.s, p7/m, z15.s");
+  COMPARE_PREFIX(frintm(z2.VnD(), p7.Merging(), z15.VnD()),
+                 "frintm z2.d, p7/m, z15.d");
+  COMPARE_PREFIX(frintn(z14.VnH(), p5.Merging(), z18.VnH()),
+                 "frintn z14.h, p5/m, z18.h");
+  COMPARE_PREFIX(frintn(z14.VnS(), p5.Merging(), z18.VnS()),
+                 "frintn z14.s, p5/m, z18.s");
+  COMPARE_PREFIX(frintn(z14.VnD(), p5.Merging(), z18.VnD()),
+                 "frintn z14.d, p5/m, z18.d");
+  COMPARE_PREFIX(frintp(z20.VnH(), p6.Merging(), z23.VnH()),
+                 "frintp z20.h, p6/m, z23.h");
+  COMPARE_PREFIX(frintp(z20.VnS(), p6.Merging(), z23.VnS()),
+                 "frintp z20.s, p6/m, z23.s");
+  COMPARE_PREFIX(frintp(z20.VnD(), p6.Merging(), z23.VnD()),
+                 "frintp z20.d, p6/m, z23.d");
+  COMPARE_PREFIX(frintx(z2.VnH(), p6.Merging(), z18.VnH()),
+                 "frintx z2.h, p6/m, z18.h");
+  COMPARE_PREFIX(frintx(z2.VnS(), p6.Merging(), z18.VnS()),
+                 "frintx z2.s, p6/m, z18.s");
+  COMPARE_PREFIX(frintx(z2.VnD(), p6.Merging(), z18.VnD()),
+                 "frintx z2.d, p6/m, z18.d");
+  COMPARE_PREFIX(frintz(z26.VnH(), p7.Merging(), z25.VnH()),
+                 "frintz z26.h, p7/m, z25.h");
+  COMPARE_PREFIX(frintz(z26.VnS(), p7.Merging(), z25.VnS()),
+                 "frintz z26.s, p7/m, z25.s");
+  COMPARE_PREFIX(frintz(z26.VnD(), p7.Merging(), z25.VnD()),
+                 "frintz z26.d, p7/m, z25.d");
+  COMPARE_PREFIX(fcvt(z5.VnH(), p2.Merging(), z11.VnD()),
+                 "fcvt z5.h, p2/m, z11.d");
+  COMPARE_PREFIX(fcvt(z30.VnS(), p7.Merging(), z0.VnD()),
+                 "fcvt z30.s, p7/m, z0.d");
+  COMPARE_PREFIX(fcvt(z10.VnD(), p0.Merging(), z17.VnH()),
+                 "fcvt z10.d, p0/m, z17.h");
+  COMPARE_PREFIX(fcvt(z28.VnS(), p3.Merging(), z27.VnH()),
+                 "fcvt z28.s, p3/m, z27.h");
+  COMPARE_PREFIX(fcvt(z9.VnD(), p7.Merging(), z0.VnS()),
+                 "fcvt z9.d, p7/m, z0.s");
+  COMPARE_PREFIX(fcvt(z27.VnH(), p7.Merging(), z9.VnS()),
+                 "fcvt z27.h, p7/m, z9.s");
+  COMPARE_PREFIX(frecpx(z16.VnH(), p1.Merging(), z29.VnH()),
+                 "frecpx z16.h, p1/m, z29.h");
+  COMPARE_PREFIX(frecpx(z16.VnS(), p1.Merging(), z29.VnS()),
+                 "frecpx z16.s, p1/m, z29.s");
+  COMPARE_PREFIX(frecpx(z16.VnD(), p1.Merging(), z29.VnD()),
+                 "frecpx z16.d, p1/m, z29.d");
+  COMPARE_PREFIX(fsqrt(z30.VnH(), p3.Merging(), z13.VnH()),
+                 "fsqrt z30.h, p3/m, z13.h");
+  COMPARE_PREFIX(fsqrt(z30.VnS(), p3.Merging(), z13.VnS()),
+                 "fsqrt z30.s, p3/m, z13.s");
+  COMPARE_PREFIX(fsqrt(z30.VnD(), p3.Merging(), z13.VnD()),
+                 "fsqrt z30.d, p3/m, z13.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_unary_op_predicated_macro) {
+  SETUP();
+
+  COMPARE_MACRO(Fcvt(z5.VnH(), p2.Zeroing(), z11.VnD()),
+                "movprfx z5.d, p2/z, z11.d\n"
+                "fcvt z5.h, p2/m, z11.d");
+  COMPARE_MACRO(Fcvt(z30.VnS(), p7.Zeroing(), z0.VnD()),
+                "movprfx z30.d, p7/z, z0.d\n"
+                "fcvt z30.s, p7/m, z0.d");
+  COMPARE_MACRO(Fcvt(z10.VnD(), p0.Zeroing(), z17.VnH()),
+                "movprfx z10.d, p0/z, z17.d\n"
+                "fcvt z10.d, p0/m, z17.h");
+  COMPARE_MACRO(Fcvt(z28.VnS(), p3.Zeroing(), z27.VnH()),
+                "movprfx z28.s, p3/z, z27.s\n"
+                "fcvt z28.s, p3/m, z27.h");
+  COMPARE_MACRO(Fcvt(z9.VnD(), p7.Zeroing(), z0.VnS()),
+                "movprfx z9.d, p7/z, z0.d\n"
+                "fcvt z9.d, p7/m, z0.s");
+  COMPARE_MACRO(Fcvt(z27.VnH(), p7.Zeroing(), z9.VnS()),
+                "movprfx z27.s, p7/z, z9.s\n"
+                "fcvt z27.h, p7/m, z9.s");
+  COMPARE_MACRO(Frecpx(z16.VnH(), p1.Zeroing(), z29.VnH()),
+                "movprfx z16.h, p1/z, z29.h\n"
+                "frecpx z16.h, p1/m, z29.h");
+  COMPARE_MACRO(Frecpx(z17.VnS(), p2.Zeroing(), z30.VnS()),
+                "movprfx z17.s, p2/z, z30.s\n"
+                "frecpx z17.s, p2/m, z30.s");
+  COMPARE_MACRO(Frecpx(z18.VnD(), p3.Zeroing(), z31.VnD()),
+                "movprfx z18.d, p3/z, z31.d\n"
+                "frecpx z18.d, p3/m, z31.d");
+  COMPARE_MACRO(Frinta(z6.VnD(), p3.Zeroing(), z12.VnD()),
+                "movprfx z6.d, p3/z, z12.d\n"
+                "frinta z6.d, p3/m, z12.d");
+  COMPARE_MACRO(Frinti(z7.VnS(), p3.Zeroing(), z11.VnS()),
+                "movprfx z7.s, p3/z, z11.s\n"
+                "frinti z7.s, p3/m, z11.s");
+  COMPARE_MACRO(Frintm(z8.VnH(), p3.Zeroing(), z10.VnH()),
+                "movprfx z8.h, p3/z, z10.h\n"
+                "frintm z8.h, p3/m, z10.h");
+  COMPARE_MACRO(Frintn(z9.VnD(), p3.Zeroing(), z9.VnD()),
+                "movprfx z9.d, p3/z, z9.d\n"
+                "frintn z9.d, p3/m, z9.d");
+  COMPARE_MACRO(Frintp(z10.VnS(), p3.Zeroing(), z8.VnS()),
+                "movprfx z10.s, p3/z, z8.s\n"
+                "frintp z10.s, p3/m, z8.s");
+  COMPARE_MACRO(Frintx(z11.VnH(), p3.Zeroing(), z7.VnH()),
+                "movprfx z11.h, p3/z, z7.h\n"
+                "frintx z11.h, p3/m, z7.h");
+  COMPARE_MACRO(Frintz(z12.VnD(), p3.Zeroing(), z6.VnD()),
+                "movprfx z12.d, p3/z, z6.d\n"
+                "frintz z12.d, p3/m, z6.d");
+  COMPARE_MACRO(Fsqrt(z30.VnH(), p3.Zeroing(), z13.VnH()),
+                "movprfx z30.h, p3/z, z13.h\n"
+                "fsqrt z30.h, p3/m, z13.h");
+  COMPARE_MACRO(Fsqrt(z29.VnS(), p3.Zeroing(), z14.VnS()),
+                "movprfx z29.s, p3/z, z14.s\n"
+                "fsqrt z29.s, p3/m, z14.s");
+  COMPARE_MACRO(Fsqrt(z28.VnD(), p3.Zeroing(), z15.VnD()),
+                "movprfx z28.d, p3/z, z15.d\n"
+                "fsqrt z28.d, p3/m, z15.d");
+
+  CLEANUP();
+}
+
+TEST(sve_fp_unary_op_unpredicated) {
+  SETUP();
+
+  COMPARE_PREFIX(frecpe(z0.VnH(), z2.VnH()), "frecpe z0.h, z2.h");
+  COMPARE_PREFIX(frecpe(z0.VnS(), z2.VnS()), "frecpe z0.s, z2.s");
+  COMPARE_PREFIX(frecpe(z0.VnD(), z2.VnD()), "frecpe z0.d, z2.d");
+  COMPARE_PREFIX(frsqrte(z27.VnH(), z14.VnH()), "frsqrte z27.h, z14.h");
+  COMPARE_PREFIX(frsqrte(z27.VnS(), z14.VnS()), "frsqrte z27.s, z14.s");
+  COMPARE_PREFIX(frsqrte(z27.VnD(), z14.VnD()), "frsqrte z27.d, z14.d");
+
+  CLEANUP();
+}
+
+TEST(sve_inc_dec_by_predicate_count) {
+  SETUP();
+
+  COMPARE_PREFIX(decp(x17, p0.VnB()), "decp x17, p0.b");
+  COMPARE_PREFIX(decp(x17, p0.VnH()), "decp x17, p0.h");
+  COMPARE_PREFIX(decp(x17, p0.VnS()), "decp x17, p0.s");
+  COMPARE_PREFIX(decp(x17, p0.VnD()), "decp x17, p0.d");
+  COMPARE_PREFIX(decp(z2.VnH(), p11), "decp z2.h, p11");
+  COMPARE_PREFIX(decp(z2.VnS(), p11), "decp z2.s, p11");
+  COMPARE_PREFIX(decp(z2.VnD(), p11), "decp z2.d, p11");
+  COMPARE_PREFIX(incp(x26, p8.VnB()), "incp x26, p8.b");
+  COMPARE_PREFIX(incp(x26, p8.VnH()), "incp x26, p8.h");
+  COMPARE_PREFIX(incp(x26, p8.VnS()), "incp x26, p8.s");
+  COMPARE_PREFIX(incp(x26, p8.VnD()), "incp x26, p8.d");
+  COMPARE_PREFIX(incp(z27.VnH(), p9), "incp z27.h, p9");
+  COMPARE_PREFIX(incp(z27.VnS(), p9), "incp z27.s, p9");
+  COMPARE_PREFIX(incp(z27.VnD(), p9), "incp z27.d, p9");
+  COMPARE_PREFIX(sqdecp(x12, p7.VnB(), w12), "sqdecp x12, p7.b, w12");
+  COMPARE_PREFIX(sqdecp(x12, p7.VnH(), w12), "sqdecp x12, p7.h, w12");
+  COMPARE_PREFIX(sqdecp(x12, p7.VnS(), w12), "sqdecp x12, p7.s, w12");
+  COMPARE_PREFIX(sqdecp(x12, p7.VnD(), w12), "sqdecp x12, p7.d, w12");
+  COMPARE_PREFIX(sqdecp(x30, p5.VnB()), "sqdecp x30, p5.b");
+  COMPARE_PREFIX(sqdecp(x30, p5.VnH()), "sqdecp x30, p5.h");
+  COMPARE_PREFIX(sqdecp(x30, p5.VnS()), "sqdecp x30, p5.s");
+  COMPARE_PREFIX(sqdecp(x30, p5.VnD()), "sqdecp x30, p5.d");
+  COMPARE_PREFIX(sqdecp(z13.VnH(), p1), "sqdecp z13.h, p1");
+  COMPARE_PREFIX(sqdecp(z13.VnS(), p1), "sqdecp z13.s, p1");
+  COMPARE_PREFIX(sqdecp(z13.VnD(), p1), "sqdecp z13.d, p1");
+  COMPARE_PREFIX(sqincp(x26, p5.VnB(), w26), "sqincp x26, p5.b, w26");
+  COMPARE_PREFIX(sqincp(x26, p5.VnH(), w26), "sqincp x26, p5.h, w26");
+  COMPARE_PREFIX(sqincp(x26, p5.VnS(), w26), "sqincp x26, p5.s, w26");
+  COMPARE_PREFIX(sqincp(x26, p5.VnD(), w26), "sqincp x26, p5.d, w26");
+  COMPARE_PREFIX(sqincp(x5, p15.VnB()), "sqincp x5, p15.b");
+  COMPARE_PREFIX(sqincp(x5, p15.VnH()), "sqincp x5, p15.h");
+  COMPARE_PREFIX(sqincp(x5, p15.VnS()), "sqincp x5, p15.s");
+  COMPARE_PREFIX(sqincp(x5, p15.VnD()), "sqincp x5, p15.d");
+  COMPARE_PREFIX(sqincp(z14.VnH(), p4), "sqincp z14.h, p4");
+  COMPARE_PREFIX(sqincp(z14.VnS(), p4), "sqincp z14.s, p4");
+  COMPARE_PREFIX(sqincp(z14.VnD(), p4), "sqincp z14.d, p4");
+  COMPARE_PREFIX(uqdecp(w3, p13.VnB()), "uqdecp w3, p13.b");
+  COMPARE_PREFIX(uqdecp(w3, p13.VnH()), "uqdecp w3, p13.h");
+  COMPARE_PREFIX(uqdecp(w3, p13.VnS()), "uqdecp w3, p13.s");
+  COMPARE_PREFIX(uqdecp(w3, p13.VnD()), "uqdecp w3, p13.d");
+  COMPARE_PREFIX(uqdecp(x19, p0.VnB()), "uqdecp x19, p0.b");
+  COMPARE_PREFIX(uqdecp(x19, p0.VnH()), "uqdecp x19, p0.h");
+  COMPARE_PREFIX(uqdecp(x19, p0.VnS()), "uqdecp x19, p0.s");
+  COMPARE_PREFIX(uqdecp(x19, p0.VnD()), "uqdecp x19, p0.d");
+  COMPARE_PREFIX(uqdecp(z15.VnH(), p9), "uqdecp z15.h, p9");
+  COMPARE_PREFIX(uqdecp(z15.VnS(), p9), "uqdecp z15.s, p9");
+  COMPARE_PREFIX(uqdecp(z15.VnD(), p9), "uqdecp z15.d, p9");
+  COMPARE_PREFIX(uqincp(w18, p1.VnB()), "uqincp w18, p1.b");
+  COMPARE_PREFIX(uqincp(w18, p1.VnH()), "uqincp w18, p1.h");
+  COMPARE_PREFIX(uqincp(w18, p1.VnS()), "uqincp w18, p1.s");
+  COMPARE_PREFIX(uqincp(w18, p1.VnD()), "uqincp w18, p1.d");
+  COMPARE_PREFIX(uqincp(x17, p15.VnB()), "uqincp x17, p15.b");
+  COMPARE_PREFIX(uqincp(x17, p15.VnH()), "uqincp x17, p15.h");
+  COMPARE_PREFIX(uqincp(x17, p15.VnS()), "uqincp x17, p15.s");
+  COMPARE_PREFIX(uqincp(x17, p15.VnD()), "uqincp x17, p15.d");
+  COMPARE_PREFIX(uqincp(z4.VnH(), p3), "uqincp z4.h, p3");
+  COMPARE_PREFIX(uqincp(z4.VnS(), p3), "uqincp z4.s, p3");
+  COMPARE_PREFIX(uqincp(z4.VnD(), p3), "uqincp z4.d, p3");
+
+  CLEANUP();
+}
+
+TEST(sve_inc_dec_by_predicate_count_macro) {
+  SETUP();
+
+  // The MacroAssembler automatically generates movprfx where it can.
+  COMPARE_MACRO(Decp(z0.VnD(), p1), "decp z0.d, p1");
+  COMPARE_MACRO(Decp(z2.VnS(), p3, z2.VnS()), "decp z2.s, p3");
+  COMPARE_MACRO(Decp(z3.VnS(), p3, z3.VnS()), "decp z3.s, p3");
+  COMPARE_MACRO(Decp(z4.VnH(), p5, z6.VnH()),
+                "movprfx z4, z6\n"
+                "decp z4.h, p5");
+  COMPARE_MACRO(Incp(z7.VnD(), p8), "incp z7.d, p8");
+  COMPARE_MACRO(Incp(z9.VnS(), p10, z9.VnS()), "incp z9.s, p10");
+  COMPARE_MACRO(Incp(z10.VnS(), p10, z10.VnS()), "incp z10.s, p10");
+  COMPARE_MACRO(Incp(z10.VnH(), p11, z12.VnH()),
+                "movprfx z10, z12\n"
+                "incp z10.h, p11");
+  COMPARE_MACRO(Sqdecp(z0.VnD(), p1), "sqdecp z0.d, p1");
+  COMPARE_MACRO(Sqdecp(z2.VnS(), p3, z2.VnS()), "sqdecp z2.s, p3");
+  COMPARE_MACRO(Sqdecp(z3.VnS(), p3, z3.VnS()), "sqdecp z3.s, p3");
+  COMPARE_MACRO(Sqdecp(z4.VnH(), p5, z6.VnH()),
+                "movprfx z4, z6\n"
+                "sqdecp z4.h, p5");
+  COMPARE_MACRO(Sqincp(z7.VnD(), p8), "sqincp z7.d, p8");
+  COMPARE_MACRO(Sqincp(z9.VnS(), p10, z9.VnS()), "sqincp z9.s, p10");
+  COMPARE_MACRO(Sqincp(z10.VnS(), p10, z10.VnS()), "sqincp z10.s, p10");
+  COMPARE_MACRO(Sqincp(z10.VnH(), p11, z12.VnH()),
+                "movprfx z10, z12\n"
+                "sqincp z10.h, p11");
+  COMPARE_MACRO(Uqdecp(z0.VnD(), p1), "uqdecp z0.d, p1");
+  COMPARE_MACRO(Uqdecp(z2.VnS(), p3, z2.VnS()), "uqdecp z2.s, p3");
+  COMPARE_MACRO(Uqdecp(z3.VnS(), p3, z3.VnS()), "uqdecp z3.s, p3");
+  COMPARE_MACRO(Uqdecp(z4.VnH(), p5, z6.VnH()),
+                "movprfx z4, z6\n"
+                "uqdecp z4.h, p5");
+  COMPARE_MACRO(Uqincp(z7.VnD(), p8), "uqincp z7.d, p8");
+  COMPARE_MACRO(Uqincp(z9.VnS(), p10, z9.VnS()), "uqincp z9.s, p10");
+  COMPARE_MACRO(Uqincp(z10.VnS(), p10, z10.VnS()), "uqincp z10.s, p10");
+  COMPARE_MACRO(Uqincp(z10.VnH(), p11, z12.VnH()),
+                "movprfx z10, z12\n"
+                "uqincp z10.h, p11");
+
+  // Sqdecp cannot write into a W register, but Uqdecp can.
+  COMPARE_MACRO(Uqdecp(w6, p7.VnD()), "uqdecp w6, p7.d");
+  COMPARE_MACRO(Uqdecp(x10, p11.VnH()), "uqdecp x10, p11.h");
+  COMPARE_MACRO(Uqdecp(x12, p13.VnS()), "uqdecp x12, p13.s");
+  COMPARE_MACRO(Uqdecp(w14, p15.VnD()), "uqdecp w14, p15.d");
+
+  CLEANUP();
+}
+
+TEST(sve_index_generation) {
+  SETUP();
+
+  COMPARE_PREFIX(index(z21.VnB(), -16, 15), "index z21.b, #-16, #15");
+  COMPARE_PREFIX(index(z22.VnB(), -2, 1), "index z22.b, #-2, #1");
+  COMPARE_PREFIX(index(z23.VnH(), -1, 0), "index z23.h, #-1, #0");
+  COMPARE_PREFIX(index(z24.VnS(), 0, -1), "index z24.s, #0, #-1");
+  COMPARE_PREFIX(index(z25.VnD(), 1, -2), "index z25.d, #1, #-2");
+  COMPARE_PREFIX(index(z26.VnB(), 15, -16), "index z26.b, #15, #-16");
+  COMPARE_PREFIX(index(z23.VnB(), -16, w8), "index z23.b, #-16, w8");
+  COMPARE_PREFIX(index(z24.VnH(), -1, x9), "index z24.h, #-1, w9");
+  COMPARE_PREFIX(index(z25.VnS(), 0, w10), "index z25.s, #0, w10");
+  COMPARE_PREFIX(index(z26.VnD(), 15, x11), "index z26.d, #15, x11");
+  COMPARE_PREFIX(index(z14.VnB(), w15, 15), "index z14.b, w15, #15");
+  COMPARE_PREFIX(index(z15.VnH(), x16, 1), "index z15.h, w16, #1");
+  COMPARE_PREFIX(index(z16.VnS(), w17, 0), "index z16.s, w17, #0");
+  COMPARE_PREFIX(index(z17.VnD(), x18, -16), "index z17.d, x18, #-16");
+  COMPARE_PREFIX(index(z20.VnB(), w23, w21), "index z20.b, w23, w21");
+  COMPARE_PREFIX(index(z21.VnH(), x24, w22), "index z21.h, w24, w22");
+  COMPARE_PREFIX(index(z22.VnS(), w25, x23), "index z22.s, w25, w23");
+  COMPARE_PREFIX(index(z23.VnD(), x26, x24), "index z23.d, x26, x24");
+
+  // Simple pass-through macros.
+  COMPARE_MACRO(Index(z21.VnB(), -16, 15), "index z21.b, #-16, #15");
+  COMPARE_MACRO(Index(z22.VnB(), -2, 1), "index z22.b, #-2, #1");
+  COMPARE_MACRO(Index(z23.VnH(), -1, 0), "index z23.h, #-1, #0");
+  COMPARE_MACRO(Index(z24.VnS(), 0, -1), "index z24.s, #0, #-1");
+  COMPARE_MACRO(Index(z25.VnD(), 1, -2), "index z25.d, #1, #-2");
+  COMPARE_MACRO(Index(z26.VnB(), 15, -16), "index z26.b, #15, #-16");
+  COMPARE_MACRO(Index(z23.VnB(), -16, w8), "index z23.b, #-16, w8");
+  COMPARE_MACRO(Index(z24.VnH(), -1, x9), "index z24.h, #-1, w9");
+  COMPARE_MACRO(Index(z25.VnS(), 0, w10), "index z25.s, #0, w10");
+  COMPARE_MACRO(Index(z26.VnD(), 15, x11), "index z26.d, #15, x11");
+  COMPARE_MACRO(Index(z14.VnB(), w15, 15), "index z14.b, w15, #15");
+  COMPARE_MACRO(Index(z15.VnH(), x16, 1), "index z15.h, w16, #1");
+  COMPARE_MACRO(Index(z16.VnS(), w17, 0), "index z16.s, w17, #0");
+  COMPARE_MACRO(Index(z17.VnD(), x18, -16), "index z17.d, x18, #-16");
+  COMPARE_MACRO(Index(z20.VnB(), w23, w21), "index z20.b, w23, w21");
+  COMPARE_MACRO(Index(z21.VnH(), x24, w22), "index z21.h, w24, w22");
+  COMPARE_MACRO(Index(z22.VnS(), w25, x23), "index z22.s, w25, w23");
+  COMPARE_MACRO(Index(z23.VnD(), x26, x24), "index z23.d, x26, x24");
+
+  // Argument synthesis.
+  COMPARE_MACRO(Index(z0.VnB(), 16, -17),
+                "mov w16, #0x10\n"
+                "mov w17, #0xffffffef\n"
+                "index z0.b, w16, w17");
+  COMPARE_MACRO(Index(z1.VnH(), x2, -17),
+                "mov w16, #0xffffffef\n"
+                "index z1.h, w2, w16");
+  COMPARE_MACRO(Index(z3.VnS(), 16, w4),
+                "mov w16, #0x10\n"
+                "index z3.s, w16, w4");
+  COMPARE_MACRO(Index(z4.VnD(), -17, 16),
+                "mov x16, #0xffffffffffffffef\n"
+                "mov x17, #0x10\n"
+                "index z4.d, x16, x17");
+
+  CLEANUP();
+}
+
+TEST(sve_int_arithmetic_unpredicated) {
+  SETUP();
+
+  COMPARE_PREFIX(add(z23.VnB(), z30.VnB(), z31.VnB()),
+                 "add z23.b, z30.b, z31.b");
+  COMPARE_PREFIX(add(z24.VnH(), z29.VnH(), z30.VnH()),
+                 "add z24.h, z29.h, z30.h");
+  COMPARE_PREFIX(add(z25.VnS(), z28.VnS(), z29.VnS()),
+                 "add z25.s, z28.s, z29.s");
+  COMPARE_PREFIX(add(z26.VnD(), z27.VnD(), z28.VnD()),
+                 "add z26.d, z27.d, z28.d");
+  COMPARE_PREFIX(sqadd(z26.VnB(), z21.VnB(), z1.VnB()),
+                 "sqadd z26.b, z21.b, z1.b");
+  COMPARE_PREFIX(sqadd(z25.VnH(), z20.VnH(), z2.VnH()),
+                 "sqadd z25.h, z20.h, z2.h");
+  COMPARE_PREFIX(sqadd(z24.VnS(), z19.VnS(), z3.VnS()),
+                 "sqadd z24.s, z19.s, z3.s");
+  COMPARE_PREFIX(sqadd(z23.VnD(), z18.VnD(), z4.VnD()),
+                 "sqadd z23.d, z18.d, z4.d");
+  COMPARE_PREFIX(sqsub(z1.VnB(), z10.VnB(), z0.VnB()),
+                 "sqsub z1.b, z10.b, z0.b");
+  COMPARE_PREFIX(sqsub(z2.VnH(), z11.VnH(), z1.VnH()),
+                 "sqsub z2.h, z11.h, z1.h");
+  COMPARE_PREFIX(sqsub(z3.VnS(), z12.VnS(), z2.VnS()),
+                 "sqsub z3.s, z12.s, z2.s");
+  COMPARE_PREFIX(sqsub(z4.VnD(), z13.VnD(), z3.VnD()),
+                 "sqsub z4.d, z13.d, z3.d");
+  COMPARE_PREFIX(sub(z9.VnB(), z7.VnB(), z25.VnB()), "sub z9.b, z7.b, z25.b");
+  COMPARE_PREFIX(sub(z8.VnH(), z8.VnH(), z26.VnH()), "sub z8.h, z8.h, z26.h");
+  COMPARE_PREFIX(sub(z7.VnS(), z9.VnS(), z27.VnS()), "sub z7.s, z9.s, z27.s");
+  COMPARE_PREFIX(sub(z6.VnD(), z10.VnD(), z28.VnD()), "sub z6.d, z10.d, z28.d");
+  COMPARE_PREFIX(uqadd(z13.VnB(), z15.VnB(), z3.VnB()),
+                 "uqadd z13.b, z15.b, z3.b");
+  COMPARE_PREFIX(uqadd(z12.VnH(), z16.VnH(), z2.VnH()),
+                 "uqadd z12.h, z16.h, z2.h");
+  COMPARE_PREFIX(uqadd(z11.VnS(), z17.VnS(), z1.VnS()),
+                 "uqadd z11.s, z17.s, z1.s");
+  COMPARE_PREFIX(uqadd(z10.VnD(), z18.VnD(), z0.VnD()),
+                 "uqadd z10.d, z18.d, z0.d");
+  COMPARE_PREFIX(uqsub(z9.VnB(), z13.VnB(), z13.VnB()),
+                 "uqsub z9.b, z13.b, z13.b");
+  COMPARE_PREFIX(uqsub(z11.VnH(), z15.VnH(), z11.VnH()),
+                 "uqsub z11.h, z15.h, z11.h");
+  COMPARE_PREFIX(uqsub(z13.VnS(), z17.VnS(), z13.VnS()),
+                 "uqsub z13.s, z17.s, z13.s");
+  COMPARE_PREFIX(uqsub(z15.VnD(), z19.VnD(), z15.VnD()),
+                 "uqsub z15.d, z19.d, z15.d");
+
+  CLEANUP();
+}
+
+TEST(sve_int_binary_arithmetic_predicated) {
+  SETUP();
+
+  COMPARE_PREFIX(add(z22.VnB(), p4.Merging(), z22.VnB(), z20.VnB()),
+                 "add z22.b, p4/m, z22.b, z20.b");
+  COMPARE_PREFIX(add(z22.VnH(), p4.Merging(), z22.VnH(), z20.VnH()),
+                 "add z22.h, p4/m, z22.h, z20.h");
+  COMPARE_PREFIX(add(z22.VnS(), p4.Merging(), z22.VnS(), z20.VnS()),
+                 "add z22.s, p4/m, z22.s, z20.s");
+  COMPARE_PREFIX(add(z22.VnD(), p4.Merging(), z22.VnD(), z20.VnD()),
+                 "add z22.d, p4/m, z22.d, z20.d");
+  COMPARE_PREFIX(and_(z22.VnB(), p3.Merging(), z22.VnB(), z3.VnB()),
+                 "and z22.b, p3/m, z22.b, z3.b");
+  COMPARE_PREFIX(and_(z22.VnH(), p3.Merging(), z22.VnH(), z3.VnH()),
+                 "and z22.h, p3/m, z22.h, z3.h");
+  COMPARE_PREFIX(and_(z22.VnS(), p3.Merging(), z22.VnS(), z3.VnS()),
+                 "and z22.s, p3/m, z22.s, z3.s");
+  COMPARE_PREFIX(and_(z22.VnD(), p3.Merging(), z22.VnD(), z3.VnD()),
+                 "and z22.d, p3/m, z22.d, z3.d");
+  COMPARE_PREFIX(bic(z17.VnB(), p7.Merging(), z17.VnB(), z10.VnB()),
+                 "bic z17.b, p7/m, z17.b, z10.b");
+  COMPARE_PREFIX(bic(z17.VnH(), p7.Merging(), z17.VnH(), z10.VnH()),
+                 "bic z17.h, p7/m, z17.h, z10.h");
+  COMPARE_PREFIX(bic(z17.VnS(), p7.Merging(), z17.VnS(), z10.VnS()),
+                 "bic z17.s, p7/m, z17.s, z10.s");
+  COMPARE_PREFIX(bic(z17.VnD(), p7.Merging(), z17.VnD(), z10.VnD()),
+                 "bic z17.d, p7/m, z17.d, z10.d");
+  COMPARE_PREFIX(eor(z23.VnB(), p4.Merging(), z23.VnB(), z15.VnB()),
+                 "eor z23.b, p4/m, z23.b, z15.b");
+  COMPARE_PREFIX(eor(z23.VnH(), p4.Merging(), z23.VnH(), z15.VnH()),
+                 "eor z23.h, p4/m, z23.h, z15.h");
+  COMPARE_PREFIX(eor(z23.VnS(), p4.Merging(), z23.VnS(), z15.VnS()),
+                 "eor z23.s, p4/m, z23.s, z15.s");
+  COMPARE_PREFIX(eor(z23.VnD(), p4.Merging(), z23.VnD(), z15.VnD()),
+                 "eor z23.d, p4/m, z23.d, z15.d");
+  COMPARE_PREFIX(mul(z15.VnB(), p5.Merging(), z15.VnB(), z15.VnB()),
+                 "mul z15.b, p5/m, z15.b, z15.b");
+  COMPARE_PREFIX(mul(z15.VnH(), p5.Merging(), z15.VnH(), z15.VnH()),
+                 "mul z15.h, p5/m, z15.h, z15.h");
+  COMPARE_PREFIX(mul(z15.VnS(), p5.Merging(), z15.VnS(), z15.VnS()),
+                 "mul z15.s, p5/m, z15.s, z15.s");
+  COMPARE_PREFIX(mul(z15.VnD(), p5.Merging(), z15.VnD(), z15.VnD()),
+                 "mul z15.d, p5/m, z15.d, z15.d");
+  COMPARE_PREFIX(orr(z9.VnB(), p1.Merging(), z9.VnB(), z28.VnB()),
+                 "orr z9.b, p1/m, z9.b, z28.b");
+  COMPARE_PREFIX(orr(z9.VnH(), p1.Merging(), z9.VnH(), z28.VnH()),
+                 "orr z9.h, p1/m, z9.h, z28.h");
+  COMPARE_PREFIX(orr(z9.VnS(), p1.Merging(), z9.VnS(), z28.VnS()),
+                 "orr z9.s, p1/m, z9.s, z28.s");
+  COMPARE_PREFIX(orr(z9.VnD(), p1.Merging(), z9.VnD(), z28.VnD()),
+                 "orr z9.d, p1/m, z9.d, z28.d");
+  COMPARE_PREFIX(sabd(z11.VnB(), p6.Merging(), z11.VnB(), z31.VnB()),
+                 "sabd z11.b, p6/m, z11.b, z31.b");
+  COMPARE_PREFIX(sabd(z11.VnH(), p6.Merging(), z11.VnH(), z31.VnH()),
+                 "sabd z11.h, p6/m, z11.h, z31.h");
+  COMPARE_PREFIX(sabd(z11.VnS(), p6.Merging(), z11.VnS(), z31.VnS()),
+                 "sabd z11.s, p6/m, z11.s, z31.s");
+  COMPARE_PREFIX(sabd(z11.VnD(), p6.Merging(), z11.VnD(), z31.VnD()),
+                 "sabd z11.d, p6/m, z11.d, z31.d");
+  COMPARE_PREFIX(sdivr(z20.VnS(), p5.Merging(), z20.VnS(), z23.VnS()),
+                 "sdivr z20.s, p5/m, z20.s, z23.s");
+  COMPARE_PREFIX(sdiv(z15.VnD(), p6.Merging(), z15.VnD(), z8.VnD()),
+                 "sdiv z15.d, p6/m, z15.d, z8.d");
+  COMPARE_PREFIX(smax(z30.VnB(), p4.Merging(), z30.VnB(), z30.VnB()),
+                 "smax z30.b, p4/m, z30.b, z30.b");
+  COMPARE_PREFIX(smax(z30.VnH(), p4.Merging(), z30.VnH(), z30.VnH()),
+                 "smax z30.h, p4/m, z30.h, z30.h");
+  COMPARE_PREFIX(smax(z30.VnS(), p4.Merging(), z30.VnS(), z30.VnS()),
+                 "smax z30.s, p4/m, z30.s, z30.s");
+  COMPARE_PREFIX(smax(z30.VnD(), p4.Merging(), z30.VnD(), z30.VnD()),
+                 "smax z30.d, p4/m, z30.d, z30.d");
+  COMPARE_PREFIX(smin(z20.VnB(), p7.Merging(), z20.VnB(), z19.VnB()),
+                 "smin z20.b, p7/m, z20.b, z19.b");
+  COMPARE_PREFIX(smin(z20.VnH(), p7.Merging(), z20.VnH(), z19.VnH()),
+                 "smin z20.h, p7/m, z20.h, z19.h");
+  COMPARE_PREFIX(smin(z20.VnS(), p7.Merging(), z20.VnS(), z19.VnS()),
+                 "smin z20.s, p7/m, z20.s, z19.s");
+  COMPARE_PREFIX(smin(z20.VnD(), p7.Merging(), z20.VnD(), z19.VnD()),
+                 "smin z20.d, p7/m, z20.d, z19.d");
+  COMPARE_PREFIX(smulh(z23.VnB(), p0.Merging(), z23.VnB(), z3.VnB()),
+                 "smulh z23.b, p0/m, z23.b, z3.b");
+  COMPARE_PREFIX(smulh(z23.VnH(), p0.Merging(), z23.VnH(), z3.VnH()),
+                 "smulh z23.h, p0/m, z23.h, z3.h");
+  COMPARE_PREFIX(smulh(z23.VnS(), p0.Merging(), z23.VnS(), z3.VnS()),
+                 "smulh z23.s, p0/m, z23.s, z3.s");
+  COMPARE_PREFIX(smulh(z23.VnD(), p0.Merging(), z23.VnD(), z3.VnD()),
+                 "smulh z23.d, p0/m, z23.d, z3.d");
+  COMPARE_PREFIX(subr(z1.VnB(), p6.Merging(), z1.VnB(), z1.VnB()),
+                 "subr z1.b, p6/m, z1.b, z1.b");
+  COMPARE_PREFIX(subr(z1.VnH(), p6.Merging(), z1.VnH(), z1.VnH()),
+                 "subr z1.h, p6/m, z1.h, z1.h");
+  COMPARE_PREFIX(subr(z1.VnS(), p6.Merging(), z1.VnS(), z1.VnS()),
+                 "subr z1.s, p6/m, z1.s, z1.s");
+  COMPARE_PREFIX(subr(z1.VnD(), p6.Merging(), z1.VnD(), z1.VnD()),
+                 "subr z1.d, p6/m, z1.d, z1.d");
+  COMPARE_PREFIX(sub(z28.VnB(), p2.Merging(), z28.VnB(), z0.VnB()),
+                 "sub z28.b, p2/m, z28.b, z0.b");
+  COMPARE_PREFIX(sub(z28.VnH(), p2.Merging(), z28.VnH(), z0.VnH()),
+                 "sub z28.h, p2/m, z28.h, z0.h");
+  COMPARE_PREFIX(sub(z28.VnS(), p2.Merging(), z28.VnS(), z0.VnS()),
+                 "sub z28.s, p2/m, z28.s, z0.s");
+  COMPARE_PREFIX(sub(z28.VnD(), p2.Merging(), z28.VnD(), z0.VnD()),
+                 "sub z28.d, p2/m, z28.d, z0.d");
+  COMPARE_PREFIX(uabd(z14.VnB(), p6.Merging(), z14.VnB(), z22.VnB()),
+                 "uabd z14.b, p6/m, z14.b, z22.b");
+  COMPARE_PREFIX(uabd(z14.VnH(), p6.Merging(), z14.VnH(), z22.VnH()),
+                 "uabd z14.h, p6/m, z14.h, z22.h");
+  COMPARE_PREFIX(uabd(z14.VnS(), p6.Merging(), z14.VnS(), z22.VnS()),
+                 "uabd z14.s, p6/m, z14.s, z22.s");
+  COMPARE_PREFIX(uabd(z14.VnD(), p6.Merging(), z14.VnD(), z22.VnD()),
+                 "uabd z14.d, p6/m, z14.d, z22.d");
+  COMPARE_PREFIX(udivr(z27.VnS(), p5.Merging(), z27.VnS(), z31.VnS()),
+                 "udivr z27.s, p5/m, z27.s, z31.s");
+  COMPARE_PREFIX(udiv(z13.VnD(), p4.Merging(), z13.VnD(), z11.VnD()),
+                 "udiv z13.d, p4/m, z13.d, z11.d");
+  COMPARE_PREFIX(umax(z0.VnB(), p5.Merging(), z0.VnB(), z14.VnB()),
+                 "umax z0.b, p5/m, z0.b, z14.b");
+  COMPARE_PREFIX(umax(z0.VnH(), p5.Merging(), z0.VnH(), z14.VnH()),
+                 "umax z0.h, p5/m, z0.h, z14.h");
+  COMPARE_PREFIX(umax(z0.VnS(), p5.Merging(), z0.VnS(), z14.VnS()),
+                 "umax z0.s, p5/m, z0.s, z14.s");
+  COMPARE_PREFIX(umax(z0.VnD(), p5.Merging(), z0.VnD(), z14.VnD()),
+                 "umax z0.d, p5/m, z0.d, z14.d");
+  COMPARE_PREFIX(umin(z26.VnB(), p5.Merging(), z26.VnB(), z12.VnB()),
+                 "umin z26.b, p5/m, z26.b, z12.b");
+  COMPARE_PREFIX(umin(z26.VnH(), p5.Merging(), z26.VnH(), z12.VnH()),
+                 "umin z26.h, p5/m, z26.h, z12.h");
+  COMPARE_PREFIX(umin(z26.VnS(), p5.Merging(), z26.VnS(), z12.VnS()),
+                 "umin z26.s, p5/m, z26.s, z12.s");
+  COMPARE_PREFIX(umin(z26.VnD(), p5.Merging(), z26.VnD(), z12.VnD()),
+                 "umin z26.d, p5/m, z26.d, z12.d");
+  COMPARE_PREFIX(umulh(z12.VnB(), p2.Merging(), z12.VnB(), z17.VnB()),
+                 "umulh z12.b, p2/m, z12.b, z17.b");
+  COMPARE_PREFIX(umulh(z12.VnH(), p2.Merging(), z12.VnH(), z17.VnH()),
+                 "umulh z12.h, p2/m, z12.h, z17.h");
+  COMPARE_PREFIX(umulh(z12.VnS(), p2.Merging(), z12.VnS(), z17.VnS()),
+                 "umulh z12.s, p2/m, z12.s, z17.s");
+  COMPARE_PREFIX(umulh(z12.VnD(), p2.Merging(), z12.VnD(), z17.VnD()),
+                 "umulh z12.d, p2/m, z12.d, z17.d");
+  CLEANUP();
+}
+
+TEST(sve_int_binary_arithmetic_predicated_macro) {
+  SETUP();
+
+  COMPARE_MACRO(Add(z22.VnB(), p4.Merging(), z22.VnB(), z20.VnB()),
+                "add z22.b, p4/m, z22.b, z20.b");
+  COMPARE_MACRO(Add(z22.VnH(), p4.Merging(), z20.VnH(), z22.VnH()),
+                "add z22.h, p4/m, z22.h, z20.h");
+  COMPARE_MACRO(Add(z22.VnS(), p4.Merging(), z21.VnS(), z20.VnS()),
+                "movprfx z22.s, p4/m, z21.s\n"
+                "add z22.s, p4/m, z22.s, z20.s");
+
+  COMPARE_MACRO(And(z22.VnH(), p3.Merging(), z22.VnH(), z3.VnH()),
+                "and z22.h, p3/m, z22.h, z3.h");
+  COMPARE_MACRO(And(z22.VnS(), p3.Merging(), z3.VnS(), z22.VnS()),
+                "and z22.s, p3/m, z22.s, z3.s");
+  COMPARE_MACRO(And(z22.VnD(), p3.Merging(), z2.VnD(), z3.VnD()),
+                "movprfx z22.d, p3/m, z2.d\n"
+                "and z22.d, p3/m, z22.d, z3.d");
+
+  COMPARE_MACRO(Bic(z17.VnB(), p7.Merging(), z17.VnB(), z10.VnB()),
+                "bic z17.b, p7/m, z17.b, z10.b");
+  COMPARE_MACRO(Bic(z17.VnS(), p7.Merging(), z10.VnS(), z17.VnS()),
+                "bic z17.s, p7/m, z17.s, z10.s");
+  COMPARE_MACRO(Bic(z17.VnD(), p7.Merging(), z7.VnD(), z27.VnD()),
+                "movprfx z17.d, p7/m, z7.d\n"
+                "bic z17.d, p7/m, z17.d, z27.d");
+
+  COMPARE_MACRO(Eor(z23.VnB(), p4.Merging(), z23.VnB(), z15.VnB()),
+                "eor z23.b, p4/m, z23.b, z15.b");
+  COMPARE_MACRO(Eor(z23.VnH(), p4.Merging(), z23.VnH(), z15.VnH()),
+                "eor z23.h, p4/m, z23.h, z15.h");
+  COMPARE_MACRO(Eor(z23.VnD(), p4.Merging(), z18.VnD(), z15.VnD()),
+                "movprfx z23.d, p4/m, z18.d\n"
+                "eor z23.d, p4/m, z23.d, z15.d");
+
+  COMPARE_MACRO(Mul(z15.VnB(), p5.Merging(), z15.VnB(), z15.VnB()),
+                "mul z15.b, p5/m, z15.b, z15.b");
+  COMPARE_MACRO(Mul(z15.VnH(), p5.Merging(), z7.VnH(), z15.VnH()),
+                "mul z15.h, p5/m, z15.h, z7.h");
+  COMPARE_MACRO(Mul(z15.VnS(), p5.Merging(), z0.VnS(), z1.VnS()),
+                "movprfx z15.s, p5/m, z0.s\n"
+                "mul z15.s, p5/m, z15.s, z1.s");
+
+  COMPARE_MACRO(Orr(z9.VnH(), p1.Merging(), z9.VnH(), z28.VnH()),
+                "orr z9.h, p1/m, z9.h, z28.h");
+  COMPARE_MACRO(Orr(z9.VnS(), p1.Merging(), z9.VnS(), z28.VnS()),
+                "orr z9.s, p1/m, z9.s, z28.s");
+  COMPARE_MACRO(Orr(z9.VnD(), p1.Merging(), z6.VnD(), z7.VnD()),
+                "movprfx z9.d, p1/m, z6.d\n"
+                "orr z9.d, p1/m, z9.d, z7.d");
+
+  COMPARE_MACRO(Sabd(z11.VnB(), p6.Merging(), z11.VnB(), z31.VnB()),
+                "sabd z11.b, p6/m, z11.b, z31.b");
+  COMPARE_MACRO(Sabd(z11.VnH(), p6.Merging(), z31.VnH(), z11.VnH()),
+                "sabd z11.h, p6/m, z11.h, z31.h");
+  COMPARE_MACRO(Sabd(z11.VnS(), p6.Merging(), z21.VnS(), z31.VnS()),
+                "movprfx z11.s, p6/m, z21.s\n"
+                "sabd z11.s, p6/m, z11.s, z31.s");
+
+  COMPARE_MACRO(Sdiv(z20.VnS(), p5.Merging(), z23.VnS(), z20.VnS()),
+                "sdivr z20.s, p5/m, z20.s, z23.s");
+  COMPARE_MACRO(Sdiv(z15.VnD(), p6.Merging(), z30.VnD(), z8.VnD()),
+                "movprfx z15.d, p6/m, z30.d\n"
+                "sdiv z15.d, p6/m, z15.d, z8.d");
+
+  COMPARE_MACRO(Smax(z30.VnB(), p4.Merging(), z30.VnB(), z31.VnB()),
+                "smax z30.b, p4/m, z30.b, z31.b");
+  COMPARE_MACRO(Smax(z30.VnS(), p4.Merging(), z3.VnS(), z30.VnS()),
+                "smax z30.s, p4/m, z30.s, z3.s");
+  COMPARE_MACRO(Smax(z30.VnD(), p4.Merging(), z1.VnD(), z5.VnD()),
+                "movprfx z30.d, p4/m, z1.d\n"
+                "smax z30.d, p4/m, z30.d, z5.d");
+
+  COMPARE_MACRO(Smin(z20.VnH(), p7.Merging(), z20.VnH(), z19.VnH()),
+                "smin z20.h, p7/m, z20.h, z19.h");
+  COMPARE_MACRO(Smin(z20.VnS(), p7.Merging(), z19.VnS(), z20.VnS()),
+                "smin z20.s, p7/m, z20.s, z19.s");
+  COMPARE_MACRO(Smin(z20.VnD(), p7.Merging(), z14.VnD(), z15.VnD()),
+                "movprfx z20.d, p7/m, z14.d\n"
+                "smin z20.d, p7/m, z20.d, z15.d");
+
+  COMPARE_MACRO(Smulh(z23.VnB(), p0.Merging(), z23.VnB(), z3.VnB()),
+                "smulh z23.b, p0/m, z23.b, z3.b");
+  COMPARE_MACRO(Smulh(z23.VnH(), p0.Merging(), z13.VnH(), z23.VnH()),
+                "smulh z23.h, p0/m, z23.h, z13.h");
+  COMPARE_MACRO(Smulh(z23.VnD(), p0.Merging(), z30.VnD(), z31.VnD()),
+                "movprfx z23.d, p0/m, z30.d\n"
+                "smulh z23.d, p0/m, z23.d, z31.d");
+
+  COMPARE_MACRO(Sub(z28.VnB(), p2.Merging(), z28.VnB(), z0.VnB()),
+                "sub z28.b, p2/m, z28.b, z0.b");
+  COMPARE_MACRO(Sub(z28.VnH(), p2.Merging(), z14.VnH(), z28.VnH()),
+                "subr z28.h, p2/m, z28.h, z14.h");
+  COMPARE_MACRO(Sub(z28.VnS(), p2.Merging(), z7.VnS(), z13.VnS()),
+                "movprfx z28.s, p2/m, z7.s\n"
+                "sub z28.s, p2/m, z28.s, z13.s");
+
+  COMPARE_MACRO(Uabd(z14.VnH(), p6.Merging(), z14.VnH(), z22.VnH()),
+                "uabd z14.h, p6/m, z14.h, z22.h");
+  COMPARE_MACRO(Uabd(z14.VnS(), p6.Merging(), z14.VnS(), z22.VnS()),
+                "uabd z14.s, p6/m, z14.s, z22.s");
+  COMPARE_MACRO(Uabd(z14.VnD(), p6.Merging(), z13.VnD(), z22.VnD()),
+                "movprfx z14.d, p6/m, z13.d\n"
+                "uabd z14.d, p6/m, z14.d, z22.d");
+
+  COMPARE_MACRO(Udiv(z27.VnS(), p5.Merging(), z16.VnS(), z27.VnS()),
+                "udivr z27.s, p5/m, z27.s, z16.s");
+  COMPARE_MACRO(Udiv(z13.VnD(), p4.Merging(), z22.VnD(), z11.VnD()),
+                "movprfx z13.d, p4/m, z22.d\n"
+                "udiv z13.d, p4/m, z13.d, z11.d");
+
+  COMPARE_MACRO(Umax(z0.VnB(), p5.Merging(), z0.VnB(), z14.VnB()),
+                "umax z0.b, p5/m, z0.b, z14.b");
+  COMPARE_MACRO(Umax(z0.VnS(), p5.Merging(), z14.VnS(), z0.VnS()),
+                "umax z0.s, p5/m, z0.s, z14.s");
+  COMPARE_MACRO(Umax(z0.VnD(), p5.Merging(), z29.VnD(), z14.VnD()),
+                "movprfx z0.d, p5/m, z29.d\n"
+                "umax z0.d, p5/m, z0.d, z14.d");
+
+  COMPARE_MACRO(Umin(z26.VnB(), p5.Merging(), z26.VnB(), z12.VnB()),
+                "umin z26.b, p5/m, z26.b, z12.b");
+  COMPARE_MACRO(Umin(z26.VnH(), p5.Merging(), z27.VnH(), z26.VnH()),
+                "umin z26.h, p5/m, z26.h, z27.h");
+  COMPARE_MACRO(Umin(z26.VnD(), p5.Merging(), z13.VnD(), z12.VnD()),
+                "movprfx z26.d, p5/m, z13.d\n"
+                "umin z26.d, p5/m, z26.d, z12.d");
+
+  COMPARE_MACRO(Umulh(z12.VnB(), p2.Merging(), z12.VnB(), z17.VnB()),
+                "umulh z12.b, p2/m, z12.b, z17.b");
+  COMPARE_MACRO(Umulh(z12.VnH(), p2.Merging(), z0.VnH(), z12.VnH()),
+                "umulh z12.h, p2/m, z12.h, z0.h");
+  COMPARE_MACRO(Umulh(z12.VnS(), p2.Merging(), z25.VnS(), z17.VnS()),
+                "movprfx z12.s, p2/m, z25.s\n"
+                "umulh z12.s, p2/m, z12.s, z17.s");
+
+  CLEANUP();
+}
+
+TEST(sve_int_compare_scalars) {
+  SETUP();
+
+  COMPARE_PREFIX(ctermeq(w30, w26), "ctermeq w30, w26");
+  COMPARE_PREFIX(ctermne(x21, x18), "ctermne x21, x18");
+  COMPARE_PREFIX(whilele(p10.VnB(), x11, x6), "whilele p10.b, x11, x6");
+  COMPARE_PREFIX(whilele(p10.VnH(), w11, w6), "whilele p10.h, w11, w6");
+  COMPARE_PREFIX(whilele(p10.VnH(), x11, x6), "whilele p10.h, x11, x6");
+  COMPARE_PREFIX(whilele(p10.VnS(), w11, w6), "whilele p10.s, w11, w6");
+  COMPARE_PREFIX(whilele(p10.VnD(), x11, x6), "whilele p10.d, x11, x6");
+  COMPARE_PREFIX(whilelo(p4.VnB(), w3, w25), "whilelo p4.b, w3, w25");
+  COMPARE_PREFIX(whilelo(p4.VnH(), x3, x25), "whilelo p4.h, x3, x25");
+  COMPARE_PREFIX(whilelo(p4.VnS(), w3, w25), "whilelo p4.s, w3, w25");
+  COMPARE_PREFIX(whilelo(p4.VnD(), x3, x25), "whilelo p4.d, x3, x25");
+  COMPARE_PREFIX(whilels(p7.VnB(), w15, w15), "whilels p7.b, w15, w15");
+  COMPARE_PREFIX(whilels(p7.VnH(), x15, x15), "whilels p7.h, x15, x15");
+  COMPARE_PREFIX(whilels(p7.VnS(), w15, w15), "whilels p7.s, w15, w15");
+  COMPARE_PREFIX(whilels(p7.VnD(), x15, x15), "whilels p7.d, x15, x15");
+  COMPARE_PREFIX(whilelt(p14.VnB(), w11, w14), "whilelt p14.b, w11, w14");
+  COMPARE_PREFIX(whilelt(p14.VnH(), x11, x14), "whilelt p14.h, x11, x14");
+  COMPARE_PREFIX(whilelt(p14.VnS(), w11, w14), "whilelt p14.s, w11, w14");
+  COMPARE_PREFIX(whilelt(p14.VnD(), x11, x14), "whilelt p14.d, x11, x14");
+
+  CLEANUP();
+}
+
+TEST(sve_int_compare_signed_imm) {
+  SETUP();
+
+  COMPARE_PREFIX(cmpeq(p0.VnB(), p3.Zeroing(), z1.VnB(), 15),
+                 "cmpeq p0.b, p3/z, z1.b, #15");
+  COMPARE_PREFIX(cmpeq(p0.VnH(), p3.Zeroing(), z1.VnH(), 7),
+                 "cmpeq p0.h, p3/z, z1.h, #7");
+  COMPARE_PREFIX(cmpeq(p0.VnS(), p3.Zeroing(), z1.VnS(), -3),
+                 "cmpeq p0.s, p3/z, z1.s, #-3");
+  COMPARE_PREFIX(cmpeq(p0.VnD(), p3.Zeroing(), z1.VnD(), -14),
+                 "cmpeq p0.d, p3/z, z1.d, #-14");
+  COMPARE_PREFIX(cmpge(p9.VnB(), p6.Zeroing(), z12.VnB(), 14),
+                 "cmpge p9.b, p6/z, z12.b, #14");
+  COMPARE_PREFIX(cmpge(p9.VnH(), p6.Zeroing(), z12.VnH(), 6),
+                 "cmpge p9.h, p6/z, z12.h, #6");
+  COMPARE_PREFIX(cmpge(p9.VnS(), p6.Zeroing(), z12.VnS(), -4),
+                 "cmpge p9.s, p6/z, z12.s, #-4");
+  COMPARE_PREFIX(cmpge(p9.VnD(), p6.Zeroing(), z12.VnD(), -13),
+                 "cmpge p9.d, p6/z, z12.d, #-13");
+  COMPARE_PREFIX(cmpgt(p15.VnB(), p4.Zeroing(), z23.VnB(), 13),
+                 "cmpgt p15.b, p4/z, z23.b, #13");
+  COMPARE_PREFIX(cmpgt(p15.VnH(), p4.Zeroing(), z23.VnH(), 5),
+                 "cmpgt p15.h, p4/z, z23.h, #5");
+  COMPARE_PREFIX(cmpgt(p15.VnS(), p4.Zeroing(), z23.VnS(), -12),
+                 "cmpgt p15.s, p4/z, z23.s, #-12");
+  COMPARE_PREFIX(cmpgt(p15.VnD(), p4.Zeroing(), z23.VnD(), -5),
+                 "cmpgt p15.d, p4/z, z23.d, #-5");
+  COMPARE_PREFIX(cmple(p4.VnB(), p3.Zeroing(), z5.VnB(), 12),
+                 "cmple p4.b, p3/z, z5.b, #12");
+  COMPARE_PREFIX(cmple(p4.VnH(), p3.Zeroing(), z5.VnH(), 4),
+                 "cmple p4.h, p3/z, z5.h, #4");
+  COMPARE_PREFIX(cmple(p4.VnS(), p3.Zeroing(), z5.VnS(), -11),
+                 "cmple p4.s, p3/z, z5.s, #-11");
+  COMPARE_PREFIX(cmple(p4.VnD(), p3.Zeroing(), z5.VnD(), -6),
+                 "cmple p4.d, p3/z, z5.d, #-6");
+  COMPARE_PREFIX(cmplt(p3.VnB(), p7.Zeroing(), z15.VnB(), 11),
+                 "cmplt p3.b, p7/z, z15.b, #11");
+  COMPARE_PREFIX(cmplt(p3.VnH(), p7.Zeroing(), z15.VnH(), 3),
+                 "cmplt p3.h, p7/z, z15.h, #3");
+  COMPARE_PREFIX(cmplt(p3.VnS(), p7.Zeroing(), z15.VnS(), -10),
+                 "cmplt p3.s, p7/z, z15.s, #-10");
+  COMPARE_PREFIX(cmplt(p3.VnD(), p7.Zeroing(), z15.VnD(), -7),
+                 "cmplt p3.d, p7/z, z15.d, #-7");
+  COMPARE_PREFIX(cmpne(p13.VnB(), p5.Zeroing(), z20.VnB(), 10),
+                 "cmpne p13.b, p5/z, z20.b, #10");
+  COMPARE_PREFIX(cmpne(p13.VnH(), p5.Zeroing(), z20.VnH(), 2),
+                 "cmpne p13.h, p5/z, z20.h, #2");
+  COMPARE_PREFIX(cmpne(p13.VnS(), p5.Zeroing(), z20.VnS(), -9),
+                 "cmpne p13.s, p5/z, z20.s, #-9");
+  COMPARE_PREFIX(cmpne(p13.VnD(), p5.Zeroing(), z20.VnD(), -8),
+                 "cmpne p13.d, p5/z, z20.d, #-8");
+
+  CLEANUP();
+}
+
+TEST(sve_int_compare_unsigned_imm) {
+  SETUP();
+
+  COMPARE_PREFIX(cmphi(p8.VnB(), p6.Zeroing(), z1.VnB(), 127),
+                 "cmphi p8.b, p6/z, z1.b, #127");
+  COMPARE_PREFIX(cmphi(p8.VnH(), p6.Zeroing(), z1.VnH(), 126),
+                 "cmphi p8.h, p6/z, z1.h, #126");
+  COMPARE_PREFIX(cmphi(p8.VnS(), p6.Zeroing(), z1.VnS(), 99),
+                 "cmphi p8.s, p6/z, z1.s, #99");
+  COMPARE_PREFIX(cmphi(p8.VnD(), p6.Zeroing(), z1.VnD(), 78),
+                 "cmphi p8.d, p6/z, z1.d, #78");
+  COMPARE_PREFIX(cmphs(p11.VnB(), p2.Zeroing(), z8.VnB(), 67),
+                 "cmphs p11.b, p2/z, z8.b, #67");
+  COMPARE_PREFIX(cmphs(p11.VnH(), p2.Zeroing(), z8.VnH(), 63),
+                 "cmphs p11.h, p2/z, z8.h, #63");
+  COMPARE_PREFIX(cmphs(p11.VnS(), p2.Zeroing(), z8.VnS(), 51),
+                 "cmphs p11.s, p2/z, z8.s, #51");
+  COMPARE_PREFIX(cmphs(p11.VnD(), p2.Zeroing(), z8.VnD(), 40),
+                 "cmphs p11.d, p2/z, z8.d, #40");
+  COMPARE_PREFIX(cmplo(p9.VnB(), p4.Zeroing(), z4.VnB(), 32),
+                 "cmplo p9.b, p4/z, z4.b, #32");
+  COMPARE_PREFIX(cmplo(p9.VnH(), p4.Zeroing(), z4.VnH(), 22),
+                 "cmplo p9.h, p4/z, z4.h, #22");
+  COMPARE_PREFIX(cmplo(p9.VnS(), p4.Zeroing(), z4.VnS(), 15),
+                 "cmplo p9.s, p4/z, z4.s, #15");
+  COMPARE_PREFIX(cmplo(p9.VnD(), p4.Zeroing(), z4.VnD(), 11),
+                 "cmplo p9.d, p4/z, z4.d, #11");
+  COMPARE_PREFIX(cmpls(p14.VnB(), p5.Zeroing(), z9.VnB(), 7),
+                 "cmpls p14.b, p5/z, z9.b, #7");
+  COMPARE_PREFIX(cmpls(p14.VnH(), p5.Zeroing(), z9.VnH(), 4),
+                 "cmpls p14.h, p5/z, z9.h, #4");
+  COMPARE_PREFIX(cmpls(p14.VnS(), p5.Zeroing(), z9.VnS(), 3),
+                 "cmpls p14.s, p5/z, z9.s, #3");
+  COMPARE_PREFIX(cmpls(p14.VnD(), p5.Zeroing(), z9.VnD(), 1),
+                 "cmpls p14.d, p5/z, z9.d, #1");
+
+  CLEANUP();
+}
+
+TEST(sve_int_compare_vectors) {
+  SETUP();
+
+  COMPARE_PREFIX(cmpeq(p13.VnB(), p0.Zeroing(), z26.VnB(), z10.VnD()),
+                 "cmpeq p13.b, p0/z, z26.b, z10.d");
+  COMPARE_PREFIX(cmpeq(p13.VnH(), p0.Zeroing(), z26.VnH(), z10.VnD()),
+                 "cmpeq p13.h, p0/z, z26.h, z10.d");
+  COMPARE_PREFIX(cmpeq(p13.VnS(), p0.Zeroing(), z26.VnS(), z10.VnD()),
+                 "cmpeq p13.s, p0/z, z26.s, z10.d");
+  COMPARE_PREFIX(cmpeq(p14.VnB(), p3.Zeroing(), z18.VnB(), z15.VnB()),
+                 "cmpeq p14.b, p3/z, z18.b, z15.b");
+  COMPARE_PREFIX(cmpeq(p14.VnH(), p3.Zeroing(), z18.VnH(), z15.VnH()),
+                 "cmpeq p14.h, p3/z, z18.h, z15.h");
+  COMPARE_PREFIX(cmpeq(p14.VnS(), p3.Zeroing(), z18.VnS(), z15.VnS()),
+                 "cmpeq p14.s, p3/z, z18.s, z15.s");
+  COMPARE_PREFIX(cmpeq(p14.VnD(), p3.Zeroing(), z18.VnD(), z15.VnD()),
+                 "cmpeq p14.d, p3/z, z18.d, z15.d");
+  COMPARE_PREFIX(cmpge(p8.VnB(), p3.Zeroing(), z13.VnB(), z0.VnD()),
+                 "cmpge p8.b, p3/z, z13.b, z0.d");
+  COMPARE_PREFIX(cmpge(p8.VnH(), p3.Zeroing(), z13.VnH(), z0.VnD()),
+                 "cmpge p8.h, p3/z, z13.h, z0.d");
+  COMPARE_PREFIX(cmpge(p8.VnS(), p3.Zeroing(), z13.VnS(), z0.VnD()),
+                 "cmpge p8.s, p3/z, z13.s, z0.d");
+  COMPARE_PREFIX(cmpge(p3.VnB(), p4.Zeroing(), z6.VnB(), z1.VnB()),
+                 "cmpge p3.b, p4/z, z6.b, z1.b");
+  COMPARE_PREFIX(cmpge(p3.VnH(), p4.Zeroing(), z6.VnH(), z1.VnH()),
+                 "cmpge p3.h, p4/z, z6.h, z1.h");
+  COMPARE_PREFIX(cmpge(p3.VnS(), p4.Zeroing(), z6.VnS(), z1.VnS()),
+                 "cmpge p3.s, p4/z, z6.s, z1.s");
+  COMPARE_PREFIX(cmpge(p3.VnD(), p4.Zeroing(), z6.VnD(), z1.VnD()),
+                 "cmpge p3.d, p4/z, z6.d, z1.d");
+  COMPARE_PREFIX(cmpgt(p4.VnB(), p2.Zeroing(), z24.VnB(), z1.VnD()),
+                 "cmpgt p4.b, p2/z, z24.b, z1.d");
+  COMPARE_PREFIX(cmpgt(p4.VnH(), p2.Zeroing(), z24.VnH(), z1.VnD()),
+                 "cmpgt p4.h, p2/z, z24.h, z1.d");
+  COMPARE_PREFIX(cmpgt(p4.VnS(), p2.Zeroing(), z24.VnS(), z1.VnD()),
+                 "cmpgt p4.s, p2/z, z24.s, z1.d");
+  COMPARE_PREFIX(cmpgt(p10.VnB(), p3.Zeroing(), z23.VnB(), z19.VnB()),
+                 "cmpgt p10.b, p3/z, z23.b, z19.b");
+  COMPARE_PREFIX(cmpgt(p10.VnH(), p3.Zeroing(), z23.VnH(), z19.VnH()),
+                 "cmpgt p10.h, p3/z, z23.h, z19.h");
+  COMPARE_PREFIX(cmpgt(p10.VnS(), p3.Zeroing(), z23.VnS(), z19.VnS()),
+                 "cmpgt p10.s, p3/z, z23.s, z19.s");
+  COMPARE_PREFIX(cmpgt(p10.VnD(), p3.Zeroing(), z23.VnD(), z19.VnD()),
+                 "cmpgt p10.d, p3/z, z23.d, z19.d");
+  COMPARE_PREFIX(cmphi(p10.VnB(), p6.Zeroing(), z6.VnB(), z11.VnD()),
+                 "cmphi p10.b, p6/z, z6.b, z11.d");
+  COMPARE_PREFIX(cmphi(p10.VnH(), p6.Zeroing(), z6.VnH(), z11.VnD()),
+                 "cmphi p10.h, p6/z, z6.h, z11.d");
+  COMPARE_PREFIX(cmphi(p10.VnS(), p6.Zeroing(), z6.VnS(), z11.VnD()),
+                 "cmphi p10.s, p6/z, z6.s, z11.d");
+  COMPARE_PREFIX(cmphi(p1.VnB(), p0.Zeroing(), z4.VnB(), z2.VnB()),
+                 "cmphi p1.b, p0/z, z4.b, z2.b");
+  COMPARE_PREFIX(cmphi(p1.VnH(), p0.Zeroing(), z4.VnH(), z2.VnH()),
+                 "cmphi p1.h, p0/z, z4.h, z2.h");
+  COMPARE_PREFIX(cmphi(p1.VnS(), p0.Zeroing(), z4.VnS(), z2.VnS()),
+                 "cmphi p1.s, p0/z, z4.s, z2.s");
+  COMPARE_PREFIX(cmphi(p1.VnD(), p0.Zeroing(), z4.VnD(), z2.VnD()),
+                 "cmphi p1.d, p0/z, z4.d, z2.d");
+  COMPARE_PREFIX(cmphs(p10.VnB(), p5.Zeroing(), z22.VnB(), z5.VnD()),
+                 "cmphs p10.b, p5/z, z22.b, z5.d");
+  COMPARE_PREFIX(cmphs(p10.VnH(), p5.Zeroing(), z22.VnH(), z5.VnD()),
+                 "cmphs p10.h, p5/z, z22.h, z5.d");
+  COMPARE_PREFIX(cmphs(p10.VnS(), p5.Zeroing(), z22.VnS(), z5.VnD()),
+                 "cmphs p10.s, p5/z, z22.s, z5.d");
+  COMPARE_PREFIX(cmphs(p12.VnB(), p6.Zeroing(), z20.VnB(), z24.VnB()),
+                 "cmphs p12.b, p6/z, z20.b, z24.b");
+  COMPARE_PREFIX(cmphs(p12.VnH(), p6.Zeroing(), z20.VnH(), z24.VnH()),
+                 "cmphs p12.h, p6/z, z20.h, z24.h");
+  COMPARE_PREFIX(cmphs(p12.VnS(), p6.Zeroing(), z20.VnS(), z24.VnS()),
+                 "cmphs p12.s, p6/z, z20.s, z24.s");
+  COMPARE_PREFIX(cmphs(p12.VnD(), p6.Zeroing(), z20.VnD(), z24.VnD()),
+                 "cmphs p12.d, p6/z, z20.d, z24.d");
+  COMPARE_PREFIX(cmple(p11.VnB(), p2.Zeroing(), z18.VnB(), z0.VnD()),
+                 "cmple p11.b, p2/z, z18.b, z0.d");
+  COMPARE_PREFIX(cmple(p11.VnH(), p2.Zeroing(), z18.VnH(), z0.VnD()),
+                 "cmple p11.h, p2/z, z18.h, z0.d");
+  COMPARE_PREFIX(cmple(p11.VnS(), p2.Zeroing(), z18.VnS(), z0.VnD()),
+                 "cmple p11.s, p2/z, z18.s, z0.d");
+  COMPARE_PREFIX(cmplo(p12.VnB(), p6.Zeroing(), z21.VnB(), z10.VnD()),
+                 "cmplo p12.b, p6/z, z21.b, z10.d");
+  COMPARE_PREFIX(cmplo(p12.VnH(), p6.Zeroing(), z21.VnH(), z10.VnD()),
+                 "cmplo p12.h, p6/z, z21.h, z10.d");
+  COMPARE_PREFIX(cmplo(p12.VnS(), p6.Zeroing(), z21.VnS(), z10.VnD()),
+                 "cmplo p12.s, p6/z, z21.s, z10.d");
+  COMPARE_PREFIX(cmpls(p8.VnB(), p4.Zeroing(), z9.VnB(), z15.VnD()),
+                 "cmpls p8.b, p4/z, z9.b, z15.d");
+  COMPARE_PREFIX(cmpls(p8.VnH(), p4.Zeroing(), z9.VnH(), z15.VnD()),
+                 "cmpls p8.h, p4/z, z9.h, z15.d");
+  COMPARE_PREFIX(cmpls(p8.VnS(), p4.Zeroing(), z9.VnS(), z15.VnD()),
+                 "cmpls p8.s, p4/z, z9.s, z15.d");
+  COMPARE_PREFIX(cmplt(p6.VnB(), p6.Zeroing(), z4.VnB(), z8.VnD()),
+                 "cmplt p6.b, p6/z, z4.b, z8.d");
+  COMPARE_PREFIX(cmplt(p6.VnH(), p6.Zeroing(), z4.VnH(), z8.VnD()),
+                 "cmplt p6.h, p6/z, z4.h, z8.d");
+  COMPARE_PREFIX(cmplt(p6.VnS(), p6.Zeroing(), z4.VnS(), z8.VnD()),
+                 "cmplt p6.s, p6/z, z4.s, z8.d");
+  COMPARE_PREFIX(cmpne(p1.VnB(), p6.Zeroing(), z31.VnB(), z16.VnD()),
+                 "cmpne p1.b, p6/z, z31.b, z16.d");
+  COMPARE_PREFIX(cmpne(p1.VnH(), p6.Zeroing(), z31.VnH(), z16.VnD()),
+                 "cmpne p1.h, p6/z, z31.h, z16.d");
+  COMPARE_PREFIX(cmpne(p1.VnS(), p6.Zeroing(), z31.VnS(), z16.VnD()),
+                 "cmpne p1.s, p6/z, z31.s, z16.d");
+  COMPARE_PREFIX(cmpne(p11.VnB(), p1.Zeroing(), z3.VnB(), z24.VnB()),
+                 "cmpne p11.b, p1/z, z3.b, z24.b");
+  COMPARE_PREFIX(cmpne(p11.VnH(), p1.Zeroing(), z3.VnH(), z24.VnH()),
+                 "cmpne p11.h, p1/z, z3.h, z24.h");
+  COMPARE_PREFIX(cmpne(p11.VnS(), p1.Zeroing(), z3.VnS(), z24.VnS()),
+                 "cmpne p11.s, p1/z, z3.s, z24.s");
+  COMPARE_PREFIX(cmpne(p11.VnD(), p1.Zeroing(), z3.VnD(), z24.VnD()),
+                 "cmpne p11.d, p1/z, z3.d, z24.d");
+  COMPARE_PREFIX(cmpls(p8.VnB(), p4.Zeroing(), z9.VnB(), z15.VnB()),
+                 "cmphs p8.b, p4/z, z15.b, z9.b");
+  COMPARE_PREFIX(cmpls(p8.VnH(), p4.Zeroing(), z9.VnH(), z15.VnH()),
+                 "cmphs p8.h, p4/z, z15.h, z9.h");
+  COMPARE_PREFIX(cmpls(p8.VnS(), p4.Zeroing(), z9.VnS(), z15.VnS()),
+                 "cmphs p8.s, p4/z, z15.s, z9.s");
+  COMPARE_PREFIX(cmpls(p8.VnD(), p4.Zeroing(), z9.VnD(), z15.VnD()),
+                 "cmphs p8.d, p4/z, z15.d, z9.d");
+  COMPARE_PREFIX(cmplo(p10.VnB(), p3.Zeroing(), z14.VnB(), z20.VnB()),
+                 "cmphi p10.b, p3/z, z20.b, z14.b");
+  COMPARE_PREFIX(cmplo(p10.VnH(), p3.Zeroing(), z14.VnH(), z20.VnH()),
+                 "cmphi p10.h, p3/z, z20.h, z14.h");
+  COMPARE_PREFIX(cmplo(p10.VnS(), p3.Zeroing(), z14.VnS(), z20.VnS()),
+                 "cmphi p10.s, p3/z, z20.s, z14.s");
+  COMPARE_PREFIX(cmplo(p10.VnD(), p3.Zeroing(), z14.VnD(), z20.VnD()),
+                 "cmphi p10.d, p3/z, z20.d, z14.d");
+  COMPARE_PREFIX(cmple(p12.VnB(), p2.Zeroing(), z19.VnB(), z25.VnB()),
+                 "cmpge p12.b, p2/z, z25.b, z19.b");
+  COMPARE_PREFIX(cmple(p12.VnH(), p2.Zeroing(), z19.VnH(), z25.VnH()),
+                 "cmpge p12.h, p2/z, z25.h, z19.h");
+  COMPARE_PREFIX(cmple(p12.VnS(), p2.Zeroing(), z19.VnS(), z25.VnS()),
+                 "cmpge p12.s, p2/z, z25.s, z19.s");
+  COMPARE_PREFIX(cmple(p12.VnD(), p2.Zeroing(), z19.VnD(), z25.VnD()),
+                 "cmpge p12.d, p2/z, z25.d, z19.d");
+  COMPARE_PREFIX(cmplt(p14.VnB(), p1.Zeroing(), z24.VnB(), z30.VnB()),
+                 "cmpgt p14.b, p1/z, z30.b, z24.b");
+  COMPARE_PREFIX(cmplt(p14.VnH(), p1.Zeroing(), z24.VnH(), z30.VnH()),
+                 "cmpgt p14.h, p1/z, z30.h, z24.h");
+  COMPARE_PREFIX(cmplt(p14.VnS(), p1.Zeroing(), z24.VnS(), z30.VnS()),
+                 "cmpgt p14.s, p1/z, z30.s, z24.s");
+  COMPARE_PREFIX(cmplt(p14.VnD(), p1.Zeroing(), z24.VnD(), z30.VnD()),
+                 "cmpgt p14.d, p1/z, z30.d, z24.d");
+
+  CLEANUP();
+}
+
+TEST(sve_int_misc_unpredicated) {
+  SETUP();
+
+  COMPARE_PREFIX(fexpa(z5.VnH(), z9.VnH()), "fexpa z5.h, z9.h");
+  COMPARE_PREFIX(fexpa(z5.VnS(), z9.VnS()), "fexpa z5.s, z9.s");
+  COMPARE_PREFIX(fexpa(z5.VnD(), z9.VnD()), "fexpa z5.d, z9.d");
+  COMPARE_PREFIX(ftssel(z17.VnH(), z24.VnH(), z14.VnH()),
+                 "ftssel z17.h, z24.h, z14.h");
+  COMPARE_PREFIX(ftssel(z17.VnS(), z24.VnS(), z14.VnS()),
+                 "ftssel z17.s, z24.s, z14.s");
+  COMPARE_PREFIX(ftssel(z17.VnD(), z24.VnD(), z14.VnD()),
+                 "ftssel z17.d, z24.d, z14.d");
+  COMPARE_PREFIX(movprfx(z24, z1), "movprfx z24, z1");
+
+  CLEANUP();
+}
+
+TEST(sve_int_mul_add_predicated) {
+  SETUP();
+
+  COMPARE_PREFIX(mad(z29.VnB(), p6.Merging(), z22.VnB(), z21.VnB()),
+                 "mad z29.b, p6/m, z22.b, z21.b");
+  COMPARE_PREFIX(mad(z29.VnH(), p6.Merging(), z22.VnH(), z21.VnH()),
+                 "mad z29.h, p6/m, z22.h, z21.h");
+  COMPARE_PREFIX(mad(z29.VnS(), p6.Merging(), z22.VnS(), z21.VnS()),
+                 "mad z29.s, p6/m, z22.s, z21.s");
+  COMPARE_PREFIX(mad(z29.VnD(), p6.Merging(), z22.VnD(), z21.VnD()),
+                 "mad z29.d, p6/m, z22.d, z21.d");
+  COMPARE_PREFIX(mla(z23.VnB(), p1.Merging(), z21.VnB(), z23.VnB()),
+                 "mla z23.b, p1/m, z21.b, z23.b");
+  COMPARE_PREFIX(mla(z23.VnH(), p1.Merging(), z21.VnH(), z23.VnH()),
+                 "mla z23.h, p1/m, z21.h, z23.h");
+  COMPARE_PREFIX(mla(z23.VnS(), p1.Merging(), z21.VnS(), z23.VnS()),
+                 "mla z23.s, p1/m, z21.s, z23.s");
+  COMPARE_PREFIX(mla(z23.VnD(), p1.Merging(), z21.VnD(), z23.VnD()),
+                 "mla z23.d, p1/m, z21.d, z23.d");
+  COMPARE_PREFIX(mls(z4.VnB(), p6.Merging(), z17.VnB(), z28.VnB()),
+                 "mls z4.b, p6/m, z17.b, z28.b");
+  COMPARE_PREFIX(mls(z4.VnH(), p6.Merging(), z17.VnH(), z28.VnH()),
+                 "mls z4.h, p6/m, z17.h, z28.h");
+  COMPARE_PREFIX(mls(z4.VnS(), p6.Merging(), z17.VnS(), z28.VnS()),
+                 "mls z4.s, p6/m, z17.s, z28.s");
+  COMPARE_PREFIX(mls(z4.VnD(), p6.Merging(), z17.VnD(), z28.VnD()),
+                 "mls z4.d, p6/m, z17.d, z28.d");
+  COMPARE_PREFIX(msb(z27.VnB(), p7.Merging(), z29.VnB(), z1.VnB()),
+                 "msb z27.b, p7/m, z29.b, z1.b");
+  COMPARE_PREFIX(msb(z27.VnH(), p7.Merging(), z29.VnH(), z1.VnH()),
+                 "msb z27.h, p7/m, z29.h, z1.h");
+  COMPARE_PREFIX(msb(z27.VnS(), p7.Merging(), z29.VnS(), z1.VnS()),
+                 "msb z27.s, p7/m, z29.s, z1.s");
+  COMPARE_PREFIX(msb(z27.VnD(), p7.Merging(), z29.VnD(), z1.VnD()),
+                 "msb z27.d, p7/m, z29.d, z1.d");
+
+  CLEANUP();
+}
+
+TEST(sve_int_mul_add_predicated_macro) {
+  SETUP();
+
+  COMPARE_MACRO(Mla(z0.VnB(), p1.Merging(), z0.VnB(), z2.VnB(), z4.VnB()),
+                "mla z0.b, p1/m, z2.b, z4.b");
+  COMPARE_MACRO(Mla(z3.VnH(), p2.Merging(), z4.VnH(), z3.VnH(), z5.VnH()),
+                "mad z3.h, p2/m, z5.h, z4.h");
+  COMPARE_MACRO(Mla(z4.VnS(), p3.Merging(), z5.VnS(), z6.VnS(), z4.VnS()),
+                "mad z4.s, p3/m, z6.s, z5.s");
+  COMPARE_MACRO(Mla(z5.VnD(), p4.Merging(), z6.VnD(), z7.VnD(), z8.VnD()),
+                "movprfx z5.d, p4/m, z6.d\n"
+                "mla z5.d, p4/m, z7.d, z8.d");
+
+  COMPARE_MACRO(Mls(z0.VnD(), p1.Merging(), z0.VnD(), z2.VnD(), z4.VnD()),
+                "mls z0.d, p1/m, z2.d, z4.d");
+  COMPARE_MACRO(Mls(z3.VnS(), p2.Merging(), z4.VnS(), z3.VnS(), z5.VnS()),
+                "msb z3.s, p2/m, z5.s, z4.s");
+  COMPARE_MACRO(Mls(z4.VnH(), p3.Merging(), z5.VnH(), z6.VnH(), z4.VnH()),
+                "msb z4.h, p3/m, z6.h, z5.h");
+  COMPARE_MACRO(Mls(z5.VnB(), p4.Merging(), z6.VnB(), z7.VnB(), z8.VnB()),
+                "movprfx z5.b, p4/m, z6.b\n"
+                "mls z5.b, p4/m, z7.b, z8.b");
+
+  CLEANUP();
+}
+
+TEST(sve_int_mul_add_unpredicated) {
+  SETUP();
+
+  COMPARE_PREFIX(sdot(z13.VnS(), z12.VnB(), z12.VnB()),
+                 "sdot z13.s, z12.b, z12.b");
+  COMPARE_PREFIX(sdot(z18.VnD(), z27.VnH(), z22.VnH()),
+                 "sdot z18.d, z27.h, z22.h");
+  COMPARE_PREFIX(udot(z23.VnS(), z22.VnB(), z11.VnB()),
+                 "udot z23.s, z22.b, z11.b");
+  COMPARE_PREFIX(udot(z21.VnD(), z27.VnH(), z27.VnH()),
+                 "udot z21.d, z27.h, z27.h");
+
+  CLEANUP();
+}
+
+TEST(sve_int_mul_add_unpredicated_macro) {
+  SETUP();
+
+  COMPARE_MACRO(Sdot(z0.VnS(), z0.VnS(), z2.VnB(), z4.VnB()),
+                "sdot z0.s, z2.b, z4.b");
+  COMPARE_MACRO(Sdot(z3.VnD(), z4.VnD(), z3.VnH(), z5.VnH()),
+                "movprfx z31, z4\n"
+                "sdot z31.d, z3.h, z5.h\n"
+                "mov z3.d, z31.d");
+  COMPARE_MACRO(Sdot(z4.VnS(), z5.VnS(), z6.VnB(), z4.VnB()),
+                "movprfx z31, z5\n"
+                "sdot z31.s, z6.b, z4.b\n"
+                "mov z4.d, z31.d");
+  COMPARE_MACRO(Sdot(z6.VnD(), z7.VnD(), z8.VnH(), z9.VnH()),
+                "movprfx z6, z7\n"
+                "sdot z6.d, z8.h, z9.h");
+  COMPARE_MACRO(Sdot(z5.VnD(), z5.VnD(), z5.VnH(), z5.VnH()),
+                "sdot z5.d, z5.h, z5.h");
+
+  COMPARE_MACRO(Udot(z0.VnD(), z0.VnD(), z2.VnH(), z4.VnH()),
+                "udot z0.d, z2.h, z4.h");
+  COMPARE_MACRO(Udot(z3.VnS(), z4.VnS(), z3.VnB(), z5.VnB()),
+                "movprfx z31, z4\n"
+                "udot z31.s, z3.b, z5.b\n"
+                "mov z3.d, z31.d");
+  COMPARE_MACRO(Udot(z4.VnD(), z5.VnD(), z6.VnH(), z4.VnH()),
+                "movprfx z31, z5\n"
+                "udot z31.d, z6.h, z4.h\n"
+                "mov z4.d, z31.d");
+  COMPARE_MACRO(Udot(z6.VnS(), z7.VnS(), z8.VnB(), z9.VnB()),
+                "movprfx z6, z7\n"
+                "udot z6.s, z8.b, z9.b");
+  COMPARE_MACRO(Udot(z5.VnS(), z5.VnS(), z5.VnB(), z5.VnB()),
+                "udot z5.s, z5.b, z5.b");
+  CLEANUP();
+}
+
+TEST(sve_int_reduction) {
+  SETUP();
+
+  COMPARE_PREFIX(andv(b15, p1, z4.VnB()), "andv b15, p1, z4.b");
+  COMPARE_PREFIX(andv(h14, p2, z3.VnH()), "andv h14, p2, z3.h");
+  COMPARE_PREFIX(andv(s13, p3, z2.VnS()), "andv s13, p3, z2.s");
+  COMPARE_PREFIX(andv(d12, p4, z1.VnD()), "andv d12, p4, z1.d");
+  COMPARE_PREFIX(eorv(b12, p0, z30.VnB()), "eorv b12, p0, z30.b");
+  COMPARE_PREFIX(eorv(h11, p1, z29.VnH()), "eorv h11, p1, z29.h");
+  COMPARE_PREFIX(eorv(s10, p2, z28.VnS()), "eorv s10, p2, z28.s");
+  COMPARE_PREFIX(eorv(d9, p3, z27.VnD()), "eorv d9, p3, z27.d");
+  COMPARE_PREFIX(movprfx(z30.VnB(), p2.Zeroing(), z23.VnB()),
+                 "movprfx z30.b, p2/z, z23.b");
+  COMPARE_PREFIX(movprfx(z10.VnH(), p0.Merging(), z10.VnH()),
+                 "movprfx z10.h, p0/m, z10.h");
+  COMPARE_PREFIX(movprfx(z0.VnS(), p2.Zeroing(), z23.VnS()),
+                 "movprfx z0.s, p2/z, z23.s");
+  COMPARE_PREFIX(movprfx(z31.VnD(), p7.Merging(), z23.VnD()),
+                 "movprfx z31.d, p7/m, z23.d");
+  COMPARE_PREFIX(orv(b4, p0, z16.VnB()), "orv b4, p0, z16.b");
+  COMPARE_PREFIX(orv(h6, p2, z18.VnH()), "orv h6, p2, z18.h");
+  COMPARE_PREFIX(orv(s8, p4, z20.VnS()), "orv s8, p4, z20.s");
+  COMPARE_PREFIX(orv(d10, p6, z22.VnD()), "orv d10, p6, z22.d");
+  COMPARE_PREFIX(saddv(d20, p1, z12.VnB()), "saddv d20, p1, z12.b");
+  COMPARE_PREFIX(saddv(d22, p3, z15.VnH()), "saddv d22, p3, z15.h");
+  COMPARE_PREFIX(saddv(d24, p5, z18.VnS()), "saddv d24, p5, z18.s");
+  COMPARE_PREFIX(smaxv(b9, p3, z1.VnB()), "smaxv b9, p3, z1.b");
+  COMPARE_PREFIX(smaxv(h19, p2, z1.VnH()), "smaxv h19, p2, z1.h");
+  COMPARE_PREFIX(smaxv(s29, p1, z1.VnS()), "smaxv s29, p1, z1.s");
+  COMPARE_PREFIX(smaxv(d9, p0, z1.VnD()), "smaxv d9, p0, z1.d");
+  COMPARE_PREFIX(sminv(b8, p3, z14.VnB()), "sminv b8, p3, z14.b");
+  COMPARE_PREFIX(sminv(h18, p2, z4.VnH()), "sminv h18, p2, z4.h");
+  COMPARE_PREFIX(sminv(s28, p1, z4.VnS()), "sminv s28, p1, z4.s");
+  COMPARE_PREFIX(sminv(d8, p0, z24.VnD()), "sminv d8, p0, z24.d");
+  COMPARE_PREFIX(uaddv(d13, p0, z15.VnB()), "uaddv d13, p0, z15.b");
+  COMPARE_PREFIX(uaddv(d15, p2, z20.VnH()), "uaddv d15, p2, z20.h");
+  COMPARE_PREFIX(uaddv(d17, p4, z25.VnS()), "uaddv d17, p4, z25.s");
+  COMPARE_PREFIX(uaddv(d19, p6, z30.VnD()), "uaddv d19, p6, z30.d");
+  COMPARE_PREFIX(umaxv(b28, p3, z4.VnB()), "umaxv b28, p3, z4.b");
+  COMPARE_PREFIX(umaxv(h18, p6, z2.VnH()), "umaxv h18, p6, z2.h");
+  COMPARE_PREFIX(umaxv(s18, p4, z29.VnS()), "umaxv s18, p4, z29.s");
+  COMPARE_PREFIX(umaxv(d28, p1, z24.VnD()), "umaxv d28, p1, z24.d");
+  COMPARE_PREFIX(uminv(b16, p3, z0.VnB()), "uminv b16, p3, z0.b");
+  COMPARE_PREFIX(uminv(h16, p2, z3.VnH()), "uminv h16, p2, z3.h");
+  COMPARE_PREFIX(uminv(s16, p1, z5.VnS()), "uminv s16, p1, z5.s");
+  COMPARE_PREFIX(uminv(d16, p7, z7.VnD()), "uminv d16, p7, z7.d");
+
+  CLEANUP();
+}
+
+TEST(sve_int_unary_arithmetic_predicated) {
+  SETUP();
+
+  COMPARE_PREFIX(abs(z5.VnB(), p5.Merging(), z31.VnB()),
+                 "abs z5.b, p5/m, z31.b");
+  COMPARE_PREFIX(abs(z29.VnH(), p5.Merging(), z17.VnH()),
+                 "abs z29.h, p5/m, z17.h");
+  COMPARE_PREFIX(abs(z6.VnS(), p4.Merging(), z24.VnS()),
+                 "abs z6.s, p4/m, z24.s");
+  COMPARE_PREFIX(abs(z19.VnD(), p3.Merging(), z25.VnD()),
+                 "abs z19.d, p3/m, z25.d");
+  COMPARE_PREFIX(cls(z4.VnB(), p0.Merging(), z20.VnB()),
+                 "cls z4.b, p0/m, z20.b");
+  COMPARE_PREFIX(cls(z11.VnH(), p0.Merging(), z26.VnH()),
+                 "cls z11.h, p0/m, z26.h");
+  COMPARE_PREFIX(cls(z10.VnS(), p1.Merging(), z10.VnS()),
+                 "cls z10.s, p1/m, z10.s");
+  COMPARE_PREFIX(cls(z5.VnD(), p1.Merging(), z4.VnD()), "cls z5.d, p1/m, z4.d");
+  COMPARE_PREFIX(clz(z18.VnB(), p3.Merging(), z1.VnB()),
+                 "clz z18.b, p3/m, z1.b");
+  COMPARE_PREFIX(clz(z13.VnH(), p4.Merging(), z18.VnH()),
+                 "clz z13.h, p4/m, z18.h");
+  COMPARE_PREFIX(clz(z15.VnS(), p4.Merging(), z24.VnS()),
+                 "clz z15.s, p4/m, z24.s");
+  COMPARE_PREFIX(clz(z29.VnD(), p2.Merging(), z22.VnD()),
+                 "clz z29.d, p2/m, z22.d");
+  COMPARE_PREFIX(cnot(z16.VnB(), p6.Merging(), z20.VnB()),
+                 "cnot z16.b, p6/m, z20.b");
+  COMPARE_PREFIX(cnot(z10.VnH(), p5.Merging(), z12.VnH()),
+                 "cnot z10.h, p5/m, z12.h");
+  COMPARE_PREFIX(cnot(z8.VnS(), p5.Merging(), z21.VnS()),
+                 "cnot z8.s, p5/m, z21.s");
+  COMPARE_PREFIX(cnot(z3.VnD(), p3.Merging(), z18.VnD()),
+                 "cnot z3.d, p3/m, z18.d");
+  COMPARE_PREFIX(cnt(z29.VnB(), p3.Merging(), z7.VnB()),
+                 "cnt z29.b, p3/m, z7.b");
+  COMPARE_PREFIX(cnt(z3.VnH(), p6.Merging(), z31.VnH()),
+                 "cnt z3.h, p6/m, z31.h");
+  COMPARE_PREFIX(cnt(z2.VnS(), p4.Merging(), z16.VnS()),
+                 "cnt z2.s, p4/m, z16.s");
+  COMPARE_PREFIX(cnt(z0.VnD(), p0.Merging(), z24.VnD()),
+                 "cnt z0.d, p0/m, z24.d");
+  COMPARE_PREFIX(fabs(z17.VnH(), p7.Merging(), z15.VnH()),
+                 "fabs z17.h, p7/m, z15.h");
+  COMPARE_PREFIX(fabs(z18.VnS(), p0.Merging(), z29.VnS()),
+                 "fabs z18.s, p0/m, z29.s");
+  COMPARE_PREFIX(fabs(z17.VnD(), p1.Merging(), z9.VnD()),
+                 "fabs z17.d, p1/m, z9.d");
+  COMPARE_PREFIX(fneg(z25.VnH(), p1.Merging(), z28.VnH()),
+                 "fneg z25.h, p1/m, z28.h");
+  COMPARE_PREFIX(fneg(z5.VnS(), p1.Merging(), z25.VnS()),
+                 "fneg z5.s, p1/m, z25.s");
+  COMPARE_PREFIX(fneg(z6.VnD(), p1.Merging(), z17.VnD()),
+                 "fneg z6.d, p1/m, z17.d");
+  COMPARE_PREFIX(neg(z25.VnB(), p4.Merging(), z8.VnB()),
+                 "neg z25.b, p4/m, z8.b");
+  COMPARE_PREFIX(neg(z30.VnH(), p3.Merging(), z23.VnH()),
+                 "neg z30.h, p3/m, z23.h");
+  COMPARE_PREFIX(neg(z7.VnS(), p2.Merging(), z26.VnS()),
+                 "neg z7.s, p2/m, z26.s");
+  COMPARE_PREFIX(neg(z21.VnD(), p3.Merging(), z5.VnD()),
+                 "neg z21.d, p3/m, z5.d");
+  COMPARE_PREFIX(not_(z24.VnB(), p1.Merging(), z27.VnB()),
+                 "not z24.b, p1/m, z27.b");
+  COMPARE_PREFIX(not_(z31.VnH(), p6.Merging(), z19.VnH()),
+                 "not z31.h, p6/m, z19.h");
+  COMPARE_PREFIX(not_(z18.VnS(), p5.Merging(), z13.VnS()),
+                 "not z18.s, p5/m, z13.s");
+  COMPARE_PREFIX(not_(z12.VnD(), p2.Merging(), z28.VnD()),
+                 "not z12.d, p2/m, z28.d");
+  COMPARE_PREFIX(sxtb(z19.VnH(), p7.Merging(), z3.VnH()),
+                 "sxtb z19.h, p7/m, z3.h");
+  COMPARE_PREFIX(sxtb(z3.VnS(), p1.Merging(), z17.VnS()),
+                 "sxtb z3.s, p1/m, z17.s");
+  COMPARE_PREFIX(sxtb(z27.VnD(), p0.Merging(), z12.VnD()),
+                 "sxtb z27.d, p0/m, z12.d");
+  COMPARE_PREFIX(sxth(z6.VnS(), p1.Merging(), z17.VnS()),
+                 "sxth z6.s, p1/m, z17.s");
+  COMPARE_PREFIX(sxth(z8.VnD(), p6.Merging(), z2.VnD()),
+                 "sxth z8.d, p6/m, z2.d");
+  COMPARE_PREFIX(sxtw(z13.VnD(), p3.Merging(), z27.VnD()),
+                 "sxtw z13.d, p3/m, z27.d");
+  COMPARE_PREFIX(uxtb(z23.VnH(), p3.Merging(), z21.VnH()),
+                 "uxtb z23.h, p3/m, z21.h");
+  COMPARE_PREFIX(uxtb(z0.VnS(), p2.Merging(), z13.VnS()),
+                 "uxtb z0.s, p2/m, z13.s");
+  COMPARE_PREFIX(uxtb(z1.VnD(), p3.Merging(), z13.VnD()),
+                 "uxtb z1.d, p3/m, z13.d");
+  COMPARE_PREFIX(uxth(z27.VnS(), p0.Merging(), z29.VnS()),
+                 "uxth z27.s, p0/m, z29.s");
+  COMPARE_PREFIX(uxth(z22.VnD(), p4.Merging(), z20.VnD()),
+                 "uxth z22.d, p4/m, z20.d");
+  COMPARE_PREFIX(uxtw(z14.VnD(), p1.Merging(), z13.VnD()),
+                 "uxtw z14.d, p1/m, z13.d");
+
+  CLEANUP();
+}
+
+TEST(sve_neg_macro) {
+  SETUP();
+
+  COMPARE_MACRO(Neg(z0.VnB(), z0.VnB()), "subr z0.b, z0.b, #0");
+  COMPARE_MACRO(Neg(z1.VnH(), z2.VnH()),
+                "movprfx z1, z2\n"
+                "subr z1.h, z1.h, #0");
+  COMPARE_MACRO(Neg(z29.VnS(), z29.VnS()), "subr z29.s, z29.s, #0");
+  COMPARE_MACRO(Neg(z30.VnD(), z31.VnD()),
+                "movprfx z30, z31\n"
+                "subr z30.d, z30.d, #0");
+
+  CLEANUP();
+}
+
+TEST(sve_cpy_fcpy_imm) {
+  SETUP();
+
+  COMPARE_PREFIX(cpy(z25.VnB(), p13.Zeroing(), -1), "mov z25.b, p13/z, #-1");
+  COMPARE_PREFIX(cpy(z25.VnB(), p13.Merging(), -1), "mov z25.b, p13/m, #-1");
+  COMPARE_PREFIX(cpy(z25.VnH(), p13.Merging(), 127), "mov z25.h, p13/m, #127");
+  COMPARE_PREFIX(cpy(z25.VnS(), p13.Merging(), 10752),
+                 "mov z25.s, p13/m, #42, lsl #8");
+  COMPARE_PREFIX(cpy(z25.VnD(), p13.Merging(), -10752),
+                 "mov z25.d, p13/m, #-42, lsl #8");
+  COMPARE_PREFIX(mov(z25.VnD(), p13.Merging(), -10752),
+                 "mov z25.d, p13/m, #-42, lsl #8");
+
+  COMPARE_PREFIX(fcpy(z20.VnH(), p11.Merging(), 29.0),
+                 "fmov z20.h, p11/m, #0x3d (29.0000)");
+  COMPARE_PREFIX(fmov(z20.VnS(), p11.Merging(), -31.0),
+                 "fmov z20.s, p11/m, #0xbf (-31.0000)");
+  COMPARE_PREFIX(fcpy(z20.VnD(), p11.Merging(), 1.0),
+                 "fmov z20.d, p11/m, #0x70 (1.0000)");
+
+  CLEANUP();
+}
+
+TEST(sve_fmov_zero) {
+  SETUP();
+
+  // Predicated `fmov` is an alias for either `fcpy` or `cpy`.
+  COMPARE_PREFIX(fmov(z13.VnS(), p0.Merging(), 1.0),
+                 "fmov z13.s, p0/m, #0x70 (1.0000)");
+  COMPARE_PREFIX(fmov(z13.VnS(), p0.Merging(), 0.0), "mov z13.s, p0/m, #0");
+  COMPARE_MACRO(Fmov(z13.VnD(), p0.Merging(), 1.0),
+                "fmov z13.d, p0/m, #0x70 (1.0000)");
+  COMPARE_MACRO(Fmov(z13.VnD(), p0.Merging(), 0.0), "mov z13.d, p0/m, #0");
+
+  // Unpredicated `fmov` is an alias for either `fdup` or `dup`.
+  COMPARE_PREFIX(fmov(z13.VnS(), 1.0), "fmov z13.s, #0x70 (1.0000)");
+  COMPARE_PREFIX(fmov(z13.VnS(), 0.0), "mov z13.s, #0");
+  COMPARE_MACRO(Fmov(z13.VnD(), 1.0), "fmov z13.d, #0x70 (1.0000)");
+  COMPARE_MACRO(Fmov(z13.VnD(), 0.0), "mov z13.d, #0");
+
+  // -0.0 cannot be encoded by this alias, but is handled by the MacroAssembler.
+  COMPARE_MACRO(Fmov(z13.VnD(), p0.Merging(), -0.0),
+                "mov x16, #0x8000000000000000\n"
+                "mov z13.d, p0/m, x16");
+  COMPARE_MACRO(Fmov(z13.VnD(), -0.0), "mov z13.d, #0x8000000000000000");
+
+  CLEANUP();
+}
+
+TEST(sve_int_wide_imm_unpredicated) {
+  SETUP();
+
+  COMPARE_PREFIX(add(z12.VnB(), z12.VnB(), 0), "add z12.b, z12.b, #0");
+  COMPARE_PREFIX(add(z13.VnH(), z13.VnH(), 255), "add z13.h, z13.h, #255");
+  COMPARE_PREFIX(add(z14.VnS(), z14.VnS(), 256),
+                 "add z14.s, z14.s, #1, lsl #8");
+  COMPARE_PREFIX(add(z15.VnD(), z15.VnD(), 255 * 256),
+                 "add z15.d, z15.d, #255, lsl #8");
+
+  COMPARE_PREFIX(dup(z6.VnB(), -128), "mov z6.b, #-128");
+  COMPARE_PREFIX(dup(z7.VnH(), 127), "mov z7.h, #127");
+  COMPARE_PREFIX(dup(z8.VnS(), -128 * 256), "mov z8.s, #-128, lsl #8");
+  COMPARE_PREFIX(dup(z9.VnD(), 127 * 256), "mov z9.d, #127, lsl #8");
+  COMPARE_PREFIX(mov(z8.VnS(), -128 * 256, -1), "mov z8.s, #-128, lsl #8");
+  COMPARE_PREFIX(mov(z9.VnD(), 127 * 256, -1), "mov z9.d, #127, lsl #8");
+
+  COMPARE_PREFIX(sqadd(z7.VnB(), z7.VnB(), 124), "sqadd z7.b, z7.b, #124");
+  COMPARE_PREFIX(sqadd(z8.VnH(), z8.VnH(), 131), "sqadd z8.h, z8.h, #131");
+  COMPARE_PREFIX(sqadd(z9.VnS(), z9.VnS(), 252 * 256),
+                 "sqadd z9.s, z9.s, #252, lsl #8");
+  COMPARE_PREFIX(sqadd(z10.VnD(), z10.VnD(), 20 * 256),
+                 "sqadd z10.d, z10.d, #20, lsl #8");
+
+  COMPARE_PREFIX(sqsub(z31.VnB(), z31.VnB(), 132), "sqsub z31.b, z31.b, #132");
+  COMPARE_PREFIX(sqsub(z30.VnH(), z30.VnH(), 251), "sqsub z30.h, z30.h, #251");
+  COMPARE_PREFIX(sqsub(z29.VnS(), z29.VnS(), 21 * 256),
+                 "sqsub z29.s, z29.s, #21, lsl #8");
+  COMPARE_PREFIX(sqsub(z28.VnD(), z28.VnD(), 123 * 256),
+                 "sqsub z28.d, z28.d, #123, lsl #8");
+
+  COMPARE_PREFIX(subr(z20.VnB(), z20.VnB(), 250), "subr z20.b, z20.b, #250");
+  COMPARE_PREFIX(subr(z21.VnH(), z21.VnH(), 22), "subr z21.h, z21.h, #22");
+  COMPARE_PREFIX(subr(z22.VnS(), z22.VnS(), 122 * 256),
+                 "subr z22.s, z22.s, #122, lsl #8");
+  COMPARE_PREFIX(subr(z23.VnD(), z23.VnD(), 133 * 256),
+                 "subr z23.d, z23.d, #133, lsl #8");
+
+  COMPARE_PREFIX(sub(z18.VnB(), z18.VnB(), 23), "sub z18.b, z18.b, #23");
+  COMPARE_PREFIX(sub(z19.VnH(), z19.VnH(), 121), "sub z19.h, z19.h, #121");
+  COMPARE_PREFIX(sub(z20.VnS(), z20.VnS(), 134 * 256),
+                 "sub z20.s, z20.s, #134, lsl #8");
+  COMPARE_PREFIX(sub(z21.VnD(), z21.VnD(), 249 * 256),
+                 "sub z21.d, z21.d, #249, lsl #8");
+
+  COMPARE_PREFIX(uqadd(z21.VnB(), z21.VnB(), 246), "uqadd z21.b, z21.b, #246");
+  COMPARE_PREFIX(uqadd(z22.VnH(), z22.VnH(), 26), "uqadd z22.h, z22.h, #26");
+  COMPARE_PREFIX(uqadd(z23.VnS(), z23.VnS(), 118 * 256),
+                 "uqadd z23.s, z23.s, #118, lsl #8");
+  COMPARE_PREFIX(uqadd(z24.VnD(), z24.VnD(), 137 * 256),
+                 "uqadd z24.d, z24.d, #137, lsl #8");
+
+  COMPARE_PREFIX(uqsub(z10.VnB(), z10.VnB(), 27), "uqsub z10.b, z10.b, #27");
+  COMPARE_PREFIX(uqsub(z11.VnH(), z11.VnH(), 117), "uqsub z11.h, z11.h, #117");
+  COMPARE_PREFIX(uqsub(z12.VnS(), z12.VnS(), 138 * 256),
+                 "uqsub z12.s, z12.s, #138, lsl #8");
+  COMPARE_PREFIX(uqsub(z13.VnD(), z13.VnD(), 245 * 256),
+                 "uqsub z13.d, z13.d, #245, lsl #8");
+
+  COMPARE_PREFIX(fdup(z26.VnH(), Float16(-5.0f)),
+                 "fmov z26.h, #0x94 (-5.0000)");
+  COMPARE_PREFIX(fdup(z27.VnS(), -13.0f), "fmov z27.s, #0xaa (-13.0000)");
+  COMPARE_PREFIX(fdup(z28.VnD(), 1.0f), "fmov z28.d, #0x70 (1.0000)");
+  COMPARE_PREFIX(fmov(z28.VnD(), 1.0f), "fmov z28.d, #0x70 (1.0000)");
+
+  COMPARE_PREFIX(mul(z15.VnB(), z15.VnB(), -128), "mul z15.b, z15.b, #-128");
+  COMPARE_PREFIX(mul(z16.VnH(), z16.VnH(), -1), "mul z16.h, z16.h, #-1");
+  COMPARE_PREFIX(mul(z17.VnS(), z17.VnS(), 17), "mul z17.s, z17.s, #17");
+  COMPARE_PREFIX(mul(z18.VnD(), z18.VnD(), 127), "mul z18.d, z18.d, #127");
+
+  COMPARE_PREFIX(smax(z7.VnB(), z7.VnB(), -2), "smax z7.b, z7.b, #-2");
+  COMPARE_PREFIX(smax(z8.VnH(), z8.VnH(), 18), "smax z8.h, z8.h, #18");
+  COMPARE_PREFIX(smax(z9.VnS(), z9.VnS(), 126), "smax z9.s, z9.s, #126");
+  COMPARE_PREFIX(smax(z10.VnD(), z10.VnD(), -127), "smax z10.d, z10.d, #-127");
+
+  COMPARE_PREFIX(smin(z5.VnB(), z5.VnB(), 19), "smin z5.b, z5.b, #19");
+  COMPARE_PREFIX(smin(z6.VnH(), z6.VnH(), 125), "smin z6.h, z6.h, #125");
+  COMPARE_PREFIX(smin(z7.VnS(), z7.VnS(), -126), "smin z7.s, z7.s, #-126");
+  COMPARE_PREFIX(smin(z8.VnD(), z8.VnD(), -3), "smin z8.d, z8.d, #-3");
+
+  COMPARE_PREFIX(umax(z15.VnB(), z15.VnB(), 120), "umax z15.b, z15.b, #120");
+  COMPARE_PREFIX(umax(z16.VnH(), z16.VnH(), 135), "umax z16.h, z16.h, #135");
+  COMPARE_PREFIX(umax(z17.VnS(), z17.VnS(), 248), "umax z17.s, z17.s, #248");
+  COMPARE_PREFIX(umax(z18.VnD(), z18.VnD(), 24), "umax z18.d, z18.d, #24");
+
+  COMPARE_PREFIX(umin(z22.VnB(), z22.VnB(), 136), "umin z22.b, z22.b, #136");
+  COMPARE_PREFIX(umin(z23.VnH(), z23.VnH(), 247), "umin z23.h, z23.h, #247");
+  COMPARE_PREFIX(umin(z24.VnS(), z24.VnS(), 25), "umin z24.s, z24.s, #25");
+  COMPARE_PREFIX(umin(z25.VnD(), z25.VnD(), 119), "umin z25.d, z25.d, #119");
+
+  CLEANUP();
+}
+
+TEST(sve_add_sub_imm_macro) {
+  SETUP();
+
+  // The MacroAssembler automatically generates movprfx where necessary.
+  COMPARE_MACRO(Add(z12.VnB(), z13.VnB(), 0),
+                "movprfx z12, z13\n"
+                "add z12.b, z12.b, #0");
+  COMPARE_MACRO(Sub(z20.VnB(), 250, z2.VnB()),
+                "movprfx z20, z2\n"
+                "subr z20.b, z20.b, #250");
+  COMPARE_MACRO(Sub(z19.VnH(), z4.VnH(), 121),
+                "movprfx z19, z4\n"
+                "sub z19.h, z19.h, #121");
+
+  // Add and Sub can make use of two's complement equivalences.
+  COMPARE_MACRO(Add(z13.VnH(), z13.VnH(), 0xffff), "sub z13.h, z13.h, #1");
+  COMPARE_MACRO(Add(z15.VnD(), z15.VnD(), 0xffffffffffffffd6),
+                "sub z15.d, z15.d, #42");
+  COMPARE_MACRO(Add(z16.VnH(), z16.VnH(), 0xff00),
+                "add z16.h, z16.h, #255, lsl #8");
+  COMPARE_MACRO(Sub(z17.VnH(), z17.VnH(), 0xfffe), "add z17.h, z17.h, #2");
+  COMPARE_MACRO(Sub(z14.VnB(), z14.VnB(), 0x80), "sub z14.b, z14.b, #128");
+
+  // The MacroAssembler automatically generates dup if an immediate isn't
+  // encodable.
+  COMPARE_MACRO(Add(z15.VnD(), z20.VnD(), 1234567890),
+                "mov x16, #0x2d2\n"
+                "movk x16, #0x4996, lsl #16\n"
+                "mov z31.d, x16\n"
+                "add z15.d, z20.d, z31.d");
+  COMPARE_MACRO(Sub(z22.VnS(), 256 * 256, z2.VnS()),
+                "mov z31.s, #0x10000\n"
+                "sub z22.s, z31.s, z2.s");
+  COMPARE_MACRO(Sub(z21.VnD(), z11.VnD(), 111111111111),
+                "mov x16, #0x1c7\n"
+                "movk x16, #0xdebd, lsl #16\n"
+                "movk x16, #0x19, lsl #32\n"
+                "mov z31.d, x16\n"
+                "sub z21.d, z11.d, z31.d");
+
+  CLEANUP();
+}
+
+TEST(sve_uqadd_uqsub_imm_macro) {
+  SETUP();
+
+  // The MacroAssembler automatically generates movprfx where necessary.
+  COMPARE_MACRO(Uqadd(z21.VnB(), z14.VnB(), 246),
+                "movprfx z21, z14\n"
+                "uqadd z21.b, z21.b, #246");
+  COMPARE_MACRO(Uqsub(z10.VnB(), z27.VnB(), 27),
+                "movprfx z10, z27\n"
+                "uqsub z10.b, z10.b, #27");
+  COMPARE_MACRO(Uqadd(z1.VnS(), z2.VnS(), 42 * 256),
+                "movprfx z1, z2\n"
+                "uqadd z1.s, z1.s, #42, lsl #8");
+
+  COMPARE_MACRO(Uqsub(z3.VnB(), z3.VnB(), 0xff), "uqsub z3.b, z3.b, #255");
+  COMPARE_MACRO(Uqadd(z8.VnS(), z8.VnS(), 0xff00),
+                "uqadd z8.s, z8.s, #255, lsl #8");
+
+  CLEANUP();
+}
+
+TEST(sve_sqadd_sqsub_imm_macro) {
+  SETUP();
+
+  // The MacroAssembler automatically generates movprfx where necessary.
+  COMPARE_MACRO(Sqadd(z21.VnB(), z14.VnB(), 123),
+                "movprfx z21, z14\n"
+                "sqadd z21.b, z21.b, #123");
+  COMPARE_MACRO(Sqsub(z10.VnB(), z27.VnB(), 27),
+                "movprfx z10, z27\n"
+                "sqsub z10.b, z10.b, #27");
+  COMPARE_MACRO(Sqadd(z22.VnS(), z15.VnS(), 256),
+                "movprfx z22, z15\n"
+                "sqadd z22.s, z22.s, #1, lsl #8");
+
+  COMPARE_MACRO(Sqsub(z3.VnB(), z3.VnB(), 0xff), "sqsub z3.b, z3.b, #255");
+  COMPARE_MACRO(Sqadd(z4.VnH(), z4.VnH(), 0xff00),
+                "sqadd z4.h, z4.h, #255, lsl #8");
+
+  CLEANUP();
+}
+
+TEST(sve_int_wide_imm_unpredicated_macro) {
+  SETUP();
+
+  // The MacroAssembler automatically generates movprfx where it can.
+  COMPARE_MACRO(Mul(z1.VnD(), z18.VnD(), 127),
+                "movprfx z1, z18\n"
+                "mul z1.d, z1.d, #127");
+  COMPARE_MACRO(Smax(z3.VnS(), z9.VnS(), 126),
+                "movprfx z3, z9\n"
+                "smax z3.s, z3.s, #126");
+  COMPARE_MACRO(Smin(z26.VnH(), z6.VnH(), 125),
+                "movprfx z26, z6\n"
+                "smin z26.h, z26.h, #125");
+  COMPARE_MACRO(Umax(z25.VnB(), z15.VnB(), 120),
+                "movprfx z25, z15\n"
+                "umax z25.b, z25.b, #120");
+  COMPARE_MACRO(Umin(z13.VnD(), z25.VnD(), 119),
+                "movprfx z13, z25\n"
+                "umin z13.d, z13.d, #119");
+  COMPARE_MACRO(Dup(z8.VnS(), -7654321),
+                "mov w16, #0x344f\n"
+                "movk w16, #0xff8b, lsl #16\n"
+                "mov z8.s, w16");
+
+  // The MacroAssembler automatically generates dup if an immediate isn't
+  // encodable, when it is out-of-range for example.
+  COMPARE_MACRO(Dup(z9.VnD(), 0x80000000), "mov z9.d, #0x80000000");
+  COMPARE_MACRO(Mov(z9.VnD(), 0x80000000), "mov z9.d, #0x80000000");
+  COMPARE_MACRO(Fdup(z26.VnH(), Float16(0.0)), "mov z26.h, #0");
+  COMPARE_MACRO(Fdup(z26.VnH(), Float16(0.0)), "mov z26.h, #0");
+  COMPARE_MACRO(Fdup(z27.VnS(), 255.0f),
+                "mov w16, #0x437f0000\n"
+                "mov z27.s, w16");
+  COMPARE_MACRO(Fdup(z28.VnD(), 12.3456),
+                "mov x16, #0xfec5\n"
+                "movk x16, #0x7bb2, lsl #16\n"
+                "movk x16, #0xb0f2, lsl #32\n"
+                "movk x16, #0x4028, lsl #48\n"
+                "mov z28.d, x16");
+  COMPARE_MACRO(Fmov(z26.VnH(), Float16(0.0)), "mov z26.h, #0");
+  COMPARE_MACRO(Fmov(z26.VnH(), Float16(0.0)), "mov z26.h, #0");
+  COMPARE_MACRO(Fmov(z27.VnS(), 255.0f),
+                "mov w16, #0x437f0000\n"
+                "mov z27.s, w16");
+  COMPARE_MACRO(Fmov(z28.VnD(), 12.3456),
+                "mov x16, #0xfec5\n"
+                "movk x16, #0x7bb2, lsl #16\n"
+                "movk x16, #0xb0f2, lsl #32\n"
+                "movk x16, #0x4028, lsl #48\n"
+                "mov z28.d, x16");
+
+  // Only predicated version of instruction is supported for unencodable
+  // immediate.
+  {
+    UseScratchRegisterScope temps(&masm);
+    temps.Include(p7, p15);
+    COMPARE_MACRO(Mul(z18.VnD(), z18.VnD(), -1270000000),
+                  "ptrue p7.d\n"
+                  "mov x16, #0xffffffffffff5680\n"
+                  "movk x16, #0xb44d, lsl #16\n"
+                  "mov z31.d, x16\n"
+                  "mul z18.d, p7/m, z18.d, z31.d");
+    COMPARE_MACRO(Smax(z9.VnS(), z11.VnS(), -0x70000001),
+                  "ptrue p7.s\n"
+                  "mov z9.s, #0x8fffffff\n"
+                  "smax z9.s, p7/m, z9.s, z11.s");
+    COMPARE_MACRO(Smin(z6.VnH(), z6.VnH(), -0x7eef),
+                  "ptrue p7.h\n"
+                  "mov w16, #0xffff8111\n"
+                  "mov z31.h, w16\n"
+                  "smin z6.h, p7/m, z6.h, z31.h");
+    COMPARE_MACRO(Umax(z15.VnH(), z7.VnH(), 0xfeee),
+                  "ptrue p7.h\n"
+                  "mov w16, #0xfeee\n"
+                  "mov z15.h, w16\n"
+                  "umax z15.h, p7/m, z15.h, z7.h");
+    COMPARE_MACRO(Umin(z25.VnD(), z25.VnD(), 123123123),
+                  "ptrue p7.d\n"
+                  "mov x16, #0xb5b3\n"
+                  "movk x16, #0x756, lsl #16\n"
+                  "mov z31.d, x16\n"
+                  "umin z25.d, p7/m, z25.d, z31.d");
+  }
+}
+
+TEST(sve_mem_32bit_gather_vector_plus_immediate_macro) {
+  SETUP();
+
+  // Simple cases.
+  COMPARE_MACRO(Ld1b(z4.VnS(), p4.Zeroing(), SVEMemOperand(z12.VnS(), 31)),
+                "ld1b {z4.s}, p4/z, [z12.s, #31]");
+  COMPARE_MACRO(Ld1h(z10.VnS(), p6.Zeroing(), SVEMemOperand(z4.VnS(), 10)),
+                "ld1h {z10.s}, p6/z, [z4.s, #10]");
+  COMPARE_MACRO(Ld1w(z16.VnS(), p0.Zeroing(), SVEMemOperand(z26.VnS(), 124)),
+                "ld1w {z16.s}, p0/z, [z26.s, #124]");
+  COMPARE_MACRO(Ld1sb(z9.VnS(), p3.Zeroing(), SVEMemOperand(z22.VnS())),
+                "ld1sb {z9.s}, p3/z, [z22.s]");
+  COMPARE_MACRO(Ld1sh(z22.VnS(), p1.Zeroing(), SVEMemOperand(z9.VnS(), 62)),
+                "ld1sh {z22.s}, p1/z, [z9.s, #62]");
+  COMPARE_MACRO(Ldff1b(z17.VnS(), p2.Zeroing(), SVEMemOperand(z29.VnS(), 0)),
+                "ldff1b {z17.s}, p2/z, [z29.s]");
+  COMPARE_MACRO(Ldff1h(z16.VnS(), p3.Zeroing(), SVEMemOperand(z15.VnS())),
+                "ldff1h {z16.s}, p3/z, [z15.s]");
+  COMPARE_MACRO(Ldff1w(z7.VnS(), p3.Zeroing(), SVEMemOperand(z20.VnS(), 4)),
+                "ldff1w {z7.s}, p3/z, [z20.s, #4]");
+  COMPARE_MACRO(Ldff1sb(z7.VnS(), p1.Zeroing(), SVEMemOperand(z10.VnS(), 21)),
+                "ldff1sb {z7.s}, p1/z, [z10.s, #21]");
+  COMPARE_MACRO(Ldff1sh(z0.VnS(), p1.Zeroing(), SVEMemOperand(z23.VnS(), 42)),
+                "ldff1sh {z0.s}, p1/z, [z23.s, #42]");
+
+  // Unencodable cases use a scalar-plus-vector form.
+  COMPARE_MACRO(Ld1b(z17.VnS(), p2.Zeroing(), SVEMemOperand(z11.VnS(), 32)),
+                "mov x16, #0x20\n"
+                "ld1b {z17.s}, p2/z, [x16, z11.s, uxtw]");
+  COMPARE_MACRO(Ld1h(z11.VnS(), p1.Zeroing(), SVEMemOperand(z8.VnS(), -2)),
+                "mov x16, #0xfffffffffffffffe\n"
+                "ld1h {z11.s}, p1/z, [x16, z8.s, uxtw]");
+  COMPARE_MACRO(Ld1w(z5.VnS(), p6.Zeroing(), SVEMemOperand(z9.VnS(), 42)),
+                "mov x16, #0x2a\n"
+                "ld1w {z5.s}, p6/z, [x16, z9.s, uxtw]");
+  COMPARE_MACRO(Ld1sb(z28.VnS(), p5.Zeroing(), SVEMemOperand(z12.VnS(), -1)),
+                "mov x16, #0xffffffffffffffff\n"
+                "ld1sb {z28.s}, p5/z, [x16, z12.s, uxtw]");
+  COMPARE_MACRO(Ld1sh(z30.VnS(), p5.Zeroing(), SVEMemOperand(z21.VnS(), 64)),
+                "mov x16, #0x40\n"
+                "ld1sh {z30.s}, p5/z, [x16, z21.s, uxtw]");
+  COMPARE_MACRO(Ldff1b(z19.VnS(), p6.Zeroing(), SVEMemOperand(z24.VnS(), 32)),
+                "mov x16, #0x20\n"
+                "ldff1b {z19.s}, p6/z, [x16, z24.s, uxtw]");
+  COMPARE_MACRO(Ldff1h(z5.VnS(), p1.Zeroing(), SVEMemOperand(z24.VnS(), -2)),
+                "mov x16, #0xfffffffffffffffe\n"
+                "ldff1h {z5.s}, p1/z, [x16, z24.s, uxtw]");
+  COMPARE_MACRO(Ldff1w(z17.VnS(), p6.Zeroing(), SVEMemOperand(z18.VnS(), 42)),
+                "mov x16, #0x2a\n"
+                "ldff1w {z17.s}, p6/z, [x16, z18.s, uxtw]");
+  COMPARE_MACRO(Ldff1sb(z31.VnS(), p5.Zeroing(), SVEMemOperand(z21.VnS(), -1)),
+                "mov x16, #0xffffffffffffffff\n"
+                "ldff1sb {z31.s}, p5/z, [x16, z21.s, uxtw]");
+  COMPARE_MACRO(Ldff1sh(z6.VnS(), p5.Zeroing(), SVEMemOperand(z22.VnS(), 64)),
+                "mov x16, #0x40\n"
+                "ldff1sh {z6.s}, p5/z, [x16, z22.s, uxtw]");
+
+  CLEANUP();
+}
+
+TEST(sve_mem_32bit_gather_and_unsized_contiguous) {
+  SETUP();
+
+  // 32-bit gather load in scalar-plus-vector vform with unscaled offset.
+  COMPARE_PREFIX(ld1b(z9.VnS(),
+                      p5.Zeroing(),
+                      SVEMemOperand(x2, z1.VnS(), SXTW)),
+                 "ld1b {z9.s}, p5/z, [x2, z1.s, sxtw]");
+  COMPARE_PREFIX(ld1b(z9.VnS(),
+                      p5.Zeroing(),
+                      SVEMemOperand(sp, z1.VnS(), UXTW)),
+                 "ld1b {z9.s}, p5/z, [sp, z1.s, uxtw]");
+  COMPARE_PREFIX(ld1h(z17.VnS(),
+                      p2.Zeroing(),
+                      SVEMemOperand(x11, z24.VnS(), SXTW)),
+                 "ld1h {z17.s}, p2/z, [x11, z24.s, sxtw]");
+  COMPARE_PREFIX(ld1w(z22.VnS(),
+                      p6.Zeroing(),
+                      SVEMemOperand(sp, z5.VnS(), UXTW)),
+                 "ld1w {z22.s}, p6/z, [sp, z5.s, uxtw]");
+  COMPARE_PREFIX(ld1sb(z12.VnS(),
+                       p7.Zeroing(),
+                       SVEMemOperand(x17, z23.VnS(), UXTW)),
+                 "ld1sb {z12.s}, p7/z, [x17, z23.s, uxtw]");
+  COMPARE_PREFIX(ld1sb(z22.VnS(),
+                       p3.Zeroing(),
+                       SVEMemOperand(x23, z23.VnS(), SXTW)),
+                 "ld1sb {z22.s}, p3/z, [x23, z23.s, sxtw]");
+  COMPARE_PREFIX(ld1sh(z11.VnS(),
+                       p2.Zeroing(),
+                       SVEMemOperand(x18, z10.VnS(), UXTW)),
+                 "ld1sh {z11.s}, p2/z, [x18, z10.s, uxtw]");
+
+  // 32-bit gather load in scalar-plus-vector vform with scaled offset.
+  COMPARE_PREFIX(ld1h(z9.VnS(),
+                      p3.Zeroing(),
+                      SVEMemOperand(sp, z4.VnS(), UXTW, 1)),
+                 "ld1h {z9.s}, p3/z, [sp, z4.s, uxtw #1]");
+  COMPARE_PREFIX(ld1w(z0.VnS(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x28, z21.VnS(), SXTW, 2)),
+                 "ld1w {z0.s}, p6/z, [x28, z21.s, sxtw #2]");
+  COMPARE_PREFIX(ld1sh(z11.VnS(),
+                       p4.Zeroing(),
+                       SVEMemOperand(sp, z0.VnS(), SXTW, 1)),
+                 "ld1sh {z11.s}, p4/z, [sp, z0.s, sxtw #1]");
+
+  // 32-bit gather first-fault load in scalar-plus-vector vform with 32-bit
+  // unpacked unscaled offset.
+  COMPARE_PREFIX(ldff1b(z18.VnS(),
+                        p6.Zeroing(),
+                        SVEMemOperand(x27, z24.VnS(), UXTW)),
+                 "ldff1b {z18.s}, p6/z, [x27, z24.s, uxtw]");
+  COMPARE_PREFIX(ldff1h(z28.VnS(),
+                        p6.Zeroing(),
+                        SVEMemOperand(x1, z30.VnS(), UXTW)),
+                 "ldff1h {z28.s}, p6/z, [x1, z30.s, uxtw]");
+  COMPARE_PREFIX(ldff1w(z12.VnS(),
+                        p3.Zeroing(),
+                        SVEMemOperand(x25, z27.VnS(), SXTW)),
+                 "ldff1w {z12.s}, p3/z, [x25, z27.s, sxtw]");
+  COMPARE_PREFIX(ldff1sb(z15.VnS(),
+                         p5.Zeroing(),
+                         SVEMemOperand(x5, z14.VnS(), SXTW)),
+                 "ldff1sb {z15.s}, p5/z, [x5, z14.s, sxtw]");
+  COMPARE_PREFIX(ldff1sh(z18.VnS(),
+                         p4.Zeroing(),
+                         SVEMemOperand(x25, z25.VnS(), SXTW)),
+                 "ldff1sh {z18.s}, p4/z, [x25, z25.s, sxtw]");
+
+  // 32-bit gather first-fault load in scalar-plus-vector vform with 32-bit
+  // scaled offset.
+  COMPARE_PREFIX(ldff1h(z25.VnS(),
+                        p3.Zeroing(),
+                        SVEMemOperand(x17, z15.VnS(), SXTW, 1)),
+                 "ldff1h {z25.s}, p3/z, [x17, z15.s, sxtw #1]");
+  COMPARE_PREFIX(ldff1w(z5.VnS(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x23, z31.VnS(), UXTW, 2)),
+                 "ldff1w {z5.s}, p4/z, [x23, z31.s, uxtw #2]");
+  COMPARE_PREFIX(ldff1sh(z10.VnS(),
+                         p0.Zeroing(),
+                         SVEMemOperand(x19, z15.VnS(), UXTW, 1)),
+                 "ldff1sh {z10.s}, p0/z, [x19, z15.s, uxtw #1]");
+
+  // Load and broadcast data to vector.
+  COMPARE_PREFIX(ld1rb(z2.VnH(), p0.Zeroing(), SVEMemOperand(x30, 0)),
+                 "ld1rb {z2.h}, p0/z, [x30]");
+  COMPARE_PREFIX(ld1rb(z14.VnS(), p2.Zeroing(), SVEMemOperand(x11, 63)),
+                 "ld1rb {z14.s}, p2/z, [x11, #63]");
+  COMPARE_PREFIX(ld1rb(z27.VnD(), p1.Zeroing(), SVEMemOperand(x29, 2)),
+                 "ld1rb {z27.d}, p1/z, [x29, #2]");
+  COMPARE_PREFIX(ld1rb(z0.VnB(), p3.Zeroing(), SVEMemOperand(sp, 59)),
+                 "ld1rb {z0.b}, p3/z, [sp, #59]");
+  COMPARE_PREFIX(ld1rh(z19.VnH(), p5.Zeroing(), SVEMemOperand(x1, 0)),
+                 "ld1rh {z19.h}, p5/z, [x1]");
+  COMPARE_PREFIX(ld1rh(z4.VnS(), p7.Zeroing(), SVEMemOperand(x29, 126)),
+                 "ld1rh {z4.s}, p7/z, [x29, #126]");
+  COMPARE_PREFIX(ld1rh(z24.VnD(), p0.Zeroing(), SVEMemOperand(sp, 78)),
+                 "ld1rh {z24.d}, p0/z, [sp, #78]");
+  COMPARE_PREFIX(ld1rw(z19.VnS(), p5.Zeroing(), SVEMemOperand(x4, 252)),
+                 "ld1rw {z19.s}, p5/z, [x4, #252]");
+  COMPARE_PREFIX(ld1rw(z13.VnD(), p3.Zeroing(), SVEMemOperand(x2, 100)),
+                 "ld1rw {z13.d}, p3/z, [x2, #100]");
+  COMPARE_PREFIX(ld1rd(z19.VnD(), p7.Zeroing(), SVEMemOperand(x14, 504)),
+                 "ld1rd {z19.d}, p7/z, [x14, #504]");
+  COMPARE_PREFIX(ld1rsb(z16.VnH(), p1.Zeroing(), SVEMemOperand(x29, 0)),
+                 "ld1rsb {z16.h}, p1/z, [x29]");
+  COMPARE_PREFIX(ld1rsb(z8.VnS(), p6.Zeroing(), SVEMemOperand(sp, 33)),
+                 "ld1rsb {z8.s}, p6/z, [sp, #33]");
+  COMPARE_PREFIX(ld1rsb(z25.VnD(), p2.Zeroing(), SVEMemOperand(x18, 63)),
+                 "ld1rsb {z25.d}, p2/z, [x18, #63]");
+  COMPARE_PREFIX(ld1rsh(z11.VnS(), p5.Zeroing(), SVEMemOperand(x14, 2)),
+                 "ld1rsh {z11.s}, p5/z, [x14, #2]");
+  COMPARE_PREFIX(ld1rsh(z28.VnD(), p1.Zeroing(), SVEMemOperand(x19, 124)),
+                 "ld1rsh {z28.d}, p1/z, [x19, #124]");
+  COMPARE_PREFIX(ld1rsw(z23.VnD(), p4.Zeroing(), SVEMemOperand(x10, 8)),
+                 "ld1rsw {z23.d}, p4/z, [x10, #8]");
+
+  CLEANUP();
+}
+
+TEST(sve_mem_32bit_gather_and_unsized_contiguous_macro) {
+  SETUP();
+
+  COMPARE_MACRO(Ld1rb(z2.VnB(), p0.Zeroing(), SVEMemOperand(x30, 100)),
+                "add x16, x30, #0x64 (100)\n"
+                "ld1rb {z2.b}, p0/z, [x16]");
+  COMPARE_MACRO(Ld1rh(z4.VnH(), p1.Zeroing(), SVEMemOperand(x21, 201)),
+                "add x16, x21, #0xc9 (201)\n"
+                "ld1rh {z4.h}, p1/z, [x16]");
+  COMPARE_MACRO(Ld1rw(z6.VnS(), p2.Zeroing(), SVEMemOperand(x14, 512)),
+                "add x16, x14, #0x200 (512)\n"
+                "ld1rw {z6.s}, p2/z, [x16]");
+  COMPARE_MACRO(Ld1rd(z8.VnD(), p3.Zeroing(), SVEMemOperand(x3, 1024)),
+                "add x16, x3, #0x400 (1024)\n"
+                "ld1rd {z8.d}, p3/z, [x16]");
+  COMPARE_MACRO(Ld1rsb(z10.VnH(), p4.Zeroing(), SVEMemOperand(sp, -100)),
+                "sub x16, sp, #0x64 (100)\n"
+                "ld1rsb {z10.h}, p4/z, [x16]");
+  COMPARE_MACRO(Ld1rsh(z12.VnS(), p5.Zeroing(), SVEMemOperand(x30, -255)),
+                "sub x16, x30, #0xff (255)\n"
+                "ld1rsh {z12.s}, p5/z, [x16]");
+  COMPARE_MACRO(Ld1rsw(z14.VnD(), p6.Zeroing(), SVEMemOperand(x1, -1024)),
+                "sub x16, x1, #0x400 (1024)\n"
+                "ld1rsw {z14.d}, p6/z, [x16]");
+}
+
+TEST(sve_mem_64bit_gather_vector_plus_immediate) {
+  SETUP();
+
+  COMPARE_PREFIX(ld1b(z2.VnD(), p2.Zeroing(), SVEMemOperand(z12.VnD(), 31)),
+                 "ld1b {z2.d}, p2/z, [z12.d, #31]");
+  COMPARE_PREFIX(ld1h(z30.VnD(), p7.Zeroing(), SVEMemOperand(z28.VnD(), 10)),
+                 "ld1h {z30.d}, p7/z, [z28.d, #10]");
+  COMPARE_PREFIX(ld1w(z10.VnD(), p5.Zeroing(), SVEMemOperand(z4.VnD(), 124)),
+                 "ld1w {z10.d}, p5/z, [z4.d, #124]");
+  COMPARE_PREFIX(ld1d(z13.VnD(), p3.Zeroing(), SVEMemOperand(z19.VnD(), 248)),
+                 "ld1d {z13.d}, p3/z, [z19.d, #248]");
+  COMPARE_PREFIX(ld1sb(z16.VnD(), p7.Zeroing(), SVEMemOperand(z31.VnD())),
+                 "ld1sb {z16.d}, p7/z, [z31.d]");
+  COMPARE_PREFIX(ld1sh(z20.VnD(), p2.Zeroing(), SVEMemOperand(z2.VnD(), 62)),
+                 "ld1sh {z20.d}, p2/z, [z2.d, #62]");
+  COMPARE_PREFIX(ld1sw(z2.VnD(), p7.Zeroing(), SVEMemOperand(z25.VnD())),
+                 "ld1sw {z2.d}, p7/z, [z25.d]");
+  COMPARE_PREFIX(ldff1b(z24.VnD(), p5.Zeroing(), SVEMemOperand(z8.VnD(), 0)),
+                 "ldff1b {z24.d}, p5/z, [z8.d]");
+  COMPARE_PREFIX(ldff1h(z9.VnD(), p3.Zeroing(), SVEMemOperand(z19.VnD())),
+                 "ldff1h {z9.d}, p3/z, [z19.d]");
+  COMPARE_PREFIX(ldff1w(z26.VnD(), p6.Zeroing(), SVEMemOperand(z15.VnD(), 4)),
+                 "ldff1w {z26.d}, p6/z, [z15.d, #4]");
+  COMPARE_PREFIX(ldff1d(z19.VnD(), p1.Zeroing(), SVEMemOperand(z14.VnD())),
+                 "ldff1d {z19.d}, p1/z, [z14.d]");
+  COMPARE_PREFIX(ldff1sb(z26.VnD(), p5.Zeroing(), SVEMemOperand(z14.VnD(), 21)),
+                 "ldff1sb {z26.d}, p5/z, [z14.d, #21]");
+  COMPARE_PREFIX(ldff1sh(z6.VnD(), p3.Zeroing(), SVEMemOperand(z19.VnD(), 42)),
+                 "ldff1sh {z6.d}, p3/z, [z19.d, #42]");
+  COMPARE_PREFIX(ldff1sw(z19.VnD(), p7.Zeroing(), SVEMemOperand(z14.VnD(), 84)),
+                 "ldff1sw {z19.d}, p7/z, [z14.d, #84]");
+
+  CLEANUP();
+}
+
+TEST(sve_mem_64bit_gather_vector_plus_immediate_macro) {
+  SETUP();
+
+  // Simple cases.
+  COMPARE_MACRO(Ld1b(z18.VnD(), p6.Zeroing(), SVEMemOperand(z31.VnD(), 31)),
+                "ld1b {z18.d}, p6/z, [z31.d, #31]");
+  COMPARE_MACRO(Ld1h(z5.VnD(), p3.Zeroing(), SVEMemOperand(z18.VnD(), 10)),
+                "ld1h {z5.d}, p3/z, [z18.d, #10]");
+  COMPARE_MACRO(Ld1w(z0.VnD(), p6.Zeroing(), SVEMemOperand(z22.VnD(), 124)),
+                "ld1w {z0.d}, p6/z, [z22.d, #124]");
+  COMPARE_MACRO(Ld1d(z18.VnD(), p3.Zeroing(), SVEMemOperand(z19.VnD(), 248)),
+                "ld1d {z18.d}, p3/z, [z19.d, #248]");
+  COMPARE_MACRO(Ld1sb(z18.VnD(), p6.Zeroing(), SVEMemOperand(z17.VnD())),
+                "ld1sb {z18.d}, p6/z, [z17.d]");
+  COMPARE_MACRO(Ld1sh(z14.VnD(), p3.Zeroing(), SVEMemOperand(z11.VnD(), 62)),
+                "ld1sh {z14.d}, p3/z, [z11.d, #62]");
+  COMPARE_MACRO(Ld1sw(z18.VnD(), p5.Zeroing(), SVEMemOperand(z14.VnD())),
+                "ld1sw {z18.d}, p5/z, [z14.d]");
+  COMPARE_MACRO(Ldff1b(z20.VnD(), p5.Zeroing(), SVEMemOperand(z17.VnD(), 0)),
+                "ldff1b {z20.d}, p5/z, [z17.d]");
+  COMPARE_MACRO(Ldff1h(z20.VnD(), p5.Zeroing(), SVEMemOperand(z16.VnD())),
+                "ldff1h {z20.d}, p5/z, [z16.d]");
+  COMPARE_MACRO(Ldff1w(z1.VnD(), p6.Zeroing(), SVEMemOperand(z16.VnD(), 4)),
+                "ldff1w {z1.d}, p6/z, [z16.d, #4]");
+  COMPARE_MACRO(Ldff1d(z16.VnD(), p1.Zeroing(), SVEMemOperand(z3.VnD())),
+                "ldff1d {z16.d}, p1/z, [z3.d]");
+  COMPARE_MACRO(Ldff1sb(z26.VnD(), p7.Zeroing(), SVEMemOperand(z3.VnD(), 21)),
+                "ldff1sb {z26.d}, p7/z, [z3.d, #21]");
+  COMPARE_MACRO(Ldff1sh(z1.VnD(), p7.Zeroing(), SVEMemOperand(z9.VnD(), 42)),
+                "ldff1sh {z1.d}, p7/z, [z9.d, #42]");
+  COMPARE_MACRO(Ldff1sw(z19.VnD(), p4.Zeroing(), SVEMemOperand(z3.VnD(), 84)),
+                "ldff1sw {z19.d}, p4/z, [z3.d, #84]");
+
+  // Unencodable cases use a scalar-plus-vector form.
+  COMPARE_MACRO(Ld1b(z23.VnD(), p6.Zeroing(), SVEMemOperand(z16.VnD(), 32)),
+                "mov x16, #0x20\n"
+                "ld1b {z23.d}, p6/z, [x16, z16.d]");
+  COMPARE_MACRO(Ld1h(z10.VnD(), p6.Zeroing(), SVEMemOperand(z11.VnD(), -2)),
+                "mov x16, #0xfffffffffffffffe\n"
+                "ld1h {z10.d}, p6/z, [x16, z11.d]");
+  COMPARE_MACRO(Ld1w(z14.VnD(), p3.Zeroing(), SVEMemOperand(z11.VnD(), 42)),
+                "mov x16, #0x2a\n"
+                "ld1w {z14.d}, p3/z, [x16, z11.d]");
+  COMPARE_MACRO(Ld1d(z10.VnD(), p4.Zeroing(), SVEMemOperand(z3.VnD(), 256)),
+                "mov x16, #0x100\n"
+                "ld1d {z10.d}, p4/z, [x16, z3.d]");
+  COMPARE_MACRO(Ld1sb(z14.VnD(), p2.Zeroing(), SVEMemOperand(z11.VnD(), -1)),
+                "mov x16, #0xffffffffffffffff\n"
+                "ld1sb {z14.d}, p2/z, [x16, z11.d]");
+  COMPARE_MACRO(Ld1sh(z20.VnD(), p7.Zeroing(), SVEMemOperand(z12.VnD(), 64)),
+                "mov x16, #0x40\n"
+                "ld1sh {z20.d}, p7/z, [x16, z12.d]");
+  COMPARE_MACRO(Ld1sw(z15.VnD(), p6.Zeroing(), SVEMemOperand(z18.VnD(), 42)),
+                "mov x16, #0x2a\n"
+                "ld1sw {z15.d}, p6/z, [x16, z18.d]");
+  COMPARE_MACRO(Ldff1b(z15.VnD(), p0.Zeroing(), SVEMemOperand(z0.VnD(), 32)),
+                "mov x16, #0x20\n"
+                "ldff1b {z15.d}, p0/z, [x16, z0.d]");
+  COMPARE_MACRO(Ldff1h(z23.VnD(), p3.Zeroing(), SVEMemOperand(z31.VnD(), -2)),
+                "mov x16, #0xfffffffffffffffe\n"
+                "ldff1h {z23.d}, p3/z, [x16, z31.d]");
+  COMPARE_MACRO(Ldff1w(z28.VnD(), p3.Zeroing(), SVEMemOperand(z17.VnD(), 42)),
+                "mov x16, #0x2a\n"
+                "ldff1w {z28.d}, p3/z, [x16, z17.d]");
+  COMPARE_MACRO(Ldff1d(z18.VnD(), p3.Zeroing(), SVEMemOperand(z13.VnD(), 256)),
+                "mov x16, #0x100\n"
+                "ldff1d {z18.d}, p3/z, [x16, z13.d]");
+  COMPARE_MACRO(Ldff1sb(z31.VnD(), p7.Zeroing(), SVEMemOperand(z3.VnD(), -1)),
+                "mov x16, #0xffffffffffffffff\n"
+                "ldff1sb {z31.d}, p7/z, [x16, z3.d]");
+  COMPARE_MACRO(Ldff1sh(z13.VnD(), p0.Zeroing(), SVEMemOperand(z15.VnD(), 64)),
+                "mov x16, #0x40\n"
+                "ldff1sh {z13.d}, p0/z, [x16, z15.d]");
+  COMPARE_MACRO(Ldff1sw(z30.VnD(), p7.Zeroing(), SVEMemOperand(z10.VnD(), 42)),
+                "mov x16, #0x2a\n"
+                "ldff1sw {z30.d}, p7/z, [x16, z10.d]");
+
+  CLEANUP();
+}
+
+TEST(sve_mem_64bit_gather_scalar_plus_vector) {
+  SETUP();
+
+  COMPARE_PREFIX(ld1b(z30.VnD(), p6.Zeroing(), SVEMemOperand(sp, z24.VnD())),
+                 "ld1b {z30.d}, p6/z, [sp, z24.d]");
+  COMPARE_PREFIX(ld1d(z18.VnD(), p5.Zeroing(), SVEMemOperand(x11, z11.VnD())),
+                 "ld1d {z18.d}, p5/z, [x11, z11.d]");
+  COMPARE_PREFIX(ld1h(z2.VnD(), p3.Zeroing(), SVEMemOperand(x16, z18.VnD())),
+                 "ld1h {z2.d}, p3/z, [x16, z18.d]");
+  COMPARE_PREFIX(ld1sb(z11.VnD(), p3.Zeroing(), SVEMemOperand(x24, z21.VnD())),
+                 "ld1sb {z11.d}, p3/z, [x24, z21.d]");
+  COMPARE_PREFIX(ld1sh(z7.VnD(), p7.Zeroing(), SVEMemOperand(x28, z23.VnD())),
+                 "ld1sh {z7.d}, p7/z, [x28, z23.d]");
+  COMPARE_PREFIX(ld1sw(z29.VnD(), p7.Zeroing(), SVEMemOperand(x27, z4.VnD())),
+                 "ld1sw {z29.d}, p7/z, [x27, z4.d]");
+  COMPARE_PREFIX(ld1w(z19.VnD(), p1.Zeroing(), SVEMemOperand(x27, z4.VnD())),
+                 "ld1w {z19.d}, p1/z, [x27, z4.d]");
+
+  COMPARE_PREFIX(ld1d(z20.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x3, z15.VnD(), LSL, 3)),
+                 "ld1d {z20.d}, p3/z, [x3, z15.d, lsl #3]");
+  COMPARE_PREFIX(ld1h(z24.VnD(),
+                      p4.Zeroing(),
+                      SVEMemOperand(x6, z11.VnD(), LSL, 1)),
+                 "ld1h {z24.d}, p4/z, [x6, z11.d, lsl #1]");
+  COMPARE_PREFIX(ld1sh(z22.VnD(),
+                       p6.Zeroing(),
+                       SVEMemOperand(x7, z31.VnD(), LSL, 1)),
+                 "ld1sh {z22.d}, p6/z, [x7, z31.d, lsl #1]");
+  COMPARE_PREFIX(ld1sw(z9.VnD(),
+                       p0.Zeroing(),
+                       SVEMemOperand(x2, z27.VnD(), LSL, 2)),
+                 "ld1sw {z9.d}, p0/z, [x2, z27.d, lsl #2]");
+  COMPARE_PREFIX(ld1w(z9.VnD(),
+                      p2.Zeroing(),
+                      SVEMemOperand(x0, z0.VnD(), LSL, 2)),
+                 "ld1w {z9.d}, p2/z, [x0, z0.d, lsl #2]");
+
+  COMPARE_PREFIX(ld1b(z19.VnD(),
+                      p5.Zeroing(),
+                      SVEMemOperand(x21, z29.VnD(), UXTW)),
+                 "ld1b {z19.d}, p5/z, [x21, z29.d, uxtw]");
+  COMPARE_PREFIX(ld1d(z9.VnD(),
+                      p5.Zeroing(),
+                      SVEMemOperand(x5, z21.VnD(), SXTW)),
+                 "ld1d {z9.d}, p5/z, [x5, z21.d, sxtw]");
+  COMPARE_PREFIX(ld1h(z26.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x1, z10.VnD(), UXTW)),
+                 "ld1h {z26.d}, p3/z, [x1, z10.d, uxtw]");
+  COMPARE_PREFIX(ld1sb(z4.VnD(),
+                       p1.Zeroing(),
+                       SVEMemOperand(x24, z15.VnD(), SXTW)),
+                 "ld1sb {z4.d}, p1/z, [x24, z15.d, sxtw]");
+  COMPARE_PREFIX(ld1sh(z9.VnD(),
+                       p1.Zeroing(),
+                       SVEMemOperand(x0, z12.VnD(), UXTW)),
+                 "ld1sh {z9.d}, p1/z, [x0, z12.d, uxtw]");
+  COMPARE_PREFIX(ld1sw(z19.VnD(),
+                       p2.Zeroing(),
+                       SVEMemOperand(x19, z16.VnD(), SXTW)),
+                 "ld1sw {z19.d}, p2/z, [x19, z16.d, sxtw]");
+  COMPARE_PREFIX(ld1w(z13.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x8, z10.VnD(), UXTW)),
+                 "ld1w {z13.d}, p3/z, [x8, z10.d, uxtw]");
+
+  COMPARE_PREFIX(ld1d(z25.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x14, z0.VnD(), UXTW, 3)),
+                 "ld1d {z25.d}, p3/z, [x14, z0.d, uxtw #3]");
+  COMPARE_PREFIX(ld1h(z21.VnD(),
+                      p5.Zeroing(),
+                      SVEMemOperand(x13, z8.VnD(), SXTW, 1)),
+                 "ld1h {z21.d}, p5/z, [x13, z8.d, sxtw #1]");
+  COMPARE_PREFIX(ld1sh(z29.VnD(),
+                       p0.Zeroing(),
+                       SVEMemOperand(x9, z10.VnD(), UXTW, 1)),
+                 "ld1sh {z29.d}, p0/z, [x9, z10.d, uxtw #1]");
+  COMPARE_PREFIX(ld1sw(z5.VnD(),
+                       p2.Zeroing(),
+                       SVEMemOperand(x1, z23.VnD(), SXTW, 2)),
+                 "ld1sw {z5.d}, p2/z, [x1, z23.d, sxtw #2]");
+  COMPARE_PREFIX(ld1w(z21.VnD(),
+                      p1.Zeroing(),
+                      SVEMemOperand(x7, z8.VnD(), UXTW, 2)),
+                 "ld1w {z21.d}, p1/z, [x7, z8.d, uxtw #2]");
+
+  CLEANUP();
+}
+
+TEST(sve_mem_prefetch) {
+  SETUP();
+
+  // Test every encodable prefetch operation.
+  const char* expected[] = {" pldl1keep",
+                            " pldl1strm",
+                            " pldl2keep",
+                            " pldl2strm",
+                            " pldl3keep",
+                            " pldl3strm",
+                            " pstl1keep",
+                            " pstl1strm",
+                            " pstl2keep",
+                            " pstl2strm",
+                            " pstl3keep",
+                            " pstl3strm"};
+
+  const PrefetchOperation kSVEPrfOperations[] = {PLDL1KEEP,
+                                                 PLDL1STRM,
+                                                 PLDL2KEEP,
+                                                 PLDL2STRM,
+                                                 PLDL3KEEP,
+                                                 PLDL3STRM,
+                                                 PSTL1KEEP,
+                                                 PSTL1STRM,
+                                                 PSTL2KEEP,
+                                                 PSTL2STRM,
+                                                 PSTL3KEEP,
+                                                 PSTL3STRM};
+
+  VIXL_STATIC_ASSERT(ArrayLength(expected) == ArrayLength(kSVEPrfOperations));
+
+
+#define VIXL_DISAM_PREFETCH_TEST(INSN, NAME, SH)                               \
+  do {                                                                         \
+    for (size_t i = 0; i < ArrayLength(kSVEPrfOperations); i++) {              \
+      PrefetchOperation op = kSVEPrfOperations[i];                             \
+      std::string str(NAME);                                                   \
+      str.append(expected[i]);                                                 \
+      /* Vector plus immediate */                                              \
+      COMPARE_PREFIX(INSN(op, p6, SVEMemOperand(z30.VnS(), 31)), str.c_str()); \
+      COMPARE_PREFIX(INSN(op, p5, SVEMemOperand(z29.VnD(), 17)), str.c_str()); \
+      /* Scalar plus immediate */                                              \
+      COMPARE_PREFIX(INSN(op, p4, SVEMemOperand(x11, -32, SVE_MUL_VL)),        \
+                     str.c_str());                                             \
+      COMPARE_PREFIX(INSN(op, p4, SVEMemOperand(sp, 31, SVE_MUL_VL)),          \
+                     str.c_str());                                             \
+      /* Scalar plus vector */                                                 \
+      COMPARE_PREFIX(INSN(op, p3, SVEMemOperand(x24, z22.VnS(), UXTW, SH)),    \
+                     str.c_str());                                             \
+      COMPARE_PREFIX(INSN(op, p2, SVEMemOperand(x24, z22.VnD(), SXTW, SH)),    \
+                     str.c_str());                                             \
+      COMPARE_PREFIX(INSN(op, p1, SVEMemOperand(x4, z2.VnD(), LSL, SH)),       \
+                     str.c_str());                                             \
+      /* Scalar plus scalar */                                                 \
+      COMPARE_PREFIX(INSN(op, p1, SVEMemOperand(x8, x29, LSL, SH)),            \
+                     str.c_str());                                             \
+      COMPARE_PREFIX(INSN(op, p0, SVEMemOperand(sp, x6, LSL, SH)),             \
+                     str.c_str());                                             \
+    }                                                                          \
+  } while (0)
+
+  VIXL_DISAM_PREFETCH_TEST(prfh, "prfh", 1);
+  VIXL_DISAM_PREFETCH_TEST(prfw, "prfw", 2);
+  VIXL_DISAM_PREFETCH_TEST(prfd, "prfd", 3);
+#undef VIXL_DISAM_PREFETCH_TEST
+
+  COMPARE_PREFIX(prfb(PLDL1KEEP, p5, SVEMemOperand(z30.VnS(), 0)),
+                 "prfb pldl1keep, p5, [z30.s]");
+  COMPARE_PREFIX(prfb(PLDL1STRM, p5, SVEMemOperand(x28, -11, SVE_MUL_VL)),
+                 "prfb pldl1strm, p5, [x28, #-11, mul vl]");
+  COMPARE_PREFIX(prfb(PLDL2KEEP, p6, SVEMemOperand(x30, x29)),
+                 "prfb pldl2keep, p6, [x30, x29]");
+  COMPARE_PREFIX(prfb(PLDL2STRM, p6, SVEMemOperand(x7, z12.VnD())),
+                 "prfb pldl2strm, p6, [x7, z12.d]");
+  COMPARE_PREFIX(prfb(PLDL2STRM, p6, SVEMemOperand(x7, z12.VnS(), UXTW)),
+                 "prfb pldl2strm, p6, [x7, z12.s, uxtw]");
+  COMPARE_PREFIX(prfd(PLDL3KEEP, p5, SVEMemOperand(z11.VnD(), 9)),
+                 "prfd pldl3keep, p5, [z11.d, #9]");
+  COMPARE_PREFIX(prfd(PLDL3STRM, p3, SVEMemOperand(x0, 0, SVE_MUL_VL)),
+                 "prfd pldl3strm, p3, [x0]");
+  COMPARE_PREFIX(prfd(PSTL1KEEP, p7, SVEMemOperand(x5, x5, LSL, 3)),
+                 "prfd pstl1keep, p7, [x5, x5, lsl #3]");
+  COMPARE_PREFIX(prfd(PSTL1STRM, p1, SVEMemOperand(x19, z18.VnS(), SXTW, 3)),
+                 "prfd pstl1strm, p1, [x19, z18.s, sxtw #3]");
+  COMPARE_PREFIX(prfh(PSTL2KEEP, p6, SVEMemOperand(z0.VnS(), 31)),
+                 "prfh pstl2keep, p6, [z0.s, #31]");
+  COMPARE_PREFIX(prfh(PSTL2STRM, p4, SVEMemOperand(x17, -3, SVE_MUL_VL)),
+                 "prfh pstl2strm, p4, [x17, #-3, mul vl]");
+  COMPARE_PREFIX(prfh(PSTL3KEEP, p3, SVEMemOperand(x0, x0, LSL, 1)),
+                 "prfh pstl3keep, p3, [x0, x0, lsl #1]");
+  COMPARE_PREFIX(prfh(PSTL3STRM, p4, SVEMemOperand(x20, z0.VnD(), LSL, 1)),
+                 "prfh pstl3strm, p4, [x20, z0.d, lsl #1]");
+  COMPARE_PREFIX(prfw(PLDL1KEEP, p3, SVEMemOperand(z23.VnD(), 5)),
+                 "prfw pldl1keep, p3, [z23.d, #5]");
+  COMPARE_PREFIX(prfw(PLDL1STRM, p1, SVEMemOperand(x4, 31, SVE_MUL_VL)),
+                 "prfw pldl1strm, p1, [x4, #31, mul vl]");
+  COMPARE_PREFIX(prfw(PLDL2KEEP, p2, SVEMemOperand(x22, x22, LSL, 2)),
+                 "prfw pldl2keep, p2, [x22, x22, lsl #2]");
+  COMPARE_PREFIX(prfw(PLDL2STRM, p1, SVEMemOperand(x2, z6.VnS(), SXTW, 2)),
+                 "prfw pldl2strm, p1, [x2, z6.s, sxtw #2]");
+
+  CLEANUP();
+}
+
+TEST(sve_mem_64bit_ff_gather_scalar_plus_vector) {
+  SETUP();
+
+  // 64-bit unscaled offset.
+  COMPARE_PREFIX(ldff1b(z18.VnD(), p6.Zeroing(), SVEMemOperand(x27, z24.VnD())),
+                 "ldff1b {z18.d}, p6/z, [x27, z24.d]");
+  COMPARE_PREFIX(ldff1h(z28.VnD(), p6.Zeroing(), SVEMemOperand(x1, z30.VnD())),
+                 "ldff1h {z28.d}, p6/z, [x1, z30.d]");
+  COMPARE_PREFIX(ldff1w(z12.VnD(), p3.Zeroing(), SVEMemOperand(x25, z27.VnD())),
+                 "ldff1w {z12.d}, p3/z, [x25, z27.d]");
+  COMPARE_PREFIX(ldff1d(z23.VnD(), p5.Zeroing(), SVEMemOperand(x29, z31.VnD())),
+                 "ldff1d {z23.d}, p5/z, [x29, z31.d]");
+  COMPARE_PREFIX(ldff1sb(z15.VnD(), p5.Zeroing(), SVEMemOperand(x5, z14.VnD())),
+                 "ldff1sb {z15.d}, p5/z, [x5, z14.d]");
+  COMPARE_PREFIX(ldff1sh(z18.VnD(),
+                         p4.Zeroing(),
+                         SVEMemOperand(x25, z25.VnD())),
+                 "ldff1sh {z18.d}, p4/z, [x25, z25.d]");
+  COMPARE_PREFIX(ldff1sw(z12.VnD(),
+                         p3.Zeroing(),
+                         SVEMemOperand(x25, z27.VnD())),
+                 "ldff1sw {z12.d}, p3/z, [x25, z27.d]");
+
+  // 64-bit scaled offset.
+  COMPARE_PREFIX(ldff1h(z25.VnD(),
+                        p3.Zeroing(),
+                        SVEMemOperand(x17, z15.VnD(), LSL, 1)),
+                 "ldff1h {z25.d}, p3/z, [x17, z15.d, lsl #1]");
+  COMPARE_PREFIX(ldff1w(z5.VnD(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x23, z31.VnD(), LSL, 2)),
+                 "ldff1w {z5.d}, p4/z, [x23, z31.d, lsl #2]");
+  COMPARE_PREFIX(ldff1d(z2.VnD(),
+                        p0.Zeroing(),
+                        SVEMemOperand(sp, z7.VnD(), LSL, 3)),
+                 "ldff1d {z2.d}, p0/z, [sp, z7.d, lsl #3]");
+  COMPARE_PREFIX(ldff1sh(z10.VnD(),
+                         p0.Zeroing(),
+                         SVEMemOperand(x19, z15.VnD(), LSL, 1)),
+                 "ldff1sh {z10.d}, p0/z, [x19, z15.d, lsl #1]");
+  COMPARE_PREFIX(ldff1sw(z5.VnD(),
+                         p4.Zeroing(),
+                         SVEMemOperand(x23, z31.VnD(), LSL, 2)),
+                 "ldff1sw {z5.d}, p4/z, [x23, z31.d, lsl #2]");
+
+  // 32-bit unpacked unscaled offset
+  COMPARE_PREFIX(ldff1b(z18.VnD(),
+                        p6.Zeroing(),
+                        SVEMemOperand(sp, z24.VnD(), UXTW)),
+                 "ldff1b {z18.d}, p6/z, [sp, z24.d, uxtw]");
+  COMPARE_PREFIX(ldff1h(z20.VnD(),
+                        p5.Zeroing(),
+                        SVEMemOperand(x7, z14.VnD(), SXTW)),
+                 "ldff1h {z20.d}, p5/z, [x7, z14.d, sxtw]");
+  COMPARE_PREFIX(ldff1w(z22.VnD(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x17, z4.VnD(), UXTW)),
+                 "ldff1w {z22.d}, p4/z, [x17, z4.d, uxtw]");
+  COMPARE_PREFIX(ldff1d(z24.VnD(),
+                        p3.Zeroing(),
+                        SVEMemOperand(x3, z24.VnD(), SXTW)),
+                 "ldff1d {z24.d}, p3/z, [x3, z24.d, sxtw]");
+  COMPARE_PREFIX(ldff1sb(z26.VnD(),
+                         p2.Zeroing(),
+                         SVEMemOperand(x13, z14.VnD(), UXTW)),
+                 "ldff1sb {z26.d}, p2/z, [x13, z14.d, uxtw]");
+  COMPARE_PREFIX(ldff1sh(z28.VnD(),
+                         p1.Zeroing(),
+                         SVEMemOperand(x23, z4.VnD(), SXTW)),
+                 "ldff1sh {z28.d}, p1/z, [x23, z4.d, sxtw]");
+  COMPARE_PREFIX(ldff1sw(z30.VnD(),
+                         p0.Zeroing(),
+                         SVEMemOperand(x8, z24.VnD(), UXTW)),
+                 "ldff1sw {z30.d}, p0/z, [x8, z24.d, uxtw]");
+
+  // 32-bit unpacked scaled offset
+  COMPARE_PREFIX(ldff1h(z4.VnD(),
+                        p5.Zeroing(),
+                        SVEMemOperand(x7, z1.VnD(), SXTW, 1)),
+                 "ldff1h {z4.d}, p5/z, [x7, z1.d, sxtw #1]");
+  COMPARE_PREFIX(ldff1w(z5.VnD(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x17, z11.VnD(), UXTW, 2)),
+                 "ldff1w {z5.d}, p4/z, [x17, z11.d, uxtw #2]");
+  COMPARE_PREFIX(ldff1d(z6.VnD(),
+                        p3.Zeroing(),
+                        SVEMemOperand(x3, z31.VnD(), SXTW, 3)),
+                 "ldff1d {z6.d}, p3/z, [x3, z31.d, sxtw #3]");
+  COMPARE_PREFIX(ldff1sh(z7.VnD(),
+                         p1.Zeroing(),
+                         SVEMemOperand(x23, z7.VnD(), UXTW, 1)),
+                 "ldff1sh {z7.d}, p1/z, [x23, z7.d, uxtw #1]");
+  COMPARE_PREFIX(ldff1sw(z8.VnD(),
+                         p0.Zeroing(),
+                         SVEMemOperand(x8, z17.VnD(), SXTW, 2)),
+                 "ldff1sw {z8.d}, p0/z, [x8, z17.d, sxtw #2]");
+
+  CLEANUP();
+}
+
+TEST(sve_ld2_scalar_plus_immediate) {
+  SETUP();
+
+  COMPARE_PREFIX(ld2b(z31.VnB(), z0.VnB(), p6.Zeroing(), SVEMemOperand(x19)),
+                 "ld2b {z31.b, z0.b}, p6/z, [x19]");
+  COMPARE_PREFIX(ld2b(z31.VnB(),
+                      z0.VnB(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19, 14, SVE_MUL_VL)),
+                 "ld2b {z31.b, z0.b}, p6/z, [x19, #14, mul vl]");
+  COMPARE_PREFIX(ld2b(z15.VnB(),
+                      z16.VnB(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19, -16, SVE_MUL_VL)),
+                 "ld2b {z15.b, z16.b}, p6/z, [x19, #-16, mul vl]");
+
+  COMPARE_PREFIX(ld2h(z15.VnH(), z16.VnH(), p6.Zeroing(), SVEMemOperand(x19)),
+                 "ld2h {z15.h, z16.h}, p6/z, [x19]");
+  COMPARE_PREFIX(ld2h(z15.VnH(),
+                      z16.VnH(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19, 14, SVE_MUL_VL)),
+                 "ld2h {z15.h, z16.h}, p0/z, [x19, #14, mul vl]");
+  COMPARE_PREFIX(ld2h(z15.VnH(),
+                      z16.VnH(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19, -16, SVE_MUL_VL)),
+                 "ld2h {z15.h, z16.h}, p0/z, [x19, #-16, mul vl]");
+
+  COMPARE_PREFIX(ld2w(z0.VnS(), z1.VnS(), p0.Zeroing(), SVEMemOperand(x19)),
+                 "ld2w {z0.s, z1.s}, p0/z, [x19]");
+  COMPARE_PREFIX(ld2w(z0.VnS(),
+                      z1.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19, 14, SVE_MUL_VL)),
+                 "ld2w {z0.s, z1.s}, p0/z, [x19, #14, mul vl]");
+  COMPARE_PREFIX(ld2w(z0.VnS(),
+                      z1.VnS(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19, -16, SVE_MUL_VL)),
+                 "ld2w {z0.s, z1.s}, p7/z, [x19, #-16, mul vl]");
+
+  COMPARE_PREFIX(ld2d(z0.VnD(), z1.VnD(), p7.Zeroing(), SVEMemOperand(x19)),
+                 "ld2d {z0.d, z1.d}, p7/z, [x19]");
+  COMPARE_PREFIX(ld2d(z31.VnD(),
+                      z0.VnD(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19, 14, SVE_MUL_VL)),
+                 "ld2d {z31.d, z0.d}, p7/z, [x19, #14, mul vl]");
+  COMPARE_PREFIX(ld2d(z31.VnD(),
+                      z0.VnD(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19, -16, SVE_MUL_VL)),
+                 "ld2d {z31.d, z0.d}, p7/z, [x19, #-16, mul vl]");
+
+  CLEANUP();
+}
+
+TEST(sve_ld3_scalar_plus_immediate) {
+  SETUP();
+
+  COMPARE_PREFIX(ld3b(z30.VnB(),
+                      z31.VnB(),
+                      z0.VnB(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19)),
+                 "ld3b {z30.b, z31.b, z0.b}, p7/z, [x19]");
+  COMPARE_PREFIX(ld3b(z30.VnB(),
+                      z31.VnB(),
+                      z0.VnB(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19, 21, SVE_MUL_VL)),
+                 "ld3b {z30.b, z31.b, z0.b}, p6/z, [x19, #21, mul vl]");
+  COMPARE_PREFIX(ld3b(z30.VnB(),
+                      z31.VnB(),
+                      z0.VnB(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19, -24, SVE_MUL_VL)),
+                 "ld3b {z30.b, z31.b, z0.b}, p6/z, [x19, #-24, mul vl]");
+
+  COMPARE_PREFIX(ld3h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19)),
+                 "ld3h {z15.h, z16.h, z17.h}, p6/z, [x19]");
+  COMPARE_PREFIX(ld3h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19, 21, SVE_MUL_VL)),
+                 "ld3h {z15.h, z16.h, z17.h}, p6/z, [x19, #21, mul vl]");
+  COMPARE_PREFIX(ld3h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19, -24, SVE_MUL_VL)),
+                 "ld3h {z15.h, z16.h, z17.h}, p0/z, [x19, #-24, mul vl]");
+
+  COMPARE_PREFIX(ld3w(z15.VnS(),
+                      z16.VnS(),
+                      z17.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19)),
+                 "ld3w {z15.s, z16.s, z17.s}, p0/z, [x19]");
+  COMPARE_PREFIX(ld3w(z0.VnS(),
+                      z1.VnS(),
+                      z2.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19, 21, SVE_MUL_VL)),
+                 "ld3w {z0.s, z1.s, z2.s}, p0/z, [x19, #21, mul vl]");
+  COMPARE_PREFIX(ld3w(z0.VnS(),
+                      z1.VnS(),
+                      z2.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19, -24, SVE_MUL_VL)),
+                 "ld3w {z0.s, z1.s, z2.s}, p0/z, [x19, #-24, mul vl]");
+
+  COMPARE_PREFIX(ld3d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19)),
+                 "ld3d {z0.d, z1.d, z2.d}, p7/z, [x19]");
+  COMPARE_PREFIX(ld3d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19, 21, SVE_MUL_VL)),
+                 "ld3d {z0.d, z1.d, z2.d}, p7/z, [x19, #21, mul vl]");
+  COMPARE_PREFIX(ld3d(z30.VnD(),
+                      z31.VnD(),
+                      z0.VnD(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19, -24, SVE_MUL_VL)),
+                 "ld3d {z30.d, z31.d, z0.d}, p7/z, [x19, #-24, mul vl]");
+
+  CLEANUP();
+}
+
+TEST(sve_ld4_scalar_plus_immediate) {
+  SETUP();
+
+  COMPARE_PREFIX(ld4b(z31.VnB(),
+                      z0.VnB(),
+                      z1.VnB(),
+                      z2.VnB(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19)),
+                 "ld4b {z31.b, z0.b, z1.b, z2.b}, p7/z, [x19]");
+  COMPARE_PREFIX(ld4b(z31.VnB(),
+                      z0.VnB(),
+                      z1.VnB(),
+                      z2.VnB(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19, 28, SVE_MUL_VL)),
+                 "ld4b {z31.b, z0.b, z1.b, z2.b}, p7/z, [x19, #28, mul vl]");
+  COMPARE_PREFIX(ld4b(z31.VnB(),
+                      z0.VnB(),
+                      z1.VnB(),
+                      z2.VnB(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19, -32, SVE_MUL_VL)),
+                 "ld4b {z31.b, z0.b, z1.b, z2.b}, p6/z, [x19, #-32, mul vl]");
+
+  COMPARE_PREFIX(ld4h(z31.VnH(),
+                      z0.VnH(),
+                      z1.VnH(),
+                      z2.VnH(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19)),
+                 "ld4h {z31.h, z0.h, z1.h, z2.h}, p6/z, [x19]");
+  COMPARE_PREFIX(ld4h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      z18.VnH(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19, 28, SVE_MUL_VL)),
+                 "ld4h {z15.h, z16.h, z17.h, z18.h}, p6/z, "
+                 "[x19, #28, mul vl]");
+  COMPARE_PREFIX(ld4h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      z18.VnH(),
+                      p6.Zeroing(),
+                      SVEMemOperand(x19, -32, SVE_MUL_VL)),
+                 "ld4h {z15.h, z16.h, z17.h, z18.h}, p6/z, "
+                 "[x19, #-32, mul vl]");
+
+  COMPARE_PREFIX(ld4w(z15.VnS(),
+                      z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19)),
+                 "ld4w {z15.s, z16.s, z17.s, z18.s}, p0/z, [x19]");
+  COMPARE_PREFIX(ld4w(z15.VnS(),
+                      z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19, 28, SVE_MUL_VL)),
+                 "ld4w {z15.s, z16.s, z17.s, z18.s}, p0/z, "
+                 "[x19, #28, mul vl]");
+  COMPARE_PREFIX(ld4w(z0.VnS(),
+                      z1.VnS(),
+                      z2.VnS(),
+                      z3.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19, -32, SVE_MUL_VL)),
+                 "ld4w {z0.s, z1.s, z2.s, z3.s}, p0/z, [x19, #-32, mul vl]");
+
+  COMPARE_PREFIX(ld4d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      z3.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x19)),
+                 "ld4d {z0.d, z1.d, z2.d, z3.d}, p0/z, [x19]");
+  COMPARE_PREFIX(ld4d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      z3.VnD(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19, 28, SVE_MUL_VL)),
+                 "ld4d {z0.d, z1.d, z2.d, z3.d}, p7/z, [x19, #28, mul vl]");
+  COMPARE_PREFIX(ld4d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      z3.VnD(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x19, -32, SVE_MUL_VL)),
+                 "ld4d {z0.d, z1.d, z2.d, z3.d}, p7/z, [x19, #-32, mul vl]");
+
+  CLEANUP();
+}
+
+TEST(sve_ld2_scalar_plus_scalar) {
+  SETUP();
+
+  COMPARE_PREFIX(ld2b(z25.VnB(),
+                      z26.VnB(),
+                      p1.Zeroing(),
+                      SVEMemOperand(x20, x19)),
+                 "ld2b {z25.b, z26.b}, p1/z, [x20, x19]");
+  COMPARE_PREFIX(ld2b(z25.VnB(),
+                      z26.VnB(),
+                      p1.Zeroing(),
+                      SVEMemOperand(sp, x19)),
+                 "ld2b {z25.b, z26.b}, p1/z, [sp, x19]");
+  COMPARE_PREFIX(ld2b(z31.VnB(),
+                      z0.VnB(),
+                      p1.Zeroing(),
+                      SVEMemOperand(sp, x19)),
+                 "ld2b {z31.b, z0.b}, p1/z, [sp, x19]");
+
+  COMPARE_PREFIX(ld2h(z31.VnH(),
+                      z0.VnH(),
+                      p1.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 1)),
+                 "ld2h {z31.h, z0.h}, p1/z, [x20, x19, lsl #1]");
+  COMPARE_PREFIX(ld2h(z31.VnH(),
+                      z0.VnH(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "ld2h {z31.h, z0.h}, p7/z, [sp, x19, lsl #1]");
+  COMPARE_PREFIX(ld2h(z31.VnH(),
+                      z0.VnH(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "ld2h {z31.h, z0.h}, p7/z, [sp, x19, lsl #1]");
+
+  COMPARE_PREFIX(ld2w(z16.VnS(),
+                      z17.VnS(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 2)),
+                 "ld2w {z16.s, z17.s}, p7/z, [x20, x19, lsl #2]");
+  COMPARE_PREFIX(ld2w(z16.VnS(),
+                      z17.VnS(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "ld2w {z16.s, z17.s}, p7/z, [sp, x19, lsl #2]");
+  COMPARE_PREFIX(ld2w(z16.VnS(),
+                      z17.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "ld2w {z16.s, z17.s}, p0/z, [sp, x19, lsl #2]");
+
+  COMPARE_PREFIX(ld2d(z16.VnD(),
+                      z17.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 3)),
+                 "ld2d {z16.d, z17.d}, p0/z, [x20, x19, lsl #3]");
+  COMPARE_PREFIX(ld2d(z25.VnD(),
+                      z26.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "ld2d {z25.d, z26.d}, p0/z, [sp, x19, lsl #3]");
+  COMPARE_PREFIX(ld2d(z25.VnD(),
+                      z26.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "ld2d {z25.d, z26.d}, p0/z, [sp, x19, lsl #3]");
+
+  CLEANUP();
+}
+
+TEST(sve_ld3_scalar_plus_scalar) {
+  SETUP();
+
+  COMPARE_PREFIX(ld3b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      p1.Zeroing(),
+                      SVEMemOperand(x20, x19)),
+                 "ld3b {z25.b, z26.b, z27.b}, p1/z, [x20, x19]");
+  COMPARE_PREFIX(ld3b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      p1.Zeroing(),
+                      SVEMemOperand(sp, x19)),
+                 "ld3b {z25.b, z26.b, z27.b}, p1/z, [sp, x19]");
+  COMPARE_PREFIX(ld3b(z30.VnB(),
+                      z31.VnB(),
+                      z0.VnB(),
+                      p1.Zeroing(),
+                      SVEMemOperand(sp, x19)),
+                 "ld3b {z30.b, z31.b, z0.b}, p1/z, [sp, x19]");
+
+  COMPARE_PREFIX(ld3h(z30.VnH(),
+                      z31.VnH(),
+                      z0.VnH(),
+                      p1.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 1)),
+                 "ld3h {z30.h, z31.h, z0.h}, p1/z, [x20, x19, lsl #1]");
+  COMPARE_PREFIX(ld3h(z30.VnH(),
+                      z31.VnH(),
+                      z0.VnH(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "ld3h {z30.h, z31.h, z0.h}, p7/z, [sp, x19, lsl #1]");
+  COMPARE_PREFIX(ld3h(z30.VnH(),
+                      z31.VnH(),
+                      z0.VnH(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "ld3h {z30.h, z31.h, z0.h}, p7/z, [sp, x19, lsl #1]");
+
+  COMPARE_PREFIX(ld3w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 2)),
+                 "ld3w {z16.s, z17.s, z18.s}, p7/z, [x20, x19, lsl #2]");
+  COMPARE_PREFIX(ld3w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "ld3w {z16.s, z17.s, z18.s}, p7/z, [sp, x19, lsl #2]");
+  COMPARE_PREFIX(ld3w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p0.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "ld3w {z16.s, z17.s, z18.s}, p0/z, [sp, x19, lsl #2]");
+
+  COMPARE_PREFIX(ld3d(z16.VnD(),
+                      z17.VnD(),
+                      z18.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 3)),
+                 "ld3d {z16.d, z17.d, z18.d}, p0/z, [x20, x19, lsl #3]");
+  COMPARE_PREFIX(ld3d(z25.VnD(),
+                      z26.VnD(),
+                      z27.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "ld3d {z25.d, z26.d, z27.d}, p0/z, [sp, x19, lsl #3]");
+  COMPARE_PREFIX(ld3d(z25.VnD(),
+                      z26.VnD(),
+                      z27.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "ld3d {z25.d, z26.d, z27.d}, p0/z, [sp, x19, lsl #3]");
+
+  CLEANUP();
+}
+
+TEST(sve_ld4_scalar_plus_scalar) {
+  SETUP();
+
+  COMPARE_PREFIX(ld4b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      z28.VnB(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x20, x19)),
+                 "ld4b {z25.b, z26.b, z27.b, z28.b}, p0/z, [x20, x19]");
+  COMPARE_PREFIX(ld4b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      z28.VnB(),
+                      p1.Zeroing(),
+                      SVEMemOperand(sp, x19)),
+                 "ld4b {z25.b, z26.b, z27.b, z28.b}, p1/z, [sp, x19]");
+  COMPARE_PREFIX(ld4b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      z28.VnB(),
+                      p1.Zeroing(),
+                      SVEMemOperand(sp, x19)),
+                 "ld4b {z25.b, z26.b, z27.b, z28.b}, p1/z, [sp, x19]");
+
+  COMPARE_PREFIX(ld4h(z31.VnH(),
+                      z0.VnH(),
+                      z1.VnH(),
+                      z2.VnH(),
+                      p1.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 1)),
+                 "ld4h {z31.h, z0.h, z1.h, z2.h}, p1/z, [x20, x19, lsl #1]");
+  COMPARE_PREFIX(ld4h(z31.VnH(),
+                      z0.VnH(),
+                      z1.VnH(),
+                      z2.VnH(),
+                      p1.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "ld4h {z31.h, z0.h, z1.h, z2.h}, p1/z, [sp, x19, lsl #1]");
+  COMPARE_PREFIX(ld4h(z31.VnH(),
+                      z0.VnH(),
+                      z1.VnH(),
+                      z2.VnH(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "ld4h {z31.h, z0.h, z1.h, z2.h}, p7/z, [sp, x19, lsl #1]");
+
+  COMPARE_PREFIX(ld4w(z31.VnS(),
+                      z0.VnS(),
+                      z1.VnS(),
+                      z2.VnS(),
+                      p7.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 2)),
+                 "ld4w {z31.s, z0.s, z1.s, z2.s}, p7/z, [x20, x19, lsl #2]");
+  COMPARE_PREFIX(ld4w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      z19.VnS(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "ld4w {z16.s, z17.s, z18.s, z19.s}, p7/z, "
+                 "[sp, x19, lsl #2]");
+  COMPARE_PREFIX(ld4w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      z19.VnS(),
+                      p7.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "ld4w {z16.s, z17.s, z18.s, z19.s}, p7/z, "
+                 "[sp, x19, lsl #2]");
+
+  COMPARE_PREFIX(ld4d(z16.VnD(),
+                      z17.VnD(),
+                      z18.VnD(),
+                      z19.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(x20, x19, LSL, 3)),
+                 "ld4d {z16.d, z17.d, z18.d, z19.d}, p0/z, "
+                 "[x20, x19, lsl #3]");
+  COMPARE_PREFIX(ld4d(z16.VnD(),
+                      z17.VnD(),
+                      z18.VnD(),
+                      z19.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "ld4d {z16.d, z17.d, z18.d, z19.d}, p0/z, "
+                 "[sp, x19, lsl #3]");
+  COMPARE_PREFIX(ld4d(z25.VnD(),
+                      z26.VnD(),
+                      z27.VnD(),
+                      z28.VnD(),
+                      p0.Zeroing(),
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "ld4d {z25.d, z26.d, z27.d, z28.d}, p0/z, "
+                 "[sp, x19, lsl #3]");
+
+  CLEANUP();
+}
+
+TEST(sve_ff_contiguous) {
+  SETUP();
+
+  COMPARE_PREFIX(ldff1b(z24.VnB(), p1.Zeroing(), SVEMemOperand(x21)),
+                 "ldff1b {z24.b}, p1/z, [x21]");
+  COMPARE_PREFIX(ldff1b(z22.VnH(), p5.Zeroing(), SVEMemOperand(x5, x28)),
+                 "ldff1b {z22.h}, p5/z, [x5, x28]");
+  COMPARE_PREFIX(ldff1b(z2.VnS(), p5.Zeroing(), SVEMemOperand(sp, x11)),
+                 "ldff1b {z2.s}, p5/z, [sp, x11]");
+  COMPARE_PREFIX(ldff1b(z12.VnD(), p3.Zeroing(), SVEMemOperand(x26, xzr)),
+                 "ldff1b {z12.d}, p3/z, [x26]");
+  COMPARE_PREFIX(ldff1h(z21.VnH(), p3.Zeroing(), SVEMemOperand(x27)),
+                 "ldff1h {z21.h}, p3/z, [x27]");
+  COMPARE_PREFIX(ldff1h(z11.VnS(),
+                        p6.Zeroing(),
+                        SVEMemOperand(sp, x15, LSL, 1)),
+                 "ldff1h {z11.s}, p6/z, [sp, x15, lsl #1]");
+  COMPARE_PREFIX(ldff1h(z6.VnD(), p7.Zeroing(), SVEMemOperand(x8, xzr, LSL, 1)),
+                 "ldff1h {z6.d}, p7/z, [x8]");
+  COMPARE_PREFIX(ldff1w(z11.VnS(), p7.Zeroing(), SVEMemOperand(sp)),
+                 "ldff1w {z11.s}, p7/z, [sp]");
+  COMPARE_PREFIX(ldff1w(z6.VnD(), p6.Zeroing(), SVEMemOperand(x5, x0, LSL, 2)),
+                 "ldff1w {z6.d}, p6/z, [x5, x0, lsl #2]");
+  COMPARE_PREFIX(ldff1d(z0.VnD(), p3.Zeroing(), SVEMemOperand(x15, x1, LSL, 3)),
+                 "ldff1d {z0.d}, p3/z, [x15, x1, lsl #3]");
+
+  COMPARE_PREFIX(ldff1sb(z31.VnH(), p4.Zeroing(), SVEMemOperand(x10, x25)),
+                 "ldff1sb {z31.h}, p4/z, [x10, x25]");
+  COMPARE_PREFIX(ldff1sb(z25.VnS(), p7.Zeroing(), SVEMemOperand(sp, x20)),
+                 "ldff1sb {z25.s}, p7/z, [sp, x20]");
+  COMPARE_PREFIX(ldff1sb(z20.VnD(), p3.Zeroing(), SVEMemOperand(x19, xzr)),
+                 "ldff1sb {z20.d}, p3/z, [x19]");
+  COMPARE_PREFIX(ldff1sh(z18.VnS(),
+                         p3.Zeroing(),
+                         SVEMemOperand(sp, x0, LSL, 1)),
+                 "ldff1sh {z18.s}, p3/z, [sp, x0, lsl #1]");
+  COMPARE_PREFIX(ldff1sh(z30.VnD(),
+                         p1.Zeroing(),
+                         SVEMemOperand(x28, xzr, LSL, 1)),
+                 "ldff1sh {z30.d}, p1/z, [x28]");
+  COMPARE_PREFIX(ldff1sw(z3.VnD(),
+                         p4.Zeroing(),
+                         SVEMemOperand(x22, x18, LSL, 2)),
+                 "ldff1sw {z3.d}, p4/z, [x22, x18, lsl #2]");
+
+  CLEANUP();
+}
+
+TEST(sve_mem_contiguous_load) {
+  SETUP();
+
+  COMPARE_PREFIX(ld1rqb(z3.VnB(), p2.Zeroing(), SVEMemOperand(x22, x18)),
+                 "ld1rqb {z3.b}, p2/z, [x22, x18]");
+  COMPARE_PREFIX(ld1rqd(z6.VnD(), p0.Zeroing(), SVEMemOperand(x18, x9, LSL, 3)),
+                 "ld1rqd {z6.d}, p0/z, [x18, x9, lsl #3]");
+  COMPARE_PREFIX(ld1rqh(z1.VnH(), p7.Zeroing(), SVEMemOperand(x9, x6, LSL, 1)),
+                 "ld1rqh {z1.h}, p7/z, [x9, x6, lsl #1]");
+  COMPARE_PREFIX(ld1rqw(z12.VnS(),
+                        p4.Zeroing(),
+                        SVEMemOperand(sp, xzr, LSL, 2)),
+                 "ld1rqw {z12.s}, p4/z, [sp, xzr, lsl #2]");
+  COMPARE_PREFIX(ld1rqb(z18.VnB(), p2.Zeroing(), SVEMemOperand(x18, 0)),
+                 "ld1rqb {z18.b}, p2/z, [x18]");
+  COMPARE_PREFIX(ld1rqb(z18.VnB(), p2.Zeroing(), SVEMemOperand(x18, 16)),
+                 "ld1rqb {z18.b}, p2/z, [x18, #16]");
+  COMPARE_PREFIX(ld1rqd(z11.VnD(), p1.Zeroing(), SVEMemOperand(x23, -16)),
+                 "ld1rqd {z11.d}, p1/z, [x23, #-16]");
+  COMPARE_PREFIX(ld1rqh(z11.VnH(), p1.Zeroing(), SVEMemOperand(x0, 112)),
+                 "ld1rqh {z11.h}, p1/z, [x0, #112]");
+  COMPARE_PREFIX(ld1rqw(z22.VnS(), p3.Zeroing(), SVEMemOperand(sp, -128)),
+                 "ld1rqw {z22.s}, p3/z, [sp, #-128]");
+
+  COMPARE_MACRO(Ld1rqb(z0.VnB(), p0.Zeroing(), SVEMemOperand(x0, 2222)),
+                "add x16, x0, #0x8ae (2222)\n"
+                "ld1rqb {z0.b}, p0/z, [x16]");
+  COMPARE_MACRO(Ld1rqw(z0.VnS(), p0.Zeroing(), SVEMemOperand(x0, x1)),
+                "add x16, x0, x1\n"
+                "ld1rqw {z0.s}, p0/z, [x16]");
+  COMPARE_MACRO(Ld1rqd(z0.VnD(), p0.Zeroing(), SVEMemOperand(x0, x1, LSL, 1)),
+                "add x16, x0, x1, lsl #1\n"
+                "ld1rqd {z0.d}, p0/z, [x16]");
+
+  COMPARE_PREFIX(ldnt1b(z21.VnB(), p5.Zeroing(), SVEMemOperand(x1, x23)),
+                 "ldnt1b {z21.b}, p5/z, [x1, x23]");
+  COMPARE_PREFIX(ldnt1d(z10.VnD(),
+                        p0.Zeroing(),
+                        SVEMemOperand(x23, x6, LSL, 3)),
+                 "ldnt1d {z10.d}, p0/z, [x23, x6, lsl #3]");
+  COMPARE_PREFIX(ldnt1h(z30.VnH(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x6, x11, LSL, 1)),
+                 "ldnt1h {z30.h}, p4/z, [x6, x11, lsl #1]");
+  COMPARE_PREFIX(ldnt1w(z0.VnS(), p4.Zeroing(), SVEMemOperand(x11, x1, LSL, 2)),
+                 "ldnt1w {z0.s}, p4/z, [x11, x1, lsl #2]");
+  COMPARE_PREFIX(ldnt1w(z0.VnS(), p4.Zeroing(), SVEMemOperand(sp, xzr, LSL, 2)),
+                 "ldnt1w {z0.s}, p4/z, [sp, xzr, lsl #2]");
+
+  COMPARE_PREFIX(ldnt1b(z1.VnB(), p3.Zeroing(), SVEMemOperand(x11)),
+                 "ldnt1b {z1.b}, p3/z, [x11]");
+  COMPARE_PREFIX(ldnt1b(z2.VnB(),
+                        p2.Zeroing(),
+                        SVEMemOperand(x12, -8, SVE_MUL_VL)),
+                 "ldnt1b {z2.b}, p2/z, [x12, #-8, mul vl]");
+  COMPARE_PREFIX(ldnt1d(z2.VnD(),
+                        p7.Zeroing(),
+                        SVEMemOperand(x13, -2, SVE_MUL_VL)),
+                 "ldnt1d {z2.d}, p7/z, [x13, #-2, mul vl]");
+  COMPARE_PREFIX(ldnt1h(z26.VnH(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x16, 3, SVE_MUL_VL)),
+                 "ldnt1h {z26.h}, p4/z, [x16, #3, mul vl]");
+  COMPARE_PREFIX(ldnt1w(z17.VnS(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                 "ldnt1w {z17.s}, p4/z, [x15, #7, mul vl]");
+  COMPARE_PREFIX(ldnt1w(z17.VnS(),
+                        p4.Zeroing(),
+                        SVEMemOperand(sp, 7, SVE_MUL_VL)),
+                 "ldnt1w {z17.s}, p4/z, [sp, #7, mul vl]");
+
+  COMPARE_MACRO(Ldnt1b(z2.VnB(),
+                       p0.Zeroing(),
+                       SVEMemOperand(x10, 42, SVE_MUL_VL)),
+                "mov x16, #0x2a\n"
+                "rdvl x17, #1\n"
+                "madd x16, x16, x17, x10\n"
+                "ldnt1b {z2.b}, p0/z, [x16]");
+  COMPARE_MACRO(Ldnt1h(z3.VnH(),
+                       p1.Zeroing(),
+                       SVEMemOperand(x11, 31, SVE_MUL_VL)),
+                "addvl x16, x11, #31\n"
+                "ldnt1h {z3.h}, p1/z, [x16]");
+  COMPARE_MACRO(Ldnt1w(z4.VnS(),
+                       p2.Zeroing(),
+                       SVEMemOperand(x12, -35, SVE_MUL_VL)),
+                "mov x16, #0xffffffffffffffdd\n"
+                "rdvl x17, #1\n"
+                "madd x16, x16, x17, x12\n"
+                "ldnt1w {z4.s}, p2/z, [x16]");
+  COMPARE_MACRO(Ldnt1d(z5.VnD(), p3.Zeroing(), SVEMemOperand(x13, 3)),
+                "add x16, x13, #0x3 (3)\n"
+                "ldnt1d {z5.d}, p3/z, [x16]");
+
+  COMPARE_PREFIX(ldnf1b(z1.VnH(),
+                        p0.Zeroing(),
+                        SVEMemOperand(x25, -8, SVE_MUL_VL)),
+                 "ldnf1b {z1.h}, p0/z, [x25, #-8, mul vl]");
+  COMPARE_PREFIX(ldnf1b(z0.VnS(),
+                        p0.Zeroing(),
+                        SVEMemOperand(x2, 7, SVE_MUL_VL)),
+                 "ldnf1b {z0.s}, p0/z, [x2, #7, mul vl]");
+  COMPARE_PREFIX(ldnf1b(z31.VnD(),
+                        p6.Zeroing(),
+                        SVEMemOperand(x0, -7, SVE_MUL_VL)),
+                 "ldnf1b {z31.d}, p6/z, [x0, #-7, mul vl]");
+  COMPARE_PREFIX(ldnf1b(z25.VnB(),
+                        p1.Zeroing(),
+                        SVEMemOperand(x5, 6, SVE_MUL_VL)),
+                 "ldnf1b {z25.b}, p1/z, [x5, #6, mul vl]");
+  COMPARE_PREFIX(ldnf1d(z25.VnD(),
+                        p0.Zeroing(),
+                        SVEMemOperand(x11, -6, SVE_MUL_VL)),
+                 "ldnf1d {z25.d}, p0/z, [x11, #-6, mul vl]");
+  COMPARE_PREFIX(ldnf1h(z22.VnH(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x7, 5, SVE_MUL_VL)),
+                 "ldnf1h {z22.h}, p4/z, [x7, #5, mul vl]");
+  COMPARE_PREFIX(ldnf1h(z7.VnS(),
+                        p2.Zeroing(),
+                        SVEMemOperand(x1, -5, SVE_MUL_VL)),
+                 "ldnf1h {z7.s}, p2/z, [x1, #-5, mul vl]");
+  COMPARE_PREFIX(ldnf1h(z5.VnD(),
+                        p3.Zeroing(),
+                        SVEMemOperand(x29, 4, SVE_MUL_VL)),
+                 "ldnf1h {z5.d}, p3/z, [x29, #4, mul vl]");
+  COMPARE_PREFIX(ldnf1sb(z12.VnH(),
+                         p5.Zeroing(),
+                         SVEMemOperand(x27, -4, SVE_MUL_VL)),
+                 "ldnf1sb {z12.h}, p5/z, [x27, #-4, mul vl]");
+  COMPARE_PREFIX(ldnf1sb(z10.VnS(),
+                         p2.Zeroing(),
+                         SVEMemOperand(x13, 3, SVE_MUL_VL)),
+                 "ldnf1sb {z10.s}, p2/z, [x13, #3, mul vl]");
+  COMPARE_PREFIX(ldnf1sb(z25.VnD(),
+                         p6.Zeroing(),
+                         SVEMemOperand(x26, -3, SVE_MUL_VL)),
+                 "ldnf1sb {z25.d}, p6/z, [x26, #-3, mul vl]");
+  COMPARE_PREFIX(ldnf1sh(z3.VnS(),
+                         p5.Zeroing(),
+                         SVEMemOperand(x1, 2, SVE_MUL_VL)),
+                 "ldnf1sh {z3.s}, p5/z, [x1, #2, mul vl]");
+  COMPARE_PREFIX(ldnf1sh(z8.VnD(),
+                         p6.Zeroing(),
+                         SVEMemOperand(x13, -2, SVE_MUL_VL)),
+                 "ldnf1sh {z8.d}, p6/z, [x13, #-2, mul vl]");
+  COMPARE_PREFIX(ldnf1sw(z5.VnD(),
+                         p6.Zeroing(),
+                         SVEMemOperand(x2, 1, SVE_MUL_VL)),
+                 "ldnf1sw {z5.d}, p6/z, [x2, #1, mul vl]");
+  COMPARE_PREFIX(ldnf1w(z11.VnS(),
+                        p3.Zeroing(),
+                        SVEMemOperand(sp, -1, SVE_MUL_VL)),
+                 "ldnf1w {z11.s}, p3/z, [sp, #-1, mul vl]");
+  COMPARE_PREFIX(ldnf1w(z10.VnD(), p6.Zeroing(), SVEMemOperand(x12)),
+                 "ldnf1w {z10.d}, p6/z, [x12]");
+
+  CLEANUP();
+}
+
+TEST(sve_mem_contiguous_store) {
+  SETUP();
+
+  COMPARE_PREFIX(stnt1b(z21.VnB(), p5.Zeroing(), SVEMemOperand(x1, x23)),
+                 "stnt1b {z21.b}, p5, [x1, x23]");
+  COMPARE_PREFIX(stnt1d(z10.VnD(),
+                        p0.Zeroing(),
+                        SVEMemOperand(x23, x6, LSL, 3)),
+                 "stnt1d {z10.d}, p0, [x23, x6, lsl #3]");
+  COMPARE_PREFIX(stnt1h(z30.VnH(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x6, x11, LSL, 1)),
+                 "stnt1h {z30.h}, p4, [x6, x11, lsl #1]");
+  COMPARE_PREFIX(stnt1w(z0.VnS(), p4.Zeroing(), SVEMemOperand(x11, x1, LSL, 2)),
+                 "stnt1w {z0.s}, p4, [x11, x1, lsl #2]");
+  COMPARE_PREFIX(stnt1w(z0.VnS(), p4.Zeroing(), SVEMemOperand(sp, xzr, LSL, 2)),
+                 "stnt1w {z0.s}, p4, [sp, xzr, lsl #2]");
+
+  COMPARE_PREFIX(stnt1b(z1.VnB(), p3.Zeroing(), SVEMemOperand(x11)),
+                 "stnt1b {z1.b}, p3, [x11]");
+  COMPARE_PREFIX(stnt1b(z2.VnB(),
+                        p2.Zeroing(),
+                        SVEMemOperand(x12, -8, SVE_MUL_VL)),
+                 "stnt1b {z2.b}, p2, [x12, #-8, mul vl]");
+  COMPARE_PREFIX(stnt1d(z2.VnD(),
+                        p7.Zeroing(),
+                        SVEMemOperand(x13, -2, SVE_MUL_VL)),
+                 "stnt1d {z2.d}, p7, [x13, #-2, mul vl]");
+  COMPARE_PREFIX(stnt1h(z26.VnH(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x16, 3, SVE_MUL_VL)),
+                 "stnt1h {z26.h}, p4, [x16, #3, mul vl]");
+  COMPARE_PREFIX(stnt1w(z17.VnS(),
+                        p4.Zeroing(),
+                        SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                 "stnt1w {z17.s}, p4, [x15, #7, mul vl]");
+  COMPARE_PREFIX(stnt1w(z17.VnS(),
+                        p4.Zeroing(),
+                        SVEMemOperand(sp, 7, SVE_MUL_VL)),
+                 "stnt1w {z17.s}, p4, [sp, #7, mul vl]");
+
+  COMPARE_MACRO(Stnt1b(z2.VnB(),
+                       p0.Zeroing(),
+                       SVEMemOperand(x10, 42, SVE_MUL_VL)),
+                "mov x16, #0x2a\n"
+                "rdvl x17, #1\n"
+                "madd x16, x16, x17, x10\n"
+                "stnt1b {z2.b}, p0, [x16]");
+  COMPARE_MACRO(Stnt1h(z3.VnH(),
+                       p1.Zeroing(),
+                       SVEMemOperand(x11, 31, SVE_MUL_VL)),
+                "addvl x16, x11, #31\n"
+                "stnt1h {z3.h}, p1, [x16]");
+  COMPARE_MACRO(Stnt1w(z4.VnS(),
+                       p2.Zeroing(),
+                       SVEMemOperand(x12, -35, SVE_MUL_VL)),
+                "mov x16, #0xffffffffffffffdd\n"
+                "rdvl x17, #1\n"
+                "madd x16, x16, x17, x12\n"
+                "stnt1w {z4.s}, p2, [x16]");
+
+  CLEANUP();
+}
+
+TEST(sve_ldr_str_simple) {
+  SETUP();
+
+  COMPARE_PREFIX(str(p14, SVEMemOperand(x0)), "str p14, [x0]");
+  COMPARE_PREFIX(str(z14, SVEMemOperand(sp)), "str z14, [sp]");
+  COMPARE_PREFIX(ldr(p4, SVEMemOperand(x0)), "ldr p4, [x0]");
+  COMPARE_PREFIX(ldr(z4, SVEMemOperand(sp)), "ldr z4, [sp]");
+  COMPARE_PREFIX(str(p15, SVEMemOperand(sp, -256, SVE_MUL_VL)),
+                 "str p15, [sp, #-256, mul vl]");
+  COMPARE_PREFIX(str(z16, SVEMemOperand(x13, 255, SVE_MUL_VL)),
+                 "str z16, [x13, #255, mul vl]");
+  COMPARE_PREFIX(ldr(p5, SVEMemOperand(sp, -42, SVE_MUL_VL)),
+                 "ldr p5, [sp, #-42, mul vl]");
+  COMPARE_PREFIX(ldr(z6, SVEMemOperand(x28, 42, SVE_MUL_VL)),
+                 "ldr z6, [x28, #42, mul vl]");
+
+  COMPARE_MACRO(Str(p14, SVEMemOperand(x0)), "str p14, [x0]");
+  COMPARE_MACRO(Str(z14, SVEMemOperand(sp)), "str z14, [sp]");
+  COMPARE_MACRO(Ldr(p4, SVEMemOperand(x0)), "ldr p4, [x0]");
+  COMPARE_MACRO(Ldr(z4, SVEMemOperand(sp)), "ldr z4, [sp]");
+  COMPARE_MACRO(Str(p15, SVEMemOperand(sp, -256, SVE_MUL_VL)),
+                "str p15, [sp, #-256, mul vl]");
+  COMPARE_MACRO(Str(z16, SVEMemOperand(x13, 255, SVE_MUL_VL)),
+                "str z16, [x13, #255, mul vl]");
+  COMPARE_MACRO(Ldr(p5, SVEMemOperand(sp, -42, SVE_MUL_VL)),
+                "ldr p5, [sp, #-42, mul vl]");
+  COMPARE_MACRO(Ldr(z6, SVEMemOperand(x28, 42, SVE_MUL_VL)),
+                "ldr z6, [x28, #42, mul vl]");
+
+  COMPARE_MACRO(Ldr(z6, SVEMemOperand(x28, 42, SVE_MUL_VL)),
+                "ldr z6, [x28, #42, mul vl]");
+
+  // IsEquivalentToScalar
+  COMPARE_MACRO(Str(p0, SVEMemOperand(x0, xzr)), "str p0, [x0]");
+  COMPARE_MACRO(Ldr(p1, SVEMemOperand(sp, xzr)), "ldr p1, [sp]");
+  COMPARE_MACRO(Str(z2, SVEMemOperand(x12, xzr)), "str z2, [x12]");
+  COMPARE_MACRO(Ldr(z3, SVEMemOperand(x7, xzr)), "ldr z3, [x7]");
+
+  // Other cases fall back on Adr. We test Adr separately, so here we just test
+  // sequences that stress scratch register allocation.
+  COMPARE_MACRO(Str(p4, SVEMemOperand(x5, 4242, SVE_MUL_VL)),
+                "mov x16, #0x1092\n"
+                "rdvl x17, #1\n"
+                "mul x16, x16, x17\n"
+                "add x16, x5, x16, asr #3\n"
+                "str p4, [x16]");
+  COMPARE_MACRO(Ldr(p6, SVEMemOperand(sp, 4242, SVE_MUL_VL)),
+                "mov x16, #0x1092\n"
+                "rdvl x17, #1\n"
+                "mul x16, x16, x17\n"
+                "asr x16, x16, #3\n"
+                "add x16, sp, x16\n"
+                "ldr p6, [x16]");
+  COMPARE_MACRO(Str(z7, SVEMemOperand(sp, 4242, SVE_MUL_VL)),
+                "mov x16, #0x1092\n"
+                "rdvl x17, #1\n"
+                "mul x16, x16, x17\n"
+                "add x16, sp, x16\n"
+                "str z7, [x16]");
+  COMPARE_MACRO(Ldr(z8, SVEMemOperand(x9, 4242, SVE_MUL_VL)),
+                "mov x16, #0x1092\n"
+                "rdvl x17, #1\n"
+                "madd x16, x16, x17, x9\n"
+                "ldr z8, [x16]");
+
+  CLEANUP();
+}
+
+TEST(sve_ld1_st1) {
+  SETUP();
+
+  COMPARE_PREFIX(st1b(z11.VnB(), p0, SVEMemOperand(x22)),
+                 "st1b {z11.b}, p0, [x22]");
+  COMPARE_PREFIX(st1b(z15.VnH(), p1, SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                 "st1b {z15.h}, p1, [x15, #7, mul vl]");
+  COMPARE_PREFIX(st1b(z19.VnS(), p2, SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                 "st1b {z19.s}, p2, [sp, #-8, mul vl]");
+  COMPARE_PREFIX(st1b(z23.VnD(), p3, SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "st1b {z23.d}, p3, [x1]");
+  COMPARE_PREFIX(st1b(z2.VnB(), p4, SVEMemOperand(x1, x2)),
+                 "st1b {z2.b}, p4, [x1, x2]");
+  COMPARE_PREFIX(st1b(z31.VnD(), p7, SVEMemOperand(x9, x9, LSL, 0)),
+                 "st1b {z31.d}, p7, [x9, x9]");
+  COMPARE_PREFIX(st1b(z3.VnS(), p0, SVEMemOperand(z14.VnS(), 30)),
+                 "st1b {z3.s}, p0, [z14.s, #30]");
+  COMPARE_PREFIX(st1b(z14.VnD(), p4, SVEMemOperand(z3.VnD(), 31)),
+                 "st1b {z14.d}, p4, [z3.d, #31]");
+  COMPARE_PREFIX(st1b(z15.VnD(), p5, SVEMemOperand(x0, z5.VnD())),
+                 "st1b {z15.d}, p5, [x0, z5.d]");
+  COMPARE_PREFIX(st1b(z15.VnS(), p5, SVEMemOperand(sp, z2.VnS(), UXTW)),
+                 "st1b {z15.s}, p5, [sp, z2.s, uxtw]");
+  COMPARE_PREFIX(st1b(z15.VnD(), p5, SVEMemOperand(x0, z25.VnD(), SXTW)),
+                 "st1b {z15.d}, p5, [x0, z25.d, sxtw]");
+
+  COMPARE_PREFIX(st1h(z15.VnH(), p1, SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                 "st1h {z15.h}, p1, [x15, #7, mul vl]");
+  COMPARE_PREFIX(st1h(z19.VnS(), p2, SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                 "st1h {z19.s}, p2, [sp, #-8, mul vl]");
+  COMPARE_PREFIX(st1h(z23.VnD(), p3, SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "st1h {z23.d}, p3, [x1]");
+  COMPARE_PREFIX(st1h(z2.VnH(), p4, SVEMemOperand(x1, x2, LSL, 1)),
+                 "st1h {z2.h}, p4, [x1, x2, lsl #1]");
+  COMPARE_PREFIX(st1h(z31.VnD(), p7, SVEMemOperand(x9, x9, LSL, 1)),
+                 "st1h {z31.d}, p7, [x9, x9, lsl #1]");
+  COMPARE_PREFIX(st1h(z3.VnS(), p0, SVEMemOperand(z14.VnS(), 30)),
+                 "st1h {z3.s}, p0, [z14.s, #30]");
+  COMPARE_PREFIX(st1h(z14.VnD(), p4, SVEMemOperand(z3.VnD(), 62)),
+                 "st1h {z14.d}, p4, [z3.d, #62]");
+  COMPARE_PREFIX(st1h(z15.VnD(), p6, SVEMemOperand(sp, z6.VnD())),
+                 "st1h {z15.d}, p6, [sp, z6.d]");
+  COMPARE_PREFIX(st1h(z15.VnD(), p6, SVEMemOperand(sp, z6.VnD(), LSL, 1)),
+                 "st1h {z15.d}, p6, [sp, z6.d, lsl #1]");
+  COMPARE_PREFIX(st1h(z15.VnS(), p3, SVEMemOperand(x25, z3.VnS(), SXTW)),
+                 "st1h {z15.s}, p3, [x25, z3.s, sxtw]");
+  COMPARE_PREFIX(st1h(z15.VnS(), p6, SVEMemOperand(x7, z15.VnS(), SXTW, 1)),
+                 "st1h {z15.s}, p6, [x7, z15.s, sxtw #1]");
+  COMPARE_PREFIX(st1h(z17.VnD(), p3, SVEMemOperand(sp, z26.VnD(), SXTW)),
+                 "st1h {z17.d}, p3, [sp, z26.d, sxtw]");
+  COMPARE_PREFIX(st1h(z15.VnD(), p6, SVEMemOperand(x13, z9.VnD(), UXTW, 1)),
+                 "st1h {z15.d}, p6, [x13, z9.d, uxtw #1]");
+
+  COMPARE_PREFIX(st1w(z19.VnS(), p2, SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                 "st1w {z19.s}, p2, [sp, #-8, mul vl]");
+  COMPARE_PREFIX(st1w(z23.VnD(), p3, SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "st1w {z23.d}, p3, [x1]");
+  COMPARE_PREFIX(st1w(z2.VnS(), p4, SVEMemOperand(x1, x2, LSL, 2)),
+                 "st1w {z2.s}, p4, [x1, x2, lsl #2]");
+  COMPARE_PREFIX(st1w(z31.VnD(), p7, SVEMemOperand(x9, x9, LSL, 2)),
+                 "st1w {z31.d}, p7, [x9, x9, lsl #2]");
+  COMPARE_PREFIX(st1w(z3.VnS(), p0, SVEMemOperand(z14.VnS(), 32)),
+                 "st1w {z3.s}, p0, [z14.s, #32]");
+  COMPARE_PREFIX(st1w(z14.VnD(), p4, SVEMemOperand(z3.VnD(), 124)),
+                 "st1w {z14.d}, p4, [z3.d, #124]");
+  COMPARE_PREFIX(st1w(z17.VnD(), p2, SVEMemOperand(x30, z5.VnD())),
+                 "st1w {z17.d}, p2, [x30, z5.d]");
+  COMPARE_PREFIX(st1w(z17.VnD(), p2, SVEMemOperand(x30, z5.VnD(), LSL, 2)),
+                 "st1w {z17.d}, p2, [x30, z5.d, lsl #2]");
+  COMPARE_PREFIX(st1w(z15.VnS(), p7, SVEMemOperand(x26, z4.VnS(), UXTW)),
+                 "st1w {z15.s}, p7, [x26, z4.s, uxtw]");
+  COMPARE_PREFIX(st1w(z15.VnS(), p4, SVEMemOperand(x8, z16.VnS(), UXTW, 2)),
+                 "st1w {z15.s}, p4, [x8, z16.s, uxtw #2]");
+  COMPARE_PREFIX(st1w(z19.VnD(), p7, SVEMemOperand(x1, z27.VnD(), UXTW)),
+                 "st1w {z19.d}, p7, [x1, z27.d, uxtw]");
+  COMPARE_PREFIX(st1w(z15.VnD(), p4, SVEMemOperand(sp, z10.VnD(), SXTW, 2)),
+                 "st1w {z15.d}, p4, [sp, z10.d, sxtw #2]");
+
+  COMPARE_PREFIX(st1d(z23.VnD(), p3, SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "st1d {z23.d}, p3, [x1]");
+  COMPARE_PREFIX(st1d(z31.VnD(), p7, SVEMemOperand(x9, x9, LSL, 3)),
+                 "st1d {z31.d}, p7, [x9, x9, lsl #3]");
+  COMPARE_PREFIX(st1d(z14.VnD(), p4, SVEMemOperand(z3.VnD(), 32)),
+                 "st1d {z14.d}, p4, [z3.d, #32]");
+  COMPARE_PREFIX(st1d(z14.VnD(), p4, SVEMemOperand(z3.VnD(), 248)),
+                 "st1d {z14.d}, p4, [z3.d, #248]");
+  COMPARE_PREFIX(st1d(z19.VnD(), p2, SVEMemOperand(x29, z22.VnD())),
+                 "st1d {z19.d}, p2, [x29, z22.d]");
+  COMPARE_PREFIX(st1d(z19.VnD(), p2, SVEMemOperand(x29, z22.VnD(), LSL, 3)),
+                 "st1d {z19.d}, p2, [x29, z22.d, lsl #3]");
+  COMPARE_PREFIX(st1d(z21.VnD(), p1, SVEMemOperand(x2, z28.VnD(), SXTW)),
+                 "st1d {z21.d}, p1, [x2, z28.d, sxtw]");
+  COMPARE_PREFIX(st1d(z15.VnD(), p2, SVEMemOperand(x14, z11.VnD(), UXTW, 3)),
+                 "st1d {z15.d}, p2, [x14, z11.d, uxtw #3]");
+
+  COMPARE_PREFIX(ld1b(z11.VnB(), p0.Zeroing(), SVEMemOperand(x22)),
+                 "ld1b {z11.b}, p0/z, [x22]");
+  COMPARE_PREFIX(ld1b(z15.VnH(),
+                      p1.Zeroing(),
+                      SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                 "ld1b {z15.h}, p1/z, [x15, #7, mul vl]");
+  COMPARE_PREFIX(ld1b(z19.VnS(),
+                      p2.Zeroing(),
+                      SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                 "ld1b {z19.s}, p2/z, [sp, #-8, mul vl]");
+  COMPARE_PREFIX(ld1b(z23.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "ld1b {z23.d}, p3/z, [x1]");
+  COMPARE_PREFIX(ld1b(z2.VnB(), p4.Zeroing(), SVEMemOperand(x1, x2)),
+                 "ld1b {z2.b}, p4/z, [x1, x2]");
+  COMPARE_PREFIX(ld1b(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 0)),
+                 "ld1b {z31.d}, p7/z, [x9, x9]");
+
+  COMPARE_PREFIX(ld1h(z15.VnH(),
+                      p1.Zeroing(),
+                      SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                 "ld1h {z15.h}, p1/z, [x15, #7, mul vl]");
+  COMPARE_PREFIX(ld1h(z19.VnS(),
+                      p2.Zeroing(),
+                      SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                 "ld1h {z19.s}, p2/z, [sp, #-8, mul vl]");
+  COMPARE_PREFIX(ld1h(z23.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "ld1h {z23.d}, p3/z, [x1]");
+  COMPARE_PREFIX(ld1h(z2.VnH(), p4.Zeroing(), SVEMemOperand(x1, x2, LSL, 1)),
+                 "ld1h {z2.h}, p4/z, [x1, x2, lsl #1]");
+  COMPARE_PREFIX(ld1h(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 1)),
+                 "ld1h {z31.d}, p7/z, [x9, x9, lsl #1]");
+
+  COMPARE_PREFIX(ld1w(z19.VnS(),
+                      p2.Zeroing(),
+                      SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                 "ld1w {z19.s}, p2/z, [sp, #-8, mul vl]");
+  COMPARE_PREFIX(ld1w(z23.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "ld1w {z23.d}, p3/z, [x1]");
+  COMPARE_PREFIX(ld1w(z2.VnS(), p4.Zeroing(), SVEMemOperand(x1, x2, LSL, 2)),
+                 "ld1w {z2.s}, p4/z, [x1, x2, lsl #2]");
+  COMPARE_PREFIX(ld1w(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 2)),
+                 "ld1w {z31.d}, p7/z, [x9, x9, lsl #2]");
+
+  COMPARE_PREFIX(ld1d(z23.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "ld1d {z23.d}, p3/z, [x1]");
+  COMPARE_PREFIX(ld1d(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 3)),
+                 "ld1d {z31.d}, p7/z, [x9, x9, lsl #3]");
+
+  COMPARE_PREFIX(ld1sb(z15.VnH(),
+                       p1.Zeroing(),
+                       SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                 "ld1sb {z15.h}, p1/z, [x15, #7, mul vl]");
+  COMPARE_PREFIX(ld1sb(z19.VnS(),
+                       p2.Zeroing(),
+                       SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                 "ld1sb {z19.s}, p2/z, [sp, #-8, mul vl]");
+  COMPARE_PREFIX(ld1d(z23.VnD(),
+                      p3.Zeroing(),
+                      SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "ld1d {z23.d}, p3/z, [x1]");
+  COMPARE_PREFIX(ld1sb(z5.VnH(), p1.Zeroing(), SVEMemOperand(x15, x1, LSL, 0)),
+                 "ld1sb {z5.h}, p1/z, [x15, x1]");
+  COMPARE_PREFIX(ld1sb(z9.VnS(), p2.Zeroing(), SVEMemOperand(x29, x3, LSL, 0)),
+                 "ld1sb {z9.s}, p2/z, [x29, x3]");
+  COMPARE_PREFIX(ld1sb(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 0)),
+                 "ld1sb {z31.d}, p7/z, [x9, x9]");
+
+  COMPARE_PREFIX(ld1sh(z19.VnS(),
+                       p2.Zeroing(),
+                       SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                 "ld1sh {z19.s}, p2/z, [sp, #-8, mul vl]");
+  COMPARE_PREFIX(ld1sh(z23.VnD(),
+                       p3.Zeroing(),
+                       SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "ld1sh {z23.d}, p3/z, [x1]");
+  COMPARE_PREFIX(ld1sh(z11.VnS(),
+                       p4.Zeroing(),
+                       SVEMemOperand(x22, x10, LSL, 1)),
+                 "ld1sh {z11.s}, p4/z, [x22, x10, lsl #1]");
+  COMPARE_PREFIX(ld1sh(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 1)),
+                 "ld1sh {z31.d}, p7/z, [x9, x9, lsl #1]");
+
+  COMPARE_PREFIX(ld1sw(z23.VnD(),
+                       p3.Zeroing(),
+                       SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                 "ld1sw {z23.d}, p3/z, [x1]");
+  COMPARE_PREFIX(ld1sw(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 2)),
+                 "ld1sw {z31.d}, p7/z, [x9, x9, lsl #2]");
+
+  CLEANUP();
+}
+
+TEST(sve_ld1_st1_macro) {
+  SETUP();
+
+  // Pass-through cases.
+  COMPARE_MACRO(St1b(z11.VnB(), p0, SVEMemOperand(x22)),
+                "st1b {z11.b}, p0, [x22]");
+  COMPARE_MACRO(St1b(z15.VnH(), p1, SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                "st1b {z15.h}, p1, [x15, #7, mul vl]");
+  COMPARE_MACRO(St1b(z19.VnS(), p2, SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                "st1b {z19.s}, p2, [sp, #-8, mul vl]");
+  COMPARE_MACRO(St1b(z23.VnD(), p3, SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                "st1b {z23.d}, p3, [x1]");
+  COMPARE_MACRO(St1b(z2.VnB(), p4, SVEMemOperand(x1, x2)),
+                "st1b {z2.b}, p4, [x1, x2]");
+  COMPARE_MACRO(St1b(z31.VnD(), p7, SVEMemOperand(x9, x9, LSL, 0)),
+                "st1b {z31.d}, p7, [x9, x9]");
+  COMPARE_MACRO(St1b(z3.VnS(), p6, SVEMemOperand(z4.VnS(), 22)),
+                "st1b {z3.s}, p6, [z4.s, #22]");
+
+  COMPARE_MACRO(St1h(z15.VnH(), p1, SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                "st1h {z15.h}, p1, [x15, #7, mul vl]");
+  COMPARE_MACRO(St1h(z19.VnS(), p2, SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                "st1h {z19.s}, p2, [sp, #-8, mul vl]");
+  COMPARE_MACRO(St1h(z23.VnD(), p3, SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                "st1h {z23.d}, p3, [x1]");
+  COMPARE_MACRO(St1h(z2.VnH(), p4, SVEMemOperand(x1, x2, LSL, 1)),
+                "st1h {z2.h}, p4, [x1, x2, lsl #1]");
+  COMPARE_MACRO(St1h(z31.VnD(), p7, SVEMemOperand(x9, x9, LSL, 1)),
+                "st1h {z31.d}, p7, [x9, x9, lsl #1]");
+  COMPARE_MACRO(St1h(z3.VnD(), p5, SVEMemOperand(z0.VnD())),
+                "st1h {z3.d}, p5, [z0.d]");
+
+  COMPARE_MACRO(St1w(z19.VnS(), p2, SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                "st1w {z19.s}, p2, [sp, #-8, mul vl]");
+  COMPARE_MACRO(St1w(z23.VnD(), p3, SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                "st1w {z23.d}, p3, [x1]");
+  COMPARE_MACRO(St1w(z2.VnS(), p4, SVEMemOperand(x1, x2, LSL, 2)),
+                "st1w {z2.s}, p4, [x1, x2, lsl #2]");
+  COMPARE_MACRO(St1w(z31.VnD(), p7, SVEMemOperand(x9, x9, LSL, 2)),
+                "st1w {z31.d}, p7, [x9, x9, lsl #2]");
+  COMPARE_MACRO(St1w(z12.VnS(), p2, SVEMemOperand(z13.VnS(), 124)),
+                "st1w {z12.s}, p2, [z13.s, #124]");
+
+  COMPARE_MACRO(St1d(z23.VnD(), p3, SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                "st1d {z23.d}, p3, [x1]");
+  COMPARE_MACRO(St1d(z31.VnD(), p7, SVEMemOperand(x9, x9, LSL, 3)),
+                "st1d {z31.d}, p7, [x9, x9, lsl #3]");
+  COMPARE_MACRO(St1d(z13.VnD(), p3, SVEMemOperand(z12.VnD(), 248)),
+                "st1d {z13.d}, p3, [z12.d, #248]");
+
+  // SVEMemOperand synthesis.
+  // Check that the MacroAssembler falls back on `CalculateSVEAddress` at the
+  // boundary conditions. We test this helper independently.
+  COMPARE_MACRO(St1b(z10.VnB(), p7, SVEMemOperand(x0, 8, SVE_MUL_VL)),
+                "addvl x16, x0, #8\n"
+                "st1b {z10.b}, p7, [x16]");
+  COMPARE_MACRO(St1h(z11.VnS(), p5, SVEMemOperand(sp, -9, SVE_MUL_VL)),
+                "mov x16, #0xffffffffffffffdc\n"
+                "rdvl x17, #1\n"
+                "mul x16, x16, x17\n"
+                "asr x16, x16, #3\n"
+                "add x16, sp, x16\n"
+                "st1h {z11.s}, p5, [x16]");
+  COMPARE_MACRO(St1w(z22.VnS(), p3, SVEMemOperand(sp, 42)),
+                "add x16, sp, #0x2a (42)\n"
+                "st1w {z22.s}, p3, [x16]");
+  COMPARE_MACRO(St1d(z22.VnD(), p1, SVEMemOperand(x3, x4)),
+                "add x16, x3, x4\n"
+                "st1d {z22.d}, p1, [x16]");
+  COMPARE_MACRO(St1b(z30.VnD(), p0, SVEMemOperand(x9, xzr)),
+                "st1b {z30.d}, p0, [x9]");
+
+// TODO: Fix these - they need scatter-store-to-scalar-plus-vector support.
+#if 0
+  COMPARE_MACRO(St1b(z1.VnD(), p6, SVEMemOperand(z0.VnD(), 32)), "mov x16, #0x20\n" "st1b {z1.d}, p6/z, [x16, z0.d]");
+  COMPARE_MACRO(St1h(z1.VnS(), p6, SVEMemOperand(z0.VnS(), -1)), "mov x16, #0xffffffffffffffff\n" "st1h {z1.s}, p6/z, [x16, z0.s]");
+#endif
+
+  COMPARE_MACRO(Ld1b(z11.VnB(), p0.Zeroing(), SVEMemOperand(x22)),
+                "ld1b {z11.b}, p0/z, [x22]");
+  COMPARE_MACRO(Ld1b(z15.VnH(),
+                     p1.Zeroing(),
+                     SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                "ld1b {z15.h}, p1/z, [x15, #7, mul vl]");
+  COMPARE_MACRO(Ld1b(z19.VnS(),
+                     p2.Zeroing(),
+                     SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                "ld1b {z19.s}, p2/z, [sp, #-8, mul vl]");
+  COMPARE_MACRO(Ld1b(z23.VnD(), p3.Zeroing(), SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                "ld1b {z23.d}, p3/z, [x1]");
+  COMPARE_MACRO(Ld1b(z2.VnB(), p4.Zeroing(), SVEMemOperand(x1, x2)),
+                "ld1b {z2.b}, p4/z, [x1, x2]");
+  COMPARE_MACRO(Ld1b(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 0)),
+                "ld1b {z31.d}, p7/z, [x9, x9]");
+
+  COMPARE_MACRO(Ld1h(z15.VnH(),
+                     p1.Zeroing(),
+                     SVEMemOperand(x15, 7, SVE_MUL_VL)),
+                "ld1h {z15.h}, p1/z, [x15, #7, mul vl]");
+  COMPARE_MACRO(Ld1h(z19.VnS(),
+                     p2.Zeroing(),
+                     SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                "ld1h {z19.s}, p2/z, [sp, #-8, mul vl]");
+  COMPARE_MACRO(Ld1h(z23.VnD(), p3.Zeroing(), SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                "ld1h {z23.d}, p3/z, [x1]");
+  COMPARE_MACRO(Ld1h(z2.VnH(), p4.Zeroing(), SVEMemOperand(x1, x2, LSL, 1)),
+                "ld1h {z2.h}, p4/z, [x1, x2, lsl #1]");
+  COMPARE_MACRO(Ld1h(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 1)),
+                "ld1h {z31.d}, p7/z, [x9, x9, lsl #1]");
+
+  COMPARE_MACRO(Ld1w(z19.VnS(),
+                     p2.Zeroing(),
+                     SVEMemOperand(sp, -8, SVE_MUL_VL)),
+                "ld1w {z19.s}, p2/z, [sp, #-8, mul vl]");
+  COMPARE_MACRO(Ld1w(z23.VnD(), p3.Zeroing(), SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                "ld1w {z23.d}, p3/z, [x1]");
+  COMPARE_MACRO(Ld1w(z2.VnS(), p4.Zeroing(), SVEMemOperand(x1, x2, LSL, 2)),
+                "ld1w {z2.s}, p4/z, [x1, x2, lsl #2]");
+  COMPARE_MACRO(Ld1w(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 2)),
+                "ld1w {z31.d}, p7/z, [x9, x9, lsl #2]");
+
+  COMPARE_MACRO(Ld1d(z23.VnD(), p3.Zeroing(), SVEMemOperand(x1, 0, SVE_MUL_VL)),
+                "ld1d {z23.d}, p3/z, [x1]");
+  COMPARE_MACRO(Ld1d(z31.VnD(), p7.Zeroing(), SVEMemOperand(x9, x9, LSL, 3)),
+                "ld1d {z31.d}, p7/z, [x9, x9, lsl #3]");
+
+  // SVEMemOperand synthesis.
+  // Check that the MacroAssembler falls back on `CalculateSVEAddress` at the
+  // boundary conditions. We test this helper independently.
+  COMPARE_MACRO(Ld1b(z10.VnB(), p7.Zeroing(), SVEMemOperand(x0, 8, SVE_MUL_VL)),
+                "addvl x16, x0, #8\n"
+                "ld1b {z10.b}, p7/z, [x16]");
+  COMPARE_MACRO(Ld1h(z11.VnS(),
+                     p5.Zeroing(),
+                     SVEMemOperand(sp, -9, SVE_MUL_VL)),
+                "mov x16, #0xffffffffffffffdc\n"
+                "rdvl x17, #1\n"
+                "mul x16, x16, x17\n"
+                "asr x16, x16, #3\n"
+                "add x16, sp, x16\n"
+                "ld1h {z11.s}, p5/z, [x16]");
+  COMPARE_MACRO(Ld1w(z22.VnS(), p3.Zeroing(), SVEMemOperand(sp, 42)),
+                "add x16, sp, #0x2a (42)\n"
+                "ld1w {z22.s}, p3/z, [x16]");
+  COMPARE_MACRO(Ld1d(z22.VnD(), p1.Zeroing(), SVEMemOperand(x3, x4)),
+                "add x16, x3, x4\n"
+                "ld1d {z22.d}, p1/z, [x16]");
+  COMPARE_MACRO(Ld1b(z30.VnD(), p0.Zeroing(), SVEMemOperand(x9, xzr)),
+                "ld1b {z30.d}, p0/z, [x9]");
+  CLEANUP();
+}
+
+TEST(sve_st2_scalar_plus_immediate) {
+  SETUP();
+
+  COMPARE_PREFIX(st2b(z31.VnB(), z0.VnB(), p6, SVEMemOperand(x19)),
+                 "st2b {z31.b, z0.b}, p6, [x19]");
+  COMPARE_PREFIX(st2b(z31.VnB(),
+                      z0.VnB(),
+                      p6,
+                      SVEMemOperand(x19, 14, SVE_MUL_VL)),
+                 "st2b {z31.b, z0.b}, p6, [x19, #14, mul vl]");
+  COMPARE_PREFIX(st2b(z15.VnB(),
+                      z16.VnB(),
+                      p6,
+                      SVEMemOperand(x19, -16, SVE_MUL_VL)),
+                 "st2b {z15.b, z16.b}, p6, [x19, #-16, mul vl]");
+
+  COMPARE_PREFIX(st2h(z15.VnH(), z16.VnH(), p6, SVEMemOperand(x19)),
+                 "st2h {z15.h, z16.h}, p6, [x19]");
+  COMPARE_PREFIX(st2h(z15.VnH(),
+                      z16.VnH(),
+                      p0,
+                      SVEMemOperand(x19, 14, SVE_MUL_VL)),
+                 "st2h {z15.h, z16.h}, p0, [x19, #14, mul vl]");
+  COMPARE_PREFIX(st2h(z15.VnH(),
+                      z16.VnH(),
+                      p0,
+                      SVEMemOperand(x19, -16, SVE_MUL_VL)),
+                 "st2h {z15.h, z16.h}, p0, [x19, #-16, mul vl]");
+
+  COMPARE_PREFIX(st2w(z0.VnS(), z1.VnS(), p0, SVEMemOperand(x19)),
+                 "st2w {z0.s, z1.s}, p0, [x19]");
+  COMPARE_PREFIX(st2w(z0.VnS(),
+                      z1.VnS(),
+                      p0,
+                      SVEMemOperand(x19, 14, SVE_MUL_VL)),
+                 "st2w {z0.s, z1.s}, p0, [x19, #14, mul vl]");
+  COMPARE_PREFIX(st2w(z0.VnS(),
+                      z1.VnS(),
+                      p7,
+                      SVEMemOperand(x19, -16, SVE_MUL_VL)),
+                 "st2w {z0.s, z1.s}, p7, [x19, #-16, mul vl]");
+
+  COMPARE_PREFIX(st2d(z0.VnD(), z1.VnD(), p7, SVEMemOperand(x19)),
+                 "st2d {z0.d, z1.d}, p7, [x19]");
+  COMPARE_PREFIX(st2d(z31.VnD(),
+                      z0.VnD(),
+                      p7,
+                      SVEMemOperand(x19, 14, SVE_MUL_VL)),
+                 "st2d {z31.d, z0.d}, p7, [x19, #14, mul vl]");
+  COMPARE_PREFIX(st2d(z31.VnD(),
+                      z0.VnD(),
+                      p7,
+                      SVEMemOperand(x19, -16, SVE_MUL_VL)),
+                 "st2d {z31.d, z0.d}, p7, [x19, #-16, mul vl]");
+
+  CLEANUP();
+}
+
+TEST(sve_st3_scalar_plus_immediate) {
+  SETUP();
+
+  COMPARE_PREFIX(st3b(z30.VnB(), z31.VnB(), z0.VnB(), p7, SVEMemOperand(x19)),
+                 "st3b {z30.b, z31.b, z0.b}, p7, [x19]");
+  COMPARE_PREFIX(st3b(z30.VnB(),
+                      z31.VnB(),
+                      z0.VnB(),
+                      p6,
+                      SVEMemOperand(x19, 21, SVE_MUL_VL)),
+                 "st3b {z30.b, z31.b, z0.b}, p6, [x19, #21, mul vl]");
+  COMPARE_PREFIX(st3b(z30.VnB(),
+                      z31.VnB(),
+                      z0.VnB(),
+                      p6,
+                      SVEMemOperand(x19, -24, SVE_MUL_VL)),
+                 "st3b {z30.b, z31.b, z0.b}, p6, [x19, #-24, mul vl]");
+
+  COMPARE_PREFIX(st3h(z15.VnH(), z16.VnH(), z17.VnH(), p6, SVEMemOperand(x19)),
+                 "st3h {z15.h, z16.h, z17.h}, p6, [x19]");
+  COMPARE_PREFIX(st3h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      p6,
+                      SVEMemOperand(x19, 21, SVE_MUL_VL)),
+                 "st3h {z15.h, z16.h, z17.h}, p6, [x19, #21, mul vl]");
+  COMPARE_PREFIX(st3h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      p0,
+                      SVEMemOperand(x19, -24, SVE_MUL_VL)),
+                 "st3h {z15.h, z16.h, z17.h}, p0, [x19, #-24, mul vl]");
+
+  COMPARE_PREFIX(st3w(z15.VnS(), z16.VnS(), z17.VnS(), p0, SVEMemOperand(x19)),
+                 "st3w {z15.s, z16.s, z17.s}, p0, [x19]");
+  COMPARE_PREFIX(st3w(z0.VnS(),
+                      z1.VnS(),
+                      z2.VnS(),
+                      p0,
+                      SVEMemOperand(x19, 21, SVE_MUL_VL)),
+                 "st3w {z0.s, z1.s, z2.s}, p0, [x19, #21, mul vl]");
+  COMPARE_PREFIX(st3w(z0.VnS(),
+                      z1.VnS(),
+                      z2.VnS(),
+                      p0,
+                      SVEMemOperand(x19, -24, SVE_MUL_VL)),
+                 "st3w {z0.s, z1.s, z2.s}, p0, [x19, #-24, mul vl]");
+
+  COMPARE_PREFIX(st3d(z0.VnD(), z1.VnD(), z2.VnD(), p7, SVEMemOperand(x19)),
+                 "st3d {z0.d, z1.d, z2.d}, p7, [x19]");
+  COMPARE_PREFIX(st3d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      p7,
+                      SVEMemOperand(x19, 21, SVE_MUL_VL)),
+                 "st3d {z0.d, z1.d, z2.d}, p7, [x19, #21, mul vl]");
+  COMPARE_PREFIX(st3d(z30.VnD(),
+                      z31.VnD(),
+                      z0.VnD(),
+                      p7,
+                      SVEMemOperand(x19, -24, SVE_MUL_VL)),
+                 "st3d {z30.d, z31.d, z0.d}, p7, [x19, #-24, mul vl]");
+
+  CLEANUP();
+}
+
+TEST(sve_st4_scalar_plus_immediate) {
+  SETUP();
+
+  COMPARE_PREFIX(st4b(z31.VnB(),
+                      z0.VnB(),
+                      z1.VnB(),
+                      z2.VnB(),
+                      p7,
+                      SVEMemOperand(x19)),
+                 "st4b {z31.b, z0.b, z1.b, z2.b}, p7, [x19]");
+  COMPARE_PREFIX(st4b(z31.VnB(),
+                      z0.VnB(),
+                      z1.VnB(),
+                      z2.VnB(),
+                      p7,
+                      SVEMemOperand(x19, 28, SVE_MUL_VL)),
+                 "st4b {z31.b, z0.b, z1.b, z2.b}, p7, [x19, #28, mul vl]");
+  COMPARE_PREFIX(st4b(z31.VnB(),
+                      z0.VnB(),
+                      z1.VnB(),
+                      z2.VnB(),
+                      p6,
+                      SVEMemOperand(x19, -32, SVE_MUL_VL)),
+                 "st4b {z31.b, z0.b, z1.b, z2.b}, p6, [x19, #-32, mul vl]");
+
+  COMPARE_PREFIX(st4h(z31.VnH(),
+                      z0.VnH(),
+                      z1.VnH(),
+                      z2.VnH(),
+                      p6,
+                      SVEMemOperand(x19)),
+                 "st4h {z31.h, z0.h, z1.h, z2.h}, p6, [x19]");
+  COMPARE_PREFIX(st4h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      z18.VnH(),
+                      p6,
+                      SVEMemOperand(x19, 28, SVE_MUL_VL)),
+                 "st4h {z15.h, z16.h, z17.h, z18.h}, p6, [x19, #28, mul vl]");
+  COMPARE_PREFIX(st4h(z15.VnH(),
+                      z16.VnH(),
+                      z17.VnH(),
+                      z18.VnH(),
+                      p6,
+                      SVEMemOperand(x19, -32, SVE_MUL_VL)),
+                 "st4h {z15.h, z16.h, z17.h, z18.h}, p6, "
+                 "[x19, #-32, mul vl]");
+
+  COMPARE_PREFIX(st4w(z15.VnS(),
+                      z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p0,
+                      SVEMemOperand(x19)),
+                 "st4w {z15.s, z16.s, z17.s, z18.s}, p0, [x19]");
+  COMPARE_PREFIX(st4w(z15.VnS(),
+                      z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p0,
+                      SVEMemOperand(x19, 28, SVE_MUL_VL)),
+                 "st4w {z15.s, z16.s, z17.s, z18.s}, p0, [x19, #28, mul vl]");
+  COMPARE_PREFIX(st4w(z0.VnS(),
+                      z1.VnS(),
+                      z2.VnS(),
+                      z3.VnS(),
+                      p0,
+                      SVEMemOperand(x19, -32, SVE_MUL_VL)),
+                 "st4w {z0.s, z1.s, z2.s, z3.s}, p0, [x19, #-32, mul vl]");
+
+  COMPARE_PREFIX(st4d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      z3.VnD(),
+                      p0,
+                      SVEMemOperand(x19)),
+                 "st4d {z0.d, z1.d, z2.d, z3.d}, p0, [x19]");
+  COMPARE_PREFIX(st4d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      z3.VnD(),
+                      p7,
+                      SVEMemOperand(x19, 28, SVE_MUL_VL)),
+                 "st4d {z0.d, z1.d, z2.d, z3.d}, p7, [x19, #28, mul vl]");
+  COMPARE_PREFIX(st4d(z0.VnD(),
+                      z1.VnD(),
+                      z2.VnD(),
+                      z3.VnD(),
+                      p7,
+                      SVEMemOperand(x19, -32, SVE_MUL_VL)),
+                 "st4d {z0.d, z1.d, z2.d, z3.d}, p7, [x19, #-32, mul vl]");
+
+  CLEANUP();
+}
+
+TEST(sve_st2_scalar_plus_scalar) {
+  SETUP();
+
+  COMPARE_PREFIX(st2b(z25.VnB(), z26.VnB(), p1, SVEMemOperand(x20, x19)),
+                 "st2b {z25.b, z26.b}, p1, [x20, x19]");
+  COMPARE_PREFIX(st2b(z25.VnB(), z26.VnB(), p1, SVEMemOperand(sp, x19)),
+                 "st2b {z25.b, z26.b}, p1, [sp, x19]");
+  COMPARE_PREFIX(st2b(z31.VnB(), z0.VnB(), p1, SVEMemOperand(sp, x19)),
+                 "st2b {z31.b, z0.b}, p1, [sp, x19]");
+
+  COMPARE_PREFIX(st2h(z31.VnH(), z0.VnH(), p1, SVEMemOperand(x20, x19, LSL, 1)),
+                 "st2h {z31.h, z0.h}, p1, [x20, x19, lsl #1]");
+  COMPARE_PREFIX(st2h(z31.VnH(), z0.VnH(), p7, SVEMemOperand(sp, x19, LSL, 1)),
+                 "st2h {z31.h, z0.h}, p7, [sp, x19, lsl #1]");
+  COMPARE_PREFIX(st2h(z31.VnH(), z0.VnH(), p7, SVEMemOperand(sp, x19, LSL, 1)),
+                 "st2h {z31.h, z0.h}, p7, [sp, x19, lsl #1]");
+
+  COMPARE_PREFIX(st2w(z16.VnS(),
+                      z17.VnS(),
+                      p7,
+                      SVEMemOperand(x20, x19, LSL, 2)),
+                 "st2w {z16.s, z17.s}, p7, [x20, x19, lsl #2]");
+  COMPARE_PREFIX(st2w(z16.VnS(), z17.VnS(), p7, SVEMemOperand(sp, x19, LSL, 2)),
+                 "st2w {z16.s, z17.s}, p7, [sp, x19, lsl #2]");
+  COMPARE_PREFIX(st2w(z16.VnS(), z17.VnS(), p0, SVEMemOperand(sp, x19, LSL, 2)),
+                 "st2w {z16.s, z17.s}, p0, [sp, x19, lsl #2]");
+
+  COMPARE_PREFIX(st2d(z16.VnD(),
+                      z17.VnD(),
+                      p0,
+                      SVEMemOperand(x20, x19, LSL, 3)),
+                 "st2d {z16.d, z17.d}, p0, [x20, x19, lsl #3]");
+  COMPARE_PREFIX(st2d(z25.VnD(), z26.VnD(), p0, SVEMemOperand(sp, x19, LSL, 3)),
+                 "st2d {z25.d, z26.d}, p0, [sp, x19, lsl #3]");
+  COMPARE_PREFIX(st2d(z25.VnD(), z26.VnD(), p0, SVEMemOperand(sp, x19, LSL, 3)),
+                 "st2d {z25.d, z26.d}, p0, [sp, x19, lsl #3]");
+
+  CLEANUP();
+}
+
+TEST(sve_st3_scalar_plus_scalar) {
+  SETUP();
+
+  COMPARE_PREFIX(st3b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      p1,
+                      SVEMemOperand(x20, x19)),
+                 "st3b {z25.b, z26.b, z27.b}, p1, [x20, x19]");
+  COMPARE_PREFIX(st3b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      p1,
+                      SVEMemOperand(sp, x19)),
+                 "st3b {z25.b, z26.b, z27.b}, p1, [sp, x19]");
+  COMPARE_PREFIX(st3b(z30.VnB(),
+                      z31.VnB(),
+                      z0.VnB(),
+                      p1,
+                      SVEMemOperand(sp, x19)),
+                 "st3b {z30.b, z31.b, z0.b}, p1, [sp, x19]");
+
+  COMPARE_PREFIX(st3h(z30.VnH(),
+                      z31.VnH(),
+                      z0.VnH(),
+                      p1,
+                      SVEMemOperand(x20, x19, LSL, 1)),
+                 "st3h {z30.h, z31.h, z0.h}, p1, [x20, x19, lsl #1]");
+  COMPARE_PREFIX(st3h(z30.VnH(),
+                      z31.VnH(),
+                      z0.VnH(),
+                      p7,
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "st3h {z30.h, z31.h, z0.h}, p7, [sp, x19, lsl #1]");
+  COMPARE_PREFIX(st3h(z30.VnH(),
+                      z31.VnH(),
+                      z0.VnH(),
+                      p7,
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "st3h {z30.h, z31.h, z0.h}, p7, [sp, x19, lsl #1]");
+
+  COMPARE_PREFIX(st3w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p7,
+                      SVEMemOperand(x20, x19, LSL, 2)),
+                 "st3w {z16.s, z17.s, z18.s}, p7, [x20, x19, lsl #2]");
+  COMPARE_PREFIX(st3w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p7,
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "st3w {z16.s, z17.s, z18.s}, p7, [sp, x19, lsl #2]");
+  COMPARE_PREFIX(st3w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      p0,
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "st3w {z16.s, z17.s, z18.s}, p0, [sp, x19, lsl #2]");
+
+  COMPARE_PREFIX(st3d(z16.VnD(),
+                      z17.VnD(),
+                      z18.VnD(),
+                      p0,
+                      SVEMemOperand(x20, x19, LSL, 3)),
+                 "st3d {z16.d, z17.d, z18.d}, p0, [x20, x19, lsl #3]");
+  COMPARE_PREFIX(st3d(z25.VnD(),
+                      z26.VnD(),
+                      z27.VnD(),
+                      p0,
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "st3d {z25.d, z26.d, z27.d}, p0, [sp, x19, lsl #3]");
+  COMPARE_PREFIX(st3d(z25.VnD(),
+                      z26.VnD(),
+                      z27.VnD(),
+                      p0,
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "st3d {z25.d, z26.d, z27.d}, p0, [sp, x19, lsl #3]");
+
+  CLEANUP();
+}
+
+TEST(sve_st4_scalar_plus_scalar) {
+  SETUP();
+
+  COMPARE_PREFIX(st4b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      z28.VnB(),
+                      p0,
+                      SVEMemOperand(x20, x19)),
+                 "st4b {z25.b, z26.b, z27.b, z28.b}, p0, [x20, x19]");
+  COMPARE_PREFIX(st4b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      z28.VnB(),
+                      p1,
+                      SVEMemOperand(sp, x19)),
+                 "st4b {z25.b, z26.b, z27.b, z28.b}, p1, [sp, x19]");
+  COMPARE_PREFIX(st4b(z25.VnB(),
+                      z26.VnB(),
+                      z27.VnB(),
+                      z28.VnB(),
+                      p1,
+                      SVEMemOperand(sp, x19)),
+                 "st4b {z25.b, z26.b, z27.b, z28.b}, p1, [sp, x19]");
+
+  COMPARE_PREFIX(st4h(z31.VnH(),
+                      z0.VnH(),
+                      z1.VnH(),
+                      z2.VnH(),
+                      p1,
+                      SVEMemOperand(x20, x19, LSL, 1)),
+                 "st4h {z31.h, z0.h, z1.h, z2.h}, p1, [x20, x19, lsl #1]");
+  COMPARE_PREFIX(st4h(z31.VnH(),
+                      z0.VnH(),
+                      z1.VnH(),
+                      z2.VnH(),
+                      p1,
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "st4h {z31.h, z0.h, z1.h, z2.h}, p1, [sp, x19, lsl #1]");
+  COMPARE_PREFIX(st4h(z31.VnH(),
+                      z0.VnH(),
+                      z1.VnH(),
+                      z2.VnH(),
+                      p7,
+                      SVEMemOperand(sp, x19, LSL, 1)),
+                 "st4h {z31.h, z0.h, z1.h, z2.h}, p7, [sp, x19, lsl #1]");
+
+  COMPARE_PREFIX(st4w(z31.VnS(),
+                      z0.VnS(),
+                      z1.VnS(),
+                      z2.VnS(),
+                      p7,
+                      SVEMemOperand(x20, x19, LSL, 2)),
+                 "st4w {z31.s, z0.s, z1.s, z2.s}, p7, [x20, x19, lsl #2]");
+  COMPARE_PREFIX(st4w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      z19.VnS(),
+                      p7,
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "st4w {z16.s, z17.s, z18.s, z19.s}, p7, [sp, x19, lsl #2]");
+  COMPARE_PREFIX(st4w(z16.VnS(),
+                      z17.VnS(),
+                      z18.VnS(),
+                      z19.VnS(),
+                      p7,
+                      SVEMemOperand(sp, x19, LSL, 2)),
+                 "st4w {z16.s, z17.s, z18.s, z19.s}, p7, [sp, x19, lsl #2]");
+
+  COMPARE_PREFIX(st4d(z16.VnD(),
+                      z17.VnD(),
+                      z18.VnD(),
+                      z19.VnD(),
+                      p0,
+                      SVEMemOperand(x20, x19, LSL, 3)),
+                 "st4d {z16.d, z17.d, z18.d, z19.d}, p0, [x20, x19, lsl #3]");
+  COMPARE_PREFIX(st4d(z16.VnD(),
+                      z17.VnD(),
+                      z18.VnD(),
+                      z19.VnD(),
+                      p0,
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "st4d {z16.d, z17.d, z18.d, z19.d}, p0, [sp, x19, lsl #3]");
+  COMPARE_PREFIX(st4d(z25.VnD(),
+                      z26.VnD(),
+                      z27.VnD(),
+                      z28.VnD(),
+                      p0,
+                      SVEMemOperand(sp, x19, LSL, 3)),
+                 "st4d {z25.d, z26.d, z27.d, z28.d}, p0, [sp, x19, lsl #3]");
+
+  CLEANUP();
+}
+
+TEST(sve_mul_index) {
+  SETUP();
+
+  COMPARE_PREFIX(sdot(z17.VnD(), z21.VnH(), z15.VnH(), 0),
+                 "sdot z17.d, z21.h, z15.h[0]");
+  COMPARE_PREFIX(sdot(z28.VnS(), z9.VnB(), z7.VnB(), 1),
+                 "sdot z28.s, z9.b, z7.b[1]");
+  COMPARE_PREFIX(udot(z26.VnD(), z15.VnH(), z1.VnH(), 1),
+                 "udot z26.d, z15.h, z1.h[1]");
+  COMPARE_PREFIX(udot(z23.VnS(), z24.VnB(), z5.VnB(), 3),
+                 "udot z23.s, z24.b, z5.b[3]");
+
+  CLEANUP();
+}
+
+TEST(sve_mul_index_macro) {
+  SETUP();
+
+  COMPARE_MACRO(Sdot(z0.VnS(), z0.VnS(), z2.VnB(), z4.VnB(), 0),
+                "sdot z0.s, z2.b, z4.b[0]");
+  COMPARE_MACRO(Sdot(z3.VnD(), z4.VnD(), z3.VnH(), z5.VnH(), 1),
+                "movprfx z31, z4\n"
+                "sdot z31.d, z3.h, z5.h[1]\n"
+                "mov z3.d, z31.d");
+  COMPARE_MACRO(Sdot(z4.VnS(), z5.VnS(), z6.VnB(), z4.VnB(), 2),
+                "movprfx z31, z5\n"
+                "sdot z31.s, z6.b, z4.b[2]\n"
+                "mov z4.d, z31.d");
+  COMPARE_MACRO(Sdot(z6.VnD(), z7.VnD(), z8.VnH(), z9.VnH(), 0),
+                "movprfx z6, z7\n"
+                "sdot z6.d, z8.h, z9.h[0]");
+  COMPARE_MACRO(Sdot(z5.VnD(), z5.VnD(), z5.VnH(), z5.VnH(), 1),
+                "sdot z5.d, z5.h, z5.h[1]");
+
+  COMPARE_MACRO(Udot(z0.VnD(), z0.VnD(), z2.VnH(), z4.VnH(), 1),
+                "udot z0.d, z2.h, z4.h[1]");
+  COMPARE_MACRO(Udot(z3.VnS(), z4.VnS(), z3.VnB(), z5.VnB(), 3),
+                "movprfx z31, z4\n"
+                "udot z31.s, z3.b, z5.b[3]\n"
+                "mov z3.d, z31.d");
+  COMPARE_MACRO(Udot(z4.VnD(), z5.VnD(), z6.VnH(), z4.VnH(), 0),
+                "movprfx z31, z5\n"
+                "udot z31.d, z6.h, z4.h[0]\n"
+                "mov z4.d, z31.d");
+  COMPARE_MACRO(Udot(z9.VnS(), z8.VnS(), z7.VnB(), z6.VnB(), 2),
+                "movprfx z9, z8\n"
+                "udot z9.s, z7.b, z6.b[2]");
+  COMPARE_MACRO(Udot(z5.VnS(), z5.VnS(), z5.VnB(), z5.VnB(), 1),
+                "udot z5.s, z5.b, z5.b[1]");
+  CLEANUP();
+}
+
+TEST(sve_partition_break) {
+  SETUP();
+
+  COMPARE_PREFIX(brkas(p8.VnB(), p5.Zeroing(), p4.VnB()),
+                 "brkas p8.b, p5/z, p4.b");
+  COMPARE_PREFIX(brka(p11.VnB(), p7.Zeroing(), p15.VnB()),
+                 "brka p11.b, p7/z, p15.b");
+  COMPARE_PREFIX(brka(p12.VnB(), p8.Merging(), p13.VnB()),
+                 "brka p12.b, p8/m, p13.b");
+  COMPARE_PREFIX(brkbs(p6.VnB(), p9.Zeroing(), p14.VnB()),
+                 "brkbs p6.b, p9/z, p14.b");
+  COMPARE_PREFIX(brkb(p11.VnB(), p6.Zeroing(), p4.VnB()),
+                 "brkb p11.b, p6/z, p4.b");
+  COMPARE_PREFIX(brkb(p12.VnB(), p7.Merging(), p5.VnB()),
+                 "brkb p12.b, p7/m, p5.b");
+  COMPARE_PREFIX(brkns(p2.VnB(), p11.Zeroing(), p0.VnB(), p2.VnB()),
+                 "brkns p2.b, p11/z, p0.b, p2.b");
+  COMPARE_PREFIX(brkn(p4.VnB(), p3.Zeroing(), p1.VnB(), p4.VnB()),
+                 "brkn p4.b, p3/z, p1.b, p4.b");
+
+  COMPARE_MACRO(Brkns(p3.VnB(), p10.Zeroing(), p2.VnB(), p5.VnB()),
+                "mov p3.b, p5.b\n"
+                "brkns p3.b, p10/z, p2.b, p3.b");
+  COMPARE_MACRO(Brkn(p5.VnB(), p4.Zeroing(), p3.VnB(), p7.VnB()),
+                "mov p5.b, p7.b\n"
+                "brkn p5.b, p4/z, p3.b, p5.b");
+
+  CLEANUP();
+}
+
+TEST(sve_permute_predicate) {
+  SETUP();
+
+  COMPARE_PREFIX(rev(p15.VnB(), p6.VnB()), "rev p15.b, p6.b");
+  COMPARE_PREFIX(rev(p15.VnH(), p6.VnH()), "rev p15.h, p6.h");
+  COMPARE_PREFIX(rev(p15.VnS(), p6.VnS()), "rev p15.s, p6.s");
+  COMPARE_PREFIX(rev(p15.VnD(), p6.VnD()), "rev p15.d, p6.d");
+  COMPARE_PREFIX(trn1(p13.VnB(), p15.VnB(), p12.VnB()),
+                 "trn1 p13.b, p15.b, p12.b");
+  COMPARE_PREFIX(trn1(p13.VnH(), p15.VnH(), p12.VnH()),
+                 "trn1 p13.h, p15.h, p12.h");
+  COMPARE_PREFIX(trn1(p13.VnS(), p15.VnS(), p12.VnS()),
+                 "trn1 p13.s, p15.s, p12.s");
+  COMPARE_PREFIX(trn1(p13.VnD(), p15.VnD(), p12.VnD()),
+                 "trn1 p13.d, p15.d, p12.d");
+  COMPARE_PREFIX(trn2(p5.VnB(), p5.VnB(), p6.VnB()), "trn2 p5.b, p5.b, p6.b");
+  COMPARE_PREFIX(trn2(p5.VnH(), p5.VnH(), p6.VnH()), "trn2 p5.h, p5.h, p6.h");
+  COMPARE_PREFIX(trn2(p5.VnS(), p5.VnS(), p6.VnS()), "trn2 p5.s, p5.s, p6.s");
+  COMPARE_PREFIX(trn2(p5.VnD(), p5.VnD(), p6.VnD()), "trn2 p5.d, p5.d, p6.d");
+  COMPARE_PREFIX(uzp1(p14.VnB(), p4.VnB(), p14.VnB()),
+                 "uzp1 p14.b, p4.b, p14.b");
+  COMPARE_PREFIX(uzp1(p14.VnH(), p4.VnH(), p14.VnH()),
+                 "uzp1 p14.h, p4.h, p14.h");
+  COMPARE_PREFIX(uzp1(p14.VnS(), p4.VnS(), p14.VnS()),
+                 "uzp1 p14.s, p4.s, p14.s");
+  COMPARE_PREFIX(uzp1(p14.VnD(), p4.VnD(), p14.VnD()),
+                 "uzp1 p14.d, p4.d, p14.d");
+  COMPARE_PREFIX(uzp2(p6.VnB(), p11.VnB(), p2.VnB()), "uzp2 p6.b, p11.b, p2.b");
+  COMPARE_PREFIX(uzp2(p6.VnH(), p11.VnH(), p2.VnH()), "uzp2 p6.h, p11.h, p2.h");
+  COMPARE_PREFIX(uzp2(p6.VnS(), p11.VnS(), p2.VnS()), "uzp2 p6.s, p11.s, p2.s");
+  COMPARE_PREFIX(uzp2(p6.VnD(), p11.VnD(), p2.VnD()), "uzp2 p6.d, p11.d, p2.d");
+  COMPARE_PREFIX(zip1(p13.VnB(), p4.VnB(), p12.VnB()),
+                 "zip1 p13.b, p4.b, p12.b");
+  COMPARE_PREFIX(zip1(p13.VnH(), p4.VnH(), p12.VnH()),
+                 "zip1 p13.h, p4.h, p12.h");
+  COMPARE_PREFIX(zip1(p13.VnS(), p4.VnS(), p12.VnS()),
+                 "zip1 p13.s, p4.s, p12.s");
+  COMPARE_PREFIX(zip1(p13.VnD(), p4.VnD(), p12.VnD()),
+                 "zip1 p13.d, p4.d, p12.d");
+  COMPARE_PREFIX(zip2(p1.VnB(), p15.VnB(), p2.VnB()), "zip2 p1.b, p15.b, p2.b");
+  COMPARE_PREFIX(zip2(p1.VnH(), p15.VnH(), p2.VnH()), "zip2 p1.h, p15.h, p2.h");
+  COMPARE_PREFIX(zip2(p1.VnS(), p15.VnS(), p2.VnS()), "zip2 p1.s, p15.s, p2.s");
+  COMPARE_PREFIX(zip2(p1.VnD(), p15.VnD(), p2.VnD()), "zip2 p1.d, p15.d, p2.d");
+  COMPARE_PREFIX(punpkhi(p12.VnH(), p6.VnB()), "punpkhi p12.h, p6.b");
+  COMPARE_PREFIX(punpklo(p4.VnH(), p14.VnB()), "punpklo p4.h, p14.b");
+
+  CLEANUP();
+}
+
+TEST(sve_permute_vector_extract) {
+  SETUP();
+
+  COMPARE_MACRO(Ext(z10.VnB(), z10.VnB(), z2.VnB(), 0),
+                "ext z10.b, z10.b, z2.b, #0");
+  COMPARE_MACRO(Ext(z10.VnB(), z10.VnB(), z2.VnB(), 1),
+                "ext z10.b, z10.b, z2.b, #1");
+  COMPARE_MACRO(Ext(z2.VnB(), z2.VnB(), z10.VnB(), 254),
+                "ext z2.b, z2.b, z10.b, #254");
+  COMPARE_MACRO(Ext(z2.VnB(), z2.VnB(), z10.VnB(), 255),
+                "ext z2.b, z2.b, z10.b, #255");
+  COMPARE_MACRO(Ext(z2.VnB(), z4.VnB(), z10.VnB(), 127),
+                "movprfx z2, z4\n"
+                "ext z2.b, z2.b, z10.b, #127");
+  COMPARE_MACRO(Ext(z2.VnB(), z12.VnB(), z2.VnB(), 2),
+                "movprfx z31, z12\n"
+                "ext z31.b, z31.b, z2.b, #2\n"
+                "mov z2.d, z31.d");
+  CLEANUP();
+}
+
+TEST(sve_permute_vector_interleaving) {
+  SETUP();
+
+  COMPARE_PREFIX(trn1(z25.VnB(), z31.VnB(), z17.VnB()),
+                 "trn1 z25.b, z31.b, z17.b");
+  COMPARE_PREFIX(trn1(z25.VnH(), z31.VnH(), z17.VnH()),
+                 "trn1 z25.h, z31.h, z17.h");
+  COMPARE_PREFIX(trn1(z25.VnS(), z31.VnS(), z17.VnS()),
+                 "trn1 z25.s, z31.s, z17.s");
+  COMPARE_PREFIX(trn1(z25.VnD(), z31.VnD(), z17.VnD()),
+                 "trn1 z25.d, z31.d, z17.d");
+  COMPARE_PREFIX(trn2(z23.VnB(), z19.VnB(), z5.VnB()),
+                 "trn2 z23.b, z19.b, z5.b");
+  COMPARE_PREFIX(trn2(z23.VnH(), z19.VnH(), z5.VnH()),
+                 "trn2 z23.h, z19.h, z5.h");
+  COMPARE_PREFIX(trn2(z23.VnS(), z19.VnS(), z5.VnS()),
+                 "trn2 z23.s, z19.s, z5.s");
+  COMPARE_PREFIX(trn2(z23.VnD(), z19.VnD(), z5.VnD()),
+                 "trn2 z23.d, z19.d, z5.d");
+  COMPARE_PREFIX(uzp1(z3.VnB(), z27.VnB(), z10.VnB()),
+                 "uzp1 z3.b, z27.b, z10.b");
+  COMPARE_PREFIX(uzp1(z3.VnH(), z27.VnH(), z10.VnH()),
+                 "uzp1 z3.h, z27.h, z10.h");
+  COMPARE_PREFIX(uzp1(z3.VnS(), z27.VnS(), z10.VnS()),
+                 "uzp1 z3.s, z27.s, z10.s");
+  COMPARE_PREFIX(uzp1(z3.VnD(), z27.VnD(), z10.VnD()),
+                 "uzp1 z3.d, z27.d, z10.d");
+  COMPARE_PREFIX(uzp2(z22.VnB(), z26.VnB(), z15.VnB()),
+                 "uzp2 z22.b, z26.b, z15.b");
+  COMPARE_PREFIX(uzp2(z22.VnH(), z26.VnH(), z15.VnH()),
+                 "uzp2 z22.h, z26.h, z15.h");
+  COMPARE_PREFIX(uzp2(z22.VnS(), z26.VnS(), z15.VnS()),
+                 "uzp2 z22.s, z26.s, z15.s");
+  COMPARE_PREFIX(uzp2(z22.VnD(), z26.VnD(), z15.VnD()),
+                 "uzp2 z22.d, z26.d, z15.d");
+  COMPARE_PREFIX(zip1(z31.VnB(), z2.VnB(), z20.VnB()),
+                 "zip1 z31.b, z2.b, z20.b");
+  COMPARE_PREFIX(zip1(z31.VnH(), z2.VnH(), z20.VnH()),
+                 "zip1 z31.h, z2.h, z20.h");
+  COMPARE_PREFIX(zip1(z31.VnS(), z2.VnS(), z20.VnS()),
+                 "zip1 z31.s, z2.s, z20.s");
+  COMPARE_PREFIX(zip1(z31.VnD(), z2.VnD(), z20.VnD()),
+                 "zip1 z31.d, z2.d, z20.d");
+  COMPARE_PREFIX(zip2(z15.VnB(), z23.VnB(), z12.VnB()),
+                 "zip2 z15.b, z23.b, z12.b");
+  COMPARE_PREFIX(zip2(z15.VnH(), z23.VnH(), z12.VnH()),
+                 "zip2 z15.h, z23.h, z12.h");
+  COMPARE_PREFIX(zip2(z15.VnS(), z23.VnS(), z12.VnS()),
+                 "zip2 z15.s, z23.s, z12.s");
+  COMPARE_PREFIX(zip2(z15.VnD(), z23.VnD(), z12.VnD()),
+                 "zip2 z15.d, z23.d, z12.d");
+
+  CLEANUP();
+}
+
+TEST(sve_cpy_reg) {
+  SETUP();
+
+  COMPARE_PREFIX(cpy(z1.VnB(), p2.Merging(), wsp), "mov z1.b, p2/m, wsp");
+  COMPARE_PREFIX(cpy(z2.VnH(), p6.Merging(), w3), "mov z2.h, p6/m, w3");
+  COMPARE_PREFIX(cpy(z3.VnS(), p7.Merging(), x5), "mov z3.s, p7/m, w5");
+  COMPARE_PREFIX(cpy(z4.VnD(), p7.Merging(), x30), "mov z4.d, p7/m, x30");
+  COMPARE_PREFIX(cpy(z5.VnD(), p7.Merging(), sp), "mov z5.d, p7/m, sp");
+
+  COMPARE_PREFIX(cpy(z27.VnB(), p3.Merging(), b23), "mov z27.b, p3/m, b23");
+  COMPARE_PREFIX(cpy(z27.VnH(), p3.Merging(), h23), "mov z27.h, p3/m, h23");
+  COMPARE_PREFIX(cpy(z27.VnS(), p3.Merging(), s23), "mov z27.s, p3/m, s23");
+  COMPARE_PREFIX(cpy(z27.VnD(), p3.Merging(), d23), "mov z27.d, p3/m, d23");
+
+  COMPARE_PREFIX(mov(z1.VnB(), p2.Merging(), wsp), "mov z1.b, p2/m, wsp");
+  COMPARE_PREFIX(mov(z4.VnD(), p7.Merging(), x30), "mov z4.d, p7/m, x30");
+  COMPARE_PREFIX(mov(z5.VnD(), p7.Merging(), sp), "mov z5.d, p7/m, sp");
+  COMPARE_PREFIX(mov(z27.VnB(), p3.Merging(), b23), "mov z27.b, p3/m, b23");
+  COMPARE_PREFIX(mov(z27.VnD(), p3.Merging(), d23), "mov z27.d, p3/m, d23");
+
+  COMPARE_MACRO(Mov(z1.VnB(), p2.Merging(), wsp), "mov z1.b, p2/m, wsp");
+  COMPARE_MACRO(Mov(z4.VnD(), p7.Merging(), x30), "mov z4.d, p7/m, x30");
+  COMPARE_MACRO(Mov(z5.VnD(), p7.Merging(), sp), "mov z5.d, p7/m, sp");
+  COMPARE_MACRO(Mov(z27.VnB(), p3.Merging(), b23), "mov z27.b, p3/m, b23");
+  COMPARE_MACRO(Mov(z27.VnD(), p3.Merging(), d23), "mov z27.d, p3/m, d23");
+
+  CLEANUP();
+}
+
+TEST(sve_permute_vector_predicated) {
+  SETUP();
+
+  COMPARE_PREFIX(compact(z13.VnS(), p7, z1.VnS()), "compact z13.s, p7, z1.s");
+  COMPARE_PREFIX(compact(z13.VnD(), p7, z1.VnD()), "compact z13.d, p7, z1.d");
+  COMPARE_PREFIX(splice(z7.VnB(), p6, z7.VnB(), z2.VnB()),
+                 "splice z7.b, p6, z7.b, z2.b");
+  COMPARE_PREFIX(splice(z7.VnH(), p6, z7.VnH(), z2.VnH()),
+                 "splice z7.h, p6, z7.h, z2.h");
+  COMPARE_PREFIX(splice(z7.VnS(), p6, z7.VnS(), z2.VnS()),
+                 "splice z7.s, p6, z7.s, z2.s");
+  COMPARE_PREFIX(splice(z7.VnD(), p6, z7.VnD(), z2.VnD()),
+                 "splice z7.d, p6, z7.d, z2.d");
+
+  COMPARE_MACRO(Splice(z0.VnB(), p1, z2.VnB(), z3.VnB()),
+                "movprfx z0, z2\n"
+                "splice z0.b, p1, z0.b, z3.b");
+  COMPARE_MACRO(Splice(z0.VnH(), p1, z2.VnH(), z0.VnH()),
+                "movprfx z31, z2\n"
+                "splice z31.h, p1, z31.h, z0.h\n"
+                "mov z0.d, z31.d");
+
+  COMPARE_PREFIX(clasta(z4.VnB(), p2, z4.VnB(), z12.VnB()),
+                 "clasta z4.b, p2, z4.b, z12.b");
+  COMPARE_PREFIX(clasta(z4.VnH(), p2, z4.VnH(), z12.VnH()),
+                 "clasta z4.h, p2, z4.h, z12.h");
+  COMPARE_PREFIX(clasta(z4.VnS(), p2, z4.VnS(), z12.VnS()),
+                 "clasta z4.s, p2, z4.s, z12.s");
+  COMPARE_PREFIX(clasta(z4.VnD(), p2, z4.VnD(), z12.VnD()),
+                 "clasta z4.d, p2, z4.d, z12.d");
+  COMPARE_PREFIX(clastb(z29.VnB(), p7, z29.VnB(), z26.VnB()),
+                 "clastb z29.b, p7, z29.b, z26.b");
+  COMPARE_PREFIX(clastb(z29.VnH(), p7, z29.VnH(), z26.VnH()),
+                 "clastb z29.h, p7, z29.h, z26.h");
+  COMPARE_PREFIX(clastb(z29.VnS(), p7, z29.VnS(), z26.VnS()),
+                 "clastb z29.s, p7, z29.s, z26.s");
+  COMPARE_PREFIX(clastb(z29.VnD(), p7, z29.VnD(), z26.VnD()),
+                 "clastb z29.d, p7, z29.d, z26.d");
+
+  COMPARE_MACRO(Clasta(z5.VnD(), p2, z4.VnD(), z12.VnD()),
+                "movprfx z5, z4\n"
+                "clasta z5.d, p2, z5.d, z12.d");
+  COMPARE_MACRO(Clastb(z30.VnD(), p7, z29.VnD(), z26.VnD()),
+                "movprfx z30, z29\n"
+                "clastb z30.d, p7, z30.d, z26.d");
+  COMPARE_MACRO(Clasta(z9.VnH(), p3, z8.VnH(), z9.VnH()),
+                "movprfx z31, z8\n"
+                "clasta z31.h, p3, z31.h, z9.h\n"
+                "mov z9.d, z31.d");
+  COMPARE_MACRO(Clastb(z1.VnS(), p1, z1.VnS(), z1.VnS()),
+                "clastb z1.s, p1, z1.s, z1.s");
+
+  COMPARE_PREFIX(clasta(w6, p0, w6, z13.VnB()), "clasta w6, p0, w6, z13.b");
+  COMPARE_PREFIX(clasta(w6, p0, w6, z13.VnH()), "clasta w6, p0, w6, z13.h");
+  COMPARE_PREFIX(clasta(w6, p0, w6, z13.VnS()), "clasta w6, p0, w6, z13.s");
+  COMPARE_PREFIX(clasta(x6, p0, x6, z13.VnD()), "clasta x6, p0, x6, z13.d");
+  COMPARE_PREFIX(clastb(w21, p2, w21, z27.VnB()), "clastb w21, p2, w21, z27.b");
+  COMPARE_PREFIX(clastb(w21, p2, w21, z27.VnH()), "clastb w21, p2, w21, z27.h");
+  COMPARE_PREFIX(clastb(w21, p2, w21, z27.VnS()), "clastb w21, p2, w21, z27.s");
+  COMPARE_PREFIX(clastb(x21, p2, x21, z27.VnD()), "clastb x21, p2, x21, z27.d");
+
+  COMPARE_PREFIX(clasta(b8, p6, b8, z7.VnB()), "clasta b8, p6, b8, z7.b");
+  COMPARE_PREFIX(clasta(h8, p6, h8, z7.VnH()), "clasta h8, p6, h8, z7.h");
+  COMPARE_PREFIX(clasta(s8, p6, s8, z7.VnS()), "clasta s8, p6, s8, z7.s");
+  COMPARE_PREFIX(clasta(d8, p6, d8, z7.VnD()), "clasta d8, p6, d8, z7.d");
+  COMPARE_PREFIX(clastb(b17, p0, b17, z19.VnB()), "clastb b17, p0, b17, z19.b");
+  COMPARE_PREFIX(clastb(h17, p0, h17, z19.VnH()), "clastb h17, p0, h17, z19.h");
+  COMPARE_PREFIX(clastb(s17, p0, s17, z19.VnS()), "clastb s17, p0, s17, z19.s");
+  COMPARE_PREFIX(clastb(d17, p0, d17, z19.VnD()), "clastb d17, p0, d17, z19.d");
+
+  COMPARE_PREFIX(lasta(w15, p3, z3.VnB()), "lasta w15, p3, z3.b");
+  COMPARE_PREFIX(lasta(w15, p3, z3.VnH()), "lasta w15, p3, z3.h");
+  COMPARE_PREFIX(lasta(w15, p3, z3.VnS()), "lasta w15, p3, z3.s");
+  COMPARE_PREFIX(lasta(x15, p3, z3.VnD()), "lasta x15, p3, z3.d");
+  COMPARE_PREFIX(lasta(b30, p4, z24.VnB()), "lasta b30, p4, z24.b");
+  COMPARE_PREFIX(lasta(h30, p4, z24.VnH()), "lasta h30, p4, z24.h");
+  COMPARE_PREFIX(lasta(s30, p4, z24.VnS()), "lasta s30, p4, z24.s");
+  COMPARE_PREFIX(lasta(d30, p4, z24.VnD()), "lasta d30, p4, z24.d");
+
+  COMPARE_PREFIX(lastb(w9, p2, z16.VnB()), "lastb w9, p2, z16.b");
+  COMPARE_PREFIX(lastb(w9, p2, z16.VnH()), "lastb w9, p2, z16.h");
+  COMPARE_PREFIX(lastb(w9, p2, z16.VnS()), "lastb w9, p2, z16.s");
+  COMPARE_PREFIX(lastb(x9, p2, z16.VnD()), "lastb x9, p2, z16.d");
+  COMPARE_PREFIX(lastb(b14, p5, z2.VnB()), "lastb b14, p5, z2.b");
+  COMPARE_PREFIX(lastb(h14, p5, z2.VnH()), "lastb h14, p5, z2.h");
+  COMPARE_PREFIX(lastb(s14, p5, z2.VnS()), "lastb s14, p5, z2.s");
+  COMPARE_PREFIX(lastb(d14, p5, z2.VnD()), "lastb d14, p5, z2.d");
+
+  CLEANUP();
+}
+
+TEST(sve_reverse) {
+  SETUP();
+
+  COMPARE_MACRO(Rbit(z22.VnB(), p2.Merging(), z24.VnB()),
+                "rbit z22.b, p2/m, z24.b");
+  COMPARE_MACRO(Rbit(z22.VnH(), p2.Merging(), z24.VnH()),
+                "rbit z22.h, p2/m, z24.h");
+  COMPARE_MACRO(Rbit(z22.VnS(), p2.Merging(), z24.VnS()),
+                "rbit z22.s, p2/m, z24.s");
+  COMPARE_MACRO(Rbit(z22.VnD(), p2.Merging(), z24.VnD()),
+                "rbit z22.d, p2/m, z24.d");
+  COMPARE_MACRO(Revb(z14.VnH(), p7.Merging(), z25.VnH()),
+                "revb z14.h, p7/m, z25.h");
+  COMPARE_MACRO(Revb(z14.VnS(), p7.Merging(), z25.VnS()),
+                "revb z14.s, p7/m, z25.s");
+  COMPARE_MACRO(Revb(z14.VnD(), p7.Merging(), z25.VnD()),
+                "revb z14.d, p7/m, z25.d");
+  COMPARE_MACRO(Revh(z16.VnS(), p2.Merging(), z4.VnS()),
+                "revh z16.s, p2/m, z4.s");
+  COMPARE_MACRO(Revh(z16.VnD(), p2.Merging(), z4.VnD()),
+                "revh z16.d, p2/m, z4.d");
+  COMPARE_MACRO(Revw(z26.VnD(), p5.Merging(), z10.VnD()),
+                "revw z26.d, p5/m, z10.d");
+
+  CLEANUP();
+}
+
+TEST(sve_permute_vector_unpredicated) {
+  SETUP();
+
+  COMPARE_PREFIX(dup(z4.VnB(), w7), "mov z4.b, w7");
+  COMPARE_PREFIX(dup(z5.VnH(), w6), "mov z5.h, w6");
+  COMPARE_PREFIX(dup(z6.VnS(), sp), "mov z6.s, wsp");
+  COMPARE_PREFIX(dup(z7.VnD(), x4), "mov z7.d, x4");
+  COMPARE_PREFIX(dup(z25.VnQ(), z28.VnQ(), 2), "mov z25.q, z28.q[2]");
+  COMPARE_PREFIX(dup(z26.VnH(), z12.VnH(), 0), "mov z26.h, h12");
+
+  COMPARE_PREFIX(mov(z4.VnB(), w7), "mov z4.b, w7");
+  COMPARE_PREFIX(mov(z5.VnH(), w6), "mov z5.h, w6");
+  COMPARE_PREFIX(mov(z6.VnS(), sp), "mov z6.s, wsp");
+  COMPARE_PREFIX(mov(z7.VnD(), x4), "mov z7.d, x4");
+  COMPARE_PREFIX(mov(z25.VnQ(), z28.VnQ(), 2), "mov z25.q, z28.q[2]");
+  COMPARE_PREFIX(mov(z0.VnS(), s1), "mov z0.s, s1");
+
+  COMPARE_MACRO(Mov(z7.VnD(), x4), "mov z7.d, x4");
+  COMPARE_MACRO(Mov(z25.VnQ(), z28.VnQ(), 2), "mov z25.q, z28.q[2]");
+  COMPARE_MACRO(Mov(z2.VnB(), b13), "mov z2.b, b13");
+  COMPARE_MACRO(Mov(z31.VnQ(), q31), "mov z31.q, q31");
+
+  // Test dup with reserved tsz field.
+  COMPARE_PREFIX(dci(0x05202000), "unimplemented");
+
+  COMPARE(insr(z15.VnB(), w13), "insr z15.b, w13");
+  COMPARE(insr(z16.VnH(), w14), "insr z16.h, w14");
+  COMPARE(insr(z17.VnS(), w15), "insr z17.s, w15");
+  COMPARE(insr(z18.VnD(), x16), "insr z18.d, x16");
+  COMPARE(insr(z5.VnB(), b3), "insr z5.b, b3");
+  COMPARE(insr(z6.VnH(), h15), "insr z6.h, h15");
+  COMPARE(insr(z7.VnS(), s22), "insr z7.s, s22");
+  COMPARE(insr(z8.VnD(), d30), "insr z8.d, d30");
+  COMPARE_PREFIX(rev(z13.VnB(), z10.VnB()), "rev z13.b, z10.b");
+  COMPARE_PREFIX(rev(z14.VnH(), z10.VnH()), "rev z14.h, z10.h");
+  COMPARE_PREFIX(rev(z15.VnS(), z10.VnS()), "rev z15.s, z10.s");
+  COMPARE_PREFIX(rev(z16.VnD(), z10.VnD()), "rev z16.d, z10.d");
+  COMPARE_PREFIX(sunpkhi(z10.VnH(), z11.VnB()), "sunpkhi z10.h, z11.b");
+  COMPARE_PREFIX(sunpkhi(z11.VnS(), z11.VnH()), "sunpkhi z11.s, z11.h");
+  COMPARE_PREFIX(sunpkhi(z12.VnD(), z11.VnS()), "sunpkhi z12.d, z11.s");
+  COMPARE_PREFIX(sunpklo(z20.VnH(), z12.VnB()), "sunpklo z20.h, z12.b");
+  COMPARE_PREFIX(sunpklo(z21.VnS(), z12.VnH()), "sunpklo z21.s, z12.h");
+  COMPARE_PREFIX(sunpklo(z22.VnD(), z12.VnS()), "sunpklo z22.d, z12.s");
+  COMPARE_PREFIX(uunpkhi(z17.VnH(), z14.VnB()), "uunpkhi z17.h, z14.b");
+  COMPARE_PREFIX(uunpkhi(z18.VnS(), z14.VnH()), "uunpkhi z18.s, z14.h");
+  COMPARE_PREFIX(uunpkhi(z19.VnD(), z14.VnS()), "uunpkhi z19.d, z14.s");
+  COMPARE_PREFIX(uunpklo(z27.VnH(), z6.VnB()), "uunpklo z27.h, z6.b");
+  COMPARE_PREFIX(uunpklo(z28.VnS(), z6.VnH()), "uunpklo z28.s, z6.h");
+  COMPARE_PREFIX(uunpklo(z29.VnD(), z6.VnS()), "uunpklo z29.d, z6.s");
+  COMPARE_PREFIX(tbl(z24.VnB(), z29.VnB(), z0.VnB()),
+                 "tbl z24.b, {z29.b}, z0.b");
+  COMPARE_PREFIX(tbl(z25.VnH(), z29.VnH(), z1.VnH()),
+                 "tbl z25.h, {z29.h}, z1.h");
+  COMPARE_PREFIX(tbl(z26.VnS(), z29.VnS(), z2.VnS()),
+                 "tbl z26.s, {z29.s}, z2.s");
+  COMPARE_PREFIX(tbl(z27.VnD(), z29.VnD(), z3.VnD()),
+                 "tbl z27.d, {z29.d}, z3.d");
+
+  CLEANUP();
+}
+
+TEST(sve_predicate_count) {
+  SETUP();
+
+  COMPARE_PREFIX(cntp(x9, p1, p0.VnB()), "cntp x9, p1, p0.b");
+  COMPARE_PREFIX(cntp(x10, p12, p1.VnH()), "cntp x10, p12, p1.h");
+  COMPARE_PREFIX(cntp(x11, p13, p14.VnS()), "cntp x11, p13, p14.s");
+  COMPARE_PREFIX(cntp(x12, p4, p15.VnD()), "cntp x12, p4, p15.d");
+
+  COMPARE_MACRO(Cntp(x0, p1, p2.VnB()), "cntp x0, p1, p2.b");
+  COMPARE_MACRO(Cntp(w10, p11, p12.VnH()), "cntp x10, p11, p12.h");
+
+  CLEANUP();
+}
+
+TEST(sve_predicate_logical_op) {
+  SETUP();
+
+  COMPARE_PREFIX(ands(p13.VnB(), p9.Zeroing(), p5.VnB(), p15.VnB()),
+                 "ands p13.b, p9/z, p5.b, p15.b");
+  COMPARE_PREFIX(and_(p9.VnB(), p3.Zeroing(), p0.VnB(), p14.VnB()),
+                 "and p9.b, p3/z, p0.b, p14.b");
+  COMPARE_PREFIX(bics(p8.VnB(), p5.Zeroing(), p3.VnB(), p1.VnB()),
+                 "bics p8.b, p5/z, p3.b, p1.b");
+  COMPARE_PREFIX(bic(p5.VnB(), p5.Zeroing(), p9.VnB(), p9.VnB()),
+                 "bic p5.b, p5/z, p9.b, p9.b");
+  COMPARE_PREFIX(eors(p11.VnB(), p1.Zeroing(), p1.VnB(), p2.VnB()),
+                 "eors p11.b, p1/z, p1.b, p2.b");
+  COMPARE_PREFIX(eor(p8.VnB(), p6.Zeroing(), p1.VnB(), p11.VnB()),
+                 "eor p8.b, p6/z, p1.b, p11.b");
+  COMPARE_PREFIX(nands(p13.VnB(), p0.Zeroing(), p9.VnB(), p4.VnB()),
+                 "nands p13.b, p0/z, p9.b, p4.b");
+  COMPARE_PREFIX(nand(p7.VnB(), p7.Zeroing(), p15.VnB(), p2.VnB()),
+                 "nand p7.b, p7/z, p15.b, p2.b");
+  COMPARE_PREFIX(nors(p8.VnB(), p8.Zeroing(), p12.VnB(), p11.VnB()),
+                 "nors p8.b, p8/z, p12.b, p11.b");
+  COMPARE_PREFIX(nor(p3.VnB(), p6.Zeroing(), p15.VnB(), p12.VnB()),
+                 "nor p3.b, p6/z, p15.b, p12.b");
+  COMPARE_PREFIX(orns(p10.VnB(), p11.Zeroing(), p0.VnB(), p15.VnB()),
+                 "orns p10.b, p11/z, p0.b, p15.b");
+  COMPARE_PREFIX(orn(p0.VnB(), p1.Zeroing(), p7.VnB(), p4.VnB()),
+                 "orn p0.b, p1/z, p7.b, p4.b");
+  COMPARE_PREFIX(orrs(p14.VnB(), p6.Zeroing(), p1.VnB(), p5.VnB()),
+                 "orrs p14.b, p6/z, p1.b, p5.b");
+  COMPARE_PREFIX(orr(p13.VnB(), p7.Zeroing(), p10.VnB(), p4.VnB()),
+                 "orr p13.b, p7/z, p10.b, p4.b");
+  COMPARE_PREFIX(sel(p9.VnB(), p15, p15.VnB(), p7.VnB()),
+                 "sel p9.b, p15, p15.b, p7.b");
+
+  // Aliases.
+  COMPARE_PREFIX(eor(p7.VnB(), p6.Zeroing(), p1.VnB(), p6.VnB()),
+                 "not p7.b, p6/z, p1.b");
+  COMPARE_PREFIX(not_(p7.VnB(), p6.Zeroing(), p1.VnB()),
+                 "not p7.b, p6/z, p1.b");
+  COMPARE_PREFIX(eors(p6.VnB(), p5.Zeroing(), p2.VnB(), p5.VnB()),
+                 "nots p6.b, p5/z, p2.b");
+  COMPARE_PREFIX(nots(p6.VnB(), p5.Zeroing(), p2.VnB()),
+                 "nots p6.b, p5/z, p2.b");
+  COMPARE_PREFIX(ands(p5.VnB(), p4.Zeroing(), p3.VnB(), p3.VnB()),
+                 "movs p5.b, p4/z, p3.b");
+  COMPARE_PREFIX(movs(p5.VnB(), p4.Zeroing(), p3.VnB()),
+                 "movs p5.b, p4/z, p3.b");
+  COMPARE_PREFIX(and_(p5.VnB(), p4.Zeroing(), p3.VnB(), p3.VnB()),
+                 "mov p5.b, p4/z, p3.b");
+  COMPARE_PREFIX(mov(p5.VnB(), p4.Zeroing(), p3.VnB()), "mov p5.b, p4/z, p3.b");
+  COMPARE_PREFIX(orrs(p4.VnB(), p3.Zeroing(), p3.VnB(), p3.VnB()),
+                 "movs p4.b, p3.b");
+  COMPARE_PREFIX(movs(p4.VnB(), p3.VnB()), "movs p4.b, p3.b");
+  COMPARE_PREFIX(orr(p4.VnB(), p3.Zeroing(), p3.VnB(), p3.VnB()),
+                 "mov p4.b, p3.b");
+  COMPARE_PREFIX(mov(p4.VnB(), p3.VnB()), "mov p4.b, p3.b");
+  COMPARE_PREFIX(sel(p3.VnB(), p2, p4.VnB(), p3.VnB()), "mov p3.b, p2/m, p4.b");
+  COMPARE_PREFIX(mov(p3.VnB(), p2.Merging(), p4.VnB()), "mov p3.b, p2/m, p4.b");
+
+  COMPARE_MACRO(Not(p7.VnB(), p6.Zeroing(), p1.VnB()), "not p7.b, p6/z, p1.b");
+  COMPARE_MACRO(Nots(p6.VnB(), p5.Zeroing(), p2.VnB()),
+                "nots p6.b, p5/z, p2.b");
+  COMPARE_MACRO(Movs(p5.VnB(), p4.Zeroing(), p3.VnB()),
+                "movs p5.b, p4/z, p3.b");
+  COMPARE_MACRO(Mov(p5.VnB(), p4.Zeroing(), p3.VnB()), "mov p5.b, p4/z, p3.b");
+  COMPARE_MACRO(Movs(p4.VnB(), p3.VnB()), "movs p4.b, p3.b");
+  COMPARE_MACRO(Mov(p4, p3), "mov p4.b, p3.b");
+  COMPARE_MACRO(Mov(p3.VnB(), p2.Merging(), p4.VnB()), "mov p3.b, p2/m, p4.b");
+
+  CLEANUP();
+}
+
+TEST(sve_predicate_first_active) {
+  SETUP();
+
+  COMPARE_PREFIX(pfirst(p0.VnB(), p7, p0.VnB()), "pfirst p0.b, p7, p0.b");
+  COMPARE_PREFIX(pfirst(p7.VnB(), p0, p7.VnB()), "pfirst p7.b, p0, p7.b");
+
+  COMPARE_MACRO(Pfirst(p1.VnB(), p2, p1.VnB()), "pfirst p1.b, p2, p1.b");
+  COMPARE_MACRO(Pfirst(p3.VnB(), p4, p5.VnB()),
+                "mov p3.b, p5.b\n"
+                "pfirst p3.b, p4, p3.b");
+
+  {
+    UseScratchRegisterScope temps(&masm);
+    temps.Include(p7, p15);
+    COMPARE_MACRO(Pfirst(p6.VnB(), p6, p0.VnB()),
+                  "mov p15.b, p6.b\n"
+                  "mov p6.b, p0.b\n"
+                  "pfirst p6.b, p15, p6.b");
+  }
+
+  CLEANUP();
+}
+
+TEST(sve_predicate_next_active) {
+  SETUP();
+
+  COMPARE_PREFIX(pnext(p0.VnB(), p8, p0.VnB()), "pnext p0.b, p8, p0.b");
+  COMPARE_PREFIX(pnext(p1.VnH(), p9, p1.VnH()), "pnext p1.h, p9, p1.h");
+  COMPARE_PREFIX(pnext(p2.VnS(), p10, p2.VnS()), "pnext p2.s, p10, p2.s");
+  COMPARE_PREFIX(pnext(p3.VnD(), p11, p3.VnD()), "pnext p3.d, p11, p3.d");
+
+  COMPARE_PREFIX(pnext(p12.VnB(), p4, p12.VnB()), "pnext p12.b, p4, p12.b");
+  COMPARE_PREFIX(pnext(p13.VnH(), p5, p13.VnH()), "pnext p13.h, p5, p13.h");
+  COMPARE_PREFIX(pnext(p14.VnS(), p6, p14.VnS()), "pnext p14.s, p6, p14.s");
+  COMPARE_PREFIX(pnext(p15.VnD(), p7, p15.VnD()), "pnext p15.d, p7, p15.d");
+
+  COMPARE_MACRO(Pnext(p5.VnB(), p9, p5.VnB()), "pnext p5.b, p9, p5.b");
+  COMPARE_MACRO(Pnext(p6.VnH(), p8, p6.VnH()), "pnext p6.h, p8, p6.h");
+  COMPARE_MACRO(Pnext(p7.VnS(), p5, p7.VnS()), "pnext p7.s, p5, p7.s");
+  COMPARE_MACRO(Pnext(p8.VnD(), p6, p8.VnD()), "pnext p8.d, p6, p8.d");
+
+  COMPARE_MACRO(Pnext(p6.VnB(), p4, p5.VnB()),
+                "mov p6.b, p5.b\n"
+                "pnext p6.b, p4, p6.b");
+  COMPARE_MACRO(Pnext(p7.VnH(), p3, p8.VnH()),
+                "mov p7.b, p8.b\n"
+                "pnext p7.h, p3, p7.h");
+  COMPARE_MACRO(Pnext(p8.VnS(), p2, p9.VnS()),
+                "mov p8.b, p9.b\n"
+                "pnext p8.s, p2, p8.s");
+  COMPARE_MACRO(Pnext(p9.VnD(), p1, p10.VnD()),
+                "mov p9.b, p10.b\n"
+                "pnext p9.d, p1, p9.d");
+
+  {
+    UseScratchRegisterScope temps(&masm);
+    temps.Include(p7, p8);
+    COMPARE_MACRO(Pnext(p6.VnB(), p6, p0.VnB()),
+                  "mov p8.b, p6.b\n"
+                  "mov p6.b, p0.b\n"
+                  "pnext p6.b, p8, p6.b");
+    COMPARE_MACRO(Pnext(p7.VnH(), p7, p1.VnH()),
+                  "mov p8.b, p7.b\n"
+                  "mov p7.b, p1.b\n"
+                  "pnext p7.h, p8, p7.h");
+    COMPARE_MACRO(Pnext(p10.VnS(), p10, p2.VnS()),
+                  "mov p8.b, p10.b\n"
+                  "mov p10.b, p2.b\n"
+                  "pnext p10.s, p8, p10.s");
+    COMPARE_MACRO(Pnext(p11.VnD(), p11, p3.VnD()),
+                  "mov p8.b, p11.b\n"
+                  "mov p11.b, p3.b\n"
+                  "pnext p11.d, p8, p11.d");
+  }
+
+  CLEANUP();
+}
+
+TEST(sve_predicate_initialize) {
+  SETUP();
+
+  // Basic forms.
+  COMPARE_PREFIX(ptrue(p0.VnB(), SVE_POW2), "ptrue p0.b, pow2");
+  COMPARE_PREFIX(ptrue(p1.VnH(), SVE_VL1), "ptrue p1.h, vl1");
+  COMPARE_PREFIX(ptrue(p2.VnS(), SVE_VL8), "ptrue p2.s, vl8");
+  COMPARE_PREFIX(ptrue(p3.VnD(), SVE_VL16), "ptrue p3.d, vl16");
+  COMPARE_PREFIX(ptrue(p4.VnB(), SVE_VL256), "ptrue p4.b, vl256");
+  COMPARE_PREFIX(ptrue(p5.VnH(), SVE_MUL3), "ptrue p5.h, mul3");
+  COMPARE_PREFIX(ptrue(p6.VnS(), SVE_MUL4), "ptrue p6.s, mul4");
+  COMPARE_PREFIX(ptrue(p7.VnD(), SVE_ALL), "ptrue p7.d");
+
+  COMPARE_PREFIX(ptrues(p8.VnB(), SVE_ALL), "ptrues p8.b");
+  COMPARE_PREFIX(ptrues(p9.VnH(), SVE_MUL4), "ptrues p9.h, mul4");
+  COMPARE_PREFIX(ptrues(p10.VnS(), SVE_MUL3), "ptrues p10.s, mul3");
+  COMPARE_PREFIX(ptrues(p11.VnD(), SVE_VL256), "ptrues p11.d, vl256");
+  COMPARE_PREFIX(ptrues(p12.VnB(), SVE_VL16), "ptrues p12.b, vl16");
+  COMPARE_PREFIX(ptrues(p13.VnH(), SVE_VL8), "ptrues p13.h, vl8");
+  COMPARE_PREFIX(ptrues(p14.VnS(), SVE_VL1), "ptrues p14.s, vl1");
+  COMPARE_PREFIX(ptrues(p15.VnD(), SVE_POW2), "ptrues p15.d, pow2");
+
+  // The Assembler supports arbitrary immediates.
+  COMPARE_PREFIX(ptrue(p7.VnS(), 0xd), "ptrue p7.s, vl256");
+  COMPARE_PREFIX(ptrue(p8.VnD(), 0xe), "ptrue p8.d, #0xe");
+  COMPARE_PREFIX(ptrue(p9.VnB(), 0x15), "ptrue p9.b, #0x15");
+  COMPARE_PREFIX(ptrue(p10.VnH(), 0x19), "ptrue p10.h, #0x19");
+  COMPARE_PREFIX(ptrue(p11.VnS(), 0x1a), "ptrue p11.s, #0x1a");
+  COMPARE_PREFIX(ptrue(p12.VnD(), 0x1c), "ptrue p12.d, #0x1c");
+  COMPARE_PREFIX(ptrue(p13.VnB(), 0x1d), "ptrue p13.b, mul4");
+
+  COMPARE_PREFIX(ptrues(p14.VnS(), 0xd), "ptrues p14.s, vl256");
+  COMPARE_PREFIX(ptrues(p15.VnD(), 0xe), "ptrues p15.d, #0xe");
+  COMPARE_PREFIX(ptrues(p0.VnB(), 0x15), "ptrues p0.b, #0x15");
+  COMPARE_PREFIX(ptrues(p1.VnH(), 0x19), "ptrues p1.h, #0x19");
+  COMPARE_PREFIX(ptrues(p2.VnS(), 0x1a), "ptrues p2.s, #0x1a");
+  COMPARE_PREFIX(ptrues(p3.VnD(), 0x1c), "ptrues p3.d, #0x1c");
+  COMPARE_PREFIX(ptrues(p4.VnB(), 0x1d), "ptrues p4.b, mul4");
+
+  // SVE_ALL is the default.
+  COMPARE_PREFIX(ptrue(p15.VnS()), "ptrue p15.s");
+  COMPARE_PREFIX(ptrues(p0.VnS()), "ptrues p0.s");
+
+  // The MacroAssembler provides a `FlagsUpdate` argument.
+  COMPARE_MACRO(Ptrue(p0.VnB(), SVE_MUL3), "ptrue p0.b, mul3");
+  COMPARE_MACRO(Ptrues(p1.VnH(), SVE_MUL4), "ptrues p1.h, mul4");
+  COMPARE_MACRO(Ptrue(p2.VnS(), SVE_VL32, LeaveFlags), "ptrue p2.s, vl32");
+  COMPARE_MACRO(Ptrue(p3.VnD(), SVE_VL64, SetFlags), "ptrues p3.d, vl64");
+}
+
+TEST(sve_pfalse) {
+  SETUP();
+
+  COMPARE_PREFIX(pfalse(p0.VnB()), "pfalse p0.b");
+  COMPARE_PREFIX(pfalse(p15.VnB()), "pfalse p15.b");
+
+  COMPARE_MACRO(Pfalse(p1.VnB()), "pfalse p1.b");
+  COMPARE_MACRO(Pfalse(p4.VnH()), "pfalse p4.b");
+  COMPARE_MACRO(Pfalse(p9.VnS()), "pfalse p9.b");
+  COMPARE_MACRO(Pfalse(p14.VnD()), "pfalse p14.b");
+}
+
+TEST(sve_ptest) {
+  SETUP();
+
+  COMPARE_PREFIX(ptest(p15, p0.VnB()), "ptest p15, p0.b");
+  COMPARE_PREFIX(ptest(p0, p15.VnB()), "ptest p0, p15.b");
+  COMPARE_PREFIX(ptest(p6, p6.VnB()), "ptest p6, p6.b");
+
+  COMPARE_MACRO(Ptest(p0, p1.VnB()), "ptest p0, p1.b");
+}
+
+TEST(sve_lane_size_relaxing) {
+  SETUP();
+
+  COMPARE_MACRO(Rdffr(p3), "rdffr p3.b");
+  COMPARE_MACRO(Rdffr(p8.VnB()), "rdffr p8.b");
+
+  COMPARE_MACRO(Wrffr(p9), "wrffr p9.b");
+  COMPARE_MACRO(Wrffr(p8.VnB()), "wrffr p8.b");
+
+  COMPARE_MACRO(And(z10, z1, z15), "and z10.d, z1.d, z15.d");
+  COMPARE_MACRO(Bic(z11, z2, z16), "bic z11.d, z2.d, z16.d");
+  COMPARE_MACRO(Eor(z12, z3, z17), "eor z12.d, z3.d, z17.d");
+  COMPARE_MACRO(Orr(z13, z4, z18), "orr z13.d, z4.d, z18.d");
+
+  COMPARE_MACRO(And(z10.VnD(), z1.VnD(), z15.VnD()), "and z10.d, z1.d, z15.d");
+  COMPARE_MACRO(Bic(z11.VnS(), z2.VnS(), z16.VnS()), "bic z11.d, z2.d, z16.d");
+  COMPARE_MACRO(Eor(z12.VnH(), z3.VnH(), z17.VnH()), "eor z12.d, z3.d, z17.d");
+  COMPARE_MACRO(Orr(z13.VnB(), z4.VnB(), z18.VnB()), "orr z13.d, z4.d, z18.d");
+
+  COMPARE_MACRO(Pfalse(p1), "pfalse p1.b");
+
+  CLEANUP();
+}
+
+TEST(sve_read_ffr) {
+  SETUP();
+
+  COMPARE_PREFIX(rdffr(p13.VnB()), "rdffr p13.b");
+  COMPARE_PREFIX(rdffrs(p14.VnB(), p9.Zeroing()), "rdffrs p14.b, p9/z");
+  COMPARE_PREFIX(rdffr(p5.VnB(), p14.Zeroing()), "rdffr p5.b, p14/z");
+
+  CLEANUP();
+}
+
+TEST(sve_propagate_break) {
+  SETUP();
+
+  COMPARE_PREFIX(brkpas(p12.VnB(), p0.Zeroing(), p12.VnB(), p11.VnB()),
+                 "brkpas p12.b, p0/z, p12.b, p11.b");
+  COMPARE_PREFIX(brkpa(p1.VnB(), p2.Zeroing(), p13.VnB(), p8.VnB()),
+                 "brkpa p1.b, p2/z, p13.b, p8.b");
+  COMPARE_PREFIX(brkpbs(p14.VnB(), p1.Zeroing(), p8.VnB(), p3.VnB()),
+                 "brkpbs p14.b, p1/z, p8.b, p3.b");
+  COMPARE_PREFIX(brkpb(p2.VnB(), p5.Zeroing(), p0.VnB(), p14.VnB()),
+                 "brkpb p2.b, p5/z, p0.b, p14.b");
+
+  CLEANUP();
+}
+
+TEST(sve_stack_allocation) {
+  SETUP();
+
+  COMPARE_PREFIX(rdvl(x26, 0), "rdvl x26, #0");
+  COMPARE_PREFIX(rdvl(x27, 31), "rdvl x27, #31");
+  COMPARE_PREFIX(rdvl(x28, -32), "rdvl x28, #-32");
+  COMPARE_PREFIX(rdvl(xzr, 9), "rdvl xzr, #9");
+
+  COMPARE_PREFIX(addvl(x6, x20, 0), "addvl x6, x20, #0");
+  COMPARE_PREFIX(addvl(x7, x21, 31), "addvl x7, x21, #31");
+  COMPARE_PREFIX(addvl(x8, x22, -32), "addvl x8, x22, #-32");
+  COMPARE_PREFIX(addvl(sp, x1, 5), "addvl sp, x1, #5");
+  COMPARE_PREFIX(addvl(x9, sp, -16), "addvl x9, sp, #-16");
+
+  COMPARE_PREFIX(addpl(x20, x6, 0), "addpl x20, x6, #0");
+  COMPARE_PREFIX(addpl(x21, x7, 31), "addpl x21, x7, #31");
+  COMPARE_PREFIX(addpl(x22, x8, -32), "addpl x22, x8, #-32");
+  COMPARE_PREFIX(addpl(sp, x1, 5), "addpl sp, x1, #5");
+  COMPARE_PREFIX(addpl(x9, sp, -16), "addpl x9, sp, #-16");
+
+  CLEANUP();
+}
+
+TEST(sve_rdvl_macro) {
+  SETUP();
+
+  // Encodable cases use rdvl directly.
+  COMPARE_MACRO(Rdvl(x0, 3), "rdvl x0, #3");
+  COMPARE_MACRO(Rdvl(x0, 31), "rdvl x0, #31");
+  COMPARE_MACRO(Rdvl(x0, -32), "rdvl x0, #-32");
+
+  // Unencodable cases fall back on `xn + (VL * multiplier)`.
+  COMPARE_MACRO(Rdvl(x2, 0x1234),
+                "mov x2, #0x1234\n"
+                "rdvl x16, #1\n"
+                "mul x2, x2, x16");
+
+  CLEANUP();
+}
+
+TEST(sve_addvl_macro) {
+  SETUP();
+
+  // Encodable cases use addvl directly.
+  COMPARE_MACRO(Addvl(sp, sp, -3), "addvl sp, sp, #-3");
+  COMPARE_MACRO(Addvl(x0, x1, 8), "addvl x0, x1, #8");
+
+  // If xn is xzr, `Addvl` behaves like `Rdvl`.
+  COMPARE_MACRO(Addvl(x7, xzr, 8), "rdvl x7, #8");
+
+  // Unencodable cases fall back on `xn + (VL * multiplier)`.
+  COMPARE_MACRO(Addvl(x7, x8, 42),
+                "mov x7, #0x2a\n"
+                "rdvl x16, #1\n"
+                "madd x7, x7, x16, x8");
+  COMPARE_MACRO(Addvl(x10, x10, 42),
+                "mov x16, #0x2a\n"
+                "rdvl x17, #1\n"
+                "madd x10, x16, x17, x10");
+  COMPARE_MACRO(Addvl(x10, sp, 42),
+                "mov x10, #0x2a\n"
+                "rdvl x16, #1\n"
+                "mul x10, x10, x16\n"
+                "add x10, sp, x10");
+  COMPARE_MACRO(Addvl(sp, x10, 42),
+                "mov x16, #0x2a\n"
+                "rdvl x17, #1\n"
+                "mul x16, x16, x17\n"
+                "add sp, x10, x16");
+
+  CLEANUP();
+}
+
+TEST(sve_rdpl_macro) {
+  SETUP();
+
+  // There is no `rdpl` instruction. `Rdpl` is implemented as `Addpl` (with
+  // xzr). However, since `addpl` operates on the stack pointer, some special
+  // cases exist.
+
+  // If the multiplier is a multiple of 8, `Rdpl` will pass through to `Rdvl`.
+  COMPARE_MACRO(Rdpl(x0, 0), "rdvl x0, #0");
+  COMPARE_MACRO(Rdpl(x0, 8), "rdvl x0, #1");
+
+  // If the multiplier is encodable with `addpl`, we use that with an
+  // explicitly-zeroed register.
+  COMPARE_MACRO(Rdpl(x1, 7),
+                "mov x1, #0x0\n"
+                "addpl x1, x1, #7");
+  COMPARE_MACRO(Rdpl(x1, -31),
+                "mov x1, #0x0\n"
+                "addpl x1, x1, #-31");
+
+  // All other cases use `Rdvl`, and scale the result.
+  COMPARE_MACRO(Rdpl(x2, 37),
+                "mov x2, #0x25\n"
+                "rdvl x16, #1\n"
+                "mul x2, x2, x16\n"
+                "asr x2, x2, #3");
+
+  CLEANUP();
+}
+
+TEST(sve_addpl_macro) {
+  SETUP();
+
+  // Encodable cases use addpl directly.
+  COMPARE_MACRO(Addpl(x22, x22, -3), "addpl x22, x22, #-3");
+  COMPARE_MACRO(Addpl(x10, x11, 8), "addpl x10, x11, #8");
+  COMPARE_MACRO(Addpl(x7, sp, 31), "addpl x7, sp, #31");
+
+  // Otherwise, if the multiplier is a multiple of 8, `Addpl` will pass through
+  // to `Addvl`.
+  COMPARE_MACRO(Addpl(sp, x0, 48), "addvl sp, x0, #6");
+  COMPARE_MACRO(Addpl(x2, sp, -48), "addvl x2, sp, #-6");
+
+  // If xn is xzr, `Addpl` behaves like `Rdpl`.
+  COMPARE_MACRO(Addpl(x7, xzr, 8), "rdvl x7, #1");
+  COMPARE_MACRO(Addpl(x29, xzr, 13),
+                "mov x29, #0x0\n"
+                "addpl x29, x29, #13");
+
+  // All other cases use `Rdvl`, and scale the result before adding it to `xn`.
+  // Where possible, the scaling `asr` is merged with the `add`.
+  COMPARE_MACRO(Addpl(x7, x8, 123),
+                "mov x7, #0x7b\n"
+                "rdvl x16, #1\n"
+                "mul x7, x7, x16\n"
+                "add x7, x8, x7, asr #3");
+  COMPARE_MACRO(Addpl(x9, x9, 122),
+                "mov x16, #0x7a\n"
+                "rdvl x17, #1\n"
+                "mul x16, x16, x17\n"
+                "add x9, x9, x16, asr #3");
+  // If the stack pointer is used, the `asr` and `add` must be separate.
+  COMPARE_MACRO(Addpl(sp, x0, 33),
+                "mov x16, #0x21\n"
+                "rdvl x17, #1\n"
+                "mul x16, x16, x17\n"
+                "asr x16, x16, #3\n"
+                "add sp, x0, x16");
+
+  CLEANUP();
+}
+
+TEST(sve_vector_select) {
+  SETUP();
+
+  COMPARE_MACRO(Sel(z13.VnB(), p3, z3.VnB(), z25.VnB()),
+                "sel z13.b, p3, z3.b, z25.b");
+  COMPARE_MACRO(Sel(z13.VnH(), p3, z3.VnH(), z25.VnH()),
+                "sel z13.h, p3, z3.h, z25.h");
+  COMPARE_MACRO(Sel(z13.VnS(), p3, z3.VnS(), z25.VnS()),
+                "sel z13.s, p3, z3.s, z25.s");
+  COMPARE_MACRO(Sel(z13.VnD(), p3, z3.VnD(), z25.VnD()),
+                "sel z13.d, p3, z3.d, z25.d");
+
+  // Check sel() where zd == zm disassemble as predicated mov.
+  COMPARE_MACRO(Sel(z1.VnB(), p4.Merging(), z30.VnB(), z1.VnB()),
+                "mov z1.b, p4/m, z30.b");
+  COMPARE_MACRO(Sel(z1.VnH(), p4.Merging(), z30.VnH(), z1.VnH()),
+                "mov z1.h, p4/m, z30.h");
+  COMPARE_MACRO(Sel(z1.VnS(), p4.Merging(), z30.VnS(), z1.VnS()),
+                "mov z1.s, p4/m, z30.s");
+  COMPARE_MACRO(Sel(z1.VnD(), p4.Merging(), z30.VnD(), z1.VnD()),
+                "mov z1.d, p4/m, z30.d");
+
+  // Check predicated mov() directly.
+  COMPARE_MACRO(Mov(z2.VnB(), p10.Merging(), z22.VnB()),
+                "mov z2.b, p10/m, z22.b");
+  COMPARE_MACRO(Mov(z2.VnH(), p10.Merging(), z22.VnH()),
+                "mov z2.h, p10/m, z22.h");
+  COMPARE_MACRO(Mov(z2.VnS(), p10.Merging(), z22.VnS()),
+                "mov z2.s, p10/m, z22.s");
+  COMPARE_MACRO(Mov(z2.VnD(), p10.Merging(), z22.VnD()),
+                "mov z2.d, p10/m, z22.d");
+
+  CLEANUP();
+}
+
+TEST(sve_write_ffr) {
+  SETUP();
+
+  COMPARE_PREFIX(setffr(), "setffr");
+  COMPARE_PREFIX(wrffr(p9.VnB()), "wrffr p9.b");
+
+  CLEANUP();
+}
+
+}  // namespace aarch64
+}  // namespace vixl
diff --git a/test/aarch64/test-simulator-aarch64.cc b/test/aarch64/test-simulator-aarch64.cc
index 5474d914..ac812fda 100644
--- a/test/aarch64/test-simulator-aarch64.cc
+++ b/test/aarch64/test-simulator-aarch64.cc
@@ -62,13 +62,12 @@ namespace aarch64 {
 
 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
 
-#define SETUP_WITH_FEATURES(...)                      \
-  MacroAssembler masm;                                \
-  masm.SetCPUFeatures(CPUFeatures(__VA_ARGS__));      \
-  Decoder decoder;                                    \
-  Simulator simulator(&decoder);                      \
-  simulator.SetColouredTrace(Test::coloured_trace()); \
-  simulator.SetInstructionStats(Test::instruction_stats());
+#define SETUP_WITH_FEATURES(...)                 \
+  MacroAssembler masm;                           \
+  masm.SetCPUFeatures(CPUFeatures(__VA_ARGS__)); \
+  Decoder decoder;                               \
+  Simulator simulator(&decoder);                 \
+  simulator.SetColouredTrace(Test::coloured_trace());
 
 #define START()                         \
   masm.Reset();                         \
@@ -82,15 +81,9 @@ namespace aarch64 {
   }                                     \
   if (Test::trace_sim()) {              \
     __ Trace(LOG_DISASM, TRACE_ENABLE); \
-  }                                     \
-  if (Test::instruction_stats()) {      \
-    __ EnableInstrumentation();         \
   }
 
 #define END()                       \
-  if (Test::instruction_stats()) {  \
-    __ DisableInstrumentation();    \
-  }                                 \
   __ Trace(LOG_ALL, TRACE_DISABLE); \
   __ PopCalleeSavedRegisters();     \
   __ Ret();                         \
@@ -3980,7 +3973,7 @@ DEFINE_TEST_FP_TO_JS_INT(fjcvtzs, FPToS, Conversions)
                                  2S,                                  \
                                  2S,                                  \
                                  kInputFloat##Basic,                  \
-                                 kInputDoubleImm##input_imm)          \
+                                 kInputDoubleImm##input_imm);         \
   }                                                                   \
   TEST(mnemonic##_4S_2OPIMM) {                                        \
     CALL_TEST_NEON_HELPER_2OPIMM(mnemonic,                            \
@@ -4003,35 +3996,35 @@ DEFINE_TEST_FP_TO_JS_INT(fjcvtzs, FPToS, Conversions)
                                  4H,                           \
                                  4H,                           \
                                  kInputFloat16##input,         \
-                                 kInput16bitsImm##input_imm)   \
+                                 kInput16bitsImm##input_imm);  \
   }                                                            \
   TEST(mnemonic##_8H_2OPIMM) {                                 \
     CALL_TEST_NEON_HELPER_2OPIMM(mnemonic,                     \
                                  8H,                           \
                                  8H,                           \
                                  kInputFloat16##input,         \
-                                 kInput16bitsImm##input_imm)   \
+                                 kInput16bitsImm##input_imm);  \
   }                                                            \
   TEST(mnemonic##_2S_2OPIMM) {                                 \
     CALL_TEST_NEON_HELPER_2OPIMM(mnemonic,                     \
                                  2S,                           \
                                  2S,                           \
                                  kInputFloat##Basic,           \
-                                 kInput32bitsImm##input_imm)   \
+                                 kInput32bitsImm##input_imm);  \
   }                                                            \
   TEST(mnemonic##_4S_2OPIMM) {                                 \
     CALL_TEST_NEON_HELPER_2OPIMM(mnemonic,                     \
                                  4S,                           \
                                  4S,                           \
                                  kInputFloat##input,           \
-                                 kInput32bitsImm##input_imm)   \
+                                 kInput32bitsImm##input_imm);  \
   }                                                            \
   TEST(mnemonic##_2D_2OPIMM) {                                 \
     CALL_TEST_NEON_HELPER_2OPIMM(mnemonic,                     \
                                  2D,                           \
                                  2D,                           \
                                  kInputDouble##input,          \
-                                 kInput64bitsImm##input_imm)   \
+                                 kInput64bitsImm##input_imm);  \
   }
 
 #define DEFINE_TEST_NEON_2OPIMM_FP_SCALAR(mnemonic, input, input_imm) \
@@ -4040,21 +4033,21 @@ DEFINE_TEST_FP_TO_JS_INT(fjcvtzs, FPToS, Conversions)
                                  H,                                   \
                                  H,                                   \
                                  kInputFloat16##Basic,                \
-                                 kInput16bitsImm##input_imm)          \
+                                 kInput16bitsImm##input_imm);         \
   }                                                                   \
   TEST(mnemonic##_S_2OPIMM) {                                         \
     CALL_TEST_NEON_HELPER_2OPIMM(mnemonic,                            \
                                  S,                                   \
                                  S,                                   \
                                  kInputFloat##Basic,                  \
-                                 kInput32bitsImm##input_imm)          \
+                                 kInput32bitsImm##input_imm);         \
   }                                                                   \
   TEST(mnemonic##_D_2OPIMM) {                                         \
     CALL_TEST_NEON_HELPER_2OPIMM(mnemonic,                            \
                                  D,                                   \
                                  D,                                   \
                                  kInputDouble##input,                 \
-                                 kInput64bitsImm##input_imm)          \
+                                 kInput64bitsImm##input_imm);         \
   }
 
 #define DEFINE_TEST_NEON_2OPIMM_HSD(mnemonic, input, input_imm) \
diff --git a/test/aarch64/test-simulator-traces-aarch64.h b/test/aarch64/test-simulator-traces-aarch64.h
index 03b58190..db57bb46 100644
--- a/test/aarch64/test-simulator-traces-aarch64.h
+++ b/test/aarch64/test-simulator-traces-aarch64.h
@@ -41,19 +41,19 @@ extern "C" {
 #include <stdint.h>
 }
 
-// To add a new simulator test to test-simulator-aarch64.cc, add dummy array(s)
-// below to build test-simulator-aarch64 for reference platform. Then, run
-// tools/generate_simulator_traces.py on a reference platform to regenerate this
-// file and traces files.
+// To add a new simulator test to test-simulator-aarch64.cc, add placeholder
+// array(s) below to build test-simulator-aarch64 for reference platform. Then,
+// run tools/generate_simulator_traces.py on a reference platform to regenerate
+// this file and traces files.
 
 // ---------------------------------------------------------------------
 // ADD DUMMY ARRAYS FOR NEW SIMULATOR TEST HERE.
 // ---------------------------------------------------------------------
-const uint64_t kExpected_dummy_64[] = {0};
-const size_t kExpectedCount_dummy_64 = 0;
+const uint64_t kExpected_placeholder_64[] = {0};
+const size_t kExpectedCount_placeholder_64 = 0;
 
-const uint32_t kExpected_dummy_32[] = {0};
-const size_t kExpectedCount_dummy_32 = 0;
+const uint32_t kExpected_placeholder_32[] = {0};
+const size_t kExpectedCount_placeholder_32 = 0;
 
 // ---------------------------------------------------------------------
 // Simulator test trace output files.
diff --git a/test/aarch64/test-trace-aarch64.cc b/test/aarch64/test-trace-aarch64.cc
index 90d1295e..a0a2172f 100644
--- a/test/aarch64/test-trace-aarch64.cc
+++ b/test/aarch64/test-trace-aarch64.cc
@@ -30,6 +30,9 @@
 #include <cstdlib>
 #include <cstring>
 
+#include <fstream>
+#include <regex>
+
 #include "test-runner.h"
 #include "test-utils-aarch64.h"
 
@@ -2738,45 +2741,180 @@ static void GenerateTestSequenceNEONFP(MacroAssembler* masm) {
 }
 
 
+static void GenerateTestSequenceSVE(MacroAssembler* masm) {
+  ExactAssemblyScope guard(masm,
+                           masm->GetBuffer()->GetRemainingBytes(),
+                           ExactAssemblyScope::kMaximumSize);
+  CPUFeaturesScope feature_guard(masm, CPUFeatures::kSVE);
+
+  // Simple, unpredicated loads and stores.
+  __ str(p12.VnD(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ str(p13.VnS(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ str(p14.VnH(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ str(p15.VnB(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ ldr(p8.VnD(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ ldr(p9.VnS(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ ldr(p10.VnH(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ ldr(p11.VnB(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+
+  __ str(z0.VnD(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ str(z1.VnS(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ str(z2.VnH(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ str(z3.VnB(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ ldr(z20.VnD(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ ldr(z21.VnS(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ ldr(z22.VnH(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+  __ ldr(z23.VnB(), SVEMemOperand(x0, 11, SVE_MUL_VL));
+
+  // Structured accesses.
+  __ st1b(z0.VnB(), p2, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st1h(z1.VnH(), p1, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st1w(z2.VnS(), p1, SVEMemOperand(x0, x3, LSL, 2));
+  __ st1d(z3.VnD(), p2, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1b(z20.VnB(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1h(z21.VnH(), p2.Zeroing(), SVEMemOperand(x0, x2, LSL, 1));
+  __ ld1w(z22.VnS(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1d(z23.VnD(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+
+  // Structured, packed accesses.
+  __ st1b(z2.VnH(), p1, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st1b(z3.VnS(), p2, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st1b(z4.VnD(), p2, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st1h(z0.VnS(), p1, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st1h(z1.VnD(), p1, SVEMemOperand(x0, x2, LSL, 1));
+  __ st1w(z2.VnD(), p1, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1b(z20.VnH(), p1.Zeroing(), SVEMemOperand(x0, x2));
+  __ ld1b(z21.VnS(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1b(z22.VnD(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1h(z23.VnS(), p2.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1h(z24.VnD(), p2.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1w(z20.VnD(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1sb(z21.VnH(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1sb(z22.VnS(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1sb(z23.VnD(), p2.Zeroing(), SVEMemOperand(x0, x2));
+  __ ld1sh(z24.VnS(), p2.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1sh(z20.VnD(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld1sw(z21.VnD(), p1.Zeroing(), SVEMemOperand(x0, 3, SVE_MUL_VL));
+
+  // Structured, interleaved accesses.
+  __ st2b(z0.VnB(), z1.VnB(), p4, SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ st2h(z1.VnH(), z2.VnH(), p4, SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ st2w(z2.VnS(), z3.VnS(), p3, SVEMemOperand(x0, x2, LSL, 2));
+  __ st2d(z3.VnD(), z4.VnD(), p4, SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ ld2b(z20.VnB(), z21.VnB(), p5.Zeroing(), SVEMemOperand(x0, x2));
+  __ ld2h(z21.VnH(), z22.VnH(), p6.Zeroing(), SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ ld2w(z22.VnS(), z23.VnS(), p6.Zeroing(), SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ ld2d(z23.VnD(), z24.VnD(), p5.Zeroing(), SVEMemOperand(x0, 4, SVE_MUL_VL));
+
+  __ st3b(z4.VnB(), z5.VnB(), z6.VnB(), p4, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st3h(z5.VnH(), z6.VnH(), z7.VnH(), p4, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st3w(z6.VnS(), z7.VnS(), z8.VnS(), p3, SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ st3d(z7.VnD(), z8.VnD(), z9.VnD(), p4, SVEMemOperand(x0, x2, LSL, 3));
+  __ ld3b(z24.VnB(),
+          z25.VnB(),
+          z26.VnB(),
+          p5.Zeroing(),
+          SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld3h(z25.VnH(),
+          z26.VnH(),
+          z27.VnH(),
+          p6.Zeroing(),
+          SVEMemOperand(x0, x2, LSL, 1));
+  __ ld3w(z26.VnS(),
+          z27.VnS(),
+          z28.VnS(),
+          p6.Zeroing(),
+          SVEMemOperand(x0, 3, SVE_MUL_VL));
+  __ ld3d(z27.VnD(),
+          z28.VnD(),
+          z29.VnD(),
+          p5.Zeroing(),
+          SVEMemOperand(x0, 3, SVE_MUL_VL));
+
+  __ st4b(z31.VnB(),
+          z0.VnB(),
+          z1.VnB(),
+          z2.VnB(),
+          p4,
+          SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ st4h(z0.VnH(),
+          z1.VnH(),
+          z2.VnH(),
+          z3.VnH(),
+          p4,
+          SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ st4w(z1.VnS(),
+          z2.VnS(),
+          z3.VnS(),
+          z4.VnS(),
+          p3,
+          SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ st4d(z2.VnD(),
+          z3.VnD(),
+          z4.VnD(),
+          z5.VnD(),
+          p4,
+          SVEMemOperand(x0, x2, LSL, 3));
+  __ ld4b(z25.VnB(),
+          z26.VnB(),
+          z27.VnB(),
+          z28.VnB(),
+          p5.Zeroing(),
+          SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ ld4h(z26.VnH(),
+          z27.VnH(),
+          z28.VnH(),
+          z29.VnH(),
+          p6.Zeroing(),
+          SVEMemOperand(x0, 4, SVE_MUL_VL));
+  __ ld4w(z27.VnS(),
+          z28.VnS(),
+          z29.VnS(),
+          z30.VnS(),
+          p6.Zeroing(),
+          SVEMemOperand(x0, x2, LSL, 2));
+  __ ld4d(z28.VnD(),
+          z29.VnD(),
+          z30.VnD(),
+          z31.VnD(),
+          p5.Zeroing(),
+          SVEMemOperand(x0, 4, SVE_MUL_VL));
+}
+
 static void MaskAddresses(const char* trace) {
-#ifdef __APPLE__
-#define MAYBE_ANSI_C_QUOTE "$"
-#define ESCAPE(c) "\\\\" #c
-  const char* sed_options = "-i \"\" -E";
-#else
-#define MAYBE_ANSI_C_QUOTE
-#define ESCAPE(c) "\\" #c
-  const char* sed_options = "-i -E";
-#endif
-#define COLOUR "(\x1b" ESCAPE([) "[01];([0-9][0-9])?m)?"
-  struct {
-    const char* search;
-    const char* replace;
-  } patterns[] =
+#define VIXL_COLOUR "(\x1b\\[[01];([0-9][0-9])?m)?"
+  // All patterns are replaced with "$1~~~~~~~~~~~~~~~~".
+  std::regex patterns[] =
       {// Mask registers that hold addresses that change from run to run.
-       {"((x0|x1|x2|sp): " COLOUR "0x)[0-9a-f]{16}",
-        ESCAPE(1) "~~~~~~~~~~~~~~~~"},
+       std::regex("((x0|x1|x2|sp): " VIXL_COLOUR "0x)[0-9a-f]{16}"),
        // Mask accessed memory addresses.
-       {"((<-|->) " COLOUR "0x)[0-9a-f]{16}", ESCAPE(1) "~~~~~~~~~~~~~~~~"},
+       std::regex("((<-|->) " VIXL_COLOUR "0x)[0-9a-f]{16}"),
        // Mask instruction addresses.
-       {"^0x[0-9a-f]{16}", "0x~~~~~~~~~~~~~~~~"},
+       std::regex("^(0x)[0-9a-f]{16}"),
        // Mask branch targets.
-       {"(Branch" COLOUR " to 0x)[0-9a-f]{16}", ESCAPE(1) "~~~~~~~~~~~~~~~~"},
-       {"addr 0x[0-9a-f]+", "addr 0x~~~~~~~~~~~~~~~~"}};
-  const size_t patterns_length = sizeof(patterns) / sizeof(patterns[0]);
-  // Rewrite `trace`, masking addresses and other values that legitimately vary
-  // from run to run.
-  char command[1024];
-  for (size_t i = 0; i < patterns_length; i++) {
-    size_t length = snprintf(command,
-                             sizeof(command),
-                             "sed %s 's/%s/%s/' '%s'",
-                             sed_options,
-                             patterns[i].search,
-                             patterns[i].replace,
-                             trace);
-    VIXL_CHECK(length < sizeof(command));
-    VIXL_CHECK(system(command) == 0);
+       std::regex("(Branch" VIXL_COLOUR " to 0x)[0-9a-f]{16}"),
+       // Mask explicit address annotations.
+       std::regex("(addr 0x)[0-9a-f]+")};
+#undef VIXL_COLOUR
+
+  std::vector<std::string> lines;
+  std::ifstream in(trace);
+  while (!in.eof()) {
+    std::string line;
+    std::getline(in, line);
+    for (auto&& pattern : patterns) {
+      line = std::regex_replace(line, pattern, "$1~~~~~~~~~~~~~~~~");
+    }
+    lines.push_back(line);
+  }
+  in.close();
+
+  // `getline` produces an empty line after a terminal "\n".
+  if (lines.back().empty()) lines.pop_back();
+
+  std::ofstream out(trace, std::ofstream::trunc);
+  for (auto&& line : lines) {
+    out << line << "\n";
   }
 }
 
@@ -2831,22 +2969,27 @@ static void TraceTestHelper(bool coloured_trace,
   simulator.SetTraceParameters(trace_parameters);
   simulator.SilenceExclusiveAccessWarning();
 
+  const int vl_in_bytes = 5 * kZRegMinSizeInBytes;
+  const int vl_in_bits = vl_in_bytes * kBitsPerByte;
+  const int pl_in_bits = vl_in_bits / kZRegBitsPerPRegBit;
+  simulator.SetVectorLengthInBits(vl_in_bits);
+
   // Set up a scratch buffer so we can test loads and stores.
-  const int kScratchSize = 64 * KBytes;
-  const int kScratchGuardSize = 128;
+  const int kScratchSize = vl_in_bytes * 1024;
+  const int kScratchGuardSize = vl_in_bytes;
   char scratch_buffer[kScratchSize + kScratchGuardSize];
   for (size_t i = 0; i < (sizeof(scratch_buffer) / sizeof(scratch_buffer[0]));
        i++) {
     scratch_buffer[i] = i & 0xff;
   }
   // Used for offset addressing.
-  simulator.WriteRegister(0, scratch_buffer);
+  simulator.WriteXRegister(0, reinterpret_cast<uintptr_t>(scratch_buffer));
   // Used for pre-/post-index addressing.
-  simulator.WriteRegister(1, scratch_buffer);
+  simulator.WriteXRegister(1, reinterpret_cast<uintptr_t>(scratch_buffer));
 
   const int kPostIndexRegisterStep = 13;  // Arbitrary interesting value.
   // Used for post-index offsets.
-  simulator.WriteRegister(2, kPostIndexRegisterStep);
+  simulator.WriteXRegister(2, kPostIndexRegisterStep);
 
   // Initialize the other registers with unique values.
   uint64_t initial_base_u64 = 0x0100001000100101;
@@ -2858,22 +3001,41 @@ static void TraceTestHelper(bool coloured_trace,
     // not printed.
     simulator.WriteRegister(i, initial_base_u64 * i, Simulator::NoRegLog);
   }
-  float initial_base_f32 = 1.2345f;
-  double initial_base_f64 = 1.3456f;
-  for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
-    // Try to initialise V registers with reasonable FP values.
-    uint64_t low = (DoubleToRawbits(initial_base_f64 * i) & ~kSRegMask) |
-                   FloatToRawbits(initial_base_f32 * i);
-    uint64_t high = low ^ 0x0005555500555555;
-    LogicVRegister reg(simulator.ReadVRegister(i));
-    reg.SetUint(kFormat2D, 0, low);
-    reg.SetUint(kFormat2D, 1, high);
+  for (unsigned r = 0; r < kNumberOfVRegisters; r++) {
+    LogicVRegister reg(simulator.ReadVRegister(r));
+    // Try to initialise Z registers with reasonable FP values. We prioritise
+    // setting double values, then floats and half-precision values. The lanes
+    // overlap, so this is a compromise, but d0, s0 and h0 views all see similar
+    // arithmetic values.
+    //
+    // The exponent of each value is set to the (biased) register number. We set
+    // the double, float and half-precision exponents where we can.
+    uint64_t base = 0x3ff000003f803c00 + (0x0010000000800400 * (0x7f + r));
+    for (unsigned lane = 0; lane < (vl_in_bytes / kDRegSizeInBytes); lane++) {
+      uint64_t mantissas = 0x0000000100010001 * (lane & 0x7f);
+      reg.SetUint(kFormatVnD, lane, base | mantissas);
+    }
+  }
+  for (unsigned r = 0; r < kNumberOfPRegisters; r++) {
+    LogicPRegister reg(simulator.ReadPRegister(r));
+    // Set `r` active lanes between each inactive lane.
+    for (unsigned bit = 0; bit < pl_in_bits; bit++) {
+      reg.SetActive(kFormatVnB, bit, ((bit + 1) % (r + 2)) != 0);
+    }
+    // Completely clear some Q-sized blocks. The trace will completely omit
+    // these for stores.
+    for (unsigned chunk = 0; chunk < (vl_in_bits / kQRegSize); chunk++) {
+      if (((chunk + 1) % (r + 2)) == 0) {
+        reg.SetActiveMask(chunk, static_cast<uint16_t>(0));
+      }
+    }
   }
 
   GenerateTestSequenceBase(&masm);
   GenerateTestSequenceFP(&masm);
   GenerateTestSequenceNEON(&masm);
   GenerateTestSequenceNEONFP(&masm);
+  GenerateTestSequenceSVE(&masm);
   masm.Ret();
   masm.FinalizeCode();
 
@@ -2964,6 +3126,7 @@ static void PrintDisassemblerTestHelper(const char* prefix,
   GenerateTestSequenceFP(&masm);
   GenerateTestSequenceNEON(&masm);
   GenerateTestSequenceNEONFP(&masm);
+  GenerateTestSequenceSVE(&masm);
   masm.FinalizeCode();
 
   Decoder decoder;
diff --git a/test/aarch64/test-utils-aarch64.cc b/test/aarch64/test-utils-aarch64.cc
index 62f8cbd5..5e6a3519 100644
--- a/test/aarch64/test-utils-aarch64.cc
+++ b/test/aarch64/test-utils-aarch64.cc
@@ -25,6 +25,7 @@
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 #include <cmath>
+#include <queue>
 
 #include "test-runner.h"
 #include "test-utils-aarch64.h"
@@ -40,15 +41,15 @@ namespace vixl {
 namespace aarch64 {
 
 
-// This value is a signalling NaN as both a double and as a float (taking the
-// least-significant word).
-const double kFP64SignallingNaN = RawbitsToDouble(UINT64_C(0x7ff000007f800001));
-const float kFP32SignallingNaN = RawbitsToFloat(0x7f800001);
+// This value is a signalling NaN as FP64, and also as FP32 or FP16 (taking the
+// least-significant bits).
+const double kFP64SignallingNaN = RawbitsToDouble(UINT64_C(0x7ff000007f807c01));
+const float kFP32SignallingNaN = RawbitsToFloat(0x7f807c01);
 const Float16 kFP16SignallingNaN = RawbitsToFloat16(0x7c01);
 
 // A similar value, but as a quiet NaN.
-const double kFP64QuietNaN = RawbitsToDouble(UINT64_C(0x7ff800007fc00001));
-const float kFP32QuietNaN = RawbitsToFloat(0x7fc00001);
+const double kFP64QuietNaN = RawbitsToDouble(UINT64_C(0x7ff800007fc07e01));
+const float kFP32QuietNaN = RawbitsToFloat(0x7fc07e01);
 const Float16 kFP16QuietNaN = RawbitsToFloat16(0x7e01);
 
 
@@ -86,18 +87,20 @@ bool Equal64(uint64_t reference,
 }
 
 
-bool Equal128(vec128_t expected, const RegisterDump*, vec128_t result) {
-  if ((result.h != expected.h) || (result.l != expected.l)) {
+bool Equal128(QRegisterValue expected,
+              const RegisterDump*,
+              QRegisterValue result) {
+  if (!expected.Equals(result)) {
     printf("Expected 0x%016" PRIx64 "%016" PRIx64
            "\t "
            "Found 0x%016" PRIx64 "%016" PRIx64 "\n",
-           expected.h,
-           expected.l,
-           result.h,
-           result.l);
+           expected.GetLane<uint64_t>(1),
+           expected.GetLane<uint64_t>(0),
+           result.GetLane<uint64_t>(1),
+           result.GetLane<uint64_t>(0));
   }
 
-  return ((expected.h == result.h) && (expected.l == result.l));
+  return expected.Equals(result);
 }
 
 
@@ -209,8 +212,10 @@ bool Equal128(uint64_t expected_h,
               const RegisterDump* core,
               const VRegister& vreg) {
   VIXL_ASSERT(vreg.Is128Bits());
-  vec128_t expected = {expected_l, expected_h};
-  vec128_t result = core->qreg(vreg.GetCode());
+  QRegisterValue expected;
+  expected.SetLane(0, expected_l);
+  expected.SetLane(1, expected_h);
+  QRegisterValue result = core->qreg(vreg.GetCode());
   return Equal128(expected, core, result);
 }
 
@@ -348,7 +353,137 @@ bool EqualRegisters(const RegisterDump* a, const RegisterDump* b) {
   return true;
 }
 
+bool EqualSVELane(uint64_t expected,
+                  const RegisterDump* core,
+                  const ZRegister& reg,
+                  int lane) {
+  unsigned lane_size = reg.GetLaneSizeInBits();
+  // For convenience in the tests, we allow negative values to be passed into
+  // `expected`, but truncate them to an appropriately-sized unsigned value for
+  // the check. For example, in `EqualSVELane(-1, core, z0.VnB())`, the expected
+  // value is truncated from 0xffffffffffffffff to 0xff before the comparison.
+  VIXL_ASSERT(IsUintN(lane_size, expected) ||
+              IsIntN(lane_size, RawbitsToInt64(expected)));
+  expected &= GetUintMask(lane_size);
+
+  uint64_t result = core->zreg_lane(reg.GetCode(), lane_size, lane);
+  if (expected != result) {
+    unsigned lane_size_in_hex_chars = lane_size / 4;
+    std::string reg_name = reg.GetArchitecturalName();
+    printf("%s[%d]\t Expected 0x%0*" PRIx64 "\t Found 0x%0*" PRIx64 "\n",
+           reg_name.c_str(),
+           lane,
+           lane_size_in_hex_chars,
+           expected,
+           lane_size_in_hex_chars,
+           result);
+    return false;
+  }
+  return true;
+}
+
+bool EqualSVELane(uint64_t expected,
+                  const RegisterDump* core,
+                  const PRegister& reg,
+                  int lane) {
+  VIXL_ASSERT(reg.HasLaneSize());
+  VIXL_ASSERT((reg.GetLaneSizeInBits() % kZRegBitsPerPRegBit) == 0);
+  unsigned p_bits_per_lane = reg.GetLaneSizeInBits() / kZRegBitsPerPRegBit;
+  VIXL_ASSERT(IsUintN(p_bits_per_lane, expected));
+  expected &= GetUintMask(p_bits_per_lane);
+
+  uint64_t result = core->preg_lane(reg.GetCode(), p_bits_per_lane, lane);
+  if (expected != result) {
+    unsigned lane_size_in_hex_chars = (p_bits_per_lane + 3) / 4;
+    std::string reg_name = reg.GetArchitecturalName();
+    printf("%s[%d]\t Expected 0x%0*" PRIx64 "\t Found 0x%0*" PRIx64 "\n",
+           reg_name.c_str(),
+           lane,
+           lane_size_in_hex_chars,
+           expected,
+           lane_size_in_hex_chars,
+           result);
+    return false;
+  }
+  return true;
+}
+
+struct EqualMemoryChunk {
+  typedef uint64_t RawChunk;
+
+  uintptr_t address;
+  RawChunk expected;
+  RawChunk result;
+
+  bool IsEqual() const { return expected == result; }
+};
+
+bool EqualMemory(const void* expected,
+                 const void* result,
+                 size_t size_in_bytes,
+                 size_t zero_offset) {
+  if (memcmp(expected, result, size_in_bytes) == 0) return true;
+
+  // Read 64-bit chunks, and print them side-by-side if they don't match.
+
+  // Remember the last few chunks, even if they matched, so we can print some
+  // context. We don't want to print the whole buffer, because it could be huge.
+  static const size_t kContextLines = 1;
+  std::queue<EqualMemoryChunk> context;
+  static const size_t kChunkSize = sizeof(EqualMemoryChunk::RawChunk);
+
+  // This assumption keeps the logic simple, and is acceptable for our tests.
+  VIXL_ASSERT((size_in_bytes % kChunkSize) == 0);
+
+  const char* expected_it = reinterpret_cast<const char*>(expected);
+  const char* result_it = reinterpret_cast<const char*>(result);
+
+  // This is the first error, so print a header row.
+  printf("  Address (of result)                  Expected           Result\n");
+
+  // Always print some context at the start of the buffer.
+  uintptr_t print_context_to =
+      reinterpret_cast<uintptr_t>(result) + (kContextLines + 1) * kChunkSize;
+  for (size_t i = 0; i < size_in_bytes; i += kChunkSize) {
+    EqualMemoryChunk chunk;
+    chunk.address = reinterpret_cast<uintptr_t>(result_it);
+    memcpy(&chunk.expected, expected_it, kChunkSize);
+    memcpy(&chunk.result, result_it, kChunkSize);
+
+    while (context.size() > kContextLines) context.pop();
+    context.push(chunk);
+
+    // Print context after an error, and at the end of the buffer.
+    if (!chunk.IsEqual() || ((i + kChunkSize) >= size_in_bytes)) {
+      if (chunk.address > print_context_to) {
+        // We aren't currently printing context, so separate this context from
+        // the previous block.
+        printf("...\n");
+      }
+      print_context_to = chunk.address + (kContextLines + 1) * kChunkSize;
+    }
 
+    // Print context (including the current line).
+    while (!context.empty() && (context.front().address < print_context_to)) {
+      uintptr_t address = context.front().address;
+      uint64_t offset = address - reinterpret_cast<uintptr_t>(result);
+      bool is_negative = (offset < zero_offset);
+      printf("0x%016" PRIxPTR " (result %c %5" PRIu64 "): 0x%016" PRIx64
+             " 0x%016" PRIx64 "\n",
+             address,
+             (is_negative ? '-' : '+'),
+             (is_negative ? (zero_offset - offset) : (offset - zero_offset)),
+             context.front().expected,
+             context.front().result);
+      context.pop();
+    }
+
+    expected_it += kChunkSize;
+    result_it += kChunkSize;
+  }
+
+  return false;
+}
 RegList PopulateRegisterArray(Register* w,
                               Register* x,
                               Register* r,
@@ -461,25 +596,57 @@ void Clobber(MacroAssembler* masm, CPURegList reg_list) {
     // This will always clobber D registers.
     ClobberFP(masm, reg_list.GetList());
   } else {
-    VIXL_UNREACHABLE();
+    VIXL_UNIMPLEMENTED();
+  }
+}
+
+// TODO: Once registers have sufficiently compatible interfaces, merge the two
+// DumpRegisters templates.
+template <typename T>
+static void DumpRegisters(MacroAssembler* masm,
+                          Register dump_base,
+                          int offset) {
+  UseScratchRegisterScope temps(masm);
+  Register dump = temps.AcquireX();
+  __ Add(dump, dump_base, offset);
+  for (unsigned i = 0; i <= T::GetMaxCode(); i++) {
+    T reg(i);
+    __ Str(reg, SVEMemOperand(dump));
+    __ Add(dump, dump, reg.GetMaxSizeInBytes());
   }
 }
 
+template <typename T>
+static void DumpRegisters(MacroAssembler* masm,
+                          Register dump_base,
+                          int offset,
+                          int reg_size_in_bytes) {
+  UseScratchRegisterScope temps(masm);
+  Register dump = temps.AcquireX();
+  __ Add(dump, dump_base, offset);
+  for (unsigned i = 0; i <= T::GetMaxCode(); i++) {
+    T reg(i, reg_size_in_bytes * kBitsPerByte);
+    __ Str(reg, MemOperand(dump));
+    __ Add(dump, dump, reg_size_in_bytes);
+  }
+}
 
 void RegisterDump::Dump(MacroAssembler* masm) {
   VIXL_ASSERT(__ StackPointer().Is(sp));
 
-  // Ensure that we don't unintentionally clobber any registers.
+  dump_cpu_features_ = *masm->GetCPUFeatures();
+
+  // We need some scratch registers, but we also need to dump them, so we have
+  // to control exactly which registers are used, and dump them separately.
+  CPURegList scratch_registers(x0, x1, x2, x3);
+
   UseScratchRegisterScope temps(masm);
   temps.ExcludeAll();
+  __ PushCPURegList(scratch_registers);
+  temps.Include(scratch_registers);
 
-  // Preserve some temporary registers.
-  Register dump_base = x0;
-  Register dump = x1;
-  Register tmp = x2;
-  Register dump_base_w = dump_base.W();
-  Register dump_w = dump.W();
-  Register tmp_w = tmp.W();
+  Register dump_base = temps.AcquireX();
+  Register tmp = temps.AcquireX();
 
   // Offsets into the dump_ structure.
   const int x_offset = offsetof(dump_t, x_);
@@ -488,11 +655,12 @@ void RegisterDump::Dump(MacroAssembler* masm) {
   const int s_offset = offsetof(dump_t, s_);
   const int h_offset = offsetof(dump_t, h_);
   const int q_offset = offsetof(dump_t, q_);
+  const int z_offset = offsetof(dump_t, z_);
+  const int p_offset = offsetof(dump_t, p_);
   const int sp_offset = offsetof(dump_t, sp_);
   const int wsp_offset = offsetof(dump_t, wsp_);
   const int flags_offset = offsetof(dump_t, flags_);
-
-  __ Push(xzr, dump_base, dump, tmp);
+  const int vl_offset = offsetof(dump_t, vl_);
 
   // Load the address where we will dump the state.
   __ Mov(dump_base, reinterpret_cast<uintptr_t>(&dump_));
@@ -503,94 +671,112 @@ void RegisterDump::Dump(MacroAssembler* masm) {
   // compensate here.
   __ Add(tmp, sp, 4 * kXRegSizeInBytes);
   __ Str(tmp, MemOperand(dump_base, sp_offset));
-  __ Add(tmp_w, wsp, 4 * kXRegSizeInBytes);
-  __ Str(tmp_w, MemOperand(dump_base, wsp_offset));
-
-  // Dump X registers.
-  __ Add(dump, dump_base, x_offset);
-  for (unsigned i = 0; i < kNumberOfRegisters; i += 2) {
-    __ Stp(Register::GetXRegFromCode(i),
-           Register::GetXRegFromCode(i + 1),
-           MemOperand(dump, i * kXRegSizeInBytes));
-  }
-
-  // Dump W registers.
-  __ Add(dump, dump_base, w_offset);
-  for (unsigned i = 0; i < kNumberOfRegisters; i += 2) {
-    __ Stp(Register::GetWRegFromCode(i),
-           Register::GetWRegFromCode(i + 1),
-           MemOperand(dump, i * kWRegSizeInBytes));
-  }
-
-  // Dump D registers.
-  __ Add(dump, dump_base, d_offset);
-  for (unsigned i = 0; i < kNumberOfVRegisters; i += 2) {
-    __ Stp(VRegister::GetDRegFromCode(i),
-           VRegister::GetDRegFromCode(i + 1),
-           MemOperand(dump, i * kDRegSizeInBytes));
-  }
-
-  // Dump S registers.
-  __ Add(dump, dump_base, s_offset);
-  for (unsigned i = 0; i < kNumberOfVRegisters; i += 2) {
-    __ Stp(VRegister::GetSRegFromCode(i),
-           VRegister::GetSRegFromCode(i + 1),
-           MemOperand(dump, i * kSRegSizeInBytes));
-  }
-
-#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
-  // Dump H registers. Note: Stp does not support 16 bits.
-  __ Add(dump, dump_base, h_offset);
-  for (unsigned i = 0; i < kNumberOfVRegisters; i++) {
-    __ Str(VRegister::GetHRegFromCode(i),
-           MemOperand(dump, i * kHRegSizeInBytes));
-  }
-#else
-  USE(h_offset);
-#endif
-
-  // Dump Q registers.
-  __ Add(dump, dump_base, q_offset);
-  for (unsigned i = 0; i < kNumberOfVRegisters; i += 2) {
-    __ Stp(VRegister::GetQRegFromCode(i),
-           VRegister::GetQRegFromCode(i + 1),
-           MemOperand(dump, i * kQRegSizeInBytes));
+  __ Add(tmp.W(), wsp, 4 * kXRegSizeInBytes);
+  __ Str(tmp.W(), MemOperand(dump_base, wsp_offset));
+
+  // Dump core registers.
+  DumpRegisters<Register>(masm, dump_base, x_offset, kXRegSizeInBytes);
+  DumpRegisters<Register>(masm, dump_base, w_offset, kWRegSizeInBytes);
+
+  // Dump NEON and FP registers.
+  DumpRegisters<VRegister>(masm, dump_base, q_offset, kQRegSizeInBytes);
+  DumpRegisters<VRegister>(masm, dump_base, d_offset, kDRegSizeInBytes);
+  DumpRegisters<VRegister>(masm, dump_base, s_offset, kSRegSizeInBytes);
+  DumpRegisters<VRegister>(masm, dump_base, h_offset, kHRegSizeInBytes);
+
+  // Dump SVE registers.
+  if (CPUHas(CPUFeatures::kSVE)) {
+    DumpRegisters<ZRegister>(masm, dump_base, z_offset);
+    DumpRegisters<PRegister>(masm, dump_base, p_offset);
+
+    // Record the vector length.
+    __ Rdvl(tmp, kBitsPerByte);
+    __ Str(tmp, MemOperand(dump_base, vl_offset));
   }
 
   // Dump the flags.
   __ Mrs(tmp, NZCV);
   __ Str(tmp, MemOperand(dump_base, flags_offset));
 
-  // To dump the values that were in tmp amd dump, we need a new scratch
+  // To dump the values we used as scratch registers, we need a new scratch
   // register. We can use any of the already dumped registers since we can
   // easily restore them.
   Register dump2_base = x10;
-  Register dump2 = x11;
-  VIXL_ASSERT(!AreAliased(dump_base, dump, tmp, dump2_base, dump2));
+  VIXL_ASSERT(!scratch_registers.IncludesAliasOf(dump2_base));
+
+  VIXL_ASSERT(scratch_registers.IncludesAliasOf(dump_base));
+
+  // Ensure that we don't try to use the scratch registers again.
+  temps.ExcludeAll();
 
   // Don't lose the dump_ address.
   __ Mov(dump2_base, dump_base);
 
-  __ Pop(tmp, dump, dump_base, xzr);
-
-  __ Add(dump2, dump2_base, w_offset);
-  __ Str(dump_base_w,
-         MemOperand(dump2, dump_base.GetCode() * kWRegSizeInBytes));
-  __ Str(dump_w, MemOperand(dump2, dump.GetCode() * kWRegSizeInBytes));
-  __ Str(tmp_w, MemOperand(dump2, tmp.GetCode() * kWRegSizeInBytes));
+  __ PopCPURegList(scratch_registers);
 
-  __ Add(dump2, dump2_base, x_offset);
-  __ Str(dump_base, MemOperand(dump2, dump_base.GetCode() * kXRegSizeInBytes));
-  __ Str(dump, MemOperand(dump2, dump.GetCode() * kXRegSizeInBytes));
-  __ Str(tmp, MemOperand(dump2, tmp.GetCode() * kXRegSizeInBytes));
+  while (!scratch_registers.IsEmpty()) {
+    CPURegister reg = scratch_registers.PopLowestIndex();
+    Register x = reg.X();
+    Register w = reg.W();
+    unsigned code = reg.GetCode();
+    __ Str(x, MemOperand(dump2_base, x_offset + (code * kXRegSizeInBytes)));
+    __ Str(w, MemOperand(dump2_base, w_offset + (code * kWRegSizeInBytes)));
+  }
 
-  // Finally, restore dump2_base and dump2.
+  // Finally, restore dump2_base.
   __ Ldr(dump2_base,
-         MemOperand(dump2, dump2_base.GetCode() * kXRegSizeInBytes));
-  __ Ldr(dump2, MemOperand(dump2, dump2.GetCode() * kXRegSizeInBytes));
+         MemOperand(dump2_base,
+                    x_offset + (dump2_base.GetCode() * kXRegSizeInBytes)));
 
   completed_ = true;
 }
 
+uint64_t GetSignallingNan(int size_in_bits) {
+  switch (size_in_bits) {
+    case kHRegSize:
+      return Float16ToRawbits(kFP16SignallingNaN);
+    case kSRegSize:
+      return FloatToRawbits(kFP32SignallingNaN);
+    case kDRegSize:
+      return DoubleToRawbits(kFP64SignallingNaN);
+    default:
+      VIXL_UNIMPLEMENTED();
+      return 0;
+  }
+}
+
+bool CanRun(const CPUFeatures& required, bool* queried_can_run) {
+  bool log_if_missing = true;
+  if (queried_can_run != NULL) {
+    log_if_missing = !*queried_can_run;
+    *queried_can_run = true;
+  }
+
+#ifdef VIXL_INCLUDE_SIMULATOR_AARCH64
+  // The Simulator can run any test that VIXL can assemble.
+  USE(required);
+  USE(log_if_missing);
+  return true;
+#else
+  CPUFeatures cpu = CPUFeatures::InferFromOS();
+  // If InferFromOS fails, assume that basic features are present.
+  if (cpu.HasNoFeatures()) cpu = CPUFeatures::AArch64LegacyBaseline();
+  VIXL_ASSERT(cpu.Has(kInfrastructureCPUFeatures));
+
+  if (cpu.Has(required)) return true;
+
+  if (log_if_missing) {
+    CPUFeatures missing = required.Without(cpu);
+    // Note: This message needs to match REGEXP_MISSING_FEATURES from
+    // tools/threaded_test.py.
+    std::cout << "SKIPPED: Missing features: { " << missing << " }\n";
+    std::cout << "This test requires the following features to run its "
+                 "generated code on this CPU: "
+              << required << "\n";
+  }
+  return false;
+#endif
+}
+
 }  // namespace aarch64
 }  // namespace vixl
diff --git a/test/aarch64/test-utils-aarch64.h b/test/aarch64/test-utils-aarch64.h
index ee09d6b8..554cd83f 100644
--- a/test/aarch64/test-utils-aarch64.h
+++ b/test/aarch64/test-utils-aarch64.h
@@ -52,12 +52,43 @@ extern const float kFP32QuietNaN;
 extern const Float16 kFP16SignallingNaN;
 extern const Float16 kFP16QuietNaN;
 
-// Structure representing Q registers in a RegisterDump.
-struct vec128_t {
-  uint64_t l;
-  uint64_t h;
+// Vector registers don't naturally fit any C++ native type, so define a class
+// with convenient accessors.
+// Note that this has to be a POD type so that we can use 'offsetof' with it.
+template <int kSizeInBytes>
+struct VectorValue {
+  template <typename T>
+  T GetLane(int lane) const {
+    size_t lane_size = sizeof(T);
+    VIXL_CHECK(lane >= 0);
+    VIXL_CHECK(kSizeInBytes >= ((lane + 1) * lane_size));
+    T result;
+    memcpy(&result, bytes + (lane * lane_size), lane_size);
+    return result;
+  }
+
+  template <typename T>
+  void SetLane(int lane, T value) {
+    size_t lane_size = sizeof(value);
+    VIXL_CHECK(kSizeInBytes >= ((lane + 1) * lane_size));
+    memcpy(bytes + (lane * lane_size), &value, lane_size);
+  }
+
+  bool Equals(const VectorValue<kSizeInBytes>& other) const {
+    return memcmp(bytes, other.bytes, kSizeInBytes) == 0;
+  }
+
+  uint8_t bytes[kSizeInBytes];
 };
 
+// It would be convenient to make these subclasses, so we can provide convenient
+// constructors and utility methods specific to each register type, but we can't
+// do that because it makes the result a non-POD type, and then we can't use
+// 'offsetof' in RegisterDump::Dump.
+typedef VectorValue<kQRegSizeInBytes> QRegisterValue;
+typedef VectorValue<kZRegMaxSizeInBytes> ZRegisterValue;
+typedef VectorValue<kPRegMaxSizeInBytes> PRegisterValue;
+
 // RegisterDump: Object allowing integer, floating point and flags registers
 // to be saved to itself for future reference.
 class RegisterDump {
@@ -101,12 +132,12 @@ class RegisterDump {
 
   // VRegister accessors.
   inline uint16_t hreg_bits(unsigned code) const {
-    VIXL_ASSERT(FPRegAliasesMatch(code));
+    VIXL_ASSERT(VRegAliasesMatch(code));
     return dump_.h_[code];
   }
 
   inline uint32_t sreg_bits(unsigned code) const {
-    VIXL_ASSERT(FPRegAliasesMatch(code));
+    VIXL_ASSERT(VRegAliasesMatch(code));
     return dump_.s_[code];
   }
 
@@ -119,7 +150,7 @@ class RegisterDump {
   }
 
   inline uint64_t dreg_bits(unsigned code) const {
-    VIXL_ASSERT(FPRegAliasesMatch(code));
+    VIXL_ASSERT(VRegAliasesMatch(code));
     return dump_.d_[code];
   }
 
@@ -127,7 +158,78 @@ class RegisterDump {
     return RawbitsToDouble(dreg_bits(code));
   }
 
-  inline vec128_t qreg(unsigned code) const { return dump_.q_[code]; }
+  inline QRegisterValue qreg(unsigned code) const { return dump_.q_[code]; }
+
+  template <typename T>
+  inline T zreg_lane(unsigned code, int lane) const {
+    VIXL_ASSERT(VRegAliasesMatch(code));
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+    VIXL_ASSERT(lane < GetSVELaneCount(sizeof(T) * kBitsPerByte));
+    return dump_.z_[code].GetLane<T>(lane);
+  }
+
+  inline uint64_t zreg_lane(unsigned code,
+                            unsigned size_in_bits,
+                            int lane) const {
+    switch (size_in_bits) {
+      case kBRegSize:
+        return zreg_lane<uint8_t>(code, lane);
+      case kHRegSize:
+        return zreg_lane<uint16_t>(code, lane);
+      case kSRegSize:
+        return zreg_lane<uint32_t>(code, lane);
+      case kDRegSize:
+        return zreg_lane<uint64_t>(code, lane);
+    }
+    VIXL_UNREACHABLE();
+    return 0;
+  }
+
+  inline uint64_t preg_lane(unsigned code,
+                            unsigned p_bits_per_lane,
+                            int lane) const {
+    VIXL_ASSERT(CPUHas(CPUFeatures::kSVE));
+    VIXL_ASSERT(lane < GetSVELaneCount(p_bits_per_lane * kZRegBitsPerPRegBit));
+    // Load a chunk and extract the necessary bits. The chunk size is arbitrary.
+    typedef uint64_t Chunk;
+    const size_t kChunkSizeInBits = sizeof(Chunk) * kBitsPerByte;
+    VIXL_ASSERT(IsPowerOf2(p_bits_per_lane));
+    VIXL_ASSERT(p_bits_per_lane <= kChunkSizeInBits);
+
+    int chunk_index = (lane * p_bits_per_lane) / kChunkSizeInBits;
+    int bit_index = (lane * p_bits_per_lane) % kChunkSizeInBits;
+    Chunk chunk = dump_.p_[code].GetLane<Chunk>(chunk_index);
+    return (chunk >> bit_index) & GetUintMask(p_bits_per_lane);
+  }
+
+  inline int GetSVELaneCount(int lane_size_in_bits) const {
+    VIXL_ASSERT(lane_size_in_bits > 0);
+    VIXL_ASSERT((dump_.vl_ % lane_size_in_bits) == 0);
+    uint64_t count = dump_.vl_ / lane_size_in_bits;
+    VIXL_ASSERT(count <= INT_MAX);
+    return static_cast<int>(count);
+  }
+
+  template <typename T>
+  inline bool HasSVELane(T reg, int lane) const {
+    VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
+    return lane < GetSVELaneCount(reg.GetLaneSizeInBits());
+  }
+
+  template <typename T>
+  inline uint64_t GetSVELane(T reg, int lane) const {
+    VIXL_ASSERT(HasSVELane(reg, lane));
+    if (reg.IsZRegister()) {
+      return zreg_lane(reg.GetCode(), reg.GetLaneSizeInBits(), lane);
+    } else if (reg.IsPRegister()) {
+      VIXL_ASSERT((reg.GetLaneSizeInBits() % kZRegBitsPerPRegBit) == 0);
+      return preg_lane(reg.GetCode(),
+                       reg.GetLaneSizeInBits() / kZRegBitsPerPRegBit,
+                       lane);
+    } else {
+      VIXL_ABORT();
+    }
+  }
 
   // Stack pointer accessors.
   inline int64_t spreg() const {
@@ -168,12 +270,30 @@ class RegisterDump {
     return ((dump_.sp_ & kWRegMask) == dump_.wsp_);
   }
 
-  // As RegAliasesMatch, but for floating-point registers.
-  bool FPRegAliasesMatch(unsigned code) const {
+  // As RegAliasesMatch, but for Z and V registers.
+  bool VRegAliasesMatch(unsigned code) const {
     VIXL_ASSERT(IsComplete());
     VIXL_ASSERT(code < kNumberOfVRegisters);
-    return (((dump_.d_[code] & kSRegMask) == dump_.s_[code]) ||
-            ((dump_.s_[code] & kHRegMask) == dump_.h_[code]));
+    bool match = ((dump_.q_[code].GetLane<uint64_t>(0) == dump_.d_[code]) &&
+                  ((dump_.d_[code] & kSRegMask) == dump_.s_[code]) &&
+                  ((dump_.s_[code] & kHRegMask) == dump_.h_[code]));
+    if (CPUHas(CPUFeatures::kSVE)) {
+      bool z_match =
+          memcmp(&dump_.q_[code], &dump_.z_[code], kQRegSizeInBytes) == 0;
+      match = match && z_match;
+    }
+    return match;
+  }
+
+  // Record the CPUFeatures enabled when Dump was called.
+  CPUFeatures dump_cpu_features_;
+
+  // Convenience pass-through for CPU feature checks.
+  bool CPUHas(CPUFeatures::Feature feature0,
+              CPUFeatures::Feature feature1 = CPUFeatures::kNone,
+              CPUFeatures::Feature feature2 = CPUFeatures::kNone,
+              CPUFeatures::Feature feature3 = CPUFeatures::kNone) const {
+    return dump_cpu_features_.Has(feature0, feature1, feature2, feature3);
   }
 
   // Store all the dumped elements in a simple struct so the implementation can
@@ -189,7 +309,10 @@ class RegisterDump {
     uint16_t h_[kNumberOfVRegisters];
 
     // Vector registers.
-    vec128_t q_[kNumberOfVRegisters];
+    QRegisterValue q_[kNumberOfVRegisters];
+    ZRegisterValue z_[kNumberOfZRegisters];
+
+    PRegisterValue p_[kNumberOfPRegisters];
 
     // The stack pointer.
     uint64_t sp_;
@@ -201,6 +324,9 @@ class RegisterDump {
     // bit[29] : Carry
     // bit[28] : oVerflow
     uint64_t flags_;
+
+    // The SVE "VL" (vector length) in bits.
+    uint64_t vl_;
   } dump_;
 };
 
@@ -219,6 +345,9 @@ bool Equal64(uint64_t reference,
              const RegisterDump*,
              uint64_t result,
              ExpectedResult option = kExpectEqual);
+bool Equal128(QRegisterValue expected,
+              const RegisterDump*,
+              QRegisterValue result);
 
 bool EqualFP16(Float16 expected, const RegisterDump*, uint16_t result);
 bool EqualFP32(float expected, const RegisterDump*, float result);
@@ -261,6 +390,92 @@ bool NotEqual64(T0 reference, const RegisterDump* core, T1 result) {
   return !Equal64(reference, core, result, kExpectNotEqual);
 }
 
+bool EqualSVELane(uint64_t expected,
+                  const RegisterDump* core,
+                  const ZRegister& reg,
+                  int lane);
+
+bool EqualSVELane(uint64_t expected,
+                  const RegisterDump* core,
+                  const PRegister& reg,
+                  int lane);
+
+// Check that each SVE lane matches the corresponding expected[] value. The
+// highest-indexed array element maps to the lowest-numbered lane.
+template <typename T, int N, typename R>
+bool EqualSVE(const T (&expected)[N],
+              const RegisterDump* core,
+              const R& reg,
+              bool* printed_warning) {
+  VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
+  VIXL_ASSERT(reg.HasLaneSize());
+  // Evaluate and report errors on every lane, rather than just the first.
+  bool equal = true;
+  for (int lane = 0; lane < N; ++lane) {
+    if (!core->HasSVELane(reg, lane)) {
+      if (*printed_warning == false) {
+        *printed_warning = true;
+        printf(
+            "Warning: Ignoring SVE lanes beyond VL (%d bytes) "
+            "because the CPU does not implement them.\n",
+            core->GetSVELaneCount(kBRegSize));
+      }
+      break;
+    }
+    // Map the highest-indexed array element to the lowest-numbered lane.
+    equal = EqualSVELane(expected[N - lane - 1], core, reg, lane) && equal;
+  }
+  return equal;
+}
+
+// Check that each SVE lanes matches the `expected` value.
+template <typename R>
+bool EqualSVE(uint64_t expected,
+              const RegisterDump* core,
+              const R& reg,
+              bool* printed_warning) {
+  VIXL_ASSERT(reg.IsZRegister() || reg.IsPRegister());
+  VIXL_ASSERT(reg.HasLaneSize());
+  USE(printed_warning);
+  // Evaluate and report errors on every lane, rather than just the first.
+  bool equal = true;
+  for (int lane = 0; lane < core->GetSVELaneCount(reg.GetLaneSizeInBits());
+       ++lane) {
+    equal = EqualSVELane(expected, core, reg, lane) && equal;
+  }
+  return equal;
+}
+
+// Check that two Z or P registers are equal.
+template <typename R>
+bool EqualSVE(const R& expected,
+              const RegisterDump* core,
+              const R& result,
+              bool* printed_warning) {
+  VIXL_ASSERT(result.IsZRegister() || result.IsPRegister());
+  VIXL_ASSERT(AreSameFormat(expected, result));
+  USE(printed_warning);
+
+  // If the lane size is omitted, pick a default.
+  if (!result.HasLaneSize()) {
+    return EqualSVE(expected.VnB(), core, result.VnB(), printed_warning);
+  }
+
+  // Evaluate and report errors on every lane, rather than just the first.
+  bool equal = true;
+  int lane_size = result.GetLaneSizeInBits();
+  for (int lane = 0; lane < core->GetSVELaneCount(lane_size); ++lane) {
+    uint64_t expected_lane = core->GetSVELane(expected, lane);
+    equal = equal && EqualSVELane(expected_lane, core, result, lane);
+  }
+  return equal;
+}
+
+bool EqualMemory(const void* expected,
+                 const void* result,
+                 size_t size_in_bytes,
+                 size_t zero_offset = 0);
+
 // Populate the w, x and r arrays with registers from the 'allowed' mask. The
 // r array will be populated with <reg_size>-sized registers,
 //
@@ -308,6 +523,66 @@ void ClobberFP(MacroAssembler* masm,
 // Clobber or ClobberFP functions.
 void Clobber(MacroAssembler* masm, CPURegList reg_list);
 
+uint64_t GetSignallingNan(int size_in_bits);
+
+// This class acts as a drop-in replacement for VIXL's MacroAssembler, giving
+// CalculateSVEAddress public visibility.
+//
+// CalculateSVEAddress normally has protected visibility, but it's useful to
+// test it in isolation because it is the basis of all SVE non-scatter-gather
+// load and store fall-backs.
+class CalculateSVEAddressMacroAssembler : public vixl::aarch64::MacroAssembler {
+ public:
+  void CalculateSVEAddress(const Register& xd,
+                           const SVEMemOperand& addr,
+                           int vl_divisor_log2) {
+    MacroAssembler::CalculateSVEAddress(xd, addr, vl_divisor_log2);
+  }
+
+  void CalculateSVEAddress(const Register& xd, const SVEMemOperand& addr) {
+    MacroAssembler::CalculateSVEAddress(xd, addr);
+  }
+};
+
+// This class acts as a drop-in replacement for VIXL's MacroAssembler, with
+// fast NaN proparation mode switched on.
+class FastNaNPropagationMacroAssembler : public MacroAssembler {
+ public:
+  FastNaNPropagationMacroAssembler() {
+    SetFPNaNPropagationOption(FastNaNPropagation);
+  }
+};
+
+// This class acts as a drop-in replacement for VIXL's MacroAssembler, with
+// strict NaN proparation mode switched on.
+class StrictNaNPropagationMacroAssembler : public MacroAssembler {
+ public:
+  StrictNaNPropagationMacroAssembler() {
+    SetFPNaNPropagationOption(StrictNaNPropagation);
+  }
+};
+
+// If the required features are available, return true.
+// Otherwise:
+//  - Print a warning message, unless *queried_can_run indicates that we've
+//    already done so.
+//  - Return false.
+//
+// If *queried_can_run is NULL, it is treated as false. Otherwise, it is set to
+// true, regardless of the return value.
+//
+// The warning message printed on failure is used by tools/threaded_tests.py to
+// count skipped tests. A test must not print more than one such warning
+// message. It is safe to call CanRun multiple times per test, as long as
+// queried_can_run is propagated correctly between calls, and the first call to
+// CanRun requires every feature that is required by subsequent calls. If
+// queried_can_run is NULL, CanRun must not be called more than once per test.
+bool CanRun(const CPUFeatures& required, bool* queried_can_run = NULL);
+
+// PushCalleeSavedRegisters(), PopCalleeSavedRegisters() and Dump() use NEON, so
+// we need to enable it in the infrastructure code for each test.
+static const CPUFeatures kInfrastructureCPUFeatures(CPUFeatures::kNEON);
+
 }  // namespace aarch64
 }  // namespace vixl
 
diff --git a/test/aarch64/traces/sim-frint64x-2d-trace-aarch64.h b/test/aarch64/traces/sim-frint64x-2d-trace-aarch64.h
index e6f0a1a3..07fdee52 100644
--- a/test/aarch64/traces/sim-frint64x-2d-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64x-2d-trace-aarch64.h
@@ -203,8 +203,8 @@ const uint64_t kExpected_NEON_frint64x_2D[] = {
   0xc3e0000000000000, 0xc3e0000000000000,
   0xc3e0000000000000, 0xc3dfffffffffffff,
   0xc3dfffffffffffff, 0x43dfffffffffffff,
-  0x43dfffffffffffff, 0x43e0000000000000,
-  0x43e0000000000000, 0xc3e0000000000000,
+  0x43dfffffffffffff, 0xc3e0000000000000,
+  0xc3e0000000000000, 0xc3e0000000000000,
   0xc3e0000000000000, 0xc3e0000000000000,
   0xc3e0000000000000, 0xc1e0000000200000,
   0xc1e0000000200000, 0xc1e0000000200000,
diff --git a/test/aarch64/traces/sim-frint64x-2s-trace-aarch64.h b/test/aarch64/traces/sim-frint64x-2s-trace-aarch64.h
index f87aa711..3e127e0a 100644
--- a/test/aarch64/traces/sim-frint64x-2s-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64x-2s-trace-aarch64.h
@@ -133,8 +133,8 @@ const uint32_t kExpected_NEON_frint64x_2S[] = {
   0xdf000000, 0xdf000000,
   0xdf000000, 0xdeffffff,
   0xdeffffff, 0x5effffff,
-  0x5effffff, 0x5f000000,
-  0x5f000000, 0xdf000000,
+  0x5effffff, 0xdf000000,
+  0xdf000000, 0xdf000000,
   0xdf000000, 0xdf000000,
   0xdf000000, 0xcf000001,
   0xcf000001, 0xcf000000,
diff --git a/test/aarch64/traces/sim-frint64x-4s-trace-aarch64.h b/test/aarch64/traces/sim-frint64x-4s-trace-aarch64.h
index 7d44398f..84ae1643 100644
--- a/test/aarch64/traces/sim-frint64x-4s-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64x-4s-trace-aarch64.h
@@ -131,10 +131,10 @@ const uint32_t kExpected_NEON_frint64x_4S[] = {
   0xca800000, 0xca800000, 0xdf000000, 0xdf000000,
   0xca800000, 0xdf000000, 0xdf000000, 0xdeffffff,
   0xdf000000, 0xdf000000, 0xdeffffff, 0x5effffff,
-  0xdf000000, 0xdeffffff, 0x5effffff, 0x5f000000,
-  0xdeffffff, 0x5effffff, 0x5f000000, 0xdf000000,
-  0x5effffff, 0x5f000000, 0xdf000000, 0xdf000000,
-  0x5f000000, 0xdf000000, 0xdf000000, 0xcf000001,
+  0xdf000000, 0xdeffffff, 0x5effffff, 0xdf000000,
+  0xdeffffff, 0x5effffff, 0xdf000000, 0xdf000000,
+  0x5effffff, 0xdf000000, 0xdf000000, 0xdf000000,
+  0xdf000000, 0xdf000000, 0xdf000000, 0xcf000001,
   0xdf000000, 0xdf000000, 0xcf000001, 0xcf000000,
   0xdf000000, 0xcf000001, 0xcf000000, 0xceffffff,
   0xcf000001, 0xcf000000, 0xceffffff, 0x4effffff,
diff --git a/test/aarch64/traces/sim-frint64x-d-trace-aarch64.h b/test/aarch64/traces/sim-frint64x-d-trace-aarch64.h
index 725b012e..8f0c269b 100644
--- a/test/aarch64/traces/sim-frint64x-d-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64x-d-trace-aarch64.h
@@ -203,7 +203,7 @@ const uint64_t kExpected_frint64x_d[] = {
   0xc3e0000000000000,
   0xc3dfffffffffffff,
   0x43dfffffffffffff,
-  0x43e0000000000000,
+  0xc3e0000000000000,
   0xc3e0000000000000,
   0xc3e0000000000000,
   0xc1e0000000200000,
diff --git a/test/aarch64/traces/sim-frint64x-s-trace-aarch64.h b/test/aarch64/traces/sim-frint64x-s-trace-aarch64.h
index d09b2f78..3cffa565 100644
--- a/test/aarch64/traces/sim-frint64x-s-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64x-s-trace-aarch64.h
@@ -131,7 +131,7 @@ const uint32_t kExpected_frint64x_s[] = {
   0xdf000000,
   0xdeffffff,
   0x5effffff,
-  0x5f000000,
+  0xdf000000,
   0xdf000000,
   0xdf000000,
   0xcf000001,
diff --git a/test/aarch64/traces/sim-frint64z-2d-trace-aarch64.h b/test/aarch64/traces/sim-frint64z-2d-trace-aarch64.h
index a9777b50..c4814334 100644
--- a/test/aarch64/traces/sim-frint64z-2d-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64z-2d-trace-aarch64.h
@@ -203,8 +203,8 @@ const uint64_t kExpected_NEON_frint64z_2D[] = {
   0xc3e0000000000000, 0xc3e0000000000000,
   0xc3e0000000000000, 0xc3dfffffffffffff,
   0xc3dfffffffffffff, 0x43dfffffffffffff,
-  0x43dfffffffffffff, 0x43e0000000000000,
-  0x43e0000000000000, 0xc3e0000000000000,
+  0x43dfffffffffffff, 0xc3e0000000000000,
+  0xc3e0000000000000, 0xc3e0000000000000,
   0xc3e0000000000000, 0xc3e0000000000000,
   0xc3e0000000000000, 0xc1e0000000200000,
   0xc1e0000000200000, 0xc1e0000000200000,
diff --git a/test/aarch64/traces/sim-frint64z-2s-trace-aarch64.h b/test/aarch64/traces/sim-frint64z-2s-trace-aarch64.h
index 97544e5a..2195c1f1 100644
--- a/test/aarch64/traces/sim-frint64z-2s-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64z-2s-trace-aarch64.h
@@ -133,8 +133,8 @@ const uint32_t kExpected_NEON_frint64z_2S[] = {
   0xdf000000, 0xdf000000,
   0xdf000000, 0xdeffffff,
   0xdeffffff, 0x5effffff,
-  0x5effffff, 0x5f000000,
-  0x5f000000, 0xdf000000,
+  0x5effffff, 0xdf000000,
+  0xdf000000, 0xdf000000,
   0xdf000000, 0xdf000000,
   0xdf000000, 0xcf000001,
   0xcf000001, 0xcf000000,
diff --git a/test/aarch64/traces/sim-frint64z-4s-trace-aarch64.h b/test/aarch64/traces/sim-frint64z-4s-trace-aarch64.h
index 34640dba..d42e93a3 100644
--- a/test/aarch64/traces/sim-frint64z-4s-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64z-4s-trace-aarch64.h
@@ -131,10 +131,10 @@ const uint32_t kExpected_NEON_frint64z_4S[] = {
   0xca7ffffc, 0xca7ffffc, 0xdf000000, 0xdf000000,
   0xca7ffffc, 0xdf000000, 0xdf000000, 0xdeffffff,
   0xdf000000, 0xdf000000, 0xdeffffff, 0x5effffff,
-  0xdf000000, 0xdeffffff, 0x5effffff, 0x5f000000,
-  0xdeffffff, 0x5effffff, 0x5f000000, 0xdf000000,
-  0x5effffff, 0x5f000000, 0xdf000000, 0xdf000000,
-  0x5f000000, 0xdf000000, 0xdf000000, 0xcf000001,
+  0xdf000000, 0xdeffffff, 0x5effffff, 0xdf000000,
+  0xdeffffff, 0x5effffff, 0xdf000000, 0xdf000000,
+  0x5effffff, 0xdf000000, 0xdf000000, 0xdf000000,
+  0xdf000000, 0xdf000000, 0xdf000000, 0xcf000001,
   0xdf000000, 0xdf000000, 0xcf000001, 0xcf000000,
   0xdf000000, 0xcf000001, 0xcf000000, 0xceffffff,
   0xcf000001, 0xcf000000, 0xceffffff, 0x4effffff,
diff --git a/test/aarch64/traces/sim-frint64z-d-trace-aarch64.h b/test/aarch64/traces/sim-frint64z-d-trace-aarch64.h
index 5f96c65a..b65f68a3 100644
--- a/test/aarch64/traces/sim-frint64z-d-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64z-d-trace-aarch64.h
@@ -203,7 +203,7 @@ const uint64_t kExpected_frint64z_d[] = {
   0xc3e0000000000000,
   0xc3dfffffffffffff,
   0x43dfffffffffffff,
-  0x43e0000000000000,
+  0xc3e0000000000000,
   0xc3e0000000000000,
   0xc3e0000000000000,
   0xc1e0000000200000,
diff --git a/test/aarch64/traces/sim-frint64z-s-trace-aarch64.h b/test/aarch64/traces/sim-frint64z-s-trace-aarch64.h
index 1df9f782..35e06868 100644
--- a/test/aarch64/traces/sim-frint64z-s-trace-aarch64.h
+++ b/test/aarch64/traces/sim-frint64z-s-trace-aarch64.h
@@ -131,7 +131,7 @@ const uint32_t kExpected_frint64z_s[] = {
   0xdf000000,
   0xdeffffff,
   0x5effffff,
-  0x5f000000,
+  0xdf000000,
   0xdf000000,
   0xdf000000,
   0xcf000001,
diff --git a/test/test-api.cc b/test/test-api.cc
index 5e0001e6..b30230d6 100644
--- a/test/test-api.cc
+++ b/test/test-api.cc
@@ -262,20 +262,20 @@ TEST(CPUFeatures_iterator_api) {
 
   // Incrementable
   // - Incrementing has no effect on an empty CPUFeatures.
-  VIXL_CHECK(it3++ == CPUFeatures::kNone);
-  VIXL_CHECK(++it3 == CPUFeatures::kNone);
+  VIXL_CHECK(*it3++ == CPUFeatures::kNone);
+  VIXL_CHECK(*(++it3) == CPUFeatures::kNone);
   VIXL_CHECK(it3 == It(&f3, CPUFeatures::kNone));
   // - Incrementing moves to the next feature, wrapping around (through kNone).
   //   This test will need to be updated if the Feature enum is reordered.
-  VIXL_CHECK(it2_neon++ == CPUFeatures::kNEON);
-  VIXL_CHECK(it2_neon++ == CPUFeatures::kCRC32);
-  VIXL_CHECK(it2_neon++ == CPUFeatures::kNone);
-  VIXL_CHECK(it2_neon++ == CPUFeatures::kFP);
+  VIXL_CHECK(*it2_neon++ == CPUFeatures::kNEON);
+  VIXL_CHECK(*it2_neon++ == CPUFeatures::kCRC32);
+  VIXL_CHECK(*it2_neon++ == CPUFeatures::kNone);
+  VIXL_CHECK(*it2_neon++ == CPUFeatures::kFP);
   VIXL_CHECK(it2_neon == It(&f2, CPUFeatures::kNEON));
-  VIXL_CHECK(++it2_crc32 == CPUFeatures::kNone);
-  VIXL_CHECK(++it2_crc32 == CPUFeatures::kFP);
-  VIXL_CHECK(++it2_crc32 == CPUFeatures::kNEON);
-  VIXL_CHECK(++it2_crc32 == CPUFeatures::kCRC32);
+  VIXL_CHECK(*(++it2_crc32) == CPUFeatures::kNone);
+  VIXL_CHECK(*(++it2_crc32) == CPUFeatures::kFP);
+  VIXL_CHECK(*(++it2_crc32) == CPUFeatures::kNEON);
+  VIXL_CHECK(*(++it2_crc32) == CPUFeatures::kCRC32);
   VIXL_CHECK(it2_crc32 == It(&f2, CPUFeatures::kCRC32));
 }
 
@@ -313,7 +313,6 @@ TEST(CPUFeatures_iterator_loops) {
   }
   VIXL_CHECK(f3_list.size() == 0);
 
-#if __cplusplus >= 201103L
   std::vector<CPUFeatures::Feature> f2_list_cxx11;
   for (auto&& feature : f2) {
     f2_list_cxx11.push_back(feature);
@@ -328,16 +327,18 @@ TEST(CPUFeatures_iterator_loops) {
     f3_list_cxx11.push_back(feature);
   }
   VIXL_CHECK(f3_list_cxx11.size() == 0);
-#endif
 }
 
 
 TEST(CPUFeatures_empty) {
   // A default-constructed CPUFeatures has no features enabled.
-  CPUFeatures f;
-  for (CPUFeatures::const_iterator it = f.begin(); it != f.end(); ++it) {
+  CPUFeatures features;
+  for (auto f : features) {
+    USE(f);
     VIXL_ABORT();
   }
+  VIXL_CHECK(features.HasNoFeatures());
+  VIXL_CHECK(features.Count() == 0);
 }
 
 
@@ -377,24 +378,6 @@ TEST(CPUFeatures_format) {
   CPUFeaturesFormatHelper("FP, NEON, CRC32, Fcma", f);
   f.Combine(CPUFeatures::kSHA1);
   CPUFeaturesFormatHelper("FP, NEON, CRC32, SHA1, Fcma", f);
-
-  CPUFeaturesFormatHelper(
-      "ID register emulation, "
-      // Armv8.0
-      "FP, NEON, CRC32, "
-      "AES, SHA1, SHA2, Pmull1Q, "
-      // Armv8.1
-      "Atomics, LORegions, RDM, "
-      // Armv8.2
-      "SVE, DotProduct, FPHalf, NEONHalf, RAS, DCPoP, DCCVADP, SHA3, SHA512, "
-      "SM3, SM4, "
-      // Armv8.3
-      "PAuth, PAuthQARMA, PAuthGeneric, PAuthGenericQARMA, JSCVT, Fcma, RCpc, "
-      // Armv8.4
-      "RCpc (imm), FlagM, USCAT, FHM, DIT, "
-      // Armv8.5
-      "BTI, AXFlag, RNG, Frint (bounded)",
-      CPUFeatures::All());
 }
 
 
@@ -402,17 +385,16 @@ static void CPUFeaturesPredefinedResultCheckHelper(
     const std::set<CPUFeatures::Feature>& unexpected,
     const std::set<CPUFeatures::Feature>& expected) {
   // Print a helpful diagnostic before checking the result.
-  typedef std::set<CPUFeatures::Feature>::const_iterator It;
   if (!unexpected.empty()) {
     std::cout << "Unexpected features:\n";
-    for (It it = unexpected.begin(); it != unexpected.end(); ++it) {
-      std::cout << "  " << *it << "\n";
+    for (auto f : unexpected) {
+      std::cout << "  " << f << "\n";
     }
   }
   if (!expected.empty()) {
     std::cout << "Missing features:\n";
-    for (It it = expected.begin(); it != expected.end(); ++it) {
-      std::cout << "  " << *it << "\n";
+    for (auto f : expected) {
+      std::cout << "  " << f << "\n";
     }
   }
   VIXL_CHECK(unexpected.empty() && expected.empty());
@@ -420,28 +402,29 @@ static void CPUFeaturesPredefinedResultCheckHelper(
 
 
 TEST(CPUFeatures_predefined_legacy) {
-  CPUFeatures f = CPUFeatures::AArch64LegacyBaseline();
+  CPUFeatures features = CPUFeatures::AArch64LegacyBaseline();
   std::set<CPUFeatures::Feature> unexpected;
   std::set<CPUFeatures::Feature> expected;
   expected.insert(CPUFeatures::kFP);
   expected.insert(CPUFeatures::kNEON);
   expected.insert(CPUFeatures::kCRC32);
 
-  for (CPUFeatures::const_iterator it = f.begin(); it != f.end(); ++it) {
-    if (expected.erase(*it) == 0) unexpected.insert(*it);
+  for (auto f : features) {
+    if (expected.erase(f) == 0) unexpected.insert(f);
   }
   CPUFeaturesPredefinedResultCheckHelper(unexpected, expected);
 }
 
 
 TEST(CPUFeatures_predefined_all) {
-  CPUFeatures f = CPUFeatures::All();
+  CPUFeatures features = CPUFeatures::All();
   std::set<CPUFeatures::Feature> found;
 
-  for (CPUFeatures::const_iterator it = f.begin(); it != f.end(); ++it) {
-    found.insert(*it);
+  for (auto f : features) {
+    found.insert(f);
   }
   VIXL_CHECK(found.size() == CPUFeatures::kNumberOfFeatures);
+  VIXL_CHECK(found.size() == features.Count());
 }
 
 // The CPUFeaturesScope constructor is templated, and needs an object which
@@ -502,7 +485,10 @@ TEST(CPUFeaturesScope) {
       CPUFeatures auth(CPUFeatures::kPAuth,
                        CPUFeatures::kPAuthQARMA,
                        CPUFeatures::kPAuthGeneric,
-                       CPUFeatures::kPAuthGenericQARMA);
+                       CPUFeatures::kPAuthGenericQARMA,
+                       CPUFeatures::kPAuthEnhancedPAC2,
+                       CPUFeatures::kPAuthFPAC,
+                       CPUFeatures::kPAuthFPACCombined);
 
       CPUFeaturesScope inner(&outer, auth);
       VIXL_CHECK(inner.GetCPUFeatures() == &cpu);
@@ -515,6 +501,11 @@ TEST(CPUFeaturesScope) {
     VIXL_CHECK(original_inner.Has(cpu));
   }
 
+  {
+    // Scopes can be initialised with no features.
+    CPUFeaturesScope scope(&top_level);
+  }
+
   // Check for equivalence.
   VIXL_CHECK(cpu.Has(original_outer));
   VIXL_CHECK(original_outer.Has(cpu));
diff --git a/test/test-code-buffer.cc b/test/test-code-buffer.cc
index b2c16a35..26da7f71 100644
--- a/test/test-code-buffer.cc
+++ b/test/test-code-buffer.cc
@@ -72,7 +72,7 @@ TEST(defaults) {
 TEST(reset) {
   CodeBuffer buffer;
   // Update the buffer by writing to it.
-  buffer.Emit("dummy data");
+  buffer.Emit("placeholder data");
   VIXL_CHECK(buffer.IsDirty());
   VIXL_CHECK(buffer.GetSizeInBytes() > 0);
   // Calling Reset() should reset it back to its default state. (It does not
diff --git a/test/test-runner.cc b/test/test-runner.cc
index b0e1d11b..092a4ed8 100644
--- a/test/test-runner.cc
+++ b/test/test-runner.cc
@@ -49,26 +49,9 @@ bool vixl::Test::disassemble_infrastructure_ = false;
 // No colour highlight by default.
 bool vixl::Test::coloured_trace_ = false;
 
-// No instruction statistics by default.
-bool vixl::Test::instruction_stats_ = false;
-
 // Don't generate traces by default.
 bool vixl::Test::generate_test_trace_ = false;
 
-// Instantiate a Test and append it to the linked list.
-vixl::Test::Test(const char* name, TestFunction* callback)
-    : name_(name), callback_(callback), next_(NULL) {
-  // Append this test to the linked list.
-  if (first_ == NULL) {
-    VIXL_ASSERT(last_ == NULL);
-    first_ = this;
-  } else {
-    last_->next_ = this;
-  }
-  last_ = this;
-}
-
-
 // Look for 'search' in the arguments.
 static bool IsInArgs(const char* search, int argc, char* argv[]) {
   for (int i = 1; i < argc; i++) {
@@ -118,7 +101,6 @@ static void PrintHelpMessage() {
       "--disassemble-test-code  "
       "As above, but don't disassemble infrastructure code.\n"
       "--coloured_trace         Generate coloured trace.\n"
-      "--instruction_stats      Log instruction statistics to vixl_stats.csv.\n"
       "--generate_test_trace    "
       "Print result traces for SIM_* and TRACE_* tests.\n");
 }
@@ -179,10 +161,6 @@ int main(int argc, char* argv[]) {
     vixl::Test::set_disassemble_infrastructure(false);
   }
 
-  if (IsInArgs("--instruction-stats", argc, argv)) {
-    vixl::Test::set_instruction_stats(true);
-  }
-
   if (IsInArgs("--generate-test-trace", argc, argv)) {
     vixl::Test::set_generate_test_trace(true);
   }
@@ -202,7 +180,7 @@ int main(int argc, char* argv[]) {
     // Run all registered tests.
     for (vixl::Test* c = vixl::Test::first(); c != NULL; c = c->next()) {
       printf("Running %s\n", c->name());
-      c->callback()();
+      c->run();
     }
 
   } else {
@@ -218,7 +196,7 @@ int main(int argc, char* argv[]) {
         vixl::Test* c;
         for (c = vixl::Test::first(); c != NULL; c = c->next()) {
           if (strcmp(c->name(), argv[i]) == 0) {
-            c->callback()();
+            c->run();
             break;
           }
         }
@@ -233,3 +211,23 @@ int main(int argc, char* argv[]) {
 
   return EXIT_SUCCESS;
 }
+
+void vixl::Test::set_callback(TestFunction* callback) {
+  callback_ = callback;
+  callback_with_config_ = NULL;
+}
+
+void vixl::Test::set_callback(TestFunctionWithConfig* callback) {
+  callback_ = NULL;
+  callback_with_config_ = callback;
+}
+
+void vixl::Test::run() {
+  if (callback_ == NULL) {
+    VIXL_ASSERT(callback_with_config_ != NULL);
+    callback_with_config_(this);
+  } else {
+    VIXL_ASSERT(callback_with_config_ == NULL);
+    callback_();
+  }
+}
diff --git a/test/test-runner.h b/test/test-runner.h
index 45303cf0..ffc8c2ad 100644
--- a/test/test-runner.h
+++ b/test/test-runner.h
@@ -28,19 +28,48 @@
 #define TEST_TEST_H_
 
 #include "utils-vixl.h"
+#include "aarch64/instructions-aarch64.h"
 
 namespace vixl {
 
 // Each actual test is represented by a Test instance.
 // Tests are appended to a static linked list upon creation.
 class Test {
-  typedef void(TestFunction)();
-
  public:
-  Test(const char* name, TestFunction* callback);
+  // Most tests require no per-test configuration, and so take no arguments. A
+  // few tests require dynamic configuration, and are passed a `Test` object.
+  template <typename Fn>
+  Test(const char* name, Fn* callback)
+      : name_(name), sve_vl_(aarch64::kZRegMinSize), next_(NULL) {
+    set_callback(callback);
+    // Append this test to the linked list.
+    if (first_ == NULL) {
+      VIXL_ASSERT(last_ == NULL);
+      first_ = this;
+    } else {
+      last_->next_ = this;
+    }
+    last_ = this;
+  }
 
   const char* name() { return name_; }
-  TestFunction* callback() { return callback_; }
+  void run();
+
+  // The SVE vector length can be configured by each test, based on either
+  // hardware feature detection (in the test itself) or Simulator configuration.
+  int sve_vl_in_bits() const { return sve_vl_; }
+  void set_sve_vl_in_bits(unsigned sve_vl) {
+    VIXL_ASSERT(sve_vl >= aarch64::kZRegMinSize);
+    VIXL_ASSERT(sve_vl <= aarch64::kZRegMaxSize);
+    VIXL_ASSERT((sve_vl % aarch64::kZRegMinSize) == 0);
+    sve_vl_ = sve_vl;
+  }
+
+  int sve_vl_in_bytes() const {
+    VIXL_ASSERT((sve_vl_ % kBitsPerByte) == 0);
+    return sve_vl_ / kBitsPerByte;
+  }
+
   static Test* first() { return first_; }
   static Test* last() { return last_; }
   Test* next() { return next_; }
@@ -64,16 +93,24 @@ class Test {
   }
   static bool coloured_trace() { return coloured_trace_; }
   static void set_coloured_trace(bool value) { coloured_trace_ = value; }
-  static bool instruction_stats() { return instruction_stats_; }
-  static void set_instruction_stats(bool value) { instruction_stats_ = value; }
   static bool generate_test_trace() { return generate_test_trace_; }
   static void set_generate_test_trace(bool value) {
     generate_test_trace_ = value;
   }
 
+  typedef void(TestFunction)();
+  typedef void(TestFunctionWithConfig)(Test* config);
+
  private:
   const char* name_;
+
   TestFunction* callback_;
+  TestFunctionWithConfig* callback_with_config_;
+
+  void set_callback(TestFunction* callback);
+  void set_callback(TestFunctionWithConfig* callback);
+
+  int sve_vl_;
 
   static Test* first_;
   static Test* last_;
@@ -86,7 +123,6 @@ class Test {
   static bool disassemble_;
   static bool disassemble_infrastructure_;
   static bool coloured_trace_;
-  static bool instruction_stats_;
   static bool generate_test_trace_;
 };
 
diff --git a/test/test-trace-reference/log-all b/test/test-trace-reference/log-all
index 3d8a3ef5..7f4dc150 100644
--- a/test/test-trace-reference/log-all
+++ b/test/test-trace-reference/log-all
@@ -1,119 +1,332 @@
-#    x0: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0300003000300303
-#    x4: 0x0400004000400404
-#    x5: 0x0500005000500505
-#    x6: 0x0600006000600606
-#    x7: 0x0700007000700707
-#    x8: 0x0800008000800808
-#    x9: 0x0900009000900909
-#   x10: 0x0a0000a000a00a0a
-#   x11: 0x0b0000b000b00b0b
-#   x12: 0x0c0000c000c00c0c
-#   x13: 0x0d0000d000d00d0d
-#   x14: 0x0e0000e000e00e0e
-#   x15: 0x0f0000f000f00f0f
-#   x16: 0x1000010001001010
-#   x17: 0x1100011001101111
-#   x18: 0x1200012001201212
-#   x19: 0x1300013001301313
-#   x20: 0x1400014001401414
-#   x21: 0x1500015001501515
-#   x22: 0x1600016001601616
-#   x23: 0x1700017001701717
-#   x24: 0x1800018001801818
-#   x25: 0x1900019001901919
-#   x26: 0x1a0001a001a01a1a
-#   x27: 0x1b0001b001b01b1b
-#   x28: 0x1c0001c001c01c1c
-#   x29: 0x1d0001d001d01d1d
-#    lr: 0x0000000000000000
-#    sp: 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00055555005555550000000000000000
-#    v1: 0x3ff0d2c63fcb514c3ff587933f9e0419
-#    v2: 0x4000d2c6404b514c40058793401e0419
-#    v3: 0x401570fb40385373401025ae406d0626
-#    v4: 0x4010d2c640cb514c40158793409e0419
-#    v5: 0x401fbc2d4090d04a401ae97840c5851f
-#    v6: 0x402570fb40b85373402025ae40ed0626
-#    v7: 0x402783f4415f16c34022d6a1410a4396
-#    v8: 0x4020d2c6414b514c40258793411e0419
-#    v9: 0x402d6dd3416491c9402838864131c49c
-#   v10: 0x402fbc2d4110d04a402ae9784145851f
-#   v11: 0x4028cf3e410c10f7402d9a6b415945a2
-#   v12: 0x403570fb41385373403025ae416d0626
-#   v13: 0x40342b7d41d5360140317e2841806354
-#   v14: 0x403783f441df16c34032d6a1418a4396
-#   v15: 0x40317a4f41c1768240342f1a419423d7
-#   v16: 0x4030d2c641cb514c40358793419e0419
-#   v17: 0x4033b55841f2b10e4036e00d41a7e45b
-#   v18: 0x403d6dd341e491c94038388641b1c49c
-#   v19: 0x403cc5aa41eef18b403990ff41bba4de
-#   v20: 0x403fbc2d4190d04a403ae97841c5851f
-#   v21: 0x403914a7419a3034403c41f241cf6561
-#   v22: 0x4038cf3e418c10f7403d9a6b41d945a2
-#   v23: 0x403ba7b141b670b1403ef2e441e325e4
-#   v24: 0x404570fb41b85373404025ae41ed0626
-#   v25: 0x404584be41a3b3324040d1eb41f6e667
-#   v26: 0x40442b7d4255360140417e2842006354
-#   v27: 0x40477f314250062040422a6442055375
-#   v28: 0x404783f4425f16c34042d6a1420a4396
-#   v29: 0x4046d78b425a66e2404382de420f33b7
-#   v30: 0x40417a4f4241768240442f1a421423d7
-#   v31: 0x40418e02424c46ad4044db57421913f8
+#             x0: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~
+#             x3: 0x0300003000300303
+#             x4: 0x0400004000400404
+#             x5: 0x0500005000500505
+#             x6: 0x0600006000600606
+#             x7: 0x0700007000700707
+#             x8: 0x0800008000800808
+#             x9: 0x0900009000900909
+#            x10: 0x0a0000a000a00a0a
+#            x11: 0x0b0000b000b00b0b
+#            x12: 0x0c0000c000c00c0c
+#            x13: 0x0d0000d000d00d0d
+#            x14: 0x0e0000e000e00e0e
+#            x15: 0x0f0000f000f00f0f
+#            x16: 0x1000010001001010
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+#            x21: 0x1500015001501515
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+#            x23: 0x1700017001701717
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+#            x27: 0x1b0001b001b01b1b
+#            x28: 0x1c0001c001c01c1c
+#            x29: 0x1d0001d001d01d1d
+#             lr: 0x0000000000000000
+#             sp: 0x~~~~~~~~~~~~~~~~
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+#      p6<47:32>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<63:48>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<79:64>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
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+#      p7<31:16>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1
+#      p7<47:32>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1
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+#      p8<31:16>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1
+#      p8<47:32>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p8<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1
+#      p8<79:64>: 0b 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#       p9<15:0>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
+#      p9<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#      p9<47:32>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0
+#      p9<63:48>: 0b 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
+#      p9<79:64>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1
+#      p10<15:0>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p10<31:16>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#     p10<47:32>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#     p10<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p10<79:64>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p11<15:0>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
+#     p11<31:16>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+#     p11<47:32>: 0b 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
+#     p11<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#     p11<79:64>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0
+#      p12<15:0>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p12<31:16>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p12<47:32>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+#     p12<63:48>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#     p12<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#      p13<15:0>: 0b 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<31:16>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<47:32>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p13<79:64>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
+#      p14<15:0>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<31:16>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<47:32>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<63:48>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<79:64>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#      p15<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p15<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
+#     p15<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
+#     p15<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
+#     p15<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#      FFR<15:0>: 0b 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
+#     FFR<31:16>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<47:32>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<63:48>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<79:64>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 0x~~~~~~~~~~~~~~~~  1a050083		adc w3, w4, w5
-#    x3: 0x0000000000900909
+#             w3:         0x00900909
 0x~~~~~~~~~~~~~~~~  9a0800e6		adc x6, x7, x8
-#    x6: 0x0f0000f000f00f0f
+#             x6: 0x0f0000f000f00f0f
 0x~~~~~~~~~~~~~~~~  3a0b0149		adcs w9, w10, w11
 # NZCV: N:0 Z:0 C:0 V:0
-#    x9: 0x0000000001501515
+#             w9:         0x01501515
 0x~~~~~~~~~~~~~~~~  ba0e01ac		adcs x12, x13, x14
 # NZCV: N:0 Z:0 C:0 V:0
-#   x12: 0x1b0001b001b01b1b
+#            x12: 0x1b0001b001b01b1b
 0x~~~~~~~~~~~~~~~~  0b11020f		add w15, w16, w17
-#   x15: 0x0000000002102121
+#            w15:         0x02102121
 0x~~~~~~~~~~~~~~~~  8b140272		add x18, x19, x20
-#   x18: 0x2700027002702727
+#            x18: 0x2700027002702727
 0x~~~~~~~~~~~~~~~~  2b1702d5		adds w21, w22, w23
 # NZCV: N:0 Z:0 C:0 V:0
-#   x21: 0x0000000002d02d2d
+#            w21:         0x02d02d2d
 0x~~~~~~~~~~~~~~~~  ab1a0338		adds x24, x25, x26
 # NZCV: N:0 Z:0 C:0 V:0
-#   x24: 0x3300033003303333
+#            x24: 0x3300033003303333
 0x~~~~~~~~~~~~~~~~  0a1d039b		and w27, w28, w29
-#   x27: 0x0000000001c01c1c
+#            w27:         0x01c01c1c
 0x~~~~~~~~~~~~~~~~  8a040062		and x2, x3, x4
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  6a0700c5		ands w5, w6, w7
 # NZCV: N:0 Z:0 C:0 V:0
-#    x5: 0x0000000000700707
+#             w5:         0x00700707
 0x~~~~~~~~~~~~~~~~  ea0a0128		ands x8, x9, x10
 # NZCV: N:0 Z:1 C:0 V:0
-#    x8: 0x0000000000000000
+#             x8: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  13007d8b		sbfx w11, w12, #0, #32
-#   x11: 0x0000000001b01b1b
+#            w11:         0x01b01b1b
 0x~~~~~~~~~~~~~~~~  9341fdcd		asr x13, x14, #1
-#   x13: 0x0700007000700707
+#            x13: 0x0700007000700707
 0x~~~~~~~~~~~~~~~~  1ad12a0f		asr w15, w16, w17
-#   x15: 0x0000000000000080
+#            w15:         0x00000080
 0x~~~~~~~~~~~~~~~~  9ad42a72		asr x18, x19, x20
-#   x18: 0x0000013000130013
+#            x18: 0x0000013000130013
 0x~~~~~~~~~~~~~~~~  33051ad5		bfxil w21, w22, #5, #2
-#   x21: 0x0000000002d02d2c
+#            w21:         0x02d02d2c
 0x~~~~~~~~~~~~~~~~  b3472317		bfxil x23, x24, #7, #2
-#   x23: 0x1700017001701716
+#            x23: 0x1700017001701716
 0x~~~~~~~~~~~~~~~~  0a3b0359		bic w25, w26, w27
-#   x25: 0x0000000000200202
+#            w25:         0x00200202
 0x~~~~~~~~~~~~~~~~  8a2203bc		bic x28, x29, x2
-#   x28: 0x1d0001d001d01d1d
+#            x28: 0x1d0001d001d01d1d
 0x~~~~~~~~~~~~~~~~  6a250083		bics w3, w4, w5
 # NZCV: N:0 Z:1 C:0 V:0
-#    x3: 0x0000000000000000
+#             w3:         0x00000000
 0x~~~~~~~~~~~~~~~~  ea2800e6		bics x6, x7, x8
 # NZCV: N:0 Z:0 C:0 V:0
-#    x6: 0x0700007000700707
+#             x6: 0x0700007000700707
 0x~~~~~~~~~~~~~~~~  3a4ae120		ccmn w9, w10, #nzcv, al
 # NZCV: N:0 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  3a4a0120		ccmn w9, w10, #nzcv, eq
@@ -139,30 +352,30 @@
 0x~~~~~~~~~~~~~~~~  fa5011e3		ccmp x15, x16, #nzCV, ne
 # NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1a922651		cinc w17, w18, lo
-#   x17: 0x0000000000130014
+#            w17:         0x00130014
 0x~~~~~~~~~~~~~~~~  1a923651		cinc w17, w18, hs
-#   x17: 0x0000000000130013
+#            w17:         0x00130013
 0x~~~~~~~~~~~~~~~~  9a949693		cinc x19, x20, hi
-#   x19: 0x1400014001401414
+#            x19: 0x1400014001401414
 0x~~~~~~~~~~~~~~~~  9a948693		cinc x19, x20, ls
-#   x19: 0x1400014001401415
+#            x19: 0x1400014001401415
 0x~~~~~~~~~~~~~~~~  5a9612d5		cinv w21, w22, eq
-#   x21: 0x0000000001601616
+#            w21:         0x01601616
 0x~~~~~~~~~~~~~~~~  5a9602d5		cinv w21, w22, ne
-#   x21: 0x00000000fe9fe9e9
+#            w21:         0xfe9fe9e9
 0x~~~~~~~~~~~~~~~~  da982317		cinv x23, x24, lo
-#   x23: 0xccfffccffccfcccc
+#            x23: 0xccfffccffccfcccc
 0x~~~~~~~~~~~~~~~~  da983317		cinv x23, x24, hs
-#   x23: 0x3300033003303333
+#            x23: 0x3300033003303333
 0x~~~~~~~~~~~~~~~~  d5033f5f		clrex
 0x~~~~~~~~~~~~~~~~  5ac01759		cls w25, w26
-#   x25: 0x0000000000000006
+#            w25:         0x00000006
 0x~~~~~~~~~~~~~~~~  dac0179b		cls x27, x28
-#   x27: 0x0000000000000002
+#            x27: 0x0000000000000002
 0x~~~~~~~~~~~~~~~~  5ac0105d		clz w29, w2
-#   x29: 0x0000000000000020
+#            w29:         0x00000020
 0x~~~~~~~~~~~~~~~~  dac01083		clz x3, x4
-#    x3: 0x0000000000000005
+#             x3: 0x0000000000000005
 0x~~~~~~~~~~~~~~~~  2b0600bf		cmn w5, w6
 # NZCV: N:0 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  ab0800ff		cmn x7, x8
@@ -172,606 +385,660 @@
 0x~~~~~~~~~~~~~~~~  eb0c017f		cmp x11, x12
 # NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  5a8e95cd		cneg w13, w14, hi
-#   x13: 0x0000000000e00e0e
+#            w13:         0x00e00e0e
 0x~~~~~~~~~~~~~~~~  5a8e85cd		cneg w13, w14, ls
-#   x13: 0x00000000ff1ff1f2
+#            w13:         0xff1ff1f2
 0x~~~~~~~~~~~~~~~~  da90160f		cneg x15, x16, eq
-#   x15: 0x1000010001001010
+#            x15: 0x1000010001001010
 0x~~~~~~~~~~~~~~~~  da90060f		cneg x15, x16, ne
-#   x15: 0xeffffefffeffeff0
+#            x15: 0xeffffefffeffeff0
 0x~~~~~~~~~~~~~~~~  1ad34251		crc32b w17, w18, w19
-#   x17: 0x00000000e963b635
+#            w17:         0xe963b635
 0x~~~~~~~~~~~~~~~~  1ad652b4		crc32cb w20, w21, w22
-#   x20: 0x00000000ad83ccb8
+#            w20:         0xad83ccb8
 0x~~~~~~~~~~~~~~~~  1ad95717		crc32ch w23, w24, w25
-#   x23: 0x000000003ed5525d
+#            w23:         0x3ed5525d
 0x~~~~~~~~~~~~~~~~  1adc5b7a		crc32cw w26, w27, w28
-#   x26: 0x00000000bc365145
+#            w26:         0xbc365145
 0x~~~~~~~~~~~~~~~~  1ac644a4		crc32h w4, w5, w6
-#    x4: 0x0000000000000070
+#             w4:         0x00000070
 0x~~~~~~~~~~~~~~~~  1ac94907		crc32w w7, w8, w9
-#    x7: 0x00000000b096abf4
+#             w7:         0xb096abf4
 0x~~~~~~~~~~~~~~~~  1a8f31cd		csel w13, w14, w15, lo
-#   x13: 0x0000000000e00e0e
+#            w13:         0x00e00e0e
 0x~~~~~~~~~~~~~~~~  1a8f21cd		csel w13, w14, w15, hs
-#   x13: 0x00000000feffeff0
+#            w13:         0xfeffeff0
 0x~~~~~~~~~~~~~~~~  9a928230		csel x16, x17, x18, hi
-#   x16: 0x0000013000130013
+#            x16: 0x0000013000130013
 0x~~~~~~~~~~~~~~~~  9a929230		csel x16, x17, x18, ls
-#   x16: 0x00000000e963b635
+#            x16: 0x00000000e963b635
 0x~~~~~~~~~~~~~~~~  1a9f17f3		cset w19, eq
-#   x19: 0x0000000000000000
+#            w19:         0x00000000
 0x~~~~~~~~~~~~~~~~  1a9f07f3		cset w19, ne
-#   x19: 0x0000000000000001
+#            w19:         0x00000001
 0x~~~~~~~~~~~~~~~~  9a9f27f4		cset x20, lo
-#   x20: 0x0000000000000001
+#            x20: 0x0000000000000001
 0x~~~~~~~~~~~~~~~~  9a9f37f4		cset x20, hs
-#   x20: 0x0000000000000000
+#            x20: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5a9f93f5		csetm w21, hi
-#   x21: 0x0000000000000000
+#            w21:         0x00000000
 0x~~~~~~~~~~~~~~~~  5a9f83f5		csetm w21, ls
-#   x21: 0x00000000ffffffff
+#            w21:         0xffffffff
 0x~~~~~~~~~~~~~~~~  da9f13f6		csetm x22, eq
-#   x22: 0x0000000000000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  da9f03f6		csetm x22, ne
-#   x22: 0xffffffffffffffff
+#            x22: 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  1a993717		csinc w23, w24, w25, lo
-#   x23: 0x0000000003303333
+#            w23:         0x03303333
 0x~~~~~~~~~~~~~~~~  1a992717		csinc w23, w24, w25, hs
-#   x23: 0x0000000000000007
+#            w23:         0x00000007
 0x~~~~~~~~~~~~~~~~  9a9c877a		csinc x26, x27, x28, hi
-#   x26: 0x1d0001d001d01d1e
+#            x26: 0x1d0001d001d01d1e
 0x~~~~~~~~~~~~~~~~  9a9c977a		csinc x26, x27, x28, ls
-#   x26: 0x0000000000000002
+#            x26: 0x0000000000000002
 0x~~~~~~~~~~~~~~~~  5a83005d		csinv w29, w2, w3, eq
-#   x29: 0x00000000fffffffa
+#            w29:         0xfffffffa
 0x~~~~~~~~~~~~~~~~  5a83105d		csinv w29, w2, w3, ne
-#   x29: 0x0000000000000000
+#            w29:         0x00000000
 0x~~~~~~~~~~~~~~~~  da8630a4		csinv x4, x5, x6, lo
-#    x4: 0x0000000000700707
+#             x4: 0x0000000000700707
 0x~~~~~~~~~~~~~~~~  da8620a4		csinv x4, x5, x6, hs
-#    x4: 0xf8ffff8fff8ff8f8
+#             x4: 0xf8ffff8fff8ff8f8
 0x~~~~~~~~~~~~~~~~  5a898507		csneg w7, w8, w9, hi
-#    x7: 0x00000000feafeaeb
+#             w7:         0xfeafeaeb
 0x~~~~~~~~~~~~~~~~  5a899507		csneg w7, w8, w9, ls
-#    x7: 0x0000000000000000
+#             w7:         0x00000000
 0x~~~~~~~~~~~~~~~~  da8c056a		csneg x10, x11, x12, eq
-#   x10: 0xe4fffe4ffe4fe4e5
+#            x10: 0xe4fffe4ffe4fe4e5
 0x~~~~~~~~~~~~~~~~  da8c156a		csneg x10, x11, x12, ne
-#   x10: 0x0000000001b01b1b
+#            x10: 0x0000000001b01b1b
 0x~~~~~~~~~~~~~~~~  d50b7a20		dc cvac, x0
 0x~~~~~~~~~~~~~~~~  d5033bbf		dmb ish
 0x~~~~~~~~~~~~~~~~  d5033b9f		dsb ish
 0x~~~~~~~~~~~~~~~~  4a2f01cd		eon w13, w14, w15
-#   x13: 0x0000000001e01e01
+#            w13:         0x01e01e01
 0x~~~~~~~~~~~~~~~~  ca320230		eon x16, x17, x18
-#   x16: 0xfffffecf168f49d9
+#            x16: 0xfffffecf168f49d9
 0x~~~~~~~~~~~~~~~~  4a150293		eor w19, w20, w21
-#   x19: 0x00000000ffffffff
+#            w19:         0xffffffff
 0x~~~~~~~~~~~~~~~~  ca1802f6		eor x22, x23, x24
-#   x22: 0x3300033003303334
+#            x22: 0x3300033003303334
 0x~~~~~~~~~~~~~~~~  139b2759		extr w25, w26, w27, #9
-#   x25: 0x0000000001000000
+#            w25:         0x01000000
 0x~~~~~~~~~~~~~~~~  93c22bbc		extr x28, x29, x2, #10
-#   x28: 0x0000000000000000
+#            x28: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  d503201f		nop
 0x~~~~~~~~~~~~~~~~  d50b7520		ic ivau, x0
 0x~~~~~~~~~~~~~~~~  d5033fdf		isb
 0x~~~~~~~~~~~~~~~~  88dffc03		ldar w3, [x0]
-#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c8dffc04		ldar x4, [x0]
-#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#             x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  08dffc05		ldarb w5, [x0]
-#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  08dffc06		ldarb w6, [x0]
-#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  48dffc07		ldarh w7, [x0]
-#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  48dffc08		ldarh w8, [x0]
-#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w8:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  887fa809		ldaxp w9, w10, [x0]
-#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w10:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c87fb00b		ldaxp x11, x12, [x0]
-#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  885ffc0d		ldaxr w13, [x0]
-#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#            w13:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c85ffc0e		ldaxr x14, [x0]
-#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  085ffc0f		ldaxrb w15, [x0]
-#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            w15:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  085ffc10		ldaxrb w16, [x0]
-#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            w16:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  485ffc11		ldaxrh w17, [x0]
-#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#            w17:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  485ffc12		ldaxrh w18, [x0]
-#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#            w18:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  28405013		ldnp w19, w20, [x0]
-#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#            w19:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w20:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a8405815		ldnp x21, x22, [x0]
-#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  29406017		ldp w23, w24, [x0]
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  28c16037		ldp w23, w24, [x1], #8
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  29c16037		ldp w23, w24, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            w23:         0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x17161514 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a9406819		ldp x25, x26, [x0]
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a8c16839		ldp x25, x26, [x1], #16
-#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a9c16839		ldp x25, x26, [x1, #16]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  6940701b		ldpsw x27, x28, [x0]
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000003020100
+#                                  ╙─ 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000007060504
+#                                  ╙─ 0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  68c1703b		ldpsw x27, x28, [x1], #8
-#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000033323130
+#                                  ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000037363534
+#                                  ╙─ 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  69c1703b		ldpsw x27, x28, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000043424140
+#                                  ╙─ 0x43424140 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000047464544
+#                                  ╙─ 0x47464544 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b940001d		ldr w29, [x0]
-#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b840443d		ldr w29, [x1], #4
-#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            w29:         0x43424140 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8404c3d		ldr w29, [x1, #4]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            w29:         0x4b4a4948 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f9400002		ldr x2, [x0]
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f8408422		ldr x2, [x1], #8
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f8408c22		ldr x2, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39400003		ldrb w3, [x0]
-#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38401423		ldrb w3, [x1], #1
-#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000058
+#                                  ╙─ 0x58 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38401c23		ldrb w3, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w3:         0x0000005a
+#                                  ╙─ 0x5a <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39400004		ldrb w4, [x0]
-#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38401424		ldrb w4, [x1], #1
-#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x0000005a
+#                                  ╙─ 0x5a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38401c24		ldrb w4, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x0000005c
+#                                  ╙─ 0x5c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  79400005		ldrh w5, [x0]
-#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78402425		ldrh w5, [x1], #2
-#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00005d5c
+#                                  ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78402c25		ldrh w5, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00006160
+#                                  ╙─ 0x6160 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  79400006		ldrh w6, [x0]
-#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78402426		ldrh w6, [x1], #2
-#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00006160
+#                                  ╙─ 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78402c26		ldrh w6, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00006564
+#                                  ╙─ 0x6564 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39c00007		ldrsb w7, [x0]
-#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38c01427		ldrsb w7, [x1], #1
-#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000064
+#                                  ╙─ 0x64 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38c01c27		ldrsb w7, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000066
+#                                  ╙─ 0x66 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39800008		ldrsb x8, [x0]
-#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38801428		ldrsb x8, [x1], #1
-#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000066
+#                                  ╙─ 0x66 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38801c28		ldrsb x8, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000068
+#                                  ╙─ 0x68 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  79c00009		ldrsh w9, [x0]
-#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78c02429		ldrsh w9, [x1], #2
-#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00006968
+#                                  ╙─ 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78c02c29		ldrsh w9, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00006d6c
+#                                  ╙─ 0x6d6c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7980000a		ldrsh x10, [x0]
-#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7880242a		ldrsh x10, [x1], #2
-#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000006d6c
+#                                  ╙─ 0x6d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78802c2a		ldrsh x10, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000007170
+#                                  ╙─ 0x7170 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b980000b		ldrsw x11, [x0]
-#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0000000003020100
+#                                  ╙─ 0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b880442b		ldrsw x11, [x1], #4
-#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0000000073727170
+#                                  ╙─ 0x73727170 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8804c2b		ldrsw x11, [x1, #4]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x11: 0x000000007b7a7978
+#                                  ╙─ 0x7b7a7978 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b840700c		ldur w12, [x0, #7]
-#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#            w12:         0x0a090807 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f840f00d		ldur x13, [x0, #15]
-#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#            x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  3840100e		ldurb w14, [x0, #1]
-#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#            w14:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  3840100f		ldurb w15, [x0, #1]
-#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#            w15:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78403010		ldurh w16, [x0, #3]
-#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#            w16:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78403011		ldurh w17, [x0, #3]
-#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#            w17:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38c01012		ldursb w18, [x0, #1]
-#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#            w18:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38801013		ldursb x19, [x0, #1]
-#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#            x19: 0x0000000000000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78c03014		ldursh w20, [x0, #3]
-#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#            w20:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78803015		ldursh x21, [x0, #3]
-#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#            x21: 0x0000000000000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8807016		ldursw x22, [x0, #7]
-#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#            x22: 0x000000000a090807
+#                                  ╙─ 0x0a090807 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  887f6017		ldxp w23, w24, [x0]
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c87f6819		ldxp x25, x26, [x0]
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  885f7c1b		ldxr w27, [x0]
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#            w27:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c85f7c1c		ldxr x28, [x0]
-#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  085f7c1d		ldxrb w29, [x0]
-#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  085f7c02		ldxrb w2, [x0]
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             w2:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  485f7c03		ldxrh w3, [x0]
-#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  485f7c04		ldxrh w4, [x0]
-#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  531e74c5		lsl w5, w6, #2
-#    x5: 0x0000000000019590
+#             w5:         0x00019590
 0x~~~~~~~~~~~~~~~~  d37df107		lsl x7, x8, #3
-#    x7: 0x0000000000000340
+#             x7: 0x0000000000000340
 0x~~~~~~~~~~~~~~~~  1acb2149		lsl w9, w10, w11
-#    x9: 0x0000000070000000
+#             w9:         0x70000000
 0x~~~~~~~~~~~~~~~~  9ace21ac		lsl x12, x13, x14
-#   x12: 0x2c2a28262422201e
+#            x12: 0x2c2a28262422201e
 0x~~~~~~~~~~~~~~~~  53047e0f		lsr w15, w16, #4
-#   x15: 0x0000000000000040
+#            w15:         0x00000040
 0x~~~~~~~~~~~~~~~~  d345fe51		lsr x17, x18, #5
-#   x17: 0x0000000000000000
+#            x17: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1ad52693		lsr w19, w20, w21
-#   x19: 0x0000000000000080
+#            w19:         0x00000080
 0x~~~~~~~~~~~~~~~~  9ad826f6		lsr x22, x23, x24
-#   x22: 0x0000000000302010
+#            x22: 0x0000000000302010
 0x~~~~~~~~~~~~~~~~  1b1b7359		madd w25, w26, w27, w28
-#   x25: 0x00000000371b0900
+#            w25:         0x371b0900
 0x~~~~~~~~~~~~~~~~  9b03105d		madd x29, x2, x3, x4
-#   x29: 0x0000000000000100
+#            x29: 0x0000000000000100
 0x~~~~~~~~~~~~~~~~  1b07fcc5		mneg w5, w6, w7
-#    x5: 0x00000000feb67b00
+#             w5:         0xfeb67b00
 0x~~~~~~~~~~~~~~~~  9b0afd28		mneg x8, x9, x10
-#    x8: 0xffffce5f00000000
+#             x8: 0xffffce5f00000000
 0x~~~~~~~~~~~~~~~~  2a0c03eb		mov w11, w12
-#   x11: 0x000000002422201e
+#            w11:         0x2422201e
 0x~~~~~~~~~~~~~~~~  aa0e03ed		mov x13, x14
-#   x13: 0x0000000000000001
+#            x13: 0x0000000000000001
 0x~~~~~~~~~~~~~~~~  7280104f		movk w15, #0x82
-#   x15: 0x0000000000000082
+#            x15: 0x0000000000000082
 0x~~~~~~~~~~~~~~~~  f2801070		movk x16, #0x83
-#   x16: 0x0000000000000083
+#            x16: 0x0000000000000083
 0x~~~~~~~~~~~~~~~~  12801091		mov w17, #0xffffff7b
-#   x17: 0x00000000ffffff7b
+#            x17: 0x00000000ffffff7b
 0x~~~~~~~~~~~~~~~~  928010b2		mov x18, #0xffffffffffffff7a
-#   x18: 0xffffffffffffff7a
+#            x18: 0xffffffffffffff7a
 0x~~~~~~~~~~~~~~~~  528010d3		mov w19, #0x86
-#   x19: 0x0000000000000086
+#            x19: 0x0000000000000086
 0x~~~~~~~~~~~~~~~~  d28010f4		mov x20, #0x87
-#   x20: 0x0000000000000087
+#            x20: 0x0000000000000087
 0x~~~~~~~~~~~~~~~~  1b18e6f6		msub w22, w23, w24, w25
-#   x22: 0x000000001b0e0500
+#            w22:         0x1b0e0500
 0x~~~~~~~~~~~~~~~~  9b1cf77a		msub x26, x27, x28, x29
-#   x26: 0xe3e9eff5fbff0100
+#            x26: 0xe3e9eff5fbff0100
 0x~~~~~~~~~~~~~~~~  1b047c62		mul w2, w3, w4
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             w2:         0x00010000
 0x~~~~~~~~~~~~~~~~  9b077cc5		mul x5, x6, x7
-#    x5: 0x0000000001498500
+#             x5: 0x0000000001498500
 0x~~~~~~~~~~~~~~~~  2a2903e8		mvn w8, w9
-#    x8: 0x000000008fffffff
+#             w8:         0x8fffffff
 0x~~~~~~~~~~~~~~~~  aa2b03ea		mvn x10, x11
-#   x10: 0xffffffffdbdddfe1
+#            x10: 0xffffffffdbdddfe1
 0x~~~~~~~~~~~~~~~~  4b0d03ec		neg w12, w13
-#   x12: 0x00000000ffffffff
+#            w12:         0xffffffff
 0x~~~~~~~~~~~~~~~~  cb0f03ee		neg x14, x15
-#   x14: 0xffffffffffffff7e
+#            x14: 0xffffffffffffff7e
 0x~~~~~~~~~~~~~~~~  6b1103f0		negs w16, w17
 # NZCV: N:0 Z:0 C:0 V:0
-#   x16: 0x0000000000000085
+#            w16:         0x00000085
 0x~~~~~~~~~~~~~~~~  eb1303f2		negs x18, x19
 # NZCV: N:1 Z:0 C:0 V:0
-#   x18: 0xffffffffffffff7a
+#            x18: 0xffffffffffffff7a
 0x~~~~~~~~~~~~~~~~  5a1503f4		ngc w20, w21
-#   x20: 0x00000000fffffbfc
+#            w20:         0xfffffbfc
 0x~~~~~~~~~~~~~~~~  da1703f6		ngc x22, x23
-#   x22: 0xfffffffffcfdfeff
+#            x22: 0xfffffffffcfdfeff
 0x~~~~~~~~~~~~~~~~  7a1903f8		ngcs w24, w25
 # NZCV: N:1 Z:0 C:0 V:0
-#   x24: 0x00000000c8e4f6ff
+#            w24:         0xc8e4f6ff
 0x~~~~~~~~~~~~~~~~  fa1b03fa		ngcs x26, x27
 # NZCV: N:1 Z:0 C:0 V:0
-#   x26: 0xfffffffffcfdfeff
+#            x26: 0xfffffffffcfdfeff
 0x~~~~~~~~~~~~~~~~  d503201f		nop
 0x~~~~~~~~~~~~~~~~  2a2203bc		orn w28, w29, w2
-#   x28: 0x00000000fffeffff
+#            w28:         0xfffeffff
 0x~~~~~~~~~~~~~~~~  aa250083		orn x3, x4, x5
-#    x3: 0xfffffffffeb67bff
+#             x3: 0xfffffffffeb67bff
 0x~~~~~~~~~~~~~~~~  2a0800e6		orr w6, w7, w8
-#    x6: 0x000000008fffffff
+#             w6:         0x8fffffff
 0x~~~~~~~~~~~~~~~~  aa0b0149		orr x9, x10, x11
-#    x9: 0xffffffffffffffff
+#             x9: 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  f8804000		prfum pldl1keep, [x0, #4]
 0x~~~~~~~~~~~~~~~~  f8801000		prfum pldl1keep, [x0, #1]
 0x~~~~~~~~~~~~~~~~  5ac001ac		rbit w12, w13
-#   x12: 0x0000000080000000
+#            w12:         0x80000000
 0x~~~~~~~~~~~~~~~~  dac001ee		rbit x14, x15
-#   x14: 0x4100000000000000
+#            x14: 0x4100000000000000
 0x~~~~~~~~~~~~~~~~  5ac00a30		rev w16, w17
-#   x16: 0x000000007bffffff
+#            w16:         0x7bffffff
 0x~~~~~~~~~~~~~~~~  dac00e72		rev x18, x19
-#   x18: 0x8600000000000000
+#            x18: 0x8600000000000000
 0x~~~~~~~~~~~~~~~~  5ac006b4		rev16 w20, w21
-#   x20: 0x0000000000000304
+#            w20:         0x00000304
 0x~~~~~~~~~~~~~~~~  dac006f6		rev16 x22, x23
-#   x22: 0x0000000002030001
+#            x22: 0x0000000002030001
 0x~~~~~~~~~~~~~~~~  dac00b38		rev32 x24, x25
-#   x24: 0x0000000000091b37
+#            x24: 0x0000000000091b37
 0x~~~~~~~~~~~~~~~~  1adc2f7a		ror w26, w27, w28
-#   x26: 0x0000000006040200
+#            w26:         0x06040200
 0x~~~~~~~~~~~~~~~~  9ac32c5d		ror x29, x2, x3
-#   x29: 0x0000000000020000
+#            x29: 0x0000000000020000
 0x~~~~~~~~~~~~~~~~  5a0600a4		sbc w4, w5, w6
-#    x4: 0x0000000071498500
+#             w4:         0x71498500
 0x~~~~~~~~~~~~~~~~  da090107		sbc x7, x8, x9
-#    x7: 0x000000008fffffff
+#             x7: 0x000000008fffffff
 0x~~~~~~~~~~~~~~~~  7a0c016a		sbcs w10, w11, w12
 # NZCV: N:1 Z:0 C:0 V:1
-#   x10: 0x00000000a422201d
+#            w10:         0xa422201d
 0x~~~~~~~~~~~~~~~~  fa0f01cd		sbcs x13, x14, x15
 # NZCV: N:0 Z:0 C:1 V:0
-#   x13: 0x40ffffffffffff7d
+#            x13: 0x40ffffffffffff7d
 0x~~~~~~~~~~~~~~~~  131e0a30		sbfiz w16, w17, #2, #3
-#   x16: 0x000000000000000c
+#            w16:         0x0000000c
 0x~~~~~~~~~~~~~~~~  937c1272		sbfiz x18, x19, #4, #5
-#   x18: 0x0000000000000060
+#            x18: 0x0000000000000060
 0x~~~~~~~~~~~~~~~~  130632f6		sbfx w22, w23, #6, #7
-#   x22: 0x0000000000000004
+#            w22:         0x00000004
 0x~~~~~~~~~~~~~~~~  93484338		sbfx x24, x25, #8, #9
-#   x24: 0xffffffffffffff09
+#            x24: 0xffffffffffffff09
 0x~~~~~~~~~~~~~~~~  1adc0f7a		sdiv w26, w27, w28
-#   x26: 0x00000000fffffcff
+#            w26:         0xfffffcff
 0x~~~~~~~~~~~~~~~~  9ac30c5d		sdiv x29, x2, x3
-#   x29: 0x0000000000000000
+#            x29: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9b4e7dac		smulh x12, x13, x14
-#   x12: 0x1080ffffffffffde
+#            x12: 0x1080ffffffffffde
 0x~~~~~~~~~~~~~~~~  889ffc12		stlr w18, [x0]
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#      x18<31:0>:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c89ffc13		stlr x19, [x0]
-#   x19: 0x0000000000000086 -> 0x~~~~~~~~~~~~~~~~
+#      x19<63:0>: 0x0000000000000086 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  089ffc14		stlrb w20, [x0]
-#   w20<7:0>:          0x04 -> 0x~~~~~~~~~~~~~~~~
+#       x20<7:0>:               0x04 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  089ffc15		stlrb w21, [x0]
-#   w21<7:0>:          0x03 -> 0x~~~~~~~~~~~~~~~~
+#       x21<7:0>:               0x03 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  489ffc16		stlrh w22, [x0]
-#   w22<15:0>:       0x0004 -> 0x~~~~~~~~~~~~~~~~
+#      x22<15:0>:             0x0004 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  489ffc17		stlrh w23, [x0]
-#   w23<15:0>:       0x0100 -> 0x~~~~~~~~~~~~~~~~
+#      x23<15:0>:             0x0100 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  8838e819		stlxp w24, w25, w26, [x0]
-#   x24: 0x0000000000000001
+#            w24:         0x00000001
 0x~~~~~~~~~~~~~~~~  c83bf41c		stlxp w27, x28, x29, [x0]
-#   x27: 0x0000000000000001
+#            w27:         0x00000001
 0x~~~~~~~~~~~~~~~~  8802fc03		stlxr w2, w3, [x0]
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             w2:         0x00000001
 0x~~~~~~~~~~~~~~~~  c804fc05		stlxr w4, x5, [x0]
-#    x4: 0x0000000000000001
+#             w4:         0x00000001
 0x~~~~~~~~~~~~~~~~  0806fc07		stlxrb w6, w7, [x0]
-#    x6: 0x0000000000000001
+#             w6:         0x00000001
 0x~~~~~~~~~~~~~~~~  0808fc09		stlxrb w8, w9, [x0]
-#    x8: 0x0000000000000001
+#             w8:         0x00000001
 0x~~~~~~~~~~~~~~~~  480afc0b		stlxrh w10, w11, [x0]
-#   x10: 0x0000000000000001
+#            w10:         0x00000001
 0x~~~~~~~~~~~~~~~~  480cfc0d		stlxrh w12, w13, [x0]
-#   x12: 0x0000000000000001
+#            w12:         0x00000001
 0x~~~~~~~~~~~~~~~~  28003c0e		stnp w14, w15, [x0]
-#   w14:         0x00000000 -> 0x~~~~~~~~~~~~~~~~
-#   w15:         0x00000082 -> 0x~~~~~~~~~~~~~~~~
+#      x14<31:0>:         0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      x15<31:0>:         0x00000082 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a8004410		stnp x16, x17, [x0]
-#   x16: 0x000000000000000c -> 0x~~~~~~~~~~~~~~~~
-#   x17: 0x00000000ffffff7b -> 0x~~~~~~~~~~~~~~~~
+#      x16<63:0>: 0x000000000000000c -> 0x~~~~~~~~~~~~~~~~
+#      x17<63:0>: 0x00000000ffffff7b -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  29004c12		stp w18, w19, [x0]
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+#      x18<31:0>:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#      x19<31:0>:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  28814c32		stp w18, w19, [x1], #8
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x18<31:0>:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#      x19<31:0>:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  29814c32		stp w18, w19, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x18<31:0>:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#      x19<31:0>:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a9005414		stp x20, x21, [x0]
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+#      x20<63:0>: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#      x21<63:0>: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a8815434		stp x20, x21, [x1], #16
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x20<63:0>: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#      x21<63:0>: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a9815434		stp x20, x21, [x1, #16]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x20<63:0>: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#      x21<63:0>: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b9000016		str w22, [x0]
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+#      x22<31:0>:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8004436		str w22, [x1], #4
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x22<31:0>:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8004c36		str w22, [x1, #4]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x22<31:0>:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f9000017		str x23, [x0]
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+#      x23<63:0>: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f8008437		str x23, [x1], #8
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x23<63:0>: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f8008c37		str x23, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x23<63:0>: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39000018		strb w24, [x0]
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+#       x24<7:0>:               0x01 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001438		strb w24, [x1], #1
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       x24<7:0>:               0x01 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001c38		strb w24, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#       x24<7:0>:               0x01 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39000019		strb w25, [x0]
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+#       x25<7:0>:               0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001439		strb w25, [x1], #1
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       x25<7:0>:               0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001c39		strb w25, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#       x25<7:0>:               0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7900001a		strh w26, [x0]
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+#      x26<15:0>:             0xfcff -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7800243a		strh w26, [x1], #2
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x26<15:0>:             0xfcff -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78002c3a		strh w26, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x26<15:0>:             0xfcff -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7900001b		strh w27, [x0]
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+#      x27<15:0>:             0x0001 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7800243b		strh w27, [x1], #2
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x27<15:0>:             0x0001 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78002c3b		strh w27, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x27<15:0>:             0x0001 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b800701c		stur w28, [x0, #7]
-#   w28:         0xfffeffff -> 0x~~~~~~~~~~~~~~~~
+#      x28<31:0>:         0xfffeffff -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f800f01d		stur x29, [x0, #15]
-#   x29: 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      x29<63:0>: 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001002		sturb w2, [x0, #1]
-#    w2<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+#        x2<7:0>:               0x01 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001003		sturb w3, [x0, #1]
-#    w3<7:0>:          0xff -> 0x~~~~~~~~~~~~~~~~
+#        x3<7:0>:               0xff -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78003004		sturh w4, [x0, #3]
-#    w4<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+#       x4<15:0>:             0x0001 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78003005		sturh w5, [x0, #3]
-#    w5<15:0>:       0x8500 -> 0x~~~~~~~~~~~~~~~~
+#       x5<15:0>:             0x8500 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  88262007		stxp w6, w7, w8, [x0]
-#    x6: 0x0000000000000001
+#             w6:         0x00000001
 0x~~~~~~~~~~~~~~~~  c8292c0a		stxp w9, x10, x11, [x0]
-#    x9: 0x0000000000000001
+#             w9:         0x00000001
 0x~~~~~~~~~~~~~~~~  880c7c0d		stxr w12, w13, [x0]
-#   x12: 0x0000000000000001
+#            w12:         0x00000001
 0x~~~~~~~~~~~~~~~~  c80e7c0f		stxr w14, x15, [x0]
-#   x14: 0x0000000000000001
+#            w14:         0x00000001
 0x~~~~~~~~~~~~~~~~  08107c11		stxrb w16, w17, [x0]
-#   x16: 0x0000000000000001
+#            w16:         0x00000001
 0x~~~~~~~~~~~~~~~~  08127c13		stxrb w18, w19, [x0]
-#   x18: 0x0000000000000001
+#            w18:         0x00000001
 0x~~~~~~~~~~~~~~~~  48147c15		stxrh w20, w21, [x0]
-#   x20: 0x0000000000000001
+#            w20:         0x00000001
 0x~~~~~~~~~~~~~~~~  48167c17		stxrh w22, w23, [x0]
-#   x22: 0x0000000000000001
+#            w22:         0x00000001
 0x~~~~~~~~~~~~~~~~  4b1a0338		sub w24, w25, w26
-#   x24: 0x00000000371b0c01
+#            w24:         0x371b0c01
 0x~~~~~~~~~~~~~~~~  cb1d039b		sub x27, x28, x29
-#   x27: 0x00000000fffeffff
+#            x27: 0x00000000fffeffff
 0x~~~~~~~~~~~~~~~~  6b040062		subs w2, w3, w4
 # NZCV: N:1 Z:0 C:1 V:0
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             w2:         0xfeb67bfe
 0x~~~~~~~~~~~~~~~~  eb0700c5		subs x5, x6, x7
 # NZCV: N:1 Z:0 C:0 V:0
-#    x5: 0xffffffff70000002
+#             x5: 0xffffffff70000002
 0x~~~~~~~~~~~~~~~~  13001d28		sxtb w8, w9
-#    x8: 0x0000000000000001
+#             w8:         0x00000001
 0x~~~~~~~~~~~~~~~~  93401d6a		sxtb x10, w11
-#   x10: 0x000000000000001e
+#            x10: 0x000000000000001e
 0x~~~~~~~~~~~~~~~~  13003dac		sxth w12, w13
-#   x12: 0x00000000ffffff7d
+#            w12:         0xffffff7d
 0x~~~~~~~~~~~~~~~~  93403dee		sxth x14, w15
-#   x14: 0x0000000000000082
+#            x14: 0x0000000000000082
 0x~~~~~~~~~~~~~~~~  13007e30		sbfx w16, w17, #0, #32
-#   x16: 0x00000000ffffff7b
+#            w16:         0xffffff7b
 0x~~~~~~~~~~~~~~~~  93407e72		sxtw x18, w19
-#   x18: 0x0000000000000086
+#            x18: 0x0000000000000086
 0x~~~~~~~~~~~~~~~~  6a15029f		tst w20, w21
 # NZCV: N:0 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  ea1702df		tst x22, x23
 # NZCV: N:0 Z:1 C:0 V:0
 0x~~~~~~~~~~~~~~~~  53162b38		ubfiz w24, w25, #10, #11
-#   x24: 0x0000000000040000
+#            w24:         0x00040000
 0x~~~~~~~~~~~~~~~~  d374337a		ubfiz x26, x27, #12, #13
-#   x26: 0x0000000001fff000
+#            x26: 0x0000000001fff000
 0x~~~~~~~~~~~~~~~~  530e3fbc		ubfx w28, w29, #14, #2
-#   x28: 0x0000000000000000
+#            w28:         0x00000000
 0x~~~~~~~~~~~~~~~~  d3410862		ubfx x2, x3, #1, #2
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  530318a4		ubfx w4, w5, #3, #4
-#    x4: 0x0000000000000000
+#             w4:         0x00000000
 0x~~~~~~~~~~~~~~~~  d34528e6		ubfx x6, x7, #5, #6
-#    x6: 0x000000000000003f
+#             x6: 0x000000000000003f
 0x~~~~~~~~~~~~~~~~  1aca0928		udiv w8, w9, w10
-#    x8: 0x0000000000000000
+#             w8:         0x00000000
 0x~~~~~~~~~~~~~~~~  9acd098b		udiv x11, x12, x13
-#   x11: 0x0000000000000000
+#            x11: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9bd87ef6		umulh x22, x23, x24
-#   x22: 0x0000000000000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  53001fbc		uxtb w28, w29
-#   x28: 0x0000000000000000
+#            w28:         0x00000000
 0x~~~~~~~~~~~~~~~~  d3401c62		uxtb x2, w3
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  53003ca4		uxth w4, w5
-#    x4: 0x0000000000000002
+#             w4:         0x00000002
 0x~~~~~~~~~~~~~~~~  d3403ce6		uxth x6, w7
-#    x6: 0x000000000000ffff
+#             x6: 0x000000000000ffff
 0x~~~~~~~~~~~~~~~~  53007d28		lsr w8, w9, #0
-#    x8: 0x0000000000000001
+#             w8:         0x00000001
 0x~~~~~~~~~~~~~~~~  d3407d6a		ubfx x10, x11, #0, #32
-#   x10: 0x0000000000000000
+#            x10: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  14000001		b #+0x4 (addr 0x~~~~~~~~~~~~~~~~)
 # Branch to 0x~~~~~~~~~~~~~~~~.
 0x~~~~~~~~~~~~~~~~  eb030063		subs x3, x3, x3
 # NZCV: N:0 Z:1 C:1 V:0
-#    x3: 0x0000000000000000
+#             x3: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  54000061		b.ne #+0xc (addr 0x~~~~~~~~~~~~~~~~)
 0x~~~~~~~~~~~~~~~~  f100047f		cmp x3, #0x1 (1)
 # NZCV: N:1 Z:0 C:0 V:0
@@ -780,5299 +1047,10814 @@
 0x~~~~~~~~~~~~~~~~  54000061		b.ne #+0xc (addr 0x~~~~~~~~~~~~~~~~)
 # Branch to 0x~~~~~~~~~~~~~~~~.
 0x~~~~~~~~~~~~~~~~  7ef3d44d		fabd d13, d2, d19
-#   v13: 0x00000000000000004036e00cd9b7e45b
+#            v13: 0x0000000000000000490ffff1110487fe
 0x~~~~~~~~~~~~~~~~  7ebed548		fabd s8, s10, s30
-#    v8: 0x00000000000000000000000041c5851e
+#             v8: 0x0000000000000000000000000e02aff8
 0x~~~~~~~~~~~~~~~~  1e60c021		fabs d1, d1
-#    v1: 0x00000000000000003ff587933f9e0419 (d1: 1.34560)
+#             d1:                 0x47f000007f823c00 (3.403e+38)
 0x~~~~~~~~~~~~~~~~  1e20c0f9		fabs s25, s7
-#   v25: 0x000000000000000000000000410a4396 (s25: 8.64150)
+#            s25:                         0x02825400 (1.915e-37)
 0x~~~~~~~~~~~~~~~~  7e70eee1		facge d1, d23, d16
-#    v1: 0x0000000000000000ffffffffffffffff
+#             v1: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e21ee24		facge s4, s17, s1
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ef8eea2		facgt d2, d21, d24
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eacef4c		facgt s12, s26, s12
-#   v12: 0x000000000000000000000000ffffffff
+#            v12: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  1e76296d		fadd d13, d11, d22
-#   v13: 0x0000000000000000404633d07142f43a (d13: 44.4048)
+#            d13:                 0x494002008a13204c (7.140e+44)
 0x~~~~~~~~~~~~~~~~  1e282a7b		fadd s27, s19, s8
-#   v27: 0x000000000000000000000000424094fe (s27: 48.1455)
+#            s27:                         0x0e029fa8 (1.610e-30)
 0x~~~~~~~~~~~~~~~~  1e6a24c0		fccmp d6, d10, #nzcv, hs
 # NZCV: N:0 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1e3417ad		fccmp s29, s20, #NZcV, ne
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1e62e55e		fccmpe d10, d2, #NZCv, al
 # NZCV: N:0 Z:0 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e23547d		fccmpe s3, s3, #NZcV, pl
 # NZCV: N:0 Z:1 C:1 V:0
 0x~~~~~~~~~~~~~~~~  5e6ae513		fcmeq d19, d8, d10
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0da40		fcmeq d0, d18, #0.0
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e3ee481		fcmeq s1, s4, s30
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ea0dbb6		fcmeq s22, s29, #0.0
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e61e65b		fcmge d27, d18, d1
-#   v27: 0x0000000000000000ffffffffffffffff
+#            v27: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7ee0cb9f		fcmge d31, d28, #0.0
-#   v31: 0x0000000000000000ffffffffffffffff
+#            v31: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e29e67f		fcmge s31, s19, s9
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  7ea0cb21		fcmge s1, s25, #0.0
-#    v1: 0x000000000000000000000000ffffffff
+#             v1: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  7eefe432		fcmgt d18, d1, d15
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0cbe3		fcmgt d3, d31, #0.0
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7ea2e72b		fcmgt s11, s25, s2
-#   v11: 0x000000000000000000000000ffffffff
+#            v11: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  5ea0ca11		fcmgt s17, s16, #0.0
-#   v17: 0x000000000000000000000000ffffffff
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ee0da38		fcmle d24, d17, #0.0
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7ea0d90b		fcmle s11, s8, #0.0
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0ebe5		fcmlt d5, d31, #0.0
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ea0eaf2		fcmlt s18, s23, #0.0
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  1e782140		fcmp d10, d24
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 0x~~~~~~~~~~~~~~~~  1e6021a8		fcmp d13, #0.0
 # NZCV: N:0 Z:0 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e262240		fcmp s18, s6
-# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 0x~~~~~~~~~~~~~~~~  1e202208		fcmp s16, #0.0
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1e712130		fcmpe d9, d17
 # NZCV: N:0 Z:0 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e6023b8		fcmpe d29, #0.0
 # NZCV: N:0 Z:0 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e312210		fcmpe s16, s17
-# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1e2022d8		fcmpe s22, #0.0
 # NZCV: N:0 Z:1 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e73cdca		fcsel d10, d14, d19, gt
-#   v10: 0x00000000000000000000000000000000 (d10: 0.00000)
+#            d10:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e22ae56		fcsel s22, s18, s2, ge
-#   v22: 0x00000000000000000000000000000000 (s22: 0.00000)
+#            s22:                         0xffffffff
 0x~~~~~~~~~~~~~~~~  1ee2c304		fcvt d4, h24
-#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+#             d4:                 0xfffffc0000000000
 0x~~~~~~~~~~~~~~~~  1e22c04b		fcvt d11, s2
-#   v11: 0x00000000000000000000000000000000 (d11: 0.00000)
+#            d11:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e63c128		fcvt h8, d9
-#    v8: 0x00000000000000000000000000004a0e
+#             h8:                             0x7c00
 0x~~~~~~~~~~~~~~~~  1e23c02c		fcvt h12, s1
-#   v12: 0x0000000000000000000000000000ffff
+#            h12:                             0xffff
 0x~~~~~~~~~~~~~~~~  1e6243ec		fcvt s12, d31
-#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+#            s12:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1ee2433b		fcvt s27, h25
-#   v27: 0x0000000000000000000000004072c000 (s27: 3.79297)
+#            s27:                         0x42800000
 0x~~~~~~~~~~~~~~~~  5e61ca1c		fcvtas d28, d16
-#   v28: 0x00000000000000000000000000000016
+#            v28: 0x00000000000000007fffffffffffffff
 0x~~~~~~~~~~~~~~~~  5e21c8a3		fcvtas s3, s5
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e6403f2		fcvtas w18, d31
-#   x18: 0x0000000000000000
+#            w18:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e24031d		fcvtas w29, s24
-#   x29: 0x0000000000000000
+#            w29:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e640029		fcvtas x9, d1
-#    x9: 0x0000000000000000
+#             x9: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e24005e		fcvtas x30, s2
-#    lr: 0x0000000000000000
+#             lr: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7e61c80e		fcvtau d14, d0
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e21c9df		fcvtau s31, s14
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e650050		fcvtau w16, d2
-#   x16: 0x0000000000000000
+#            w16:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e250012		fcvtau w18, s0
-#   x18: 0x0000000000000000
+#            w18:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e6500fa		fcvtau x26, d7
-#   x26: 0x0000000000000009
+#            x26: 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  9e250279		fcvtau x25, s19
-#   x25: 0x0000000000000000
+#            x25: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5e61bb3e		fcvtms d30, d25
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e21b9ec		fcvtms s12, s15
-#   v12: 0x00000000000000000000000000000012
+#            v12: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  1e7000e9		fcvtms w9, d7
-#    x9: 0x0000000000000009
+#             w9:         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1e3000d3		fcvtms w19, s6
-#   x19: 0x0000000000000007
+#            w19:         0xffffffff
 0x~~~~~~~~~~~~~~~~  9e7000c6		fcvtms x6, d6
-#    x6: 0x0000000000000008
+#             x6: 0x7fffffffffffffff
 0x~~~~~~~~~~~~~~~~  9e3000f6		fcvtms x22, s7
-#   x22: 0x0000000000000008
+#            x22: 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e61b81b		fcvtmu d27, d0
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e21bac8		fcvtmu s8, s22
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e71027d		fcvtmu w29, d19
-#   x29: 0x0000000000000000
+#            w29:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e31001a		fcvtmu w26, s0
-#   x26: 0x0000000000000000
+#            w26:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e7100ad		fcvtmu x13, d5
-#   x13: 0x0000000000000000
+#            x13: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e310245		fcvtmu x5, s18
-#    x5: 0x0000000000000000
+#             x5: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5e61a9fe		fcvtns d30, d15
-#   v30: 0x00000000000000000000000000000014
+#            v30: 0x00000000000000007fffffffffffffff
 0x~~~~~~~~~~~~~~~~  5e21a96a		fcvtns s10, s11
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e6001f5		fcvtns w21, d15
-#   x21: 0x0000000000000014
+#            w21:         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1e200152		fcvtns w18, s10
-#   x18: 0x0000000000000000
+#            w18:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e600228		fcvtns x8, d17
-#    x8: 0x0000000000000000
+#             x8: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e200191		fcvtns x17, s12
-#   x17: 0x0000000000000000
+#            x17: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7e61aaa0		fcvtnu d0, d21
-#    v0: 0x0000000000000000000000000000001c
+#             v0: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e21ab26		fcvtnu s6, s25
-#    v6: 0x00000000000000000000000000000009
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e61017d		fcvtnu w29, d11
-#   x29: 0x0000000000000000
+#            w29:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e2103f9		fcvtnu w25, s31
-#   x25: 0x0000000000000000
+#            w25:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e61017e		fcvtnu x30, d11
-#    lr: 0x0000000000000000
+#             lr: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e21025b		fcvtnu x27, s18
-#   x27: 0x0000000000000000
+#            x27: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5ee1aacb		fcvtps d11, d22
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  5ea1aa9d		fcvtps s29, s20
-#   v29: 0x00000000000000000000000000000019
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e68032f		fcvtps w15, d25
-#   x15: 0x0000000000000001
+#            w15:         0x00000001
 0x~~~~~~~~~~~~~~~~  1e2800f0		fcvtps w16, s7
-#   x16: 0x0000000000000009
+#            w16:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e68028d		fcvtps x13, d20
-#   x13: 0x000000000000001b
+#            x13: 0x7fffffffffffffff
 0x~~~~~~~~~~~~~~~~  9e2802e3		fcvtps x3, s23
-#    x3: 0x000000000000001d
+#             x3: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7ee1a838		fcvtpu d24, d1
-#   v24: 0x00000000000000000000000000000001
+#            v24: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  7ea1ab0e		fcvtpu s14, s24
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  1e6903ba		fcvtpu w26, d29
-#   x26: 0x0000000000000001
+#            w26:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e29035f		fcvtpu wzr, s26
 0x~~~~~~~~~~~~~~~~  9e6900db		fcvtpu x27, d6
-#   x27: 0x0000000000000001
+#            x27: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e2901dd		fcvtpu x29, s14
-#   x29: 0x0000000000000001
+#            x29: 0x0000000000000001
 0x~~~~~~~~~~~~~~~~  7e61698c		fcvtxn s12, d12
-#   v12: 0x00000000000000000000000000000001
+#            v12: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  5ee1b80f		fcvtzs d15, d0
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f56fc8d		fcvtzs d13, d4, #42
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ea1b968		fcvtzs s8, s11
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f27fcdf		fcvtzs s31, s6, #25
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e780126		fcvtzs w6, d9
-#    x6: 0x000000000000000c
+#             w6:         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1e58b159		fcvtzs w25, d10, #20
-#   x25: 0x0000000000000000
+#            w25:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e380029		fcvtzs w9, s1
-#    x9: 0x0000000000000000
+#             w9:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e188bb1		fcvtzs w17, s29, #30
-#   x17: 0x0000000000000000
+#            w17:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e780053		fcvtzs x19, d2
-#   x19: 0x0000000000000000
+#            x19: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e58fdd6		fcvtzs x22, d14, #1
-#   x22: 0x0000000000000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e38028e		fcvtzs x14, s20
-#   x14: 0x0000000000000018
+#            x14: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e187fc3		fcvtzs x3, s30, #33
-#    x3: 0x0000000000000000
+#             x3: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7ee1b9fc		fcvtzu d28, d15
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f7dfc80		fcvtzu d0, d4, #3
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ea1b8a2		fcvtzu s2, s5
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f22fc04		fcvtzu s4, s0, #30
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e79008b		fcvtzu w11, d4
-#   x11: 0x0000000000000000
+#            w11:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e598307		fcvtzu w7, d24, #32
-#    x7: 0x0000000000000000
+#             w7:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e390312		fcvtzu w18, s24
-#   x18: 0x0000000000000000
+#            w18:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e19f36e		fcvtzu w14, s27, #4
-#   x14: 0x0000000000000000
+#            w14:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e790176		fcvtzu x22, d11
-#   x22: 0x0000000000000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e593368		fcvtzu x8, d27, #52
-#    x8: 0x0000000000000000
+#             x8: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e390287		fcvtzu x7, s20
-#    x7: 0x0000000000000018
+#             x7: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e1950f6		fcvtzu x22, s7, #44
-#   x22: 0x00008a4396000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e6f19c6		fdiv d6, d14, d15
-#    v6: 0x00000000000000007ff0000000000000 (d6: inf)
+#             d6:                 0x7ff0000000000000 (inf)
 0x~~~~~~~~~~~~~~~~  1e3918ba		fdiv s26, s5, s25
-#   v26: 0x00000000000000000000000000000000 (s26: 0.00000)
+#            s26:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1f4c7b52		fmadd d18, d26, d12, d30
-#   v18: 0x00000000000000000000000000000014 (d18: 9.88131e-323)
+#            d18:                 0x7fffffffffffffff
 0x~~~~~~~~~~~~~~~~  1f1c112d		fmadd s13, s9, s28, s4
-#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+#            s13:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e6548ac		fmax d12, d5, d5
-#   v12: 0x00000000000000000000000000000000 (d12: 0.00000)
+#            d12:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e264b8c		fmax s12, s28, s6
-#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+#            s12:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e62689c		fmaxnm d28, d4, d2
-#   v28: 0x00000000000000000000000000000000 (d28: 0.00000)
+#            d28:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e286946		fmaxnm s6, s10, s8
-#    v6: 0x00000000000000000000000000000000 (s6: 0.00000)
+#             s6:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e725a94		fmin d20, d20, d18
-#   v20: 0x00000000000000000000000000000014 (d20: 9.88131e-323)
+#            d20:                 0x7fffffffffffffff (nan)
 0x~~~~~~~~~~~~~~~~  1e3059a7		fmin s7, s13, s16
-#    v7: 0x00000000000000000000000000000000 (s7: 0.00000)
+#             s7:                         0x87027800 (-9.815e-35)
 0x~~~~~~~~~~~~~~~~  1e7e79d3		fminnm d19, d14, d30
-#   v19: 0x00000000000000000000000000000001 (d19: 4.94066e-324)
+#            d19:                 0x0000000000000001 (4.941e-324)
 0x~~~~~~~~~~~~~~~~  1e217820		fminnm s0, s1, s1
-#    v0: 0x000000000000000000000000ffffffff (s0: nan)
+#             s0:                         0xffffffff (nan)
 0x~~~~~~~~~~~~~~~~  1e6040cd		fmov d13, d6
-#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+#            d13:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e670222		fmov d2, x17
-#    v2: 0x00000000000000000000000000000000
+#             d2:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e709008		fmov d8, #0x84 (-2.5000)
-#    v8: 0x0000000000000000c004000000000000 (d8: -2.50000)
+#             d8:                 0xc004000000000000
 0x~~~~~~~~~~~~~~~~  1e204065		fmov s5, s3
-#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+#             s5:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e270299		fmov s25, w20
-#   v25: 0x00000000000000000000000000000001
+#            s25:                         0x00000001
 0x~~~~~~~~~~~~~~~~  1e20f015		fmov s21, #0x7 (2.8750)
-#   v21: 0x00000000000000000000000040380000 (s21: 2.87500)
+#            s21:                         0x40380000
 0x~~~~~~~~~~~~~~~~  1e260312		fmov w18, s24
-#   x18: 0x0000000000000001
+#            w18:         0x00000001
 0x~~~~~~~~~~~~~~~~  9e660052		fmov x18, d2
-#   x18: 0x0000000000000000
+#            x18: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1f43cfd4		fmsub d20, d30, d3, d19
-#   v20: 0x00000000000000000000000000000001 (d20: 4.94066e-324)
+#            d20:                 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  1f04b265		fmsub s5, s19, s4, s12
-#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+#             s5:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e770b7e		fmul d30, d27, d23
-#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
+#            d30:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e2f0a39		fmul s25, s17, s15
-#   v25: 0x000000000000000000000000ffffffff (s25: nan)
+#            s25:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  5e61de24		fmulx d4, d17, d1
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e24df2e		fmulx s14, s25, s4
-#   v14: 0x000000000000000000000000ffffffff
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e61400f		fneg d15, d0
-#   v15: 0x000000000000000080000000ffffffff (d15: -2.12200e-314)
+#            d15:                 0x80000000ffffffff (-2.122e-314)
 0x~~~~~~~~~~~~~~~~  1e2141ee		fneg s14, s15
-#   v14: 0x0000000000000000000000007fffffff (s14: nan)
+#            s14:                         0x7fffffff (nan)
 0x~~~~~~~~~~~~~~~~  1f767e00		fnmadd d0, d16, d22, d31
-#    v0: 0x00000000000000008000000000000000 (d0: -0.00000)
+#             d0:                 0x87c0000086f277ff
 0x~~~~~~~~~~~~~~~~  1f3a4a40		fnmadd s0, s18, s26, s18
-#    v0: 0x00000000000000000000000080000014 (s0: -2.80260e-44)
+#             s0:                         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1f6fd593		fnmsub d19, d12, d15, d21
-#   v19: 0x00000000000000008000000040380000 (d19: -5.32312e-315)
+#            d19:                 0x8000000040380000
 0x~~~~~~~~~~~~~~~~  1f2be81d		fnmsub s29, s0, s11, s26
-#   v29: 0x00000000000000000000000080000000 (s29: -0.00000)
+#            s29:                         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1e618a7f		fnmul d31, d19, d1
-#   v31: 0x00000000000000000000000000000000 (d31: 0.00000)
+#            d31:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e318872		fnmul s18, s3, s17
-#   v18: 0x0000000000000000000000007fffffff (s18: nan)
+#            s18:                         0x80000000 (-0.000)
 0x~~~~~~~~~~~~~~~~  5ee1daa7		frecpe d7, d21
-#    v7: 0x00000000000000007ff0000000000000
+#             v7: 0x00000000000000007ff0000000000000
 0x~~~~~~~~~~~~~~~~  5ea1da3d		frecpe s29, s17
-#   v29: 0x000000000000000000000000ffffffff
+#            v29: 0x0000000000000000000000007f800000
 0x~~~~~~~~~~~~~~~~  5e71ff4b		frecps d11, d26, d17
-#   v11: 0x00000000000000004000000000000000
+#            v11: 0x00000000000000004000000000000000
 0x~~~~~~~~~~~~~~~~  5e21ff72		frecps s18, s27, s1
-#   v18: 0x000000000000000000000000ffffffff
+#            v18: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  5ee1fa4f		frecpx d15, d18
-#   v15: 0x00000000000000007fe0000000000000
+#            v15: 0x00000000000000007fe0000000000000
 0x~~~~~~~~~~~~~~~~  5ea1f945		frecpx s5, s10
-#    v5: 0x0000000000000000000000007f000000
+#             v5: 0x0000000000000000000000007f000000
 0x~~~~~~~~~~~~~~~~  1e6643d0		frinta d16, d30
-#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
+#            d16:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e2642c1		frinta s1, s22
-#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
+#             s1:                         0xffffffff (nan)
 0x~~~~~~~~~~~~~~~~  1e67c3b3		frinti d19, d29
-#   v19: 0x00000000000000000000000000000000 (d19: 0.00000)
+#            d19:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e27c2ae		frinti s14, s21
-#   v14: 0x00000000000000000000000040400000 (s14: 3.00000)
+#            s14:                         0x40400000 (3.000)
 0x~~~~~~~~~~~~~~~~  1e6543d4		frintm d20, d30
-#   v20: 0x00000000000000000000000000000000 (d20: 0.00000)
+#            d20:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e254201		frintm s1, s16
-#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
+#             s1:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e64403e		frintn d30, d1
-#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
+#            d30:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e244158		frintn s24, s10
-#   v24: 0x00000000000000000000000000000000 (s24: 0.00000)
+#            s24:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e64c284		frintp d4, d20
-#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+#             d4:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e24c06d		frintp s13, s3
-#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+#            s13:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e67428d		frintx d13, d20
-#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+#            d13:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e2740f1		frintx s17, s7
-#   v17: 0x00000000000000000000000000000000 (s17: 0.00000)
+#            s17:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e65c100		frintz d0, d8
-#    v0: 0x0000000000000000c000000000000000 (d0: -2.00000)
+#             d0:                 0xc000000000000000 (-2.000)
 0x~~~~~~~~~~~~~~~~  1e25c3af		frintz s15, s29
-#   v15: 0x000000000000000000000000ffffffff (s15: nan)
+#            s15:                         0x7f800000 (inf)
 0x~~~~~~~~~~~~~~~~  7ee1d955		frsqrte d21, d10
-#   v21: 0x00000000000000007ff0000000000000
+#            v21: 0x00000000000000007ff0000000000000
 0x~~~~~~~~~~~~~~~~  7ea1db31		frsqrte s17, s25
-#   v17: 0x000000000000000000000000ffffffff
+#            v17: 0x0000000000000000000000007f800000
 0x~~~~~~~~~~~~~~~~  5ef1ffa4		frsqrts d4, d29, d17
-#    v4: 0x00000000000000003ff8000000000000
+#             v4: 0x00000000000000003ff8000000000000
 0x~~~~~~~~~~~~~~~~  5eb8fc6e		frsqrts s14, s3, s24
-#   v14: 0x0000000000000000000000003fc00000
+#            v14: 0x0000000000000000000000003fc00000
 0x~~~~~~~~~~~~~~~~  1e61c22e		fsqrt d14, d17
-#   v14: 0x00000000000000001f5ffffffff00000 (d14: 1.45671e-157)
+#            d14:                 0x1f56954b41cd4293 (1.028e-157)
 0x~~~~~~~~~~~~~~~~  1e21c1c4		fsqrt s4, s14
-#    v4: 0x000000000000000000000000fff00000 (s4: nan)
+#             s4:                         0x40a21722 (5.065)
 0x~~~~~~~~~~~~~~~~  1e673a6d		fsub d13, d19, d7
-#   v13: 0x0000000000000000fff0000000000000 (d13: -inf)
+#            d13:                 0xfff0000000000000 (-inf)
 0x~~~~~~~~~~~~~~~~  1e3b3aa3		fsub s3, s21, s27
-#    v3: 0x00000000000000000000000000000000 (s3: 0.00000)
+#             s3:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  5e61da1f		scvtf d31, d16
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f68e7fa		scvtf d26, d31, #24
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e620206		scvtf d6, w16
-#    v6: 0x00000000000000004022000000000000 (d6: 9.00000)
+#             d6:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e42ea85		scvtf d5, w20, #6
-#    v5: 0x00000000000000003f90000000000000 (d5: 0.0156250)
+#             d5:                 0x3f90000000000000
 0x~~~~~~~~~~~~~~~~  9e620110		scvtf d16, x8
-#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
+#            d16:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e42d90f		scvtf d15, x8, #10
-#   v15: 0x00000000000000000000000000000000 (d15: 0.00000)
+#            d15:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5e21d887		scvtf s7, s4
-#    v7: 0x00000000000000007ff00000c9800000
+#             v7: 0x00000000000000007ff000004e81442e
 0x~~~~~~~~~~~~~~~~  5f32e5e8		scvtf s8, s15, #14
-#    v8: 0x0000000000000000c004000000000000
+#             v8: 0x0000000000000000c004000000000000
 0x~~~~~~~~~~~~~~~~  1e22015d		scvtf s29, w10
-#   v29: 0x00000000000000000000000000000000 (s29: 0.00000)
+#            s29:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e02d6af		scvtf s15, w21, #11
-#   v15: 0x0000000000000000000000003c200000 (s15: 0.00976562)
+#            s15:                         0x49800000
 0x~~~~~~~~~~~~~~~~  9e22035b		scvtf s27, x26
-#   v27: 0x0000000000000000000000003f800000 (s27: 1.00000)
+#            s27:                         0x00000000
 0x~~~~~~~~~~~~~~~~  9e02699a		scvtf s26, x12, #38
-#   v26: 0x0000000000000000000000003c7fffff (s26: 0.0156250)
+#            s26:                         0x3c7fffff
 0x~~~~~~~~~~~~~~~~  7e61d920		ucvtf d0, d9
-#    v0: 0x000000000000000043d00a0e21904c71
+#             v0: 0x000000000000000043d21c000020e097
 0x~~~~~~~~~~~~~~~~  7f51e6c5		ucvtf d5, d22, #47
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000003effffffffe00000
 0x~~~~~~~~~~~~~~~~  1e63037e		ucvtf d30, w27
-#   v30: 0x00000000000000003ff0000000000000 (d30: 1.00000)
+#            d30:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e43fe63		ucvtf d3, w19, #1
-#    v3: 0x00000000000000000000000000000000 (d3: 0.00000)
+#             d3:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e6302bc		ucvtf d28, x21
-#   v28: 0x00000000000000004034000000000000 (d28: 20.0000)
+#            d28:                 0x41dfffffffc00000
 0x~~~~~~~~~~~~~~~~  9e4377db		ucvtf d27, x30, #35
-#   v27: 0x00000000000000000000000000000000 (d27: 0.00000)
+#            d27:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7e21d8ab		ucvtf s11, s5
-#   v11: 0x00000000000000004000000000000000
+#            v11: 0x0000000000000000400000004f7fe000
 0x~~~~~~~~~~~~~~~~  7f32e6e0		ucvtf s0, s23, #14
-#    v0: 0x000000000000000043d00a0e4783c64c
+#             v0: 0x000000000000000043d21c00480a8294
 0x~~~~~~~~~~~~~~~~  1e230274		ucvtf s20, w19
-#   v20: 0x00000000000000000000000000000000 (s20: 0.00000)
+#            s20:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e03bad5		ucvtf s21, w22, #18
-#   v21: 0x00000000000000000000000046160000 (s21: 9600.00)
+#            s21:                         0x00000000
 0x~~~~~~~~~~~~~~~~  9e2301a6		ucvtf s6, x13
-#    v6: 0x00000000000000000000000041d80000 (s6: 27.0000)
+#             s6:                         0x5f000000
 0x~~~~~~~~~~~~~~~~  9e03ac47		ucvtf s7, x2, #21
-#    v7: 0x00000000000000000000000038ff0000 (s7: 0.000121593)
+#             s7:                         0x38ff0000
 0x~~~~~~~~~~~~~~~~  5ee0b813		abs d19, d0
-#   v19: 0x000000000000000043d00a0e4783c64c
+#            v19: 0x000000000000000043d21c00480a8294
 0x~~~~~~~~~~~~~~~~  4e20b970		abs v16.16b, v11.16b
-#   v16: 0x00000000000000004000000000000000
+#            v16: 0x0000000000000000400000004f7f2000
 0x~~~~~~~~~~~~~~~~  4ee0bbe0		abs v0.2d, v31.2d
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0bb3b		abs v27.2s, v25.2s
-#   v27: 0x00000000000000000000000000000001
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e60bb75		abs v21.4h, v27.4h
-#   v21: 0x00000000000000000000000000000001
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea0b830		abs v16.4s, v1.4s
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e20b8bf		abs v31.8b, v5.8b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000003e01010101200000
 0x~~~~~~~~~~~~~~~~  4e60b9bd		abs v29.8h, v13.8h
-#   v29: 0x00000000000000000010000000000000
+#            v29: 0x00000000000000000010000000000000
 0x~~~~~~~~~~~~~~~~  5ef184aa		add d10, d5, d17
-#   v10: 0x000000000000000000000000ffffffff
+#            v10: 0x00000000000000003f0000007f600000
 0x~~~~~~~~~~~~~~~~  4e3785ff		add v31.16b, v15.16b, v23.16b
-#   v31: 0x403ba7b141b670b1403ef2e47d0325e4
+#            v31: 0x495000018a83940149500000d3029400
 0x~~~~~~~~~~~~~~~~  4eee87ea		add v10.2d, v31.2d, v14.2d
-#   v10: 0x403ba7b141b670b15f9ef2e47cf325e4
+#            v10: 0x495000018a83940168a6954c14cfd693
 0x~~~~~~~~~~~~~~~~  0eb385cf		add v15.2s, v14.2s, v19.2s
-#   v15: 0x000000000000000063300a0d4773c64c
+#            v15: 0x00000000000000006328b14b89d7c527
 0x~~~~~~~~~~~~~~~~  0e7186fb		add v27.4h, v23.4h, v17.4h
-#   v27: 0x0000000000000000403ef2e441e225e3
+#            v27: 0x0000000000000000495000000a029400
 0x~~~~~~~~~~~~~~~~  4ebd8799		add v25.4s, v28.4s, v29.4s
-#   v25: 0x00000000000000004044000000000000
+#            v25: 0x000000000000000041efffffffc00000
 0x~~~~~~~~~~~~~~~~  0e3284ed		add v13.8b, v7.8b, v18.8b
-#   v13: 0x00000000000000000000000037feffff
+#            v13: 0x00000000000000000000000037feffff
 0x~~~~~~~~~~~~~~~~  4e618444		add v4.8h, v2.8h, v1.8h
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eaf41ca		addhn v10.2s, v14.2d, v15.2d
-#   v10: 0x00000000000000000000000082900a0d
+#            v10: 0x000000000000000000000000827f4696
 0x~~~~~~~~~~~~~~~~  0e7a43ca		addhn v10.4h, v30.4s, v26.4s
-#   v10: 0x0000000000000000000000003ff03c7f
+#            v10: 0x00000000000000000000000000003c7f
 0x~~~~~~~~~~~~~~~~  0e36419f		addhn v31.8b, v12.8h, v22.8h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  4e3442b0		addhn2 v16.16b, v21.8h, v20.8h
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb14040		addhn2 v0.4s, v2.2d, v17.2d
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7140ff		addhn2 v31.8h, v7.4s, v17.4s
-#   v31: 0x00000000000038fe0000000000000000
+#            v31: 0x000000000000b87f000000000000ffff
 0x~~~~~~~~~~~~~~~~  5ef1ba6e		addp d14, v19.2d
-#   v14: 0x000000000000000043d00a0e4783c64c
+#            v14: 0x000000000000000043d21c00480a8294
 0x~~~~~~~~~~~~~~~~  4e3cbd03		addp v3.16b, v8.16b, v28.16b
-#    v3: 0x000000007400000000000000c4000000
+#             v3: 0x0000000020febf0000000000c4000000
 0x~~~~~~~~~~~~~~~~  4ef1bca8		addp v8.2d, v5.2d, v17.2d
-#    v8: 0x00000000ffffffff0000000000000000
+#             v8: 0x000000007f8000003effffffffe00000
 0x~~~~~~~~~~~~~~~~  0ebabfd6		addp v22.2s, v30.2s, v26.2s
-#   v22: 0x00000000000000003c7fffff3ff00000
+#            v22: 0x00000000000000003c7fffff00000000
 0x~~~~~~~~~~~~~~~~  0e6ebf1d		addp v29.4h, v24.4h, v14.4h
-#   v29: 0x00000000000000004dde0dcf00000000
+#            v29: 0x00000000000000005fd2ca9e00000000
 0x~~~~~~~~~~~~~~~~  4eb8bf5e		addp v30.4s, v26.4s, v24.4s
-#   v30: 0x0000000000000000000000003c7fffff
+#            v30: 0x0000000000000000000000003c7fffff
 0x~~~~~~~~~~~~~~~~  0e27bf4c		addp v12.8b, v26.8b, v7.8b
-#   v12: 0x0000000000000000000037000000bbfe
+#            v12: 0x0000000000000000000037000000bbfe
 0x~~~~~~~~~~~~~~~~  4e6cbd11		addp v17.8h, v8.8h, v12.8h
-#   v17: 0x000000003700bbfe0000fffe00000000
+#            v17: 0x000000003700bbfe00007f803efeffe0
 0x~~~~~~~~~~~~~~~~  4e31bafb		addv b27, v23.16b
-#   v27: 0x0000000000000000000000000000006c
+#            v27: 0x00000000000000000000000000000075
 0x~~~~~~~~~~~~~~~~  0e31ba8c		addv b12, v20.8b
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e71bbdb		addv h27, v30.4h
-#   v27: 0x00000000000000000000000000003c7e
+#            v27: 0x00000000000000000000000000003c7e
 0x~~~~~~~~~~~~~~~~  4e71b9d3		addv h19, v14.8h
-#   v19: 0x00000000000000000000000000005bad
+#            v19: 0x00000000000000000000000000002a70
 0x~~~~~~~~~~~~~~~~  4eb1bb6e		addv s14, v27.4s
-#   v14: 0x00000000000000000000000000003c7e
+#            v14: 0x00000000000000000000000000003c7e
 0x~~~~~~~~~~~~~~~~  4e3b1d0a		and v10.16b, v8.16b, v27.16b
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e301c25		and v5.8b, v1.8b, v16.8b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e781c7a		bic v26.16b, v3.16b, v24.16b
-#   v26: 0x000000007400000000000000c4000000
+#            v26: 0x0000000020febf0000000000c4000000
 0x~~~~~~~~~~~~~~~~  2f075487		bic v7.2s, #0xe4, lsl #16
-#    v7: 0x000000000000000000000000381b0000
+#             v7: 0x000000000000000000000000381b0000
 0x~~~~~~~~~~~~~~~~  2f01b47c		bic v28.4h, #0x23, lsl #8
-#   v28: 0x00000000000000004034000000000000
+#            v28: 0x000000000000000040dfdcffdcc00000
 0x~~~~~~~~~~~~~~~~  6f05159d		bic v29.4s, #0xac, lsl #0
-#   v29: 0x00000000000000004dde0d4300000000
+#            v29: 0x00000000000000005fd2ca1200000000
 0x~~~~~~~~~~~~~~~~  0e751fec		bic v12.8b, v31.8b, v21.8b
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  6f049712		bic v18.8h, #0x98, lsl #0
-#   v18: 0x000000000000000000000000ff67ff67
+#            v18: 0x000000000000000000000000ff67ff67
 0x~~~~~~~~~~~~~~~~  6ee81f4c		bif v12.16b, v26.16b, v8.16b
-#   v12: 0x000000000000000000000000c4000000
+#            v12: 0x00000000007ebf000000000000000000
 0x~~~~~~~~~~~~~~~~  2efb1ee2		bif v2.8b, v23.8b, v27.8b
-#    v2: 0x0000000000000000403ef2e441e30180
+#             v2: 0x0000000000000000495000008a828000
 0x~~~~~~~~~~~~~~~~  6ead1c68		bit v8.16b, v3.16b, v13.16b
-#    v8: 0x00000000ffffffff0000000004000000
+#             v8: 0x000000007f8000003effffffcc000000
 0x~~~~~~~~~~~~~~~~  2eb71ca5		bit v5.8b, v5.8b, v23.8b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e771fe9		bsl v9.16b, v31.16b, v23.16b
-#    v9: 0x00128220009270f80016c26000c22160
+#             v9: 0x0100000008009801010000000800dc00
 0x~~~~~~~~~~~~~~~~  2e631cee		bsl v14.8b, v7.8b, v3.8b
-#   v14: 0x000000000000000000000000c4000000
+#            v14: 0x000000000000000000000000c4000000
 0x~~~~~~~~~~~~~~~~  4e2048bd		cls v29.16b, v5.16b
-#   v29: 0x07070707070707070707070707070707
+#            v29: 0x07070707070707070707070707070707
 0x~~~~~~~~~~~~~~~~  0ea04815		cls v21.2s, v0.2s
-#   v21: 0x00000000000000000000001f0000001f
+#            v21: 0x00000000000000000000001f0000001f
 0x~~~~~~~~~~~~~~~~  0e604981		cls v1.4h, v12.4h
-#    v1: 0x0000000000000000000f000f0001000f
+#             v1: 0x0000000000000000000f000f000f000f
 0x~~~~~~~~~~~~~~~~  4ea0495b		cls v27.4s, v10.4s
-#   v27: 0x0000001f0000001f0000001f0000001f
+#            v27: 0x0000001f0000001f0000001f0000001f
 0x~~~~~~~~~~~~~~~~  0e204893		cls v19.8b, v4.8b
-#   v19: 0x00000000000000000707070707070707
+#            v19: 0x00000000000000000707070707070707
 0x~~~~~~~~~~~~~~~~  4e6049cf		cls v15.8h, v14.8h
-#   v15: 0x000f000f000f000f000f000f0001000f
+#            v15: 0x000f000f000f000f000f000f0001000f
 0x~~~~~~~~~~~~~~~~  6e204881		clz v1.16b, v4.16b
-#    v1: 0x08080808080808080808080808080808
+#             v1: 0x08080808080808080808080808080808
 0x~~~~~~~~~~~~~~~~  2ea04a3b		clz v27.2s, v17.2s
-#   v27: 0x00000000000000000000001000000020
+#            v27: 0x00000000000000000000001100000002
 0x~~~~~~~~~~~~~~~~  2e604929		clz v9.4h, v9.4h
-#    v9: 0x0000000000000000000b000000080002
+#             v9: 0x00000000000000000007001000040000
 0x~~~~~~~~~~~~~~~~  6ea049ff		clz v31.4s, v15.4s
-#   v31: 0x0000000c0000000c0000000c0000000f
+#            v31: 0x0000000c0000000c0000000c0000000f
 0x~~~~~~~~~~~~~~~~  2e204a6e		clz v14.8b, v19.8b
-#   v14: 0x00000000000000000505050505050505
+#            v14: 0x00000000000000000505050505050505
 0x~~~~~~~~~~~~~~~~  6e604966		clz v6.8h, v11.8h
-#    v6: 0x00100010001000100001001000100010
+#             v6: 0x00100010001000100001001000010000
 0x~~~~~~~~~~~~~~~~  7efd8cb2		cmeq d18, d5, d29
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee09bee		cmeq d14, d31, #0
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e368c73		cmeq v19.16b, v3.16b, v22.16b
-#   v19: 0xffffffff00ffffff000000000000ffff
+#            v19: 0xffffffff000000ff0000000000ffffff
 0x~~~~~~~~~~~~~~~~  4e20992f		cmeq v15.16b, v9.16b, #0
-#   v15: 0xffffffffffffffffff00ffffff00ff00
+#            v15: 0xffffffffffffffffff00ff00ff00ffff
 0x~~~~~~~~~~~~~~~~  6eea8e0c		cmeq v12.2d, v16.2d, v10.2d
-#   v12: 0xffffffffffffffffffffffffffffffff
+#            v12: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4ee09ac8		cmeq v8.2d, v22.2d, #0
-#    v8: 0xffffffffffffffff0000000000000000
+#             v8: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  2ea98c62		cmeq v2.2s, v3.2s, v9.2s
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea09b30		cmeq v16.2s, v25.2s, #0
-#   v16: 0x000000000000000000000000ffffffff
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e748ee6		cmeq v6.4h, v23.4h, v20.4h
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000ffff00000000
 0x~~~~~~~~~~~~~~~~  0e6099b0		cmeq v16.4h, v13.4h, #0
-#   v16: 0x0000000000000000ffffffff00000000
+#            v16: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  6ea28e35		cmeq v21.4s, v17.4s, v2.4s
-#   v21: 0xffffffff0000000000000000ffffffff
+#            v21: 0xffffffff000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea09b26		cmeq v6.4s, v25.4s, #0
-#    v6: 0xffffffffffffffff00000000ffffffff
+#             v6: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  2e228db0		cmeq v16.8b, v13.8b, v2.8b
-#   v16: 0x0000000000000000ffffffff00000000
+#            v16: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  0e209a15		cmeq v21.8b, v16.8b, #0
-#   v21: 0x000000000000000000000000ffffffff
+#            v21: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  6e798cf4		cmeq v20.8h, v7.8h, v25.8h
-#   v20: 0xffffffffffffffff0000ffff0000ffff
+#            v20: 0xffffffffffffffff000000000000ffff
 0x~~~~~~~~~~~~~~~~  4e60991a		cmeq v26.8h, v8.8h, #0
-#   v26: 0x0000000000000000ffffffffffffffff
+#            v26: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  5eff3db0		cmge d16, d13, d31
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ee08b19		cmge d25, d24, #0
-#   v25: 0x0000000000000000ffffffffffffffff
+#            v25: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e313e71		cmge v17.16b, v19.16b, v17.16b
-#   v17: 0x000000000000ffffffffffffffff0000
+#            v17: 0x0000000000ffffffffff00ff00ffffff
 0x~~~~~~~~~~~~~~~~  6e208bd6		cmge v22.16b, v30.16b, #0
-#   v22: 0xffffffffffffffffffffffffffff0000
+#            v22: 0xffffffffffffffffffffffffffff0000
 0x~~~~~~~~~~~~~~~~  4efa3e9c		cmge v28.2d, v20.2d, v26.2d
-#   v28: 0x0000000000000000ffffffffffffffff
+#            v28: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ee08ae6		cmge v6.2d, v23.2d, #0
-#    v6: 0xffffffffffffffffffffffffffffffff
+#             v6: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0ea33ed9		cmge v25.2s, v22.2s, v3.2s
-#   v25: 0x000000000000000000000000ffffffff
+#            v25: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  2ea08975		cmge v21.2s, v11.2s, #0
-#   v21: 0x0000000000000000ffffffffffffffff
+#            v21: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0e6c3c70		cmge v16.4h, v3.4h, v12.4h
-#   v16: 0x0000000000000000ffffffff0000ffff
+#            v16: 0x0000000000000000ffffffff0000ffff
 0x~~~~~~~~~~~~~~~~  2e608937		cmge v23.4h, v9.4h, #0
-#   v23: 0x0000000000000000ffffffffffffffff
+#            v23: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4eab3c47		cmge v7.4s, v2.4s, v11.4s
-#    v7: 0xffffffffffffffff00000000ffffffff
+#             v7: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  6ea08ac0		cmge v0.4s, v22.4s, #0
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e293fca		cmge v10.8b, v30.8b, v9.8b
-#   v10: 0x0000000000000000ff00ffffffff0000
+#            v10: 0x0000000000000000ff00ff00ffff0000
 0x~~~~~~~~~~~~~~~~  2e208915		cmge v21.8b, v8.8b, #0
-#   v21: 0x0000000000000000ffffffffffffffff
+#            v21: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e7a3ce2		cmge v2.8h, v7.8h, v26.8h
-#    v2: 0x0000000000000000ffffffffffffffff
+#             v2: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e608953		cmge v19.8h, v10.8h, #0
-#   v19: 0xffffffffffffffff000000000000ffff
+#            v19: 0xffffffffffffffff000000000000ffff
 0x~~~~~~~~~~~~~~~~  5ee135a6		cmgt d6, d13, d1
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee08b1e		cmgt d30, d24, #0
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e3b3734		cmgt v20.16b, v25.16b, v27.16b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e208b20		cmgt v0.16b, v25.16b, #0
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee13736		cmgt v22.2d, v25.2d, v1.2d
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee08a10		cmgt v16.2d, v16.2d, #0
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eaf3525		cmgt v5.2s, v9.2s, v15.2s
-#    v5: 0x0000000000000000ffffffffffffffff
+#             v5: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0ea08a4c		cmgt v12.2s, v18.2s, #0
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6b365c		cmgt v28.4h, v18.4h, v11.4h
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  0e608876		cmgt v22.4h, v3.4h, #0
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ebb3565		cmgt v5.4s, v11.4s, v27.4s
-#    v5: 0x0000000000000000ffffffff00000000
+#             v5: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4ea08a8d		cmgt v13.4s, v20.4s, #0
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e2737fb		cmgt v27.8b, v31.8b, v7.8b
-#   v27: 0x0000000000000000000000ffffffffff
+#            v27: 0x0000000000000000000000ff000000ff
 0x~~~~~~~~~~~~~~~~  0e208805		cmgt v5.8b, v0.8b, #0
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6d3796		cmgt v22.8h, v28.8h, v13.8h
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e608846		cmgt v6.8h, v2.8h, #0
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ef63515		cmhi d21, d8, d22
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e333672		cmhi v18.16b, v19.16b, v19.16b
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ef53407		cmhi v7.2d, v0.2d, v21.2d
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea0366f		cmhi v15.2s, v19.2s, v0.2s
-#   v15: 0x000000000000000000000000ffffffff
+#            v15: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  2e6c34ff		cmhi v31.4h, v7.4h, v12.4h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb63609		cmhi v9.4s, v16.4s, v22.4s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3c3707		cmhi v7.8b, v24.8b, v28.8b
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e79354b		cmhi v11.8h, v10.8h, v25.8h
-#   v11: 0x0000000000000000ffffffff00000000
+#            v11: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  7ef13d81		cmhs d1, d12, d17
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e3e3f35		cmhs v21.16b, v25.16b, v30.16b
-#   v21: 0xffffffffffffffffffffffffffffffff
+#            v21: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6efa3c48		cmhs v8.2d, v2.2d, v26.2d
-#    v8: 0xffffffffffffffffffffffffffffffff
+#             v8: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ebd3ec1		cmhs v1.2s, v22.2s, v29.2s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e7e3fda		cmhs v26.4h, v30.4h, v30.4h
-#   v26: 0x0000000000000000ffffffffffffffff
+#            v26: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6eb03e93		cmhs v19.4s, v20.4s, v16.4s
-#   v19: 0xffffffffffffffffffffffffffffffff
+#            v19: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e3a3c61		cmhs v1.8b, v3.8b, v26.8b
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e683f94		cmhs v20.8h, v28.8h, v8.8h
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  7ee09b1e		cmle d30, d24, #0
-#   v30: 0x0000000000000000ffffffffffffffff
+#            v30: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e209860		cmle v0.16b, v3.16b, #0
-#    v0: 0xffffffff00ffffffffffffffffffffff
+#             v0: 0xffffffff00ffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ee09bc2		cmle v2.2d, v30.2d, #0
-#    v2: 0xffffffffffffffffffffffffffffffff
+#             v2: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ea09947		cmle v7.2s, v10.2s, #0
-#    v7: 0x0000000000000000ffffffffffffffff
+#             v7: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e609be9		cmle v9.4h, v31.4h, #0
-#    v9: 0x0000000000000000ffffffffffffffff
+#             v9: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ea09a49		cmle v9.4s, v18.4s, #0
-#    v9: 0xffffffffffffffffffffffffffffffff
+#             v9: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e209bf5		cmle v21.8b, v31.8b, #0
-#   v21: 0x0000000000000000ffffffffffffffff
+#            v21: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e609abd		cmle v29.8h, v21.8h, #0
-#   v29: 0xffffffffffffffffffffffffffffffff
+#            v29: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  5ee0aaf9		cmlt d25, d23, #0
-#   v25: 0x0000000000000000ffffffffffffffff
+#            v25: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e20aaa7		cmlt v7.16b, v21.16b, #0
-#    v7: 0x0000000000000000ffffffffffffffff
+#             v7: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4ee0abc7		cmlt v7.2d, v30.2d, #0
-#    v7: 0x0000000000000000ffffffffffffffff
+#             v7: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0ea0ab99		cmlt v25.2s, v28.2s, #0
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e60a960		cmlt v0.4h, v11.4h, #0
-#    v0: 0x0000000000000000ffffffff00000000
+#             v0: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  4ea0a8b8		cmlt v24.4s, v5.4s, #0
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e20a97a		cmlt v26.8b, v11.8b, #0
-#   v26: 0x0000000000000000ffffffff00000000
+#            v26: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  4e60aaa1		cmlt v1.8h, v21.8h, #0
-#    v1: 0x0000000000000000ffffffffffffffff
+#             v1: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  5efe8efc		cmtst d28, d23, d30
-#   v28: 0x0000000000000000ffffffffffffffff
+#            v28: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e3f8cda		cmtst v26.16b, v6.16b, v31.16b
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee48ea1		cmtst v1.2d, v21.2d, v4.2d
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eb48f5b		cmtst v27.2s, v26.2s, v20.2s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e728c1a		cmtst v26.4h, v0.4h, v18.4h
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea48e19		cmtst v25.4s, v16.4s, v4.4s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e298d4b		cmtst v11.8b, v10.8b, v9.8b
-#   v11: 0x0000000000000000ff00ffffffff0000
+#            v11: 0x0000000000000000ff00ff00ffff0000
 0x~~~~~~~~~~~~~~~~  4e618c40		cmtst v0.8h, v2.8h, v1.8h
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2059f9		cnt v25.16b, v15.16b
-#   v25: 0x00000000000000000000000008080808
+#            v25: 0x00000000000000000000000008080808
 0x~~~~~~~~~~~~~~~~  0e2058dc		cnt v28.8b, v6.8b
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e0f04e6		dup v6.16b, v7.b[7]
-#    v6: 0xffffffffffffffffffffffffffffffff
+#             v6: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e010e89		dup v9.16b, w20
-#    v9: 0x01010101010101010101010101010101
+#             v9: 0x01010101010101010101010101010101
 0x~~~~~~~~~~~~~~~~  4e1805ac		dup v12.2d, v13.d[1]
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e080fe9		dup v9.2d, xzr
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e140744		dup v4.2s, v26.s[2]
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e040d83		dup v3.2s, w12
-#    v3: 0x0000000000000000ffffff7dffffff7d
+#             v3: 0x0000000000000000ffffff7dffffff7d
 0x~~~~~~~~~~~~~~~~  0e1e04b6		dup v22.4h, v5.h[7]
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e020f30		dup v16.4h, w25
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e140554		dup v20.4s, v10.s[2]
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e040cea		dup v10.4s, w7
-#   v10: 0x00000018000000180000001800000018
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e0507de		dup v30.8b, v30.b[2]
-#   v30: 0x0000000000000000ffffffffffffffff
+#            v30: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0e010dff		dup v31.8b, w15
-#   v31: 0x00000000000000000101010101010101
+#            v31: 0x00000000000000000101010101010101
 0x~~~~~~~~~~~~~~~~  4e12063c		dup v28.8h, v17.h[4]
-#   v28: 0xffffffffffffffffffffffffffffffff
+#            v28: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e020c62		dup v2.8h, w3
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e231f3d		eor v29.16b, v25.16b, v3.16b
-#   v29: 0x0000000000000000ffffff7df7f7f775
+#            v29: 0x0000000000000000ffffff7df7f7f775
 0x~~~~~~~~~~~~~~~~  2e3c1e03		eor v3.8b, v16.8b, v28.8b
-#    v3: 0x0000000000000000ffffffffffffffff
+#             v3: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e060b41		ext v1.16b, v26.16b, v6.16b, #1
-#    v1: 0xff000000000000000000000000000000
+#             v1: 0xff000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e010bc2		ext v2.8b, v30.8b, v1.8b, #1
-#    v2: 0x000000000000000000ffffffffffffff
+#             v2: 0x000000000000000000ffffffffffffff
 0x~~~~~~~~~~~~~~~~  4c402012		ld1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
-#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x3f3e3d3c3b3a39383736353433323130
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc22037		ld1 {v23.16b, v24.16b, v25.16b, v26.16b}, [x1], x2
-#   v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x0b0a09080706050403020100fffefdfc <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0b0a09080706050403020100fffefdfc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfb <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xeb <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xdb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf2025		ld1 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
-#    v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0a09080706050403020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x0a09080706050403020100fffefdfcfb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xeb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c406012		ld1 {v18.16b, v19.16b, v20.16b}, [x0]
-#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2602d		ld1 {v13.16b, v14.16b, v15.16b}, [x1], x2
-#   v13: 0x1a191817161514131211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x2a292827262524232221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x3a393837363534333231302f2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x3a393837363534333231302f2e2d2c2b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x2a292827262524232221201f1e1d1c1b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x1a191817161514131211100f0e0d0c0b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf6033		ld1 {v19.16b, v20.16b, v21.16b}, [x1], #48
-#   v19: 0x191817161514131211100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x292827262524232221201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x393837363534333231302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x393837363534333231302f2e2d2c2b2a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x292827262524232221201f1e1d1c1b1a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x191817161514131211100f0e0d0c0b0a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40a011		ld1 {v17.16b, v18.16b}, [x0]
-#   v17: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2a034		ld1 {v20.16b, v21.16b}, [x1], x2
-#   v20: 0x494847464544434241403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x595857565554535251504f4e4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x595857565554535251504f4e4d4c4b4a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x59 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x494847464544434241403f3e3d3c3b3a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdfa03c		ld1 {v28.16b, v29.16b}, [x1], #32
-#   v28: 0x4847464544434241403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x5857565554535251504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x5857565554535251504f4e4d4c4b4a49
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x49 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x4847464544434241403f3e3d3c3b3a39
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40701d		ld1 {v29.16b}, [x0]
-#   v29: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc27035		ld1 {v21.16b}, [x1], x2
-#   v21: 0x6867666564636261605f5e5d5c5b5a59 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x6867666564636261605f5e5d5c5b5a59
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x59 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x5a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x5b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x5c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x5d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x5e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x5f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x60 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x61 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x62 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x63 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x64 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x65 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x66 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x67 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x68 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf7024		ld1 {v4.16b}, [x1], #16
-#    v4: 0x67666564636261605f5e5d5c5b5a5958 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v4: 0x67666564636261605f5e5d5c5b5a5958
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x59 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x5a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x5b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x5c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x5d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x5e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x5f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x60 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x61 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x62 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x63 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x64 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x65 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x66 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x67 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c402c04		ld1 {v4.1d, v5.1d, v6.1d, v7.1d}, [x0]
-#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000001f1e1d1c1b1a1918 (d7: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc22c31		ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x1], x2
-#   v17: 0x00000000000000006f6e6d6c6b6a6968 (d17: 5.76650e+228) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000007776757473727170 (d18: 2.89670e+267) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000007f7e7d7c7b7a7978 (d19: 1.33818e+306) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000008786858483828180 (d20: -2.08158e-272) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x8786858483828180 (-2.082e-272)
+#                                                  ╙─ 0x8786858483828180 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x7f7e7d7c7b7a7978 (1.338e+306)
+#                                                  ╙─ 0x7f7e7d7c7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#            d18:                 0x7776757473727170 (2.897e+267)
+#                                                  ╙─ 0x7776757473727170 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x6f6e6d6c6b6a6968 (5.766e+228)
+#                                                  ╙─ 0x6f6e6d6c6b6a6968 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf2c3c		ld1 {v28.1d, v29.1d, v30.1d, v31.1d}, [x1], #32
-#   v28: 0x00000000000000006e6d6c6b6a696867 (d28: 8.50866e+223) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000767574737271706f (d29: 4.22243e+262) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000007e7d7c7b7a797877 (d30: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x0000000000000000868584838281807f (d31: -3.03465e-277) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x868584838281807f (-3.035e-277)
+#                                                  ╙─ 0x868584838281807f <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0x7e7d7c7b7a797877 (1.975e+301)
+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x767574737271706f (4.222e+262)
+#                                                  ╙─ 0x767574737271706f <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x6e6d6c6b6a696867 (8.509e+223)
+#                                                  ╙─ 0x6e6d6c6b6a696867 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c406c14		ld1 {v20.1d, v21.1d, v22.1d}, [x0]
-#   v20: 0x0000000000000000ff0000850002ff01 (d20: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x00000000000000000000000000fffeff (d21: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x00000000000000001700000000000000 (d22: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc26c33		ld1 {v19.1d, v20.1d, v21.1d}, [x1], x2
-#   v19: 0x00000000000000008e8d8c8b8a898887 (d19: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x0000000000000000969594939291908f (d20: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x00000000000000009e9d9c9b9a999897 (d21: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x9e9d9c9b9a999897 (-3.291e-161)
+#                                                  ╙─ 0x9e9d9c9b9a999897 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x969594939291908f (-7.048e-200)
+#                                                  ╙─ 0x969594939291908f <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x8e8d8c8b8a898887 (-1.418e-238)
+#                                                  ╙─ 0x8e8d8c8b8a898887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf6c2c		ld1 {v12.1d, v13.1d, v14.1d}, [x1], #24
-#   v12: 0x00000000000000008d8c8b8a89888786 (d12: -2.09028e-243) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x00000000000000009594939291908f8e (d13: -1.02545e-204) <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x00000000000000009d9c9b9a99989796 (d14: -4.85140e-166) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x9d9c9b9a99989796 (-4.851e-166)
+#                                                  ╙─ 0x9d9c9b9a99989796 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x9594939291908f8e (-1.025e-204)
+#                                                  ╙─ 0x9594939291908f8e <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x8d8c8b8a89888786 (-2.090e-243)
+#                                                  ╙─ 0x8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40ac1d		ld1 {v29.1d, v30.1d}, [x0]
-#   v29: 0x0000000000000000ff0000850002ff01 (d29: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000000000000000fffeff (d30: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2ac3f		ld1 {v31.1d, v0.1d}, [x1], x2
-#   v31: 0x0000000000000000a5a4a3a2a1a09f9e (d31: -2.38202e-127) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x0000000000000000adacabaaa9a8a7a6 (d0: -1.12597e-88) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xadacabaaa9a8a7a6 (-1.126e-88)
+#                                                  ╙─ 0xadacabaaa9a8a7a6 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0xa5a4a3a2a1a09f9e (-2.382e-127)
+#                                                  ╙─ 0xa5a4a3a2a1a09f9e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdfac23		ld1 {v3.1d, v4.1d}, [x1], #16
-#    v3: 0x0000000000000000a4a3a2a1a09f9e9d (d3: -3.45787e-132) <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000acabaaa9a8a7a6a5 (d4: -1.65794e-93) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xacabaaa9a8a7a6a5 (-1.658e-93)
+#                                                  ╙─ 0xacabaaa9a8a7a6a5 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xa4a3a2a1a09f9e9d (-3.458e-132)
+#                                                  ╙─ 0xa4a3a2a1a09f9e9d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c407c1c		ld1 {v28.1d}, [x0]
-#   v28: 0x0000000000000000ff0000850002ff01 (d28: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc27c2b		ld1 {v11.1d}, [x1], x2
-#   v11: 0x0000000000000000b4b3b2b1b0afaead (d11: -8.03348e-55) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xb4b3b2b1b0afaead (-8.033e-55)
+#                                                  ╙─ 0xb4b3b2b1b0afaead <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf7c3d		ld1 {v29.1d}, [x1], #8
-#   v29: 0x0000000000000000b3b2b1b0afaeadac (d29: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c402c1c		ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0]
-#   v28: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x3f3e3d3c3b3a39383736353433323130 (0.000461414, 9.95833e-43) <- 0x~~~~~~~~~~~~~~~~
+#            v31: 0x3f3e3d3c3b3a39383736353433323130 (0.0004614, 9.958e-43)
+#                                  ║               ╙─ 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x2f2e2d2c2b2a29282726252423222120 (1.988e-81, 4.288e-120)
+#                                  ║               ╙─ 0x2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc22c28		ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x1], x2
-#    v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.70315e+18, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.28100e+95, -1.31369e+57) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.45943e+173, -3.04943e+134) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.39104e+250, -7.07849e+211) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.391e+250, -7.078e+211)
+#                                  ║               ╙─ 0xebeae9e8e7e6e5e4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xf3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.459e+173, -3.049e+134)
+#                                  ║               ╙─ 0xdbdad9d8d7d6d5d4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.281e+95, -1.314e+57)
+#                                  ║               ╙─ 0xcbcac9c8c7c6c5c4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xd3d2d1d0cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.703e+18, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xc3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf2c2e		ld1 {v14.2d, v15.2d, v16.2d, v17.2d}, [x1], #64
-#   v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.90391e+13, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.07279e+90, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.10851e+168, -4.47908e+129) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.90012e+245, -1.03980e+207) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.900e+245, -1.040e+207)
+#                                  ║               ╙─ 0xeae9e8e7e6e5e4e3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xf2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.109e+168, -4.479e+129)
+#                                  ║               ╙─ 0xdad9d8d7d6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.073e+90, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.904e+13, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xc2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c406c1a		ld1 {v26.2d, v27.2d, v28.2d}, [x0]
-#   v26: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.988e-81, 4.288e-120)
+#                                  ║               ╙─ 0x2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc26c25		ld1 {v5.2d, v6.2d, v7.2d}, [x1], x2
-#    v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.07812e-299, -2.41385e+284) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x1211100f0e0d0c0b0a09080706050403 (1.18008e-221, 2.54377e-260) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x2221201f1e1d1c1b1a19181716151413 (2.74293e-144, 5.90574e-183) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2221201f1e1d1c1b1a19181716151413 (2.743e-144, 5.906e-183)
+#                                  ║               ╙─ 0x1a19181716151413 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1211100f0e0d0c0b0a09080706050403 (1.180e-221, 2.544e-260)
+#                                  ║               ╙─ 0x0a09080706050403 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.078e-299, -2.414e+284)
+#                                  ║               ╙─ 0xfaf9f8f7f6f5f4f3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf6c3a		ld1 {v26.2d, v27.2d, v28.2d}, [x1], #48
-#   v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.74681e-304, -3.54087e+279) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x11100f0e0d0c0b0a0908070605040302 (1.69471e-226, 3.72581e-265) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x21201f1e1d1c1b1a1918171615141312 (3.94003e-149, 8.65093e-188) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x21201f1e1d1c1b1a1918171615141312 (3.940e-149, 8.651e-188)
+#                                  ║               ╙─ 0x1918171615141312 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x21201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x11100f0e0d0c0b0a0908070605040302 (1.695e-226, 3.726e-265)
+#                                  ║               ╙─ 0x0908070605040302 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x11100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.747e-304, -3.541e+279)
+#                                  ║               ╙─ 0xf9f8f7f6f5f4f3f2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0100fffefdfcfbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40ac12		ld1 {v18.2d, v19.2d}, [x0]
-#   v18: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2ac35		ld1 {v21.2d, v22.2d}, [x1], x2
-#   v21: 0x31302f2e2d2c2b2a2928272625242322 (9.15999e-72, 2.00864e-110) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x41403f3e3d3c3b3a3938373635343332 (2.12953e+06, 4.66377e-33) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x41403f3e3d3c3b3a3938373635343332 (2.130e+06, 4.664e-33)
+#                                  ║               ╙─ 0x3938373635343332 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x41403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x31302f2e2d2c2b2a2928272625242322 (9.160e-72, 2.009e-110)
+#                                  ║               ╙─ 0x2928272625242322 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x31302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdfac31		ld1 {v17.2d, v18.2d}, [x1], #32
-#   v17: 0x302f2e2d2c2b2a292827262524232221 (1.34639e-76, 2.93754e-115) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x403f3e3d3c3b3a393837363534333231 (31.2431, 6.82132e-38) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0x403f3e3d3c3b3a393837363534333231 (31.24, 6.821e-38)
+#                                  ║               ╙─ 0x3837363534333231 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x302f2e2d2c2b2a292827262524232221 (1.346e-76, 2.938e-115)
+#                                  ║               ╙─ 0x2827262524232221 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x302f2e2d2c2b2a29 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c407c05		ld1 {v5.2d}, [x0]
-#    v5: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc27c26		ld1 {v6.2d}, [x1], x2
-#    v6: 0x504f4e4d4c4b4a494847464544434241 (7.24994e+78, 1.58398e+40) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x504f4e4d4c4b4a494847464544434241 (7.250e+78, 1.584e+40)
+#                                  ║               ╙─ 0x4847464544434241 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf7c2f		ld1 {v15.2d}, [x1], #16
-#   v15: 0x4f4e4d4c4b4a49484746454443424140 (1.07078e+74, 2.31271e+35) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x4f4e4d4c4b4a49484746454443424140 (1.071e+74, 2.313e+35)
+#                                  ║               ╙─ 0x4746454443424140 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x4f4e4d4c4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40281e		ld1 {v30.2s, v31.2s, v0.2s, v1.2s}, [x0]
-#   v30: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x00000000000000001f1e1d1c1b1a1918 (..., 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x1f1e1d1c1b1a1918 (3.348e-20, 1.275e-22)
+#                                          ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x1700000000000000 (4.136e-25, 0.000)
+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc22838		ld1 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
-#   v24: 0x00000000000000005756555453525150 (..., 2.35662e+14, 9.03307e+11) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000005f5e5d5c5b5a5958 (..., 1.60231e+19, 6.14598e+16) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x00000000000000006766656463626160 (..., 1.08801e+24, 4.17598e+21) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000006f6e6d6c6b6a6968 (..., 7.37897e+28, 2.83386e+26) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x6f6e6d6c6b6a6968 (7.379e+28, 2.834e+26)
+#                                          ║       ╙─ 0x6b6a6968 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x6f6e6d6c <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x6766656463626160 (1.088e+24, 4.176e+21)
+#                                          ║       ╙─ 0x63626160 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x67666564 <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0x5f5e5d5c5b5a5958 (1.602e+19, 6.146e+16)
+#                                          ║       ╙─ 0x5b5a5958 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x5f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x5756555453525150 (2.357e+14, 9.033e+11)
+#                                          ║       ╙─ 0x53525150 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x57565554 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf283b		ld1 {v27.2s, v28.2s, v29.2s, v30.2s}, [x1], #32
-#   v27: 0x0000000000000000565554535251504f (..., 5.86395e+13, 2.24749e+11) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00000000000000005e5d5c5b5a595857 (..., 3.98768e+18, 1.52943e+16) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000666564636261605f (..., 2.70818e+23, 1.03937e+21) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000006e6d6c6b6a696867 (..., 1.83698e+28, 7.05432e+25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d30:                 0x6e6d6c6b6a696867 (1.837e+28, 7.054e+25)
+#                                          ║       ╙─ 0x6a696867 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x666564636261605f (2.708e+23, 1.039e+21)
+#                                          ║       ╙─ 0x6261605f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x66656463 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x5e5d5c5b5a595857 (3.988e+18, 1.529e+16)
+#                                          ║       ╙─ 0x5a595857 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x565554535251504f (5.864e+13, 2.247e+11)
+#                                          ║       ╙─ 0x5251504f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x56555453 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40680b		ld1 {v11.2s, v12.2s, v13.2s}, [x0]
-#   v11: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x1700000000000000 (4.136e-25, 0.000)
+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc26828		ld1 {v8.2s, v9.2s, v10.2s}, [x1], x2
-#    v8: 0x0000000000000000767574737271706f (..., 1.24460e+33, 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x00000000000000007e7d7c7b7a797877 (..., 8.42353e+37, 3.23831e+35) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x0000000000000000868584838281807f (..., -5.02237e-35, -1.90286e-37) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x868584838281807f (-5.022e-35, -1.903e-37)
+#                                          ║       ╙─ 0x8281807f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x86858483 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7e7d7c7b7a797877 (8.424e+37, 3.238e+35)
+#                                          ║       ╙─ 0x7a797877 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7e7d7c7b <- 0x~~~~~~~~~~~~~~~~
+#             d8:                 0x767574737271706f (1.245e+33, 4.782e+30)
+#                                          ║       ╙─ 0x7271706f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf683f		ld1 {v31.2s, v0.2s, v1.2s}, [x1], #24
-#   v31: 0x00000000000000007574737271706f6e (..., 3.09878e+32, 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000007d7c7b7a79787776 (..., 2.09754e+37, 8.06320e+34) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x00000000000000008584838281807f7e (..., -1.24615e-35, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8584838281807f7e (-1.246e-35, -4.720e-38)
+#                                          ║       ╙─ 0x81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x85848382 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x7d7c7b7a79787776 (2.098e+37, 8.063e+34)
+#                                          ║       ╙─ 0x79787776 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7d7c7b7a <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x7574737271706f6e (3.099e+32, 1.191e+30)
+#                                          ║       ╙─ 0x71706f6e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x75747372 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40a800		ld1 {v0.2s, v1.2s}, [x0]
-#    v0: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2a82d		ld1 {v13.2s, v14.2s}, [x1], x2
-#   v13: 0x00000000000000008d8c8b8a89888786 (..., -8.66176e-31, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x00000000000000009594939291908f8e (..., -6.00095e-26, -2.28077e-28) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x9594939291908f8e (-6.001e-26, -2.281e-28)
+#                                          ║       ╙─ 0x91908f8e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x95949392 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x8d8c8b8a89888786 (-8.662e-31, -3.287e-33)
+#                                          ║       ╙─ 0x89888786 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8d8c8b8a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdfa823		ld1 {v3.2s, v4.2s}, [x1], #16
-#    v3: 0x00000000000000008c8b8a8988878685 (..., -2.14997e-31, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x000000000000000094939291908f8e8d (..., -1.49010e-26, -5.66232e-29) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x94939291908f8e8d (-1.490e-26, -5.662e-29)
+#                                          ║       ╙─ 0x908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x94939291 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0x8c8b8a8988878685 (-2.150e-31, -8.157e-34)
+#                                          ║       ╙─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40781a		ld1 {v26.2s}, [x0]
-#   v26: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc27820		ld1 {v0.2s}, [x1], x2
-#    v0: 0x00000000000000009c9b9a9998979695 (..., -1.02970e-21, -3.91846e-24) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x9c9b9a9998979695 (-1.030e-21, -3.918e-24)
+#                                          ║       ╙─ 0x98979695 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf782b		ld1 {v11.2s}, [x1], #8
-#   v11: 0x00000000000000009b9a999897969594 (..., -2.55764e-22, -9.73128e-25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x9b9a999897969594 (-2.558e-22, -9.731e-25)
+#                                          ║       ╙─ 0x97969594 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9b9a9998 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c402410		ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
-#   v16: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x1f1e1d1c1b1a1918 (0.006950, 0.004990, 0.003468, 0.002487)
+#                                      ║   ║   ║   ╙─ 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            d18:                 0x1700000000000000 (0.001709, 0.000, 0.000, 0.000)
+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc22438		ld1 {v24.4h, v25.4h, v26.4h, v27.4h}, [x1], x2
-#   v24: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x0000000000000000abaaa9a8a7a6a5a4 <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x0000000000000000b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000bbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xbbbab9b8b7b6b5b4 (-0.9658, -0.7148, -0.4819, -0.3564)
+#                                      ║   ║   ║   ╙─ 0xb5b4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb7b6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb9b8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xb3b2b1b0afaeadac (-0.2405, -0.1777, -0.1200, -0.08862)
+#                                      ║   ║   ║   ╙─ 0xadac <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xafae <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb1b0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb3b2 <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xabaaa9a8a7a6a5a4 (-0.05988, -0.04419, -0.02988, -0.02203)
+#                                      ║   ║   ║   ╙─ 0xa5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa7a6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa9a8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xabaa <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0xa3a2a1a09f9e9d9c (-0.01491, -0.01099, -0.007439, -0.005478)
+#                                      ║   ║   ║   ╙─ 0x9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9f9e <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa1a0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa3a2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf2421		ld1 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
-#    v1: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xbab9b8b7b6b5b4b3 (-0.8403, -0.5894, -0.4192, -0.2937)
+#                                      ║   ║   ║   ╙─ 0xb4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb6b5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb8b7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbab9 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xb2b1b0afaeadacab (-0.2091, -0.1464, -0.1043, -0.07294)
+#                                      ║   ║   ║   ╙─ 0xacab <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xaead <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb0af <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb2b1 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xaaa9a8a7a6a5a4a3 (-0.05203, -0.03635, -0.02596, -0.01811)
+#                                      ║   ║   ║   ╙─ 0xa4a3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa8a7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xaaa9 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xa2a1a09f9e9d9c9b (-0.01295, -0.009026, -0.006458, -0.004498)
+#                                      ║   ║   ║   ╙─ 0x9c9b <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa09f <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa2a1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40641e		ld1 {v30.4h, v31.4h, v0.4h}, [x0]
-#   v30: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x1700000000000000 (0.001709, 0.000, 0.000, 0.000)
+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc26439		ld1 {v25.4h, v26.4h, v27.4h}, [x1], x2
-#   v25: 0x0000000000000000c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x0000000000000000cac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xd2d1d0cfcecdcccb (-54.53, -38.47, -27.20, -19.17)
+#                                      ║   ║   ║   ╙─ 0xcccb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcecd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xcac9c8c7c6c5c4c3 (-13.57, -9.555, -6.770, -4.762)
+#                                      ║   ║   ║   ╙─ 0xc4c3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xc6c5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc8c7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xcac9 <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xc2c1c0bfbebdbcbb (-3.377, -2.373, -1.685, -1.183)
+#                                      ║   ║   ║   ╙─ 0xbcbb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbebd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc0bf <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc2c1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf6423		ld1 {v3.4h, v4.4h, v5.4h}, [x1], #24
-#    v3: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0000000000000000d1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d5:                 0xd1d0cfcecdcccbca (-46.50, -31.22, -23.19, -15.58)
+#                                      ║   ║   ║   ╙─ 0xcbca <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcdcc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xcfce <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xc9c8c7c6c5c4c3c2 (-11.56, -7.773, -5.766, -3.879)
+#                                      ║   ║   ║   ╙─ 0xc3c2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xc5c4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc7c6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc9c8 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xc1c0bfbebdbcbbba (-2.875, -1.936, -1.434, -0.9658)
+#                                      ║   ║   ║   ╙─ 0xbbba <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbdbc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xbfbe <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc1c0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40a403		ld1 {v3.4h, v4.4h}, [x0]
-#    v3: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2a423		ld1 {v3.4h, v4.4h}, [x1], x2
-#    v3: 0x0000000000000000d9d8d7d6d5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000e1e0dfdedddcdbda <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xe1e0dfdedddcdbda (-752.0, -503.5, -375.0, -251.2)
+#                                      ║   ║   ║   ╙─ 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xd9d8d7d6d5d4d3d2 (-187.0, -125.4, -93.25, -62.56)
+#                                      ║   ║   ║   ╙─ 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdfa437		ld1 {v23.4h, v24.4h}, [x1], #16
-#   v23: 0x0000000000000000d8d7d6d5d4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000e0dfdedddcdbdad9 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d24:                 0xe0dfdedddcdbdad9 (-623.5, -439.2, -310.8, -219.1)
+#                                      ║   ║   ║   ╙─ 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xd8d7d6d5d4d3d2d1 (-154.9, -109.3, -77.19, -54.53)
+#                                      ║   ║   ║   ╙─ 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40741a		ld1 {v26.4h}, [x0]
-#   v26: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc27421		ld1 {v1.4h}, [x1], x2
-#    v1: 0x0000000000000000e8e7e6e5e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe8e7e6e5e4e3e2e1 (-2510., -1765., -1251., -880.5)
+#                                      ║   ║   ║   ╙─ 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf742e		ld1 {v14.4h}, [x1], #8
-#   v14: 0x0000000000000000e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0xe7e6e5e4e3e2e1e0 (-2022., -1508., -1009., -752.0)
+#                                      ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40281a		ld1 {v26.4s, v27.4s, v28.4s, v29.4s}, [x0]
-#   v26: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x3f3e3d3c3b3a39383736353433323130 (0.743122, 0.00284155, 1.08604e-05, 4.14886e-08) <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x3f3e3d3c3b3a39383736353433323130 (0.7431, 0.002842, 1.086e-05, 4.149e-08)
+#                          ║       ║       ║       ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2283c		ld1 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
-#   v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.00179e+34, -3.84962e+31, -1.47890e+29, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.00825e-34, 3.82047e-37, nan, -2.60629e+36) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x17161514131211100f0e0d0c0b0a0908 (4.84942e-25, 1.84362e-27, 7.00365e-30, 2.65846e-32) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x27262524232221201f1e1d1c1b1a1918 (2.30573e-15, 8.78905e-18, 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v31: 0x27262524232221201f1e1d1c1b1a1918 (2.306e-15, 8.789e-18, 3.348e-20, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x17161514131211100f0e0d0c0b0a0908 (4.849e-25, 1.844e-27, 7.004e-30, 2.658e-32)
+#                          ║       ║       ║       ╙─ 0x0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x17161514 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.008e-34, 3.820e-37, nan, -2.606e+36)
+#                          ║       ║       ║       ╙─ 0xfbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.002e+34, -3.850e+31, -1.479e+29, -5.680e+26)
+#                          ║       ║       ║       ╙─ 0xebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xefeeedec <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf7f6f5f4 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf2824		ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64
-#    v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.49430e+33, -9.58428e+30, -3.68172e+28, -1.41390e+26) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.50175e-35, 9.47771e-38, -1.68804e+38, -6.48966e+35) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x161514131211100f0e0d0c0b0a090807 (1.20425e-25, 4.57737e-28, 1.73854e-30, 6.59782e-33) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x262524232221201f1e1d1c1b1a191817 (5.72948e-16, 2.18366e-18, 8.31732e-21, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x262524232221201f1e1d1c1b1a191817 (5.729e-16, 2.184e-18, 8.317e-21, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2221201f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x26252423 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x161514131211100f0e0d0c0b0a090807 (1.204e-25, 4.577e-28, 1.739e-30, 6.598e-33)
+#                          ║       ║       ║       ╙─ 0x0a090807 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x16151413 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.502e-35, 9.478e-38, -1.688e+38, -6.490e+35)
+#                          ║       ║       ║       ╙─ 0xfaf9f8f7 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x020100ff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x06050403 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.494e+33, -9.584e+30, -3.682e+28, -1.414e+26)
+#                          ║       ║       ║       ╙─ 0xeae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf6f5f4f3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c406802		ld1 {v2.4s, v3.4s, v4.4s}, [x0]
-#    v2: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc26836		ld1 {v22.4s, v23.4s, v24.4s}, [x1], x2
-#   v22: 0x363534333231302f2e2d2c2b2a292827 (2.70015e-06, 1.03137e-08, 3.93749e-11, 1.50241e-13) <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x464544434241403f3e3d3c3b3a393837 (12625.1, 48.3127, 0.184800, 0.000706557) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x565554535251504f4e4d4c4b4a494847 (5.86395e+13, 2.24749e+11, 8.61082e+08, 3.29781e+06) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x565554535251504f4e4d4c4b4a494847 (5.864e+13, 2.247e+11, 8.611e+08, 3.298e+06)
+#                          ║       ║       ║       ╙─ 0x4a494847 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x4e4d4c4b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x5251504f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x56555453 <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0x464544434241403f3e3d3c3b3a393837 (1.263e+04, 48.31, 0.1848, 0.0007066)
+#                          ║       ║       ║       ╙─ 0x3a393837 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x3e3d3c3b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x4241403f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x46454443 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x363534333231302f2e2d2c2b2a292827 (2.700e-06, 1.031e-08, 3.937e-11, 1.502e-13)
+#                          ║       ║       ║       ╙─ 0x2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3231302f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x36353433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf682f		ld1 {v15.4s, v16.4s, v17.4s}, [x1], #48
-#   v15: 0x3534333231302f2e2d2c2b2a29282726 (6.71297e-07, 2.56382e-09, 9.78665e-12, 3.73374e-14) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x4544434241403f3e3d3c3b3a39383736 (3140.20, 12.0154, 0.0459549, 0.000175682) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x5554535251504f4e4d4c4b4a49484746 (1.45909e+13, 5.59177e+10, 2.14218e+08, 820340.) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v17: 0x5554535251504f4e4d4c4b4a49484746 (1.459e+13, 5.592e+10, 2.142e+08, 8.203e+05)
+#                          ║       ║       ║       ╙─ 0x49484746 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x51504f4e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x55545352 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x4544434241403f3e3d3c3b3a39383736 (3140., 12.02, 0.04595, 0.0001757)
+#                          ║       ║       ║       ╙─ 0x39383736 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x41403f3e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x45444342 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x3534333231302f2e2d2c2b2a29282726 (6.713e-07, 2.564e-09, 9.787e-12, 3.734e-14)
+#                          ║       ║       ║       ╙─ 0x29282726 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x31302f2e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x35343332 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40a814		ld1 {v20.4s, v21.4s}, [x0]
-#   v20: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2a83e		ld1 {v30.4s, v31.4s}, [x1], x2
-#   v30: 0x6564636261605f5e5d5c5b5a59585756 (6.74083e+22, 2.58684e+20, 9.92399e+17, 3.80591e+15) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x7574737271706f6e6d6c6b6a69686766 (3.09878e+32, 1.19058e+30, 4.57302e+27, 1.75599e+25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v31: 0x7574737271706f6e6d6c6b6a69686766 (3.099e+32, 1.191e+30, 4.573e+27, 1.756e+25)
+#                          ║       ║       ║       ╙─ 0x69686766 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x6d6c6b6a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x71706f6e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x75747372 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x6564636261605f5e5d5c5b5a59585756 (6.741e+22, 2.587e+20, 9.924e+17, 3.806e+15)
+#                          ║       ║       ║       ╙─ 0x59585756 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5d5c5b5a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x61605f5e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x65646362 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdfa82b		ld1 {v11.4s, v12.4s}, [x1], #32
-#   v11: 0x64636261605f5e5d5c5b5a5958575655 (1.67780e+22, 6.43816e+19, 2.46969e+17, 9.47063e+14) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x74737271706f6e6d6c6b6a6968676665 (7.71514e+31, 2.96402e+29, 1.13840e+27, 4.37102e+24) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x74737271706f6e6d6c6b6a6968676665 (7.715e+31, 2.964e+29, 1.138e+27, 4.371e+24)
+#                          ║       ║       ║       ╙─ 0x68676665 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x6c6b6a69 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x706f6e6d <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x74737271 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0x64636261605f5e5d5c5b5a5958575655 (1.678e+22, 6.438e+19, 2.470e+17, 9.471e+14)
+#                          ║       ║       ║       ╙─ 0x58575655 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5c5b5a59 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x64636261 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40780f		ld1 {v15.4s}, [x0]
-#   v15: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2782c		ld1 {v12.4s}, [x1], x2
-#   v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.09178e-36, -1.17085e-38, 5.22300e+36, 2.00766e+34) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.092e-36, -1.171e-38, 5.223e+36, 2.008e+34)
+#                          ║       ║       ║       ╙─ 0x78777675 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x84838281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf7820		ld1 {v0.4s}, [x1], #16
-#    v0: 0x838281807f7e7d7c7b7a797877767574 (-7.67045e-37, 3.38275e+38, 1.30054e+36, 4.99878e+33) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v0: 0x838281807f7e7d7c7b7a797877767574 (-7.670e-37, 3.383e+38, 1.301e+36, 4.999e+33)
+#                          ║       ║       ║       ╙─ 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f7e7d7c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x83828180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c402011		ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x0]
-#   v17: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x1f1e1d1c1b1a1918
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x1700000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#            d18:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc22025		ld1 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], x2
-#    v5: 0x00000000000000008b8a898887868584 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x0000000000000000939291908f8e8d8c <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000009b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xa3a2a1a09f9e9d9c
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x9c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x9d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x9e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x9f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x9b9a999897969594
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x94 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x95 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x96 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x97 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x98 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x99 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x9a <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x9b <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x939291908f8e8d8c
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x8d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x8e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x8f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x90 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x91 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x92 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x93 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x8b8a898887868584
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x84 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x86 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x87 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x88 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x89 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x8a <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf2029		ld1 {v9.8b, v10.8b, v11.8b, v12.8b}, [x1], #32
-#    v9: 0x00000000000000008a89888786858483 <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000009291908f8e8d8c8b <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000009a99989796959493 <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xa2a1a09f9e9d9c9b
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x9b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x9c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x9d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x9e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x9f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x9a99989796959493
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x93 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x94 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x95 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x96 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x97 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x98 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x99 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x9a <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x9291908f8e8d8c8b
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x8c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x8d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x8e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x8f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x90 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x91 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x92 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x8a89888786858483
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x83 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x84 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x86 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x87 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x88 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x89 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x8a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c406004		ld1 {v4.8b, v5.8b, v6.8b}, [x0]
-#    v4: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x1700000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc26022		ld1 {v2.8b, v3.8b, v4.8b}, [x1], x2
-#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xbab9b8b7b6b5b4b3
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xb4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xb5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xb6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xb7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xba <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xb2b1b0afaeadacab
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xab <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xac <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xad <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xae <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xaf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb2 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xaaa9a8a7a6a5a4a3
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xa4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xa5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xa6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xaa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf602c		ld1 {v12.8b, v13.8b, v14.8b}, [x1], #24
-#   v12: 0x0000000000000000a9a8a7a6a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0000000000000000b1b0afaeadacabaa <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x0000000000000000b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0xb9b8b7b6b5b4b3b2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xb3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xb4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xb5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xb6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0xb1b0afaeadacabaa
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xaa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xab <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xac <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xad <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xae <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xaf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb1 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xa9a8a7a6a5a4a3a2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xa4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xa5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40a00a		ld1 {v10.8b, v11.8b}, [x0]
-#   v10: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2a02b		ld1 {v11.8b, v12.8b}, [x1], x2
-#   v11: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xc9c8c7c6c5c4c3c2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xc1c0bfbebdbcbbba
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdfa03b		ld1 {v27.8b, v28.8b}, [x1], #16
-#   v27: 0x0000000000000000c0bfbebdbcbbbab9 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x0000000000000000c8c7c6c5c4c3c2c1 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xc8c7c6c5c4c3c2c1
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xc0bfbebdbcbbbab9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40701f		ld1 {v31.8b}, [x0]
-#   v31: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2702a		ld1 {v10.8b}, [x1], x2
-#   v10: 0x0000000000000000d0cfcecdcccbcac9 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xd0cfcecdcccbcac9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf703c		ld1 {v28.8b}, [x1], #8
-#   v28: 0x0000000000000000cfcecdcccbcac9c8 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xcfcecdcccbcac9c8
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c402405		ld1 {v5.8h, v6.8h, v7.8h, v8.8h}, [x0]
-#    v5: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0x3f3e3d3c3b3a39383736353433323130 (1.811, 1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc22422		ld1 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
-#    v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0f0e0d0c0b0a09080706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0f0e0d0c0b0a09080706050403020100 (0.0004306, 0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 (nan, nan, -6.534e+04, -4.890e+04, -3.261e+04, -2.438e+04, -1.627e+04, -1.216e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf1f0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf3f2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf5f4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf7f6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfbfa <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfdfc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 (-8120., -6064., -4052., -3024., -2022., -1508., -1009., -752.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe9e8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xebea <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xedec <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xefee <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 (-503.5, -375.0, -251.2, -187.0, -125.4, -93.25, -62.56, -46.50)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf242a		ld1 {v10.8h, v11.8h, v12.8h, v13.8h}, [x1], #64
-#   v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0e0d0c0b0a09080706050403020100ff <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b0a09080706050403020100ff (0.0003693, 0.0002468, 0.0001842, 0.0001229, 9.185e-05, 6.121e-05, 3.058e-05, 1.520e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0201 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0605 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0807 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0a09 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0c0b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0e0d <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef (nan, nan, -5.712e+04, -4.067e+04, -2.850e+04, -2.027e+04, -1.422e+04, -1.010e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf0ef <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf2f1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf4f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf6f5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf8f7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfcfb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfefd <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df (-7092., -5036., -3538., -2510., -1765., -1251., -880.5, -623.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xeae9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xeceb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xeeed <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf (-439.2, -310.8, -219.1, -154.9, -109.3, -77.19, -54.53, -38.47)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40641a		ld1 {v26.8h, v27.8h, v28.8h}, [x0]
-#   v26: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc26423		ld1 {v3.8h, v4.8h, v5.8h}, [x1], x2
-#    v3: 0x1e1d1c1b1a191817161514131211100f <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x2e2d2c2b2a292827262524232221201f <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x3e3d3c3b3a393837363534333231302f <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3e3d3c3b3a393837363534333231302f (1.560, 1.058, 0.7778, 0.5269, 0.3879, 0.2625, 0.1935, 0.1307)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x302f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3433 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3635 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3837 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3c3b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2e2d2c2b2a292827262524232221201f (0.09650, 0.06512, 0.04813, 0.03244, 0.02400, 0.01616, 0.01197, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2e2d <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1e1d1c1b1a191817161514131211100f (0.005970, 0.004009, 0.002977, 0.001997, 0.001485, 0.0009947, 0.0007405, 0.0004954)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x100f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1211 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1413 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1615 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1e1d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf6431		ld1 {v17.8h, v18.8h, v19.8h}, [x1], #48
-#   v17: 0x1d1c1b1a191817161514131211100f0e <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x2d2c2b2a292827262524232221201f1e <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x3d3c3b3a393837363534333231302f2e <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a393837363534333231302f2e (1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40a404		ld1 {v4.8h, v5.8h}, [x0]
-#    v4: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2a435		ld1 {v21.8h, v22.8h}, [x1], x2
-#   v21: 0x4d4c4b4a494847464544434241403f3e <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x5d5c5b5a595857565554535251504f4e <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x5d5c5b5a595857565554535251504f4e (343.0, 235.2, 171.0, 117.4, 85.25, 58.56, 42.50, 29.22)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4f4e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5150 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5554 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5958 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5b5a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdfa424		ld1 {v4.8h, v5.8h}, [x1], #32
-#    v4: 0x4c4b4a494847464544434241403f3e3d <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x5c5b5a595857565554535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857565554535251504f4e4d (278.8, 203.1, 138.9, 101.3, 69.19, 50.53, 34.47, 25.20)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4e4d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x504f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5251 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5453 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5857 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5a59 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5c5b <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x4c4b4a494847464544434241403f3e3d (17.17, 12.57, 8.555, 6.270, 4.262, 3.127, 2.123, 1.560)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x403f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4443 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4645 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4c4b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c407409		ld1 {v9.8h}, [x0]
-#    v9: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2743b		ld1 {v27.8h}, [x1], x2
-#   v27: 0x6c6b6a696867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a696867666564636261605f5e5d (4524., 3282., 2254., 1637., 1123., 816.5, 559.5, 407.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5e5d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6463 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6665 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6a69 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6c6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf743a		ld1 {v26.8h}, [x1], #16
-#   v26: 0x6b6a696867666564636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x6b6a696867666564636261605f5e5d5c (3796., 2768., 1894., 1380., 945.0, 688.0, 471.5, 343.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6766 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6b6a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d400413		ld1 {v19.b}[1], [x0]
-#   v19: 0x3d3c3b3a39383736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a39383736353433323130012e
+#                                                ╙─── 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc20c2c		ld1 {v12.b}[3], [x1], x2
-#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef
+#                                            ╙─────── 0x6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddf103b		ld1 {v27.b}[12], [x1], #1
-#   v27: 0x6c6b6a6b6867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a6b6867666564636261605f5e5d
+#                          ╙───────────────────────── 0x6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40840a		ld1 {v10.d}[1], [x0]
-#   v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.487e+303, ...)
+#                                  ╙───────────────── 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2843a		ld1 {v26.d}[1], [x1], x2
-#   v26: 0x737271706f6e6d6c636261605f5e5d5c (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x737271706f6e6d6c636261605f5e5d5c (1.290e+248, ...)
+#                                  ╙───────────────── 0x737271706f6e6d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddf8427		ld1 {v7.d}[1], [x1], #8
-#    v7: 0x7271706f6e6d6c6b2726252423222120 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x7271706f6e6d6c6b2726252423222120 (1.861e+243, ...)
+#                                  ╙───────────────── 0x7271706f6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d404813		ld1 {v19.h}[5], [x0]
-#   v19: 0x3d3c3b3aff013736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3aff013736353433323130012e (..., nan, ...)
+#                              ╙───────────────────── 0xff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2482a		ld1 {v10.h}[1], [x1], x2
-#   v10: 0xff0000850002ff01d6d5d4d37473d0cf <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d37473d0cf (..., 1.822e+04, ...)
+#                                              ╙───── 0x7473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddf4025		ld1 {v5.h}[4], [x1], #2
-#    v5: 0x5c5b5a595857737254535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857737254535251504f4e4d (..., 1.525e+04, ...)
+#                                  ╙───────────────── 0x7372 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d408015		ld1 {v21.s}[2], [x0]
-#   v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.751e-40, ...)
+#                                  ╙───────────────── 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2802d		ld1 {v13.s}[2], [x1], x2
-#   v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.99878e+33, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.999e+33, ...)
+#                                  ╙───────────────── 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddf8021		ld1 {v1.s}[2], [x1], #4
-#    v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.24460e+33, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.245e+33, ...)
+#                                  ╙───────────────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40c002		ld1r {v2.16b}, [x0]
-#    v2: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x01010101010101010101010101010101
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2c022		ld1r {v2.16b}, [x1], x2
-#    v2: 0x77777777777777777777777777777777 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x77777777777777777777777777777777
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x77 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfc036		ld1r {v22.16b}, [x1], #1
-#   v22: 0x76767676767676767676767676767676 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x76767676767676767676767676767676
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x76 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40cc19		ld1r {v25.1d}, [x0]
-#   v25: 0x0000000000000000ff0000850002ff01 (d25: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2cc29		ld1r {v9.1d}, [x1], x2
-#    v9: 0x00000000000000007e7d7c7b7a797877 (d9: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7e7d7c7b7a797877 (1.975e+301)
+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfcc37		ld1r {v23.1d}, [x1], #8
-#   v23: 0x00000000000000007d7c7b7a79787776 (d23: 2.91053e+296) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x7d7c7b7a79787776 (2.911e+296)
+#                                                  ╙─ 0x7d7c7b7a79787776 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40cc13		ld1r {v19.2d}, [x0]
-#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#                                  ╙───────────────╨─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2cc35		ld1r {v21.2d}, [x1], x2
-#   v21: 0x8584838281807f7e8584838281807f7e (-4.41447e-282, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8584838281807f7e8584838281807f7e (-4.414e-282, -4.414e-282)
+#                                  ╙───────────────╨─ 0x8584838281807f7e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfcc3e		ld1r {v30.2d}, [x1], #8
-#   v30: 0x84838281807f7e7d84838281807f7e7d (-6.40629e-287, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84838281807f7e7d84838281807f7e7d (-6.406e-287, -6.406e-287)
+#                                  ╙───────────────╨─ 0x84838281807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40c818		ld1r {v24.2s}, [x0]
-#   v24: 0x00000000000000000002ff010002ff01 (s24: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#                                          ╙───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2c83a		ld1r {v26.2s}, [x1], x2
-#   v26: 0x00000000000000008887868588878685 (s26: -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x8887868588878685 (-8.157e-34, -8.157e-34)
+#                                          ╙───────╨─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfc83c		ld1r {v28.2s}, [x1], #4
-#   v28: 0x00000000000000008786858487868584 (s28: -2.02406e-34) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x8786858487868584 (-2.024e-34, -2.024e-34)
+#                                          ╙───────╨─ 0x87868584 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40c413		ld1r {v19.4h}, [x0]
-#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2c421		ld1r {v1.4h}, [x1], x2
-#    v1: 0x00000000000000008988898889888988 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8988898889888988 (-0.0001688, -0.0001688, -0.0001688, -0.0001688)
+#                                      ╙───╨───╨───╨─ 0x8988 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfc435		ld1r {v21.4h}, [x1], #2
-#   v21: 0x00000000000000008887888788878887 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x8887888788878887 (-0.0001382, -0.0001382, -0.0001382, -0.0001382)
+#                                      ╙───╨───╨───╨─ 0x8887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40c80f		ld1r {v15.4s}, [x0]
-#   v15: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#                          ╙───────╨───────╨───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2c835		ld1r {v21.4s}, [x1], x2
-#   v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (..., -2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (-2.150e-31, -2.150e-31, -2.150e-31, -2.150e-31)
+#                          ╙───────╨───────╨───────╨─ 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfc837		ld1r {v23.4s}, [x1], #4
-#   v23: 0x8b8a89888b8a89888b8a89888b8a8988 (..., -5.33626e-32, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0x8b8a89888b8a89888b8a89888b8a8988 (-5.336e-32, -5.336e-32, -5.336e-32, -5.336e-32)
+#                          ╙───────╨───────╨───────╨─ 0x8b8a8988 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40c01a		ld1r {v26.8b}, [x0]
-#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2c02e		ld1r {v14.8b}, [x1], x2
-#   v14: 0x00000000000000008c8c8c8c8c8c8c8c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x8c8c8c8c8c8c8c8c
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfc033		ld1r {v19.8b}, [x1], #1
-#   v19: 0x00000000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x8b8b8b8b8b8b8b8b
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40c40d		ld1r {v13.8h}, [x0]
-#   v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2c43e		ld1r {v30.8h}, [x1], x2
-#   v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c (-0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8d8c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfc43b		ld1r {v27.8h}, [x1], #2
-#   v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b (-0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8c8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c408015		ld2 {v21.16b, v22.16b}, [x0]
-#   v21: 0x1e1c1a18000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x1f1d1b1917000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1e1c1a18000000000000ffff00850201
+#            v22: 0x1f1d1b1917000000000000feff0000ff
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x17'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1b'1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f'1e <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc28035		ld2 {v21.16b, v22.16b}, [x1], x2
-#   v21: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0xacaaa8a6a4a2a09e9c9a98969492908e <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#            v22: 0xacaaa8a6a4a2a09e9c9a98969492908e
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x92'91 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x98'97 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa4'a3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaa'a9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xac'ab <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf802c		ld2 {v12.16b, v13.16b}, [x1], #32
-#   v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c
+#            v13: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x8f'8e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x95'94 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa1'a0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa7'a6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xa9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xab'aa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c408c0e		ld2 {v14.2d, v15.2d}, [x0]
-#   v14: 0x1700000000000000ff0000850002ff01 (6.68887e-198, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.56775e-159, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x1700000000000000ff0000850002ff01 (6.689e-198, -5.487e+303)
+#            v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.568e-159, 8.289e-317)
+#                                  ║               ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc28c20		ld2 {v0.2d, v1.2d}, [x1], x2
-#    v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.70315e+18, -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.31369e+57, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.703e+18, -1.163e-59)
+#             v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.314e+57, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4'b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcbcac9c8c7c6c5c4'c3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf8c2c		ld2 {v12.2d, v13.2d}, [x1], #32
-#   v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.90391e+13, -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.92941e+52, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.904e+13, -1.680e-64)
+#            v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.929e+52, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3'b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40881b		ld2 {v27.2s, v28.2s}, [x0]
-#   v27: 0x000000000000000000fffeff0002ff01 (..., 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00fffeff0002ff01 (2.351e-38, 2.751e-40)
+#            d28:                 0x00000000ff000085 (0.000, -1.701e+38)
+#                                          ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc28822		ld2 {v2.2s, v3.2s}, [x1], x2
-#    v2: 0x0000000000000000d6d5d4d3cecdcccb (..., -1.17555e+14, -1.72638e+09) <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000dad9d8d7d2d1d0cf (..., -3.06592e+16, -4.50576e+11) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xd6d5d4d3cecdcccb (-1.176e+14, -1.726e+09)
+#             d3:                 0xdad9d8d7d2d1d0cf (-3.066e+16, -4.506e+11)
+#                                          ║       ╙─ 0xd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xdad9d8d7'd6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf882c		ld2 {v12.2s, v13.2s}, [x1], #16
-#   v12: 0x0000000000000000d5d4d3d2cdcccbca (..., -2.92508e+13, -4.29488e+08) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0000000000000000d9d8d7d6d1d0cfce (..., -7.62949e+15, -1.12105e+11) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xd5d4d3d2cdcccbca (-2.925e+13, -4.295e+08)
+#            d13:                 0xd9d8d7d6d1d0cfce (-7.629e+15, -1.121e+11)
+#                                          ║       ╙─ 0xd1d0cfce'cdcccbca <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c408409		ld2 {v9.4h, v10.4h}, [x0]
-#    v9: 0x00000000000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x0000000000000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x0000feff0085ff01 (0.000, nan, 7.927e-06, nan)
+#            d10:                 0x000000ffff000002 (0.000, 1.520e-05, nan, 1.192e-07)
+#                                      ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc28437		ld2 {v23.4h, v24.4h}, [x1], x2
-#   v23: 0x0000000000000000e7e6e3e2dfdedbda <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000e9e8e5e4e1e0dddc <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe7e6e3e2dfdedbda (-2022., -1009., -503.5, -251.2)
+#            d24:                 0xe9e8e5e4e1e0dddc (-3024., -1508., -752.0, -375.0)
+#                                      ║   ║   ║   ╙─ 0xdddc'dbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe1e0'dfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe9e8'e7e6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf8421		ld2 {v1.4h, v2.4h}, [x1], #16
-#    v1: 0x0000000000000000e6e5e2e1dedddad9 <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x0000000000000000e8e7e4e3e0dfdcdb <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe6e5e2e1dedddad9 (-1765., -880.5, -439.2, -219.1)
+#             d2:                 0xe8e7e4e3e0dfdcdb (-2510., -1251., -623.5, -310.8)
+#                                      ║   ║   ║   ╙─ 0xdcdb'dad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe0df'dedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7'e6e5 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c408814		ld2 {v20.4s, v21.4s}, [x0]
-#   v20: 0x1b1a19180000000000fffeff0002ff01 (1.27467e-22, 0.00000, 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x1f1e1d1c1700000000000000ff000085 (3.34819e-20, 4.13590e-25, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x1b1a19180000000000fffeff0002ff01 (1.275e-22, 0.000, 2.351e-38, 2.751e-40)
+#            v21: 0x1f1e1d1c1700000000000000ff000085 (3.348e-20, 4.136e-25, 0.000, -1.701e+38)
+#                          ║       ║       ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2882a		ld2 {v10.4s, v11.4s}, [x1], x2
-#   v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.53999e-36, -1.04669e+37, -1.54621e+32, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.06322e-34, 2.35095e-38, -4.02346e+34, -5.94046e+29) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.540e-36, -1.047e+37, -1.546e+32, -2.282e+27)
+#            v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.063e-34, 2.351e-38, -4.023e+34, -5.940e+29)
+#                          ║       ║       ║       ╙─ 0xf0efeeed'ecebeae9 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf8f7f6f5'f4f3f2f1 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffefd'fcfbfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x08070605'04030201 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf8838		ld2 {v24.4s, v25.4s}, [x1], #32
-#   v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.82047e-37, -2.60629e+36, -3.84962e+31, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.00825e-34, nan, -1.00179e+34, -1.47890e+29) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.820e-37, -2.606e+36, -3.850e+31, -5.680e+26)
+#            v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.008e-34, nan, -1.002e+34, -1.479e+29)
+#                          ║       ║       ║       ╙─ 0xefeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf7f6f5f4'f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xfffefdfc'fbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504'03020100 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c408011		ld2 {v17.8b, v18.8b}, [x0]
-#   v17: 0x00000000000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x0000000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000ffff00850201
+#            d18:                 0x000000feff0000ff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2802d		ld2 {v13.8b, v14.8b}, [x1], x2
-#   v13: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x0000000000000000171513110f0d0b09 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x161412100e0c0a08
+#            d14:                 0x171513110f0d0b09
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x09'08 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x11'10 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'16 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf8027		ld2 {v7.8b, v8.8b}, [x1], #16
-#    v7: 0x00000000000000001513110f0d0b0907 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1513110f0d0b0907
+#             d8:                 0x161412100e0c0a08
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0a'09 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0e'0d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x16'15 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40841e		ld2 {v30.8h, v31.8h}, [x0]
-#   v30: 0x1d1c1918000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x1f1e1b1a17000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c1918000000000000feff0085ff01 (0.004990, 0.002487, 0.000, 0.000, 0.000, nan, 7.927e-06, nan)
+#            v31: 0x1f1e1b1a17000000000000ffff000002 (0.006950, 0.003468, 0.001709, 0.000, 0.000, 1.520e-05, nan, 1.192e-07)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1700'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc28424		ld2 {v4.8h, v5.8h}, [x1], x2
-#    v4: 0x3433302f2c2b28272423201f1c1b1817 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x363532312e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v4: 0x3433302f2c2b28272423201f1c1b1817 (0.2625, 0.1307, 0.06512, 0.03244, 0.01616, 0.008049, 0.004009, 0.001997)
+#             v5: 0x363532312e2d2a29262522211e1d1a19 (0.3879, 0.1935, 0.09650, 0.04813, 0.02400, 0.01197, 0.005970, 0.002977)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1a19'1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1e1d'1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2221'201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625'2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2a29'2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2e2d'2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3231'302f <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3635'3433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf842d		ld2 {v13.8h, v14.8h}, [x1], #32
-#   v13: 0x33322f2e2b2a272623221f1e1b1a1716 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x353431302d2c2928252421201d1c1918 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x33322f2e2b2a272623221f1e1b1a1716 (0.2249, 0.1122, 0.05597, 0.02792, 0.01393, 0.006950, 0.003468, 0.001730)
+#            v14: 0x353431302d2c2928252421201d1c1918 (0.3252, 0.1621, 0.08081, 0.04028, 0.02008, 0.01001, 0.004990, 0.002487)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928'2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d601005		ld2 {v5.b, v6.b}[12], [x0]
-#    v5: 0x363532012e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x1f1e1dff1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x363532012e2d2a29262522211e1d1a19
+#             v6: 0x1f1e1dff1b1a19181700000000000000
+#                          ╙───────────────────────── 0xff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de21c30		ld2 {v16.b, v17.b}[7], [x1], x2
-#   v16: 0x4544434241403f3e363c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x4544434241403f3e363c3b3a39383736
+#            v17: 0x00000000000000003700ffff00850201
+#                                    ╙─────────────── 0x37'36 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff083d		ld2 {v29.b, v30.b}[2], [x1], #2
-#   v29: 0x0706050403020100fffefdfcfb35f9f8 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x1d1c1918000000000000feff0036ff01 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfb35f9f8
+#            v30: 0x1d1c1918000000000000feff0036ff01
+#                                              ╙───── 0x36'35 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60840b		ld2 {v11.d, v12.d}[1], [x0]
-#   v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.487e+303, ...)
+#            v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.289e-317, ...)
+#                                  ╙───────────────── 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2843a		ld2 {v26.d, v27.d}[0], [x1], x2
-#   v26: 0x00000000000000003e3d3c3b3a393837 (d26: 6.80687e-09) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000464544434241403f (d27: 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x00000000000000003e3d3c3b3a393837 (..., 6.807e-09)
+#            v27: 0x0000000000000000464544434241403f (..., 3.370e+30)
+#                                                  ╙─ 0x464544434241403f'3e3d3c3b3a393837 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff8439		ld2 {v25.d, v26.d}[0], [x1], #16
-#   v25: 0x07060504fffefdfc3d3c3b3a39383736 (d25: 1.00298e-13) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x00000000000000004544434241403f3e (d26: 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x07060504fffefdfc3d3c3b3a39383736 (..., 1.003e-13)
+#            v26: 0x00000000000000004544434241403f3e (..., 4.899e+25)
+#                                                  ╙─ 0x4544434241403f3e'3d3c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d605812		ld2 {v18.h, v19.h}[7], [x0]
-#   v18: 0xff01000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00020000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0xff01000000000000000000feff0000ff (nan, ...)
+#            v19: 0x00020000000000008b8b8b8b8b8b8b8b (1.192e-07, ...)
+#                      ╙───────────────────────────── 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de24831		ld2 {v17.h, v18.h}[5], [x1], x2
-#   v17: 0x00000000474600003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0xff01000049480000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v17: 0x00000000474600003700ffff00850201 (..., 7.273, ...)
+#            v18: 0xff01000049480000000000feff0000ff (..., 10.56, ...)
+#                              ╙───────────────────── 0x4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff503e		ld2 {v30.h, v31.h}[2], [x1], #4
-#   v30: 0x1d1c191800000000000046450036ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x1f1e1b1a1700000000004847ff000002 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c191800000000000046450036ff01 (..., 6.270, ...)
+#            v31: 0x1f1e1b1a1700000000004847ff000002 (..., 8.555, ...)
+#                                          ╙───────── 0x4847'4645 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60901d		ld2 {v29.s, v30.s}[3], [x0]
-#   v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xff00008500000000000046450036ff01 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.751e-40, ...)
+#            v30: 0xff00008500000000000046450036ff01 (-1.701e+38, ...)
+#                          ╙───────────────────────── 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2803c		ld2 {v28.s, v29.s}[0], [x1], x2
-#   v28: 0x0000000000000000000000004c4b4a49 (s28: 5.32913e+07) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0002ff0103020100fffefdfc504f4e4d (s29: 1.39121e+10) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000000000000000004c4b4a49 (..., 5.329e+07)
+#            v29: 0x0002ff0103020100fffefdfc504f4e4d (..., 1.391e+10)
+#                                                  ╙─ 0x504f4e4d'4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff9026		ld2 {v6.s, v7.s}[1], [x1], #8
-#    v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.32570e+07, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.46117e+09, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.326e+07, ...)
+#             v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.461e+09, ...)
+#                                          ╙───────── 0x4f4e4d4c'4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60c01a		ld2r {v26.16b, v27.16b}, [x0]
-#   v26: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x01010101010101010101010101010101
+#            v27: 0xffffffffffffffffffffffffffffffff
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2c035		ld2r {v21.16b, v22.16b}, [x1], x2
-#   v21: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x51515151515151515151515151515151 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x50505050505050505050505050505050
+#            v22: 0x51515151515151515151515151515151
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x51'50 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffc025		ld2r {v5.16b, v6.16b}, [x1], #2
-#    v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f
+#             v6: 0x50505050505050505050505050505050
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x50'4f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60cc1a		ld2r {v26.1d, v27.1d}, [x0]
-#   v26: 0x0000000000000000ff0000850002ff01 (d26: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000000000000000fffeff (d27: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-5.487e+303)
+#            d27:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2cc2e		ld2r {v14.1d, v15.1d}, [x1], x2
-#   v14: 0x00000000000000005857565554535251 (d14: 3.67814e+117) <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x0000000000000000605f5e5d5c5b5a59 (d15: 1.68234e+156) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x5857565554535251 (3.678e+117)
+#            d15:                 0x605f5e5d5c5b5a59 (1.682e+156)
+#                                                  ╙─ 0x605f5e5d5c5b5a59'5857565554535251 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffcc37		ld2r {v23.1d, v24.1d}, [x1], #16
-#   v23: 0x00000000000000005756555453525150 (d23: 5.37096e+112) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00000000000000005f5e5d5c5b5a5958 (d24: 2.48489e+151) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x5756555453525150 (5.371e+112)
+#            d24:                 0x5f5e5d5c5b5a5958 (2.485e+151)
+#                                                  ╙─ 0x5f5e5d5c5b5a5958'5756555453525150 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60cc0b		ld2r {v11.2d, v12.2d}, [x0]
-#   v11: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v12: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#                                  ╙───────────────╨─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2cc3d		ld2r {v29.2d, v30.2d}, [x1], x2
-#   v29: 0x67666564636261606766656463626160 (1.24732e+190, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.76650e+228, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x67666564636261606766656463626160 (1.247e+190, 1.247e+190)
+#            v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.766e+228, 5.766e+228)
+#                                  ╙───────────────╨─ 0x6f6e6d6c6b6a6968'6766656463626160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffcc2f		ld2r {v15.2d, v16.2d}, [x1], #16
-#   v15: 0x666564636261605f666564636261605f (1.81795e+185, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.50866e+223, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x666564636261605f666564636261605f (1.818e+185, 1.818e+185)
+#            v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.509e+223, 8.509e+223)
+#                                  ╙───────────────╨─ 0x6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60c81a		ld2r {v26.2s, v27.2s}, [x0]
-#   v26: 0x00000000000000000002ff010002ff01 (s26: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000ff000085ff000085 (s27: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d27:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#                                          ╙───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2c836		ld2r {v22.2s, v23.2s}, [x1], x2
-#   v22: 0x00000000000000007271706f7271706f (s22: 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000007675747376757473 (s23: 1.24460e+33) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x7271706f7271706f (4.782e+30, 4.782e+30)
+#            d23:                 0x7675747376757473 (1.245e+33, 1.245e+33)
+#                                          ╙───────╨─ 0x76757473'7271706f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffc822		ld2r {v2.2s, v3.2s}, [x1], #8
-#    v2: 0x000000000000000071706f6e71706f6e (s2: 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x00000000000000007574737275747372 (s3: 3.09878e+32) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x71706f6e71706f6e (1.191e+30, 1.191e+30)
+#             d3:                 0x7574737275747372 (3.099e+32, 3.099e+32)
+#                                          ╙───────╨─ 0x75747372'71706f6e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60c402		ld2r {v2.4h, v3.4h}, [x0]
-#    v2: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#             d3:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                                      ╙───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2c429		ld2r {v9.4h, v10.4h}, [x1], x2
-#    v9: 0x00000000000000007776777677767776 <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000007978797879787978 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7776777677767776 (3.056e+04, 3.056e+04, 3.056e+04, 3.056e+04)
+#            d10:                 0x7978797879787978 (4.480e+04, 4.480e+04, 4.480e+04, 4.480e+04)
+#                                      ╙───╨───╨───╨─ 0x7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffc426		ld2r {v6.4h, v7.4h}, [x1], #4
-#    v6: 0x00000000000000007675767576757675 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000007877787778777877 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x7675767576757675 (2.645e+04, 2.645e+04, 2.645e+04, 2.645e+04)
+#             d7:                 0x7877787778777877 (3.658e+04, 3.658e+04, 3.658e+04, 3.658e+04)
+#                                      ╙───╨───╨───╨─ 0x7877'7675 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60c807		ld2r {v7.4s, v8.4s}, [x0]
-#    v7: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#             v8: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#                          ╙───────╨───────╨───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2c833		ld2r {v19.4s, v20.4s}, [x1], x2
-#   v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (..., 5.22300e+36, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (..., -1.17085e-38, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (5.223e+36, 5.223e+36, 5.223e+36, 5.223e+36)
+#            v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (-1.171e-38, -1.171e-38, -1.171e-38, -1.171e-38)
+#                          ╙───────╨───────╨───────╨─ 0x807f7e7d'7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffc835		ld2r {v21.4s, v22.4s}, [x1], #8
-#   v21: 0x7b7a79787b7a79787b7a79787b7a7978 (..., 1.30054e+36, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (..., 3.38275e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x7b7a79787b7a79787b7a79787b7a7978 (1.301e+36, 1.301e+36, 1.301e+36, 1.301e+36)
+#            v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (3.383e+38, 3.383e+38, 3.383e+38, 3.383e+38)
+#                          ╙───────╨───────╨───────╨─ 0x7f7e7d7c'7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60c01a		ld2r {v26.8b, v27.8b}, [x0]
-#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#            d27:                 0xffffffffffffffff
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2c034		ld2r {v20.8b, v21.8b}, [x1], x2
-#   v20: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x00000000000000008181818181818181 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x8080808080808080
+#            d21:                 0x8181818181818181
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x81'80 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffc02b		ld2r {v11.8b, v12.8b}, [x1], #2
-#   v11: 0x00000000000000007f7f7f7f7f7f7f7f <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x7f7f7f7f7f7f7f7f
+#            d12:                 0x8080808080808080
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x80'7f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60c40c		ld2r {v12.8h, v13.8h}, [x0]
-#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v13: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2c426		ld2r {v6.8h, v7.8h}, [x1], x2
-#    v6: 0x82818281828182818281828182818281 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x84838483848384838483848384838483 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x82818281828182818281828182818281 (-3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05)
+#             v7: 0x84838483848384838483848384838483 (-6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8483'8281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffc439		ld2r {v25.8h, v26.8h}, [x1], #4
-#   v25: 0x81808180818081808180818081808180 <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x83828382838283828382838283828382 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x81808180818081808180818081808180 (-2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05)
+#            v26: 0x83828382838283828382838283828382 (-5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c404014		ld3 {v20.16b, v21.16b, v22.16b}, [x0]
-#   v20: 0x2d2a2724211e1b1800000000fe000001 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x2e2b2825221f1c1900000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x2f2c292623201d1a1700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2d2a2724211e1b1800000000fe000001
+#            v21: 0x2e2b2825221f1c1900000000ffff85ff
+#            v22: 0x2f2c292623201d1a1700000000ff0002
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x20'1f'1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x23'22'21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2c'2b'2a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f'2e'2d <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2403c		ld3 {v28.16b, v29.16b, v30.16b}, [x1], x2
-#   v28: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v29: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#            v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x89'88'87 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8c'8b'8a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8f'8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x95'94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x98'97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa1'a0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa4'a3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa7'a6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xaa'a9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xad'ac'ab <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb3'b2'b1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf4034		ld3 {v20.16b, v21.16b, v22.16b}, [x1], #48
-#   v20: 0xb0adaaa7a4a19e9b9895928f8c898683 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0xb0adaaa7a4a19e9b9895928f8c898683
+#            v21: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v22: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x85'84'83 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x88'87'86 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8b'8a'89 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8e'8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x91'90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x94'93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x97'96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9a'99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa3'a2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa6'a5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa9'a8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xac'ab'aa <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb2'b1'b0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c404c15		ld3 {v21.2d, v22.2d, v23.2d}, [x0]
-#   v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.56775e-159, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x27262524232221200000000000fffeff (4.28794e-120, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x2f2e2d2c2b2a29281700000000000000 (1.98829e-81, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.568e-159, -5.487e+303)
+#            v22: 0x27262524232221200000000000fffeff (4.288e-120, 8.289e-317)
+#            v23: 0x2f2e2d2c2b2a29281700000000000000 (1.988e-81, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928'2726252423222120'1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc24c32		ld3 {v18.2d, v19.2d, v20.2d}, [x1], x2
-#   v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.07279e+90, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.47908e+129, -3.90391e+13) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.10851e+168, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.073e+90, -8.311e-26)
+#            v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.479e+129, -3.904e+13)
+#            v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.109e+168, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb'dad9d8d7d6d5d4d3'd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf4c3b		ld3 {v27.2d, v28.2d, v29.2d}, [x1], #48
-#   v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.30639e+86, -1.21867e-30) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.56908e+124, -5.62003e+08) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.03668e+163, -2.82942e+47) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.306e+86, -1.219e-30)
+#            v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.569e+124, -5.620e+08)
+#            v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.037e+163, -2.829e+47)
+#                                  ║               ╙─ 0xc9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe1e0dfdedddcdbda'd9d8d7d6d5d4d3d2'd1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c404807		ld3 {v7.2s, v8.2s, v9.2s}, [x0]
-#    v7: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x00000000000000001700000000fffeff (..., 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x000000000002ff01 (0.000, 2.751e-40)
+#             d8:                 0x00000000ff000085 (0.000, -1.701e+38)
+#             d9:                 0x1700000000fffeff (4.136e-25, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc24834		ld3 {v20.2s, v21.2s, v22.2s}, [x1], x2
-#   v20: 0x0000000000000000f1f0efeee5e4e3e2 (..., -2.38613e+30, -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x0000000000000000f5f4f3f2e9e8e7e6 (..., -6.21029e+32, -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x0000000000000000f9f8f7f6edecebea (..., -1.61590e+35, -9.16546e+27) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xf1f0efeee5e4e3e2 (-2.386e+30, -1.351e+23)
+#            d21:                 0xf5f4f3f2e9e8e7e6 (-6.210e+32, -3.520e+25)
+#            d22:                 0xf9f8f7f6edecebea (-1.616e+35, -9.165e+27)
+#                                          ║       ╙─ 0xedecebea'e9e8e7e6'e5e4e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf483a		ld3 {v26.2s, v27.2s, v28.2s}, [x1], #24
-#   v26: 0x0000000000000000f0efeeede4e3e2e1 (..., -5.94046e+29, -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000f4f3f2f1e8e7e6e5 (..., -1.54621e+32, -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x0000000000000000f8f7f6f5ecebeae9 (..., -4.02346e+34, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xf0efeeede4e3e2e1 (-5.940e+29, -3.363e+22)
+#            d27:                 0xf4f3f2f1e8e7e6e5 (-1.546e+32, -8.761e+24)
+#            d28:                 0xf8f7f6f5ecebeae9 (-4.023e+34, -2.282e+27)
+#                                          ║       ╙─ 0xecebeae9'e8e7e6e5'e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40441b		ld3 {v27.4h, v28.4h, v29.4h}, [x0]
-#   v27: 0x000000000000000000000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x000000000000000000000000feff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000001700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00000000ff00ff01 (0.000, 0.000, nan, nan)
+#            d28:                 0x00000000feff0002 (0.000, 0.000, nan, 1.192e-07)
+#            d29:                 0x1700000000ff0085 (0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                                      ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2443c		ld3 {v28.4h, v29.4h, v30.4h}, [x1], x2
-#   v28: 0x00000000000000000c0b060500fffaf9 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000000e0d08070201fcfb <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000100f0a090403fefd <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x0c0b060500fffaf9 (0.0002468, 9.185e-05, 1.520e-05, -5.712e+04)
+#            d29:                 0x0e0d08070201fcfb (0.0003693, 0.0001229, 3.058e-05, nan)
+#            d30:                 0x100f0a090403fefd (0.0004954, 0.0001842, 6.121e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0403'0201'00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0a09'0807'0605 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x100f'0e0d'0c0b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf4427		ld3 {v7.4h, v8.4h, v9.4h}, [x1], #24
-#    v7: 0x00000000000000000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000d0c07060100fbfa <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x00000000000000000f0e09080302fdfc <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x0b0a0504fffef9f8 (0.0002148, 7.653e-05, nan, -4.890e+04)
+#             d8:                 0x0d0c07060100fbfa (0.0003080, 0.0001072, 1.526e-05, -6.534e+04)
+#             d9:                 0x0f0e09080302fdfc (0.0004306, 0.0001535, 4.590e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfdfc'fbfa'f9f8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0302'0100'fffe <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0908'0706'0504 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0f0e'0d0c'0b0a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c404802		ld3 {v2.4s, v3.4s, v4.4s}, [x0]
-#    v2: 0x272625241b1a1918000000000002ff01 (2.30573e-15, 1.27467e-22, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.04532e-13, 3.34819e-20, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x2f2e2d2c232221201700000000fffeff (1.58413e-10, 8.78905e-18, 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x272625241b1a1918000000000002ff01 (2.306e-15, 1.275e-22, 0.000, 2.751e-40)
+#             v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.045e-13, 3.348e-20, 0.000, -1.701e+38)
+#             v4: 0x2f2e2d2c232221201700000000fffeff (1.584e-10, 8.789e-18, 4.136e-25, 2.351e-38)
+#                          ║       ║       ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120'1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c'2b2a2928'27262524 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc24838		ld3 {v24.4s, v25.4s, v26.4s}, [x1], x2
-#   v24: 0x373635342b2a29281f1e1d1c13121110 (1.08604e-05, 6.04532e-13, 3.34819e-20, 1.84362e-27) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x3b3a39382f2e2d2c2322212017161514 (0.00284155, 1.58413e-10, 8.78905e-18, 4.84942e-25) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x3f3e3d3c33323130272625241b1a1918 (0.743122, 4.14886e-08, 2.30573e-15, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x373635342b2a29281f1e1d1c13121110 (1.086e-05, 6.045e-13, 3.348e-20, 1.844e-27)
+#            v25: 0x3b3a39382f2e2d2c2322212017161514 (0.002842, 1.584e-10, 8.789e-18, 4.849e-25)
+#            v26: 0x3f3e3d3c33323130272625241b1a1918 (0.7431, 4.149e-08, 2.306e-15, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918'17161514'13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x33323130'2f2e2d2c'2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf482b		ld3 {v11.4s, v12.4s, v13.4s}, [x1], #48
-#   v11: 0x363534332a2928271e1d1c1b1211100f (2.70015e-06, 1.50241e-13, 8.31732e-21, 4.57737e-28) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x3a3938372e2d2c2b2221201f16151413 (0.000706557, 3.93749e-11, 2.18366e-18, 1.20425e-25) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x3e3d3c3b3231302f262524231a191817 (0.184800, 1.03137e-08, 5.72948e-16, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0x363534332a2928271e1d1c1b1211100f (2.700e-06, 1.502e-13, 8.317e-21, 4.577e-28)
+#            v12: 0x3a3938372e2d2c2b2221201f16151413 (0.0007066, 3.937e-11, 2.184e-18, 1.204e-25)
+#            v13: 0x3e3d3c3b3231302f262524231a191817 (0.1848, 1.031e-08, 5.729e-16, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817'16151413'1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x26252423'2221201f'1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3231302f'2e2d2c2b'2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3e3d3c3b'3a393837'36353433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40401d		ld3 {v29.8b, v30.8b, v31.8b}, [x0]
-#   v29: 0x000000000000000000000000fe000001 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x000000000000000000000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000000000001700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x00000000fe000001
+#            d30:                 0x00000000ffff85ff
+#            d31:                 0x1700000000ff0002
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc24021		ld3 {v1.8b, v2.8b, v3.8b}, [x1], x2
-#    v1: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x00000000000000005653504d4a474441 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x54514e4b4845423f
+#             d2:                 0x55524f4c49464340
+#             d3:                 0x5653504d4a474441
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x41'40'3f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x44'43'42 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x47'46'45 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x4a'49'48 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4d'4c'4b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x50'4f'4e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x53'52'51 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x56'55'54 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf402c		ld3 {v12.8b, v13.8b, v14.8b}, [x1], #24
-#   v12: 0x000000000000000053504d4a4744413e <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x53504d4a4744413e
+#            d13:                 0x54514e4b4845423f
+#            d14:                 0x55524f4c49464340
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40'3f'3e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x43'42'41 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x46'45'44 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x49'48'47 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4c'4b'4a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x4f'4e'4d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x52'51'50 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x55'54'53 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c404416		ld3 {v22.8h, v23.8h, v24.8h}, [x0]
-#   v22: 0x2b2a25241f1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x2d2c272621201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x2b2a25241f1e191800000000ff00ff01 (0.05597, 0.02008, 0.006950, 0.002487, 0.000, 0.000, nan, nan)
+#            v23: 0x2d2c272621201b1a00000000feff0002 (0.08081, 0.02792, 0.01001, 0.003468, 0.000, 0.000, nan, 1.192e-07)
+#            v24: 0x2f2e292823221d1c1700000000ff0085 (0.1122, 0.04028, 0.01393, 0.004990, 0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2322'2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2928'2726'2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2442d		ld3 {v13.8h, v14.8h, v15.8h}, [x1], x2
-#   v13: 0x81807b7a75746f6e696863625d5c5756 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x83827d7c777671706b6a65645f5e5958 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x85847f7e797873726d6c676661605b5a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e696863625d5c5756 (-2.289e-05, 6.125e+04, 2.234e+04, 7608., 2768., 945.0, 343.0, 117.4)
+#            v14: 0x83827d7c777671706b6a65645f5e5958 (-5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5, 171.0)
+#            v15: 0x85847f7e797873726d6c676661605b5a (-8.416e-05, nan, 4.480e+04, 1.525e+04, 5552., 1894., 688.0, 235.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5b5a'5958'5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6160'5f5e'5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6766'6564'6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6d6c'6b6a'6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7372'7170'6f6e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7978'7776'7574 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8584'8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf443c		ld3 {v28.8h, v29.8h, v30.8h}, [x1], #48
-#   v28: 0x807f7a7974736e6d686762615c5b5655 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x82817c7b7675706f6a6964635e5d5857 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x84837e7d787772716c6b6665605f5a59 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x807f7a7974736e6d686762615c5b5655 (-7.570e-06, 5.302e+04, 1.822e+04, 6580., 2254., 816.5, 278.8, 101.3)
+#            v29: 0x82817c7b7675706f6a6964635e5d5857 (-3.821e-05, nan, 2.645e+04, 9080., 3282., 1123., 407.2, 138.9)
+#            v30: 0x84837e7d787772716c6b6665605f5a59 (-6.884e-05, nan, 3.658e+04, 1.319e+04, 4524., 1637., 559.5, 203.1)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5a59'5857'5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f'5e5d'5c5b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6665'6463'6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6c6b'6a69'6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7271'706f'6e6d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7877'7675'7473 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7e7d'7c7b'7a79 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8483'8281'807f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d402c15		ld3 {v21.b, v22.b, v23.b}[11], [x0]
-#   v21: 0x0000000001000000f5f4f3f2e9e8e7e6 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x2b2a2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x2d2c272602201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x0000000001000000f5f4f3f2e9e8e7e6
+#            v22: 0x2b2a2524ff1e191800000000ff00ff01
+#            v23: 0x2d2c272602201b1a00000000feff0002
+#                            ╙─────────────────────── 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc22425		ld3 {v5.b, v6.b, v7.b}[9], [x1], x2
-#    v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x82818281828186818281828182818281 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000087000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f
+#             v6: 0x82818281828186818281828182818281
+#             v7: 0x00000000000087000b0a0504fffef9f8
+#                                ╙─────────────────── 0x87'86'85 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddf2037		ld3 {v23.b, v24.b, v25.b}[0], [x1], #3
-#   v23: 0x2d2c272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x3b3a39382f2e2d2c2322212017161586 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0x2d2c272602201b1a00000000feff0084
+#            v24: 0x2f2e292823221d1c1700000000ff0085
+#            v25: 0x3b3a39382f2e2d2c2322212017161586
+#                                                  ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40a410		ld3 {v16.d, v17.d, v18.d}[0], [x0]
-#   v16: 0x6e6d6c6b6a696867ff0000850002ff01 (d16: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000474600000000000000fffeff (d17: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0xd2d1d0cfcecdcccb1700000000000000 (d18: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6e6d6c6b6a696867ff0000850002ff01 (..., -5.487e+303)
+#            v17: 0x00000000474600000000000000fffeff (..., 8.289e-317)
+#            v18: 0xd2d1d0cfcecdcccb1700000000000000 (..., 6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2a43e		ld3 {v30.d, v31.d, v0.d}[0], [x1], x2
-#   v30: 0x84837e7d787772718e8d8c8b8a898887 (d30: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x0000000000000000969594939291908f (d31: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (d0: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84837e7d787772718e8d8c8b8a898887 (..., -1.418e-238)
+#            v31: 0x0000000000000000969594939291908f (..., -7.048e-200)
+#             v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (..., -3.291e-161)
+#                                                  ╙─ 0x9e9d9c9b9a999897'969594939291908f'8e8d8c8b8a898887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfa43c		ld3 {v28.d, v29.d, v30.d}[1], [x1], #24
-#   v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.09028e-243, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x9594939291908f8e6a6964635e5d5857 (-1.02545e-204, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.85140e-166, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.090e-243, ...)
+#            v29: 0x9594939291908f8e6a6964635e5d5857 (-1.025e-204, ...)
+#            v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.851e-166, ...)
+#                                  ╙───────────────── 0x9d9c9b9a99989796'9594939291908f8e'8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40700d		ld3 {v13.h, v14.h, v15.h}[2], [x0]
-#   v13: 0x81807b7a75746f6e6968ff015d5c5756 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x83827d7c777671706b6a00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x85847f7e797873726d6c008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e6968ff015d5c5756 (..., nan, ...)
+#            v14: 0x83827d7c777671706b6a00025f5e5958 (..., 1.192e-07, ...)
+#            v15: 0x85847f7e797873726d6c008561605b5a (..., 7.927e-06, ...)
+#                                          ╙───────── 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc27836		ld3 {v22.h, v23.h, v24.h}[7], [x1], x2
-#   v22: 0x9f9e2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0xa1a0272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0xa3a2292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x9f9e2524ff1e191800000000ff00ff01 (-0.007439, ...)
+#            v23: 0xa1a0272602201b1a00000000feff0084 (-0.01099, ...)
+#            v24: 0xa3a2292823221d1c1700000000ff0085 (-0.01491, ...)
+#                      ╙───────────────────────────── 0xa3a2'a1a0'9f9e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddf782e		ld3 {v14.h, v15.h, v16.h}[3], [x1], #6
-#   v14: 0x83827d7c777671709e9d00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x85847f7e79787372a09f008561605b5a <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x6e6d6c6b6a696867a2a100850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0x83827d7c777671709e9d00025f5e5958 (..., -0.006458, ...)
+#            v15: 0x85847f7e79787372a09f008561605b5a (..., -0.009026, ...)
+#            v16: 0x6e6d6c6b6a696867a2a100850002ff01 (..., -0.01295, ...)
+#                                      ╙───────────── 0xa2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40b016		ld3 {v22.s, v23.s, v24.s}[3], [x0]
-#   v22: 0x0002ff01ff1e191800000000ff00ff01 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0xff00008502201b1a00000000feff0084 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00fffeff23221d1c1700000000ff0085 (2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x0002ff01ff1e191800000000ff00ff01 (2.751e-40, ...)
+#            v23: 0xff00008502201b1a00000000feff0084 (-1.701e+38, ...)
+#            v24: 0x00fffeff23221d1c1700000000ff0085 (2.351e-38, ...)
+#                          ╙───────────────────────── 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2a03e		ld3 {v30.s, v31.s, v0.s}[2], [x1], x2
-#   v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.14938e-15, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000aaa9a8a7969594939291908f (..., -3.01375e-13, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.89780e-11, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.149e-15, ...)
+#            v31: 0x00000000aaa9a8a7969594939291908f (..., -3.014e-13, ...)
+#             v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.898e-11, ...)
+#                                  ╙───────────────── 0xaeadacab'aaa9a8a7'a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfb02c		ld3 {v12.s, v13.s, v14.s}[1], [x1], #12
-#   v12: 0x0000000000000000a5a4a3a24744413e (..., -2.85603e-16, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.48978e-14, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.96304e-11, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000a5a4a3a24744413e (..., -2.856e-16, ...)
+#            v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.490e-14, ...)
+#            v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.963e-11, ...)
+#                                          ╙───────── 0xadacabaa'a9a8a7a6'a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40e018		ld3r {v24.16b, v25.16b, v26.16b}, [x0]
-#   v24: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x01010101010101010101010101010101
+#            v25: 0xffffffffffffffffffffffffffffffff
+#            v26: 0x02020202020202020202020202020202
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2e038		ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
-#   v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#            v25: 0xafafafafafafafafafafafafafafafaf
+#            v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfe023		ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
-#    v3: 0xadadadadadadadadadadadadadadadad <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v3: 0xadadadadadadadadadadadadadadadad
+#             v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#             v5: 0xafafafafafafafafafafafafafafafaf
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40ec04		ld3r {v4.1d, v5.1d, v6.1d}, [x0]
-#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01 (-5.487e+303)
+#             d5:                 0x0000000000fffeff (8.289e-317)
+#             d6:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2ec27		ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
-#    v7: 0x0000000000000000b7b6b5b4b3b2b1b0 (d7: -2.60696e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000bfbebdbcbbbab9b8 (d8: -0.120083) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x0000000000000000c7c6c5c4c3c2c1c0 (d9: -6.05398e+37) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xb7b6b5b4b3b2b1b0 (-2.607e-40)
+#             d8:                 0xbfbebdbcbbbab9b8 (-0.1201)
+#             d9:                 0xc7c6c5c4c3c2c1c0 (-6.054e+37)
+#                                                  ╙─ 0xc7c6c5c4c3c2c1c0'bfbebdbcbbbab9b8'b7b6b5b4b3b2b1b0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfec31		ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
-#   v17: 0x0000000000000000b6b5b4b3b2b1b0af (d17: -3.80205e-45) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x0000000000000000bebdbcbbbab9b8b7 (d18: -1.77248e-06) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x0000000000000000c6c5c4c3c2c1c0bf (d19: -8.83040e+32) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xb6b5b4b3b2b1b0af (-3.802e-45)
+#            d18:                 0xbebdbcbbbab9b8b7 (-1.772e-06)
+#            d19:                 0xc6c5c4c3c2c1c0bf (-8.830e+32)
+#                                                  ╙─ 0xc6c5c4c3c2c1c0bf'bebdbcbbbab9b8b7'b6b5b4b3b2b1b0af <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40ec10		ld3r {v16.2d, v17.2d, v18.2d}, [x0]
-#   v16: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v17: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v18: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#                                  ╙───────────────╨─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2ec34		ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
-#   v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.11344e+71, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.05087e+110, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.54613e+148, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.113e+71, -4.113e+71)
+#            v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.051e+110, -2.051e+110)
+#            v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.546e+148, -9.546e+148)
+#                                  ╙───────────────╨─ 0xdedddcdbdad9d8d7'd6d5d4d3d2d1d0cf'cecdcccbcac9c8c7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfec2e		ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
-#   v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.06516e+66, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.98548e+105, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.40766e+144, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.065e+66, -6.065e+66)
+#            v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.985e+105, -2.985e+105)
+#            v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.408e+144, -1.408e+144)
+#                                  ╙───────────────╨─ 0xdddcdbdad9d8d7d6'd5d4d3d2d1d0cfce'cdcccbcac9c8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40e80a		ld3r {v10.2s, v11.2s, v12.2s}, [x0]
-#   v10: 0x00000000000000000002ff010002ff01 (s10: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x0000000000000000ff000085ff000085 (s11: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x000000000000000000fffeff00fffeff (s12: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d11:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#            d12:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#                                          ╙───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2e820		ld3r {v0.2s, v1.2s, v2.2s}, [x1], x2
-#    v0: 0x0000000000000000e1e0dfdee1e0dfde (s0: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x0000000000000000e5e4e3e2e5e4e3e2 (s1: -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x0000000000000000e9e8e7e6e9e8e7e6 (s2: -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#             d1:                 0xe5e4e3e2e5e4e3e2 (-1.351e+23, -1.351e+23)
+#             d2:                 0xe9e8e7e6e9e8e7e6 (-3.520e+25, -3.520e+25)
+#                                          ╙───────╨─ 0xe9e8e7e6'e5e4e3e2'e1e0dfde <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfe837		ld3r {v23.2s, v24.2s, v25.2s}, [x1], #12
-#   v23: 0x0000000000000000e0dfdedde0dfdedd (s23: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000e4e3e2e1e4e3e2e1 (s24: -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x0000000000000000e8e7e6e5e8e7e6e5 (s25: -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#            d24:                 0xe4e3e2e1e4e3e2e1 (-3.363e+22, -3.363e+22)
+#            d25:                 0xe8e7e6e5e8e7e6e5 (-8.761e+24, -8.761e+24)
+#                                          ╙───────╨─ 0xe8e7e6e5'e4e3e2e1'e0dfdedd <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40e416		ld3r {v22.4h, v23.4h, v24.4h}, [x0]
-#   v22: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d23:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d24:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                                      ╙───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2e426		ld3r {v6.4h, v7.4h, v8.4h}, [x1], x2
-#    v6: 0x0000000000000000eae9eae9eae9eae9 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x0000000000000000ecebecebecebeceb <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000eeedeeedeeedeeed <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d6:                 0xeae9eae9eae9eae9 (-3538., -3538., -3538., -3538.)
+#             d7:                 0xecebecebecebeceb (-5036., -5036., -5036., -5036.)
+#             d8:                 0xeeedeeedeeedeeed (-7092., -7092., -7092., -7092.)
+#                                      ╙───╨───╨───╨─ 0xeeed'eceb'eae9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfe427		ld3r {v7.4h, v8.4h, v9.4h}, [x1], #6
-#    v7: 0x0000000000000000e9e8e9e8e9e8e9e8 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000ebeaebeaebeaebea <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x0000000000000000edecedecedecedec <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xe9e8e9e8e9e8e9e8 (-3024., -3024., -3024., -3024.)
+#             d8:                 0xebeaebeaebeaebea (-4052., -4052., -4052., -4052.)
+#             d9:                 0xedecedecedecedec (-6064., -6064., -6064., -6064.)
+#                                      ╙───╨───╨───╨─ 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40e81a		ld3r {v26.4s, v27.4s, v28.4s}, [x0]
-#   v26: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v27: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v28: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#                          ╙───────╨───────╨───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2e820		ld3r {v0.4s, v1.4s, v2.4s}, [x1], x2
-#    v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (..., -2.38613e+30, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (..., -6.21029e+32, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (..., -1.61590e+35, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (-2.386e+30, -2.386e+30, -2.386e+30, -2.386e+30)
+#             v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (-6.210e+32, -6.210e+32, -6.210e+32, -6.210e+32)
+#             v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (-1.616e+35, -1.616e+35, -1.616e+35, -1.616e+35)
+#                          ╙───────╨───────╨───────╨─ 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfe83e		ld3r {v30.4s, v31.4s, v0.4s}, [x1], #12
-#   v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (..., -5.94046e+29, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (..., -1.54621e+32, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (..., -4.02346e+34, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (-5.940e+29, -5.940e+29, -5.940e+29, -5.940e+29)
+#            v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (-1.546e+32, -1.546e+32, -1.546e+32, -1.546e+32)
+#             v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (-4.023e+34, -4.023e+34, -4.023e+34, -4.023e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40e002		ld3r {v2.8b, v3.8b, v4.8b}, [x0]
-#    v2: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x0101010101010101
+#             d3:                 0xffffffffffffffff
+#             d4:                 0x0202020202020202
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2e02a		ld3r {v10.8b, v11.8b, v12.8b}, [x1], x2
-#   v10: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000000000fbfbfbfbfbfbfbfb <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xf9f9f9f9f9f9f9f9
+#            d11:                 0xfafafafafafafafa
+#            d12:                 0xfbfbfbfbfbfbfbfb
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfb'fa'f9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfe03c		ld3r {v28.8b, v29.8b, v30.8b}, [x1], #3
-#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40e406		ld3r {v6.8h, v7.8h, v8.8h}, [x0]
-#    v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v7: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#             v8: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2e43d		ld3r {v29.8h, v30.8h, v31.8h}, [x1], x2
-#   v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfe427		ld3r {v7.8h, v8.8h, v9.8h}, [x1], #6
-#    v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#             v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v9: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xfffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c400003		ld4 {v3.16b, v4.16b, v5.16b, v6.16b}, [x0]
-#    v3: 0x3c3834302c2824201c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x3d3935312d2925211d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x3e3a36322e2a26221e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x3f3b37332f2b27231f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x3c3834302c2824201c18000000ff8501
+#             v4: 0x3d3935312d2925211d19000000fe00ff
+#             v5: 0x3e3a36322e2a26221e1a000000ff0002
+#             v6: 0x3f3b37332f2b27231f1b17000000ff00
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc20022		ld4 {v2.16b, v3.16b, v4.16b, v5.16b}, [x1], x2
-#    v2: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x3f3b37332f2b27231f1b17130f0b0703 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x3c3834302c2824201c1814100c080400
+#             v3: 0x3d3935312d2925211d1915110d090501
+#             v4: 0x3e3a36322e2a26221e1a16120e0a0602
+#             v5: 0x3f3b37332f2b27231f1b17130f0b0703
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x03'02'01'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x07'06'05'04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0b'0a'09'08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0f'0e'0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x13'12'11'10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'16'15'14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf0025		ld4 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
-#    v5: 0x3b37332f2b27231f1b17130f0b0703ff <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3b37332f2b27231f1b17130f0b0703ff
+#             v6: 0x3c3834302c2824201c1814100c080400
+#             v7: 0x3d3935312d2925211d1915110d090501
+#             v8: 0x3e3a36322e2a26221e1a16120e0a0602
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1e'1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22'21'20'1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x26'25'24'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a'29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2e'2d'2c'2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x32'31'30'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x36'35'34'33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3a'39'38'37 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3e'3d'3c'3b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c400c12		ld4 {v18.2d, v19.2d, v20.2d, v21.2d}, [x0]
-#   v18: 0x2726252423222120ff0000850002ff01 (4.28794e-120, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.98829e-81, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x37363534333231301700000000000000 (9.95833e-43, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.000461414, 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2726252423222120ff0000850002ff01 (4.288e-120, -5.487e+303)
+#            v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.988e-81, 8.289e-317)
+#            v20: 0x37363534333231301700000000000000 (9.958e-43, 6.689e-198)
+#            v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.0004614, 8.568e-159)
+#                                  ║               ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938'3736353433323130'2f2e2d2c2b2a2928'2726252423222120 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc20c24		ld4 {v4.2d, v5.2d, v6.2d, v7.2d}, [x1], x2
-#    v4: 0x666564636261605f464544434241403f (1.81795e+185, 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.50866e+223, 1.57975e+69) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x767574737271706f565554535251504f (4.22243e+262, 7.82703e+107) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.97467e+301, 3.66628e+146) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v4: 0x666564636261605f464544434241403f (1.818e+185, 3.370e+30)
+#             v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.509e+223, 1.580e+69)
+#             v6: 0x767574737271706f565554535251504f (4.222e+262, 7.827e+107)
+#             v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.975e+301, 3.666e+146)
+#                                  ║               ╙─ 0x5e5d5c5b5a595857'565554535251504f'4e4d4c4b4a494847'464544434241403f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7e7d7c7b7a797877'767574737271706f'6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf0c3d		ld4 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1], #64
-#   v29: 0x6564636261605f5e4544434241403f3e (2.64379e+180, 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.25402e+219, 2.32790e+64) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x7574737271706f6e5554535251504f4e (6.14144e+257, 1.13810e+103) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.91053e+296, 5.40301e+141) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x6564636261605f5e4544434241403f3e (2.644e+180, 4.899e+25)
+#            v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.254e+219, 2.328e+64)
+#            v31: 0x7574737271706f6e5554535251504f4e (6.141e+257, 1.138e+103)
+#             v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.911e+296, 5.403e+141)
+#                                  ║               ╙─ 0x5d5c5b5a59585756'5554535251504f4e'4d4c4b4a49484746'4544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7d7c7b7a79787776'7574737271706f6e'6d6c6b6a69686766'6564636261605f5e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40081b		ld4 {v27.2s, v28.2s, v29.2s, v30.2s}, [x0]
-#   v27: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x000000000000000017000000ff000085 (..., 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000001b1a191800fffeff (..., 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000001f1e1d1c00000000 (..., 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x000000000002ff01 (0.000, 2.751e-40)
+#            d28:                 0x17000000ff000085 (4.136e-25, -1.701e+38)
+#            d29:                 0x1b1a191800fffeff (1.275e-22, 2.351e-38)
+#            d30:                 0x1f1e1d1c00000000 (3.348e-20, 0.000)
+#                                          ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc20838		ld4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
-#   v24: 0x000000000000000091908f8e81807f7e (..., -2.28077e-28, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000009594939285848382 (..., -6.00095e-26, -1.24615e-35) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x00000000000000009998979689888786 (..., -1.57777e-23, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000009d9c9b9a8d8c8b8a (..., -4.14537e-21, -8.66176e-31) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x91908f8e81807f7e (-2.281e-28, -4.720e-38)
+#            d25:                 0x9594939285848382 (-6.001e-26, -1.246e-35)
+#            d26:                 0x9998979689888786 (-1.578e-23, -3.287e-33)
+#            d27:                 0x9d9c9b9a8d8c8b8a (-4.145e-21, -8.662e-31)
+#                                          ║       ╙─ 0x8d8c8b8a'89888786'85848382'81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9d9c9b9a'99989796'95949392'91908f8e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf0824		ld4 {v4.2s, v5.2s, v6.2s, v7.2s}, [x1], #32
-#    v4: 0x0000000000000000908f8e8d807f7e7d (..., -5.66232e-29, -1.17085e-38) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000009493929184838281 (..., -1.49010e-26, -3.09178e-36) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000009897969588878685 (..., -3.91846e-24, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000009c9b9a998c8b8a89 (..., -1.02970e-21, -2.14997e-31) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x908f8e8d807f7e7d (-5.662e-29, -1.171e-38)
+#             d5:                 0x9493929184838281 (-1.490e-26, -3.092e-36)
+#             d6:                 0x9897969588878685 (-3.918e-24, -8.157e-34)
+#             d7:                 0x9c9b9a998c8b8a89 (-1.030e-21, -2.150e-31)
+#                                          ║       ╙─ 0x8c8b8a89'88878685'84838281'807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99'98979695'94939291'908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c400410		ld4 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
-#   v16: 0x000000000000000019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000001b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000001d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000001f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0x19180000feffff01 (0.002487, 0.000, nan, nan)
+#            d17:                 0x1b1a000000ff0002 (0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            d18:                 0x1d1c000000000085 (0.004990, 0.000, 0.000, 7.927e-06)
+#            d19:                 0x1f1e17000000ff00 (0.006950, 0.001709, 0.000, nan)
+#                                      ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc20437		ld4 {v23.4h, v24.4h, v25.4h, v26.4h}, [x1], x2
-#   v23: 0x0000000000000000b6b5aeada6a59e9d <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000b8b7b0afa8a7a09f <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x0000000000000000bab9b2b1aaa9a2a1 <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x0000000000000000bcbbb4b3acaba4a3 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xb6b5aeada6a59e9d (-0.4192, -0.1043, -0.02596, -0.006458)
+#            d24:                 0xb8b7b0afa8a7a09f (-0.5894, -0.1464, -0.03635, -0.009026)
+#            d25:                 0xbab9b2b1aaa9a2a1 (-0.8403, -0.2091, -0.05203, -0.01295)
+#            d26:                 0xbcbbb4b3acaba4a3 (-1.183, -0.2937, -0.07294, -0.01811)
+#                                      ║   ║   ║   ╙─ 0xa4a3'a2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xacab'aaa9'a8a7'a6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb4b3'b2b1'b0af'aead <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbcbb'bab9'b8b7'b6b5 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf0422		ld4 {v2.4h, v3.4h, v4.4h, v5.4h}, [x1], #32
-#    v2: 0x0000000000000000b5b4adaca5a49d9c <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000b7b6afaea7a69f9e <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000b9b8b1b0a9a8a1a0 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0000000000000000bbbab3b2abaaa3a2 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xb5b4adaca5a49d9c (-0.3564, -0.08862, -0.02203, -0.005478)
+#             d3:                 0xb7b6afaea7a69f9e (-0.4819, -0.1200, -0.02988, -0.007439)
+#             d4:                 0xb9b8b1b0a9a8a1a0 (-0.7148, -0.1777, -0.04419, -0.01099)
+#             d5:                 0xbbbab3b2abaaa3a2 (-0.9658, -0.2405, -0.05988, -0.01491)
+#                                      ║   ║   ║   ╙─ 0xa3a2'a1a0'9f9e'9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xabaa'a9a8'a7a6'a5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb3b2'b1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba'b9b8'b7b6'b5b4 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c400807		ld4 {v7.4s, v8.4s, v9.4s, v10.4s}, [x0]
-#    v7: 0x3332313023222120000000000002ff01 (4.14886e-08, 8.78905e-18, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x373635342726252417000000ff000085 (1.08604e-05, 2.30573e-15, 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x3b3a39382b2a29281b1a191800fffeff (0.00284155, 6.04532e-13, 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.743122, 1.58413e-10, 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x3332313023222120000000000002ff01 (4.149e-08, 8.789e-18, 0.000, 2.751e-40)
+#             v8: 0x373635342726252417000000ff000085 (1.086e-05, 2.306e-15, 4.136e-25, -1.701e+38)
+#             v9: 0x3b3a39382b2a29281b1a191800fffeff (0.002842, 6.045e-13, 1.275e-22, 2.351e-38)
+#            v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.7431, 1.584e-10, 3.348e-20, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2f2e2d2c'2b2a2928'27262524'23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534'33323130 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2083c		ld4 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
-#   v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.47890e+29, -3.21185e+19, -6.93919e+09, -1.49017) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.84962e+31, -8.37048e+21, -1.81093e+12, -389.514) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.00179e+34, -2.18077e+24, -4.72428e+14, -101772.) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.60629e+36, -5.67986e+26, -1.23202e+17, -2.65799e+07) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#            v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.850e+31, -8.370e+21, -1.811e+12, -389.5)
+#            v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.002e+34, -2.181e+24, -4.724e+14, -1.018e+05)
+#            v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.606e+36, -5.680e+26, -1.232e+17, -2.658e+07)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf083d		ld4 {v29.4s, v30.4s, v31.4s, v0.4s}, [x1], #64
-#   v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.68172e+28, -7.99345e+18, -1.72638e+09, -0.370581) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.58428e+30, -2.08336e+21, -4.50576e+11, -96.8765) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.49430e+33, -5.42822e+23, -1.17555e+14, -25314.4) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.48966e+35, -1.41390e+26, -3.06592e+16, -6.61207e+06) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.682e+28, -7.993e+18, -1.726e+09, -0.3706)
+#            v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.584e+30, -2.083e+21, -4.506e+11, -96.88)
+#            v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.494e+33, -5.428e+23, -1.176e+14, -2.531e+04)
+#             v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.490e+35, -1.414e+26, -3.066e+16, -6.612e+06)
+#                          ║       ║       ║       ╙─ 0xcac9c8c7'c6c5c4c3'c2c1c0bf'bebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdad9d8d7'd6d5d4d3'd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xeae9e8e7'e6e5e4e3'e2e1e0df'dedddcdb <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfaf9f8f7'f6f5f4f3'f2f1f0ef'eeedeceb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40000f		ld4 {v15.8b, v16.8b, v17.8b, v18.8b}, [x0]
-#   v15: 0x00000000000000001c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x00000000000000001d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000001e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000001f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#            d15:                 0x1c18000000ff8501
+#            d16:                 0x1d19000000fe00ff
+#            d17:                 0x1e1a000000ff0002
+#            d18:                 0x1f1b17000000ff00
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2003b		ld4 {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
-#   v27: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000001a16120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x17130f0b0703fffb
+#            d28:                 0x1814100c080400fc
+#            d29:                 0x1915110d090501fd
+#            d30:                 0x1a16120e0a0602fe
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfe'fd'fc'fb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf0025		ld4 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], #32
-#    v5: 0x000000000000000016120e0a0602fefa <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x16120e0a0602fefa
+#             d6:                 0x17130f0b0703fffb
+#             d7:                 0x1814100c080400fc
+#             d8:                 0x1915110d090501fd
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfd'fc'fb'fa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x01'00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x05'04'03'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x09'08'07'06 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0d'0c'0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x11'10'0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14'13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x19'18'17'16 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c400419		ld4 {v25.8h, v26.8h, v27.8h, v28.8h}, [x0]
-#   v25: 0x393831302928212019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x3b3a33322b2a23221b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x3d3c35342d2c25241d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x3f3e37362f2e27261f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831302928212019180000feffff01 (0.6523, 0.1621, 0.04028, 0.01001, 0.002487, 0.000, nan, nan)
+#            v26: 0x3b3a33322b2a23221b1a000000ff0002 (0.9033, 0.2249, 0.05597, 0.01393, 0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            v27: 0x3d3c35342d2c25241d1c000000000085 (1.309, 0.3252, 0.08081, 0.02008, 0.004990, 0.000, 0.000, 7.927e-06)
+#            v28: 0x3f3e37362f2e27261f1e17000000ff00 (1.811, 0.4507, 0.1122, 0.02792, 0.006950, 0.001709, 0.000, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726'2524'2322'2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2f2e'2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3736'3534'3332'3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e'3d3c'3b3a'3938 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc20422		ld4 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
-#    v2: 0x53524b4a43423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x55544d4c45443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x57564f4e47463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x59585150494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x53524b4a43423b3a33322b2a23221b1a (58.56, 14.58, 3.629, 0.9033, 0.2249, 0.05597, 0.01393, 0.003468)
+#             v3: 0x55544d4c45443d3c35342d2c25241d1c (85.25, 21.19, 5.266, 1.309, 0.3252, 0.08081, 0.02008, 0.004990)
+#             v4: 0x57564f4e47463f3e37362f2e27261f1e (117.4, 29.22, 7.273, 1.811, 0.4507, 0.1122, 0.02792, 0.006950)
+#             v5: 0x59585150494841403938313029282120 (171.0, 42.50, 10.56, 2.625, 0.6523, 0.1621, 0.04028, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120'1f1e'1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2928'2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3130'2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3938'3736'3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4140'3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948'4746'4544'4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5150'4f4e'4d4c'4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5958'5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf0434		ld4 {v20.8h, v21.8h, v22.8h, v23.8h}, [x1], #64
-#   v20: 0x52514a4942413a3932312a2922211a19 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x54534c4b44433c3b34332c2b24231c1b <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x56554e4d46453e3d36352e2d26251e1d <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x5857504f4847403f3837302f2827201f <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2922211a19 (50.53, 12.57, 3.127, 0.7778, 0.1935, 0.04813, 0.01197, 0.002977)
+#            v21: 0x54534c4b44433c3b34332c2b24231c1b (69.19, 17.17, 4.262, 1.058, 0.2625, 0.06512, 0.01616, 0.004009)
+#            v22: 0x56554e4d46453e3d36352e2d26251e1d (101.3, 25.20, 6.270, 1.560, 0.3879, 0.09650, 0.02400, 0.005970)
+#            v23: 0x5857504f4847403f3837302f2827201f (138.9, 34.47, 8.555, 2.123, 0.5269, 0.1307, 0.03244, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f'1e1d'1c1b'1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2827'2625'2423'2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x302f'2e2d'2c2b'2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3837'3635'3433'3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x403f'3e3d'3c3b'3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847'4645'4443'4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x504f'4e4d'4c4b'4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5857'5655'5453'5251 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d602c14		ld4 {v20.b, v21.b, v22.b, v23.b}[3], [x0]
-#   v20: 0x52514a4942413a3932312a2901211a19 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x54534c4b44433c3b34332c2bff231c1b <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x56554e4d46453e3d36352e2d02251e1d <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x5857504f4847403f3837302f0027201f <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2901211a19
+#            v21: 0x54534c4b44433c3b34332c2bff231c1b
+#            v22: 0x56554e4d46453e3d36352e2d02251e1d
+#            v23: 0x5857504f4847403f3837302f0027201f
+#                                            ╙─────── 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de22c2c		ld4 {v12.b, v13.b, v14.b, v15.b}[3], [x1], x2
-#   v12: 0x0000000000000000fbfbfbfb59fbfbfb <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x81807b7a75746f6ea9a8a7a65a5c5756 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x00000000000000001c1800005cff8501 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000fbfbfbfb59fbfbfb
+#            v13: 0x81807b7a75746f6ea9a8a7a65a5c5756
+#            v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6
+#            v15: 0x00000000000000001c1800005cff8501
+#                                            ╙─────── 0x5c'5b'5a'59 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff383b		ld4 {v27.b, v28.b, v29.b, v30.b}[6], [x1], #4
-#   v27: 0x3d3c35342d2c25241d58000000000085 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x3f3e37362f2e27261f5917000000ff00 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000195a110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000001a5b120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x3d3c35342d2c25241d58000000000085
+#            v28: 0x3f3e37362f2e27261f5917000000ff00
+#            v29: 0x0000000000000000195a110d090501fd
+#            v30: 0x00000000000000001a5b120e0a0602fe
+#                                      ╙───────────── 0x5b'5a'59'58 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60a41c		ld4 {v28.d, v29.d, v30.d, v31.d}[1], [x0]
-#   v28: 0xff0000850002ff011f5917000000ff00 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000fffeff195a110d090501fd (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x17000000000000001a5b120e0a0602fe (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff0000850002ff011f5917000000ff00 (-5.487e+303, ...)
+#            v29: 0x0000000000fffeff195a110d090501fd (8.289e-317, ...)
+#            v30: 0x17000000000000001a5b120e0a0602fe (6.689e-198, ...)
+#            v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.568e-159, ...)
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2a42f		ld4 {v15.d, v16.d, v17.d, v18.d}[1], [x1], x2
-#   v15: 0x636261605f5e5d5c1c1800005cff8501 (5.54935e+170, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x6b6a6968676665641d19000000fe00ff (2.71346e+209, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x7b7a7978777675741f1b17000000ff00 (6.29888e+286, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x636261605f5e5d5c1c1800005cff8501 (5.549e+170, ...)
+#            v16: 0x6b6a6968676665641d19000000fe00ff (2.713e+209, ...)
+#            v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.290e+248, ...)
+#            v18: 0x7b7a7978777675741f1b17000000ff00 (6.299e+286, ...)
+#                                  ╙───────────────── 0x7b7a797877767574'737271706f6e6d6c'6b6a696867666564'636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffa430		ld4 {v16.d, v17.d, v18.d, v19.d}[1], [x1], #32
-#   v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.00514e+165, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x6a696867666564631e1a000000ff0002 (3.98304e+204, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x7a797877767574731f1e17000000ff00 (9.24687e+281, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.005e+165, ...)
+#            v17: 0x6a696867666564631e1a000000ff0002 (3.983e+204, ...)
+#            v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.861e+243, ...)
+#            v19: 0x7a797877767574731f1e17000000ff00 (9.247e+281, ...)
+#                                  ╙───────────────── 0x7a79787776757473'7271706f6e6d6c6b'6a69686766656463'6261605f5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d607002		ld4 {v2.h, v3.h, v4.h, v5.h}[6], [x0]
-#    v2: 0x5352ff0143423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x5554000245443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x5756008547463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x5958ff00494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x5352ff0143423b3a33322b2a23221b1a (..., nan, ...)
+#             v3: 0x5554000245443d3c35342d2c25241d1c (..., 1.192e-07, ...)
+#             v4: 0x5756008547463f3e37362f2e27261f1e (..., 7.927e-06, ...)
+#             v5: 0x5958ff00494841403938313029282120 (..., nan, ...)
+#                          ╙───────────────────────── 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de27825		ld4 {v5.h, v6.h, v7.h, v8.h}[3], [x1], x2
-#    v5: 0x5958ff00494841407c7b313029282120 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000007e7d0f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x0000000000000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5958ff00494841407c7b313029282120 (..., nan, ...)
+#             v6: 0x00000000000000007e7d0f0b0703fffb (..., nan, ...)
+#             v7: 0x0000000000000000807f100c080400fc (..., -7.570e-06, ...)
+#             v8: 0x00000000000000008281110d090501fd (..., -3.821e-05, ...)
+#                                      ╙───────────── 0x8281'807f'7e7d'7c7b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dff7027		ld4 {v7.h, v8.h, v9.h, v10.h}[6], [x1], #8
-#    v7: 0x00007b7a00000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00007d7c000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x3b3a7f7e2b2a29281b1a191800fffeff <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x00007b7a00000000807f100c080400fc (..., 6.125e+04, ...)
+#             v8: 0x00007d7c000000008281110d090501fd (..., nan, ...)
+#             v9: 0x3b3a7f7e2b2a29281b1a191800fffeff (..., nan, ...)
+#            v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 (..., -2.289e-05, ...)
+#                          ╙───────────────────────── 0x8180'7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60b006		ld4 {v6.s, v7.s, v8.s, v9.s}[1], [x0]
-#    v6: 0x00000000000000000002ff010703fffb (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00007b7a00000000ff000085080400fc (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00007d7c0000000000fffeff090501fd (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x00000000000000000002ff010703fffb (..., 2.751e-40, ...)
+#             v7: 0x00007b7a00000000ff000085080400fc (..., -1.701e+38, ...)
+#             v8: 0x00007d7c0000000000fffeff090501fd (..., 2.351e-38, ...)
+#             v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.000, ...)
+#                                          ╙───────── 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2a039		ld4 {v25.s, v26.s, v27.s, v28.s}[2], [x1], x2
-#   v25: 0x393831308584838219180000feffff01 (..., -1.24615e-35, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.28683e-33, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.66176e-31, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.28077e-28, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831308584838219180000feffff01 (..., -1.246e-35, ...)
+#            v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.287e-33, ...)
+#            v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.662e-31, ...)
+#            v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.281e-28, ...)
+#                                  ╙───────────────── 0x91908f8e'8d8c8b8a'89888786'85848382 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffb028		ld4 {v8.s, v9.s, v10.s, v11.s}[3], [x1], #16
-#    v8: 0x848382810000000000fffeff090501fd (-3.09178e-36, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x888786852b2a29280000000000fffeff (-8.15664e-34, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x908f8e8d00000000fafafafafafafafa (-5.66232e-29, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x848382810000000000fffeff090501fd (-3.092e-36, ...)
+#             v9: 0x888786852b2a29280000000000fffeff (-8.157e-34, ...)
+#            v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.150e-31, ...)
+#            v11: 0x908f8e8d00000000fafafafafafafafa (-5.662e-29, ...)
+#                          ╙───────────────────────── 0x908f8e8d'8c8b8a89'88878685'84838281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60e00e		ld4r {v14.16b, v15.16b, v16.16b, v17.16b}, [x0]
-#   v14: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x01010101010101010101010101010101
+#            v15: 0xffffffffffffffffffffffffffffffff
+#            v16: 0x02020202020202020202020202020202
+#            v17: 0x00000000000000000000000000000000
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2e02d		ld4r {v13.16b, v14.16b, v15.16b, v16.16b}, [x1], x2
-#   v13: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x94949494949494949494949494949494 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x91919191919191919191919191919191
+#            v14: 0x92929292929292929292929292929292
+#            v15: 0x93939393939393939393939393939393
+#            v16: 0x94949494949494949494949494949494
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x94'93'92'91 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffe029		ld4r {v9.16b, v10.16b, v11.16b, v12.16b}, [x1], #4
-#    v9: 0x90909090909090909090909090909090 <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v9: 0x90909090909090909090909090909090
+#            v10: 0x91919191919191919191919191919191
+#            v11: 0x92929292929292929292929292929292
+#            v12: 0x93939393939393939393939393939393
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x93'92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60ec08		ld4r {v8.1d, v9.1d, v10.1d, v11.1d}, [x0]
-#    v8: 0x0000000000000000ff0000850002ff01 (d8: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x00000000000000000000000000fffeff (d9: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000001700000000000000 (d10: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000001f1e1d1c1b1a1918 (d11: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xff0000850002ff01 (-5.487e+303)
+#             d9:                 0x0000000000fffeff (8.289e-317)
+#            d10:                 0x1700000000000000 (6.689e-198)
+#            d11:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2ec24		ld4r {v4.1d, v5.1d, v6.1d, v7.1d}, [x1], x2
-#    v4: 0x00000000000000009b9a999897969594 (d4: -1.05028e-175) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0000000000000000a3a2a1a09f9e9d9c (d5: -5.00653e-137) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x0000000000000000abaaa9a8a7a6a5a4 (d6: -2.43801e-98) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x0000000000000000b3b2b1b0afaeadac (d7: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x9b9a999897969594 (-1.050e-175)
+#             d5:                 0xa3a2a1a09f9e9d9c (-5.007e-137)
+#             d6:                 0xabaaa9a8a7a6a5a4 (-2.438e-98)
+#             d7:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac'abaaa9a8a7a6a5a4'a3a2a1a09f9e9d9c'9b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffec3a		ld4r {v26.1d, v27.1d, v28.1d, v29.1d}, [x1], #32
-#   v26: 0x00000000000000009a99989796959493 (d26: -1.54211e-180) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000a2a1a09f9e9d9c9b (d27: -7.22772e-142) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x0000000000000000aaa9a8a7a6a5a4a3 (d28: -3.58004e-103) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000b2b1b0afaeadacab (d29: -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x9a99989796959493 (-1.542e-180)
+#            d27:                 0xa2a1a09f9e9d9c9b (-7.228e-142)
+#            d28:                 0xaaa9a8a7a6a5a4a3 (-3.580e-103)
+#            d29:                 0xb2b1b0afaeadacab (-1.680e-64)
+#                                                  ╙─ 0xb2b1b0afaeadacab'aaa9a8a7a6a5a4a3'a2a1a09f9e9d9c9b'9a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60ec13		ld4r {v19.2d, v20.2d, v21.2d, v22.2d}, [x0]
-#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v20: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v21: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#            v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.568e-159, 8.568e-159)
+#                                  ╙───────────────╨─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2ec3c		ld4r {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], x2
-#   v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.31108e-26, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.90391e+13, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.92941e+52, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.07279e+90, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.311e-26, -8.311e-26)
+#            v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.904e+13, -3.904e+13)
+#            v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.929e+52, -1.929e+52)
+#            v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.073e+90, -9.073e+90)
+#                                  ╙───────────────╨─ 0xd2d1d0cfcecdcccb'cac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffec2f		ld4r {v15.2d, v16.2d, v17.2d, v18.2d}, [x1], #32
-#   v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.21867e-30, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.62003e+08, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.82942e+47, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.30639e+86, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.219e-30, -1.219e-30)
+#            v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.620e+08, -5.620e+08)
+#            v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.829e+47, -2.829e+47)
+#            v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.306e+86, -1.306e+86)
+#                                  ╙───────────────╨─ 0xd1d0cfcecdcccbca'c9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60e81f		ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [x0]
-#   v31: 0x00000000000000000002ff010002ff01 (s31: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x0000000000000000ff000085ff000085 (s0: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x000000000000000000fffeff00fffeff (s1: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x00000000000000000000000000000000 (s2: 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#             d0:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#             d1:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#             d2:                 0x0000000000000000 (0.000, 0.000)
+#                                          ╙───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2e83c		ld4r {v28.2s, v29.2s, v30.2s, v31.2s}, [x1], x2
-#   v28: 0x0000000000000000d5d4d3d2d5d4d3d2 (s28: -2.92508e+13) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000d9d8d7d6d9d8d7d6 (s29: -7.62949e+15) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000dddcdbdadddcdbda (s30: -1.98932e+18) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x0000000000000000e1e0dfdee1e0dfde (s31: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xd5d4d3d2d5d4d3d2 (-2.925e+13, -2.925e+13)
+#            d29:                 0xd9d8d7d6d9d8d7d6 (-7.629e+15, -7.629e+15)
+#            d30:                 0xdddcdbdadddcdbda (-1.989e+18, -1.989e+18)
+#            d31:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#                                          ╙───────╨─ 0xe1e0dfde'dddcdbda'd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffe82b		ld4r {v11.2s, v12.2s, v13.2s, v14.2s}, [x1], #16
-#   v11: 0x0000000000000000d4d3d2d1d4d3d2d1 (s11: -7.27820e+12) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000000000d8d7d6d5d8d7d6d5 (s12: -1.89854e+15) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0000000000000000dcdbdad9dcdbdad9 (s13: -4.95069e+17) <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x0000000000000000e0dfdedde0dfdedd (s14: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xd4d3d2d1d4d3d2d1 (-7.278e+12, -7.278e+12)
+#            d12:                 0xd8d7d6d5d8d7d6d5 (-1.899e+15, -1.899e+15)
+#            d13:                 0xdcdbdad9dcdbdad9 (-4.951e+17, -4.951e+17)
+#            d14:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#                                          ╙───────╨─ 0xe0dfdedd'dcdbdad9'd8d7d6d5'd4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60e413		ld4r {v19.4h, v20.4h, v21.4h, v22.4h}, [x0]
-#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x0000000000000000ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d20:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d21:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            d22:                 0xff00ff00ff00ff00 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2e436		ld4r {v22.4h, v23.4h, v24.4h, v25.4h}, [x1], x2
-#   v22: 0x0000000000000000e2e1e2e1e2e1e2e1 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x0000000000000000e4e3e4e3e4e3e4e3 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000e6e5e6e5e6e5e6e5 <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x0000000000000000e8e7e8e7e8e7e8e7 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xe2e1e2e1e2e1e2e1 (-880.5, -880.5, -880.5, -880.5)
+#            d23:                 0xe4e3e4e3e4e3e4e3 (-1251., -1251., -1251., -1251.)
+#            d24:                 0xe6e5e6e5e6e5e6e5 (-1765., -1765., -1765., -1765.)
+#            d25:                 0xe8e7e8e7e8e7e8e7 (-2510., -2510., -2510., -2510.)
+#                                      ╙───╨───╨───╨─ 0xe8e7'e6e5'e4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffe434		ld4r {v20.4h, v21.4h, v22.4h, v23.4h}, [x1], #8
-#   v20: 0x0000000000000000e1e0e1e0e1e0e1e0 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x0000000000000000e3e2e3e2e3e2e3e2 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x0000000000000000e5e4e5e4e5e4e5e4 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x0000000000000000e7e6e7e6e7e6e7e6 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xe1e0e1e0e1e0e1e0 (-752.0, -752.0, -752.0, -752.0)
+#            d21:                 0xe3e2e3e2e3e2e3e2 (-1009., -1009., -1009., -1009.)
+#            d22:                 0xe5e4e5e4e5e4e5e4 (-1508., -1508., -1508., -1508.)
+#            d23:                 0xe7e6e7e6e7e6e7e6 (-2022., -2022., -2022., -2022.)
+#                                      ╙───╨───╨───╨─ 0xe7e6'e5e4'e3e2'e1e0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60e810		ld4r {v16.4s, v17.4s, v18.4s, v19.4s}, [x0]
-#   v16: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v17: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v18: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#            v19: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ╙───────╨───────╨───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2e839		ld4r {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
-#   v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (..., -5.67986e+26, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0xefeeedecefeeedecefeeedecefeeedec (..., -1.47890e+29, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (..., -3.84962e+31, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (..., -1.00179e+34, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (-5.680e+26, -5.680e+26, -5.680e+26, -5.680e+26)
+#            v26: 0xefeeedecefeeedecefeeedecefeeedec (-1.479e+29, -1.479e+29, -1.479e+29, -1.479e+29)
+#            v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (-3.850e+31, -3.850e+31, -3.850e+31, -3.850e+31)
+#            v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (-1.002e+34, -1.002e+34, -1.002e+34, -1.002e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf7f6f5f4'f3f2f1f0'efeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffe837		ld4r {v23.4s, v24.4s, v25.4s, v26.4s}, [x1], #16
-#   v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (..., -1.41390e+26, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0xeeedecebeeedecebeeedecebeeedeceb (..., -3.68172e+28, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (..., -9.58428e+30, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (..., -2.49430e+33, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (-1.414e+26, -1.414e+26, -1.414e+26, -1.414e+26)
+#            v24: 0xeeedecebeeedecebeeedecebeeedeceb (-3.682e+28, -3.682e+28, -3.682e+28, -3.682e+28)
+#            v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (-9.584e+30, -9.584e+30, -9.584e+30, -9.584e+30)
+#            v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (-2.494e+33, -2.494e+33, -2.494e+33, -2.494e+33)
+#                          ╙───────╨───────╨───────╨─ 0xf6f5f4f3'f2f1f0ef'eeedeceb'eae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60e016		ld4r {v22.8b, v23.8b, v24.8b, v25.8b}, [x0]
-#   v22: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x0101010101010101
+#            d23:                 0xffffffffffffffff
+#            d24:                 0x0202020202020202
+#            d25:                 0x0000000000000000
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2e03b		ld4r {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
-#   v27: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xf7f7f7f7f7f7f7f7
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8'f7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffe03d		ld4r {v29.8b, v30.8b, v31.8b, v0.8b}, [x1], #4
-#   v29: 0x0000000000000000f6f6f6f6f6f6f6f6 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xf6f6f6f6f6f6f6f6
+#            d30:                 0xf7f7f7f7f7f7f7f7
+#            d31:                 0xf8f8f8f8f8f8f8f8
+#             d0:                 0xf9f9f9f9f9f9f9f9
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xf9'f8'f7'f6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60e41c		ld4r {v28.8h, v29.8h, v30.8h, v31.8h}, [x0]
-#   v28: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xff00ff00ff00ff00ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v29: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            v30: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            v31: 0xff00ff00ff00ff00ff00ff00ff00ff00 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2e439		ld4r {v25.8h, v26.8h, v27.8h, v28.8h}, [x1], x2
-#   v25: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x01000100010001000100010001000100 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#            v26: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v27: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v28: 0x01000100010001000100010001000100 (1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0100'fffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffe436		ld4r {v22.8h, v23.8h, v24.8h, v25.8h}, [x1], #8
-#   v22: 0xfaf9faf9faf9faf9faf9faf9faf9faf9 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0xfaf9faf9faf9faf9faf9faf9faf9faf9 (-5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04)
+#            v23: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v24: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v25: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4e3a94fd		mla v29.16b, v7.16b, v26.16b
-#   v29: 0x0002000200020002e73aed42f34af952
+#            v29: 0x0002000200020002e73aed42f34af952
 0x~~~~~~~~~~~~~~~~  0eae9486		mla v6.2s, v4.2s, v14.2s
-#    v6: 0x0000000000000000dcbb11e0e6481e68
+#             v6: 0x0000000000000000dcbb11e0e6481e68
 0x~~~~~~~~~~~~~~~~  2f800969		mla v9.2s, v11.2s, v0.s[2]
-#    v9: 0x00000000000000000000000000fffeff
+#             v9: 0x00000000000000000000000000fffeff
 0x~~~~~~~~~~~~~~~~  0e799625		mla v5.4h, v17.4h, v25.4h
-#    v5: 0x0000000000000000a4a2261ba09e2217
+#             v5: 0x0000000000000000a4a2261ba09e2217
 0x~~~~~~~~~~~~~~~~  2f7b00f8		mla v24.4h, v7.4h, v11.h[3]
-#   v24: 0x000000000000000082b3330de36793c1
+#            v24: 0x000000000000000082b3330de36793c1
 0x~~~~~~~~~~~~~~~~  4ea4946c		mla v12.4s, v3.4s, v4.4s
-#   v12: 0x00000000000000006f49f4f5e911f705
+#            v12: 0x00000000000000006f49f4f5e911f705
 0x~~~~~~~~~~~~~~~~  6fa708ea		mla v10.4s, v7.4s, v7.s[3]
-#   v10: 0x00000000000000001700000000000000
+#            v10: 0x00000000000000001700000000000000
 0x~~~~~~~~~~~~~~~~  0e299603		mla v3.8b, v16.8b, v9.8b
-#    v3: 0x000000000000000035342d2c25221f1b
+#             v3: 0x000000000000000035342d2c25221f1b
 0x~~~~~~~~~~~~~~~~  4e7296d3		mla v19.8h, v22.8h, v18.8h
-#   v19: 0xfe070c07fe070c07fe070c07fe070c07
+#            v19: 0xfe070c07fe070c07fe070c07fe070c07
 0x~~~~~~~~~~~~~~~~  6f400046		mla v6.8h, v2.8h, v0.h[0]
-#    v6: 0x0000000000000000dcbb11e0e6481e68
+#             v6: 0x0000000000000000dcbb11e0e6481e68
 0x~~~~~~~~~~~~~~~~  6e2b9557		mls v23.16b, v10.16b, v11.16b
-#   v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+#            v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
 0x~~~~~~~~~~~~~~~~  2eb697ee		mls v14.2s, v31.2s, v22.2s
-#   v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+#            v14: 0x0000000000000000d8e1d7ddd8e1d7dd
 0x~~~~~~~~~~~~~~~~  2fa149bc		mls v28.2s, v13.2s, v1.s[3]
-#   v28: 0x00000000000000000100010001000100
+#            v28: 0x00000000000000000100010001000100
 0x~~~~~~~~~~~~~~~~  2e6d9662		mls v2.4h, v19.4h, v13.4h
-#    v2: 0x0000000000000000ac03d811ac03d811
+#             v2: 0x0000000000000000ac03d811ac03d811
 0x~~~~~~~~~~~~~~~~  2f6c49f2		mls v18.4h, v15.4h, v12.h[6]
-#   v18: 0x000000000000000000fffeff00fffeff
+#            v18: 0x000000000000000000fffeff00fffeff
 0x~~~~~~~~~~~~~~~~  6eb09566		mls v6.4s, v11.4s, v16.4s
-#    v6: 0x00000000000000006347100f6cd41c97
+#             v6: 0x00000000000000006347100f6cd41c97
 0x~~~~~~~~~~~~~~~~  6f8a4a17		mls v23.4s, v16.4s, v10.s[2]
-#   v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+#            v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
 0x~~~~~~~~~~~~~~~~  2e3795ba		mls v26.8b, v13.8b, v23.8b
-#   v26: 0x0000000000000000bd4365396d436539
+#            v26: 0x0000000000000000bd4365396d436539
 0x~~~~~~~~~~~~~~~~  6e6c954a		mls v10.8h, v10.8h, v12.8h
-#   v10: 0x00000000000000008800000000000000
+#            v10: 0x00000000000000008800000000000000
 0x~~~~~~~~~~~~~~~~  6f7e480e		mls v14.8h, v0.8h, v14.h[7]
-#   v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+#            v14: 0x0000000000000000d8e1d7ddd8e1d7dd
 0x~~~~~~~~~~~~~~~~  5e070436		mov b22, v1.b[3]
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e1805a7		mov d7, v13.d[1]
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e0a06ba		mov h26, v21.h[2]
-#   v26: 0x0000000000000000000000000000e3e2
+#            v26: 0x0000000000000000000000000000e3e2
 0x~~~~~~~~~~~~~~~~  5e04067a		mov s26, v19.s[0]
-#   v26: 0x000000000000000000000000fe070c07
+#            v26: 0x000000000000000000000000fe070c07
 0x~~~~~~~~~~~~~~~~  4eab1d7a		mov v26.16b, v11.16b
-#   v26: 0x0000000000000000d4d3d2d1d4d3d2d1
+#            v26: 0x0000000000000000d4d3d2d1d4d3d2d1
 0x~~~~~~~~~~~~~~~~  0ea01c14		mov v20.8b, v0.8b
-#   v20: 0x0000000000000000f9f9f9f9f9f9f9f9
+#            v20: 0x0000000000000000f9f9f9f9f9f9f9f9
 0x~~~~~~~~~~~~~~~~  6e1b24d3		mov v19.b[13], v6.b[4]
-#   v19: 0xfe070f07fe070c07fe070c07fe070c07
+#            v19: 0xfe070f07fe070c07fe070c07fe070c07
 0x~~~~~~~~~~~~~~~~  4e1b1e64		mov v4.b[13], w19
-#    v4: 0x00000000000000009b9a999897969594
+#             v4: 0x00000000000000009b9a999897969594
 0x~~~~~~~~~~~~~~~~  6e18050b		mov v11.d[1], v8.d[0]
-#   v11: 0xff0000850002ff01d4d3d2d1d4d3d2d1
+#            v11: 0xff0000850002ff01d4d3d2d1d4d3d2d1
 0x~~~~~~~~~~~~~~~~  4e081fc3		mov v3.d[0], x30
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e12757d		mov v29.h[4], v11.h[7]
-#   v29: 0x000200020002ff00e73aed42f34af952
+#            v29: 0x000200020002ff00e73aed42f34af952
 0x~~~~~~~~~~~~~~~~  4e1a1cc2		mov v2.h[6], w6
-#    v2: 0x0000000c00000000ac03d811ac03d811
+#             v2: 0x0000ffff00000000ac03d811ac03d811
 0x~~~~~~~~~~~~~~~~  6e0444b6		mov v22.s[0], v5.s[2]
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e1c1d18		mov v24.s[3], w8
-#   v24: 0x000000000000000082b3330de36793c1
+#            v24: 0x000000000000000082b3330de36793c1
 0x~~~~~~~~~~~~~~~~  0e1c3c32		mov w18, v1.s[3]
-#   x18: 0x0000000000000000
+#            x18: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  4e083ebc		mov x28, v21.d[0]
-#   x28: 0xe3e2e3e2e3e2e3e2
+#            x28: 0xe3e2e3e2e3e2e3e2
 0x~~~~~~~~~~~~~~~~  2f03e4f8		movi d24, #0xffff0000ffffff
-#   v24: 0x000000000000000000ffff0000ffffff
+#            v24: 0x000000000000000000ffff0000ffffff
 0x~~~~~~~~~~~~~~~~  4f04e41d		movi v29.16b, #0x80
-#   v29: 0x80808080808080808080808080808080
+#            v29: 0x80808080808080808080808080808080
 0x~~~~~~~~~~~~~~~~  6f06e6cc		movi v12.2d, #0xffff00ff00ffff00
-#   v12: 0xffff00ff00ffff00ffff00ff00ffff00
+#            v12: 0xffff00ff00ffff00ffff00ff00ffff00
 0x~~~~~~~~~~~~~~~~  0f07658c		movi v12.2s, #0xec, lsl #24
-#   v12: 0x0000000000000000ec000000ec000000
+#            v12: 0x0000000000000000ec000000ec000000
 0x~~~~~~~~~~~~~~~~  0f02d58a		movi v10.2s, #0x4c, msl #16
-#   v10: 0x0000000000000000004cffff004cffff
+#            v10: 0x0000000000000000004cffff004cffff
 0x~~~~~~~~~~~~~~~~  0f06841a		movi v26.4h, #0xc0, lsl #0
-#   v26: 0x000000000000000000c000c000c000c0
+#            v26: 0x000000000000000000c000c000c000c0
 0x~~~~~~~~~~~~~~~~  4f044718		movi v24.4s, #0x98, lsl #16
-#   v24: 0x00980000009800000098000000980000
+#            v24: 0x00980000009800000098000000980000
 0x~~~~~~~~~~~~~~~~  4f06d7c1		movi v1.4s, #0xde, msl #16
-#    v1: 0x00deffff00deffff00deffff00deffff
+#             v1: 0x00deffff00deffff00deffff00deffff
 0x~~~~~~~~~~~~~~~~  0f02e5b5		movi v21.8b, #0x4d
-#   v21: 0x00000000000000004d4d4d4d4d4d4d4d
+#            v21: 0x00000000000000004d4d4d4d4d4d4d4d
 0x~~~~~~~~~~~~~~~~  4f03853d		movi v29.8h, #0x69, lsl #0
-#   v29: 0x00690069006900690069006900690069
+#            v29: 0x00690069006900690069006900690069
 0x~~~~~~~~~~~~~~~~  4e319de1		mul v1.16b, v15.16b, v17.16b
-#    v1: 0x4700008e4b00007a4700008e4b00007a
+#             v1: 0x4700008e4b00007a4700008e4b00007a
 0x~~~~~~~~~~~~~~~~  0ebd9e75		mul v21.2s, v19.2s, v29.2s
-#   v21: 0x00000000000000001fc2eedf1fc2eedf
+#            v21: 0x00000000000000001fc2eedf1fc2eedf
 0x~~~~~~~~~~~~~~~~  0f8380b3		mul v19.2s, v5.2s, v3.s[0]
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e629d7d		mul v29.4h, v11.4h, v2.4h
-#   v29: 0x0000000000000000427957e1427957e1
+#            v29: 0x0000000000000000427957e1427957e1
 0x~~~~~~~~~~~~~~~~  0f4080e2		mul v2.4h, v7.4h, v0.h[0]
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb09f59		mul v25.4s, v26.4s, v16.4s
-#   v25: 0x000000000000000042ff40c042ff40c0
+#            v25: 0x000000000000000042ff40c042ff40c0
 0x~~~~~~~~~~~~~~~~  4f8f88da		mul v26.4s, v6.4s, v15.s[2]
-#   v26: 0x00000000000000009d2fa76ed8a575fe
+#            v26: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  0e3f9deb		mul v11.8b, v15.8b, v31.8b
-#   v11: 0x0000000000000000470049004b004d00
+#            v11: 0x0000000000000000470049004b004d00
 0x~~~~~~~~~~~~~~~~  4e6f9ff4		mul v20.8h, v31.8h, v15.8h
-#   v20: 0x48004a004c004e0048004a004c004e00
+#            v20: 0x48004a004c004e0048004a004c004e00
 0x~~~~~~~~~~~~~~~~  4f4988bd		mul v29.8h, v5.8h, v9.h[4]
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e205aad		mvn v13.16b, v21.16b
-#   v13: 0xffffffffffffffffe03d1120e03d1120
+#            v13: 0xffffffffffffffffe03d1120e03d1120
 0x~~~~~~~~~~~~~~~~  2e205a7c		mvn v28.8b, v19.8b
-#   v28: 0x0000000000000000ffffffffffffffff
+#            v28: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2f052719		mvni v25.2s, #0xb8, lsl #8
-#   v25: 0x0000000000000000ffff47ffffff47ff
+#            v25: 0x0000000000000000ffff47ffffff47ff
 0x~~~~~~~~~~~~~~~~  2f03d591		mvni v17.2s, #0x6c, msl #16
-#   v17: 0x0000000000000000ff930000ff930000
+#            v17: 0x0000000000000000ff930000ff930000
 0x~~~~~~~~~~~~~~~~  2f02851d		mvni v29.4h, #0x48, lsl #0
-#   v29: 0x0000000000000000ffb7ffb7ffb7ffb7
+#            v29: 0x0000000000000000ffb7ffb7ffb7ffb7
 0x~~~~~~~~~~~~~~~~  6f034754		mvni v20.4s, #0x7a, lsl #16
-#   v20: 0xff85ffffff85ffffff85ffffff85ffff
+#            v20: 0xff85ffffff85ffffff85ffffff85ffff
 0x~~~~~~~~~~~~~~~~  6f00c7c0		mvni v0.4s, #0x1e, msl #8
-#    v0: 0xffffe100ffffe100ffffe100ffffe100
+#             v0: 0xffffe100ffffe100ffffe100ffffe100
 0x~~~~~~~~~~~~~~~~  6f0187df		mvni v31.8h, #0x3e, lsl #0
-#   v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
+#            v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
 0x~~~~~~~~~~~~~~~~  7ee0b979		neg d25, d11
-#   v25: 0x0000000000000000b8ffb6ffb4ffb300
+#            v25: 0x0000000000000000b8ffb6ffb4ffb300
 0x~~~~~~~~~~~~~~~~  6e20b924		neg v4.16b, v9.16b
-#    v4: 0x00000000000000000000000000010201
+#             v4: 0x00000000000000000000000000010201
 0x~~~~~~~~~~~~~~~~  6ee0bb2b		neg v11.2d, v25.2d
-#   v11: 0x0000000000000000470049004b004d00
+#            v11: 0x0000000000000000470049004b004d00
 0x~~~~~~~~~~~~~~~~  2ea0ba47		neg v7.2s, v18.2s
-#    v7: 0x0000000000000000ff000101ff000101
+#             v7: 0x0000000000000000ff000101ff000101
 0x~~~~~~~~~~~~~~~~  2e60b9e7		neg v7.4h, v15.4h
-#    v7: 0x00000000000000004648484a4a4c4c4e
+#             v7: 0x00000000000000004648484a4a4c4c4e
 0x~~~~~~~~~~~~~~~~  6ea0ba51		neg v17.4s, v18.4s
-#   v17: 0x0000000000000000ff000101ff000101
+#            v17: 0x0000000000000000ff000101ff000101
 0x~~~~~~~~~~~~~~~~  2e20ba34		neg v20.8b, v17.8b
-#   v20: 0x00000000000000000100ffff0100ffff
+#            v20: 0x00000000000000000100ffff0100ffff
 0x~~~~~~~~~~~~~~~~  6e60b960		neg v0.8h, v11.8h
-#    v0: 0x0000000000000000b900b700b500b300
+#             v0: 0x0000000000000000b900b700b500b300
 0x~~~~~~~~~~~~~~~~  4eff1d6d		orn v13.16b, v11.16b, v31.16b
-#   v13: 0x003e003e003e003e473e493e4b3e4d3e
+#            v13: 0x003e003e003e003e473e493e4b3e4d3e
 0x~~~~~~~~~~~~~~~~  0ef61e16		orn v22.8b, v16.8b, v22.8b
-#   v22: 0x0000000000000000ffffffffffffffff
+#            v22: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4eb71e31		orr v17.16b, v17.16b, v23.16b
-#   v17: 0xfcfbfcfbfcfbfcfbfffbfdfbfffbfdfb
+#            v17: 0xfcfbfcfbfcfbfcfbfffbfdfbfffbfdfb
 0x~~~~~~~~~~~~~~~~  0f071468		orr v8.2s, #0xe3, lsl #0
-#    v8: 0x0000000000000000ff0000e70002ffe3
+#             v8: 0x0000000000000000ff0000e70002ffe3
 0x~~~~~~~~~~~~~~~~  0f04b6eb		orr v11.4h, #0x97, lsl #8
-#   v11: 0x0000000000000000d700df00df00df00
+#            v11: 0x0000000000000000d700df00df00df00
 0x~~~~~~~~~~~~~~~~  4f051567		orr v7.4s, #0xab, lsl #0
-#    v7: 0x000000ab000000ab464848eb4a4c4cef
+#             v7: 0x000000ab000000ab464848eb4a4c4cef
 0x~~~~~~~~~~~~~~~~  0ea31c88		orr v8.8b, v4.8b, v3.8b
-#    v8: 0x00000000000000000000000000010201
+#             v8: 0x00000000000000000000000000010201
 0x~~~~~~~~~~~~~~~~  4f05b61f		orr v31.8h, #0xb0, lsl #8
-#   v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
+#            v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
 0x~~~~~~~~~~~~~~~~  6e379e4b		pmul v11.16b, v18.16b, v23.16b
-#   v11: 0x000000000000000000a9a8a900a9a8a9
+#            v11: 0x000000000000000000a9a8a900a9a8a9
 0x~~~~~~~~~~~~~~~~  2e259f08		pmul v8.8b, v24.8b, v5.8b
-#    v8: 0x00000000000000000030000000100000
+#             v8: 0x00000000000000000030000000100000
 0x~~~~~~~~~~~~~~~~  0e36e258		pmull v24.8h, v18.8b, v22.8b
-#   v24: 0x0000555555aa55550000555555aa5555
+#            v24: 0x0000555555aa55550000555555aa5555
 0x~~~~~~~~~~~~~~~~  4e35e06d		pmull2 v13.8h, v3.16b, v21.16b
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb54156		raddhn v22.2s, v10.2d, v21.2d
-#   v22: 0x000000000000000000000000200feede
+#            v22: 0x000000000000000000000000200feede
 0x~~~~~~~~~~~~~~~~  2e6d41a5		raddhn v5.4h, v13.4s, v13.4s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3a422a		raddhn v10.8b, v17.8h, v26.8h
-#   v10: 0x0000000000000000fdfdfdfd9da5d974
+#            v10: 0x0000000000000000fdfdfdfd9da5d974
 0x~~~~~~~~~~~~~~~~  6e2d43a9		raddhn2 v9.16b, v29.8h, v13.8h
-#    v9: 0x00000000000000000000000000fffeff
+#             v9: 0x00000000000000000000000000fffeff
 0x~~~~~~~~~~~~~~~~  6eba42fb		raddhn2 v27.4s, v23.2d, v26.2d
-#   v27: 0xfcfbfcfc8e2ba46bfffefffefffefffe
+#            v27: 0xfcfbfcfc8e2ba46bfffefffefffefffe
 0x~~~~~~~~~~~~~~~~  6e6743a0		raddhn2 v0.8h, v29.4s, v7.4s
-#    v0: 0x0000000046004a04b900b700b500b300
+#             v0: 0x0000000046004a04b900b700b500b300
 0x~~~~~~~~~~~~~~~~  6e6059f6		rbit v22.16b, v15.16b
-#   v22: 0x9d1ded6dad2dcd4d9d1ded6dad2dcd4d
+#            v22: 0x9d1ded6dad2dcd4d9d1ded6dad2dcd4d
 0x~~~~~~~~~~~~~~~~  2e60587e		rbit v30.8b, v3.8b
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e201b7f		rev16 v31.16b, v27.16b
-#   v31: 0xfbfcfcfc2b8e6ba4fefffefffefffeff
+#            v31: 0xfbfcfcfc2b8e6ba4fefffefffefffeff
 0x~~~~~~~~~~~~~~~~  0e201b4c		rev16 v12.8b, v26.8b
-#   v12: 0x00000000000000002f9d6ea7a5d8fe75
+#            v12: 0x00000000000000002f9d6ea7a5d8fe75
 0x~~~~~~~~~~~~~~~~  6e200885		rev32 v5.16b, v4.16b
-#    v5: 0x00000000000000000000000001020100
+#             v5: 0x00000000000000000000000001020100
 0x~~~~~~~~~~~~~~~~  2e600b50		rev32 v16.4h, v26.4h
-#   v16: 0x0000000000000000a76e9d2f75fed8a5
+#            v16: 0x0000000000000000a76e9d2f75fed8a5
 0x~~~~~~~~~~~~~~~~  2e200874		rev32 v20.8b, v3.8b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e600b94		rev32 v20.8h, v28.8h
-#   v20: 0x0000000000000000ffffffffffffffff
+#            v20: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e200a69		rev64 v9.16b, v19.16b
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea00a05		rev64 v5.2s, v16.2s
-#    v5: 0x000000000000000075fed8a5a76e9d2f
+#             v5: 0x000000000000000075fed8a5a76e9d2f
 0x~~~~~~~~~~~~~~~~  0e600be7		rev64 v7.4h, v31.4h
-#    v7: 0x0000000000000000fefffefffefffeff
+#             v7: 0x0000000000000000fefffefffefffeff
 0x~~~~~~~~~~~~~~~~  4ea00b4f		rev64 v15.4s, v26.4s
-#   v15: 0x0000000000000000d8a575fe9d2fa76e
+#            v15: 0x0000000000000000d8a575fe9d2fa76e
 0x~~~~~~~~~~~~~~~~  0e200939		rev64 v25.8b, v9.8b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6008ab		rev64 v11.8h, v5.8h
-#   v11: 0x00000000000000009d2fa76ed8a575fe
+#            v11: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  0f3f8db2		rshrn v18.2s, v13.2d, #1
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f1e8fd9		rshrn v25.4h, v30.4s, #2
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f088d2d		rshrn v13.8b, v9.8h, #8
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f088cc3		rshrn2 v3.16b, v6.8h, #8
-#    v3: 0x0000000063106d1d0000000000000000
+#             v3: 0x0000000063106d1d0000000000000000
 0x~~~~~~~~~~~~~~~~  4f278fa0		rshrn2 v0.4s, v29.2d, #25
-#    v0: 0x00000000dbffdc00b900b700b500b300
+#             v0: 0x00000000dbffdc00b900b700b500b300
 0x~~~~~~~~~~~~~~~~  4f118f5b		rshrn2 v27.8h, v26.4s, #15
-#   v27: 0x000000003a5fb14bfffefffefffefffe
+#            v27: 0x000000003a5fb14bfffefffefffefffe
 0x~~~~~~~~~~~~~~~~  2ea4632f		rsubhn v15.2s, v25.2d, v4.2d
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e636137		rsubhn v23.4h, v9.4s, v3.4s
-#   v23: 0x000000000000000000009cf000000000
+#            v23: 0x000000000000000000009cf000000000
 0x~~~~~~~~~~~~~~~~  2e3863c6		rsubhn v6.8b, v30.8h, v24.8h
-#    v6: 0x000000000000000000abaaab00abaaab
+#             v6: 0x000000000000000000abaaab00abaaab
 0x~~~~~~~~~~~~~~~~  6e346304		rsubhn2 v4.16b, v24.8h, v20.8h
-#    v4: 0x00555655005556550000000000010201
+#             v4: 0x00555655005556550000000000010201
 0x~~~~~~~~~~~~~~~~  6eb662e1		rsubhn2 v1.4s, v23.2d, v22.2d
-#    v1: 0x62e2129262e2af824700008e4b00007a
+#             v1: 0x62e2129262e2af824700008e4b00007a
 0x~~~~~~~~~~~~~~~~  6e746053		rsubhn2 v19.8h, v2.4s, v20.4s
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e397d3c		saba v28.16b, v9.16b, v25.16b
-#   v28: 0x0000000000000000ffffffffffffffff
+#            v28: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0eb47f89		saba v9.2s, v28.2s, v20.2s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e767ed1		saba v17.4h, v22.4h, v22.4h
-#   v17: 0x0000000000000000fffbfdfbfffbfdfb
+#            v17: 0x0000000000000000fffbfdfbfffbfdfb
 0x~~~~~~~~~~~~~~~~  4ebb7cbd		saba v29.4s, v5.4s, v27.4s
-#   v29: 0x000000003a5fb14b75b7d85e58486286
+#            v29: 0x000000003a5fb14b75b7d85e58486286
 0x~~~~~~~~~~~~~~~~  0e327eb4		saba v20.8b, v21.8b, v18.8b
-#   v20: 0x00000000000000001e3d11201e3d1120
+#            v20: 0x00000000000000001e3d11201e3d1120
 0x~~~~~~~~~~~~~~~~  4e7e7e3b		saba v27.8h, v17.8h, v30.8h
-#   v27: 0x000000003a5fb14b0003020300030203
+#            v27: 0x000000003a5fb14b0003020300030203
 0x~~~~~~~~~~~~~~~~  0ea751b4		sabal v20.2d, v13.2s, v7.2s
-#   v20: 0x00000000010001011e3d11201f3d1221
+#            v20: 0x00000000010001011e3d11201f3d1221
 0x~~~~~~~~~~~~~~~~  0e645184		sabal v4.4s, v12.4h, v4.4h
-#    v4: 0x005585f20055c4fc00005a290001058d
+#             v4: 0x005585f20055c4fc00005a290001058d
 0x~~~~~~~~~~~~~~~~  0e345317		sabal v23.8h, v24.8b, v20.8b
-#   v23: 0x001e003d0044003500369d8300430034
+#            v23: 0x001e003d0044003500369d8300430034
 0x~~~~~~~~~~~~~~~~  4eb252ba		sabal2 v26.2d, v21.4s, v18.4s
-#   v26: 0x00000000000000009d2fa76ed8a575fe
+#            v26: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  4e68539b		sabal2 v27.4s, v28.8h, v8.8h
-#   v27: 0x000000003a5fb14b0003020300030203
+#            v27: 0x000000003a5fb14b0003020300030203
 0x~~~~~~~~~~~~~~~~  4e35520c		sabal2 v12.8h, v16.16b, v21.16b
-#   v12: 0x00000000000000002f9d6ea7a5d8fe75
+#            v12: 0x00000000000000002f9d6ea7a5d8fe75
 0x~~~~~~~~~~~~~~~~  4e2d75e0		sabd v0.16b, v15.16b, v13.16b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ebe74ef		sabd v15.2s, v7.2s, v30.2s
-#   v15: 0x00000000000000000100010101000101
+#            v15: 0x00000000000000000100010101000101
 0x~~~~~~~~~~~~~~~~  0e6c7631		sabd v17.4h, v17.4h, v12.4h
-#   v17: 0x00000000000000002fa270ac5a23007a
+#            v17: 0x00000000000000002fa270ac5a23007a
 0x~~~~~~~~~~~~~~~~  4eb67487		sabd v7.4s, v4.4s, v22.4s
-#    v7: 0x633798855327f7af62e26cbc52d33840
+#             v7: 0x633798855327f7af62e26cbc52d33840
 0x~~~~~~~~~~~~~~~~  0e3a7477		sabd v23.8b, v3.8b, v26.8b
-#   v23: 0x0000000000000000632f596e285b7502
+#            v23: 0x0000000000000000632f596e285b7502
 0x~~~~~~~~~~~~~~~~  4e657794		sabd v20.8h, v28.8h, v5.8h
-#   v20: 0x000000000000000075ff275a589162d0
+#            v20: 0x000000000000000075ff275a589162d0
 0x~~~~~~~~~~~~~~~~  0eb472db		sabdl v27.2d, v22.2s, v20.2s
-#   v27: 0x00000000d8e139ed00000000ab639583
+#            v27: 0x00000000d8e139ed00000000ab639583
 0x~~~~~~~~~~~~~~~~  0e77729f		sabdl v31.4s, v20.4h, v23.4h
-#   v31: 0x000012d0000032140000303600001232
+#            v31: 0x000012d0000032140000303600001232
 0x~~~~~~~~~~~~~~~~  0e3b7280		sabdl v0.8h, v20.8b, v27.8b
-#    v0: 0x007500010027005a00ad00d200cd004d
+#             v0: 0x007500010027005a00ad00d200cd004d
 0x~~~~~~~~~~~~~~~~  4ea3717f		sabdl2 v31.2d, v11.4s, v3.4s
-#   v31: 0x00000000000000000000000063106d1d
+#            v31: 0x00000000000000000000000063106d1d
 0x~~~~~~~~~~~~~~~~  4e7b717a		sabdl2 v26.4s, v11.8h, v27.8h
-#   v26: 0x00000000000000000000271f000039ed
+#            v26: 0x00000000000000000000271f000039ed
 0x~~~~~~~~~~~~~~~~  4e327106		sabdl2 v6.8h, v8.16b, v18.16b
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea06b48		sadalp v8.1d, v26.2s
-#    v8: 0x0000000000000000003000000010610c
+#             v8: 0x0000000000000000003000000010610c
 0x~~~~~~~~~~~~~~~~  4ea06b4c		sadalp v12.2d, v26.4s
-#   v12: 0x00000000000000002f9d6ea7a5d95f81
+#            v12: 0x00000000000000002f9d6ea7a5d95f81
 0x~~~~~~~~~~~~~~~~  0e606b4c		sadalp v12.2s, v26.4h
-#   v12: 0x00000000000000002f9d95c6a5d9996e
+#            v12: 0x00000000000000002f9d95c6a5d9996e
 0x~~~~~~~~~~~~~~~~  0e206824		sadalp v4.4h, v1.8b
-#    v4: 0x0000000000000000004759b7004c0607
+#             v4: 0x0000000000000000004759b7004c0607
 0x~~~~~~~~~~~~~~~~  4e606a2f		sadalp v15.4s, v17.8h
-#   v15: 0x00000000000000000100a14f01005b9e
+#            v15: 0x00000000000000000100a14f01005b9e
 0x~~~~~~~~~~~~~~~~  4e206b35		sadalp v21.8h, v25.16b
-#   v21: 0x00000000000000001fc2eedf1fc2eedf
+#            v21: 0x00000000000000001fc2eedf1fc2eedf
 0x~~~~~~~~~~~~~~~~  0eae0145		saddl v5.2d, v10.2s, v14.2s
-#    v5: 0xffffffffd6dfd5daffffffff7687b151
+#             v5: 0xffffffffd6dfd5daffffffff7687b151
 0x~~~~~~~~~~~~~~~~  0e6f0072		saddl v18.4s, v3.4h, v15.4h
-#   v18: 0x00000100ffffa14f0000010000005b9e
+#            v18: 0x00000100ffffa14f0000010000005b9e
 0x~~~~~~~~~~~~~~~~  0e37004f		saddl v15.8h, v2.8b, v23.8b
-#   v15: 0x0063002f0059006e0028005b00750002
+#            v15: 0x0063002f0059006e0028005b00750002
 0x~~~~~~~~~~~~~~~~  4ebb0210		saddl2 v16.2d, v16.4s, v27.4s
-#   v16: 0x0000000000000000ffffffffd8e139ed
+#            v16: 0x0000000000000000ffffffffd8e139ed
 0x~~~~~~~~~~~~~~~~  4e600306		saddl2 v6.4s, v24.8h, v0.8h
-#    v6: 0x0000007500005556000055d1000055af
+#             v6: 0x0000007500005556000055d1000055af
 0x~~~~~~~~~~~~~~~~  4e3c0287		saddl2 v7.8h, v20.16b, v28.16b
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea02b2a		saddlp v10.1d, v25.2s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea02a0f		saddlp v15.2d, v16.4s
-#   v15: 0x0000000000000000ffffffffd8e139ec
+#            v15: 0x0000000000000000ffffffffd8e139ec
 0x~~~~~~~~~~~~~~~~  0e602952		saddlp v18.2s, v10.4h
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e202b5d		saddlp v29.4h, v26.8b
-#   v29: 0x00000000000000000000004600000026
+#            v29: 0x00000000000000000000004600000026
 0x~~~~~~~~~~~~~~~~  4e60282a		saddlp v10.4s, v1.8h
-#   v10: 0x00007574000012640000478e00004b7a
+#            v10: 0x00007574000012640000478e00004b7a
 0x~~~~~~~~~~~~~~~~  4e202aa0		saddlp v0.8h, v21.16b
-#    v0: 0x0000000000000000ffe1ffcdffe1ffcd
+#             v0: 0x0000000000000000ffe1ffcdffe1ffcd
 0x~~~~~~~~~~~~~~~~  4eb038ec		saddlv d12, v7.4s
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e303b8e		saddlv h14, v28.16b
-#   v14: 0x0000000000000000000000000000fff8
+#            v14: 0x0000000000000000000000000000fff8
 0x~~~~~~~~~~~~~~~~  0e303bde		saddlv h30, v30.8b
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e70387b		saddlv s27, v3.4h
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e703a10		saddlv s16, v16.8h
-#   v16: 0x000000000000000000000000000012cc
+#            v16: 0x000000000000000000000000000012cc
 0x~~~~~~~~~~~~~~~~  0eb21178		saddw v24.2d, v11.2d, v18.2s
-#   v24: 0x00000000000000009d2fa76ed8a575fe
+#            v24: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  0e66118d		saddw v13.4s, v12.4s, v6.4h
-#   v13: 0x00000000000055d100000000000055af
+#            v13: 0x00000000000055d100000000000055af
 0x~~~~~~~~~~~~~~~~  0e271273		saddw v19.8h, v19.8h, v7.8b
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eba113b		saddw2 v27.2d, v9.2d, v26.4s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7512f3		saddw2 v19.4s, v23.4s, v21.8h
-#   v19: 0x0000000000000000632f596e285b7502
+#            v19: 0x0000000000000000632f596e285b7502
 0x~~~~~~~~~~~~~~~~  4e3e132f		saddw2 v15.8h, v25.8h, v30.16b
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e290487		shadd v7.16b, v4.16b, v9.16b
-#    v7: 0x000000000000000000232cdb00260303
+#             v7: 0x000000000000000000232cdb00260303
 0x~~~~~~~~~~~~~~~~  0eb8073d		shadd v29.2s, v25.2s, v24.2s
-#   v29: 0x0000000000000000ce97d3b7ec52baff
+#            v29: 0x0000000000000000ce97d3b7ec52baff
 0x~~~~~~~~~~~~~~~~  0e6d055f		shadd v31.4h, v10.4h, v13.4h
-#   v31: 0x0000000000000000000023c700005094
+#            v31: 0x0000000000000000000023c700005094
 0x~~~~~~~~~~~~~~~~  4ea80615		shadd v21.4s, v16.4s, v8.4s
-#   v21: 0x000000000000000000180000000839ec
+#            v21: 0x000000000000000000180000000839ec
 0x~~~~~~~~~~~~~~~~  0e3607ae		shadd v14.8b, v29.8b, v22.8b
-#   v14: 0x0000000000000000b5dae012cc3fc326
+#            v14: 0x0000000000000000b5dae012cc3fc326
 0x~~~~~~~~~~~~~~~~  4e740713		shadd v19.8h, v24.8h, v20.8h
-#   v19: 0x00000000000000000997e764189b6c67
+#            v19: 0x00000000000000000997e764189b6c67
 0x~~~~~~~~~~~~~~~~  5f575736		shl d22, d25, #23
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0f5625		shl v5.16b, v17.16b, #7
-#    v5: 0x00000000000000008000000000800000
+#             v5: 0x00000000000000008000000000800000
 0x~~~~~~~~~~~~~~~~  4f555482		shl v2.2d, v4.2d, #21
-#    v2: 0x000000000000000036e00980c0e00000
+#             v2: 0x000000000000000036e00980c0e00000
 0x~~~~~~~~~~~~~~~~  0f3a5464		shl v4.2s, v3.2s, #26
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f185783		shl v3.4h, v28.4h, #8
-#    v3: 0x0000000000000000ff00ff00ff00ff00
+#             v3: 0x0000000000000000ff00ff00ff00ff00
 0x~~~~~~~~~~~~~~~~  4f3857e4		shl v4.4s, v31.4s, #24
-#    v4: 0x0000000000000000c700000094000000
+#             v4: 0x0000000000000000c700000094000000
 0x~~~~~~~~~~~~~~~~  0f0a5612		shl v18.8b, v16.8b, #2
-#   v18: 0x00000000000000000000000000004830
+#            v18: 0x00000000000000000000000000004830
 0x~~~~~~~~~~~~~~~~  4f135560		shl v0.8h, v11.8h, #3
-#    v0: 0x0000000000000000e9783b70c528aff0
+#             v0: 0x0000000000000000e9783b70c528aff0
 0x~~~~~~~~~~~~~~~~  2ea13b05		shll v5.2d, v24.2s, #32
-#    v5: 0x9d2fa76e00000000d8a575fe00000000
+#             v5: 0x9d2fa76e00000000d8a575fe00000000
 0x~~~~~~~~~~~~~~~~  2e613a9a		shll v26.4s, v20.4h, #16
-#   v26: 0x75ff0000275a00005891000062d00000
+#            v26: 0x75ff0000275a00005891000062d00000
 0x~~~~~~~~~~~~~~~~  2e213925		shll v5.8h, v9.8b, #8
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea13b95		shll2 v21.2d, v28.4s, #32
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e613836		shll2 v22.4s, v1.8h, #16
-#   v22: 0x62e200001292000062e20000af820000
+#            v22: 0x62e200001292000062e20000af820000
 0x~~~~~~~~~~~~~~~~  6e213b3e		shll2 v30.8h, v25.16b, #8
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f248425		shrn v5.2s, v1.2d, #28
-#    v5: 0x00000000000000002e212926700008e4
+#             v5: 0x00000000000000002e212926700008e4
 0x~~~~~~~~~~~~~~~~  0f19865d		shrn v29.4h, v18.4s, #7
-#   v29: 0x00000000000000000000000000000090
+#            v29: 0x00000000000000000000000000000090
 0x~~~~~~~~~~~~~~~~  0f0e87b1		shrn v17.8b, v29.8h, #2
-#   v17: 0x00000000000000000000000000000024
+#            v17: 0x00000000000000000000000000000024
 0x~~~~~~~~~~~~~~~~  4f0d87c5		shrn2 v5.16b, v30.8h, #3
-#    v5: 0x00000000000000002e212926700008e4
+#             v5: 0x00000000000000002e212926700008e4
 0x~~~~~~~~~~~~~~~~  4f3f8438		shrn2 v24.4s, v1.2d, #1
-#   v24: 0x317157c12580003d9d2fa76ed8a575fe
+#            v24: 0x317157c12580003d9d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  4f1085c5		shrn2 v5.8h, v14.4s, #16
-#    v5: 0x00000000b5dacc3f2e212926700008e4
+#             v5: 0x00000000b5dacc3f2e212926700008e4
 0x~~~~~~~~~~~~~~~~  4e3726de		shsub v30.16b, v22.16b, v23.16b
-#   v30: 0x31f1000009c90000ffd9d3c9c393c5ff
+#            v30: 0x31f1000009c90000ffd9d3c9c393c5ff
 0x~~~~~~~~~~~~~~~~  0eb92776		shsub v22.2s, v27.2s, v25.2s
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6126cd		shsub v13.4h, v22.4h, v1.4h
-#   v13: 0x0000000000000000dc80ffb9da80ffc3
+#            v13: 0x0000000000000000dc80ffb9da80ffc3
 0x~~~~~~~~~~~~~~~~  4eb7250a		shsub v10.4s, v8.4s, v23.4s
-#   v10: 0x0000000000000000ce805349ebda7605
+#            v10: 0x0000000000000000ce805349ebda7605
 0x~~~~~~~~~~~~~~~~  0e3f2526		shsub v6.8b, v9.8b, v31.8b
-#    v6: 0x00000000000000000000ee1c0000d836
+#             v6: 0x00000000000000000000ee1c0000d836
 0x~~~~~~~~~~~~~~~~  4e6827e8		shsub v8.8h, v31.8h, v8.8h
-#    v8: 0x0000000000000000ffe811e3fff8f7c4
+#             v8: 0x0000000000000000ffe811e3fff8f7c4
 0x~~~~~~~~~~~~~~~~  7f5457b3		sli d19, d29, #20
-#   v19: 0x000000000000000000000000090b6c67
+#            v19: 0x000000000000000000000000090b6c67
 0x~~~~~~~~~~~~~~~~  6f085709		sli v9.16b, v24.16b, #0
-#    v9: 0x317157c12580003d9d2fa76ed8a575fe
+#             v9: 0x317157c12580003d9d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  6f4a5536		sli v22.2d, v9.2d, #10
-#   v22: 0xc55f04960000f400be9dbb6295d7f800
+#            v22: 0xc55f04960000f400be9dbb6295d7f800
 0x~~~~~~~~~~~~~~~~  2f34576b		sli v11.2s, v27.2s, #20
-#   v11: 0x0000000000000000000fa76e000575fe
+#            v11: 0x0000000000000000000fa76e000575fe
 0x~~~~~~~~~~~~~~~~  2f1555f0		sli v16.4h, v15.4h, #5
-#   v16: 0x0000000000000000000000000000000c
+#            v16: 0x0000000000000000000000000000000c
 0x~~~~~~~~~~~~~~~~  6f395508		sli v8.4s, v8.4s, #25
-#    v8: 0x0000000000000000c7e811e389f8f7c4
+#             v8: 0x0000000000000000c7e811e389f8f7c4
 0x~~~~~~~~~~~~~~~~  2f0857ca		sli v10.8b, v30.8b, #0
-#   v10: 0x0000000000000000ffd9d3c9c393c5ff
+#            v10: 0x0000000000000000ffd9d3c9c393c5ff
 0x~~~~~~~~~~~~~~~~  6f165787		sli v7.8h, v28.8h, #6
-#    v7: 0x0000000000000000ffe3ffdbffe6ffc3
+#             v7: 0x0000000000000000ffe3ffdbffe6ffc3
 0x~~~~~~~~~~~~~~~~  4e216512		smax v18.16b, v8.16b, v1.16b
-#   v18: 0x6200120062000000470011e34b00007a
+#            v18: 0x6200120062000000470011e34b00007a
 0x~~~~~~~~~~~~~~~~  0ea164be		smax v30.2s, v5.2s, v1.2s
-#   v30: 0x00000000000000004700008e700008e4
+#            v30: 0x00000000000000004700008e700008e4
 0x~~~~~~~~~~~~~~~~  0e736731		smax v17.4h, v25.4h, v19.4h
-#   v17: 0x000000000000000000000000090b6c67
+#            v17: 0x000000000000000000000000090b6c67
 0x~~~~~~~~~~~~~~~~  4ebf6701		smax v1.4s, v24.4s, v31.4s
-#    v1: 0x317157c12580003d000023c700005094
+#             v1: 0x317157c12580003d000023c700005094
 0x~~~~~~~~~~~~~~~~  0e386711		smax v17.8b, v24.8b, v24.8b
-#   v17: 0x00000000000000009d2fa76ed8a575fe
+#            v17: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  4e6a674b		smax v11.8h, v26.8h, v10.8h
-#   v11: 0x75ff0000275a00005891000062d00000
+#            v11: 0x75ff0000275a00005891000062d00000
 0x~~~~~~~~~~~~~~~~  4e27a5cc		smaxp v12.16b, v14.16b, v7.16b
-#   v12: 0x00000000ffffffff00000000da123f26
+#            v12: 0x00000000ffffffff00000000da123f26
 0x~~~~~~~~~~~~~~~~  0ea6a71f		smaxp v31.2s, v24.2s, v6.2s
-#   v31: 0x00000000000000000000ee1cd8a575fe
+#            v31: 0x00000000000000000000ee1cd8a575fe
 0x~~~~~~~~~~~~~~~~  0e6aa7aa		smaxp v10.4h, v29.4h, v10.4h
-#   v10: 0x0000000000000000ffd9c5ff00000090
+#            v10: 0x0000000000000000ffd9c5ff00000090
 0x~~~~~~~~~~~~~~~~  4ea7a572		smaxp v18.4s, v11.4s, v7.4s
-#   v18: 0x00000000ffe6ffc375ff000062d00000
+#            v18: 0x00000000ffe6ffc375ff000062d00000
 0x~~~~~~~~~~~~~~~~  0e32a415		smaxp v21.8b, v0.8b, v18.8b
-#   v21: 0x000000000000000075006200787028f0
+#            v21: 0x000000000000000075006200787028f0
 0x~~~~~~~~~~~~~~~~  4e6fa51a		smaxp v26.8h, v8.8h, v15.8h
-#   v26: 0x00000000000000000000000011e3f7c4
+#            v26: 0x00000000000000000000000011e3f7c4
 0x~~~~~~~~~~~~~~~~  4e30a8a4		smaxv b4, v5.16b
-#    v4: 0x00000000000000000000000000000070
+#             v4: 0x00000000000000000000000000000070
 0x~~~~~~~~~~~~~~~~  0e30a817		smaxv b23, v0.8b
-#   v23: 0x00000000000000000000000000000078
+#            v23: 0x00000000000000000000000000000078
 0x~~~~~~~~~~~~~~~~  0e70a806		smaxv h6, v0.4h
-#    v6: 0x00000000000000000000000000003b70
+#             v6: 0x00000000000000000000000000003b70
 0x~~~~~~~~~~~~~~~~  4e70a918		smaxv h24, v8.8h
-#   v24: 0x000000000000000000000000000011e3
+#            v24: 0x000000000000000000000000000011e3
 0x~~~~~~~~~~~~~~~~  4eb0aa03		smaxv s3, v16.4s
-#    v3: 0x0000000000000000000000000000000c
+#             v3: 0x0000000000000000000000000000000c
 0x~~~~~~~~~~~~~~~~  4e326d18		smin v24.16b, v8.16b, v18.16b
-#   v24: 0x00000000ffe6ffc3c7e800e389d0f7c4
+#            v24: 0x00000000ffe6ffc3c7e800e389d0f7c4
 0x~~~~~~~~~~~~~~~~  0eb76d1d		smin v29.2s, v8.2s, v23.2s
-#   v29: 0x0000000000000000c7e811e389f8f7c4
+#            v29: 0x0000000000000000c7e811e389f8f7c4
 0x~~~~~~~~~~~~~~~~  0e756d66		smin v6.4h, v11.4h, v21.4h
-#    v6: 0x00000000000000005891000062d00000
+#             v6: 0x00000000000000005891000062d00000
 0x~~~~~~~~~~~~~~~~  4eaf6ef8		smin v24.4s, v23.4s, v15.4s
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e246e08		smin v8.8b, v16.8b, v4.8b
-#    v8: 0x0000000000000000000000000000000c
+#             v8: 0x0000000000000000000000000000000c
 0x~~~~~~~~~~~~~~~~  4e6a6c2c		smin v12.8h, v1.8h, v10.8h
-#   v12: 0x0000000000000000ffd9c5ff00000090
+#            v12: 0x0000000000000000ffd9c5ff00000090
 0x~~~~~~~~~~~~~~~~  4e3cae4d		sminp v13.16b, v18.16b, v28.16b
-#   v13: 0x00000000ffffffff0000e6c3ff00d000
+#            v13: 0x00000000ffffffff0000e6c3ff00d000
 0x~~~~~~~~~~~~~~~~  0eb0af96		sminp v22.2s, v28.2s, v16.2s
-#   v22: 0x000000000000000000000000ffffffff
+#            v22: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  0e65ad8f		sminp v15.4h, v12.4h, v5.4h
-#   v15: 0x0000000000000000292608e4c5ff0000
+#            v15: 0x0000000000000000292608e4c5ff0000
 0x~~~~~~~~~~~~~~~~  4ea8ae2f		sminp v15.4s, v17.4s, v8.4s
-#   v15: 0x0000000000000000000000009d2fa76e
+#            v15: 0x0000000000000000000000009d2fa76e
 0x~~~~~~~~~~~~~~~~  0e26ac55		sminp v21.8b, v2.8b, v6.8b
-#   v21: 0x00000000000000009100d000e080c000
+#            v21: 0x00000000000000009100d000e080c000
 0x~~~~~~~~~~~~~~~~  4e66ad95		sminp v21.8h, v12.8h, v6.8h
-#   v21: 0x000000000000000000000000c5ff0000
+#            v21: 0x000000000000000000000000c5ff0000
 0x~~~~~~~~~~~~~~~~  4e31a8c8		sminv b8, v6.16b
-#    v8: 0x00000000000000000000000000000091
+#             v8: 0x00000000000000000000000000000091
 0x~~~~~~~~~~~~~~~~  0e31aa46		sminv b6, v18.8b
-#    v6: 0x000000000000000000000000000000d0
+#             v6: 0x000000000000000000000000000000d0
 0x~~~~~~~~~~~~~~~~  0e71a834		sminv h20, v1.4h
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e71aa27		sminv h7, v17.8h
-#    v7: 0x00000000000000000000000000009d2f
+#             v7: 0x00000000000000000000000000009d2f
 0x~~~~~~~~~~~~~~~~  4eb1a895		sminv s21, v4.4s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eb581d8		smlal v24.2d, v14.2s, v21.2s
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f8e287f		smlal v31.2d, v3.2s, v14.s[2]
-#   v31: 0x00000000000000000000ee1cd8a575fe
+#            v31: 0x00000000000000000000ee1cd8a575fe
 0x~~~~~~~~~~~~~~~~  0e758287		smlal v7.4s, v20.4h, v21.4h
-#    v7: 0x00000000000000000000000000009d2f
+#             v7: 0x00000000000000000000000000009d2f
 0x~~~~~~~~~~~~~~~~  0f792213		smlal v19.4s, v16.4h, v9.h[3]
-#   v19: 0x0000000000000000000000000906ca9b
+#            v19: 0x0000000000000000000000000906ca9b
 0x~~~~~~~~~~~~~~~~  0e2181dd		smlal v29.8h, v14.8b, v1.8b
-#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+#            v29: 0x00000000fba0fbfec7e811e376e8e7bc
 0x~~~~~~~~~~~~~~~~  4eb0835e		smlal2 v30.2d, v26.4s, v16.4s
-#   v30: 0x00000000000000004700008e700008e4
+#            v30: 0x00000000000000004700008e700008e4
 0x~~~~~~~~~~~~~~~~  4f8123df		smlal2 v31.2d, v30.4s, v1.s[0]
-#   v31: 0x00000000000000000000ee1cd8a575fe
+#            v31: 0x00000000000000000000ee1cd8a575fe
 0x~~~~~~~~~~~~~~~~  4e6380d1		smlal2 v17.4s, v6.8h, v3.8h
-#   v17: 0x00000000000000009d2fa76ed8a575fe
+#            v17: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  4f752beb		smlal2 v11.4s, v31.8h, v5.h[7]
-#   v11: 0x75ff0000275a00005891000062d00000
+#            v11: 0x75ff0000275a00005891000062d00000
 0x~~~~~~~~~~~~~~~~  4e3d821e		smlal2 v30.8h, v16.16b, v29.16b
-#   v30: 0x00000000000000004700008e700008e4
+#            v30: 0x00000000000000004700008e700008e4
 0x~~~~~~~~~~~~~~~~  0eb1a281		smlsl v1.2d, v20.2s, v17.2s
-#    v1: 0x317157c12580003d000023c700005094
+#             v1: 0x317157c12580003d000023c700005094
 0x~~~~~~~~~~~~~~~~  0fa5699d		smlsl v29.2d, v12.2s, v5.s[3]
-#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+#            v29: 0x00000000fba0fbfec7e811e376e8e7bc
 0x~~~~~~~~~~~~~~~~  0e61a340		smlsl v0.4s, v26.4h, v1.4h
-#    v0: 0x0000000000000000e9783b70c7c032a0
+#             v0: 0x0000000000000000e9783b70c7c032a0
 0x~~~~~~~~~~~~~~~~  0f5668a3		smlsl v3.4s, v5.4h, v6.h[5]
-#    v3: 0x0000000000000000000000000000000c
+#             v3: 0x0000000000000000000000000000000c
 0x~~~~~~~~~~~~~~~~  0e3aa004		smlsl v4.8h, v0.8b, v26.8b
-#    v4: 0x000000000000000003c9f8c001c2e9f0
+#             v4: 0x000000000000000003c9f8c001c2e9f0
 0x~~~~~~~~~~~~~~~~  4ea5a1ce		smlsl2 v14.2d, v14.4s, v5.4s
-#   v14: 0x0000000000000000b5dae012cc3fc326
+#            v14: 0x0000000000000000b5dae012cc3fc326
 0x~~~~~~~~~~~~~~~~  4fa060af		smlsl2 v15.2d, v5.4s, v0.s[1]
-#   v15: 0x0000000000000000f9797b018bdbc6de
+#            v15: 0x0000000000000000f9797b018bdbc6de
 0x~~~~~~~~~~~~~~~~  4e7fa23d		smlsl2 v29.4s, v17.8h, v31.8h
-#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+#            v29: 0x00000000fba0fbfec7e811e376e8e7bc
 0x~~~~~~~~~~~~~~~~  4f6969e6		smlsl2 v6.4s, v15.8h, v9.h[6]
-#    v6: 0x000000000000000000000000000000d0
+#             v6: 0x000000000000000000000000000000d0
 0x~~~~~~~~~~~~~~~~  4e2fa1fe		smlsl2 v30.8h, v15.16b, v15.16b
-#   v30: 0x00000000000000004700008e700008e4
+#            v30: 0x00000000000000004700008e700008e4
 0x~~~~~~~~~~~~~~~~  0e072cd5		smov w21, v6.b[3]
-#   x21: 0x0000000000000000
+#            w21:         0x00000000
 0x~~~~~~~~~~~~~~~~  0e1e2f4d		smov w13, v26.h[7]
-#   x13: 0x0000000000000000
+#            w13:         0x00000000
 0x~~~~~~~~~~~~~~~~  4e0f2e18		smov x24, v16.b[7]
-#   x24: 0x0000000000000000
+#            x24: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  4e0e2c87		smov x7, v4.h[3]
-#    x7: 0x00000000000003c9
+#             x7: 0x00000000000003c9
 0x~~~~~~~~~~~~~~~~  4e0c2cfd		smov x29, v7.s[1]
-#   x29: 0x0000000000000000
+#            x29: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  0eb1c3a4		smull v4.2d, v29.2s, v17.2s
-#    v4: 0x15a6d000c90fc48aedb876b6692ad888
+#             v4: 0x15a6d000c90fc48aedb876b6692ad888
 0x~~~~~~~~~~~~~~~~  0f86aabe		smull v30.2d, v21.2s, v6.s[2]
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e77c0b7		smull v23.4s, v5.4h, v23.4h
-#   v23: 0x00000000000000000000000000042ae0
+#            v23: 0x00000000000000000000000000042ae0
 0x~~~~~~~~~~~~~~~~  0f52a128		smull v8.4s, v9.4h, v2.h[1]
-#    v8: 0x185dc92015d7004009b45060e2e7be40
+#             v8: 0x185dc92015d7004009b45060e2e7be40
 0x~~~~~~~~~~~~~~~~  0e21c23f		smull v31.8h, v17.8b, v1.8b
-#   v31: 0x00000000f3d5e78200000000249000d8
+#            v31: 0x00000000f3d5e78200000000249000d8
 0x~~~~~~~~~~~~~~~~  4eb7c063		smull2 v3.2d, v3.4s, v23.4s
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4fa6a3af		smull2 v15.2d, v29.4s, v6.s[1]
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7ec293		smull2 v19.4s, v20.8h, v30.8h
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f47a946		smull2 v6.4s, v10.8h, v7.h[4]
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e3bc119		smull2 v25.8h, v8.16b, v27.16b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e2079e3		sqabs b3, b15
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0792e		sqabs d14, d9
-#   v14: 0x000000000000000062d05891275a8a02
+#            v14: 0x000000000000000062d05891275a8a02
 0x~~~~~~~~~~~~~~~~  5e607b9f		sqabs h31, h28
-#   v31: 0x00000000000000000000000000000001
+#            v31: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  5ea07808		sqabs s8, s0
-#    v8: 0x000000000000000000000000383fcd60
+#             v8: 0x000000000000000000000000383fcd60
 0x~~~~~~~~~~~~~~~~  4e2078ee		sqabs v14.16b, v7.16b
-#   v14: 0x0000000000000000000000000000632f
+#            v14: 0x0000000000000000000000000000632f
 0x~~~~~~~~~~~~~~~~  4ee07a77		sqabs v23.2d, v19.2d
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea07b0a		sqabs v10.2s, v24.2s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e607a7f		sqabs v31.4h, v19.4h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea07817		sqabs v23.4s, v0.4s
-#   v23: 0x00000000000000001687c490383fcd60
+#            v23: 0x00000000000000001687c490383fcd60
 0x~~~~~~~~~~~~~~~~  0e207afd		sqabs v29.8b, v23.8b
-#   v29: 0x000000000000000016793c70383f3360
+#            v29: 0x000000000000000016793c70383f3360
 0x~~~~~~~~~~~~~~~~  4e607ab1		sqabs v17.8h, v21.8h
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e2d0ee9		sqadd b9, b23, b13
-#    v9: 0x00000000000000000000000000000060
+#             v9: 0x00000000000000000000000000000060
 0x~~~~~~~~~~~~~~~~  5efa0f22		sqadd d2, d25, d26
-#    v2: 0x00000000000000000000000011e3f7c4
+#             v2: 0x00000000000000000000000011e3f7c4
 0x~~~~~~~~~~~~~~~~  5e790fa7		sqadd h7, h29, h25
-#    v7: 0x00000000000000000000000000003360
+#             v7: 0x00000000000000000000000000003360
 0x~~~~~~~~~~~~~~~~  5eb80ceb		sqadd s11, s7, s24
-#   v11: 0x00000000000000000000000000003360
+#            v11: 0x00000000000000000000000000003360
 0x~~~~~~~~~~~~~~~~  4e3d0e14		sqadd v20.16b, v16.16b, v29.16b
-#   v20: 0x000000000000000016793c70383f336c
+#            v20: 0x000000000000000016793c70383f336c
 0x~~~~~~~~~~~~~~~~  4efc0fd7		sqadd v23.2d, v30.2d, v28.2d
-#   v23: 0x0000000000000000ffffffffffffffff
+#            v23: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0ea20e68		sqadd v8.2s, v19.2s, v2.2s
-#    v8: 0x00000000000000000000000011e3f7c4
+#             v8: 0x00000000000000000000000011e3f7c4
 0x~~~~~~~~~~~~~~~~  0e7f0d94		sqadd v20.4h, v12.4h, v31.4h
-#   v20: 0x0000000000000000ffd9c5ff00000090
+#            v20: 0x0000000000000000ffd9c5ff00000090
 0x~~~~~~~~~~~~~~~~  4eb10dee		sqadd v14.4s, v15.4s, v17.4s
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e2d0fa2		sqadd v2.8b, v29.8b, v13.8b
-#    v2: 0x000000000000000016792233373f0360
+#             v2: 0x000000000000000016792233373f0360
 0x~~~~~~~~~~~~~~~~  4e6e0e67		sqadd v7.8h, v19.8h, v14.8h
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ebe90af		sqdmlal d15, s5, s30
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5fa23958		sqdmlal d24, s10, v2.s[3]
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e689269		sqdmlal s9, h19, h8
-#    v9: 0x00000000000000000000000000000060
+#             v9: 0x00000000000000000000000000000060
 0x~~~~~~~~~~~~~~~~  5f7c302e		sqdmlal s14, h1, v12.h[3]
-#   v14: 0x000000000000000000000000ffe772e8
+#            v14: 0x000000000000000000000000ffe772e8
 0x~~~~~~~~~~~~~~~~  0ebf90be		sqdmlal v30.2d, v5.2s, v31.2s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0faa31d9		sqdmlal v25.2d, v14.2s, v10.s[1]
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e709233		sqdmlal v19.4s, v17.4h, v16.4h
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f5830a8		sqdmlal v8.4s, v5.4h, v8.h[1]
-#    v8: 0x0672308605c005640fa6a0001322041c
+#             v8: 0x0672308605c005640fa6a0001322041c
 0x~~~~~~~~~~~~~~~~  4ea392e1		sqdmlal2 v1.2d, v23.4s, v3.4s
-#    v1: 0x317157c12580003d000023c700005094
+#             v1: 0x317157c12580003d000023c700005094
 0x~~~~~~~~~~~~~~~~  4f893013		sqdmlal2 v19.2d, v0.4s, v9.s[0]
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6b92da		sqdmlal2 v26.4s, v22.8h, v11.8h
-#   v26: 0x00000000000000000000000011e3f7c4
+#            v26: 0x00000000000000000000000011e3f7c4
 0x~~~~~~~~~~~~~~~~  4f4d3b86		sqdmlal2 v6.4s, v28.8h, v13.h[4]
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5eb4b3aa		sqdmlsl d10, s29, s20
-#   v10: 0x0000000000000000ffffffc0b8e63400
+#            v10: 0x0000000000000000ffffffc0b8e63400
 0x~~~~~~~~~~~~~~~~  5faa712a		sqdmlsl d10, s9, v10.s[1]
-#   v10: 0x0000000000000000ffffffc0b8e66400
+#            v10: 0x0000000000000000ffffffc0b8e66400
 0x~~~~~~~~~~~~~~~~  5e78b13e		sqdmlsl s30, h9, h24
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f56730d		sqdmlsl s13, h24, v6.h[1]
-#   v13: 0x000000000000000000000000ff00d000
+#            v13: 0x000000000000000000000000ff00d000
 0x~~~~~~~~~~~~~~~~  0eb4b15b		sqdmlsl v27.2d, v10.2s, v20.2s
-#   v27: 0xffffffffece2ff800000004ffccf8000
+#            v27: 0xffffffffece2ff800000004ffccf8000
 0x~~~~~~~~~~~~~~~~  0fa37af7		sqdmlsl v23.2d, v23.2s, v3.s[3]
-#   v23: 0x0000000000000000ffffffffffffffff
+#            v23: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0e7db227		sqdmlsl v7.4s, v17.4h, v29.4h
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f437ab6		sqdmlsl v22.4s, v21.4h, v3.h[4]
-#   v22: 0x000000000000000000000000ffffffff
+#            v22: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  4eb6b0ec		sqdmlsl2 v12.2d, v7.4s, v22.4s
-#   v12: 0x0000000000000000ffd9c5ff00000090
+#            v12: 0x0000000000000000ffd9c5ff00000090
 0x~~~~~~~~~~~~~~~~  4f887334		sqdmlsl2 v20.2d, v25.4s, v8.s[0]
-#   v20: 0x0000000000000000ffd9c5ff00000090
+#            v20: 0x0000000000000000ffd9c5ff00000090
 0x~~~~~~~~~~~~~~~~  4e72b359		sqdmlsl2 v25.4s, v26.8h, v18.8h
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f457279		sqdmlsl2 v25.4s, v19.8h, v5.h[0]
-#   v25: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  5e6cb771		sqdmulh h17, h27, h12
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 0x~~~~~~~~~~~~~~~~  5eb0b661		sqdmulh s1, s19, s16
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 0x~~~~~~~~~~~~~~~~  5f82c201		sqdmulh s1, s16, v2.s[0]
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 0x~~~~~~~~~~~~~~~~  0ea8b43c		sqdmulh v28.2s, v1.2s, v8.2s
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 0x~~~~~~~~~~~~~~~~  0f83c11c		sqdmulh v28.2s, v8.2s, v3.s[0]
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 0x~~~~~~~~~~~~~~~~  0e65b72b		sqdmulh v11.4h, v25.4h, v5.4h
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 0x~~~~~~~~~~~~~~~~  0f58c9de		sqdmulh v30.4h, v14.4h, v8.h[5]
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 0x~~~~~~~~~~~~~~~~  4eadb6b9		sqdmulh v25.4s, v21.4s, v13.4s
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 0x~~~~~~~~~~~~~~~~  4faac857		sqdmulh v23.4s, v2.4s, v10.s[3]
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 0x~~~~~~~~~~~~~~~~  4e77b4ba		sqdmulh v26.8h, v5.8h, v23.8h
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 0x~~~~~~~~~~~~~~~~  4f74c2c4		sqdmulh v4.8h, v22.8h, v4.h[3]
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 0x~~~~~~~~~~~~~~~~  5ebad059		sqdmull d25, s2, s26
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 0x~~~~~~~~~~~~~~~~  5fa5b1de		sqdmull d30, s14, v5.s[1]
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 0x~~~~~~~~~~~~~~~~  5e6bd25d		sqdmull s29, h18, h11
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 0x~~~~~~~~~~~~~~~~  5f67b9ab		sqdmull s11, h13, v7.h[6]
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 0x~~~~~~~~~~~~~~~~  0ea8d137		sqdmull v23.2d, v9.2s, v8.2s
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 0x~~~~~~~~~~~~~~~~  0fa4b3b2		sqdmull v18.2d, v29.2s, v4.s[1]
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 0x~~~~~~~~~~~~~~~~  0e67d311		sqdmull v17.4s, v24.4h, v7.4h
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 0x~~~~~~~~~~~~~~~~  0f55b1e8		sqdmull v8.4s, v15.4h, v5.h[1]
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 0x~~~~~~~~~~~~~~~~  4ea2d1dc		sqdmull2 v28.2d, v14.4s, v2.4s
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 0x~~~~~~~~~~~~~~~~  4f8dbb01		sqdmull2 v1.2d, v24.4s, v13.s[2]
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 0x~~~~~~~~~~~~~~~~  4e7fd22b		sqdmull2 v11.4s, v17.8h, v31.8h
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 0x~~~~~~~~~~~~~~~~  4f7bb281		sqdmull2 v1.4s, v20.8h, v11.h[3]
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 0x~~~~~~~~~~~~~~~~  7e207802		sqneg b2, b0
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 0x~~~~~~~~~~~~~~~~  7ee07858		sqneg d24, d2
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 0x~~~~~~~~~~~~~~~~  7e60787d		sqneg h29, h3
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 0x~~~~~~~~~~~~~~~~  7ea07924		sqneg s4, s9
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 0x~~~~~~~~~~~~~~~~  6e207bae		sqneg v14.16b, v29.16b
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 0x~~~~~~~~~~~~~~~~  6ee0799e		sqneg v30.2d, v12.2d
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 0x~~~~~~~~~~~~~~~~  2ea07b5c		sqneg v28.2s, v26.2s
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 0x~~~~~~~~~~~~~~~~  2e607884		sqneg v4.4h, v4.4h
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 0x~~~~~~~~~~~~~~~~  6ea07909		sqneg v9.4s, v8.4s
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 0x~~~~~~~~~~~~~~~~  2e207a94		sqneg v20.8b, v20.8b
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 0x~~~~~~~~~~~~~~~~  6e60795b		sqneg v27.8h, v10.8h
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 0x~~~~~~~~~~~~~~~~  7e60b707		sqrdmulh h7, h24, h0
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 0x~~~~~~~~~~~~~~~~  5f64d86e		sqrdmulh h14, h3, v4.h[6]
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 0x~~~~~~~~~~~~~~~~  7eb8b67b		sqrdmulh s27, s19, s24
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 0x~~~~~~~~~~~~~~~~  5f84d2bf		sqrdmulh s31, s21, v4.s[0]
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 0x~~~~~~~~~~~~~~~~  2ea1b732		sqrdmulh v18.2s, v25.2s, v1.2s
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 0x~~~~~~~~~~~~~~~~  0f8dd0b6		sqrdmulh v22.2s, v5.2s, v13.s[0]
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 0x~~~~~~~~~~~~~~~~  2e69b716		sqrdmulh v22.4h, v24.4h, v9.4h
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 0x~~~~~~~~~~~~~~~~  0f6cd84d		sqrdmulh v13.4h, v2.4h, v12.h[6]
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 0x~~~~~~~~~~~~~~~~  6ea2b769		sqrdmulh v9.4s, v27.4s, v2.4s
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 0x~~~~~~~~~~~~~~~~  4fa7d2e3		sqrdmulh v3.4s, v23.4s, v7.s[1]
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 0x~~~~~~~~~~~~~~~~  6e67b402		sqrdmulh v2.8h, v0.8h, v7.8h
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 0x~~~~~~~~~~~~~~~~  4f68d130		sqrdmulh v16.8h, v9.8h, v8.h[2]
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 0x~~~~~~~~~~~~~~~~  5e2d5ea8		sqrshl b8, b21, b13
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 0x~~~~~~~~~~~~~~~~  5ef45cfd		sqrshl d29, d7, d20
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 0x~~~~~~~~~~~~~~~~  5e6a5ddc		sqrshl h28, h14, h10
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 0x~~~~~~~~~~~~~~~~  5ea25e5a		sqrshl s26, s18, s2
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 0x~~~~~~~~~~~~~~~~  4e3a5ff2		sqrshl v18.16b, v31.16b, v26.16b
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 0x~~~~~~~~~~~~~~~~  4ee05c9c		sqrshl v28.2d, v4.2d, v0.2d
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 0x~~~~~~~~~~~~~~~~  0ea05cc3		sqrshl v3.2s, v6.2s, v0.2s
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 0x~~~~~~~~~~~~~~~~  0e765e41		sqrshl v1.4h, v18.4h, v22.4h
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 0x~~~~~~~~~~~~~~~~  4ea75f30		sqrshl v16.4s, v25.4s, v7.4s
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 0x~~~~~~~~~~~~~~~~  0e255ea0		sqrshl v0.8b, v21.8b, v5.8b
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 0x~~~~~~~~~~~~~~~~  4e685e7e		sqrshl v30.8h, v19.8h, v8.8h
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 0x~~~~~~~~~~~~~~~~  5f0c9ea6		sqrshrn b6, h21, #4
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 0x~~~~~~~~~~~~~~~~  5f159e2e		sqrshrn h14, s17, #11
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 0x~~~~~~~~~~~~~~~~  5f369f79		sqrshrn s25, d27, #10
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 0x~~~~~~~~~~~~~~~~  0f2e9da6		sqrshrn v6.2s, v13.2d, #18
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 0x~~~~~~~~~~~~~~~~  0f119d25		sqrshrn v5.4h, v9.4s, #15
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 0x~~~~~~~~~~~~~~~~  0f0f9d93		sqrshrn v19.8b, v12.8h, #1
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 0x~~~~~~~~~~~~~~~~  4f099eb3		sqrshrn2 v19.16b, v21.8h, #7
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 0x~~~~~~~~~~~~~~~~  4f339f1d		sqrshrn2 v29.4s, v24.2d, #13
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 0x~~~~~~~~~~~~~~~~  4f169c4c		sqrshrn2 v12.8h, v2.4s, #10
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 0x~~~~~~~~~~~~~~~~  7f0b8d30		sqrshrun b16, h9, #5
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 0x~~~~~~~~~~~~~~~~  7f118f03		sqrshrun h3, s24, #15
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 0x~~~~~~~~~~~~~~~~  7f388e50		sqrshrun s16, d18, #8
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 0x~~~~~~~~~~~~~~~~  2f388efc		sqrshrun v28.2s, v23.2d, #8
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 0x~~~~~~~~~~~~~~~~  2f168f3f		sqrshrun v31.4h, v25.4s, #10
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 0x~~~~~~~~~~~~~~~~  2f0e8ef3		sqrshrun v19.8b, v23.8h, #2
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 0x~~~~~~~~~~~~~~~~  6f088c18		sqrshrun2 v24.16b, v0.8h, #8
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 0x~~~~~~~~~~~~~~~~  6f298c36		sqrshrun2 v22.4s, v1.2d, #23
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 0x~~~~~~~~~~~~~~~~  6f138ebc		sqrshrun2 v28.8h, v21.4s, #13
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 0x~~~~~~~~~~~~~~~~  5ee44c1d		sqshl d29, d0, d4
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 0x~~~~~~~~~~~~~~~~  5f6374f5		sqshl d21, d7, #35
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 0x~~~~~~~~~~~~~~~~  5e714f34		sqshl h20, h25, h17
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 0x~~~~~~~~~~~~~~~~  5f187414		sqshl h20, h0, #8
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 0x~~~~~~~~~~~~~~~~  5ea44dbd		sqshl s29, s13, s4
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 0x~~~~~~~~~~~~~~~~  5f34756a		sqshl s10, s11, #20
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 0x~~~~~~~~~~~~~~~~  4e3c4e48		sqshl v8.16b, v18.16b, v28.16b
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 0x~~~~~~~~~~~~~~~~  4f0a77bd		sqshl v29.16b, v29.16b, #2
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 0x~~~~~~~~~~~~~~~~  4ef04fe8		sqshl v8.2d, v31.2d, v16.2d
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 0x~~~~~~~~~~~~~~~~  4f6575c7		sqshl v7.2d, v14.2d, #37
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 0x~~~~~~~~~~~~~~~~  0ea74f40		sqshl v0.2s, v26.2s, v7.2s
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 0x~~~~~~~~~~~~~~~~  0f337565		sqshl v5.2s, v11.2s, #19
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 0x~~~~~~~~~~~~~~~~  0e604fcb		sqshl v11.4h, v30.4h, v0.4h
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 0x~~~~~~~~~~~~~~~~  0f177641		sqshl v1.4h, v18.4h, #7
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 0x~~~~~~~~~~~~~~~~  4ebe4c76		sqshl v22.4s, v3.4s, v30.4s
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 0x~~~~~~~~~~~~~~~~  4f3c75f0		sqshl v16.4s, v15.4s, #28
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 0x~~~~~~~~~~~~~~~~  0e394f86		sqshl v6.8b, v28.8b, v25.8b
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 0x~~~~~~~~~~~~~~~~  0f0875e0		sqshl v0.8b, v15.8b, #0
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 0x~~~~~~~~~~~~~~~~  4e7e4e06		sqshl v6.8h, v16.8h, v30.8h
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 0x~~~~~~~~~~~~~~~~  4f1e7683		sqshl v3.8h, v20.8h, #14
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 0x~~~~~~~~~~~~~~~~  7f0e65cd		sqshlu b13, b14, #6
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 0x~~~~~~~~~~~~~~~~  7f6c6600		sqshlu d0, d16, #44
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 0x~~~~~~~~~~~~~~~~  7f1f67a5		sqshlu h5, h29, #15
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 0x~~~~~~~~~~~~~~~~  7f2d651d		sqshlu s29, s8, #13
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 0x~~~~~~~~~~~~~~~~  6f0a669b		sqshlu v27.16b, v20.16b, #2
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 0x~~~~~~~~~~~~~~~~  6f4b6598		sqshlu v24.2d, v12.2d, #11
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 0x~~~~~~~~~~~~~~~~  2f36666c		sqshlu v12.2s, v19.2s, #22
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 0x~~~~~~~~~~~~~~~~  2f1b6588		sqshlu v8.4h, v12.4h, #11
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 0x~~~~~~~~~~~~~~~~  6f286472		sqshlu v18.4s, v3.4s, #8
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 0x~~~~~~~~~~~~~~~~  2f096543		sqshlu v3.8b, v10.8b, #1
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 0x~~~~~~~~~~~~~~~~  6f14671e		sqshlu v30.8h, v24.8h, #4
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 0x~~~~~~~~~~~~~~~~  5f0f9781		sqshrn b1, h28, #1
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 0x~~~~~~~~~~~~~~~~  5f1694ff		sqshrn h31, s7, #10
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 0x~~~~~~~~~~~~~~~~  5f289544		sqshrn s4, d10, #24
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 0x~~~~~~~~~~~~~~~~  0f23942a		sqshrn v10.2s, v1.2d, #29
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 0x~~~~~~~~~~~~~~~~  0f1295a3		sqshrn v3.4h, v13.4s, #14
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 0x~~~~~~~~~~~~~~~~  0f0994db		sqshrn v27.8b, v6.8h, #7
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 0x~~~~~~~~~~~~~~~~  4f0f96ee		sqshrn2 v14.16b, v23.8h, #1
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 0x~~~~~~~~~~~~~~~~  4f2596d9		sqshrn2 v25.4s, v22.2d, #27
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 0x~~~~~~~~~~~~~~~~  4f16959f		sqshrn2 v31.8h, v12.4s, #10
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 0x~~~~~~~~~~~~~~~~  7f0f8409		sqshrun b9, h0, #1
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 0x~~~~~~~~~~~~~~~~  7f1984cb		sqshrun h11, s6, #7
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 0x~~~~~~~~~~~~~~~~  7f33858d		sqshrun s13, d12, #13
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 0x~~~~~~~~~~~~~~~~  2f3f87ca		sqshrun v10.2s, v30.2d, #1
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 0x~~~~~~~~~~~~~~~~  2f15847f		sqshrun v31.4h, v3.4s, #11
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 0x~~~~~~~~~~~~~~~~  2f0887dc		sqshrun v28.8b, v30.8h, #8
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 0x~~~~~~~~~~~~~~~~  6f0d8770		sqshrun2 v16.16b, v27.8h, #3
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 0x~~~~~~~~~~~~~~~~  6f2e85db		sqshrun2 v27.4s, v14.2d, #18
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 0x~~~~~~~~~~~~~~~~  6f1f85d7		sqshrun2 v23.8h, v14.4s, #1
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 0x~~~~~~~~~~~~~~~~  5e2b2fb3		sqsub b19, b29, b11
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 0x~~~~~~~~~~~~~~~~  5ee62ff5		sqsub d21, d31, d6
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 0x~~~~~~~~~~~~~~~~  5e732d52		sqsub h18, h10, h19
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 0x~~~~~~~~~~~~~~~~  5ea02ca6		sqsub s6, s5, s0
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 0x~~~~~~~~~~~~~~~~  4e202ed5		sqsub v21.16b, v22.16b, v0.16b
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 0x~~~~~~~~~~~~~~~~  4ef12d56		sqsub v22.2d, v10.2d, v17.2d
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 0x~~~~~~~~~~~~~~~~  0ea22ea8		sqsub v8.2s, v21.2s, v2.2s
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 0x~~~~~~~~~~~~~~~~  0e7b2f32		sqsub v18.4h, v25.4h, v27.4h
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 0x~~~~~~~~~~~~~~~~  4ea62c6d		sqsub v13.4s, v3.4s, v6.4s
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 0x~~~~~~~~~~~~~~~~  0e302fbc		sqsub v28.8b, v29.8b, v16.8b
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 0x~~~~~~~~~~~~~~~~  4e6a2cd1		sqsub v17.8h, v6.8h, v10.8h
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 0x~~~~~~~~~~~~~~~~  5e214b5b		sqxtn b27, h26
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 0x~~~~~~~~~~~~~~~~  5e614971		sqxtn h17, s11
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 0x~~~~~~~~~~~~~~~~  5ea14bf6		sqxtn s22, d31
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 0x~~~~~~~~~~~~~~~~  0ea148ba		sqxtn v26.2s, v5.2d
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 0x~~~~~~~~~~~~~~~~  0e6148ed		sqxtn v13.4h, v7.4s
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 0x~~~~~~~~~~~~~~~~  0e214a73		sqxtn v19.8b, v19.8h
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 0x~~~~~~~~~~~~~~~~  4e214873		sqxtn2 v19.16b, v3.8h
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 0x~~~~~~~~~~~~~~~~  4ea14837		sqxtn2 v23.4s, v1.2d
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 0x~~~~~~~~~~~~~~~~  4e61486d		sqxtn2 v13.8h, v3.4s
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 0x~~~~~~~~~~~~~~~~  7e21293a		sqxtun b26, h9
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 0x~~~~~~~~~~~~~~~~  7e612993		sqxtun h19, s12
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 0x~~~~~~~~~~~~~~~~  7ea128c3		sqxtun s3, d6
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea12b5d		sqxtun v29.2s, v26.2d
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e61295a		sqxtun v26.4h, v10.4s
-#   v26: 0x000000000000000000000000ffff0000
+#            v26: 0x000000000000000000000000ffff0000
 0x~~~~~~~~~~~~~~~~  2e212ba7		sqxtun v7.8b, v29.8h
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e2129d5		sqxtun2 v21.16b, v14.8h
-#   v21: 0x000007ff000000000000000000000000
+#            v21: 0x000007ff000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea129f8		sqxtun2 v24.4s, v15.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e61283e		sqxtun2 v30.8h, v1.4s
-#   v30: 0x00000000000000800000000000000000
+#            v30: 0x00000000000000800000000000000000
 0x~~~~~~~~~~~~~~~~  4e2f1635		srhadd v21.16b, v17.16b, v15.16b
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ebd16bc		srhadd v28.2s, v21.2s, v29.2s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e7e1429		srhadd v9.4h, v1.4h, v30.4h
-#    v9: 0x00000000000000000000000000000040
+#             v9: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  4ea21418		srhadd v24.4s, v0.4s, v2.4s
-#   v24: 0x00000000000000000000000000007ff9
+#            v24: 0x00000000000000000000000000007ff9
 0x~~~~~~~~~~~~~~~~  0e2f1626		srhadd v6.8b, v17.8b, v15.8b
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7514e5		srhadd v5.8h, v7.8h, v21.8h
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f4f45ce		sri d14, d14, #49
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0c4517		sri v23.16b, v8.16b, #4
-#   v23: 0x0000000000000080000000005f8f1000
+#            v23: 0x0000000000000080000000005f8f1000
 0x~~~~~~~~~~~~~~~~  6f6c45b4		sri v20.2d, v13.2d, #20
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f284450		sri v16.2s, v2.2s, #24
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f1546e5		sri v5.4h, v23.4h, #11
-#    v5: 0x000000000000000000000000000b0002
+#             v5: 0x000000000000000000000000000b0002
 0x~~~~~~~~~~~~~~~~  6f2945fb		sri v27.4s, v15.4s, #23
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0c47b3		sri v19.8b, v29.8b, #4
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1d47a7		sri v7.8h, v29.8h, #3
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5efa5522		srshl d2, d9, d26
-#    v2: 0x00000000000000000000000000000040
+#             v2: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  4e2b563d		srshl v29.16b, v17.16b, v11.16b
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee455e8		srshl v8.2d, v15.2d, v4.2d
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea85639		srshl v25.2s, v17.2s, v8.2s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6754f3		srshl v19.4h, v7.4h, v7.4h
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb1544d		srshl v13.4s, v2.4s, v17.4s
-#   v13: 0x00000000000000000000000000000040
+#            v13: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  0e3554d6		srshl v22.8b, v6.8b, v21.8b
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e64562a		srshl v10.8h, v17.8h, v4.8h
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f532655		srshr d21, d18, #45
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f092563		srshr v3.16b, v11.16b, #7
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f4b2755		srshr v21.2d, v26.2d, #53
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f2424ab		srshr v11.2s, v5.2s, #28
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f142647		srshr v7.4h, v18.4h, #12
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f222467		srshr v7.4s, v3.4s, #30
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0a244e		srshr v14.8b, v2.8b, #6
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  4f1d2695		srshr v21.8h, v20.8h, #3
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f4137d5		srsra d21, d30, #63
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0a37db		srsra v27.16b, v30.16b, #6
-#   v27: 0x00000000000000fe0000000000000000
+#            v27: 0x00000000000000fe0000000000000000
 0x~~~~~~~~~~~~~~~~  4f653594		srsra v20.2d, v12.2d, #27
-#   v20: 0x00000000000000000000000000000020
+#            v20: 0x00000000000000000000000000000020
 0x~~~~~~~~~~~~~~~~  0f3b3620		srsra v0.2s, v17.2s, #5
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f11360e		srsra v14.4h, v16.4h, #15
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  4f2c3472		srsra v18.4s, v3.4s, #20
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0f3435		srsra v21.8b, v1.8b, #1
-#   v21: 0x000000000000000000000000000000c0
+#            v21: 0x000000000000000000000000000000c0
 0x~~~~~~~~~~~~~~~~  4f1e373f		srsra v31.8h, v25.8h, #2
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee945a1		sshl d1, d13, d9
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2f47f1		sshl v17.16b, v31.16b, v15.16b
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee0460d		sshl v13.2d, v16.2d, v0.2d
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eb644e0		sshl v0.2s, v7.2s, v22.2s
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e644677		sshl v23.4h, v19.4h, v4.4h
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eab44a5		sshl v5.4s, v5.4s, v11.4s
-#    v5: 0x000000000000000000000000000b0002
+#             v5: 0x000000000000000000000000000b0002
 0x~~~~~~~~~~~~~~~~  0e274777		sshl v23.8b, v27.8b, v7.8b
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e65455d		sshl v29.8h, v10.8h, v5.8h
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f37a440		sshll v0.2d, v2.2s, #23
-#    v0: 0x00000000000000000000000020000000
+#             v0: 0x00000000000000000000000020000000
 0x~~~~~~~~~~~~~~~~  0f18a50b		sshll v11.4s, v8.4h, #8
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f09a7a4		sshll v4.8h, v29.8b, #1
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f2ea48a		sshll2 v10.2d, v4.4s, #14
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f16a7fa		sshll2 v26.4s, v31.8h, #6
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0ca743		sshll2 v3.8h, v26.16b, #4
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f6c06b3		sshr d19, d21, #20
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0b06ef		sshr v15.16b, v23.16b, #5
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f5a05d1		sshr v17.2d, v14.2d, #38
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f2907a3		sshr v3.2s, v29.2s, #23
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f1c0777		sshr v23.4h, v27.4h, #4
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f3c047c		sshr v28.4s, v3.4s, #4
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0a044e		sshr v14.8b, v2.8b, #6
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  4f1a0503		sshr v3.8h, v8.8h, #6
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f54178c		ssra d12, d28, #44
-#   v12: 0x000000000000000000000000ffffffff
+#            v12: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  4f0c17fd		ssra v29.16b, v31.16b, #4
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f681403		ssra v3.2d, v0.2d, #24
-#    v3: 0x00000000000000000000000000000020
+#             v3: 0x00000000000000000000000000000020
 0x~~~~~~~~~~~~~~~~  0f3a178e		ssra v14.2s, v28.2s, #6
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  0f191512		ssra v18.4h, v8.4h, #7
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f2815df		ssra v31.4s, v14.4s, #24
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0b175c		ssra v28.8b, v26.8b, #5
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f121529		ssra v9.8h, v9.8h, #14
-#    v9: 0x00000000000000000000000000000040
+#             v9: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  0ea321cd		ssubl v13.2d, v14.2s, v3.2s
-#   v13: 0x0000000000000000ffffffffffffffe1
+#            v13: 0x0000000000000000ffffffffffffffe1
 0x~~~~~~~~~~~~~~~~  0e682205		ssubl v5.4s, v16.4h, v8.4h
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e262380		ssubl v0.8h, v28.8b, v6.8b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb921a5		ssubl2 v5.2d, v13.4s, v25.4s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7121e3		ssubl2 v3.4s, v15.8h, v17.8h
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2e21ef		ssubl2 v15.8h, v15.16b, v14.16b
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eba32f9		ssubw v25.2d, v23.2d, v26.2s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e783255		ssubw v21.4s, v18.4s, v24.4h
-#   v21: 0x000000000000000000000000ffff8007
+#            v21: 0x000000000000000000000000ffff8007
 0x~~~~~~~~~~~~~~~~  0e2332de		ssubw v30.8h, v22.8h, v3.8b
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ebc3310		ssubw2 v16.2d, v24.2d, v28.4s
-#   v16: 0x00000000000000000000000000007ff9
+#            v16: 0x00000000000000000000000000007ff9
 0x~~~~~~~~~~~~~~~~  4e6f317f		ssubw2 v31.4s, v11.4s, v15.8h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e303104		ssubw2 v4.8h, v8.8h, v16.16b
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4c002012		st1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#     v21<127:0>: 0x000000000000000000000000ffff8007
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x07 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x80 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v20<127:0>: 0x00000000000000000000000000000020
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82202a		st1 {v10.16b, v11.16b, v12.16b, v13.16b}, [x1], x2
-#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v12: 0x000000000000000000000000ffffffff -> 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0000000000000000ffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v13<127:0>: 0x0000000000000000ffffffffffffffe1
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xe1 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v12<127:0>: 0x000000000000000000000000ffffffff
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v11<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v10<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f203b		st1 {v27.16b, v28.16b, v29.16b, v30.16b}, [x1], #64
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v30<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v29<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v28<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xfe -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c006010		st1 {v16.16b, v17.16b, v18.16b}, [x0]
-#   v16: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v17<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v16<127:0>: 0x00000000000000000000000000007ff9
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xf9 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c826035		st1 {v21.16b, v22.16b, v23.16b}, [x1], x2
-#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v22<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#     v21<127:0>: 0x000000000000000000000000ffff8007
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 0x~~~~~~~~~~~~~~~~  4c9f6029		st1 {v9.16b, v10.16b, v11.16b}, [x1], #48
-#    v9: 0x00000000000000000000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#     v10<127:0>: 0x00000000000000000000000000000000
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+#      v9<127:0>: 0x00000000000000000000000000000040
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 0x~~~~~~~~~~~~~~~~  4c00a007		st1 {v7.16b, v8.16b}, [x0]
-#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v8<127:0>: 0x00000000000000000000000000000000
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+#      v7<127:0>: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  4c82a03a		st1 {v26.16b, v27.16b}, [x1], x2
-#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000
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+#     v26<127:0>: 0x00000000000000000000000000000000
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+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9fa036		st1 {v22.16b, v23.16b}, [x1], #32
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000
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+#     v22<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c007017		st1 {v23.16b}, [x0]
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c82703c		st1 {v28.16b}, [x1], x2
-#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v28<127:0>: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  0c006802		st1 {v2.2s, v3.2s, v4.2s}, [x0]
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-#    v3:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v4:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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+#                                          ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c826837		st1 {v23.2s, v24.2s, v25.2s}, [x1], x2
-#   v23:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v24:                 0x0000000000007ff9 (..., 0.00000, 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
-#   v25:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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+#                                          ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f6827		st1 {v7.2s, v8.2s, v9.2s}, [x1], #24
-#    v7:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v8:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v9:                 0x0000000000000040 (..., 0.00000, 8.96831e-44) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c00a81c		st1 {v28.2s, v29.2s}, [x0]
-#   v28:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v29:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c82a83d		st1 {v29.2s, v30.2s}, [x1], x2
-#   v29:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v30:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9fa837		st1 {v23.2s, v24.2s}, [x1], #16
-#   v23:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v24:                 0x0000000000007ff9 (..., 0.00000, 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c007806		st1 {v6.2s}, [x0]
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 0x~~~~~~~~~~~~~~~~  0c82782b		st1 {v11.2s}, [x1], x2
-#   v11:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f7831		st1 {v17.2s}, [x1], #8
-#   v17:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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+#                                          ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c002406		st1 {v6.4h, v7.4h, v8.4h, v9.4h}, [x0]
-#    v6:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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-#    v8:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c822429		st1 {v9.4h, v10.4h, v11.4h, v12.4h}, [x1], x2
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-#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f2439		st1 {v25.4h, v26.4h, v27.4h, v28.4h}, [x1], #32
-#   v25:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v26:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v28:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c00640b		st1 {v11.4h, v12.4h, v13.4h}, [x0]
-#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
-#   v13:                 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c82642a		st1 {v10.4h, v11.4h, v12.4h}, [x1], x2
-#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f642c		st1 {v12.4h, v13.4h, v14.4h}, [x1], #24
-#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
-#   v13:                 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
-#   v14:                 0x0000000000000001 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c00a40d		st1 {v13.4h, v14.4h}, [x0]
-#   v13:                 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
-#   v14:                 0x0000000000000001 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c82a42f		st1 {v15.4h, v16.4h}, [x1], x2
-#   v15:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9fa435		st1 {v21.4h, v22.4h}, [x1], #16
-#   v21:                 0x00000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
-#   v22:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c007410		st1 {v16.4h}, [x0]
-#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c827428		st1 {v8.4h}, [x1], x2
-#    v8:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f743e		st1 {v30.4h}, [x1], #8
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 0x~~~~~~~~~~~~~~~~  4c002803		st1 {v3.4s, v4.4s, v5.4s, v6.4s}, [x0]
-#    v3: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c822839		st1 {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
-#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#     v25<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f2825		st1 {v5.4s, v6.4s, v7.4s, v8.4s}, [x1], #64
-#    v5: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v8<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      v7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      v5<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00681f		st1 {v31.4s, v0.4s, v1.4s}, [x0]
-#   v31: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v1: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#      v1<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      v0<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82683e		st1 {v30.4s, v31.4s, v0.4s}, [x1], x2
-#   v30: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v0<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#     v30<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f6826		st1 {v6.4s, v7.4s, v8.4s}, [x1], #48
-#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v8<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      v7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00a811		st1 {v17.4s, v18.4s}, [x0]
-#   v17: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#     v17<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82a83f		st1 {v31.4s, v0.4s}, [x1], x2
-#   v31: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v0<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9fa821		st1 {v1.4s, v2.4s}, [x1], #32
-#    v1: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v2: 0x00000000000000000000000000000040 (0.00000, 0.00000, 0.00000, 8.96831e-44) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v2<127:0>: 0x00000000000000000000000000000040 (0.000, 0.000, 0.000, 8.968e-44)
+#                          ║       ║       ║       ╙─ 0x00000040 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      v1<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00781a		st1 {v26.4s}, [x0]
-#   v26: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#     v26<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82782f		st1 {v15.4s}, [x1], x2
-#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v15<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f782d		st1 {v13.4s}, [x1], #16
-#   v13: 0x0000000000000000ffffffffffffffe1 (0.00000, 0.00000, nan, nan) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v13<127:0>: 0x0000000000000000ffffffffffffffe1 (0.000, 0.000, nan, nan)
+#                          ║       ║       ║       ╙─ 0xffffffe1 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xffffffff -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c00201a		st1 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
-#   v26:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v28:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v29:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v29<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v28<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v27<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v26<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c82202a		st1 {v10.8b, v11.8b, v12.8b, v13.8b}, [x1], x2
-#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
-#   v13:                 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v13<63:0>:                 0xffffffffffffffe1
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xe1 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#      v12<63:0>:                 0x00000000ffffffff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v11<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v10<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f202f		st1 {v15.8b, v16.8b, v17.8b, v18.8b}, [x1], #32
-#   v15:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v17:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v18:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v18<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v17<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v16<63:0>:                 0x0000000000007ff9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xf9 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x7f -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v15<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c006013		st1 {v19.8b, v20.8b, v21.8b}, [x0]
-#   v19:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20:                 0x0000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#   v21:                 0x00000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#      v21<63:0>:                 0x00000000ffff8007
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x07 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x80 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v20<63:0>:                 0x0000000000000020
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v19<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c82603f		st1 {v31.8b, v0.8b, v1.8b}, [x1], x2
-#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v1<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#       v0<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v31<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f6029		st1 {v9.8b, v10.8b, v11.8b}, [x1], #24
-#    v9:                 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v11<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v10<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#       v9<63:0>:                 0x0000000000000040
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c00a00c		st1 {v12.8b, v13.8b}, [x0]
-#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
-#   v13:                 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
+#      v13<63:0>:                 0xffffffffffffffe1
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xe1 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#      v12<63:0>:                 0x00000000ffffffff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c82a022		st1 {v2.8b, v3.8b}, [x1], x2
-#    v2:                 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#    v3:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v3<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#       v2<63:0>:                 0x0000000000000040
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9fa020		st1 {v0.8b, v1.8b}, [x1], #16
-#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v1<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#       v0<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c007010		st1 {v16.8b}, [x0]
-#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#      v16<63:0>:                 0x0000000000007ff9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xf9 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x7f -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c827039		st1 {v25.8b}, [x1], x2
-#   v25:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v25<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f703f		st1 {v31.8b}, [x1], #8
-#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v31<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c002404		st1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x0]
-#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v5<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v4<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c822423		st1 {v3.8h, v4.8h, v5.8h, v6.8h}, [x1], x2
-#    v3: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v5<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v4<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v3<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f243a		st1 {v26.8h, v27.8h, v28.8h, v29.8h}, [x1], #64
-#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (0.000, 0.000, 0.000, 1.514e-05, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x00fe -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v26<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00640a		st1 {v10.8h, v11.8h, v12.8h}, [x0]
-#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v12: 0x000000000000000000000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#     v12<127:0>: 0x000000000000000000000000ffffffff (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, nan, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v10<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c826435		st1 {v21.8h, v22.8h, v23.8h}, [x1], x2
-#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v22<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v21<127:0>: 0x000000000000000000000000ffff8007 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, nan, -4.172e-07)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x8007 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f6432		st1 {v18.8h, v19.8h, v20.8h}, [x1], #48
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v20<127:0>: 0x00000000000000000000000000000020 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 1.907e-06)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0020 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00a41a		st1 {v26.8h, v27.8h}, [x0]
-#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (0.000, 0.000, 0.000, 1.514e-05, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x00fe -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v26<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82a438		st1 {v24.8h, v25.8h}, [x1], x2
-#   v24: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v25<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v24<127:0>: 0x00000000000000000000000000007ff9 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x7ff9 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9fa431		st1 {v17.8h, v18.8h}, [x1], #32
-#   v17: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v17<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00741d		st1 {v29.8h}, [x0]
-#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c827433		st1 {v19.8h}, [x1], x2
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f7437		st1 {v23.8h}, [x1], #16
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d001c13		st1 {v19.b}[15], [x0]
-#   v19: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d820439		st1 {v25.b}[9], [x1], x2
-#   v25:             0x00                   -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v25<127:0>: 0x00000000000000000000000000000000
+#                                ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d9f0024		st1 {v4.b}[8], [x1], #1
-#    v4:               0x00                 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v4<127:0>: 0x00000000000000000000000000000000
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d00840d		st1 {v13.d}[0], [x0]
-#   v13:                 0xffffffffffffffe1 (d13: nan) -> 0x~~~~~~~~~~~~~~~~
+#     v13<127:0>: 0x0000000000000000ffffffffffffffe1 (..., nan)
+#                                                  ╙─ 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d82843e		st1 {v30.d}[0], [x1], x2
-#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v30<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d9f8423		st1 {v3.d}[0], [x1], #8
-#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v3<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d004016		st1 {v22.h}[0], [x0]
-#   v22:                             0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v22<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d82583f		st1 {v31.h}[7], [x1], x2
-#   v31: 0x0000                             -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d9f5837		st1 {v23.h}[3], [x1], #2
-#   v23:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                      ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d008000		st1 {v0.s}[0], [x0]
-#    v0:                         0x00000000 (s0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#      v0<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d82902b		st1 {v11.s}[3], [x1], x2
-#   v11: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v11<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d9f9038		st1 {v24.s}[3], [x1], #4
-#   v24: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v24<127:0>: 0x00000000000000000000000000007ff9 (0.000, ...)
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c008007		st2 {v7.16b, v8.16b}, [x0]
-#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v7<127:0>: 0x00000000000000000000000000000000
+#      v8<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c828025		st2 {v5.16b, v6.16b}, [x1], x2
-#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v5<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f8032		st2 {v18.16b, v19.16b}, [x1], #32
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4da21c28		st2 {v8.b, v9.b}[15], [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c824035		st3 {v21.16b, v22.16b, v23.16b}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c824c37		st3 {v23.2d, v24.2d, v25.2d}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9f4c2a		st3 {v10.2d, v11.2d, v12.2d}, [x1], #48
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 0x~~~~~~~~~~~~~~~~  0c004809		st3 {v9.2s, v10.2s, v11.2s}, [x0]
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 0x~~~~~~~~~~~~~~~~  0c82482d		st3 {v13.2s, v14.2s, v15.2s}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  0c9f4836		st3 {v22.2s, v23.2s, v24.2s}, [x1], #24
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 0x~~~~~~~~~~~~~~~~  0c00441f		st3 {v31.4h, v0.4h, v1.4h}, [x0]
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 0x~~~~~~~~~~~~~~~~  0c824428		st3 {v8.4h, v9.4h, v10.4h}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  0c9f4433		st3 {v19.4h, v20.4h, v21.4h}, [x1], #24
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 0x~~~~~~~~~~~~~~~~  4c004812		st3 {v18.4s, v19.4s, v20.4s}, [x0]
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 0x~~~~~~~~~~~~~~~~  4c824839		st3 {v25.4s, v26.4s, v27.4s}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9f4830		st3 {v16.4s, v17.4s, v18.4s}, [x1], #48
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 0x~~~~~~~~~~~~~~~~  0c00401b		st3 {v27.8b, v28.8b, v29.8b}, [x0]
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 0x~~~~~~~~~~~~~~~~  0c82403d		st3 {v29.8b, v30.8b, v31.8b}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  0c9f403e		st3 {v30.8b, v31.8b, v0.8b}, [x1], #24
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 0x~~~~~~~~~~~~~~~~  4c004408		st3 {v8.8h, v9.8h, v10.8h}, [x0]
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 0x~~~~~~~~~~~~~~~~  4c824432		st3 {v18.8h, v19.8h, v20.8h}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9f4432		st3 {v18.8h, v19.8h, v20.8h}, [x1], #48
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-#    v2:                 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c00080d		st4 {v13.4s, v14.4s, v15.4s, v16.4s}, [x0]
-#   v13: 0x0000000000000000ffffffffffffffe1 (0.00000, 0.00000, nan, nan) -> 0x~~~~~~~~~~~~~~~~
-#   v14: 0x00000000000000000000000000000001 (0.00000, 0.00000, 0.00000, 1.40130e-45) -> 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000'ffffffff -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c820826		st4 {v6.4s, v7.4s, v8.4s, v9.4s}, [x1], x2
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+#                          ║       ║       ║       ╙─ 0x00000040'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f082f		st4 {v15.4s, v16.4s, v17.4s, v18.4s}, [x1], #64
-#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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-#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c00001a		st4 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
-#   v26:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v28:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v29:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c820039		st4 {v25.8b, v26.8b, v27.8b, v28.8b}, [x1], x2
-#   v25:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v26:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v28:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v25<63:0>:                 0x0000000000000000
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+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f0033		st4 {v19.8b, v20.8b, v21.8b, v22.8b}, [x1], #32
-#   v19:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20:                 0x0000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#   v21:                 0x00000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
-#   v22:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v19<63:0>:                 0x0000000000000000
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+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'07'20'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'80'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'ff'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'ff'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c000413		st4 {v19.8h, v20.8h, v21.8h, v22.8h}, [x0]
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'8007'0020'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'ffff'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82042f		st4 {v15.8h, v16.8h, v17.8h, v18.8h}, [x1], x2
-#   v15: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v16: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'7ff9'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f043f		st4 {v31.8h, v0.8h, v1.8h, v2.8h}, [x1], #64
-#   v31: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v1: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v2: 0x00000000000000000000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0040'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d203400		st4 {v0.b, v1.b, v2.b, v3.b}[13], [x0]
-#    v0:     0x00                           -> 0x~~~~~~~~~~~~~~~~
-#    v1:     0x00                           -> 0x~~~~~~~~~~~~~~~~
-#    v2:     0x00                           -> 0x~~~~~~~~~~~~~~~~
-#    v3:     0x00                           -> 0x~~~~~~~~~~~~~~~~
+#      v0<127:0>: 0x00000000000000000000000000000000
+#      v1<127:0>: 0x00000000000000000000000000000000
+#      v2<127:0>: 0x00000000000000000000000000000040
+#      v3<127:0>: 0x00000000000000000000000000000000
+#                        ╙─────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4da22824		st4 {v4.b, v5.b, v6.b, v7.b}[10], [x1], x2
-#    v4:           0x00                     -> 0x~~~~~~~~~~~~~~~~
-#    v5:           0x00                     -> 0x~~~~~~~~~~~~~~~~
-#    v6:           0x00                     -> 0x~~~~~~~~~~~~~~~~
-#    v7:           0x00                     -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v4<127:0>: 0x00000000000000000000000000000000
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+#      v6<127:0>: 0x00000000000000000000000000000000
+#      v7<127:0>: 0x00000000000000000000000000000000
+#                              ╙───────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dbf2429		st4 {v9.b, v10.b, v11.b, v12.b}[9], [x1], #4
-#    v9:             0x00                   -> 0x~~~~~~~~~~~~~~~~
-#   v10:             0x00                   -> 0x~~~~~~~~~~~~~~~~
-#   v11:             0x00                   -> 0x~~~~~~~~~~~~~~~~
-#   v12:             0x00                   -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v9<127:0>: 0x00000000000000000000000000000040
+#     v10<127:0>: 0x00000000000000000000000000000000
+#     v11<127:0>: 0x00000000000000000000000000000000
+#     v12<127:0>: 0x000000000000000000000000ffffffff
+#                                ╙─────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d20a402		st4 {v2.d, v3.d, v4.d, v5.d}[1], [x0]
-#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#      v2<127:0>: 0x00000000000000000000000000000040 (0.000, ...)
+#      v3<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v4<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v5<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0da2a427		st4 {v7.d, v8.d, v9.d, v10.d}[0], [x1], x2
-#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v9:                 0x0000000000000040 (d9: 3.16202e-322) -> 0x~~~~~~~~~~~~~~~~
-#   v10:                 0x0000000000000000 (d10: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v7<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#      v8<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#      v9<127:0>: 0x00000000000000000000000000000040 (..., 3.162e-322)
+#     v10<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000'0000000000000040'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dbfa43f		st4 {v31.d, v0.d, v1.d, v2.d}[1], [x1], #32
-#   v31: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v0: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v1: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v0<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v1<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v2<127:0>: 0x00000000000000000000000000000040 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d206802		st4 {v2.h, v3.h, v4.h, v5.h}[1], [x0]
-#    v2:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
-#    v3:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
-#    v4:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
-#    v5:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#      v2<127:0>: 0x00000000000000000000000000000040 (..., 0.000, ...)
+#      v3<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#      v4<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#      v5<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                              ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0da2783b		st4 {v27.h, v28.h, v29.h, v30.h}[3], [x1], x2
-#   v27:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#   v28:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#   v29:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#   v30:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (..., 0.000, ...)
+#     v28<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v29<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v30<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                      ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dbf6038		st4 {v24.h, v25.h, v26.h, v27.h}[4], [x1], #8
-#   v24:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
-#   v25:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
-#   v26:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
-#   v27:             0x00fe                 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v24<127:0>: 0x00000000000000000000000000007ff9 (..., 0.000, ...)
+#     v25<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v26<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (..., 1.514e-05, ...)
+#                                  ╙───────────────── 0x00fe'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d20a012		st4 {v18.s, v19.s, v20.s, v21.s}[2], [x0]
-#   v18:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v19:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v20:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v21:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v19<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v20<127:0>: 0x00000000000000000000000000000020 (..., 0.000, ...)
+#     v21<127:0>: 0x000000000000000000000000ffff8007 (..., 0.000, ...)
+#                                  ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4da2a026		st4 {v6.s, v7.s, v8.s, v9.s}[2], [x1], x2
-#    v6:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v7:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v8:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v9:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
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+#      v8<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#      v9<127:0>: 0x00000000000000000000000000000040 (..., 0.000, ...)
+#                                  ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dbfb039		st4 {v25.s, v26.s, v27.s, v28.s}[1], [x1], #16
-#   v25:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v26:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v27:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v28:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v25<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v26<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (..., 0.000, ...)
+#     v28<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                          ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7ee2862c		sub d12, d17, d2
-#   v12: 0x0000000000000000ffffffffffffffc0
+#            v12: 0x0000000000000000ffffffffffffffc0
 0x~~~~~~~~~~~~~~~~  6e288714		sub v20.16b, v24.16b, v8.16b
-#   v20: 0x00000000000000000000000000007ff9
+#            v20: 0x00000000000000000000000000007ff9
 0x~~~~~~~~~~~~~~~~  6ee587a8		sub v8.2d, v29.2d, v5.2d
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb88782		sub v2.2s, v28.2s, v24.2s
-#    v2: 0x000000000000000000000000ffff8007
+#             v2: 0x000000000000000000000000ffff8007
 0x~~~~~~~~~~~~~~~~  2e648558		sub v24.4h, v10.4h, v4.4h
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb1849c		sub v28.4s, v4.4s, v17.4s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e228770		sub v16.8b, v27.8b, v2.8b
-#   v16: 0x000000000000000000000000010180f9
+#            v16: 0x000000000000000000000000010180f9
 0x~~~~~~~~~~~~~~~~  6e6d8554		sub v20.8h, v10.8h, v13.8h
-#   v20: 0x0000000000000000000100010001001f
+#            v20: 0x0000000000000000000100010001001f
 0x~~~~~~~~~~~~~~~~  0ead61c5		subhn v5.2s, v14.2d, v13.2d
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6860aa		subhn v10.4h, v5.4s, v8.4s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e366146		subhn v6.8b, v10.8h, v22.8h
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2960cb		subhn2 v11.16b, v6.8h, v9.8h
-#   v11: 0x00000000000000ff0000000000000000
+#            v11: 0x00000000000000ff0000000000000000
 0x~~~~~~~~~~~~~~~~  4eb86259		subhn2 v25.4s, v18.2d, v24.2d
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6162b4		subhn2 v20.8h, v21.4s, v1.4s
-#   v20: 0x000000000000ffff000100010001001f
+#            v20: 0x000000000000ffff000100010001001f
 0x~~~~~~~~~~~~~~~~  5e203979		suqadd b25, b11
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0382d		suqadd d13, d1
-#   v13: 0x0000000000000000ffffffffffffffe1
+#            v13: 0x0000000000000000ffffffffffffffe1
 0x~~~~~~~~~~~~~~~~  5e603920		suqadd h0, h9
-#    v0: 0x00000000000000000000000000000040
+#             v0: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  5ea03916		suqadd s22, s8
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e203b78		suqadd v24.16b, v27.16b
-#   v24: 0x000000000000007f0000000000000000
+#            v24: 0x000000000000007f0000000000000000
 0x~~~~~~~~~~~~~~~~  4ee039da		suqadd v26.2d, v14.2d
-#   v26: 0x00000000000000000000000000000001
+#            v26: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  0ea03947		suqadd v7.2s, v10.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e603999		suqadd v25.4h, v12.4h
-#   v25: 0x00000000000000007fff7fff7fff7fff
+#            v25: 0x00000000000000007fff7fff7fff7fff
 0x~~~~~~~~~~~~~~~~  4ea03864		suqadd v4.4s, v3.4s
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e203a4e		suqadd v14.8b, v18.8b
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  4e60391f		suqadd v31.8h, v8.8h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f20a690		sxtl v16.2d, v20.2s
-#   v16: 0x0000000000010001000000000001001f
+#            v16: 0x0000000000010001000000000001001f
 0x~~~~~~~~~~~~~~~~  0f10a79b		sxtl v27.4s, v28.4h
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f08a6c0		sxtl v0.8h, v22.8b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f20a4e6		sxtl2 v6.2d, v7.4s
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f10a769		sxtl2 v9.4s, v27.8h
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f08a610		sxtl2 v16.8h, v16.16b
-#   v16: 0x00000000000000000000000100000001
+#            v16: 0x00000000000000000000000100000001
 0x~~~~~~~~~~~~~~~~  4e166239		tbl v25.16b, {v17.16b, v18.16b, v19.16b, v20.16b}, v22.16b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e0441bc		tbl v28.16b, {v13.16b, v14.16b, v15.16b}, v4.16b
-#   v28: 0xe1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1
+#            v28: 0xe1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1
 0x~~~~~~~~~~~~~~~~  4e022003		tbl v3.16b, {v0.16b, v1.16b}, v2.16b
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e0401f4		tbl v20.16b, {v15.16b}, v4.16b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1462e7		tbl v7.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v20.8b
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1f4028		tbl v8.8b, {v1.16b, v2.16b, v3.16b}, v31.8b
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e102328		tbl v8.8b, {v25.16b, v26.16b}, v16.8b
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1e026b		tbl v11.8b, {v19.16b}, v30.8b
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e057339		tbx v25.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v5.16b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e1853b5		tbx v21.16b, {v29.16b, v30.16b, v31.16b}, v24.16b
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e013206		tbx v6.16b, {v16.16b, v17.16b}, v1.16b
-#    v6: 0x01010101010101010101010101010101
+#             v6: 0x01010101010101010101010101010101
 0x~~~~~~~~~~~~~~~~  4e14106d		tbx v13.16b, {v3.16b}, v20.16b
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e0973b8		tbx v24.8b, {v29.16b, v30.16b, v31.16b, v0.16b}, v9.8b
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1a5131		tbx v17.8b, {v9.16b, v10.16b, v11.16b}, v26.8b
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e153065		tbx v5.8b, {v3.16b, v4.16b}, v21.8b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1d1170		tbx v16.8b, {v11.16b}, v29.8b
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e0c2b13		trn1 v19.16b, v24.16b, v12.16b
-#   v19: 0x0000000000000000ff00ff00ff00c000
+#            v19: 0x0000000000000000ff00ff00ff00c000
 0x~~~~~~~~~~~~~~~~  4eca28e2		trn1 v2.2d, v7.2d, v10.2d
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e952816		trn1 v22.2s, v0.2s, v21.2s
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e5429ec		trn1 v12.4h, v15.4h, v20.4h
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e892a3e		trn1 v30.4s, v17.4s, v9.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1d2a6c		trn1 v12.8b, v19.8b, v29.8b
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e492917		trn1 v23.8h, v8.8h, v9.8h
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e196bdc		trn2 v28.16b, v30.16b, v25.16b
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ec76b67		trn2 v7.2d, v27.2d, v7.2d
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e936a1e		trn2 v30.2s, v16.2s, v19.2s
-#   v30: 0x0000000000000000ff00ff0000000000
+#            v30: 0x0000000000000000ff00ff0000000000
 0x~~~~~~~~~~~~~~~~  0e5968d8		trn2 v24.4h, v6.4h, v25.4h
-#   v24: 0x00000000000000000000010100000101
+#            v24: 0x00000000000000000000010100000101
 0x~~~~~~~~~~~~~~~~  4e8b6a62		trn2 v2.4s, v19.4s, v11.4s
-#    v2: 0x000000000000000000000000ff00ff00
+#             v2: 0x000000000000000000000000ff00ff00
 0x~~~~~~~~~~~~~~~~  0e126b79		trn2 v25.8b, v27.8b, v18.8b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e4f688c		trn2 v12.8h, v4.8h, v15.8h
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e3c7d9f		uaba v31.16b, v12.16b, v28.16b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eae7cb2		uaba v18.2s, v5.2s, v14.2s
-#   v18: 0x00000000000000000000000000000001
+#            v18: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  2e757e89		uaba v9.4h, v20.4h, v21.4h
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea27e86		uaba v6.4s, v20.4s, v2.4s
-#    v6: 0x01010101010101010101010100020001
+#             v6: 0x01010101010101010101010100020001
 0x~~~~~~~~~~~~~~~~  2e257d90		uaba v16.8b, v12.8b, v5.8b
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7e7f4f		uaba v15.8h, v26.8h, v30.8h
-#   v15: 0x0000000000000000ff00ff0000000001
+#            v15: 0x0000000000000000ff00ff0000000001
 0x~~~~~~~~~~~~~~~~  2eaf524a		uabal v10.2d, v18.2s, v15.2s
-#   v10: 0x00000000ff00ff000000000000000000
+#            v10: 0x00000000ff00ff000000000000000000
 0x~~~~~~~~~~~~~~~~  2e67527e		uabal v30.4s, v19.4h, v7.4h
-#   v30: 0x0000ff000000ff00ff01fe000000c000
+#            v30: 0x0000ff000000ff00ff01fe000000c000
 0x~~~~~~~~~~~~~~~~  2e205364		uabal v4.8h, v27.8b, v0.8b
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea25193		uabal2 v19.2d, v12.4s, v2.4s
-#   v19: 0x0000000000000000ff00ff00ff00c000
+#            v19: 0x0000000000000000ff00ff00ff00c000
 0x~~~~~~~~~~~~~~~~  6e6c50ba		uabal2 v26.4s, v5.8h, v12.8h
-#   v26: 0x00000000000000000000000000000001
+#            v26: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  6e3c5293		uabal2 v19.8h, v20.16b, v28.16b
-#   v19: 0x0000000000000000ff00ff00ff00c000
+#            v19: 0x0000000000000000ff00ff00ff00c000
 0x~~~~~~~~~~~~~~~~  6e357492		uabd v18.16b, v4.16b, v21.16b
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb076be		uabd v30.2s, v21.2s, v16.2s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e797788		uabd v8.4h, v28.4h, v25.4h
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb5759c		uabd v28.4s, v12.4s, v21.4s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3c7613		uabd v19.8b, v16.8b, v28.8b
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7d7589		uabd v9.8h, v12.8h, v29.8h
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea8701a		uabdl v26.2d, v0.2s, v8.2s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e7973fd		uabdl v29.4s, v31.4h, v25.4h
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e2e73bb		uabdl v27.8h, v29.8b, v14.8b
-#   v27: 0x00000000000000000000000000000001
+#            v27: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  6ea87294		uabdl2 v20.2d, v20.4s, v8.4s
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7271f6		uabdl2 v22.4s, v15.8h, v18.8h
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e377249		uabdl2 v9.8h, v18.16b, v23.16b
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea069e9		uadalp v9.1d, v15.2s
-#    v9: 0x000000000000000000000000ff00ff01
+#             v9: 0x000000000000000000000000ff00ff01
 0x~~~~~~~~~~~~~~~~  6ea0698e		uadalp v14.2d, v12.4s
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  2e60699c		uadalp v28.2s, v12.4h
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e206a20		uadalp v0.4h, v17.8b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e606ba1		uadalp v1.4s, v29.8h
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e206acf		uadalp v15.8h, v22.16b
-#   v15: 0x0000000000000000ff00ff0000000001
+#            v15: 0x0000000000000000ff00ff0000000001
 0x~~~~~~~~~~~~~~~~  2ebb0281		uaddl v1.2d, v20.2s, v27.2s
-#    v1: 0x00000000000000000000000000000001
+#             v1: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  2e65033f		uaddl v31.4s, v25.4h, v5.4h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e23006c		uaddl v12.8h, v3.8b, v3.8b
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea602e5		uaddl2 v5.2d, v23.4s, v6.4s
-#    v5: 0x00000000010101010000000001010101
+#             v5: 0x00000000010101010000000001010101
 0x~~~~~~~~~~~~~~~~  6e7900a1		uaddl2 v1.4s, v5.8h, v25.8h
-#    v1: 0x00000000000000000000010100000101
+#             v1: 0x00000000000000000000010100000101
 0x~~~~~~~~~~~~~~~~  6e3c03d6		uaddl2 v22.8h, v30.16b, v28.16b
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea02927		uaddlp v7.1d, v9.2s
-#    v7: 0x000000000000000000000000ff00ff01
+#             v7: 0x000000000000000000000000ff00ff01
 0x~~~~~~~~~~~~~~~~  6ea0289a		uaddlp v26.2d, v4.4s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e60283c		uaddlp v28.2s, v1.4h
-#   v28: 0x00000000000000000000010100000101
+#            v28: 0x00000000000000000000010100000101
 0x~~~~~~~~~~~~~~~~  2e202bf4		uaddlp v20.4h, v31.8b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e602a30		uaddlp v16.4s, v17.8h
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e202846		uaddlp v6.8h, v2.16b
-#    v6: 0x00000000000000000000000000ff00ff
+#             v6: 0x00000000000000000000000000ff00ff
 0x~~~~~~~~~~~~~~~~  6eb03adc		uaddlv d28, v22.4s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e303a60		uaddlv h0, v19.16b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e303bde		uaddlv h30, v30.8b
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e703a58		uaddlv s24, v18.4h
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e70380a		uaddlv s10, v0.8h
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eae1229		uaddw v9.2d, v17.2d, v14.2s
-#    v9: 0x00000000000000000000000000000001
+#             v9: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  2e631329		uaddw v9.4s, v25.4s, v3.4h
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e201032		uaddw v18.8h, v1.8h, v0.8b
-#   v18: 0x00000000000000000000010100000101
+#            v18: 0x00000000000000000000010100000101
 0x~~~~~~~~~~~~~~~~  6ea610b2		uaddw2 v18.2d, v5.2d, v6.4s
-#   v18: 0x00000000010101010000000001010101
+#            v18: 0x00000000010101010000000001010101
 0x~~~~~~~~~~~~~~~~  6e6b11f1		uaddw2 v17.4s, v15.4s, v11.8h
-#   v17: 0x0000000000000000ff00ff0000000001
+#            v17: 0x0000000000000000ff00ff0000000001
 0x~~~~~~~~~~~~~~~~  6e27117d		uaddw2 v29.8h, v11.8h, v7.16b
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e23052d		uhadd v13.16b, v9.16b, v3.16b
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb80731		uhadd v17.2s, v25.2s, v24.2s
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e6d06f9		uhadd v25.4h, v23.4h, v13.4h
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb00680		uhadd v0.4s, v20.4s, v16.4s
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3904a5		uhadd v5.8b, v5.8b, v25.8b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7207a3		uhadd v3.8h, v29.8h, v18.8h
-#    v3: 0x00000000008000800000000000800080
+#             v3: 0x00000000008000800000000000800080
 0x~~~~~~~~~~~~~~~~  6e2d26c1		uhsub v1.16b, v22.16b, v13.16b
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ebe27ce		uhsub v14.2s, v30.2s, v30.2s
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e7125dd		uhsub v29.4h, v14.4h, v17.4h
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb224ba		uhsub v26.4s, v5.4s, v18.4s
-#   v26: 0x00000000ff7f7f7f00000000ff7f7f7f
+#            v26: 0x00000000ff7f7f7f00000000ff7f7f7f
 0x~~~~~~~~~~~~~~~~  2e2c24e3		uhsub v3.8b, v7.8b, v12.8b
-#    v3: 0x0000000000000000000000007f007f00
+#             v3: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6e6526b9		uhsub v25.8h, v21.8h, v5.8h
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e26659c		umax v28.16b, v12.16b, v6.16b
-#   v28: 0x00000000000000000000000000ff00ff
+#            v28: 0x00000000000000000000000000ff00ff
 0x~~~~~~~~~~~~~~~~  2eba6674		umax v20.2s, v19.2s, v26.2s
-#   v20: 0x000000000000000000000000ff7f7f7f
+#            v20: 0x000000000000000000000000ff7f7f7f
 0x~~~~~~~~~~~~~~~~  2e7267e0		umax v0.4h, v31.4h, v18.4h
-#    v0: 0x00000000000000000000000001010101
+#             v0: 0x00000000000000000000000001010101
 0x~~~~~~~~~~~~~~~~  6ebc66a6		umax v6.4s, v21.4s, v28.4s
-#    v6: 0x00000000000000000000000000ff00ff
+#             v6: 0x00000000000000000000000000ff00ff
 0x~~~~~~~~~~~~~~~~  2e346440		umax v0.8b, v2.8b, v20.8b
-#    v0: 0x000000000000000000000000ff7fff7f
+#             v0: 0x000000000000000000000000ff7fff7f
 0x~~~~~~~~~~~~~~~~  6e766564		umax v4.8h, v11.8h, v22.8h
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e3da4c1		umaxp v1.16b, v6.16b, v29.16b
-#    v1: 0x0000000000000000000000000000ffff
+#             v1: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  2ebba633		umaxp v19.2s, v17.2s, v27.2s
-#   v19: 0x00000000000000000000000100000000
+#            v19: 0x00000000000000000000000100000000
 0x~~~~~~~~~~~~~~~~  2e67a615		umaxp v21.4h, v16.4h, v7.4h
-#   v21: 0x00000000000000000000ff0100000000
+#            v21: 0x00000000000000000000ff0100000000
 0x~~~~~~~~~~~~~~~~  6ebda689		umaxp v9.4s, v20.4s, v29.4s
-#    v9: 0x000000000000000000000000ff7f7f7f
+#             v9: 0x000000000000000000000000ff7f7f7f
 0x~~~~~~~~~~~~~~~~  2e30a42d		umaxp v13.8b, v1.8b, v16.8b
-#   v13: 0x000000000000000000000000000000ff
+#            v13: 0x000000000000000000000000000000ff
 0x~~~~~~~~~~~~~~~~  6e7aa6f3		umaxp v19.8h, v23.8h, v26.8h
-#   v19: 0x0000ff7f0000ff7f0000000000000000
+#            v19: 0x0000ff7f0000ff7f0000000000000000
 0x~~~~~~~~~~~~~~~~  6e30abd1		umaxv b17, v30.16b
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e30a997		umaxv b23, v12.8b
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e70a9ff		umaxv h31, v15.4h
-#   v31: 0x0000000000000000000000000000ff00
+#            v31: 0x0000000000000000000000000000ff00
 0x~~~~~~~~~~~~~~~~  6e70ab2f		umaxv h15, v25.8h
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb0aab2		umaxv s18, v21.4s
-#   v18: 0x0000000000000000000000000000ff01
+#            v18: 0x0000000000000000000000000000ff01
 0x~~~~~~~~~~~~~~~~  6e326c16		umin v22.16b, v0.16b, v18.16b
-#   v22: 0x0000000000000000000000000000ff01
+#            v22: 0x0000000000000000000000000000ff01
 0x~~~~~~~~~~~~~~~~  2eb06ea1		umin v1.2s, v21.2s, v16.2s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e796c91		umin v17.4h, v4.4h, v25.4h
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ead6f58		umin v24.4s, v26.4s, v13.4s
-#   v24: 0x000000000000000000000000000000ff
+#            v24: 0x000000000000000000000000000000ff
 0x~~~~~~~~~~~~~~~~  2e256c34		umin v20.8b, v1.8b, v5.8b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e776f3a		umin v26.8h, v25.8h, v23.8h
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e37ac25		uminp v5.16b, v1.16b, v23.16b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ebeaf47		uminp v7.2s, v26.2s, v30.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e79aca9		uminp v9.4h, v5.4h, v25.4h
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea1ad57		uminp v23.4s, v10.4s, v1.4s
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e2eafa4		uminp v4.8b, v29.8b, v14.8b
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e6eac15		uminp v21.8h, v0.8h, v14.8h
-#   v21: 0x0000000000000000000000000000ff7f
+#            v21: 0x0000000000000000000000000000ff7f
 0x~~~~~~~~~~~~~~~~  6e31aa20		uminv b0, v17.16b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e31abe0		uminv b0, v31.8b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e71a818		uminv h24, v0.4h
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e71a9dd		uminv h29, v14.8h
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb1a87e		uminv s30, v3.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb8816b		umlal v11.2d, v11.2s, v24.2s
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2fab2a1e		umlal v30.2d, v16.2s, v11.s[3]
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e7a8120		umlal v0.4s, v9.4h, v26.4h
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f4c2b14		umlal v20.4s, v24.4h, v12.h[4]
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e2682b0		umlal v16.8h, v21.8b, v6.8b
-#   v16: 0x00000000000000000000000000007e81
+#            v16: 0x00000000000000000000000000007e81
 0x~~~~~~~~~~~~~~~~  6eb78271		umlal2 v17.2d, v19.4s, v23.4s
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f8823c5		umlal2 v5.2d, v30.4s, v8.s[0]
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e6f8110		umlal2 v16.4s, v8.8h, v15.8h
-#   v16: 0x00000000000000000000000000007e81
+#            v16: 0x00000000000000000000000000007e81
 0x~~~~~~~~~~~~~~~~  6f512b4f		umlal2 v15.4s, v26.8h, v1.h[5]
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e31803e		umlal2 v30.8h, v1.16b, v17.16b
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ebca272		umlsl v18.2d, v19.2s, v28.2s
-#   v18: 0x0000000000000000000000000000ff01
+#            v18: 0x0000000000000000000000000000ff01
 0x~~~~~~~~~~~~~~~~  2f8860e7		umlsl v7.2d, v7.2s, v8.s[0]
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e64a118		umlsl v24.4s, v8.4h, v4.4h
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f4c6ad2		umlsl v18.4s, v22.4h, v12.h[4]
-#   v18: 0x0000000000000000000000000000ff01
+#            v18: 0x0000000000000000000000000000ff01
 0x~~~~~~~~~~~~~~~~  2e34a1dc		umlsl v28.8h, v14.8b, v20.8b
-#   v28: 0x00000000000000000000000000ff00ff
+#            v28: 0x00000000000000000000000000ff00ff
 0x~~~~~~~~~~~~~~~~  6ea9a00b		umlsl2 v11.2d, v0.4s, v9.4s
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f896a1a		umlsl2 v26.2d, v16.4s, v9.s[2]
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e69a163		umlsl2 v3.4s, v11.8h, v9.8h
-#    v3: 0x0000000000000000000000007f007f00
+#             v3: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6f496b2a		umlsl2 v10.4s, v25.8h, v9.h[4]
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e3ca218		umlsl2 v24.8h, v16.16b, v28.16b
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e183f3e		mov x30, v25.d[1]
-#    lr: 0x0000000000000000
+#             lr: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  2ebdc14c		umull v12.2d, v10.2s, v29.2s
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2fa5abd6		umull v22.2d, v30.2s, v5.s[3]
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e79c007		umull v7.4s, v0.4h, v25.4h
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f63a1ab		umull v11.4s, v13.4h, v3.h[2]
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e2ac219		umull v25.8h, v16.8b, v10.8b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ebac071		umull2 v17.2d, v3.4s, v26.4s
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6fa2a97a		umull2 v26.2d, v11.4s, v2.s[3]
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e77c22c		umull2 v12.4s, v17.8h, v23.8h
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f61a3e4		umull2 v4.4s, v31.8h, v1.h[2]
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e31c185		umull2 v5.8h, v12.16b, v17.16b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e3c0c9e		uqadd b30, b4, b28
-#   v30: 0x000000000000000000000000000000ff
+#            v30: 0x000000000000000000000000000000ff
 0x~~~~~~~~~~~~~~~~  7ef00e9b		uqadd d27, d20, d16
-#   v27: 0x00000000000000000000000000007e81
+#            v27: 0x00000000000000000000000000007e81
 0x~~~~~~~~~~~~~~~~  7e7c0dc7		uqadd h7, h14, h28
-#    v7: 0x000000000000000000000000000000ff
+#             v7: 0x000000000000000000000000000000ff
 0x~~~~~~~~~~~~~~~~  7ea40e3c		uqadd s28, s17, s4
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e350ed3		uqadd v19.16b, v22.16b, v21.16b
-#   v19: 0x0000000000000000000000000000ff7f
+#            v19: 0x0000000000000000000000000000ff7f
 0x~~~~~~~~~~~~~~~~  6eeb0c90		uqadd v16.2d, v4.2d, v11.2d
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea40dd4		uqadd v20.2s, v14.2s, v4.2s
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e700c05		uqadd v5.4h, v0.4h, v16.4h
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea90ff5		uqadd v21.4s, v31.4s, v9.4s
-#   v21: 0x0000000000000000000000000000ff00
+#            v21: 0x0000000000000000000000000000ff00
 0x~~~~~~~~~~~~~~~~  2e230f17		uqadd v23.8b, v24.8b, v3.8b
-#   v23: 0x0000000000000000000000007f007f00
+#            v23: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6e6b0f71		uqadd v17.8h, v27.8h, v11.8h
-#   v17: 0x00000000000000000000000000007e81
+#            v17: 0x00000000000000000000000000007e81
 0x~~~~~~~~~~~~~~~~  7e2a5eca		uqrshl b10, b22, b10
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eeb5cbd		uqrshl d29, d5, d11
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e7e5f1b		uqrshl h27, h24, h30
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ea85daa		uqrshl s10, s13, s8
-#   v10: 0x000000000000000000000000000000ff
+#            v10: 0x000000000000000000000000000000ff
 0x~~~~~~~~~~~~~~~~  6e2e5e49		uqrshl v9.16b, v18.16b, v14.16b
-#    v9: 0x0000000000000000000000000000ff01
+#             v9: 0x0000000000000000000000000000ff01
 0x~~~~~~~~~~~~~~~~  6ef15df8		uqrshl v24.2d, v15.2d, v17.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ebb5dc4		uqrshl v4.2s, v14.2s, v27.2s
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e685caf		uqrshl v15.4h, v5.4h, v8.4h
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea05fb5		uqrshl v21.4s, v29.4s, v0.4s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e295f10		uqrshl v16.8b, v24.8b, v9.8b
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e6f5c02		uqrshl v2.8h, v0.8h, v15.8h
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f0c9f4b		uqrshrn b11, h26, #4
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f1b9fc7		uqrshrn h7, s30, #5
-#    v7: 0x00000000000000000000000000000008
+#             v7: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  7f2b9d0a		uqrshrn s10, d8, #21
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f359ccf		uqrshrn v15.2s, v6.2d, #11
-#   v15: 0x00000000000000000000000000001fe0
+#            v15: 0x00000000000000000000000000001fe0
 0x~~~~~~~~~~~~~~~~  2f149f45		uqrshrn v5.4h, v26.4s, #12
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0b9f3c		uqrshrn v28.8b, v25.8h, #5
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0e9fd9		uqrshrn2 v25.16b, v30.8h, #2
-#   v25: 0x00000000000000400000000000000000
+#            v25: 0x00000000000000400000000000000000
 0x~~~~~~~~~~~~~~~~  6f209dd5		uqrshrn2 v21.4s, v14.2d, #32
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1e9ced		uqrshrn2 v13.8h, v7.4s, #2
-#   v13: 0x000000000000000200000000000000ff
+#            v13: 0x000000000000000200000000000000ff
 0x~~~~~~~~~~~~~~~~  7e374c0d		uqshl b13, b0, b23
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f0c7629		uqshl b9, b17, #4
-#    v9: 0x000000000000000000000000000000ff
+#             v9: 0x000000000000000000000000000000ff
 0x~~~~~~~~~~~~~~~~  7ee44cd7		uqshl d23, d6, d4
-#   v23: 0x00000000000000000000000000ff00ff
+#            v23: 0x00000000000000000000000000ff00ff
 0x~~~~~~~~~~~~~~~~  7f6c7568		uqshl d8, d11, #44
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e6f4db3		uqshl h19, h13, h15
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f167759		uqshl h25, h26, #6
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eaa4f04		uqshl s4, s24, s10
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f2175d3		uqshl s19, s14, #1
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e394fce		uqshl v14.16b, v30.16b, v25.16b
-#   v14: 0x000000000000000000000000000000ff
+#            v14: 0x000000000000000000000000000000ff
 0x~~~~~~~~~~~~~~~~  6f0d7546		uqshl v6.16b, v10.16b, #5
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee74d12		uqshl v18.2d, v8.2d, v7.2d
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f5275d9		uqshl v25.2d, v14.2d, #18
-#   v25: 0x00000000000000000000000003fc0000
+#            v25: 0x00000000000000000000000003fc0000
 0x~~~~~~~~~~~~~~~~  2eb74e19		uqshl v25.2s, v16.2s, v23.2s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f3f75ed		uqshl v13.2s, v15.2s, #31
-#   v13: 0x000000000000000000000000ffffffff
+#            v13: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  2e6f4f1c		uqshl v28.4h, v24.4h, v15.4h
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f117624		uqshl v4.4h, v17.4h, #1
-#    v4: 0x0000000000000000000000000000fd02
+#             v4: 0x0000000000000000000000000000fd02
 0x~~~~~~~~~~~~~~~~  6eb74fe9		uqshl v9.4s, v31.4s, v23.4s
-#    v9: 0x00000000000000000000000000007f80
+#             v9: 0x00000000000000000000000000007f80
 0x~~~~~~~~~~~~~~~~  6f3f7792		uqshl v18.4s, v28.4s, #31
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e2f4ebf		uqshl v31.8b, v21.8b, v15.8b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0976a6		uqshl v6.8b, v21.8b, #1
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e714c5c		uqshl v28.8h, v2.8h, v17.8h
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1e7518		uqshl v24.8h, v8.8h, #14
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f099775		uqshrn b21, h27, #7
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f15975c		uqshrn h28, s26, #11
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f2f97ed		uqshrn s13, d31, #17
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f389615		uqshrn v21.2s, v16.2d, #8
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f1e9718		uqshrn v24.4h, v24.4s, #2
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f089425		uqshrn v5.8b, v1.8h, #8
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0a97b0		uqshrn2 v16.16b, v29.8h, #6
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f3f94c2		uqshrn2 v2.4s, v6.2d, #1
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f129550		uqshrn2 v16.8h, v10.4s, #14
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e3a2e9c		uqsub b28, b20, b26
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eea2ce0		uqsub d0, d7, d10
-#    v0: 0x00000000000000000000000000000008
+#             v0: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  7e672f1a		uqsub h26, h24, h7
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eb02ef7		uqsub s23, s23, s16
-#   v23: 0x00000000000000000000000000ff00ff
+#            v23: 0x00000000000000000000000000ff00ff
 0x~~~~~~~~~~~~~~~~  6e382e0e		uqsub v14.16b, v16.16b, v24.16b
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee62e2b		uqsub v11.2d, v17.2d, v6.2d
-#   v11: 0x00000000000000000000000000007e81
+#            v11: 0x00000000000000000000000000007e81
 0x~~~~~~~~~~~~~~~~  2ea82d4a		uqsub v10.2s, v10.2s, v8.2s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e6c2de9		uqsub v9.4h, v15.4h, v12.4h
-#    v9: 0x00000000000000000000000000001fe0
+#             v9: 0x00000000000000000000000000001fe0
 0x~~~~~~~~~~~~~~~~  6ea72e57		uqsub v23.4s, v18.4s, v7.4s
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e312e69		uqsub v9.8b, v19.8b, v17.8b
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e662c54		uqsub v20.8h, v2.8h, v6.8h
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e214a7d		uqxtn b29, h19
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e6149a0		uqxtn h0, s13
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ea14ada		uqxtn s26, d22
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea14be5		uqxtn v5.2s, v31.2d
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e614a7e		uqxtn v30.4h, v19.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e21484f		uqxtn v15.8b, v2.8h
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21487d		uqxtn2 v29.16b, v3.8h
-#   v29: 0x000000000000ffff0000000000000000
+#            v29: 0x000000000000ffff0000000000000000
 0x~~~~~~~~~~~~~~~~  6ea14a2d		uqxtn2 v13.4s, v17.2d
-#   v13: 0x0000000000007e810000000000000000
+#            v13: 0x0000000000007e810000000000000000
 0x~~~~~~~~~~~~~~~~  6e61497c		uqxtn2 v28.8h, v11.4s
-#   v28: 0x0000000000007e810000000000000000
+#            v28: 0x0000000000007e810000000000000000
 0x~~~~~~~~~~~~~~~~  0ea1c9f7		urecpe v23.2s, v15.2s
-#   v23: 0x0000000000000000ffffffffffffffff
+#            v23: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4ea1c8fb		urecpe v27.4s, v7.4s
-#   v27: 0xffffffffffffffffffffffffffffffff
+#            v27: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e3b15e2		urhadd v2.16b, v15.16b, v27.16b
-#    v2: 0x80808080808080808080808080808080
+#             v2: 0x80808080808080808080808080808080
 0x~~~~~~~~~~~~~~~~  2eb2142f		urhadd v15.2s, v1.2s, v18.2s
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e7a1491		urhadd v17.4h, v4.4h, v26.4h
-#   v17: 0x00000000000000000000000000007e81
+#            v17: 0x00000000000000000000000000007e81
 0x~~~~~~~~~~~~~~~~  6eae1762		urhadd v2.4s, v27.4s, v14.4s
-#    v2: 0x80000000800000008000000080000000
+#             v2: 0x80000000800000008000000080000000
 0x~~~~~~~~~~~~~~~~  2e2e1625		urhadd v5.8b, v17.8b, v14.8b
-#    v5: 0x00000000000000000000000000003f41
+#             v5: 0x00000000000000000000000000003f41
 0x~~~~~~~~~~~~~~~~  6e79145e		urhadd v30.8h, v2.8h, v25.8h
-#   v30: 0x40000000400000004000000040000000
+#            v30: 0x40000000400000004000000040000000
 0x~~~~~~~~~~~~~~~~  7efe5784		urshl d4, d28, d30
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e3357ed		urshl v13.16b, v31.16b, v19.16b
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ef556ee		urshl v14.2d, v23.2d, v21.2d
-#   v14: 0x0000000000000000ffffffffffffffff
+#            v14: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ea854ea		urshl v10.2s, v7.2s, v8.2s
-#   v10: 0x00000000000000000000000000000008
+#            v10: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  2e7c56af		urshl v15.4h, v21.4h, v28.4h
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb7551e		urshl v30.4s, v8.4s, v23.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e25569f		urshl v31.8b, v20.8b, v5.8b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7e577e		urshl v30.8h, v27.8h, v30.8h
-#   v30: 0xffffffffffffffffffffffffffffffff
+#            v30: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7f4f25a4		urshr d4, d13, #49
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0f2682		urshr v2.16b, v20.16b, #1
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f4d256d		urshr v13.2d, v11.2d, #51
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f3627f5		urshr v21.2s, v31.2s, #10
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f152635		urshr v21.4h, v17.4h, #11
-#   v21: 0x00000000000000000000000000000010
+#            v21: 0x00000000000000000000000000000010
 0x~~~~~~~~~~~~~~~~  6f3f26c4		urshr v4.4s, v22.4s, #1
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f092420		urshr v0.8b, v1.8b, #7
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1f268d		urshr v13.8h, v20.8h, #1
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea1ca14		ursqrte v20.2s, v16.2s
-#   v20: 0x0000000000000000ffffffffffffffff
+#            v20: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ea1c91c		ursqrte v28.4s, v8.4s
-#   v28: 0xffffffffffffffffffffffffffffffff
+#            v28: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7f53361b		ursra d27, d16, #45
-#   v27: 0x0000000000000000ffffffffffffffff
+#            v27: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6f0d3632		ursra v18.16b, v17.16b, #3
-#   v18: 0x00000000000000000000000000001010
+#            v18: 0x00000000000000000000000000001010
 0x~~~~~~~~~~~~~~~~  6f46379a		ursra v26.2d, v28.2d, #58
-#   v26: 0x00000000000000400000000000000040
+#            v26: 0x00000000000000400000000000000040
 0x~~~~~~~~~~~~~~~~  2f2136c8		ursra v8.2s, v22.2s, #31
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f19349f		ursra v31.4h, v4.4h, #7
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f3e35ff		ursra v31.4s, v15.4s, #2
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0b3423		ursra v3.8b, v1.8b, #5
-#    v3: 0x0000000000000000000000007f007f00
+#             v3: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6f1335d2		ursra v18.8h, v14.8h, #13
-#   v18: 0x00000000000000000008000800081018
+#            v18: 0x00000000000000000008000800081018
 0x~~~~~~~~~~~~~~~~  7ef0441f		ushl d31, d0, d16
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e2244c0		ushl v0.16b, v6.16b, v2.16b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ef24432		ushl v18.2d, v1.2d, v18.2d
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ebd44fb		ushl v27.2s, v7.2s, v29.2s
-#   v27: 0x00000000000000000000000000000008
+#            v27: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  2e6d45ce		ushl v14.4h, v14.4h, v13.4h
-#   v14: 0x0000000000000000ffffffffffffffff
+#            v14: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ea94496		ushl v22.4s, v4.4s, v9.4s
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3b46d7		ushl v23.8b, v22.8b, v27.8b
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e684735		ushl v21.8h, v25.8h, v8.8h
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f35a40b		ushll v11.2d, v0.2s, #21
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f18a622		ushll v2.4s, v17.4h, #8
-#    v2: 0x000000000000000000000000007e8100
+#             v2: 0x000000000000000000000000007e8100
 0x~~~~~~~~~~~~~~~~  2f09a5cb		ushll v11.8h, v14.8b, #1
-#   v11: 0x01fe01fe01fe01fe01fe01fe01fe01fe
+#            v11: 0x01fe01fe01fe01fe01fe01fe01fe01fe
 0x~~~~~~~~~~~~~~~~  6f27a7a8		ushll2 v8.2d, v29.4s, #7
-#    v8: 0x000000000000000000000000007fff80
+#             v8: 0x000000000000000000000000007fff80
 0x~~~~~~~~~~~~~~~~  6f12a53d		ushll2 v29.4s, v9.8h, #2
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0ea705		ushll2 v5.8h, v24.16b, #6
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f4b077c		ushr d28, d27, #53
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f090521		ushr v1.16b, v9.16b, #7
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f550702		ushr v2.2d, v24.2d, #43
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f35073e		ushr v30.2s, v25.2s, #11
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f14074a		ushr v10.4h, v26.4h, #12
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f2204a4		ushr v4.4s, v5.4s, #30
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0f045e		ushr v30.8b, v2.8b, #1
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1e0586		ushr v6.8h, v12.8h, #2
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e2038b3		usqadd b19, b5
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ee03849		usqadd d9, d2
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e603a02		usqadd h2, h16
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ea03870		usqadd s16, s3
-#   v16: 0x0000000000000000000000007f007f00
+#            v16: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6e203bbf		usqadd v31.16b, v29.16b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee03948		usqadd v8.2d, v10.2d
-#    v8: 0x000000000000000000000000007fff80
+#             v8: 0x000000000000000000000000007fff80
 0x~~~~~~~~~~~~~~~~  2ea03932		usqadd v18.2s, v9.2s
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e6039d8		usqadd v24.4h, v14.4h
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea03bca		usqadd v10.4s, v30.4s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e203a90		usqadd v16.8b, v20.8b
-#   v16: 0x0000000000000000000000007e007e00
+#            v16: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  6e603a0c		usqadd v12.8h, v16.8h
-#   v12: 0x0000000000000000000000007e007e00
+#            v12: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  7f5b177c		usra d28, d27, #37
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0b16c5		usra v5.16b, v22.16b, #5
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f5f1662		usra v2.2d, v19.2d, #33
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f2b1400		usra v0.2s, v0.2s, #21
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f1414c7		usra v7.4h, v6.4h, #12
-#    v7: 0x00000000000000000000000000000008
+#             v7: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  6f371624		usra v4.4s, v17.4s, #9
-#    v4: 0x0000000000000000000000000000003f
+#             v4: 0x0000000000000000000000000000003f
 0x~~~~~~~~~~~~~~~~  2f091589		usra v9.8b, v12.8b, #7
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f121763		usra v3.8h, v27.8h, #14
-#    v3: 0x0000000000000000000000007f007f00
+#             v3: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  2ebe219d		usubl v29.2d, v12.2s, v30.2s
-#   v29: 0x0000000000000000000000007e007e00
+#            v29: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  2e66239d		usubl v29.4s, v28.4h, v6.4h
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e2e208c		usubl v12.8h, v4.8b, v14.8b
-#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff40
+#            v12: 0xff01ff01ff01ff01ff01ff01ff01ff40
 0x~~~~~~~~~~~~~~~~  6eb12301		usubl2 v1.2d, v24.4s, v17.4s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e632024		usubl2 v4.4s, v1.8h, v3.8h
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e272097		usubl2 v23.8h, v4.16b, v7.16b
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ebe3289		usubw v9.2d, v20.2d, v30.2s
-#    v9: 0x0000000000000000ffffffffffffffff
+#             v9: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e773214		usubw v20.4s, v16.4s, v23.4h
-#   v20: 0x0000000000000000000000007e007e00
+#            v20: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  2e3d3119		usubw v25.8h, v8.8h, v29.8b
-#   v25: 0x000000000000000000000000007fff80
+#            v25: 0x000000000000000000000000007fff80
 0x~~~~~~~~~~~~~~~~  6ea633b2		usubw2 v18.2d, v29.2d, v6.4s
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7430c6		usubw2 v6.4s, v6.4s, v20.8h
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e303092		usubw2 v18.8h, v4.8h, v16.16b
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f20a6bb		uxtl v27.2d, v21.2s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f10a7e0		uxtl v0.4s, v31.4h
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f08a55b		uxtl v27.8h, v10.8b
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f20a606		uxtl2 v6.2d, v16.4s
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f10a696		uxtl2 v22.4s, v20.8h
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f08a6b4		uxtl2 v20.8h, v21.16b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e11193e		uzp1 v30.16b, v9.16b, v17.16b
-#   v30: 0x000000000000008100000000ffffffff
+#            v30: 0x000000000000008100000000ffffffff
 0x~~~~~~~~~~~~~~~~  4edc1b47		uzp1 v7.2d, v26.2d, v28.2d
-#    v7: 0x00000000000000000000000000000040
+#             v7: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  0e961a1a		uzp1 v26.2s, v16.2s, v22.2s
-#   v26: 0x0000000000000000000000007e007e00
+#            v26: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  0e461a6e		uzp1 v14.4h, v19.4h, v6.4h
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e9e1af1		uzp1 v17.4s, v23.4s, v30.4s
-#   v17: 0x00000081ffffffff0000000000000000
+#            v17: 0x00000081ffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  0e0d1b7c		uzp1 v28.8b, v27.8b, v13.8b
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e4c1831		uzp1 v17.8h, v1.8h, v12.8h
-#   v17: 0xff01ff01ff01ff400000000000000000
+#            v17: 0xff01ff01ff01ff400000000000000000
 0x~~~~~~~~~~~~~~~~  4e1a5a48		uzp2 v8.16b, v18.16b, v26.16b
-#    v8: 0x0000000000007e7e0000000000000000
+#             v8: 0x0000000000007e7e0000000000000000
 0x~~~~~~~~~~~~~~~~  4ed85ad5		uzp2 v21.2d, v22.2d, v24.2d
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e825ab4		uzp2 v20.2s, v21.2s, v2.2s
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e465bf0		uzp2 v16.4h, v31.4h, v6.4h
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e885979		uzp2 v25.4s, v11.4s, v8.4s
-#   v25: 0x000000000000000001fe01fe01fe01fe
+#            v25: 0x000000000000000001fe01fe01fe01fe
 0x~~~~~~~~~~~~~~~~  0e0d5bff		uzp2 v31.8b, v31.8b, v13.8b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e415a28		uzp2 v8.8h, v17.8h, v1.8h
-#    v8: 0x0000000000000000ff01ff0100000000
+#             v8: 0x0000000000000000ff01ff0100000000
 0x~~~~~~~~~~~~~~~~  0ea12b51		xtn v17.2s, v26.2d
-#   v17: 0x0000000000000000000000007e007e00
+#            v17: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  0e612803		xtn v3.4h, v0.4s
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e212912		xtn v18.8b, v8.8h
-#   v18: 0x00000000000000000000000001010000
+#            v18: 0x00000000000000000000000001010000
 0x~~~~~~~~~~~~~~~~  4e212800		xtn2 v0.16b, v0.8h
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea1288f		xtn2 v15.4s, v4.2d
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e612a5f		xtn2 v31.8h, v18.4s
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e063936		zip1 v22.16b, v9.16b, v6.16b
-#   v22: 0x00ff00ff00ff00ff00ff00ff00ff00ff
+#            v22: 0x00ff00ff00ff00ff00ff00ff00ff00ff
 0x~~~~~~~~~~~~~~~~  4ec23977		zip1 v23.2d, v11.2d, v2.2d
-#   v23: 0x000000000000000001fe01fe01fe01fe
+#            v23: 0x000000000000000001fe01fe01fe01fe
 0x~~~~~~~~~~~~~~~~  0e893a1a		zip1 v26.2s, v16.2s, v9.2s
-#   v26: 0x0000000000000000ffffffff00000000
+#            v26: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  0e473921		zip1 v1.4h, v9.4h, v7.4h
-#    v1: 0x00000000000000000000ffff0040ffff
+#             v1: 0x00000000000000000000ffff0040ffff
 0x~~~~~~~~~~~~~~~~  4e943bc0		zip1 v0.4s, v30.4s, v20.4s
-#    v0: 0x000000000000000000000000ffffffff
+#             v0: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  0e0f3a3e		zip1 v30.8b, v17.8b, v15.8b
-#   v30: 0x0000000000000000007e0000007e0000
+#            v30: 0x0000000000000000007e0000007e0000
 0x~~~~~~~~~~~~~~~~  4e423911		zip1 v17.8h, v8.8h, v2.8h
-#   v17: 0x0000ff010000ff010000000000000000
+#            v17: 0x0000ff010000ff010000000000000000
 0x~~~~~~~~~~~~~~~~  4e0b7957		zip2 v23.16b, v10.16b, v11.16b
-#   v23: 0x0100fe000100fe000100fe000100fe00
+#            v23: 0x0100fe000100fe000100fe000100fe00
 0x~~~~~~~~~~~~~~~~  4ece78de		zip2 v30.2d, v6.2d, v14.2d
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e957949		zip2 v9.2s, v10.2s, v21.2s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e5d7b08		zip2 v8.4h, v24.4h, v29.4h
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e977aa0		zip2 v0.4s, v21.4s, v23.4s
-#    v0: 0x0100fe00000000000100fe0000000000
+#             v0: 0x0100fe00000000000100fe0000000000
 0x~~~~~~~~~~~~~~~~  0e1e7af9		zip2 v25.8b, v23.8b, v30.8b
-#   v25: 0x00000000000000000001000000fe0000
+#            v25: 0x00000000000000000001000000fe0000
 0x~~~~~~~~~~~~~~~~  4e5e7947		zip2 v7.8h, v10.8h, v30.8h
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee8d723		fabd v3.2d, v25.2d, v8.2d
-#    v3: 0x00000000000000000001000000fe0000
+#             v3: 0x00000000000000000001000000fe0000
 0x~~~~~~~~~~~~~~~~  2eabd76e		fabd v14.2s, v27.2s, v11.2s
-#   v14: 0x000000000000000001fe01fe01fe01fe
+#            v14: 0x000000000000000001fe01fe01fe01fe
 0x~~~~~~~~~~~~~~~~  6eb2d6c9		fabd v9.4s, v22.4s, v18.4s
-#    v9: 0x00ff00ff00ff00ff00ff00ff0002ff01
+#             v9: 0x00ff00ff00ff00ff00ff00ff0002ff01
 0x~~~~~~~~~~~~~~~~  4ee0fba1		fabs v1.2d, v29.2d
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0faa6		fabs v6.2s, v21.2s
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea0fb2c		fabs v12.4s, v25.4s
-#   v12: 0x00000000000000000001000000fe0000
+#            v12: 0x00000000000000000001000000fe0000
 0x~~~~~~~~~~~~~~~~  6e60ecb2		facge v18.2d, v5.2d, v0.2d
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e26ed6f		facge v15.2s, v11.2s, v6.2s
-#   v15: 0x0000000000000000ffffffffffffffff
+#            v15: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e39ed5e		facge v30.4s, v10.4s, v25.4s
-#   v30: 0xffffffffffffffff0000000000000000
+#            v30: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  6effee1c		facgt v28.2d, v16.2d, v31.2d
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea4ec2f		facgt v15.2s, v1.2s, v4.2s
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eaaec76		facgt v22.4s, v3.4s, v10.4s
-#   v22: 0x0000000000000000ffffffffffffffff
+#            v22: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e78d547		fadd v7.2d, v10.2d, v24.2d
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e27d6ea		fadd v10.2s, v23.2s, v7.2s
-#   v10: 0x00000000000000000100fe000100fe00
+#            v10: 0x00000000000000000100fe000100fe00
 0x~~~~~~~~~~~~~~~~  4e2bd6d0		fadd v16.4s, v22.4s, v11.4s
-#   v16: 0x01fe01fe01fe01feffffffffffffffff
+#            v16: 0x01fe01fe01fe01feffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e70db9b		faddp d27, v28.2d
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e30daf4		faddp s20, v23.2s
-#   v20: 0x0000000000000000000000000180fe00
+#            v20: 0x0000000000000000000000000180fe00
 0x~~~~~~~~~~~~~~~~  6e6bd495		faddp v21.2d, v4.2d, v11.2d
-#   v21: 0x020e01fe01fe01fe0000000000000000
+#            v21: 0x020e01fe01fe01fe0000000000000000
 0x~~~~~~~~~~~~~~~~  2e21d75f		faddp v31.2s, v26.2s, v1.2s
-#   v31: 0x000000000000000000000000ffffffff
+#            v31: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  6e3cd76d		faddp v13.4s, v27.4s, v28.4s
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e74e5b1		fcmeq v17.2d, v13.2d, v20.2d
-#   v17: 0xffffffffffffffff0000000000000000
+#            v17: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  4ee0da18		fcmeq v24.2d, v16.2d, #0.0
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e2ae63a		fcmeq v26.2s, v17.2s, v10.2s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0d898		fcmeq v24.2s, v4.2s, #0.0
-#   v24: 0x0000000000000000ffffffffffffffff
+#            v24: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e2ee488		fcmeq v8.4s, v4.4s, v14.4s
-#    v8: 0xffffffffffffffff0000000000000000
+#             v8: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  4ea0db3a		fcmeq v26.4s, v25.4s, #0.0
-#   v26: 0xffffffffffffffff0000000000000000
+#            v26: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  6e60e41b		fcmge v27.2d, v0.2d, v0.2d
-#   v27: 0xffffffffffffffffffffffffffffffff
+#            v27: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ee0cbd6		fcmge v22.2d, v30.2d, #0.0
-#   v22: 0x0000000000000000ffffffffffffffff
+#            v22: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e39e6a7		fcmge v7.2s, v21.2s, v25.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea0c9ef		fcmge v15.2s, v15.2s, #0.0
-#   v15: 0x0000000000000000ffffffffffffffff
+#            v15: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e3be49d		fcmge v29.4s, v4.4s, v27.4s
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea0cab6		fcmge v22.4s, v21.4s, #0.0
-#   v22: 0xffffffffffffffffffffffffffffffff
+#            v22: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6eefe741		fcmgt v1.2d, v26.2d, v15.2d
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee0caef		fcmgt v15.2d, v23.2d, #0.0
-#   v15: 0xffffffffffffffffffffffffffffffff
+#            v15: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ea6e615		fcmgt v21.2s, v16.2s, v6.2s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0c9a1		fcmgt v1.2s, v13.2s, #0.0
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb9e40e		fcmgt v14.4s, v0.4s, v25.4s
-#   v14: 0xffffffff00000000ffffffff00000000
+#            v14: 0xffffffff00000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  4ea0c90d		fcmgt v13.4s, v8.4s, #0.0
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee0d8c4		fcmle v4.2d, v6.2d, #0.0
-#    v4: 0xffffffffffffffffffffffffffffffff
+#             v4: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ea0dbf8		fcmle v24.2s, v31.2s, #0.0
-#   v24: 0x0000000000000000ffffffff00000000
+#            v24: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  6ea0dae8		fcmle v8.4s, v23.4s, #0.0
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee0e867		fcmlt v7.2d, v3.2d, #0.0
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0eaaf		fcmlt v15.2s, v21.2s, #0.0
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea0e841		fcmlt v1.4s, v2.4s, #0.0
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e61c906		fcvtas v6.2d, v8.2d
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21c921		fcvtas v1.2s, v9.2s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21ca68		fcvtas v8.4s, v19.4s
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e61cbe5		fcvtau v5.2d, v31.2d
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e21cbbc		fcvtau v28.2s, v29.2s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21cb4b		fcvtau v11.4s, v26.4s
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e617b28		fcvtl v8.2d, v25.2s
-#    v8: 0x37a0000000000000381fc00000000000
+#             v8: 0x37a0000000000000381fc00000000000
 0x~~~~~~~~~~~~~~~~  0e2179db		fcvtl v27.4s, v14.4h
-#   v27: 0xffffe000ffffe0000000000000000000
+#            v27: 0xffffe000ffffe0000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6178c1		fcvtl2 v1.2d, v6.4s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e217938		fcvtl2 v24.4s, v9.8h
-#   v24: 0x377f0000377f0000377f0000377f0000
+#            v24: 0x377f0000377f0000377f0000377f0000
 0x~~~~~~~~~~~~~~~~  4e61bb09		fcvtms v9.2d, v24.2d
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21b967		fcvtms v7.2s, v11.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21bab7		fcvtms v23.4s, v21.4s
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e61b82d		fcvtmu v13.2d, v1.2d
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e21b99a		fcvtmu v26.2s, v12.2s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21bab5		fcvtmu v21.4s, v21.4s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e61682b		fcvtn v11.2s, v1.2d
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e216848		fcvtn v8.4h, v2.4s
-#    v8: 0x37a00000000000000000000000000000
+#             v8: 0x37a00000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e616bb8		fcvtn2 v24.4s, v29.2d
-#   v24: 0x0000000000000000377f0000377f0000
+#            v24: 0x0000000000000000377f0000377f0000
 0x~~~~~~~~~~~~~~~~  4e216944		fcvtn2 v4.8h, v10.4s
-#    v4: 0x0000000000000000ffffffffffffffff
+#             v4: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e61a959		fcvtns v25.2d, v10.2d
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21a904		fcvtns v4.2s, v8.2s
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21ab7d		fcvtns v29.4s, v27.4s
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e61ab72		fcvtnu v18.2d, v27.2d
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e21a9cb		fcvtnu v11.2s, v14.2s
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21aabb		fcvtnu v27.4s, v21.4s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee1a8b7		fcvtps v23.2d, v5.2d
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea1a9f8		fcvtps v24.2s, v15.2s
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea1aa65		fcvtps v5.4s, v19.4s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee1aaa3		fcvtpu v3.2d, v21.2d
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea1aaa3		fcvtpu v3.2s, v21.2s
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea1a8e0		fcvtpu v0.4s, v7.4s
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e61697d		fcvtxn v29.2s, v11.2d
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e616b3f		fcvtxn2 v31.4s, v25.2d
-#   v31: 0x000000000000000000000000ffffffff
+#            v31: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  4ee1ba33		fcvtzs v19.2d, v17.2d
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f40ff0c		fcvtzs v12.2d, v24.2d, #64
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea1b849		fcvtzs v9.2s, v2.2s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f23fe85		fcvtzs v5.2s, v20.2s, #29
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea1bb35		fcvtzs v21.4s, v25.4s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f3afc3a		fcvtzs v26.4s, v1.4s, #6
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee1bb2d		fcvtzu v13.2d, v25.2d
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f60fdbc		fcvtzu v28.2d, v13.2d, #32
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea1b8da		fcvtzu v26.2s, v6.2s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f31fd49		fcvtzu v9.2s, v10.2s, #15
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea1b8de		fcvtzu v30.4s, v6.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f2efed3		fcvtzu v19.4s, v22.4s, #18
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e6ffd0f		fdiv v15.2d, v8.2d, v15.2d
-#   v15: 0x7ff00000000000007ff8000000000000
+#            v15: 0x7ff00000000000007ff8000000000000
 0x~~~~~~~~~~~~~~~~  2e3afd2c		fdiv v12.2s, v9.2s, v26.2s
-#   v12: 0x00000000000000007fc000007fc00000
+#            v12: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  6e33fed3		fdiv v19.4s, v22.4s, v19.4s
-#   v19: 0xffffffffffffffffffffffffffffffff
+#            v19: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e68f4f3		fmax v19.2d, v7.2d, v8.2d
-#   v19: 0x37a00000000000000000000000000000
+#            v19: 0x37a00000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e3df599		fmax v25.2s, v12.2s, v29.2s
-#   v25: 0x00000000000000007fc000007fc00000
+#            v25: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  4e25f5e6		fmax v6.4s, v15.4s, v5.4s
-#    v6: 0x7ff00000000000007ff8000000000000
+#             v6: 0x7ff00000000000007ff8000000000000
 0x~~~~~~~~~~~~~~~~  4e74c510		fmaxnm v16.2d, v8.2d, v20.2d
-#   v16: 0x37a0000000000000000000000180fe00
+#            v16: 0x37a0000000000000000000000180fe00
 0x~~~~~~~~~~~~~~~~  0e39c74f		fmaxnm v15.2s, v26.2s, v25.2s
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e30c5d7		fmaxnm v23.4s, v14.4s, v16.4s
-#   v23: 0x37a0000000000000000000000180fe00
+#            v23: 0x37a0000000000000000000000180fe00
 0x~~~~~~~~~~~~~~~~  7e70ca66		fmaxnmp d6, v19.2d
-#    v6: 0x000000000000000037a0000000000000
+#             v6: 0x000000000000000037a0000000000000
 0x~~~~~~~~~~~~~~~~  7e30cb5b		fmaxnmp s27, v26.2s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e77c588		fmaxnmp v8.2d, v12.2d, v23.2d
-#    v8: 0x37a00000000000007fc000007fc00000
+#             v8: 0x37a00000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  2e36c72d		fmaxnmp v13.2s, v25.2s, v22.2s
-#   v13: 0x0000000000000000ffffffff7fc00000
+#            v13: 0x0000000000000000ffffffff7fc00000
 0x~~~~~~~~~~~~~~~~  6e31c56f		fmaxnmp v15.4s, v11.4s, v17.4s
-#   v15: 0xffffffff000000000000000000000000
+#            v15: 0xffffffff000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e30ca7b		fmaxnmv s27, v19.4s
-#   v27: 0x00000000000000000000000037a00000
+#            v27: 0x00000000000000000000000037a00000
 0x~~~~~~~~~~~~~~~~  7e70f9d4		fmaxp d20, v14.2d
-#   v20: 0x0000000000000000ffffffff00000000
+#            v20: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  7e30f852		fmaxp s18, v2.2s
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7ff6e9		fmaxp v9.2d, v23.2d, v31.2d
-#    v9: 0x00000000ffffffff37a0000000000000
+#             v9: 0x00000000ffffffff37a0000000000000
 0x~~~~~~~~~~~~~~~~  2e3ff6c7		fmaxp v7.2s, v22.2s, v31.2s
-#    v7: 0x0000000000000000ffffffffffffffff
+#             v7: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e3df4f2		fmaxp v18.4s, v7.4s, v29.4s
-#   v18: 0x000000000000000000000000ffffffff
+#            v18: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  6e30fbbf		fmaxv s31, v29.4s
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee2f4a2		fmin v2.2d, v5.2d, v2.2d
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eaaf63f		fmin v31.2s, v17.2s, v10.2s
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb0f48a		fmin v10.4s, v4.4s, v16.4s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee5c4d5		fminnm v21.2d, v6.2d, v5.2d
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eaec656		fminnm v22.2s, v18.2s, v14.2s
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea3c7f9		fminnm v25.4s, v31.4s, v3.4s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ef0c829		fminnmp d9, v1.2d
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eb0ca95		fminnmp s21, v20.2s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ef3c6b0		fminnmp v16.2d, v21.2d, v19.2d
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb9c7f0		fminnmp v16.2s, v31.2s, v25.2s
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eafc61a		fminnmp v26.4s, v16.4s, v15.4s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb0c883		fminnmv s3, v4.4s
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ef0fb58		fminp d24, v26.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eb0fa27		fminp s7, v17.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee3f677		fminp v23.2d, v19.2d, v3.2d
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea9f6bd		fminp v29.2s, v21.2s, v9.2s
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb5f700		fminp v0.4s, v24.4s, v21.4s
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb0f919		fminv s25, v8.4s
-#   v25: 0x0000000000000000000000007fc00000
+#            v25: 0x0000000000000000000000007fc00000
 0x~~~~~~~~~~~~~~~~  5fc91817		fmla d23, d0, v9.d[2]
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f8711f7		fmla s23, s15, v7.s[0]
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e66cd71		fmla v17.2d, v11.2d, v6.2d
-#   v17: 0xffffffffffffffff0000000000000000
+#            v17: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  4fcb13de		fmla v30.2d, v30.2d, v11.d[0]
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e26cd93		fmla v19.2s, v12.2s, v6.2s
-#   v19: 0x00000000000000007fc000007fc00000
+#            v19: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  0f891238		fmla v24.2s, v17.2s, v9.s[0]
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2bcd70		fmla v16.4s, v11.4s, v11.4s
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f891afb		fmla v27.4s, v23.4s, v9.s[2]
-#   v27: 0x00000000000000000000000037a00000
+#            v27: 0x00000000000000000000000037a00000
 0x~~~~~~~~~~~~~~~~  5fc653db		fmls d27, d30, v6.d[0]
-#   v27: 0x00000000000000000000000037a00000
+#            v27: 0x00000000000000000000000037a00000
 0x~~~~~~~~~~~~~~~~  5f825215		fmls s21, s16, v2.s[0]
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ef5ce65		fmls v5.2d, v19.2d, v21.2d
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4fcc53d2		fmls v18.2d, v30.2d, v12.d[0]
-#   v18: 0x000000000000000000000000ffffffff
+#            v18: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  0ea7ce05		fmls v5.2s, v16.2s, v7.2s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0fab5243		fmls v3.2s, v18.2s, v11.s[1]
-#    v3: 0x0000000000000000000000007fffffff
+#             v3: 0x0000000000000000000000007fffffff
 0x~~~~~~~~~~~~~~~~  4ebeccbb		fmls v27.4s, v5.4s, v30.4s
-#   v27: 0x00000000000000000000000037a00000
+#            v27: 0x00000000000000000000000037a00000
 0x~~~~~~~~~~~~~~~~  4fa45a9a		fmls v26.4s, v20.4s, v4.s[3]
-#   v26: 0x00000000000000007fffffff00000000
+#            v26: 0x00000000000000007fffffff00000000
 0x~~~~~~~~~~~~~~~~  6f06f6ce		fmov v14.2d, #0xd6 (-0.3438)
-#   v14: 0xbfd6000000000000bfd6000000000000
+#            v14: 0xbfd6000000000000bfd6000000000000
 0x~~~~~~~~~~~~~~~~  0f03f5ba		fmov v26.2s, #0x6d (0.9062)
-#   v26: 0x00000000000000003f6800003f680000
+#            v26: 0x00000000000000003f6800003f680000
 0x~~~~~~~~~~~~~~~~  4f04f69f		fmov v31.4s, #0x94 (-5.0000)
-#   v31: 0xc0a00000c0a00000c0a00000c0a00000
+#            v31: 0xc0a00000c0a00000c0a00000c0a00000
 0x~~~~~~~~~~~~~~~~  9eaf033c		fmov v28.D[1], x25
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  9eae0052		fmov x18, v2.D[1]
-#   x18: 0x0000000000000000
+#            x18: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5fc1988c		fmul d12, d4, v1.d[2]
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5faf983e		fmul s30, s1, v15.s[3]
-#   v30: 0x000000000000000000000000ffffffff
+#            v30: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  6e75dc19		fmul v25.2d, v0.2d, v21.2d
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4fca9b0a		fmul v10.2d, v24.2d, v10.d[2]
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e30df07		fmul v7.2s, v24.2s, v16.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f849a01		fmul v1.2s, v16.2s, v4.s[2]
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e39df85		fmul v5.4s, v28.4s, v25.4s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f88906b		fmul v11.4s, v3.4s, v8.s[0]
-#   v11: 0x7fc000007fc000007fc000007fffffff
+#            v11: 0x7fc000007fc000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  7fc3993c		fmulx d28, d9, v3.d[2]
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7faf92b9		fmulx s25, s21, v15.s[1]
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e68df9f		fmulx v31.2d, v28.2d, v8.2d
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6fc692a3		fmulx v3.2d, v21.2d, v6.d[0]
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e20dc29		fmulx v9.2s, v1.2s, v0.2s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f869370		fmulx v16.2s, v27.2s, v6.s[0]
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e25dc82		fmulx v2.4s, v4.4s, v5.4s
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f8490f2		fmulx v18.4s, v7.4s, v4.s[0]
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee0fb21		fneg v1.2d, v25.2d
-#    v1: 0x80000000000000008000000000000000
+#             v1: 0x80000000000000008000000000000000
 0x~~~~~~~~~~~~~~~~  2ea0fbee		fneg v14.2s, v31.2s
-#   v14: 0x00000000000000008000000080000000
+#            v14: 0x00000000000000008000000080000000
 0x~~~~~~~~~~~~~~~~  6ea0f885		fneg v5.4s, v4.4s
-#    v5: 0x80000000800000008000000080000000
+#             v5: 0x80000000800000008000000080000000
 0x~~~~~~~~~~~~~~~~  4ee1d992		frecpe v18.2d, v12.2d
-#   v18: 0x7ff00000000000007ff0000000000000
+#            v18: 0x7ff00000000000007ff0000000000000
 0x~~~~~~~~~~~~~~~~  0ea1daca		frecpe v10.2s, v22.2s
-#   v10: 0x00000000000000007f8000007f800000
+#            v10: 0x00000000000000007f8000007f800000
 0x~~~~~~~~~~~~~~~~  4ea1d8c5		frecpe v5.4s, v6.4s
-#    v5: 0x7f8000007f800000474c80007f800000
+#             v5: 0x7f8000007f800000474c80007f800000
 0x~~~~~~~~~~~~~~~~  4e7afcf6		frecps v22.2d, v7.2d, v26.2d
-#   v22: 0x40000000000000004000000000000000
+#            v22: 0x40000000000000004000000000000000
 0x~~~~~~~~~~~~~~~~  0e22ff7f		frecps v31.2s, v27.2s, v2.2s
-#   v31: 0x00000000000000004000000040000000
+#            v31: 0x00000000000000004000000040000000
 0x~~~~~~~~~~~~~~~~  4e3bfcd2		frecps v18.4s, v6.4s, v27.4s
-#   v18: 0x40000000400000004000000040000000
+#            v18: 0x40000000400000004000000040000000
 0x~~~~~~~~~~~~~~~~  6e6189ba		frinta v26.2d, v13.2d
-#   v26: 0x0000000000000000ffffffff7fc00000
+#            v26: 0x0000000000000000ffffffff7fc00000
 0x~~~~~~~~~~~~~~~~  2e218b4f		frinta v15.2s, v26.2s
-#   v15: 0x0000000000000000ffffffff7fc00000
+#            v15: 0x0000000000000000ffffffff7fc00000
 0x~~~~~~~~~~~~~~~~  6e218a0d		frinta v13.4s, v16.4s
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee19989		frinti v9.2d, v12.2d
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea19a65		frinti v5.2s, v19.2s
-#    v5: 0x00000000000000007fc000007fc00000
+#             v5: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  6ea1996f		frinti v15.4s, v11.4s
-#   v15: 0x7fc000007fc000007fc000007fffffff
+#            v15: 0x7fc000007fc000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  4e619bb1		frintm v17.2d, v29.2d
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21997e		frintm v30.2s, v11.2s
-#   v30: 0x00000000000000007fc000007fffffff
+#            v30: 0x00000000000000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  4e219a81		frintm v1.4s, v20.4s
-#    v1: 0x0000000000000000ffffffff00000000
+#             v1: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  4e6188d8		frintn v24.2d, v6.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e218a2c		frintn v12.2s, v17.2s
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21897d		frintn v29.4s, v11.4s
-#   v29: 0x7fc000007fc000007fc000007fffffff
+#            v29: 0x7fc000007fc000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  4ee188ea		frintp v10.2d, v7.2d
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea18a4c		frintp v12.2s, v18.2s
-#   v12: 0x00000000000000004000000040000000
+#            v12: 0x00000000000000004000000040000000
 0x~~~~~~~~~~~~~~~~  4ea18bfa		frintp v26.4s, v31.4s
-#   v26: 0x00000000000000004000000040000000
+#            v26: 0x00000000000000004000000040000000
 0x~~~~~~~~~~~~~~~~  6e6199b8		frintx v24.2d, v13.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e219927		frintx v7.2s, v9.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e219ab2		frintx v18.4s, v21.4s
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee19b33		frintz v19.2d, v25.2d
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea1990f		frintz v15.2s, v8.2s
-#   v15: 0x00000000000000007fc000007fc00000
+#            v15: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  4ea19874		frintz v20.4s, v3.4s
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee1d8b7		frsqrte v23.2d, v5.2d
-#   v23: 0x7ff00000000000002006900000000000
+#            v23: 0x7ff00000000000002006900000000000
 0x~~~~~~~~~~~~~~~~  2ea1d8e9		frsqrte v9.2s, v7.2s
-#    v9: 0x00000000000000007f8000007f800000
+#             v9: 0x00000000000000007f8000007f800000
 0x~~~~~~~~~~~~~~~~  6ea1d923		frsqrte v3.4s, v9.4s
-#    v3: 0x7f8000007f8000000000000000000000
+#             v3: 0x7f8000007f8000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eefff99		frsqrts v25.2d, v28.2d, v15.2d
-#   v25: 0x3ff80000000000003ff8000000000000
+#            v25: 0x3ff80000000000003ff8000000000000
 0x~~~~~~~~~~~~~~~~  0eaaff49		frsqrts v9.2s, v26.2s, v10.2s
-#    v9: 0x00000000000000003fc000003fc00000
+#             v9: 0x00000000000000003fc000003fc00000
 0x~~~~~~~~~~~~~~~~  4eaafc25		frsqrts v5.4s, v1.4s, v10.4s
-#    v5: 0x3fc000003fc000007fffffff3fc00000
+#             v5: 0x3fc000003fc000007fffffff3fc00000
 0x~~~~~~~~~~~~~~~~  6ee1fa46		fsqrt v6.2d, v18.2d
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea1fa46		fsqrt v6.2s, v18.2s
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea1fbe0		fsqrt v0.4s, v31.4s
-#    v0: 0x00000000000000003fb504f33fb504f3
+#             v0: 0x00000000000000003fb504f33fb504f3
 0x~~~~~~~~~~~~~~~~  4effd7df		fsub v31.2d, v30.2d, v31.2d
-#   v31: 0x00000000000000007fc000007fffffff
+#            v31: 0x00000000000000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  0ea6d50b		fsub v11.2s, v8.2s, v6.2s
-#   v11: 0x00000000000000007fc000007fc00000
+#            v11: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  4ebfd410		fsub v16.4s, v0.4s, v31.4s
-#   v16: 0x00000000000000007fc000007fffffff
+#            v16: 0x00000000000000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  4e61dbf9		scvtf v25.2d, v31.2d
-#   v25: 0x000000000000000043dff00000200000
+#            v25: 0x000000000000000043dff00000200000
 0x~~~~~~~~~~~~~~~~  4f53e5aa		scvtf v10.2d, v13.2d, #45
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21d9ea		scvtf v10.2s, v15.2s
-#   v10: 0x00000000000000004eff80004eff8000
+#            v10: 0x00000000000000004eff80004eff8000
 0x~~~~~~~~~~~~~~~~  0f25e492		scvtf v18.2s, v4.2s, #27
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21d8b1		scvtf v17.4s, v5.4s
-#   v17: 0x4e7f00004e7f00004f0000004e7f0000
+#            v17: 0x4e7f00004e7f00004f0000004e7f0000
 0x~~~~~~~~~~~~~~~~  4f28e72b		scvtf v11.4s, v25.4s, #24
-#   v11: 0x00000000000000004287bfe03e000000
+#            v11: 0x00000000000000004287bfe03e000000
 0x~~~~~~~~~~~~~~~~  6e61d869		ucvtf v9.2d, v3.2d
-#    v9: 0x43dfe000001fe0000000000000000000
+#             v9: 0x43dfe000001fe0000000000000000000
 0x~~~~~~~~~~~~~~~~  6f52e7da		ucvtf v26.2d, v30.2d, #46
-#   v26: 0x000000000000000040fff00000200000
+#            v26: 0x000000000000000040fff00000200000
 0x~~~~~~~~~~~~~~~~  2e21d88b		ucvtf v11.2s, v4.2s
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25
-#   v29: 0x7fc000007fc000000000000000000000
+#            v29: 0x7fc000007fc000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s
-#   v22: 0x4effe000000000004e001a4000000000
+#            v22: 0x4effe000000000004e001a4000000000
 0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25
-#   v18: 0x4207bfc03d7f00000000000000000000
+#            v18: 0x4207bfc03d7f00000000000000000000
+0x~~~~~~~~~~~~~~~~  e5810c0c		str p12, [x0, #11, mul vl]
+#      p12<15:0>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p12<31:16>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p12<47:32>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p12<63:48>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p12<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5810c0d		str p13, [x0, #11, mul vl]
+#      p13<15:0>: 0b 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p13<31:16>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p13<47:32>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p13<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p13<79:64>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5810c0e		str p14, [x0, #11, mul vl]
+#      p14<15:0>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p14<31:16>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p14<47:32>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p14<63:48>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p14<79:64>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5810c0f		str p15, [x0, #11, mul vl]
+#      p15<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p15<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 -> 0x~~~~~~~~~~~~~~~~
+#     p15<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 -> 0x~~~~~~~~~~~~~~~~
+#     p15<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p15<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85810c08		ldr p8, [x0, #11, mul vl]
+#       p8<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#      p8<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85810c09		ldr p9, [x0, #11, mul vl]
+#       p9<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#      p9<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85810c0a		ldr p10, [x0, #11, mul vl]
+#      p10<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#     p10<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85810c0b		ldr p11, [x0, #11, mul vl]
+#      p11<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#     p11<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5814c00		str z0, [x0, #11, mul vl]
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3 -> 0x~~~~~~~~~~~~~~~~
+#    z0<255:128>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<383:256>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<511:384>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5814c01		str z1, [x0, #11, mul vl]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<383:256>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<639:512>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5814c02		str z2, [x0, #11, mul vl]
+#      z2<127:0>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<383:256>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5814c03		str z3, [x0, #11, mul vl]
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<255:128>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<383:256>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<511:384>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<639:512>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85814c14		ldr z20, [x0, #11, mul vl]
+#     z20<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85814c15		ldr z21, [x0, #11, mul vl]
+#     z21<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85814c16		ldr z22, [x0, #11, mul vl]
+#     z22<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85814c17		ldr z23, [x0, #11, mul vl]
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e403e800		st1b {z0.b}, p2, [x0, #3, mul vl]
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ║ ╙─ 0xf3 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ╙─── 0x04 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ╙───── 0xb5 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ╙───────── 0xf3 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ╙─────────── 0x04 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ╙───────────── 0xb5 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<255:128>: 0x00000000000000000000000000000000
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<383:256>: 0x00000000000000000000000000000000
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4a3e401		st1h {z1.h}, p1, [x0, #3, mul vl]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000 (..., 0.000, 0.000, ..., nan, nan, ..., 0.000)
+#                          ║   ║       ║   ║       ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000, 0.000, ..., 0.000, 0.000)
+#                      ║   ║       ║   ║       ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, ..., 0.000, 0.000, ..., 0.000)
+#                          ║   ║       ║   ║       ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000, 0.000, ..., 0.000, 0.000)
+#                      ║   ║       ║   ║       ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5434402		st1w {z2.s}, p1, [x0, x3, lsl #2]
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5e3e803		st1d {z3.d}, p2, [x0, #3, mul vl]
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7f8000007f800000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a403a414		ld1b {z20.b}, p1/z, [x0, #3, mul vl]
+#     z20<127:0>: 0x7f000000008000000000000000000000
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ╙───────────────────── 0x80 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x7f <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x2f000000000029000000000023000000
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4a24815		ld1h {z21.h}, p2/z, [x0, x2, lsl #1]
+#     z21<127:0>: 0x0d0c0b0a09080706050403020100fffe (0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 (...)
+#
+#   z21<639:512>: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a543a416		ld1w {z22.s}, p1/z, [x0, #3, mul vl]
+#     z22<127:0>: 0x7f800000000000000000000000000000 (inf, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x7f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (...)
+#
+#   z22<511:384>: 0x2f2e0000000000000000000023220000 (1.583e-10, ..., 0.000, 8.782e-18)
+#                          ║               ║       ╙─ 0x23220000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e0000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5e3a417		ld1d {z23.d}, p1/z, [x0, #3, mul vl]
+#     z23<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (...)
+#
+#   z23<511:384>: 0x00000000000000000000000023220000 (..., 2.912e-315)
+#                                                  ╙─ 0x0000000023220000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e423e402		st1b {z2.h}, p1, [x0, #3, mul vl]
+#      z2<127:0>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e443e803		st1b {z3.s}, p2, [x0, #3, mul vl]
+#      z3<127:0>: 0x7f8000007f8000000000000000000000
+#                          ║       ║       ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z3<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z3<383:256>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z3<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e463e804		st1b {z4.d}, p2, [x0, #3, mul vl]
+#      z4<127:0>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4c3e400		st1h {z0.s}, p1, [x0, #3, mul vl]
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3
+#                          ║               ║       ╙─ 0x04f3 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x04f3 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4e24401		st1h {z1.d}, p1, [x0, x2, lsl #1]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000
+#                                                  ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e563e402		st1w {z2.d}, p1, [x0, #3, mul vl]
+#      z2<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4224414		ld1b {z20.h}, p1/z, [x0, x2]
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#                          ║   ║       ║   ║       ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000230022000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a443a415		ld1b {z21.s}, p1/z, [x0, #3, mul vl]
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a463a416		ld1b {z22.d}, p1/z, [x0, #3, mul vl]
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4c3a817		ld1h {z23.s}, p2/z, [x0, #3, mul vl]
+#     z23<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4e3a818		ld1h {z24.d}, p2/z, [x0, #3, mul vl]
+#     z24<127:0>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a563a414		ld1w {z20.d}, p1/z, [x0, #3, mul vl]
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5c3a415		ld1sb {z21.h}, p1/z, [x0, #3, mul vl]
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5a3a416		ld1sb {z22.s}, p1/z, [x0, #3, mul vl]
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5824817		ld1sb {z23.d}, p2/z, [x0, x2]
+#     z23<127:0>: 0x0000000000000000000000000000007f
+#                                  ║               ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a523a818		ld1sh {z24.s}, p2/z, [x0, #3, mul vl]
+#     z24<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a503a414		ld1sh {z20.d}, p1/z, [x0, #3, mul vl]
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a483a415		ld1sw {z21.d}, p1/z, [x0, #3, mul vl]
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e432f000		st2b {z0.b, z1.b}, p4, [x0, #4, mul vl]
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3
+#      z1<127:0>: 0x0000000000000000ffffffff00000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'f3 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'04 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'b5 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'3f -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0xff'f3 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0xff'b5 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0xff'3f -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<255:128>: 0x00000000000000000000000000000000
+#    z1<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<383:256>: 0x00000000000000000000000000000000
+#    z1<383:256>: 0x00000000000000000000000000000000
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ╙─────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<511:384>: 0x00000000000000000000000000000000
+#    z1<511:384>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000
+#    z1<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4b2f001		st2h {z1.h, z2.h}, p4, [x0, #4, mul vl]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000 (0.000, 0.000, 0.000, 0.000, nan, nan, 0.000, 0.000)
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, nan, nan, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'ffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'ffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5226c02		st2w {z2.s, z3.s}, p3, [x0, x2, lsl #2]
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f800000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x7f800000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z3<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#                                  ║       ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ║       ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5b2f003		st2d {z3.d, z4.d}, p4, [x0, #4, mul vl]
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#      z4<127:0>: 0x00000000000000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'7f8000007f800000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a422d414		ld2b {z20.b, z21.b}, p5/z, [x0, x2]
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x000000000000002f0000290000230000
+#   z21<255:128>: 0x00000000000000002e00000000002200
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x22'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x2e'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x0000007f007f00000000000000000000
+#   z21<383:256>: 0x00000000800000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x80'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<511:384>: 0x00000000000000000000000000000000
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4a2f815		ld2h {z21.h, z22.h}, p6/z, [x0, #4, mul vl]
+#     z21<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#     z22<127:0>: 0x000000007f807f800000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a522f816		ld2w {z22.s, z23.s}, p6/z, [x0, #4, mul vl]
+#     z22<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#     z23<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f800000'7f800000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5a2f417		ld2d {z23.d, z24.d}, p5/z, [x0, #4, mul vl]
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#     z24<127:0>: 0x00000000000000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'7f8000007f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z24<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e451f004		st3b {z4.b, z5.b, z6.b}, p4, [x0, #3, mul vl]
+#      z4<127:0>: 0x00000000000000000000000000000000
+#      z5<127:0>: 0x3fc000003fc000007fffffff3fc00000
+#      z6<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'c0'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'3f'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0x00'ff'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'ff'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'7f'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'c0'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'c0'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'3f'00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<255:128>: 0x00000000000000000000000000000000
+#    z5<255:128>: 0x00000000000000000000000000000000
+#    z6<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<383:256>: 0x00000000000000000000000000000000
+#    z5<383:256>: 0x00000000000000000000000000000000
+#    z6<383:256>: 0x00000000000000000000000000000000
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ╙─────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<511:384>: 0x00000000000000000000000000000000
+#    z5<511:384>: 0x00000000000000000000000000000000
+#    z6<511:384>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<639:512>: 0x00000000000000000000000000000000
+#    z5<639:512>: 0x00000000000000000000000000000000
+#    z6<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4d1f005		st3h {z5.h, z6.h, z7.h}, p4, [x0, #3, mul vl]
+#      z5<127:0>: 0x3fc000003fc000007fffffff3fc00000 (1.938, 0.000, 1.938, 0.000, nan, nan, 1.938, 0.000)
+#      z6<127:0>: 0x00000000000000000000000000000000 (1.938, 0.000, 1.938, 0.000, nan, nan, 1.938, 0.000)
+#      z7<127:0>: 0x00000000000000000000000000000000 (1.938, 0.000, 1.938, 0.000, nan, nan, 1.938, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'3fc0 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'ffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'7fff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'3fc0 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'3fc0 -> 0x~~~~~~~~~~~~~~~~
+#    z5<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z6<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z7<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z5<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z6<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z7<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z5<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z6<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z7<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z5<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z6<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z7<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e551ec06		st3w {z6.s, z7.s, z8.s}, p3, [x0, #3, mul vl]
+#      z6<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z8<127:0>: 0x37a00000000000007fc000007fc00000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x7fc00000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x37a00000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z6<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z7<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z8<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z6<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z7<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z8<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#                                  ║       ║       ╙─ 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ║       ╙───────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z6<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z7<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z8<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5c27007		st3d {z7.d, z8.d, z9.d}, p4, [x0, x2, lsl #3]
+#      z7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#      z8<127:0>: 0x37a00000000000007fc000007fc00000 (0.000, 0.000)
+#      z9<127:0>: 0x43dfe000001fe0000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'7fc000007fc00000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x43dfe000001fe000'37a0000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z7<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z8<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z9<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z7<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z8<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z9<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z7<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z8<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z9<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z7<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z8<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z9<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a441f418		ld3b {z24.b, z25.b, z26.b}, p5/z, [x0, #3, mul vl]
+#     z24<127:0>: 0x0000000000000000000000ff00000000
+#     z25<127:0>: 0xa000000000000000000000ffc0000000
+#     z26<127:0>: 0x3700000000000000000000007f000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x7f'c0'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'ff'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x37'a0'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<639:512>: 0x00000000000000000000000000000000
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4c2d819		ld3h {z25.h, z26.h, z27.h}, p6/z, [x0, x2, lsl #1]
+#     z25<127:0>: 0x292823221d1c17160000000000000000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z26<127:0>: 0x2b2a25241f1e191813120d0c07060100 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z27<127:0>: 0x2d2c272621201b1a1514000009080000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0100'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0908'0706'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0d0c'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514'1312'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1b1a'1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2120'1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x595853524d4c474641403b3a35342f2e (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z26<255:128>: 0x5b5a55544f4e494843423d3c37363130 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z27<255:128>: 0x5d5c575651504b4a45443f3e39383332 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3332'3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3938'3736'3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544'4342'4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4b4a'4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5150'4f4e'4d4c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c'5b5a'5958 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x898883827d7c777671706b6a65645f5e (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z26<383:256>: 0x8b8a85847f7e797873726d6c67666160 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z27<383:256>: 0x8d8c878681807b7a75746f6e69686362 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x6362'6160'5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6968'6766'6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6f6e'6d6c'6b6a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x7574'7372'7170 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7b7a'7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x8180'7f7e'7d7c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x8786'8584'8382 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8d8c'8b8a'8988 <- 0x~~~~~~~~~~~~~~~~
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+#   z27<511:384>: 0xbdbcb7b6b1b0abaaa5a49f9e99989392 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x9392'9190'8f8e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x9998'9796'9594 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x9f9e'9d9c'9b9a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xa5a4'a3a2'a1a0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xabaa'a9a8'a7a6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xb1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xb7b6'b5b4'b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xbdbc'bbba'b9b8 <- 0x~~~~~~~~~~~~~~~~
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+#   z26<639:512>: 0xebeae5e4dfded9d8d3d2cdccc7c6c1c0 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#   z27<639:512>: 0xedece7e6e1e0dbdad5d4cfcec9c8c3c2 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xc3c2'c1c0'bfbe <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xc9c8'c7c6'c5c4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xcfce'cdcc'cbca <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd5d4'd3d2'd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xdbda'd9d8'd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xe1e0'dfde'dddc <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xe7e6'e5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a541f81a		ld3w {z26.s, z27.s, z28.s}, p6/z, [x0, #3, mul vl]
+#     z26<127:0>: 0x00000000000000000000ffff00000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z27<127:0>: 0x00000000000000007fff000000000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z28<127:0>: 0x37a0000000000000000000007fc00000 (0.000, 0.000, 9.183e-41, 0.000)
+#                          ║       ║       ║       ╙─ 0x7fc00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'7fff0000'0000ffff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x37a00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5c1f41b		ld3d {z27.d, z28.d, z29.d}, p5/z, [x0, #3, mul vl]
+#     z27<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000ffff7fc00000 (0.000, 0.000)
+#     z29<127:0>: 0x37a0000000000000000000007fff0000 (0.000, 0.000)
+#                                  ║               ╙─ 0x000000007fff0000'0000ffff7fc00000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x37a0000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e471f01f		st4b {z31.b, z0.b, z1.b, z2.b}, p4, [x0, #4, mul vl]
+#     z31<127:0>: 0x00000000000000007fc000007fffffff
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3
+#      z1<127:0>: 0x0000000000000000ffffffff00000000
+#      z2<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ╙───────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║ ╙─────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4f1f000		st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'04f3 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'3fb5 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'ffff'04f3 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'ffff'3fb5 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z1<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z3<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e571ec01		st4w {z1.s, z2.s, z3.s, z4.s}, p3, [x0, #4, mul vl]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000 (0.000, 0.000, ..., 0.000)
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z4<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'7f800000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'7f800000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z4<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z2<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z3<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z4<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#                                  ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ║       ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z4<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5e27002		st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (0.000, 0.000)
+#      z4<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#      z5<127:0>: 0x3fc000003fc000007fffffff3fc00000 (0.000, 0.000)
+#                                  ║               ╙─ 0x7fffffff3fc00000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3fc000003fc00000'0000000000000000'7f8000007f800000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z3<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z3<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a461f419		ld4b {z25.b, z26.b, z27.b, z28.b}, p5/z, [x0, #4, mul vl]
+#     z25<127:0>: 0x0000000000000000000000f300000000
+#     z26<127:0>: 0x00000000000000000000000400000000
+#     z27<127:0>: 0x0080000000800000000000ff00000000
+#     z28<127:0>: 0x007f0000007f0000000000ff00000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0xff'ff'04'f3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#   z27<255:128>: 0x00000000000000000000000000000000
+#   z28<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#   z27<383:256>: 0x00000000000000000000000000000000
+#   z28<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#   z27<511:384>: 0x00000000000000000000000000000000
+#   z28<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#   z27<639:512>: 0x00000000000000000000000000000000
+#   z28<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4e1f81a		ld4h {z26.h, z27.h, z28.h, z29.h}, p6/z, [x0, #4, mul vl]
+#     z26<127:0>: 0x00000000000000003fb504f300000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z27<127:0>: 0x7f8000007f800000ffffffff00000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'ffff'04f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'ffff'3fb5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
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+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
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+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
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+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
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+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a562d81b		ld4w {z27.s, z28.s, z29.s, z30.s}, p6/z, [x0, x2, lsl #2]
+#     z27<127:0>: 0x2f2e2d2c000000000000000000000000 (1.584e-10, 0.000, 0.000, 0.000)
+#     z28<127:0>: 0x33323130000000007f80000000000000 (1.584e-10, 0.000, 0.000, 0.000)
+#     z29<127:0>: 0x00000000000000000000000007060504 (1.584e-10, 0.000, 0.000, 0.000)
+#     z30<127:0>: 0x00000000000000007f8000000b0a0908 (1.584e-10, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7f800000'00000000'7f800000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z29<255:128>: 0x00000000000000005756555400000000 (0.000, 0.000, 0.000, 0.000)
+#   z30<255:128>: 0x00000000000000005b5a595800000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5b5a5958'57565554'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<383:256>: 0xafaeadac9f9e9d9c8f8e8d8c7f7e7d7c (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z28<383:256>: 0xb3b2b1b0a3a2a1a09392919083828180 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z29<383:256>: 0xb7b6b5b4a7a6a5a49796959487868584 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z30<383:256>: 0xbbbab9b8abaaa9a89b9a99988b8a8988 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#                          ║       ║       ║       ╙─ 0x8b8a8988'87868584'83828180'7f7e7d7c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x9b9a9998'97969594'93929190'8f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xabaaa9a8'a7a6a5a4'a3a2a1a0'9f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xbbbab9b8'b7b6b5b4'b3b2b1b0'afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   z27<511:384>: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z28<511:384>: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z29<511:384>: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z30<511:384>: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#   z27<639:512>: 0x2f2e2d2c1f1e1d1c0f0e0d0cfffefdfc (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z28<639:512>: 0x33323130232221201312111003020100 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z29<639:512>: 0x37363534272625241716151407060504 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z30<639:512>: 0x3b3a39382b2a29281b1a19180b0a0908 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'03020100'fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1b1a1918'17161514'13121110'0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928'27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3b3a3938'37363534'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5e1f41c		ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]
+#     z28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z29<127:0>: 0x000000007f8000000000000000000000 (0.000, 0.000)
+#     z30<127:0>: 0x000000000000000000000000ffff04f3 (0.000, 0.000)
+#     z31<127:0>: 0x000000007f80000000000000ffff3fb5 (0.000, 0.000)
+#                                  ║               ╙─ 0x00000000ffff3fb5'00000000ffff04f3'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x000000007f800000'0000000000000000'000000007f800000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z30<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z31<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  d65f03c0		ret
 # Branch to 0x~~~~~~~~~~~~~~~~.
diff --git a/test/test-trace-reference/log-all-colour b/test/test-trace-reference/log-all-colour
index f70031f9..a844829f 100644
--- a/test/test-trace-reference/log-all-colour
+++ b/test/test-trace-reference/log-all-colour
@@ -1,119 +1,332 @@
-#    x0: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0300003000300303
-#    x4: 0x0400004000400404
-#    x5: 0x0500005000500505
-#    x6: 0x0600006000600606
-#    x7: 0x0700007000700707
-#    x8: 0x0800008000800808
-#    x9: 0x0900009000900909
-#   x10: 0x0a0000a000a00a0a
-#   x11: 0x0b0000b000b00b0b
-#   x12: 0x0c0000c000c00c0c
-#   x13: 0x0d0000d000d00d0d
-#   x14: 0x0e0000e000e00e0e
-#   x15: 0x0f0000f000f00f0f
-#   x16: 0x1000010001001010
-#   x17: 0x1100011001101111
-#   x18: 0x1200012001201212
-#   x19: 0x1300013001301313
-#   x20: 0x1400014001401414
-#   x21: 0x1500015001501515
-#   x22: 0x1600016001601616
-#   x23: 0x1700017001701717
-#   x24: 0x1800018001801818
-#   x25: 0x1900019001901919
-#   x26: 0x1a0001a001a01a1a
-#   x27: 0x1b0001b001b01b1b
-#   x28: 0x1c0001c001c01c1c
-#   x29: 0x1d0001d001d01d1d
-#    lr: 0x0000000000000000
-#    sp: 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00055555005555550000000000000000
-#    v1: 0x3ff0d2c63fcb514c3ff587933f9e0419
-#    v2: 0x4000d2c6404b514c40058793401e0419
-#    v3: 0x401570fb40385373401025ae406d0626
-#    v4: 0x4010d2c640cb514c40158793409e0419
-#    v5: 0x401fbc2d4090d04a401ae97840c5851f
-#    v6: 0x402570fb40b85373402025ae40ed0626
-#    v7: 0x402783f4415f16c34022d6a1410a4396
-#    v8: 0x4020d2c6414b514c40258793411e0419
-#    v9: 0x402d6dd3416491c9402838864131c49c
-#   v10: 0x402fbc2d4110d04a402ae9784145851f
-#   v11: 0x4028cf3e410c10f7402d9a6b415945a2
-#   v12: 0x403570fb41385373403025ae416d0626
-#   v13: 0x40342b7d41d5360140317e2841806354
-#   v14: 0x403783f441df16c34032d6a1418a4396
-#   v15: 0x40317a4f41c1768240342f1a419423d7
-#   v16: 0x4030d2c641cb514c40358793419e0419
-#   v17: 0x4033b55841f2b10e4036e00d41a7e45b
-#   v18: 0x403d6dd341e491c94038388641b1c49c
-#   v19: 0x403cc5aa41eef18b403990ff41bba4de
-#   v20: 0x403fbc2d4190d04a403ae97841c5851f
-#   v21: 0x403914a7419a3034403c41f241cf6561
-#   v22: 0x4038cf3e418c10f7403d9a6b41d945a2
-#   v23: 0x403ba7b141b670b1403ef2e441e325e4
-#   v24: 0x404570fb41b85373404025ae41ed0626
-#   v25: 0x404584be41a3b3324040d1eb41f6e667
-#   v26: 0x40442b7d4255360140417e2842006354
-#   v27: 0x40477f314250062040422a6442055375
-#   v28: 0x404783f4425f16c34042d6a1420a4396
-#   v29: 0x4046d78b425a66e2404382de420f33b7
-#   v30: 0x40417a4f4241768240442f1a421423d7
-#   v31: 0x40418e02424c46ad4044db57421913f8
+#             x0: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~
+#             x3: 0x0300003000300303
+#             x4: 0x0400004000400404
+#             x5: 0x0500005000500505
+#             x6: 0x0600006000600606
+#             x7: 0x0700007000700707
+#             x8: 0x0800008000800808
+#             x9: 0x0900009000900909
+#            x10: 0x0a0000a000a00a0a
+#            x11: 0x0b0000b000b00b0b
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+#            x13: 0x0d0000d000d00d0d
+#            x14: 0x0e0000e000e00e0e
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+#            x17: 0x1100011001101111
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+#            x20: 0x1400014001401414
+#            x21: 0x1500015001501515
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+#            x25: 0x1900019001901919
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+#            x27: 0x1b0001b001b01b1b
+#            x28: 0x1c0001c001c01c1c
+#            x29: 0x1d0001d001d01d1d
+#             lr: 0x0000000000000000
+#             sp: 0x~~~~~~~~~~~~~~~~
+#      z0<127:0>: 0x47e000017f03380147e000007f023800
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+#   z22<639:512>: 0x494000098a0b9009494000088a0a9008
+#     z23<127:0>: 0x495000018a839401495000008a829400
+#   z23<255:128>: 0x495000038a839403495000028a829402
+#   z23<383:256>: 0x495000058a879405495000048a869404
+#   z23<511:384>: 0x495000078a879407495000068a869406
+#   z23<639:512>: 0x495000098a8b9409495000088a8a9408
+#     z24<127:0>: 0x496000018b039801496000008b029800
+#   z24<255:128>: 0x496000038b039803496000028b029802
+#   z24<383:256>: 0x496000058b079805496000048b069804
+#   z24<511:384>: 0x496000078b079807496000068b069806
+#   z24<639:512>: 0x496000098b0b9809496000088b0a9808
+#     z25<127:0>: 0x497000018b839c01497000008b829c00
+#   z25<255:128>: 0x497000038b839c03497000028b829c02
+#   z25<383:256>: 0x497000058b879c05497000048b869c04
+#   z25<511:384>: 0x497000078b879c07497000068b869c06
+#   z25<639:512>: 0x497000098b8b9c09497000088b8a9c08
+#     z26<127:0>: 0x498000018c03a001498000008c02a000
+#   z26<255:128>: 0x498000038c03a003498000028c02a002
+#   z26<383:256>: 0x498000058c07a005498000048c06a004
+#   z26<511:384>: 0x498000078c07a007498000068c06a006
+#   z26<639:512>: 0x498000098c0ba009498000088c0aa008
+#     z27<127:0>: 0x499000018c83a401499000008c82a400
+#   z27<255:128>: 0x499000038c83a403499000028c82a402
+#   z27<383:256>: 0x499000058c87a405499000048c86a404
+#   z27<511:384>: 0x499000078c87a407499000068c86a406
+#   z27<639:512>: 0x499000098c8ba409499000088c8aa408
+#     z28<127:0>: 0x49a000018d03a80149a000008d02a800
+#   z28<255:128>: 0x49a000038d03a80349a000028d02a802
+#   z28<383:256>: 0x49a000058d07a80549a000048d06a804
+#   z28<511:384>: 0x49a000078d07a80749a000068d06a806
+#   z28<639:512>: 0x49a000098d0ba80949a000088d0aa808
+#     z29<127:0>: 0x49b000018d83ac0149b000008d82ac00
+#   z29<255:128>: 0x49b000038d83ac0349b000028d82ac02
+#   z29<383:256>: 0x49b000058d87ac0549b000048d86ac04
+#   z29<511:384>: 0x49b000078d87ac0749b000068d86ac06
+#   z29<639:512>: 0x49b000098d8bac0949b000088d8aac08
+#     z30<127:0>: 0x49c000018e03b00149c000008e02b000
+#   z30<255:128>: 0x49c000038e03b00349c000028e02b002
+#   z30<383:256>: 0x49c000058e07b00549c000048e06b004
+#   z30<511:384>: 0x49c000078e07b00749c000068e06b006
+#   z30<639:512>: 0x49c000098e0bb00949c000088e0ab008
+#     z31<127:0>: 0x49d000018e83b40149d000008e82b400
+#   z31<255:128>: 0x49d000038e83b40349d000028e82b402
+#   z31<383:256>: 0x49d000058e87b40549d000048e86b404
+#   z31<511:384>: 0x49d000078e87b40749d000068e86b406
+#   z31<639:512>: 0x49d000098e8bb40949d000088e8ab408
+#       p0<15:0>: 0b 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
+#      p0<31:16>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#      p0<47:32>: 0b 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
+#      p0<63:48>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#      p0<79:64>: 0b 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
+#       p1<15:0>: 0b 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
+#      p1<31:16>: 0b 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1
+#      p1<47:32>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#      p1<63:48>: 0b 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1
+#      p1<79:64>: 0b 1 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1
+#       p2<15:0>: 0b 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
+#      p2<31:16>: 0b 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
+#      p2<47:32>: 0b 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
+#      p2<63:48>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#      p2<79:64>: 0b 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
+#       p3<15:0>: 0b 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1
+#      p3<31:16>: 0b 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1
+#      p3<47:32>: 0b 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1
+#      p3<63:48>: 0b 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1
+#      p3<79:64>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#       p4<15:0>: 0b 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1
+#      p4<31:16>: 0b 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1
+#      p4<47:32>: 0b 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1
+#      p4<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1
+#      p4<79:64>: 0b 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1
+#       p5<15:0>: 0b 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1
+#      p5<31:16>: 0b 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1
+#      p5<47:32>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1
+#      p5<63:48>: 0b 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0
+#      p5<79:64>: 0b 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1
+#       p6<15:0>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<31:16>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<47:32>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<63:48>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<79:64>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#       p7<15:0>: 0b 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
+#      p7<31:16>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1
+#      p7<47:32>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1
+#      p7<63:48>: 0b 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#      p7<79:64>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#       p8<15:0>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+#      p8<31:16>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1
+#      p8<47:32>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p8<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1
+#      p8<79:64>: 0b 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#       p9<15:0>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
+#      p9<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#      p9<47:32>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0
+#      p9<63:48>: 0b 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
+#      p9<79:64>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1
+#      p10<15:0>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p10<31:16>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#     p10<47:32>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#     p10<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p10<79:64>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p11<15:0>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
+#     p11<31:16>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+#     p11<47:32>: 0b 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
+#     p11<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#     p11<79:64>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0
+#      p12<15:0>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p12<31:16>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p12<47:32>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+#     p12<63:48>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#     p12<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#      p13<15:0>: 0b 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<31:16>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<47:32>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p13<79:64>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
+#      p14<15:0>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<31:16>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<47:32>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<63:48>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<79:64>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#      p15<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p15<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
+#     p15<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
+#     p15<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
+#     p15<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#      FFR<15:0>: 0b 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
+#     FFR<31:16>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<47:32>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<63:48>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<79:64>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
 0x~~~~~~~~~~~~~~~~  1a050083		adc w3, w4, w5
-#    x3: 0x0000000000900909
+#             w3:         0x00900909
 0x~~~~~~~~~~~~~~~~  9a0800e6		adc x6, x7, x8
-#    x6: 0x0f0000f000f00f0f
+#             x6: 0x0f0000f000f00f0f
 0x~~~~~~~~~~~~~~~~  3a0b0149		adcs w9, w10, w11
 # NZCV: N:0 Z:0 C:0 V:0
-#    x9: 0x0000000001501515
+#             w9:         0x01501515
 0x~~~~~~~~~~~~~~~~  ba0e01ac		adcs x12, x13, x14
 # NZCV: N:0 Z:0 C:0 V:0
-#   x12: 0x1b0001b001b01b1b
+#            x12: 0x1b0001b001b01b1b
 0x~~~~~~~~~~~~~~~~  0b11020f		add w15, w16, w17
-#   x15: 0x0000000002102121
+#            w15:         0x02102121
 0x~~~~~~~~~~~~~~~~  8b140272		add x18, x19, x20
-#   x18: 0x2700027002702727
+#            x18: 0x2700027002702727
 0x~~~~~~~~~~~~~~~~  2b1702d5		adds w21, w22, w23
 # NZCV: N:0 Z:0 C:0 V:0
-#   x21: 0x0000000002d02d2d
+#            w21:         0x02d02d2d
 0x~~~~~~~~~~~~~~~~  ab1a0338		adds x24, x25, x26
 # NZCV: N:0 Z:0 C:0 V:0
-#   x24: 0x3300033003303333
+#            x24: 0x3300033003303333
 0x~~~~~~~~~~~~~~~~  0a1d039b		and w27, w28, w29
-#   x27: 0x0000000001c01c1c
+#            w27:         0x01c01c1c
 0x~~~~~~~~~~~~~~~~  8a040062		and x2, x3, x4
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  6a0700c5		ands w5, w6, w7
 # NZCV: N:0 Z:0 C:0 V:0
-#    x5: 0x0000000000700707
+#             w5:         0x00700707
 0x~~~~~~~~~~~~~~~~  ea0a0128		ands x8, x9, x10
 # NZCV: N:0 Z:1 C:0 V:0
-#    x8: 0x0000000000000000
+#             x8: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  13007d8b		sbfx w11, w12, #0, #32
-#   x11: 0x0000000001b01b1b
+#            w11:         0x01b01b1b
 0x~~~~~~~~~~~~~~~~  9341fdcd		asr x13, x14, #1
-#   x13: 0x0700007000700707
+#            x13: 0x0700007000700707
 0x~~~~~~~~~~~~~~~~  1ad12a0f		asr w15, w16, w17
-#   x15: 0x0000000000000080
+#            w15:         0x00000080
 0x~~~~~~~~~~~~~~~~  9ad42a72		asr x18, x19, x20
-#   x18: 0x0000013000130013
+#            x18: 0x0000013000130013
 0x~~~~~~~~~~~~~~~~  33051ad5		bfxil w21, w22, #5, #2
-#   x21: 0x0000000002d02d2c
+#            w21:         0x02d02d2c
 0x~~~~~~~~~~~~~~~~  b3472317		bfxil x23, x24, #7, #2
-#   x23: 0x1700017001701716
+#            x23: 0x1700017001701716
 0x~~~~~~~~~~~~~~~~  0a3b0359		bic w25, w26, w27
-#   x25: 0x0000000000200202
+#            w25:         0x00200202
 0x~~~~~~~~~~~~~~~~  8a2203bc		bic x28, x29, x2
-#   x28: 0x1d0001d001d01d1d
+#            x28: 0x1d0001d001d01d1d
 0x~~~~~~~~~~~~~~~~  6a250083		bics w3, w4, w5
 # NZCV: N:0 Z:1 C:0 V:0
-#    x3: 0x0000000000000000
+#             w3:         0x00000000
 0x~~~~~~~~~~~~~~~~  ea2800e6		bics x6, x7, x8
 # NZCV: N:0 Z:0 C:0 V:0
-#    x6: 0x0700007000700707
+#             x6: 0x0700007000700707
 0x~~~~~~~~~~~~~~~~  3a4ae120		ccmn w9, w10, #nzcv, al
 # NZCV: N:0 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  3a4a0120		ccmn w9, w10, #nzcv, eq
@@ -139,30 +352,30 @@
 0x~~~~~~~~~~~~~~~~  fa5011e3		ccmp x15, x16, #nzCV, ne
 # NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1a922651		cinc w17, w18, lo
-#   x17: 0x0000000000130014
+#            w17:         0x00130014
 0x~~~~~~~~~~~~~~~~  1a923651		cinc w17, w18, hs
-#   x17: 0x0000000000130013
+#            w17:         0x00130013
 0x~~~~~~~~~~~~~~~~  9a949693		cinc x19, x20, hi
-#   x19: 0x1400014001401414
+#            x19: 0x1400014001401414
 0x~~~~~~~~~~~~~~~~  9a948693		cinc x19, x20, ls
-#   x19: 0x1400014001401415
+#            x19: 0x1400014001401415
 0x~~~~~~~~~~~~~~~~  5a9612d5		cinv w21, w22, eq
-#   x21: 0x0000000001601616
+#            w21:         0x01601616
 0x~~~~~~~~~~~~~~~~  5a9602d5		cinv w21, w22, ne
-#   x21: 0x00000000fe9fe9e9
+#            w21:         0xfe9fe9e9
 0x~~~~~~~~~~~~~~~~  da982317		cinv x23, x24, lo
-#   x23: 0xccfffccffccfcccc
+#            x23: 0xccfffccffccfcccc
 0x~~~~~~~~~~~~~~~~  da983317		cinv x23, x24, hs
-#   x23: 0x3300033003303333
+#            x23: 0x3300033003303333
 0x~~~~~~~~~~~~~~~~  d5033f5f		clrex
 0x~~~~~~~~~~~~~~~~  5ac01759		cls w25, w26
-#   x25: 0x0000000000000006
+#            w25:         0x00000006
 0x~~~~~~~~~~~~~~~~  dac0179b		cls x27, x28
-#   x27: 0x0000000000000002
+#            x27: 0x0000000000000002
 0x~~~~~~~~~~~~~~~~  5ac0105d		clz w29, w2
-#   x29: 0x0000000000000020
+#            w29:         0x00000020
 0x~~~~~~~~~~~~~~~~  dac01083		clz x3, x4
-#    x3: 0x0000000000000005
+#             x3: 0x0000000000000005
 0x~~~~~~~~~~~~~~~~  2b0600bf		cmn w5, w6
 # NZCV: N:0 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  ab0800ff		cmn x7, x8
@@ -172,606 +385,660 @@
 0x~~~~~~~~~~~~~~~~  eb0c017f		cmp x11, x12
 # NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  5a8e95cd		cneg w13, w14, hi
-#   x13: 0x0000000000e00e0e
+#            w13:         0x00e00e0e
 0x~~~~~~~~~~~~~~~~  5a8e85cd		cneg w13, w14, ls
-#   x13: 0x00000000ff1ff1f2
+#            w13:         0xff1ff1f2
 0x~~~~~~~~~~~~~~~~  da90160f		cneg x15, x16, eq
-#   x15: 0x1000010001001010
+#            x15: 0x1000010001001010
 0x~~~~~~~~~~~~~~~~  da90060f		cneg x15, x16, ne
-#   x15: 0xeffffefffeffeff0
+#            x15: 0xeffffefffeffeff0
 0x~~~~~~~~~~~~~~~~  1ad34251		crc32b w17, w18, w19
-#   x17: 0x00000000e963b635
+#            w17:         0xe963b635
 0x~~~~~~~~~~~~~~~~  1ad652b4		crc32cb w20, w21, w22
-#   x20: 0x00000000ad83ccb8
+#            w20:         0xad83ccb8
 0x~~~~~~~~~~~~~~~~  1ad95717		crc32ch w23, w24, w25
-#   x23: 0x000000003ed5525d
+#            w23:         0x3ed5525d
 0x~~~~~~~~~~~~~~~~  1adc5b7a		crc32cw w26, w27, w28
-#   x26: 0x00000000bc365145
+#            w26:         0xbc365145
 0x~~~~~~~~~~~~~~~~  1ac644a4		crc32h w4, w5, w6
-#    x4: 0x0000000000000070
+#             w4:         0x00000070
 0x~~~~~~~~~~~~~~~~  1ac94907		crc32w w7, w8, w9
-#    x7: 0x00000000b096abf4
+#             w7:         0xb096abf4
 0x~~~~~~~~~~~~~~~~  1a8f31cd		csel w13, w14, w15, lo
-#   x13: 0x0000000000e00e0e
+#            w13:         0x00e00e0e
 0x~~~~~~~~~~~~~~~~  1a8f21cd		csel w13, w14, w15, hs
-#   x13: 0x00000000feffeff0
+#            w13:         0xfeffeff0
 0x~~~~~~~~~~~~~~~~  9a928230		csel x16, x17, x18, hi
-#   x16: 0x0000013000130013
+#            x16: 0x0000013000130013
 0x~~~~~~~~~~~~~~~~  9a929230		csel x16, x17, x18, ls
-#   x16: 0x00000000e963b635
+#            x16: 0x00000000e963b635
 0x~~~~~~~~~~~~~~~~  1a9f17f3		cset w19, eq
-#   x19: 0x0000000000000000
+#            w19:         0x00000000
 0x~~~~~~~~~~~~~~~~  1a9f07f3		cset w19, ne
-#   x19: 0x0000000000000001
+#            w19:         0x00000001
 0x~~~~~~~~~~~~~~~~  9a9f27f4		cset x20, lo
-#   x20: 0x0000000000000001
+#            x20: 0x0000000000000001
 0x~~~~~~~~~~~~~~~~  9a9f37f4		cset x20, hs
-#   x20: 0x0000000000000000
+#            x20: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5a9f93f5		csetm w21, hi
-#   x21: 0x0000000000000000
+#            w21:         0x00000000
 0x~~~~~~~~~~~~~~~~  5a9f83f5		csetm w21, ls
-#   x21: 0x00000000ffffffff
+#            w21:         0xffffffff
 0x~~~~~~~~~~~~~~~~  da9f13f6		csetm x22, eq
-#   x22: 0x0000000000000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  da9f03f6		csetm x22, ne
-#   x22: 0xffffffffffffffff
+#            x22: 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  1a993717		csinc w23, w24, w25, lo
-#   x23: 0x0000000003303333
+#            w23:         0x03303333
 0x~~~~~~~~~~~~~~~~  1a992717		csinc w23, w24, w25, hs
-#   x23: 0x0000000000000007
+#            w23:         0x00000007
 0x~~~~~~~~~~~~~~~~  9a9c877a		csinc x26, x27, x28, hi
-#   x26: 0x1d0001d001d01d1e
+#            x26: 0x1d0001d001d01d1e
 0x~~~~~~~~~~~~~~~~  9a9c977a		csinc x26, x27, x28, ls
-#   x26: 0x0000000000000002
+#            x26: 0x0000000000000002
 0x~~~~~~~~~~~~~~~~  5a83005d		csinv w29, w2, w3, eq
-#   x29: 0x00000000fffffffa
+#            w29:         0xfffffffa
 0x~~~~~~~~~~~~~~~~  5a83105d		csinv w29, w2, w3, ne
-#   x29: 0x0000000000000000
+#            w29:         0x00000000
 0x~~~~~~~~~~~~~~~~  da8630a4		csinv x4, x5, x6, lo
-#    x4: 0x0000000000700707
+#             x4: 0x0000000000700707
 0x~~~~~~~~~~~~~~~~  da8620a4		csinv x4, x5, x6, hs
-#    x4: 0xf8ffff8fff8ff8f8
+#             x4: 0xf8ffff8fff8ff8f8
 0x~~~~~~~~~~~~~~~~  5a898507		csneg w7, w8, w9, hi
-#    x7: 0x00000000feafeaeb
+#             w7:         0xfeafeaeb
 0x~~~~~~~~~~~~~~~~  5a899507		csneg w7, w8, w9, ls
-#    x7: 0x0000000000000000
+#             w7:         0x00000000
 0x~~~~~~~~~~~~~~~~  da8c056a		csneg x10, x11, x12, eq
-#   x10: 0xe4fffe4ffe4fe4e5
+#            x10: 0xe4fffe4ffe4fe4e5
 0x~~~~~~~~~~~~~~~~  da8c156a		csneg x10, x11, x12, ne
-#   x10: 0x0000000001b01b1b
+#            x10: 0x0000000001b01b1b
 0x~~~~~~~~~~~~~~~~  d50b7a20		dc cvac, x0
 0x~~~~~~~~~~~~~~~~  d5033bbf		dmb ish
 0x~~~~~~~~~~~~~~~~  d5033b9f		dsb ish
 0x~~~~~~~~~~~~~~~~  4a2f01cd		eon w13, w14, w15
-#   x13: 0x0000000001e01e01
+#            w13:         0x01e01e01
 0x~~~~~~~~~~~~~~~~  ca320230		eon x16, x17, x18
-#   x16: 0xfffffecf168f49d9
+#            x16: 0xfffffecf168f49d9
 0x~~~~~~~~~~~~~~~~  4a150293		eor w19, w20, w21
-#   x19: 0x00000000ffffffff
+#            w19:         0xffffffff
 0x~~~~~~~~~~~~~~~~  ca1802f6		eor x22, x23, x24
-#   x22: 0x3300033003303334
+#            x22: 0x3300033003303334
 0x~~~~~~~~~~~~~~~~  139b2759		extr w25, w26, w27, #9
-#   x25: 0x0000000001000000
+#            w25:         0x01000000
 0x~~~~~~~~~~~~~~~~  93c22bbc		extr x28, x29, x2, #10
-#   x28: 0x0000000000000000
+#            x28: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  d503201f		nop
 0x~~~~~~~~~~~~~~~~  d50b7520		ic ivau, x0
 0x~~~~~~~~~~~~~~~~  d5033fdf		isb
 0x~~~~~~~~~~~~~~~~  88dffc03		ldar w3, [x0]
-#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c8dffc04		ldar x4, [x0]
-#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#             x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  08dffc05		ldarb w5, [x0]
-#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  08dffc06		ldarb w6, [x0]
-#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  48dffc07		ldarh w7, [x0]
-#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  48dffc08		ldarh w8, [x0]
-#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w8:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  887fa809		ldaxp w9, w10, [x0]
-#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w10:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c87fb00b		ldaxp x11, x12, [x0]
-#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  885ffc0d		ldaxr w13, [x0]
-#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#            w13:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c85ffc0e		ldaxr x14, [x0]
-#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  085ffc0f		ldaxrb w15, [x0]
-#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            w15:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  085ffc10		ldaxrb w16, [x0]
-#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            w16:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  485ffc11		ldaxrh w17, [x0]
-#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#            w17:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  485ffc12		ldaxrh w18, [x0]
-#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#            w18:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  28405013		ldnp w19, w20, [x0]
-#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#            w19:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w20:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a8405815		ldnp x21, x22, [x0]
-#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  29406017		ldp w23, w24, [x0]
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  28c16037		ldp w23, w24, [x1], #8
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  29c16037		ldp w23, w24, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            w23:         0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x17161514 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a9406819		ldp x25, x26, [x0]
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a8c16839		ldp x25, x26, [x1], #16
-#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a9c16839		ldp x25, x26, [x1, #16]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  6940701b		ldpsw x27, x28, [x0]
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000003020100
+#                                  ╙─ 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000007060504
+#                                  ╙─ 0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  68c1703b		ldpsw x27, x28, [x1], #8
-#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000033323130
+#                                  ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000037363534
+#                                  ╙─ 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  69c1703b		ldpsw x27, x28, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000043424140
+#                                  ╙─ 0x43424140 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000047464544
+#                                  ╙─ 0x47464544 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b940001d		ldr w29, [x0]
-#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b840443d		ldr w29, [x1], #4
-#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            w29:         0x43424140 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8404c3d		ldr w29, [x1, #4]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            w29:         0x4b4a4948 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f9400002		ldr x2, [x0]
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f8408422		ldr x2, [x1], #8
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f8408c22		ldr x2, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39400003		ldrb w3, [x0]
-#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38401423		ldrb w3, [x1], #1
-#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000058
+#                                  ╙─ 0x58 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38401c23		ldrb w3, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w3:         0x0000005a
+#                                  ╙─ 0x5a <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39400004		ldrb w4, [x0]
-#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38401424		ldrb w4, [x1], #1
-#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x0000005a
+#                                  ╙─ 0x5a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38401c24		ldrb w4, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x0000005c
+#                                  ╙─ 0x5c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  79400005		ldrh w5, [x0]
-#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78402425		ldrh w5, [x1], #2
-#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00005d5c
+#                                  ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78402c25		ldrh w5, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00006160
+#                                  ╙─ 0x6160 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  79400006		ldrh w6, [x0]
-#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78402426		ldrh w6, [x1], #2
-#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00006160
+#                                  ╙─ 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78402c26		ldrh w6, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00006564
+#                                  ╙─ 0x6564 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39c00007		ldrsb w7, [x0]
-#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38c01427		ldrsb w7, [x1], #1
-#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000064
+#                                  ╙─ 0x64 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38c01c27		ldrsb w7, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000066
+#                                  ╙─ 0x66 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39800008		ldrsb x8, [x0]
-#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38801428		ldrsb x8, [x1], #1
-#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000066
+#                                  ╙─ 0x66 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38801c28		ldrsb x8, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000068
+#                                  ╙─ 0x68 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  79c00009		ldrsh w9, [x0]
-#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78c02429		ldrsh w9, [x1], #2
-#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00006968
+#                                  ╙─ 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78c02c29		ldrsh w9, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00006d6c
+#                                  ╙─ 0x6d6c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7980000a		ldrsh x10, [x0]
-#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7880242a		ldrsh x10, [x1], #2
-#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000006d6c
+#                                  ╙─ 0x6d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78802c2a		ldrsh x10, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000007170
+#                                  ╙─ 0x7170 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b980000b		ldrsw x11, [x0]
-#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0000000003020100
+#                                  ╙─ 0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b880442b		ldrsw x11, [x1], #4
-#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0000000073727170
+#                                  ╙─ 0x73727170 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8804c2b		ldrsw x11, [x1, #4]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x11: 0x000000007b7a7978
+#                                  ╙─ 0x7b7a7978 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b840700c		ldur w12, [x0, #7]
-#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#            w12:         0x0a090807 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f840f00d		ldur x13, [x0, #15]
-#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#            x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  3840100e		ldurb w14, [x0, #1]
-#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#            w14:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  3840100f		ldurb w15, [x0, #1]
-#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#            w15:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78403010		ldurh w16, [x0, #3]
-#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#            w16:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78403011		ldurh w17, [x0, #3]
-#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#            w17:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38c01012		ldursb w18, [x0, #1]
-#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#            w18:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38801013		ldursb x19, [x0, #1]
-#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
+#            x19: 0x0000000000000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78c03014		ldursh w20, [x0, #3]
-#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#            w20:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78803015		ldursh x21, [x0, #3]
-#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
+#            x21: 0x0000000000000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8807016		ldursw x22, [x0, #7]
-#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
+#            x22: 0x000000000a090807
+#                                  ╙─ 0x0a090807 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  887f6017		ldxp w23, w24, [x0]
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c87f6819		ldxp x25, x26, [x0]
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  885f7c1b		ldxr w27, [x0]
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
+#            w27:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c85f7c1c		ldxr x28, [x0]
-#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  085f7c1d		ldxrb w29, [x0]
-#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  085f7c02		ldxrb w2, [x0]
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             w2:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  485f7c03		ldxrh w3, [x0]
-#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  485f7c04		ldxrh w4, [x0]
-#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  531e74c5		lsl w5, w6, #2
-#    x5: 0x0000000000019590
+#             w5:         0x00019590
 0x~~~~~~~~~~~~~~~~  d37df107		lsl x7, x8, #3
-#    x7: 0x0000000000000340
+#             x7: 0x0000000000000340
 0x~~~~~~~~~~~~~~~~  1acb2149		lsl w9, w10, w11
-#    x9: 0x0000000070000000
+#             w9:         0x70000000
 0x~~~~~~~~~~~~~~~~  9ace21ac		lsl x12, x13, x14
-#   x12: 0x2c2a28262422201e
+#            x12: 0x2c2a28262422201e
 0x~~~~~~~~~~~~~~~~  53047e0f		lsr w15, w16, #4
-#   x15: 0x0000000000000040
+#            w15:         0x00000040
 0x~~~~~~~~~~~~~~~~  d345fe51		lsr x17, x18, #5
-#   x17: 0x0000000000000000
+#            x17: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1ad52693		lsr w19, w20, w21
-#   x19: 0x0000000000000080
+#            w19:         0x00000080
 0x~~~~~~~~~~~~~~~~  9ad826f6		lsr x22, x23, x24
-#   x22: 0x0000000000302010
+#            x22: 0x0000000000302010
 0x~~~~~~~~~~~~~~~~  1b1b7359		madd w25, w26, w27, w28
-#   x25: 0x00000000371b0900
+#            w25:         0x371b0900
 0x~~~~~~~~~~~~~~~~  9b03105d		madd x29, x2, x3, x4
-#   x29: 0x0000000000000100
+#            x29: 0x0000000000000100
 0x~~~~~~~~~~~~~~~~  1b07fcc5		mneg w5, w6, w7
-#    x5: 0x00000000feb67b00
+#             w5:         0xfeb67b00
 0x~~~~~~~~~~~~~~~~  9b0afd28		mneg x8, x9, x10
-#    x8: 0xffffce5f00000000
+#             x8: 0xffffce5f00000000
 0x~~~~~~~~~~~~~~~~  2a0c03eb		mov w11, w12
-#   x11: 0x000000002422201e
+#            w11:         0x2422201e
 0x~~~~~~~~~~~~~~~~  aa0e03ed		mov x13, x14
-#   x13: 0x0000000000000001
+#            x13: 0x0000000000000001
 0x~~~~~~~~~~~~~~~~  7280104f		movk w15, #0x82
-#   x15: 0x0000000000000082
+#            x15: 0x0000000000000082
 0x~~~~~~~~~~~~~~~~  f2801070		movk x16, #0x83
-#   x16: 0x0000000000000083
+#            x16: 0x0000000000000083
 0x~~~~~~~~~~~~~~~~  12801091		mov w17, #0xffffff7b
-#   x17: 0x00000000ffffff7b
+#            x17: 0x00000000ffffff7b
 0x~~~~~~~~~~~~~~~~  928010b2		mov x18, #0xffffffffffffff7a
-#   x18: 0xffffffffffffff7a
+#            x18: 0xffffffffffffff7a
 0x~~~~~~~~~~~~~~~~  528010d3		mov w19, #0x86
-#   x19: 0x0000000000000086
+#            x19: 0x0000000000000086
 0x~~~~~~~~~~~~~~~~  d28010f4		mov x20, #0x87
-#   x20: 0x0000000000000087
+#            x20: 0x0000000000000087
 0x~~~~~~~~~~~~~~~~  1b18e6f6		msub w22, w23, w24, w25
-#   x22: 0x000000001b0e0500
+#            w22:         0x1b0e0500
 0x~~~~~~~~~~~~~~~~  9b1cf77a		msub x26, x27, x28, x29
-#   x26: 0xe3e9eff5fbff0100
+#            x26: 0xe3e9eff5fbff0100
 0x~~~~~~~~~~~~~~~~  1b047c62		mul w2, w3, w4
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             w2:         0x00010000
 0x~~~~~~~~~~~~~~~~  9b077cc5		mul x5, x6, x7
-#    x5: 0x0000000001498500
+#             x5: 0x0000000001498500
 0x~~~~~~~~~~~~~~~~  2a2903e8		mvn w8, w9
-#    x8: 0x000000008fffffff
+#             w8:         0x8fffffff
 0x~~~~~~~~~~~~~~~~  aa2b03ea		mvn x10, x11
-#   x10: 0xffffffffdbdddfe1
+#            x10: 0xffffffffdbdddfe1
 0x~~~~~~~~~~~~~~~~  4b0d03ec		neg w12, w13
-#   x12: 0x00000000ffffffff
+#            w12:         0xffffffff
 0x~~~~~~~~~~~~~~~~  cb0f03ee		neg x14, x15
-#   x14: 0xffffffffffffff7e
+#            x14: 0xffffffffffffff7e
 0x~~~~~~~~~~~~~~~~  6b1103f0		negs w16, w17
 # NZCV: N:0 Z:0 C:0 V:0
-#   x16: 0x0000000000000085
+#            w16:         0x00000085
 0x~~~~~~~~~~~~~~~~  eb1303f2		negs x18, x19
 # NZCV: N:1 Z:0 C:0 V:0
-#   x18: 0xffffffffffffff7a
+#            x18: 0xffffffffffffff7a
 0x~~~~~~~~~~~~~~~~  5a1503f4		ngc w20, w21
-#   x20: 0x00000000fffffbfc
+#            w20:         0xfffffbfc
 0x~~~~~~~~~~~~~~~~  da1703f6		ngc x22, x23
-#   x22: 0xfffffffffcfdfeff
+#            x22: 0xfffffffffcfdfeff
 0x~~~~~~~~~~~~~~~~  7a1903f8		ngcs w24, w25
 # NZCV: N:1 Z:0 C:0 V:0
-#   x24: 0x00000000c8e4f6ff
+#            w24:         0xc8e4f6ff
 0x~~~~~~~~~~~~~~~~  fa1b03fa		ngcs x26, x27
 # NZCV: N:1 Z:0 C:0 V:0
-#   x26: 0xfffffffffcfdfeff
+#            x26: 0xfffffffffcfdfeff
 0x~~~~~~~~~~~~~~~~  d503201f		nop
 0x~~~~~~~~~~~~~~~~  2a2203bc		orn w28, w29, w2
-#   x28: 0x00000000fffeffff
+#            w28:         0xfffeffff
 0x~~~~~~~~~~~~~~~~  aa250083		orn x3, x4, x5
-#    x3: 0xfffffffffeb67bff
+#             x3: 0xfffffffffeb67bff
 0x~~~~~~~~~~~~~~~~  2a0800e6		orr w6, w7, w8
-#    x6: 0x000000008fffffff
+#             w6:         0x8fffffff
 0x~~~~~~~~~~~~~~~~  aa0b0149		orr x9, x10, x11
-#    x9: 0xffffffffffffffff
+#             x9: 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  f8804000		prfum pldl1keep, [x0, #4]
 0x~~~~~~~~~~~~~~~~  f8801000		prfum pldl1keep, [x0, #1]
 0x~~~~~~~~~~~~~~~~  5ac001ac		rbit w12, w13
-#   x12: 0x0000000080000000
+#            w12:         0x80000000
 0x~~~~~~~~~~~~~~~~  dac001ee		rbit x14, x15
-#   x14: 0x4100000000000000
+#            x14: 0x4100000000000000
 0x~~~~~~~~~~~~~~~~  5ac00a30		rev w16, w17
-#   x16: 0x000000007bffffff
+#            w16:         0x7bffffff
 0x~~~~~~~~~~~~~~~~  dac00e72		rev x18, x19
-#   x18: 0x8600000000000000
+#            x18: 0x8600000000000000
 0x~~~~~~~~~~~~~~~~  5ac006b4		rev16 w20, w21
-#   x20: 0x0000000000000304
+#            w20:         0x00000304
 0x~~~~~~~~~~~~~~~~  dac006f6		rev16 x22, x23
-#   x22: 0x0000000002030001
+#            x22: 0x0000000002030001
 0x~~~~~~~~~~~~~~~~  dac00b38		rev32 x24, x25
-#   x24: 0x0000000000091b37
+#            x24: 0x0000000000091b37
 0x~~~~~~~~~~~~~~~~  1adc2f7a		ror w26, w27, w28
-#   x26: 0x0000000006040200
+#            w26:         0x06040200
 0x~~~~~~~~~~~~~~~~  9ac32c5d		ror x29, x2, x3
-#   x29: 0x0000000000020000
+#            x29: 0x0000000000020000
 0x~~~~~~~~~~~~~~~~  5a0600a4		sbc w4, w5, w6
-#    x4: 0x0000000071498500
+#             w4:         0x71498500
 0x~~~~~~~~~~~~~~~~  da090107		sbc x7, x8, x9
-#    x7: 0x000000008fffffff
+#             x7: 0x000000008fffffff
 0x~~~~~~~~~~~~~~~~  7a0c016a		sbcs w10, w11, w12
 # NZCV: N:1 Z:0 C:0 V:1
-#   x10: 0x00000000a422201d
+#            w10:         0xa422201d
 0x~~~~~~~~~~~~~~~~  fa0f01cd		sbcs x13, x14, x15
 # NZCV: N:0 Z:0 C:1 V:0
-#   x13: 0x40ffffffffffff7d
+#            x13: 0x40ffffffffffff7d
 0x~~~~~~~~~~~~~~~~  131e0a30		sbfiz w16, w17, #2, #3
-#   x16: 0x000000000000000c
+#            w16:         0x0000000c
 0x~~~~~~~~~~~~~~~~  937c1272		sbfiz x18, x19, #4, #5
-#   x18: 0x0000000000000060
+#            x18: 0x0000000000000060
 0x~~~~~~~~~~~~~~~~  130632f6		sbfx w22, w23, #6, #7
-#   x22: 0x0000000000000004
+#            w22:         0x00000004
 0x~~~~~~~~~~~~~~~~  93484338		sbfx x24, x25, #8, #9
-#   x24: 0xffffffffffffff09
+#            x24: 0xffffffffffffff09
 0x~~~~~~~~~~~~~~~~  1adc0f7a		sdiv w26, w27, w28
-#   x26: 0x00000000fffffcff
+#            w26:         0xfffffcff
 0x~~~~~~~~~~~~~~~~  9ac30c5d		sdiv x29, x2, x3
-#   x29: 0x0000000000000000
+#            x29: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9b4e7dac		smulh x12, x13, x14
-#   x12: 0x1080ffffffffffde
+#            x12: 0x1080ffffffffffde
 0x~~~~~~~~~~~~~~~~  889ffc12		stlr w18, [x0]
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#      x18<31:0>:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  c89ffc13		stlr x19, [x0]
-#   x19: 0x0000000000000086 -> 0x~~~~~~~~~~~~~~~~
+#      x19<63:0>: 0x0000000000000086 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  089ffc14		stlrb w20, [x0]
-#   w20<7:0>:          0x04 -> 0x~~~~~~~~~~~~~~~~
+#       x20<7:0>:               0x04 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  089ffc15		stlrb w21, [x0]
-#   w21<7:0>:          0x03 -> 0x~~~~~~~~~~~~~~~~
+#       x21<7:0>:               0x03 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  489ffc16		stlrh w22, [x0]
-#   w22<15:0>:       0x0004 -> 0x~~~~~~~~~~~~~~~~
+#      x22<15:0>:             0x0004 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  489ffc17		stlrh w23, [x0]
-#   w23<15:0>:       0x0100 -> 0x~~~~~~~~~~~~~~~~
+#      x23<15:0>:             0x0100 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  8838e819		stlxp w24, w25, w26, [x0]
-#   x24: 0x0000000000000001
+#            w24:         0x00000001
 0x~~~~~~~~~~~~~~~~  c83bf41c		stlxp w27, x28, x29, [x0]
-#   x27: 0x0000000000000001
+#            w27:         0x00000001
 0x~~~~~~~~~~~~~~~~  8802fc03		stlxr w2, w3, [x0]
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             w2:         0x00000001
 0x~~~~~~~~~~~~~~~~  c804fc05		stlxr w4, x5, [x0]
-#    x4: 0x0000000000000001
+#             w4:         0x00000001
 0x~~~~~~~~~~~~~~~~  0806fc07		stlxrb w6, w7, [x0]
-#    x6: 0x0000000000000001
+#             w6:         0x00000001
 0x~~~~~~~~~~~~~~~~  0808fc09		stlxrb w8, w9, [x0]
-#    x8: 0x0000000000000001
+#             w8:         0x00000001
 0x~~~~~~~~~~~~~~~~  480afc0b		stlxrh w10, w11, [x0]
-#   x10: 0x0000000000000001
+#            w10:         0x00000001
 0x~~~~~~~~~~~~~~~~  480cfc0d		stlxrh w12, w13, [x0]
-#   x12: 0x0000000000000001
+#            w12:         0x00000001
 0x~~~~~~~~~~~~~~~~  28003c0e		stnp w14, w15, [x0]
-#   w14:         0x00000000 -> 0x~~~~~~~~~~~~~~~~
-#   w15:         0x00000082 -> 0x~~~~~~~~~~~~~~~~
+#      x14<31:0>:         0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#      x15<31:0>:         0x00000082 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a8004410		stnp x16, x17, [x0]
-#   x16: 0x000000000000000c -> 0x~~~~~~~~~~~~~~~~
-#   x17: 0x00000000ffffff7b -> 0x~~~~~~~~~~~~~~~~
+#      x16<63:0>: 0x000000000000000c -> 0x~~~~~~~~~~~~~~~~
+#      x17<63:0>: 0x00000000ffffff7b -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  29004c12		stp w18, w19, [x0]
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+#      x18<31:0>:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#      x19<31:0>:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  28814c32		stp w18, w19, [x1], #8
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x18<31:0>:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#      x19<31:0>:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  29814c32		stp w18, w19, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x18<31:0>:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
+#      x19<31:0>:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a9005414		stp x20, x21, [x0]
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+#      x20<63:0>: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#      x21<63:0>: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a8815434		stp x20, x21, [x1], #16
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x20<63:0>: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#      x21<63:0>: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  a9815434		stp x20, x21, [x1, #16]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x20<63:0>: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
+#      x21<63:0>: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b9000016		str w22, [x0]
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+#      x22<31:0>:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8004436		str w22, [x1], #4
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x22<31:0>:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b8004c36		str w22, [x1, #4]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x22<31:0>:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f9000017		str x23, [x0]
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+#      x23<63:0>: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f8008437		str x23, [x1], #8
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x23<63:0>: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f8008c37		str x23, [x1, #8]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x23<63:0>: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39000018		strb w24, [x0]
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+#       x24<7:0>:               0x01 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001438		strb w24, [x1], #1
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       x24<7:0>:               0x01 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001c38		strb w24, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#       x24<7:0>:               0x01 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  39000019		strb w25, [x0]
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+#       x25<7:0>:               0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001439		strb w25, [x1], #1
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       x25<7:0>:               0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001c39		strb w25, [x1, #1]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#       x25<7:0>:               0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7900001a		strh w26, [x0]
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+#      x26<15:0>:             0xfcff -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7800243a		strh w26, [x1], #2
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x26<15:0>:             0xfcff -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78002c3a		strh w26, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x26<15:0>:             0xfcff -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7900001b		strh w27, [x0]
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+#      x27<15:0>:             0x0001 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7800243b		strh w27, [x1], #2
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      x27<15:0>:             0x0001 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78002c3b		strh w27, [x1, #2]!
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#      x27<15:0>:             0x0001 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  b800701c		stur w28, [x0, #7]
-#   w28:         0xfffeffff -> 0x~~~~~~~~~~~~~~~~
+#      x28<31:0>:         0xfffeffff -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  f800f01d		stur x29, [x0, #15]
-#   x29: 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      x29<63:0>: 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001002		sturb w2, [x0, #1]
-#    w2<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
+#        x2<7:0>:               0x01 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  38001003		sturb w3, [x0, #1]
-#    w3<7:0>:          0xff -> 0x~~~~~~~~~~~~~~~~
+#        x3<7:0>:               0xff -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78003004		sturh w4, [x0, #3]
-#    w4<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
+#       x4<15:0>:             0x0001 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  78003005		sturh w5, [x0, #3]
-#    w5<15:0>:       0x8500 -> 0x~~~~~~~~~~~~~~~~
+#       x5<15:0>:             0x8500 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  88262007		stxp w6, w7, w8, [x0]
-#    x6: 0x0000000000000001
+#             w6:         0x00000001
 0x~~~~~~~~~~~~~~~~  c8292c0a		stxp w9, x10, x11, [x0]
-#    x9: 0x0000000000000001
+#             w9:         0x00000001
 0x~~~~~~~~~~~~~~~~  880c7c0d		stxr w12, w13, [x0]
-#   x12: 0x0000000000000001
+#            w12:         0x00000001
 0x~~~~~~~~~~~~~~~~  c80e7c0f		stxr w14, x15, [x0]
-#   x14: 0x0000000000000001
+#            w14:         0x00000001
 0x~~~~~~~~~~~~~~~~  08107c11		stxrb w16, w17, [x0]
-#   x16: 0x0000000000000001
+#            w16:         0x00000001
 0x~~~~~~~~~~~~~~~~  08127c13		stxrb w18, w19, [x0]
-#   x18: 0x0000000000000001
+#            w18:         0x00000001
 0x~~~~~~~~~~~~~~~~  48147c15		stxrh w20, w21, [x0]
-#   x20: 0x0000000000000001
+#            w20:         0x00000001
 0x~~~~~~~~~~~~~~~~  48167c17		stxrh w22, w23, [x0]
-#   x22: 0x0000000000000001
+#            w22:         0x00000001
 0x~~~~~~~~~~~~~~~~  4b1a0338		sub w24, w25, w26
-#   x24: 0x00000000371b0c01
+#            w24:         0x371b0c01
 0x~~~~~~~~~~~~~~~~  cb1d039b		sub x27, x28, x29
-#   x27: 0x00000000fffeffff
+#            x27: 0x00000000fffeffff
 0x~~~~~~~~~~~~~~~~  6b040062		subs w2, w3, w4
 # NZCV: N:1 Z:0 C:1 V:0
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             w2:         0xfeb67bfe
 0x~~~~~~~~~~~~~~~~  eb0700c5		subs x5, x6, x7
 # NZCV: N:1 Z:0 C:0 V:0
-#    x5: 0xffffffff70000002
+#             x5: 0xffffffff70000002
 0x~~~~~~~~~~~~~~~~  13001d28		sxtb w8, w9
-#    x8: 0x0000000000000001
+#             w8:         0x00000001
 0x~~~~~~~~~~~~~~~~  93401d6a		sxtb x10, w11
-#   x10: 0x000000000000001e
+#            x10: 0x000000000000001e
 0x~~~~~~~~~~~~~~~~  13003dac		sxth w12, w13
-#   x12: 0x00000000ffffff7d
+#            w12:         0xffffff7d
 0x~~~~~~~~~~~~~~~~  93403dee		sxth x14, w15
-#   x14: 0x0000000000000082
+#            x14: 0x0000000000000082
 0x~~~~~~~~~~~~~~~~  13007e30		sbfx w16, w17, #0, #32
-#   x16: 0x00000000ffffff7b
+#            w16:         0xffffff7b
 0x~~~~~~~~~~~~~~~~  93407e72		sxtw x18, w19
-#   x18: 0x0000000000000086
+#            x18: 0x0000000000000086
 0x~~~~~~~~~~~~~~~~  6a15029f		tst w20, w21
 # NZCV: N:0 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  ea1702df		tst x22, x23
 # NZCV: N:0 Z:1 C:0 V:0
 0x~~~~~~~~~~~~~~~~  53162b38		ubfiz w24, w25, #10, #11
-#   x24: 0x0000000000040000
+#            w24:         0x00040000
 0x~~~~~~~~~~~~~~~~  d374337a		ubfiz x26, x27, #12, #13
-#   x26: 0x0000000001fff000
+#            x26: 0x0000000001fff000
 0x~~~~~~~~~~~~~~~~  530e3fbc		ubfx w28, w29, #14, #2
-#   x28: 0x0000000000000000
+#            w28:         0x00000000
 0x~~~~~~~~~~~~~~~~  d3410862		ubfx x2, x3, #1, #2
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  530318a4		ubfx w4, w5, #3, #4
-#    x4: 0x0000000000000000
+#             w4:         0x00000000
 0x~~~~~~~~~~~~~~~~  d34528e6		ubfx x6, x7, #5, #6
-#    x6: 0x000000000000003f
+#             x6: 0x000000000000003f
 0x~~~~~~~~~~~~~~~~  1aca0928		udiv w8, w9, w10
-#    x8: 0x0000000000000000
+#             w8:         0x00000000
 0x~~~~~~~~~~~~~~~~  9acd098b		udiv x11, x12, x13
-#   x11: 0x0000000000000000
+#            x11: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9bd87ef6		umulh x22, x23, x24
-#   x22: 0x0000000000000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  53001fbc		uxtb w28, w29
-#   x28: 0x0000000000000000
+#            w28:         0x00000000
 0x~~~~~~~~~~~~~~~~  d3401c62		uxtb x2, w3
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  53003ca4		uxth w4, w5
-#    x4: 0x0000000000000002
+#             w4:         0x00000002
 0x~~~~~~~~~~~~~~~~  d3403ce6		uxth x6, w7
-#    x6: 0x000000000000ffff
+#             x6: 0x000000000000ffff
 0x~~~~~~~~~~~~~~~~  53007d28		lsr w8, w9, #0
-#    x8: 0x0000000000000001
+#             w8:         0x00000001
 0x~~~~~~~~~~~~~~~~  d3407d6a		ubfx x10, x11, #0, #32
-#   x10: 0x0000000000000000
+#            x10: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  14000001		b #+0x4 (addr 0x~~~~~~~~~~~~~~~~)
 # Branch to 0x~~~~~~~~~~~~~~~~.
 0x~~~~~~~~~~~~~~~~  eb030063		subs x3, x3, x3
 # NZCV: N:0 Z:1 C:1 V:0
-#    x3: 0x0000000000000000
+#             x3: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  54000061		b.ne #+0xc (addr 0x~~~~~~~~~~~~~~~~)
 0x~~~~~~~~~~~~~~~~  f100047f		cmp x3, #0x1 (1)
 # NZCV: N:1 Z:0 C:0 V:0
@@ -780,5299 +1047,10814 @@
 0x~~~~~~~~~~~~~~~~  54000061		b.ne #+0xc (addr 0x~~~~~~~~~~~~~~~~)
 # Branch to 0x~~~~~~~~~~~~~~~~.
 0x~~~~~~~~~~~~~~~~  7ef3d44d		fabd d13, d2, d19
-#   v13: 0x00000000000000004036e00cd9b7e45b
+#            v13: 0x0000000000000000490ffff1110487fe
 0x~~~~~~~~~~~~~~~~  7ebed548		fabd s8, s10, s30
-#    v8: 0x00000000000000000000000041c5851e
+#             v8: 0x0000000000000000000000000e02aff8
 0x~~~~~~~~~~~~~~~~  1e60c021		fabs d1, d1
-#    v1: 0x00000000000000003ff587933f9e0419 (d1: 1.34560)
+#             d1:                 0x47f000007f823c00 (3.403e+38)
 0x~~~~~~~~~~~~~~~~  1e20c0f9		fabs s25, s7
-#   v25: 0x000000000000000000000000410a4396 (s25: 8.64150)
+#            s25:                         0x02825400 (1.915e-37)
 0x~~~~~~~~~~~~~~~~  7e70eee1		facge d1, d23, d16
-#    v1: 0x0000000000000000ffffffffffffffff
+#             v1: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e21ee24		facge s4, s17, s1
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ef8eea2		facgt d2, d21, d24
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eacef4c		facgt s12, s26, s12
-#   v12: 0x000000000000000000000000ffffffff
+#            v12: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  1e76296d		fadd d13, d11, d22
-#   v13: 0x0000000000000000404633d07142f43a (d13: 44.4048)
+#            d13:                 0x494002008a13204c (7.140e+44)
 0x~~~~~~~~~~~~~~~~  1e282a7b		fadd s27, s19, s8
-#   v27: 0x000000000000000000000000424094fe (s27: 48.1455)
+#            s27:                         0x0e029fa8 (1.610e-30)
 0x~~~~~~~~~~~~~~~~  1e6a24c0		fccmp d6, d10, #nzcv, hs
 # NZCV: N:0 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1e3417ad		fccmp s29, s20, #NZcV, ne
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1e62e55e		fccmpe d10, d2, #NZCv, al
 # NZCV: N:0 Z:0 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e23547d		fccmpe s3, s3, #NZcV, pl
 # NZCV: N:0 Z:1 C:1 V:0
 0x~~~~~~~~~~~~~~~~  5e6ae513		fcmeq d19, d8, d10
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0da40		fcmeq d0, d18, #0.0
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e3ee481		fcmeq s1, s4, s30
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ea0dbb6		fcmeq s22, s29, #0.0
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e61e65b		fcmge d27, d18, d1
-#   v27: 0x0000000000000000ffffffffffffffff
+#            v27: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7ee0cb9f		fcmge d31, d28, #0.0
-#   v31: 0x0000000000000000ffffffffffffffff
+#            v31: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e29e67f		fcmge s31, s19, s9
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  7ea0cb21		fcmge s1, s25, #0.0
-#    v1: 0x000000000000000000000000ffffffff
+#             v1: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  7eefe432		fcmgt d18, d1, d15
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0cbe3		fcmgt d3, d31, #0.0
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7ea2e72b		fcmgt s11, s25, s2
-#   v11: 0x000000000000000000000000ffffffff
+#            v11: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  5ea0ca11		fcmgt s17, s16, #0.0
-#   v17: 0x000000000000000000000000ffffffff
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ee0da38		fcmle d24, d17, #0.0
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7ea0d90b		fcmle s11, s8, #0.0
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0ebe5		fcmlt d5, d31, #0.0
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ea0eaf2		fcmlt s18, s23, #0.0
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  1e782140		fcmp d10, d24
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 0x~~~~~~~~~~~~~~~~  1e6021a8		fcmp d13, #0.0
 # NZCV: N:0 Z:0 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e262240		fcmp s18, s6
-# NZCV: N:1 Z:0 C:0 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 0x~~~~~~~~~~~~~~~~  1e202208		fcmp s16, #0.0
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1e712130		fcmpe d9, d17
 # NZCV: N:0 Z:0 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e6023b8		fcmpe d29, #0.0
 # NZCV: N:0 Z:0 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e312210		fcmpe s16, s17
-# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
 0x~~~~~~~~~~~~~~~~  1e2022d8		fcmpe s22, #0.0
 # NZCV: N:0 Z:1 C:1 V:0
 0x~~~~~~~~~~~~~~~~  1e73cdca		fcsel d10, d14, d19, gt
-#   v10: 0x00000000000000000000000000000000 (d10: 0.00000)
+#            d10:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e22ae56		fcsel s22, s18, s2, ge
-#   v22: 0x00000000000000000000000000000000 (s22: 0.00000)
+#            s22:                         0xffffffff
 0x~~~~~~~~~~~~~~~~  1ee2c304		fcvt d4, h24
-#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+#             d4:                 0xfffffc0000000000
 0x~~~~~~~~~~~~~~~~  1e22c04b		fcvt d11, s2
-#   v11: 0x00000000000000000000000000000000 (d11: 0.00000)
+#            d11:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e63c128		fcvt h8, d9
-#    v8: 0x00000000000000000000000000004a0e
+#             h8:                             0x7c00
 0x~~~~~~~~~~~~~~~~  1e23c02c		fcvt h12, s1
-#   v12: 0x0000000000000000000000000000ffff
+#            h12:                             0xffff
 0x~~~~~~~~~~~~~~~~  1e6243ec		fcvt s12, d31
-#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+#            s12:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1ee2433b		fcvt s27, h25
-#   v27: 0x0000000000000000000000004072c000 (s27: 3.79297)
+#            s27:                         0x42800000
 0x~~~~~~~~~~~~~~~~  5e61ca1c		fcvtas d28, d16
-#   v28: 0x00000000000000000000000000000016
+#            v28: 0x00000000000000007fffffffffffffff
 0x~~~~~~~~~~~~~~~~  5e21c8a3		fcvtas s3, s5
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e6403f2		fcvtas w18, d31
-#   x18: 0x0000000000000000
+#            w18:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e24031d		fcvtas w29, s24
-#   x29: 0x0000000000000000
+#            w29:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e640029		fcvtas x9, d1
-#    x9: 0x0000000000000000
+#             x9: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e24005e		fcvtas x30, s2
-#    lr: 0x0000000000000000
+#             lr: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7e61c80e		fcvtau d14, d0
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e21c9df		fcvtau s31, s14
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e650050		fcvtau w16, d2
-#   x16: 0x0000000000000000
+#            w16:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e250012		fcvtau w18, s0
-#   x18: 0x0000000000000000
+#            w18:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e6500fa		fcvtau x26, d7
-#   x26: 0x0000000000000009
+#            x26: 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  9e250279		fcvtau x25, s19
-#   x25: 0x0000000000000000
+#            x25: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5e61bb3e		fcvtms d30, d25
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e21b9ec		fcvtms s12, s15
-#   v12: 0x00000000000000000000000000000012
+#            v12: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  1e7000e9		fcvtms w9, d7
-#    x9: 0x0000000000000009
+#             w9:         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1e3000d3		fcvtms w19, s6
-#   x19: 0x0000000000000007
+#            w19:         0xffffffff
 0x~~~~~~~~~~~~~~~~  9e7000c6		fcvtms x6, d6
-#    x6: 0x0000000000000008
+#             x6: 0x7fffffffffffffff
 0x~~~~~~~~~~~~~~~~  9e3000f6		fcvtms x22, s7
-#   x22: 0x0000000000000008
+#            x22: 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e61b81b		fcvtmu d27, d0
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e21bac8		fcvtmu s8, s22
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e71027d		fcvtmu w29, d19
-#   x29: 0x0000000000000000
+#            w29:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e31001a		fcvtmu w26, s0
-#   x26: 0x0000000000000000
+#            w26:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e7100ad		fcvtmu x13, d5
-#   x13: 0x0000000000000000
+#            x13: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e310245		fcvtmu x5, s18
-#    x5: 0x0000000000000000
+#             x5: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5e61a9fe		fcvtns d30, d15
-#   v30: 0x00000000000000000000000000000014
+#            v30: 0x00000000000000007fffffffffffffff
 0x~~~~~~~~~~~~~~~~  5e21a96a		fcvtns s10, s11
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e6001f5		fcvtns w21, d15
-#   x21: 0x0000000000000014
+#            w21:         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1e200152		fcvtns w18, s10
-#   x18: 0x0000000000000000
+#            w18:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e600228		fcvtns x8, d17
-#    x8: 0x0000000000000000
+#             x8: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e200191		fcvtns x17, s12
-#   x17: 0x0000000000000000
+#            x17: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7e61aaa0		fcvtnu d0, d21
-#    v0: 0x0000000000000000000000000000001c
+#             v0: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e21ab26		fcvtnu s6, s25
-#    v6: 0x00000000000000000000000000000009
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e61017d		fcvtnu w29, d11
-#   x29: 0x0000000000000000
+#            w29:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e2103f9		fcvtnu w25, s31
-#   x25: 0x0000000000000000
+#            w25:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e61017e		fcvtnu x30, d11
-#    lr: 0x0000000000000000
+#             lr: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e21025b		fcvtnu x27, s18
-#   x27: 0x0000000000000000
+#            x27: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5ee1aacb		fcvtps d11, d22
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  5ea1aa9d		fcvtps s29, s20
-#   v29: 0x00000000000000000000000000000019
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e68032f		fcvtps w15, d25
-#   x15: 0x0000000000000001
+#            w15:         0x00000001
 0x~~~~~~~~~~~~~~~~  1e2800f0		fcvtps w16, s7
-#   x16: 0x0000000000000009
+#            w16:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e68028d		fcvtps x13, d20
-#   x13: 0x000000000000001b
+#            x13: 0x7fffffffffffffff
 0x~~~~~~~~~~~~~~~~  9e2802e3		fcvtps x3, s23
-#    x3: 0x000000000000001d
+#             x3: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7ee1a838		fcvtpu d24, d1
-#   v24: 0x00000000000000000000000000000001
+#            v24: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  7ea1ab0e		fcvtpu s14, s24
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  1e6903ba		fcvtpu w26, d29
-#   x26: 0x0000000000000001
+#            w26:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e29035f		fcvtpu wzr, s26
 0x~~~~~~~~~~~~~~~~  9e6900db		fcvtpu x27, d6
-#   x27: 0x0000000000000001
+#            x27: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e2901dd		fcvtpu x29, s14
-#   x29: 0x0000000000000001
+#            x29: 0x0000000000000001
 0x~~~~~~~~~~~~~~~~  7e61698c		fcvtxn s12, d12
-#   v12: 0x00000000000000000000000000000001
+#            v12: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  5ee1b80f		fcvtzs d15, d0
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f56fc8d		fcvtzs d13, d4, #42
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ea1b968		fcvtzs s8, s11
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f27fcdf		fcvtzs s31, s6, #25
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e780126		fcvtzs w6, d9
-#    x6: 0x000000000000000c
+#             w6:         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1e58b159		fcvtzs w25, d10, #20
-#   x25: 0x0000000000000000
+#            w25:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e380029		fcvtzs w9, s1
-#    x9: 0x0000000000000000
+#             w9:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e188bb1		fcvtzs w17, s29, #30
-#   x17: 0x0000000000000000
+#            w17:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e780053		fcvtzs x19, d2
-#   x19: 0x0000000000000000
+#            x19: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e58fdd6		fcvtzs x22, d14, #1
-#   x22: 0x0000000000000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e38028e		fcvtzs x14, s20
-#   x14: 0x0000000000000018
+#            x14: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e187fc3		fcvtzs x3, s30, #33
-#    x3: 0x0000000000000000
+#             x3: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7ee1b9fc		fcvtzu d28, d15
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f7dfc80		fcvtzu d0, d4, #3
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ea1b8a2		fcvtzu s2, s5
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f22fc04		fcvtzu s4, s0, #30
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e79008b		fcvtzu w11, d4
-#   x11: 0x0000000000000000
+#            w11:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e598307		fcvtzu w7, d24, #32
-#    x7: 0x0000000000000000
+#             w7:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e390312		fcvtzu w18, s24
-#   x18: 0x0000000000000000
+#            w18:         0x00000000
 0x~~~~~~~~~~~~~~~~  1e19f36e		fcvtzu w14, s27, #4
-#   x14: 0x0000000000000000
+#            w14:         0x00000000
 0x~~~~~~~~~~~~~~~~  9e790176		fcvtzu x22, d11
-#   x22: 0x0000000000000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e593368		fcvtzu x8, d27, #52
-#    x8: 0x0000000000000000
+#             x8: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e390287		fcvtzu x7, s20
-#    x7: 0x0000000000000018
+#             x7: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e1950f6		fcvtzu x22, s7, #44
-#   x22: 0x00008a4396000000
+#            x22: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e6f19c6		fdiv d6, d14, d15
-#    v6: 0x00000000000000007ff0000000000000 (d6: inf)
+#             d6:                 0x7ff0000000000000 (inf)
 0x~~~~~~~~~~~~~~~~  1e3918ba		fdiv s26, s5, s25
-#   v26: 0x00000000000000000000000000000000 (s26: 0.00000)
+#            s26:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1f4c7b52		fmadd d18, d26, d12, d30
-#   v18: 0x00000000000000000000000000000014 (d18: 9.88131e-323)
+#            d18:                 0x7fffffffffffffff
 0x~~~~~~~~~~~~~~~~  1f1c112d		fmadd s13, s9, s28, s4
-#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+#            s13:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e6548ac		fmax d12, d5, d5
-#   v12: 0x00000000000000000000000000000000 (d12: 0.00000)
+#            d12:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e264b8c		fmax s12, s28, s6
-#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
+#            s12:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e62689c		fmaxnm d28, d4, d2
-#   v28: 0x00000000000000000000000000000000 (d28: 0.00000)
+#            d28:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e286946		fmaxnm s6, s10, s8
-#    v6: 0x00000000000000000000000000000000 (s6: 0.00000)
+#             s6:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e725a94		fmin d20, d20, d18
-#   v20: 0x00000000000000000000000000000014 (d20: 9.88131e-323)
+#            d20:                 0x7fffffffffffffff (nan)
 0x~~~~~~~~~~~~~~~~  1e3059a7		fmin s7, s13, s16
-#    v7: 0x00000000000000000000000000000000 (s7: 0.00000)
+#             s7:                         0x87027800 (-9.815e-35)
 0x~~~~~~~~~~~~~~~~  1e7e79d3		fminnm d19, d14, d30
-#   v19: 0x00000000000000000000000000000001 (d19: 4.94066e-324)
+#            d19:                 0x0000000000000001 (4.941e-324)
 0x~~~~~~~~~~~~~~~~  1e217820		fminnm s0, s1, s1
-#    v0: 0x000000000000000000000000ffffffff (s0: nan)
+#             s0:                         0xffffffff (nan)
 0x~~~~~~~~~~~~~~~~  1e6040cd		fmov d13, d6
-#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+#            d13:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e670222		fmov d2, x17
-#    v2: 0x00000000000000000000000000000000
+#             d2:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e709008		fmov d8, #0x84 (-2.5000)
-#    v8: 0x0000000000000000c004000000000000 (d8: -2.50000)
+#             d8:                 0xc004000000000000
 0x~~~~~~~~~~~~~~~~  1e204065		fmov s5, s3
-#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+#             s5:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e270299		fmov s25, w20
-#   v25: 0x00000000000000000000000000000001
+#            s25:                         0x00000001
 0x~~~~~~~~~~~~~~~~  1e20f015		fmov s21, #0x7 (2.8750)
-#   v21: 0x00000000000000000000000040380000 (s21: 2.87500)
+#            s21:                         0x40380000
 0x~~~~~~~~~~~~~~~~  1e260312		fmov w18, s24
-#   x18: 0x0000000000000001
+#            w18:         0x00000001
 0x~~~~~~~~~~~~~~~~  9e660052		fmov x18, d2
-#   x18: 0x0000000000000000
+#            x18: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1f43cfd4		fmsub d20, d30, d3, d19
-#   v20: 0x00000000000000000000000000000001 (d20: 4.94066e-324)
+#            d20:                 0xffffffffffffffff
 0x~~~~~~~~~~~~~~~~  1f04b265		fmsub s5, s19, s4, s12
-#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
+#             s5:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e770b7e		fmul d30, d27, d23
-#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
+#            d30:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e2f0a39		fmul s25, s17, s15
-#   v25: 0x000000000000000000000000ffffffff (s25: nan)
+#            s25:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  5e61de24		fmulx d4, d17, d1
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e24df2e		fmulx s14, s25, s4
-#   v14: 0x000000000000000000000000ffffffff
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e61400f		fneg d15, d0
-#   v15: 0x000000000000000080000000ffffffff (d15: -2.12200e-314)
+#            d15:                 0x80000000ffffffff (-2.122e-314)
 0x~~~~~~~~~~~~~~~~  1e2141ee		fneg s14, s15
-#   v14: 0x0000000000000000000000007fffffff (s14: nan)
+#            s14:                         0x7fffffff (nan)
 0x~~~~~~~~~~~~~~~~  1f767e00		fnmadd d0, d16, d22, d31
-#    v0: 0x00000000000000008000000000000000 (d0: -0.00000)
+#             d0:                 0x87c0000086f277ff
 0x~~~~~~~~~~~~~~~~  1f3a4a40		fnmadd s0, s18, s26, s18
-#    v0: 0x00000000000000000000000080000014 (s0: -2.80260e-44)
+#             s0:                         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1f6fd593		fnmsub d19, d12, d15, d21
-#   v19: 0x00000000000000008000000040380000 (d19: -5.32312e-315)
+#            d19:                 0x8000000040380000
 0x~~~~~~~~~~~~~~~~  1f2be81d		fnmsub s29, s0, s11, s26
-#   v29: 0x00000000000000000000000080000000 (s29: -0.00000)
+#            s29:                         0x7fffffff
 0x~~~~~~~~~~~~~~~~  1e618a7f		fnmul d31, d19, d1
-#   v31: 0x00000000000000000000000000000000 (d31: 0.00000)
+#            d31:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e318872		fnmul s18, s3, s17
-#   v18: 0x0000000000000000000000007fffffff (s18: nan)
+#            s18:                         0x80000000 (-0.000)
 0x~~~~~~~~~~~~~~~~  5ee1daa7		frecpe d7, d21
-#    v7: 0x00000000000000007ff0000000000000
+#             v7: 0x00000000000000007ff0000000000000
 0x~~~~~~~~~~~~~~~~  5ea1da3d		frecpe s29, s17
-#   v29: 0x000000000000000000000000ffffffff
+#            v29: 0x0000000000000000000000007f800000
 0x~~~~~~~~~~~~~~~~  5e71ff4b		frecps d11, d26, d17
-#   v11: 0x00000000000000004000000000000000
+#            v11: 0x00000000000000004000000000000000
 0x~~~~~~~~~~~~~~~~  5e21ff72		frecps s18, s27, s1
-#   v18: 0x000000000000000000000000ffffffff
+#            v18: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  5ee1fa4f		frecpx d15, d18
-#   v15: 0x00000000000000007fe0000000000000
+#            v15: 0x00000000000000007fe0000000000000
 0x~~~~~~~~~~~~~~~~  5ea1f945		frecpx s5, s10
-#    v5: 0x0000000000000000000000007f000000
+#             v5: 0x0000000000000000000000007f000000
 0x~~~~~~~~~~~~~~~~  1e6643d0		frinta d16, d30
-#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
+#            d16:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e2642c1		frinta s1, s22
-#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
+#             s1:                         0xffffffff (nan)
 0x~~~~~~~~~~~~~~~~  1e67c3b3		frinti d19, d29
-#   v19: 0x00000000000000000000000000000000 (d19: 0.00000)
+#            d19:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e27c2ae		frinti s14, s21
-#   v14: 0x00000000000000000000000040400000 (s14: 3.00000)
+#            s14:                         0x40400000 (3.000)
 0x~~~~~~~~~~~~~~~~  1e6543d4		frintm d20, d30
-#   v20: 0x00000000000000000000000000000000 (d20: 0.00000)
+#            d20:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e254201		frintm s1, s16
-#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
+#             s1:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e64403e		frintn d30, d1
-#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
+#            d30:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e244158		frintn s24, s10
-#   v24: 0x00000000000000000000000000000000 (s24: 0.00000)
+#            s24:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e64c284		frintp d4, d20
-#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
+#             d4:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e24c06d		frintp s13, s3
-#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
+#            s13:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e67428d		frintx d13, d20
-#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
+#            d13:                 0x0000000000000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e2740f1		frintx s17, s7
-#   v17: 0x00000000000000000000000000000000 (s17: 0.00000)
+#            s17:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  1e65c100		frintz d0, d8
-#    v0: 0x0000000000000000c000000000000000 (d0: -2.00000)
+#             d0:                 0xc000000000000000 (-2.000)
 0x~~~~~~~~~~~~~~~~  1e25c3af		frintz s15, s29
-#   v15: 0x000000000000000000000000ffffffff (s15: nan)
+#            s15:                         0x7f800000 (inf)
 0x~~~~~~~~~~~~~~~~  7ee1d955		frsqrte d21, d10
-#   v21: 0x00000000000000007ff0000000000000
+#            v21: 0x00000000000000007ff0000000000000
 0x~~~~~~~~~~~~~~~~  7ea1db31		frsqrte s17, s25
-#   v17: 0x000000000000000000000000ffffffff
+#            v17: 0x0000000000000000000000007f800000
 0x~~~~~~~~~~~~~~~~  5ef1ffa4		frsqrts d4, d29, d17
-#    v4: 0x00000000000000003ff8000000000000
+#             v4: 0x00000000000000003ff8000000000000
 0x~~~~~~~~~~~~~~~~  5eb8fc6e		frsqrts s14, s3, s24
-#   v14: 0x0000000000000000000000003fc00000
+#            v14: 0x0000000000000000000000003fc00000
 0x~~~~~~~~~~~~~~~~  1e61c22e		fsqrt d14, d17
-#   v14: 0x00000000000000001f5ffffffff00000 (d14: 1.45671e-157)
+#            d14:                 0x1f56954b41cd4293 (1.028e-157)
 0x~~~~~~~~~~~~~~~~  1e21c1c4		fsqrt s4, s14
-#    v4: 0x000000000000000000000000fff00000 (s4: nan)
+#             s4:                         0x40a21722 (5.065)
 0x~~~~~~~~~~~~~~~~  1e673a6d		fsub d13, d19, d7
-#   v13: 0x0000000000000000fff0000000000000 (d13: -inf)
+#            d13:                 0xfff0000000000000 (-inf)
 0x~~~~~~~~~~~~~~~~  1e3b3aa3		fsub s3, s21, s27
-#    v3: 0x00000000000000000000000000000000 (s3: 0.00000)
+#             s3:                         0x00000000 (0.000)
 0x~~~~~~~~~~~~~~~~  5e61da1f		scvtf d31, d16
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f68e7fa		scvtf d26, d31, #24
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  1e620206		scvtf d6, w16
-#    v6: 0x00000000000000004022000000000000 (d6: 9.00000)
+#             d6:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e42ea85		scvtf d5, w20, #6
-#    v5: 0x00000000000000003f90000000000000 (d5: 0.0156250)
+#             d5:                 0x3f90000000000000
 0x~~~~~~~~~~~~~~~~  9e620110		scvtf d16, x8
-#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
+#            d16:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e42d90f		scvtf d15, x8, #10
-#   v15: 0x00000000000000000000000000000000 (d15: 0.00000)
+#            d15:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5e21d887		scvtf s7, s4
-#    v7: 0x00000000000000007ff00000c9800000
+#             v7: 0x00000000000000007ff000004e81442e
 0x~~~~~~~~~~~~~~~~  5f32e5e8		scvtf s8, s15, #14
-#    v8: 0x0000000000000000c004000000000000
+#             v8: 0x0000000000000000c004000000000000
 0x~~~~~~~~~~~~~~~~  1e22015d		scvtf s29, w10
-#   v29: 0x00000000000000000000000000000000 (s29: 0.00000)
+#            s29:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e02d6af		scvtf s15, w21, #11
-#   v15: 0x0000000000000000000000003c200000 (s15: 0.00976562)
+#            s15:                         0x49800000
 0x~~~~~~~~~~~~~~~~  9e22035b		scvtf s27, x26
-#   v27: 0x0000000000000000000000003f800000 (s27: 1.00000)
+#            s27:                         0x00000000
 0x~~~~~~~~~~~~~~~~  9e02699a		scvtf s26, x12, #38
-#   v26: 0x0000000000000000000000003c7fffff (s26: 0.0156250)
+#            s26:                         0x3c7fffff
 0x~~~~~~~~~~~~~~~~  7e61d920		ucvtf d0, d9
-#    v0: 0x000000000000000043d00a0e21904c71
+#             v0: 0x000000000000000043d21c000020e097
 0x~~~~~~~~~~~~~~~~  7f51e6c5		ucvtf d5, d22, #47
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000003effffffffe00000
 0x~~~~~~~~~~~~~~~~  1e63037e		ucvtf d30, w27
-#   v30: 0x00000000000000003ff0000000000000 (d30: 1.00000)
+#            d30:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  1e43fe63		ucvtf d3, w19, #1
-#    v3: 0x00000000000000000000000000000000 (d3: 0.00000)
+#             d3:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  9e6302bc		ucvtf d28, x21
-#   v28: 0x00000000000000004034000000000000 (d28: 20.0000)
+#            d28:                 0x41dfffffffc00000
 0x~~~~~~~~~~~~~~~~  9e4377db		ucvtf d27, x30, #35
-#   v27: 0x00000000000000000000000000000000 (d27: 0.00000)
+#            d27:                 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  7e21d8ab		ucvtf s11, s5
-#   v11: 0x00000000000000004000000000000000
+#            v11: 0x0000000000000000400000004f7fe000
 0x~~~~~~~~~~~~~~~~  7f32e6e0		ucvtf s0, s23, #14
-#    v0: 0x000000000000000043d00a0e4783c64c
+#             v0: 0x000000000000000043d21c00480a8294
 0x~~~~~~~~~~~~~~~~  1e230274		ucvtf s20, w19
-#   v20: 0x00000000000000000000000000000000 (s20: 0.00000)
+#            s20:                         0x00000000
 0x~~~~~~~~~~~~~~~~  1e03bad5		ucvtf s21, w22, #18
-#   v21: 0x00000000000000000000000046160000 (s21: 9600.00)
+#            s21:                         0x00000000
 0x~~~~~~~~~~~~~~~~  9e2301a6		ucvtf s6, x13
-#    v6: 0x00000000000000000000000041d80000 (s6: 27.0000)
+#             s6:                         0x5f000000
 0x~~~~~~~~~~~~~~~~  9e03ac47		ucvtf s7, x2, #21
-#    v7: 0x00000000000000000000000038ff0000 (s7: 0.000121593)
+#             s7:                         0x38ff0000
 0x~~~~~~~~~~~~~~~~  5ee0b813		abs d19, d0
-#   v19: 0x000000000000000043d00a0e4783c64c
+#            v19: 0x000000000000000043d21c00480a8294
 0x~~~~~~~~~~~~~~~~  4e20b970		abs v16.16b, v11.16b
-#   v16: 0x00000000000000004000000000000000
+#            v16: 0x0000000000000000400000004f7f2000
 0x~~~~~~~~~~~~~~~~  4ee0bbe0		abs v0.2d, v31.2d
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0bb3b		abs v27.2s, v25.2s
-#   v27: 0x00000000000000000000000000000001
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e60bb75		abs v21.4h, v27.4h
-#   v21: 0x00000000000000000000000000000001
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea0b830		abs v16.4s, v1.4s
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e20b8bf		abs v31.8b, v5.8b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000003e01010101200000
 0x~~~~~~~~~~~~~~~~  4e60b9bd		abs v29.8h, v13.8h
-#   v29: 0x00000000000000000010000000000000
+#            v29: 0x00000000000000000010000000000000
 0x~~~~~~~~~~~~~~~~  5ef184aa		add d10, d5, d17
-#   v10: 0x000000000000000000000000ffffffff
+#            v10: 0x00000000000000003f0000007f600000
 0x~~~~~~~~~~~~~~~~  4e3785ff		add v31.16b, v15.16b, v23.16b
-#   v31: 0x403ba7b141b670b1403ef2e47d0325e4
+#            v31: 0x495000018a83940149500000d3029400
 0x~~~~~~~~~~~~~~~~  4eee87ea		add v10.2d, v31.2d, v14.2d
-#   v10: 0x403ba7b141b670b15f9ef2e47cf325e4
+#            v10: 0x495000018a83940168a6954c14cfd693
 0x~~~~~~~~~~~~~~~~  0eb385cf		add v15.2s, v14.2s, v19.2s
-#   v15: 0x000000000000000063300a0d4773c64c
+#            v15: 0x00000000000000006328b14b89d7c527
 0x~~~~~~~~~~~~~~~~  0e7186fb		add v27.4h, v23.4h, v17.4h
-#   v27: 0x0000000000000000403ef2e441e225e3
+#            v27: 0x0000000000000000495000000a029400
 0x~~~~~~~~~~~~~~~~  4ebd8799		add v25.4s, v28.4s, v29.4s
-#   v25: 0x00000000000000004044000000000000
+#            v25: 0x000000000000000041efffffffc00000
 0x~~~~~~~~~~~~~~~~  0e3284ed		add v13.8b, v7.8b, v18.8b
-#   v13: 0x00000000000000000000000037feffff
+#            v13: 0x00000000000000000000000037feffff
 0x~~~~~~~~~~~~~~~~  4e618444		add v4.8h, v2.8h, v1.8h
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eaf41ca		addhn v10.2s, v14.2d, v15.2d
-#   v10: 0x00000000000000000000000082900a0d
+#            v10: 0x000000000000000000000000827f4696
 0x~~~~~~~~~~~~~~~~  0e7a43ca		addhn v10.4h, v30.4s, v26.4s
-#   v10: 0x0000000000000000000000003ff03c7f
+#            v10: 0x00000000000000000000000000003c7f
 0x~~~~~~~~~~~~~~~~  0e36419f		addhn v31.8b, v12.8h, v22.8h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  4e3442b0		addhn2 v16.16b, v21.8h, v20.8h
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb14040		addhn2 v0.4s, v2.2d, v17.2d
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7140ff		addhn2 v31.8h, v7.4s, v17.4s
-#   v31: 0x00000000000038fe0000000000000000
+#            v31: 0x000000000000b87f000000000000ffff
 0x~~~~~~~~~~~~~~~~  5ef1ba6e		addp d14, v19.2d
-#   v14: 0x000000000000000043d00a0e4783c64c
+#            v14: 0x000000000000000043d21c00480a8294
 0x~~~~~~~~~~~~~~~~  4e3cbd03		addp v3.16b, v8.16b, v28.16b
-#    v3: 0x000000007400000000000000c4000000
+#             v3: 0x0000000020febf0000000000c4000000
 0x~~~~~~~~~~~~~~~~  4ef1bca8		addp v8.2d, v5.2d, v17.2d
-#    v8: 0x00000000ffffffff0000000000000000
+#             v8: 0x000000007f8000003effffffffe00000
 0x~~~~~~~~~~~~~~~~  0ebabfd6		addp v22.2s, v30.2s, v26.2s
-#   v22: 0x00000000000000003c7fffff3ff00000
+#            v22: 0x00000000000000003c7fffff00000000
 0x~~~~~~~~~~~~~~~~  0e6ebf1d		addp v29.4h, v24.4h, v14.4h
-#   v29: 0x00000000000000004dde0dcf00000000
+#            v29: 0x00000000000000005fd2ca9e00000000
 0x~~~~~~~~~~~~~~~~  4eb8bf5e		addp v30.4s, v26.4s, v24.4s
-#   v30: 0x0000000000000000000000003c7fffff
+#            v30: 0x0000000000000000000000003c7fffff
 0x~~~~~~~~~~~~~~~~  0e27bf4c		addp v12.8b, v26.8b, v7.8b
-#   v12: 0x0000000000000000000037000000bbfe
+#            v12: 0x0000000000000000000037000000bbfe
 0x~~~~~~~~~~~~~~~~  4e6cbd11		addp v17.8h, v8.8h, v12.8h
-#   v17: 0x000000003700bbfe0000fffe00000000
+#            v17: 0x000000003700bbfe00007f803efeffe0
 0x~~~~~~~~~~~~~~~~  4e31bafb		addv b27, v23.16b
-#   v27: 0x0000000000000000000000000000006c
+#            v27: 0x00000000000000000000000000000075
 0x~~~~~~~~~~~~~~~~  0e31ba8c		addv b12, v20.8b
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e71bbdb		addv h27, v30.4h
-#   v27: 0x00000000000000000000000000003c7e
+#            v27: 0x00000000000000000000000000003c7e
 0x~~~~~~~~~~~~~~~~  4e71b9d3		addv h19, v14.8h
-#   v19: 0x00000000000000000000000000005bad
+#            v19: 0x00000000000000000000000000002a70
 0x~~~~~~~~~~~~~~~~  4eb1bb6e		addv s14, v27.4s
-#   v14: 0x00000000000000000000000000003c7e
+#            v14: 0x00000000000000000000000000003c7e
 0x~~~~~~~~~~~~~~~~  4e3b1d0a		and v10.16b, v8.16b, v27.16b
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e301c25		and v5.8b, v1.8b, v16.8b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e781c7a		bic v26.16b, v3.16b, v24.16b
-#   v26: 0x000000007400000000000000c4000000
+#            v26: 0x0000000020febf0000000000c4000000
 0x~~~~~~~~~~~~~~~~  2f075487		bic v7.2s, #0xe4, lsl #16
-#    v7: 0x000000000000000000000000381b0000
+#             v7: 0x000000000000000000000000381b0000
 0x~~~~~~~~~~~~~~~~  2f01b47c		bic v28.4h, #0x23, lsl #8
-#   v28: 0x00000000000000004034000000000000
+#            v28: 0x000000000000000040dfdcffdcc00000
 0x~~~~~~~~~~~~~~~~  6f05159d		bic v29.4s, #0xac, lsl #0
-#   v29: 0x00000000000000004dde0d4300000000
+#            v29: 0x00000000000000005fd2ca1200000000
 0x~~~~~~~~~~~~~~~~  0e751fec		bic v12.8b, v31.8b, v21.8b
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  6f049712		bic v18.8h, #0x98, lsl #0
-#   v18: 0x000000000000000000000000ff67ff67
+#            v18: 0x000000000000000000000000ff67ff67
 0x~~~~~~~~~~~~~~~~  6ee81f4c		bif v12.16b, v26.16b, v8.16b
-#   v12: 0x000000000000000000000000c4000000
+#            v12: 0x00000000007ebf000000000000000000
 0x~~~~~~~~~~~~~~~~  2efb1ee2		bif v2.8b, v23.8b, v27.8b
-#    v2: 0x0000000000000000403ef2e441e30180
+#             v2: 0x0000000000000000495000008a828000
 0x~~~~~~~~~~~~~~~~  6ead1c68		bit v8.16b, v3.16b, v13.16b
-#    v8: 0x00000000ffffffff0000000004000000
+#             v8: 0x000000007f8000003effffffcc000000
 0x~~~~~~~~~~~~~~~~  2eb71ca5		bit v5.8b, v5.8b, v23.8b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e771fe9		bsl v9.16b, v31.16b, v23.16b
-#    v9: 0x00128220009270f80016c26000c22160
+#             v9: 0x0100000008009801010000000800dc00
 0x~~~~~~~~~~~~~~~~  2e631cee		bsl v14.8b, v7.8b, v3.8b
-#   v14: 0x000000000000000000000000c4000000
+#            v14: 0x000000000000000000000000c4000000
 0x~~~~~~~~~~~~~~~~  4e2048bd		cls v29.16b, v5.16b
-#   v29: 0x07070707070707070707070707070707
+#            v29: 0x07070707070707070707070707070707
 0x~~~~~~~~~~~~~~~~  0ea04815		cls v21.2s, v0.2s
-#   v21: 0x00000000000000000000001f0000001f
+#            v21: 0x00000000000000000000001f0000001f
 0x~~~~~~~~~~~~~~~~  0e604981		cls v1.4h, v12.4h
-#    v1: 0x0000000000000000000f000f0001000f
+#             v1: 0x0000000000000000000f000f000f000f
 0x~~~~~~~~~~~~~~~~  4ea0495b		cls v27.4s, v10.4s
-#   v27: 0x0000001f0000001f0000001f0000001f
+#            v27: 0x0000001f0000001f0000001f0000001f
 0x~~~~~~~~~~~~~~~~  0e204893		cls v19.8b, v4.8b
-#   v19: 0x00000000000000000707070707070707
+#            v19: 0x00000000000000000707070707070707
 0x~~~~~~~~~~~~~~~~  4e6049cf		cls v15.8h, v14.8h
-#   v15: 0x000f000f000f000f000f000f0001000f
+#            v15: 0x000f000f000f000f000f000f0001000f
 0x~~~~~~~~~~~~~~~~  6e204881		clz v1.16b, v4.16b
-#    v1: 0x08080808080808080808080808080808
+#             v1: 0x08080808080808080808080808080808
 0x~~~~~~~~~~~~~~~~  2ea04a3b		clz v27.2s, v17.2s
-#   v27: 0x00000000000000000000001000000020
+#            v27: 0x00000000000000000000001100000002
 0x~~~~~~~~~~~~~~~~  2e604929		clz v9.4h, v9.4h
-#    v9: 0x0000000000000000000b000000080002
+#             v9: 0x00000000000000000007001000040000
 0x~~~~~~~~~~~~~~~~  6ea049ff		clz v31.4s, v15.4s
-#   v31: 0x0000000c0000000c0000000c0000000f
+#            v31: 0x0000000c0000000c0000000c0000000f
 0x~~~~~~~~~~~~~~~~  2e204a6e		clz v14.8b, v19.8b
-#   v14: 0x00000000000000000505050505050505
+#            v14: 0x00000000000000000505050505050505
 0x~~~~~~~~~~~~~~~~  6e604966		clz v6.8h, v11.8h
-#    v6: 0x00100010001000100001001000100010
+#             v6: 0x00100010001000100001001000010000
 0x~~~~~~~~~~~~~~~~  7efd8cb2		cmeq d18, d5, d29
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee09bee		cmeq d14, d31, #0
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e368c73		cmeq v19.16b, v3.16b, v22.16b
-#   v19: 0xffffffff00ffffff000000000000ffff
+#            v19: 0xffffffff000000ff0000000000ffffff
 0x~~~~~~~~~~~~~~~~  4e20992f		cmeq v15.16b, v9.16b, #0
-#   v15: 0xffffffffffffffffff00ffffff00ff00
+#            v15: 0xffffffffffffffffff00ff00ff00ffff
 0x~~~~~~~~~~~~~~~~  6eea8e0c		cmeq v12.2d, v16.2d, v10.2d
-#   v12: 0xffffffffffffffffffffffffffffffff
+#            v12: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4ee09ac8		cmeq v8.2d, v22.2d, #0
-#    v8: 0xffffffffffffffff0000000000000000
+#             v8: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  2ea98c62		cmeq v2.2s, v3.2s, v9.2s
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea09b30		cmeq v16.2s, v25.2s, #0
-#   v16: 0x000000000000000000000000ffffffff
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e748ee6		cmeq v6.4h, v23.4h, v20.4h
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000ffff00000000
 0x~~~~~~~~~~~~~~~~  0e6099b0		cmeq v16.4h, v13.4h, #0
-#   v16: 0x0000000000000000ffffffff00000000
+#            v16: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  6ea28e35		cmeq v21.4s, v17.4s, v2.4s
-#   v21: 0xffffffff0000000000000000ffffffff
+#            v21: 0xffffffff000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea09b26		cmeq v6.4s, v25.4s, #0
-#    v6: 0xffffffffffffffff00000000ffffffff
+#             v6: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  2e228db0		cmeq v16.8b, v13.8b, v2.8b
-#   v16: 0x0000000000000000ffffffff00000000
+#            v16: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  0e209a15		cmeq v21.8b, v16.8b, #0
-#   v21: 0x000000000000000000000000ffffffff
+#            v21: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  6e798cf4		cmeq v20.8h, v7.8h, v25.8h
-#   v20: 0xffffffffffffffff0000ffff0000ffff
+#            v20: 0xffffffffffffffff000000000000ffff
 0x~~~~~~~~~~~~~~~~  4e60991a		cmeq v26.8h, v8.8h, #0
-#   v26: 0x0000000000000000ffffffffffffffff
+#            v26: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  5eff3db0		cmge d16, d13, d31
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ee08b19		cmge d25, d24, #0
-#   v25: 0x0000000000000000ffffffffffffffff
+#            v25: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e313e71		cmge v17.16b, v19.16b, v17.16b
-#   v17: 0x000000000000ffffffffffffffff0000
+#            v17: 0x0000000000ffffffffff00ff00ffffff
 0x~~~~~~~~~~~~~~~~  6e208bd6		cmge v22.16b, v30.16b, #0
-#   v22: 0xffffffffffffffffffffffffffff0000
+#            v22: 0xffffffffffffffffffffffffffff0000
 0x~~~~~~~~~~~~~~~~  4efa3e9c		cmge v28.2d, v20.2d, v26.2d
-#   v28: 0x0000000000000000ffffffffffffffff
+#            v28: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ee08ae6		cmge v6.2d, v23.2d, #0
-#    v6: 0xffffffffffffffffffffffffffffffff
+#             v6: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0ea33ed9		cmge v25.2s, v22.2s, v3.2s
-#   v25: 0x000000000000000000000000ffffffff
+#            v25: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  2ea08975		cmge v21.2s, v11.2s, #0
-#   v21: 0x0000000000000000ffffffffffffffff
+#            v21: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0e6c3c70		cmge v16.4h, v3.4h, v12.4h
-#   v16: 0x0000000000000000ffffffff0000ffff
+#            v16: 0x0000000000000000ffffffff0000ffff
 0x~~~~~~~~~~~~~~~~  2e608937		cmge v23.4h, v9.4h, #0
-#   v23: 0x0000000000000000ffffffffffffffff
+#            v23: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4eab3c47		cmge v7.4s, v2.4s, v11.4s
-#    v7: 0xffffffffffffffff00000000ffffffff
+#             v7: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  6ea08ac0		cmge v0.4s, v22.4s, #0
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e293fca		cmge v10.8b, v30.8b, v9.8b
-#   v10: 0x0000000000000000ff00ffffffff0000
+#            v10: 0x0000000000000000ff00ff00ffff0000
 0x~~~~~~~~~~~~~~~~  2e208915		cmge v21.8b, v8.8b, #0
-#   v21: 0x0000000000000000ffffffffffffffff
+#            v21: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e7a3ce2		cmge v2.8h, v7.8h, v26.8h
-#    v2: 0x0000000000000000ffffffffffffffff
+#             v2: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e608953		cmge v19.8h, v10.8h, #0
-#   v19: 0xffffffffffffffff000000000000ffff
+#            v19: 0xffffffffffffffff000000000000ffff
 0x~~~~~~~~~~~~~~~~  5ee135a6		cmgt d6, d13, d1
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee08b1e		cmgt d30, d24, #0
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e3b3734		cmgt v20.16b, v25.16b, v27.16b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e208b20		cmgt v0.16b, v25.16b, #0
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee13736		cmgt v22.2d, v25.2d, v1.2d
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee08a10		cmgt v16.2d, v16.2d, #0
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eaf3525		cmgt v5.2s, v9.2s, v15.2s
-#    v5: 0x0000000000000000ffffffffffffffff
+#             v5: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0ea08a4c		cmgt v12.2s, v18.2s, #0
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6b365c		cmgt v28.4h, v18.4h, v11.4h
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  0e608876		cmgt v22.4h, v3.4h, #0
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ebb3565		cmgt v5.4s, v11.4s, v27.4s
-#    v5: 0x0000000000000000ffffffff00000000
+#             v5: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4ea08a8d		cmgt v13.4s, v20.4s, #0
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e2737fb		cmgt v27.8b, v31.8b, v7.8b
-#   v27: 0x0000000000000000000000ffffffffff
+#            v27: 0x0000000000000000000000ff000000ff
 0x~~~~~~~~~~~~~~~~  0e208805		cmgt v5.8b, v0.8b, #0
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6d3796		cmgt v22.8h, v28.8h, v13.8h
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e608846		cmgt v6.8h, v2.8h, #0
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ef63515		cmhi d21, d8, d22
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e333672		cmhi v18.16b, v19.16b, v19.16b
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ef53407		cmhi v7.2d, v0.2d, v21.2d
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea0366f		cmhi v15.2s, v19.2s, v0.2s
-#   v15: 0x000000000000000000000000ffffffff
+#            v15: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  2e6c34ff		cmhi v31.4h, v7.4h, v12.4h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb63609		cmhi v9.4s, v16.4s, v22.4s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3c3707		cmhi v7.8b, v24.8b, v28.8b
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e79354b		cmhi v11.8h, v10.8h, v25.8h
-#   v11: 0x0000000000000000ffffffff00000000
+#            v11: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  7ef13d81		cmhs d1, d12, d17
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e3e3f35		cmhs v21.16b, v25.16b, v30.16b
-#   v21: 0xffffffffffffffffffffffffffffffff
+#            v21: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6efa3c48		cmhs v8.2d, v2.2d, v26.2d
-#    v8: 0xffffffffffffffffffffffffffffffff
+#             v8: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ebd3ec1		cmhs v1.2s, v22.2s, v29.2s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e7e3fda		cmhs v26.4h, v30.4h, v30.4h
-#   v26: 0x0000000000000000ffffffffffffffff
+#            v26: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6eb03e93		cmhs v19.4s, v20.4s, v16.4s
-#   v19: 0xffffffffffffffffffffffffffffffff
+#            v19: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e3a3c61		cmhs v1.8b, v3.8b, v26.8b
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e683f94		cmhs v20.8h, v28.8h, v8.8h
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x0000000000000000000000000000ffff
 0x~~~~~~~~~~~~~~~~  7ee09b1e		cmle d30, d24, #0
-#   v30: 0x0000000000000000ffffffffffffffff
+#            v30: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e209860		cmle v0.16b, v3.16b, #0
-#    v0: 0xffffffff00ffffffffffffffffffffff
+#             v0: 0xffffffff00ffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ee09bc2		cmle v2.2d, v30.2d, #0
-#    v2: 0xffffffffffffffffffffffffffffffff
+#             v2: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ea09947		cmle v7.2s, v10.2s, #0
-#    v7: 0x0000000000000000ffffffffffffffff
+#             v7: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e609be9		cmle v9.4h, v31.4h, #0
-#    v9: 0x0000000000000000ffffffffffffffff
+#             v9: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ea09a49		cmle v9.4s, v18.4s, #0
-#    v9: 0xffffffffffffffffffffffffffffffff
+#             v9: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e209bf5		cmle v21.8b, v31.8b, #0
-#   v21: 0x0000000000000000ffffffffffffffff
+#            v21: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e609abd		cmle v29.8h, v21.8h, #0
-#   v29: 0xffffffffffffffffffffffffffffffff
+#            v29: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  5ee0aaf9		cmlt d25, d23, #0
-#   v25: 0x0000000000000000ffffffffffffffff
+#            v25: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e20aaa7		cmlt v7.16b, v21.16b, #0
-#    v7: 0x0000000000000000ffffffffffffffff
+#             v7: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4ee0abc7		cmlt v7.2d, v30.2d, #0
-#    v7: 0x0000000000000000ffffffffffffffff
+#             v7: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0ea0ab99		cmlt v25.2s, v28.2s, #0
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e60a960		cmlt v0.4h, v11.4h, #0
-#    v0: 0x0000000000000000ffffffff00000000
+#             v0: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  4ea0a8b8		cmlt v24.4s, v5.4s, #0
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e20a97a		cmlt v26.8b, v11.8b, #0
-#   v26: 0x0000000000000000ffffffff00000000
+#            v26: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  4e60aaa1		cmlt v1.8h, v21.8h, #0
-#    v1: 0x0000000000000000ffffffffffffffff
+#             v1: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  5efe8efc		cmtst d28, d23, d30
-#   v28: 0x0000000000000000ffffffffffffffff
+#            v28: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e3f8cda		cmtst v26.16b, v6.16b, v31.16b
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee48ea1		cmtst v1.2d, v21.2d, v4.2d
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eb48f5b		cmtst v27.2s, v26.2s, v20.2s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e728c1a		cmtst v26.4h, v0.4h, v18.4h
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea48e19		cmtst v25.4s, v16.4s, v4.4s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e298d4b		cmtst v11.8b, v10.8b, v9.8b
-#   v11: 0x0000000000000000ff00ffffffff0000
+#            v11: 0x0000000000000000ff00ff00ffff0000
 0x~~~~~~~~~~~~~~~~  4e618c40		cmtst v0.8h, v2.8h, v1.8h
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2059f9		cnt v25.16b, v15.16b
-#   v25: 0x00000000000000000000000008080808
+#            v25: 0x00000000000000000000000008080808
 0x~~~~~~~~~~~~~~~~  0e2058dc		cnt v28.8b, v6.8b
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e0f04e6		dup v6.16b, v7.b[7]
-#    v6: 0xffffffffffffffffffffffffffffffff
+#             v6: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e010e89		dup v9.16b, w20
-#    v9: 0x01010101010101010101010101010101
+#             v9: 0x01010101010101010101010101010101
 0x~~~~~~~~~~~~~~~~  4e1805ac		dup v12.2d, v13.d[1]
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e080fe9		dup v9.2d, xzr
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e140744		dup v4.2s, v26.s[2]
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e040d83		dup v3.2s, w12
-#    v3: 0x0000000000000000ffffff7dffffff7d
+#             v3: 0x0000000000000000ffffff7dffffff7d
 0x~~~~~~~~~~~~~~~~  0e1e04b6		dup v22.4h, v5.h[7]
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e020f30		dup v16.4h, w25
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e140554		dup v20.4s, v10.s[2]
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e040cea		dup v10.4s, w7
-#   v10: 0x00000018000000180000001800000018
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e0507de		dup v30.8b, v30.b[2]
-#   v30: 0x0000000000000000ffffffffffffffff
+#            v30: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0e010dff		dup v31.8b, w15
-#   v31: 0x00000000000000000101010101010101
+#            v31: 0x00000000000000000101010101010101
 0x~~~~~~~~~~~~~~~~  4e12063c		dup v28.8h, v17.h[4]
-#   v28: 0xffffffffffffffffffffffffffffffff
+#            v28: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e020c62		dup v2.8h, w3
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e231f3d		eor v29.16b, v25.16b, v3.16b
-#   v29: 0x0000000000000000ffffff7df7f7f775
+#            v29: 0x0000000000000000ffffff7df7f7f775
 0x~~~~~~~~~~~~~~~~  2e3c1e03		eor v3.8b, v16.8b, v28.8b
-#    v3: 0x0000000000000000ffffffffffffffff
+#             v3: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e060b41		ext v1.16b, v26.16b, v6.16b, #1
-#    v1: 0xff000000000000000000000000000000
+#             v1: 0xff000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e010bc2		ext v2.8b, v30.8b, v1.8b, #1
-#    v2: 0x000000000000000000ffffffffffffff
+#             v2: 0x000000000000000000ffffffffffffff
 0x~~~~~~~~~~~~~~~~  4c402012		ld1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
-#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x3f3e3d3c3b3a39383736353433323130
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc22037		ld1 {v23.16b, v24.16b, v25.16b, v26.16b}, [x1], x2
-#   v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x0b0a09080706050403020100fffefdfc <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0b0a09080706050403020100fffefdfc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfb <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xeb <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xdb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf2025		ld1 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
-#    v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0a09080706050403020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x0a09080706050403020100fffefdfcfb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xeb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c406012		ld1 {v18.16b, v19.16b, v20.16b}, [x0]
-#   v18: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2602d		ld1 {v13.16b, v14.16b, v15.16b}, [x1], x2
-#   v13: 0x1a191817161514131211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x2a292827262524232221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x3a393837363534333231302f2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x3a393837363534333231302f2e2d2c2b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x2a292827262524232221201f1e1d1c1b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x1a191817161514131211100f0e0d0c0b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf6033		ld1 {v19.16b, v20.16b, v21.16b}, [x1], #48
-#   v19: 0x191817161514131211100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x292827262524232221201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x393837363534333231302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x393837363534333231302f2e2d2c2b2a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x292827262524232221201f1e1d1c1b1a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x191817161514131211100f0e0d0c0b0a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40a011		ld1 {v17.16b, v18.16b}, [x0]
-#   v17: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2a034		ld1 {v20.16b, v21.16b}, [x1], x2
-#   v20: 0x494847464544434241403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x595857565554535251504f4e4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x595857565554535251504f4e4d4c4b4a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x59 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x494847464544434241403f3e3d3c3b3a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdfa03c		ld1 {v28.16b, v29.16b}, [x1], #32
-#   v28: 0x4847464544434241403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x5857565554535251504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x5857565554535251504f4e4d4c4b4a49
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x49 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x4847464544434241403f3e3d3c3b3a39
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40701d		ld1 {v29.16b}, [x0]
-#   v29: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc27035		ld1 {v21.16b}, [x1], x2
-#   v21: 0x6867666564636261605f5e5d5c5b5a59 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x6867666564636261605f5e5d5c5b5a59
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x59 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x5a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x5b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x5c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x5d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x5e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x5f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x60 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x61 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x62 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x63 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x64 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x65 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x66 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x67 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x68 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf7024		ld1 {v4.16b}, [x1], #16
-#    v4: 0x67666564636261605f5e5d5c5b5a5958 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v4: 0x67666564636261605f5e5d5c5b5a5958
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x59 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x5a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x5b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x5c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x5d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x5e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x5f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x60 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x61 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x62 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x63 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x64 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x65 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x66 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x67 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c402c04		ld1 {v4.1d, v5.1d, v6.1d, v7.1d}, [x0]
-#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000001f1e1d1c1b1a1918 (d7: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc22c31		ld1 {v17.1d, v18.1d, v19.1d, v20.1d}, [x1], x2
-#   v17: 0x00000000000000006f6e6d6c6b6a6968 (d17: 5.76650e+228) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000007776757473727170 (d18: 2.89670e+267) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000007f7e7d7c7b7a7978 (d19: 1.33818e+306) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000008786858483828180 (d20: -2.08158e-272) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x8786858483828180 (-2.082e-272)
+#                                                  ╙─ 0x8786858483828180 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x7f7e7d7c7b7a7978 (1.338e+306)
+#                                                  ╙─ 0x7f7e7d7c7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#            d18:                 0x7776757473727170 (2.897e+267)
+#                                                  ╙─ 0x7776757473727170 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x6f6e6d6c6b6a6968 (5.766e+228)
+#                                                  ╙─ 0x6f6e6d6c6b6a6968 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf2c3c		ld1 {v28.1d, v29.1d, v30.1d, v31.1d}, [x1], #32
-#   v28: 0x00000000000000006e6d6c6b6a696867 (d28: 8.50866e+223) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000767574737271706f (d29: 4.22243e+262) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000007e7d7c7b7a797877 (d30: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x0000000000000000868584838281807f (d31: -3.03465e-277) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x868584838281807f (-3.035e-277)
+#                                                  ╙─ 0x868584838281807f <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0x7e7d7c7b7a797877 (1.975e+301)
+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x767574737271706f (4.222e+262)
+#                                                  ╙─ 0x767574737271706f <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x6e6d6c6b6a696867 (8.509e+223)
+#                                                  ╙─ 0x6e6d6c6b6a696867 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c406c14		ld1 {v20.1d, v21.1d, v22.1d}, [x0]
-#   v20: 0x0000000000000000ff0000850002ff01 (d20: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x00000000000000000000000000fffeff (d21: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x00000000000000001700000000000000 (d22: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc26c33		ld1 {v19.1d, v20.1d, v21.1d}, [x1], x2
-#   v19: 0x00000000000000008e8d8c8b8a898887 (d19: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x0000000000000000969594939291908f (d20: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x00000000000000009e9d9c9b9a999897 (d21: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x9e9d9c9b9a999897 (-3.291e-161)
+#                                                  ╙─ 0x9e9d9c9b9a999897 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x969594939291908f (-7.048e-200)
+#                                                  ╙─ 0x969594939291908f <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x8e8d8c8b8a898887 (-1.418e-238)
+#                                                  ╙─ 0x8e8d8c8b8a898887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf6c2c		ld1 {v12.1d, v13.1d, v14.1d}, [x1], #24
-#   v12: 0x00000000000000008d8c8b8a89888786 (d12: -2.09028e-243) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x00000000000000009594939291908f8e (d13: -1.02545e-204) <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x00000000000000009d9c9b9a99989796 (d14: -4.85140e-166) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x9d9c9b9a99989796 (-4.851e-166)
+#                                                  ╙─ 0x9d9c9b9a99989796 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x9594939291908f8e (-1.025e-204)
+#                                                  ╙─ 0x9594939291908f8e <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x8d8c8b8a89888786 (-2.090e-243)
+#                                                  ╙─ 0x8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40ac1d		ld1 {v29.1d, v30.1d}, [x0]
-#   v29: 0x0000000000000000ff0000850002ff01 (d29: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000000000000000fffeff (d30: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2ac3f		ld1 {v31.1d, v0.1d}, [x1], x2
-#   v31: 0x0000000000000000a5a4a3a2a1a09f9e (d31: -2.38202e-127) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x0000000000000000adacabaaa9a8a7a6 (d0: -1.12597e-88) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xadacabaaa9a8a7a6 (-1.126e-88)
+#                                                  ╙─ 0xadacabaaa9a8a7a6 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0xa5a4a3a2a1a09f9e (-2.382e-127)
+#                                                  ╙─ 0xa5a4a3a2a1a09f9e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdfac23		ld1 {v3.1d, v4.1d}, [x1], #16
-#    v3: 0x0000000000000000a4a3a2a1a09f9e9d (d3: -3.45787e-132) <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000acabaaa9a8a7a6a5 (d4: -1.65794e-93) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xacabaaa9a8a7a6a5 (-1.658e-93)
+#                                                  ╙─ 0xacabaaa9a8a7a6a5 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xa4a3a2a1a09f9e9d (-3.458e-132)
+#                                                  ╙─ 0xa4a3a2a1a09f9e9d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c407c1c		ld1 {v28.1d}, [x0]
-#   v28: 0x0000000000000000ff0000850002ff01 (d28: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc27c2b		ld1 {v11.1d}, [x1], x2
-#   v11: 0x0000000000000000b4b3b2b1b0afaead (d11: -8.03348e-55) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xb4b3b2b1b0afaead (-8.033e-55)
+#                                                  ╙─ 0xb4b3b2b1b0afaead <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf7c3d		ld1 {v29.1d}, [x1], #8
-#   v29: 0x0000000000000000b3b2b1b0afaeadac (d29: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c402c1c		ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0]
-#   v28: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x3f3e3d3c3b3a39383736353433323130 (0.000461414, 9.95833e-43) <- 0x~~~~~~~~~~~~~~~~
+#            v31: 0x3f3e3d3c3b3a39383736353433323130 (0.0004614, 9.958e-43)
+#                                  ║               ╙─ 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x2f2e2d2c2b2a29282726252423222120 (1.988e-81, 4.288e-120)
+#                                  ║               ╙─ 0x2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc22c28		ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [x1], x2
-#    v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.70315e+18, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.28100e+95, -1.31369e+57) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.45943e+173, -3.04943e+134) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.39104e+250, -7.07849e+211) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.391e+250, -7.078e+211)
+#                                  ║               ╙─ 0xebeae9e8e7e6e5e4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xf3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.459e+173, -3.049e+134)
+#                                  ║               ╙─ 0xdbdad9d8d7d6d5d4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.281e+95, -1.314e+57)
+#                                  ║               ╙─ 0xcbcac9c8c7c6c5c4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xd3d2d1d0cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.703e+18, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xc3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf2c2e		ld1 {v14.2d, v15.2d, v16.2d, v17.2d}, [x1], #64
-#   v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.90391e+13, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.07279e+90, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.10851e+168, -4.47908e+129) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.90012e+245, -1.03980e+207) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.900e+245, -1.040e+207)
+#                                  ║               ╙─ 0xeae9e8e7e6e5e4e3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xf2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.109e+168, -4.479e+129)
+#                                  ║               ╙─ 0xdad9d8d7d6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.073e+90, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.904e+13, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xc2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c406c1a		ld1 {v26.2d, v27.2d, v28.2d}, [x0]
-#   v26: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.98829e-81, 4.28794e-120) <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.988e-81, 4.288e-120)
+#                                  ║               ╙─ 0x2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc26c25		ld1 {v5.2d, v6.2d, v7.2d}, [x1], x2
-#    v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.07812e-299, -2.41385e+284) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x1211100f0e0d0c0b0a09080706050403 (1.18008e-221, 2.54377e-260) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x2221201f1e1d1c1b1a19181716151413 (2.74293e-144, 5.90574e-183) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2221201f1e1d1c1b1a19181716151413 (2.743e-144, 5.906e-183)
+#                                  ║               ╙─ 0x1a19181716151413 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1211100f0e0d0c0b0a09080706050403 (1.180e-221, 2.544e-260)
+#                                  ║               ╙─ 0x0a09080706050403 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.078e-299, -2.414e+284)
+#                                  ║               ╙─ 0xfaf9f8f7f6f5f4f3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf6c3a		ld1 {v26.2d, v27.2d, v28.2d}, [x1], #48
-#   v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.74681e-304, -3.54087e+279) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x11100f0e0d0c0b0a0908070605040302 (1.69471e-226, 3.72581e-265) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x21201f1e1d1c1b1a1918171615141312 (3.94003e-149, 8.65093e-188) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x21201f1e1d1c1b1a1918171615141312 (3.940e-149, 8.651e-188)
+#                                  ║               ╙─ 0x1918171615141312 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x21201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x11100f0e0d0c0b0a0908070605040302 (1.695e-226, 3.726e-265)
+#                                  ║               ╙─ 0x0908070605040302 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x11100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.747e-304, -3.541e+279)
+#                                  ║               ╙─ 0xf9f8f7f6f5f4f3f2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0100fffefdfcfbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40ac12		ld1 {v18.2d, v19.2d}, [x0]
-#   v18: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x1f1e1d1c1b1a19181700000000000000 (8.56775e-159, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2ac35		ld1 {v21.2d, v22.2d}, [x1], x2
-#   v21: 0x31302f2e2d2c2b2a2928272625242322 (9.15999e-72, 2.00864e-110) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x41403f3e3d3c3b3a3938373635343332 (2.12953e+06, 4.66377e-33) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x41403f3e3d3c3b3a3938373635343332 (2.130e+06, 4.664e-33)
+#                                  ║               ╙─ 0x3938373635343332 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x41403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x31302f2e2d2c2b2a2928272625242322 (9.160e-72, 2.009e-110)
+#                                  ║               ╙─ 0x2928272625242322 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x31302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdfac31		ld1 {v17.2d, v18.2d}, [x1], #32
-#   v17: 0x302f2e2d2c2b2a292827262524232221 (1.34639e-76, 2.93754e-115) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x403f3e3d3c3b3a393837363534333231 (31.2431, 6.82132e-38) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0x403f3e3d3c3b3a393837363534333231 (31.24, 6.821e-38)
+#                                  ║               ╙─ 0x3837363534333231 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x302f2e2d2c2b2a292827262524232221 (1.346e-76, 2.938e-115)
+#                                  ║               ╙─ 0x2827262524232221 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x302f2e2d2c2b2a29 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c407c05		ld1 {v5.2d}, [x0]
-#    v5: 0x0000000000fffeffff0000850002ff01 (8.28892e-317, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc27c26		ld1 {v6.2d}, [x1], x2
-#    v6: 0x504f4e4d4c4b4a494847464544434241 (7.24994e+78, 1.58398e+40) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x504f4e4d4c4b4a494847464544434241 (7.250e+78, 1.584e+40)
+#                                  ║               ╙─ 0x4847464544434241 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf7c2f		ld1 {v15.2d}, [x1], #16
-#   v15: 0x4f4e4d4c4b4a49484746454443424140 (1.07078e+74, 2.31271e+35) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x4f4e4d4c4b4a49484746454443424140 (1.071e+74, 2.313e+35)
+#                                  ║               ╙─ 0x4746454443424140 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x4f4e4d4c4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40281e		ld1 {v30.2s, v31.2s, v0.2s, v1.2s}, [x0]
-#   v30: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x00000000000000001f1e1d1c1b1a1918 (..., 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x1f1e1d1c1b1a1918 (3.348e-20, 1.275e-22)
+#                                          ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x1700000000000000 (4.136e-25, 0.000)
+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc22838		ld1 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
-#   v24: 0x00000000000000005756555453525150 (..., 2.35662e+14, 9.03307e+11) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000005f5e5d5c5b5a5958 (..., 1.60231e+19, 6.14598e+16) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x00000000000000006766656463626160 (..., 1.08801e+24, 4.17598e+21) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000006f6e6d6c6b6a6968 (..., 7.37897e+28, 2.83386e+26) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x6f6e6d6c6b6a6968 (7.379e+28, 2.834e+26)
+#                                          ║       ╙─ 0x6b6a6968 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x6f6e6d6c <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x6766656463626160 (1.088e+24, 4.176e+21)
+#                                          ║       ╙─ 0x63626160 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x67666564 <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0x5f5e5d5c5b5a5958 (1.602e+19, 6.146e+16)
+#                                          ║       ╙─ 0x5b5a5958 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x5f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x5756555453525150 (2.357e+14, 9.033e+11)
+#                                          ║       ╙─ 0x53525150 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x57565554 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf283b		ld1 {v27.2s, v28.2s, v29.2s, v30.2s}, [x1], #32
-#   v27: 0x0000000000000000565554535251504f (..., 5.86395e+13, 2.24749e+11) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00000000000000005e5d5c5b5a595857 (..., 3.98768e+18, 1.52943e+16) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000666564636261605f (..., 2.70818e+23, 1.03937e+21) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000006e6d6c6b6a696867 (..., 1.83698e+28, 7.05432e+25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d30:                 0x6e6d6c6b6a696867 (1.837e+28, 7.054e+25)
+#                                          ║       ╙─ 0x6a696867 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x666564636261605f (2.708e+23, 1.039e+21)
+#                                          ║       ╙─ 0x6261605f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x66656463 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x5e5d5c5b5a595857 (3.988e+18, 1.529e+16)
+#                                          ║       ╙─ 0x5a595857 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x565554535251504f (5.864e+13, 2.247e+11)
+#                                          ║       ╙─ 0x5251504f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x56555453 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40680b		ld1 {v11.2s, v12.2s, v13.2s}, [x0]
-#   v11: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x00000000000000001700000000000000 (..., 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x1700000000000000 (4.136e-25, 0.000)
+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc26828		ld1 {v8.2s, v9.2s, v10.2s}, [x1], x2
-#    v8: 0x0000000000000000767574737271706f (..., 1.24460e+33, 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x00000000000000007e7d7c7b7a797877 (..., 8.42353e+37, 3.23831e+35) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x0000000000000000868584838281807f (..., -5.02237e-35, -1.90286e-37) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x868584838281807f (-5.022e-35, -1.903e-37)
+#                                          ║       ╙─ 0x8281807f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x86858483 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7e7d7c7b7a797877 (8.424e+37, 3.238e+35)
+#                                          ║       ╙─ 0x7a797877 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7e7d7c7b <- 0x~~~~~~~~~~~~~~~~
+#             d8:                 0x767574737271706f (1.245e+33, 4.782e+30)
+#                                          ║       ╙─ 0x7271706f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf683f		ld1 {v31.2s, v0.2s, v1.2s}, [x1], #24
-#   v31: 0x00000000000000007574737271706f6e (..., 3.09878e+32, 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000007d7c7b7a79787776 (..., 2.09754e+37, 8.06320e+34) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x00000000000000008584838281807f7e (..., -1.24615e-35, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8584838281807f7e (-1.246e-35, -4.720e-38)
+#                                          ║       ╙─ 0x81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x85848382 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x7d7c7b7a79787776 (2.098e+37, 8.063e+34)
+#                                          ║       ╙─ 0x79787776 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7d7c7b7a <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x7574737271706f6e (3.099e+32, 1.191e+30)
+#                                          ║       ╙─ 0x71706f6e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x75747372 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40a800		ld1 {v0.2s, v1.2s}, [x0]
-#    v0: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x00000000000000000000000000fffeff (..., 0.00000, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2a82d		ld1 {v13.2s, v14.2s}, [x1], x2
-#   v13: 0x00000000000000008d8c8b8a89888786 (..., -8.66176e-31, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x00000000000000009594939291908f8e (..., -6.00095e-26, -2.28077e-28) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x9594939291908f8e (-6.001e-26, -2.281e-28)
+#                                          ║       ╙─ 0x91908f8e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x95949392 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x8d8c8b8a89888786 (-8.662e-31, -3.287e-33)
+#                                          ║       ╙─ 0x89888786 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8d8c8b8a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdfa823		ld1 {v3.2s, v4.2s}, [x1], #16
-#    v3: 0x00000000000000008c8b8a8988878685 (..., -2.14997e-31, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x000000000000000094939291908f8e8d (..., -1.49010e-26, -5.66232e-29) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x94939291908f8e8d (-1.490e-26, -5.662e-29)
+#                                          ║       ╙─ 0x908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x94939291 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0x8c8b8a8988878685 (-2.150e-31, -8.157e-34)
+#                                          ║       ╙─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40781a		ld1 {v26.2s}, [x0]
-#   v26: 0x0000000000000000ff0000850002ff01 (..., -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc27820		ld1 {v0.2s}, [x1], x2
-#    v0: 0x00000000000000009c9b9a9998979695 (..., -1.02970e-21, -3.91846e-24) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x9c9b9a9998979695 (-1.030e-21, -3.918e-24)
+#                                          ║       ╙─ 0x98979695 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf782b		ld1 {v11.2s}, [x1], #8
-#   v11: 0x00000000000000009b9a999897969594 (..., -2.55764e-22, -9.73128e-25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x9b9a999897969594 (-2.558e-22, -9.731e-25)
+#                                          ║       ╙─ 0x97969594 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9b9a9998 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c402410		ld1 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
-#   v16: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x1f1e1d1c1b1a1918 (0.006950, 0.004990, 0.003468, 0.002487)
+#                                      ║   ║   ║   ╙─ 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            d18:                 0x1700000000000000 (0.001709, 0.000, 0.000, 0.000)
+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc22438		ld1 {v24.4h, v25.4h, v26.4h, v27.4h}, [x1], x2
-#   v24: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x0000000000000000abaaa9a8a7a6a5a4 <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x0000000000000000b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000bbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xbbbab9b8b7b6b5b4 (-0.9658, -0.7148, -0.4819, -0.3564)
+#                                      ║   ║   ║   ╙─ 0xb5b4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb7b6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb9b8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xb3b2b1b0afaeadac (-0.2405, -0.1777, -0.1200, -0.08862)
+#                                      ║   ║   ║   ╙─ 0xadac <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xafae <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb1b0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb3b2 <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xabaaa9a8a7a6a5a4 (-0.05988, -0.04419, -0.02988, -0.02203)
+#                                      ║   ║   ║   ╙─ 0xa5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa7a6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa9a8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xabaa <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0xa3a2a1a09f9e9d9c (-0.01491, -0.01099, -0.007439, -0.005478)
+#                                      ║   ║   ║   ╙─ 0x9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9f9e <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa1a0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa3a2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf2421		ld1 {v1.4h, v2.4h, v3.4h, v4.4h}, [x1], #32
-#    v1: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xbab9b8b7b6b5b4b3 (-0.8403, -0.5894, -0.4192, -0.2937)
+#                                      ║   ║   ║   ╙─ 0xb4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb6b5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb8b7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbab9 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xb2b1b0afaeadacab (-0.2091, -0.1464, -0.1043, -0.07294)
+#                                      ║   ║   ║   ╙─ 0xacab <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xaead <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb0af <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb2b1 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xaaa9a8a7a6a5a4a3 (-0.05203, -0.03635, -0.02596, -0.01811)
+#                                      ║   ║   ║   ╙─ 0xa4a3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa8a7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xaaa9 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xa2a1a09f9e9d9c9b (-0.01295, -0.009026, -0.006458, -0.004498)
+#                                      ║   ║   ║   ╙─ 0x9c9b <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa09f <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa2a1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40641e		ld1 {v30.4h, v31.4h, v0.4h}, [x0]
-#   v30: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x1700000000000000 (0.001709, 0.000, 0.000, 0.000)
+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc26439		ld1 {v25.4h, v26.4h, v27.4h}, [x1], x2
-#   v25: 0x0000000000000000c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x0000000000000000cac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000d2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xd2d1d0cfcecdcccb (-54.53, -38.47, -27.20, -19.17)
+#                                      ║   ║   ║   ╙─ 0xcccb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcecd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xcac9c8c7c6c5c4c3 (-13.57, -9.555, -6.770, -4.762)
+#                                      ║   ║   ║   ╙─ 0xc4c3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xc6c5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc8c7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xcac9 <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xc2c1c0bfbebdbcbb (-3.377, -2.373, -1.685, -1.183)
+#                                      ║   ║   ║   ╙─ 0xbcbb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbebd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc0bf <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc2c1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf6423		ld1 {v3.4h, v4.4h, v5.4h}, [x1], #24
-#    v3: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0000000000000000d1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d5:                 0xd1d0cfcecdcccbca (-46.50, -31.22, -23.19, -15.58)
+#                                      ║   ║   ║   ╙─ 0xcbca <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcdcc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xcfce <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xc9c8c7c6c5c4c3c2 (-11.56, -7.773, -5.766, -3.879)
+#                                      ║   ║   ║   ╙─ 0xc3c2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xc5c4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc7c6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc9c8 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xc1c0bfbebdbcbbba (-2.875, -1.936, -1.434, -0.9658)
+#                                      ║   ║   ║   ╙─ 0xbbba <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbdbc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xbfbe <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc1c0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40a403		ld1 {v3.4h, v4.4h}, [x0]
-#    v3: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2a423		ld1 {v3.4h, v4.4h}, [x1], x2
-#    v3: 0x0000000000000000d9d8d7d6d5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000e1e0dfdedddcdbda <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xe1e0dfdedddcdbda (-752.0, -503.5, -375.0, -251.2)
+#                                      ║   ║   ║   ╙─ 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xd9d8d7d6d5d4d3d2 (-187.0, -125.4, -93.25, -62.56)
+#                                      ║   ║   ║   ╙─ 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdfa437		ld1 {v23.4h, v24.4h}, [x1], #16
-#   v23: 0x0000000000000000d8d7d6d5d4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000e0dfdedddcdbdad9 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d24:                 0xe0dfdedddcdbdad9 (-623.5, -439.2, -310.8, -219.1)
+#                                      ║   ║   ║   ╙─ 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xd8d7d6d5d4d3d2d1 (-154.9, -109.3, -77.19, -54.53)
+#                                      ║   ║   ║   ╙─ 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40741a		ld1 {v26.4h}, [x0]
-#   v26: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc27421		ld1 {v1.4h}, [x1], x2
-#    v1: 0x0000000000000000e8e7e6e5e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe8e7e6e5e4e3e2e1 (-2510., -1765., -1251., -880.5)
+#                                      ║   ║   ║   ╙─ 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf742e		ld1 {v14.4h}, [x1], #8
-#   v14: 0x0000000000000000e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0xe7e6e5e4e3e2e1e0 (-2022., -1508., -1009., -752.0)
+#                                      ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40281a		ld1 {v26.4s, v27.4s, v28.4s, v29.4s}, [x0]
-#   v26: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x3f3e3d3c3b3a39383736353433323130 (0.743122, 0.00284155, 1.08604e-05, 4.14886e-08) <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x3f3e3d3c3b3a39383736353433323130 (0.7431, 0.002842, 1.086e-05, 4.149e-08)
+#                          ║       ║       ║       ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2283c		ld1 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
-#   v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.00179e+34, -3.84962e+31, -1.47890e+29, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.00825e-34, 3.82047e-37, nan, -2.60629e+36) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x17161514131211100f0e0d0c0b0a0908 (4.84942e-25, 1.84362e-27, 7.00365e-30, 2.65846e-32) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x27262524232221201f1e1d1c1b1a1918 (2.30573e-15, 8.78905e-18, 3.34819e-20, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v31: 0x27262524232221201f1e1d1c1b1a1918 (2.306e-15, 8.789e-18, 3.348e-20, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x17161514131211100f0e0d0c0b0a0908 (4.849e-25, 1.844e-27, 7.004e-30, 2.658e-32)
+#                          ║       ║       ║       ╙─ 0x0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x17161514 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.008e-34, 3.820e-37, nan, -2.606e+36)
+#                          ║       ║       ║       ╙─ 0xfbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.002e+34, -3.850e+31, -1.479e+29, -5.680e+26)
+#                          ║       ║       ║       ╙─ 0xebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xefeeedec <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf7f6f5f4 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf2824		ld1 {v4.4s, v5.4s, v6.4s, v7.4s}, [x1], #64
-#    v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.49430e+33, -9.58428e+30, -3.68172e+28, -1.41390e+26) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.50175e-35, 9.47771e-38, -1.68804e+38, -6.48966e+35) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x161514131211100f0e0d0c0b0a090807 (1.20425e-25, 4.57737e-28, 1.73854e-30, 6.59782e-33) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x262524232221201f1e1d1c1b1a191817 (5.72948e-16, 2.18366e-18, 8.31732e-21, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x262524232221201f1e1d1c1b1a191817 (5.729e-16, 2.184e-18, 8.317e-21, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2221201f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x26252423 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x161514131211100f0e0d0c0b0a090807 (1.204e-25, 4.577e-28, 1.739e-30, 6.598e-33)
+#                          ║       ║       ║       ╙─ 0x0a090807 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x16151413 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.502e-35, 9.478e-38, -1.688e+38, -6.490e+35)
+#                          ║       ║       ║       ╙─ 0xfaf9f8f7 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x020100ff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x06050403 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.494e+33, -9.584e+30, -3.682e+28, -1.414e+26)
+#                          ║       ║       ║       ╙─ 0xeae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf6f5f4f3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c406802		ld1 {v2.4s, v3.4s, v4.4s}, [x0]
-#    v2: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x2f2e2d2c2b2a29282726252423222120 (1.58413e-10, 6.04532e-13, 2.30573e-15, 8.78905e-18) <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc26836		ld1 {v22.4s, v23.4s, v24.4s}, [x1], x2
-#   v22: 0x363534333231302f2e2d2c2b2a292827 (2.70015e-06, 1.03137e-08, 3.93749e-11, 1.50241e-13) <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x464544434241403f3e3d3c3b3a393837 (12625.1, 48.3127, 0.184800, 0.000706557) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x565554535251504f4e4d4c4b4a494847 (5.86395e+13, 2.24749e+11, 8.61082e+08, 3.29781e+06) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x565554535251504f4e4d4c4b4a494847 (5.864e+13, 2.247e+11, 8.611e+08, 3.298e+06)
+#                          ║       ║       ║       ╙─ 0x4a494847 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x4e4d4c4b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x5251504f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x56555453 <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0x464544434241403f3e3d3c3b3a393837 (1.263e+04, 48.31, 0.1848, 0.0007066)
+#                          ║       ║       ║       ╙─ 0x3a393837 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x3e3d3c3b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x4241403f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x46454443 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x363534333231302f2e2d2c2b2a292827 (2.700e-06, 1.031e-08, 3.937e-11, 1.502e-13)
+#                          ║       ║       ║       ╙─ 0x2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3231302f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x36353433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf682f		ld1 {v15.4s, v16.4s, v17.4s}, [x1], #48
-#   v15: 0x3534333231302f2e2d2c2b2a29282726 (6.71297e-07, 2.56382e-09, 9.78665e-12, 3.73374e-14) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x4544434241403f3e3d3c3b3a39383736 (3140.20, 12.0154, 0.0459549, 0.000175682) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x5554535251504f4e4d4c4b4a49484746 (1.45909e+13, 5.59177e+10, 2.14218e+08, 820340.) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v17: 0x5554535251504f4e4d4c4b4a49484746 (1.459e+13, 5.592e+10, 2.142e+08, 8.203e+05)
+#                          ║       ║       ║       ╙─ 0x49484746 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x51504f4e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x55545352 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x4544434241403f3e3d3c3b3a39383736 (3140., 12.02, 0.04595, 0.0001757)
+#                          ║       ║       ║       ╙─ 0x39383736 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x41403f3e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x45444342 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x3534333231302f2e2d2c2b2a29282726 (6.713e-07, 2.564e-09, 9.787e-12, 3.734e-14)
+#                          ║       ║       ║       ╙─ 0x29282726 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x31302f2e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x35343332 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40a814		ld1 {v20.4s, v21.4s}, [x0]
-#   v20: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x1f1e1d1c1b1a19181700000000000000 (3.34819e-20, 1.27467e-22, 4.13590e-25, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2a83e		ld1 {v30.4s, v31.4s}, [x1], x2
-#   v30: 0x6564636261605f5e5d5c5b5a59585756 (6.74083e+22, 2.58684e+20, 9.92399e+17, 3.80591e+15) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x7574737271706f6e6d6c6b6a69686766 (3.09878e+32, 1.19058e+30, 4.57302e+27, 1.75599e+25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v31: 0x7574737271706f6e6d6c6b6a69686766 (3.099e+32, 1.191e+30, 4.573e+27, 1.756e+25)
+#                          ║       ║       ║       ╙─ 0x69686766 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x6d6c6b6a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x71706f6e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x75747372 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x6564636261605f5e5d5c5b5a59585756 (6.741e+22, 2.587e+20, 9.924e+17, 3.806e+15)
+#                          ║       ║       ║       ╙─ 0x59585756 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5d5c5b5a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x61605f5e <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x65646362 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdfa82b		ld1 {v11.4s, v12.4s}, [x1], #32
-#   v11: 0x64636261605f5e5d5c5b5a5958575655 (1.67780e+22, 6.43816e+19, 2.46969e+17, 9.47063e+14) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x74737271706f6e6d6c6b6a6968676665 (7.71514e+31, 2.96402e+29, 1.13840e+27, 4.37102e+24) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x74737271706f6e6d6c6b6a6968676665 (7.715e+31, 2.964e+29, 1.138e+27, 4.371e+24)
+#                          ║       ║       ║       ╙─ 0x68676665 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x6c6b6a69 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x706f6e6d <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x74737271 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0x64636261605f5e5d5c5b5a5958575655 (1.678e+22, 6.438e+19, 2.470e+17, 9.471e+14)
+#                          ║       ║       ║       ╙─ 0x58575655 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5c5b5a59 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x605f5e5d <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x64636261 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40780f		ld1 {v15.4s}, [x0]
-#   v15: 0x0000000000fffeffff0000850002ff01 (0.00000, 2.35095e-38, -1.70144e+38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2782c		ld1 {v12.4s}, [x1], x2
-#   v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.09178e-36, -1.17085e-38, 5.22300e+36, 2.00766e+34) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.092e-36, -1.171e-38, 5.223e+36, 2.008e+34)
+#                          ║       ║       ║       ╙─ 0x78777675 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x84838281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf7820		ld1 {v0.4s}, [x1], #16
-#    v0: 0x838281807f7e7d7c7b7a797877767574 (-7.67045e-37, 3.38275e+38, 1.30054e+36, 4.99878e+33) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v0: 0x838281807f7e7d7c7b7a797877767574 (-7.670e-37, 3.383e+38, 1.301e+36, 4.999e+33)
+#                          ║       ║       ║       ╙─ 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f7e7d7c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x83828180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c402011		ld1 {v17.8b, v18.8b, v19.8b, v20.8b}, [x0]
-#   v17: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000001f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x1f1e1d1c1b1a1918
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x1700000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#            d18:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc22025		ld1 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], x2
-#    v5: 0x00000000000000008b8a898887868584 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x0000000000000000939291908f8e8d8c <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000009b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000a3a2a1a09f9e9d9c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xa3a2a1a09f9e9d9c
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x9c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x9d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x9e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x9f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x9b9a999897969594
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x94 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x95 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x96 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x97 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x98 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x99 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x9a <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x9b <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x939291908f8e8d8c
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x8d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x8e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x8f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x90 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x91 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x92 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x93 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x8b8a898887868584
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x84 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x86 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x87 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x88 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x89 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x8a <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf2029		ld1 {v9.8b, v10.8b, v11.8b, v12.8b}, [x1], #32
-#    v9: 0x00000000000000008a89888786858483 <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000009291908f8e8d8c8b <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000009a99989796959493 <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000000000a2a1a09f9e9d9c9b <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xa2a1a09f9e9d9c9b
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x9b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x9c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x9d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x9e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x9f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x9a99989796959493
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x93 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x94 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x95 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x96 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x97 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x98 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x99 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x9a <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x9291908f8e8d8c8b
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x8c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x8d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x8e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x8f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x90 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x91 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x92 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x8a89888786858483
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x83 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x84 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x86 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x87 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x88 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x89 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x8a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c406004		ld1 {v4.8b, v5.8b, v6.8b}, [x0]
-#    v4: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000001700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x1700000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc26022		ld1 {v2.8b, v3.8b, v4.8b}, [x1], x2
-#    v2: 0x0000000000000000aaa9a8a7a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xbab9b8b7b6b5b4b3
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xb4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xb5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xb6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xb7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xba <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xb2b1b0afaeadacab
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xab <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xac <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xad <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xae <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xaf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb2 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xaaa9a8a7a6a5a4a3
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xa4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xa5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xa6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xaa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf602c		ld1 {v12.8b, v13.8b, v14.8b}, [x1], #24
-#   v12: 0x0000000000000000a9a8a7a6a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0000000000000000b1b0afaeadacabaa <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x0000000000000000b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0xb9b8b7b6b5b4b3b2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xb3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xb4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xb5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xb6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0xb1b0afaeadacabaa
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xaa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xab <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xac <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xad <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xae <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xaf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb1 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xa9a8a7a6a5a4a3a2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xa4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xa5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40a00a		ld1 {v10.8b, v11.8b}, [x0]
-#   v10: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000000000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2a02b		ld1 {v11.8b, v12.8b}, [x1], x2
-#   v11: 0x0000000000000000c1c0bfbebdbcbbba <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000000000c9c8c7c6c5c4c3c2 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xc9c8c7c6c5c4c3c2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xc1c0bfbebdbcbbba
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdfa03b		ld1 {v27.8b, v28.8b}, [x1], #16
-#   v27: 0x0000000000000000c0bfbebdbcbbbab9 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x0000000000000000c8c7c6c5c4c3c2c1 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xc8c7c6c5c4c3c2c1
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xc0bfbebdbcbbbab9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40701f		ld1 {v31.8b}, [x0]
-#   v31: 0x0000000000000000ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2702a		ld1 {v10.8b}, [x1], x2
-#   v10: 0x0000000000000000d0cfcecdcccbcac9 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xd0cfcecdcccbcac9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf703c		ld1 {v28.8b}, [x1], #8
-#   v28: 0x0000000000000000cfcecdcccbcac9c8 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xcfcecdcccbcac9c8
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c402405		ld1 {v5.8h, v6.8h, v7.8h, v8.8h}, [x0]
-#    v5: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x3f3e3d3c3b3a39383736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0x3f3e3d3c3b3a39383736353433323130 (1.811, 1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc22422		ld1 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
-#    v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0f0e0d0c0b0a09080706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0f0e0d0c0b0a09080706050403020100 (0.0004306, 0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 (nan, nan, -6.534e+04, -4.890e+04, -3.261e+04, -2.438e+04, -1.627e+04, -1.216e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf1f0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf3f2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf5f4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf7f6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfbfa <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfdfc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 (-8120., -6064., -4052., -3024., -2022., -1508., -1009., -752.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe9e8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xebea <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xedec <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xefee <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 (-503.5, -375.0, -251.2, -187.0, -125.4, -93.25, -62.56, -46.50)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf242a		ld1 {v10.8h, v11.8h, v12.8h, v13.8h}, [x1], #64
-#   v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0e0d0c0b0a09080706050403020100ff <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b0a09080706050403020100ff (0.0003693, 0.0002468, 0.0001842, 0.0001229, 9.185e-05, 6.121e-05, 3.058e-05, 1.520e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0201 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0605 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0807 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0a09 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0c0b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0e0d <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef (nan, nan, -5.712e+04, -4.067e+04, -2.850e+04, -2.027e+04, -1.422e+04, -1.010e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf0ef <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf2f1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf4f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf6f5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf8f7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfcfb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfefd <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df (-7092., -5036., -3538., -2510., -1765., -1251., -880.5, -623.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xeae9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xeceb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xeeed <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf (-439.2, -310.8, -219.1, -154.9, -109.3, -77.19, -54.53, -38.47)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40641a		ld1 {v26.8h, v27.8h, v28.8h}, [x0]
-#   v26: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x2f2e2d2c2b2a29282726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc26423		ld1 {v3.8h, v4.8h, v5.8h}, [x1], x2
-#    v3: 0x1e1d1c1b1a191817161514131211100f <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x2e2d2c2b2a292827262524232221201f <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x3e3d3c3b3a393837363534333231302f <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3e3d3c3b3a393837363534333231302f (1.560, 1.058, 0.7778, 0.5269, 0.3879, 0.2625, 0.1935, 0.1307)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x302f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3433 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3635 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3837 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3c3b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2e2d2c2b2a292827262524232221201f (0.09650, 0.06512, 0.04813, 0.03244, 0.02400, 0.01616, 0.01197, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2e2d <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1e1d1c1b1a191817161514131211100f (0.005970, 0.004009, 0.002977, 0.001997, 0.001485, 0.0009947, 0.0007405, 0.0004954)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x100f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1211 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1413 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1615 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1e1d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf6431		ld1 {v17.8h, v18.8h, v19.8h}, [x1], #48
-#   v17: 0x1d1c1b1a191817161514131211100f0e <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x2d2c2b2a292827262524232221201f1e <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x3d3c3b3a393837363534333231302f2e <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a393837363534333231302f2e (1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40a404		ld1 {v4.8h, v5.8h}, [x0]
-#    v4: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x1f1e1d1c1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2a435		ld1 {v21.8h, v22.8h}, [x1], x2
-#   v21: 0x4d4c4b4a494847464544434241403f3e <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x5d5c5b5a595857565554535251504f4e <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x5d5c5b5a595857565554535251504f4e (343.0, 235.2, 171.0, 117.4, 85.25, 58.56, 42.50, 29.22)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4f4e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5150 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5554 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5958 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5b5a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdfa424		ld1 {v4.8h, v5.8h}, [x1], #32
-#    v4: 0x4c4b4a494847464544434241403f3e3d <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x5c5b5a595857565554535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857565554535251504f4e4d (278.8, 203.1, 138.9, 101.3, 69.19, 50.53, 34.47, 25.20)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4e4d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x504f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5251 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5453 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5857 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5a59 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5c5b <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x4c4b4a494847464544434241403f3e3d (17.17, 12.57, 8.555, 6.270, 4.262, 3.127, 2.123, 1.560)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x403f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4443 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4645 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4c4b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c407409		ld1 {v9.8h}, [x0]
-#    v9: 0x0000000000fffeffff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2743b		ld1 {v27.8h}, [x1], x2
-#   v27: 0x6c6b6a696867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a696867666564636261605f5e5d (4524., 3282., 2254., 1637., 1123., 816.5, 559.5, 407.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5e5d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6463 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6665 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6a69 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6c6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf743a		ld1 {v26.8h}, [x1], #16
-#   v26: 0x6b6a696867666564636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x6b6a696867666564636261605f5e5d5c (3796., 2768., 1894., 1380., 945.0, 688.0, 471.5, 343.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6766 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6b6a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d400413		ld1 {v19.b}[1], [x0]
-#   v19: 0x3d3c3b3a39383736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a39383736353433323130012e
+#                                                ╙─── 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc20c2c		ld1 {v12.b}[3], [x1], x2
-#   v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef
+#                                            ╙─────── 0x6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddf103b		ld1 {v27.b}[12], [x1], #1
-#   v27: 0x6c6b6a6b6867666564636261605f5e5d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a6b6867666564636261605f5e5d
+#                          ╙───────────────────────── 0x6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40840a		ld1 {v10.d}[1], [x0]
-#   v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.487e+303, ...)
+#                                  ╙───────────────── 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2843a		ld1 {v26.d}[1], [x1], x2
-#   v26: 0x737271706f6e6d6c636261605f5e5d5c (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x737271706f6e6d6c636261605f5e5d5c (1.290e+248, ...)
+#                                  ╙───────────────── 0x737271706f6e6d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddf8427		ld1 {v7.d}[1], [x1], #8
-#    v7: 0x7271706f6e6d6c6b2726252423222120 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x7271706f6e6d6c6b2726252423222120 (1.861e+243, ...)
+#                                  ╙───────────────── 0x7271706f6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d404813		ld1 {v19.h}[5], [x0]
-#   v19: 0x3d3c3b3aff013736353433323130012e <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3aff013736353433323130012e (..., nan, ...)
+#                              ╙───────────────────── 0xff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2482a		ld1 {v10.h}[1], [x1], x2
-#   v10: 0xff0000850002ff01d6d5d4d37473d0cf <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d37473d0cf (..., 1.822e+04, ...)
+#                                              ╙───── 0x7473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddf4025		ld1 {v5.h}[4], [x1], #2
-#    v5: 0x5c5b5a595857737254535251504f4e4d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857737254535251504f4e4d (..., 1.525e+04, ...)
+#                                  ╙───────────────── 0x7372 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d408015		ld1 {v21.s}[2], [x0]
-#   v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.751e-40, ...)
+#                                  ╙───────────────── 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2802d		ld1 {v13.s}[2], [x1], x2
-#   v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.99878e+33, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.999e+33, ...)
+#                                  ╙───────────────── 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddf8021		ld1 {v1.s}[2], [x1], #4
-#    v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.24460e+33, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.245e+33, ...)
+#                                  ╙───────────────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40c002		ld1r {v2.16b}, [x0]
-#    v2: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x01010101010101010101010101010101
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2c022		ld1r {v2.16b}, [x1], x2
-#    v2: 0x77777777777777777777777777777777 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x77777777777777777777777777777777
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x77 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfc036		ld1r {v22.16b}, [x1], #1
-#   v22: 0x76767676767676767676767676767676 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x76767676767676767676767676767676
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x76 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40cc19		ld1r {v25.1d}, [x0]
-#   v25: 0x0000000000000000ff0000850002ff01 (d25: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2cc29		ld1r {v9.1d}, [x1], x2
-#    v9: 0x00000000000000007e7d7c7b7a797877 (d9: 1.97467e+301) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7e7d7c7b7a797877 (1.975e+301)
+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfcc37		ld1r {v23.1d}, [x1], #8
-#   v23: 0x00000000000000007d7c7b7a79787776 (d23: 2.91053e+296) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x7d7c7b7a79787776 (2.911e+296)
+#                                                  ╙─ 0x7d7c7b7a79787776 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40cc13		ld1r {v19.2d}, [x0]
-#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#                                  ╙───────────────╨─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2cc35		ld1r {v21.2d}, [x1], x2
-#   v21: 0x8584838281807f7e8584838281807f7e (-4.41447e-282, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8584838281807f7e8584838281807f7e (-4.414e-282, -4.414e-282)
+#                                  ╙───────────────╨─ 0x8584838281807f7e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfcc3e		ld1r {v30.2d}, [x1], #8
-#   v30: 0x84838281807f7e7d84838281807f7e7d (-6.40629e-287, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84838281807f7e7d84838281807f7e7d (-6.406e-287, -6.406e-287)
+#                                  ╙───────────────╨─ 0x84838281807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40c818		ld1r {v24.2s}, [x0]
-#   v24: 0x00000000000000000002ff010002ff01 (s24: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#                                          ╙───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2c83a		ld1r {v26.2s}, [x1], x2
-#   v26: 0x00000000000000008887868588878685 (s26: -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x8887868588878685 (-8.157e-34, -8.157e-34)
+#                                          ╙───────╨─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfc83c		ld1r {v28.2s}, [x1], #4
-#   v28: 0x00000000000000008786858487868584 (s28: -2.02406e-34) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x8786858487868584 (-2.024e-34, -2.024e-34)
+#                                          ╙───────╨─ 0x87868584 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40c413		ld1r {v19.4h}, [x0]
-#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2c421		ld1r {v1.4h}, [x1], x2
-#    v1: 0x00000000000000008988898889888988 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8988898889888988 (-0.0001688, -0.0001688, -0.0001688, -0.0001688)
+#                                      ╙───╨───╨───╨─ 0x8988 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfc435		ld1r {v21.4h}, [x1], #2
-#   v21: 0x00000000000000008887888788878887 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x8887888788878887 (-0.0001382, -0.0001382, -0.0001382, -0.0001382)
+#                                      ╙───╨───╨───╨─ 0x8887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40c80f		ld1r {v15.4s}, [x0]
-#   v15: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#                          ╙───────╨───────╨───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2c835		ld1r {v21.4s}, [x1], x2
-#   v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (..., -2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (-2.150e-31, -2.150e-31, -2.150e-31, -2.150e-31)
+#                          ╙───────╨───────╨───────╨─ 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfc837		ld1r {v23.4s}, [x1], #4
-#   v23: 0x8b8a89888b8a89888b8a89888b8a8988 (..., -5.33626e-32, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0x8b8a89888b8a89888b8a89888b8a8988 (-5.336e-32, -5.336e-32, -5.336e-32, -5.336e-32)
+#                          ╙───────╨───────╨───────╨─ 0x8b8a8988 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40c01a		ld1r {v26.8b}, [x0]
-#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2c02e		ld1r {v14.8b}, [x1], x2
-#   v14: 0x00000000000000008c8c8c8c8c8c8c8c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x8c8c8c8c8c8c8c8c
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfc033		ld1r {v19.8b}, [x1], #1
-#   v19: 0x00000000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x8b8b8b8b8b8b8b8b
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40c40d		ld1r {v13.8h}, [x0]
-#   v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2c43e		ld1r {v30.8h}, [x1], x2
-#   v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c (-0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8d8c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfc43b		ld1r {v27.8h}, [x1], #2
-#   v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b (-0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8c8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c408015		ld2 {v21.16b, v22.16b}, [x0]
-#   v21: 0x1e1c1a18000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x1f1d1b1917000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1e1c1a18000000000000ffff00850201
+#            v22: 0x1f1d1b1917000000000000feff0000ff
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x17'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1b'1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f'1e <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc28035		ld2 {v21.16b, v22.16b}, [x1], x2
-#   v21: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0xacaaa8a6a4a2a09e9c9a98969492908e <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#            v22: 0xacaaa8a6a4a2a09e9c9a98969492908e
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x92'91 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x98'97 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa4'a3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaa'a9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xac'ab <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf802c		ld2 {v12.16b, v13.16b}, [x1], #32
-#   v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0xaba9a7a5a3a19f9d9b99979593918f8d <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c
+#            v13: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x8f'8e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x95'94 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa1'a0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa7'a6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xa9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xab'aa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c408c0e		ld2 {v14.2d, v15.2d}, [x0]
-#   v14: 0x1700000000000000ff0000850002ff01 (6.68887e-198, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.56775e-159, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x1700000000000000ff0000850002ff01 (6.689e-198, -5.487e+303)
+#            v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.568e-159, 8.289e-317)
+#                                  ║               ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc28c20		ld2 {v0.2d, v1.2d}, [x1], x2
-#    v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.70315e+18, -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.31369e+57, -5.65934e-21) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.703e+18, -1.163e-59)
+#             v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.314e+57, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4'b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcbcac9c8c7c6c5c4'c3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf8c2c		ld2 {v12.2d, v13.2d}, [x1], #32
-#   v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.90391e+13, -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.92941e+52, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.904e+13, -1.680e-64)
+#            v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.929e+52, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3'b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40881b		ld2 {v27.2s, v28.2s}, [x0]
-#   v27: 0x000000000000000000fffeff0002ff01 (..., 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00fffeff0002ff01 (2.351e-38, 2.751e-40)
+#            d28:                 0x00000000ff000085 (0.000, -1.701e+38)
+#                                          ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc28822		ld2 {v2.2s, v3.2s}, [x1], x2
-#    v2: 0x0000000000000000d6d5d4d3cecdcccb (..., -1.17555e+14, -1.72638e+09) <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000dad9d8d7d2d1d0cf (..., -3.06592e+16, -4.50576e+11) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xd6d5d4d3cecdcccb (-1.176e+14, -1.726e+09)
+#             d3:                 0xdad9d8d7d2d1d0cf (-3.066e+16, -4.506e+11)
+#                                          ║       ╙─ 0xd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xdad9d8d7'd6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf882c		ld2 {v12.2s, v13.2s}, [x1], #16
-#   v12: 0x0000000000000000d5d4d3d2cdcccbca (..., -2.92508e+13, -4.29488e+08) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0000000000000000d9d8d7d6d1d0cfce (..., -7.62949e+15, -1.12105e+11) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xd5d4d3d2cdcccbca (-2.925e+13, -4.295e+08)
+#            d13:                 0xd9d8d7d6d1d0cfce (-7.629e+15, -1.121e+11)
+#                                          ║       ╙─ 0xd1d0cfce'cdcccbca <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c408409		ld2 {v9.4h, v10.4h}, [x0]
-#    v9: 0x00000000000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x0000000000000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x0000feff0085ff01 (0.000, nan, 7.927e-06, nan)
+#            d10:                 0x000000ffff000002 (0.000, 1.520e-05, nan, 1.192e-07)
+#                                      ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc28437		ld2 {v23.4h, v24.4h}, [x1], x2
-#   v23: 0x0000000000000000e7e6e3e2dfdedbda <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000e9e8e5e4e1e0dddc <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe7e6e3e2dfdedbda (-2022., -1009., -503.5, -251.2)
+#            d24:                 0xe9e8e5e4e1e0dddc (-3024., -1508., -752.0, -375.0)
+#                                      ║   ║   ║   ╙─ 0xdddc'dbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe1e0'dfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe9e8'e7e6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf8421		ld2 {v1.4h, v2.4h}, [x1], #16
-#    v1: 0x0000000000000000e6e5e2e1dedddad9 <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x0000000000000000e8e7e4e3e0dfdcdb <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe6e5e2e1dedddad9 (-1765., -880.5, -439.2, -219.1)
+#             d2:                 0xe8e7e4e3e0dfdcdb (-2510., -1251., -623.5, -310.8)
+#                                      ║   ║   ║   ╙─ 0xdcdb'dad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe0df'dedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7'e6e5 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c408814		ld2 {v20.4s, v21.4s}, [x0]
-#   v20: 0x1b1a19180000000000fffeff0002ff01 (1.27467e-22, 0.00000, 2.35095e-38, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x1f1e1d1c1700000000000000ff000085 (3.34819e-20, 4.13590e-25, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x1b1a19180000000000fffeff0002ff01 (1.275e-22, 0.000, 2.351e-38, 2.751e-40)
+#            v21: 0x1f1e1d1c1700000000000000ff000085 (3.348e-20, 4.136e-25, 0.000, -1.701e+38)
+#                          ║       ║       ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2882a		ld2 {v10.4s, v11.4s}, [x1], x2
-#   v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.53999e-36, -1.04669e+37, -1.54621e+32, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.06322e-34, 2.35095e-38, -4.02346e+34, -5.94046e+29) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.540e-36, -1.047e+37, -1.546e+32, -2.282e+27)
+#            v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.063e-34, 2.351e-38, -4.023e+34, -5.940e+29)
+#                          ║       ║       ║       ╙─ 0xf0efeeed'ecebeae9 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf8f7f6f5'f4f3f2f1 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffefd'fcfbfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x08070605'04030201 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf8838		ld2 {v24.4s, v25.4s}, [x1], #32
-#   v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.82047e-37, -2.60629e+36, -3.84962e+31, -5.67986e+26) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.00825e-34, nan, -1.00179e+34, -1.47890e+29) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.820e-37, -2.606e+36, -3.850e+31, -5.680e+26)
+#            v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.008e-34, nan, -1.002e+34, -1.479e+29)
+#                          ║       ║       ║       ╙─ 0xefeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf7f6f5f4'f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xfffefdfc'fbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504'03020100 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c408011		ld2 {v17.8b, v18.8b}, [x0]
-#   v17: 0x00000000000000000000ffff00850201 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x0000000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000ffff00850201
+#            d18:                 0x000000feff0000ff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2802d		ld2 {v13.8b, v14.8b}, [x1], x2
-#   v13: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x0000000000000000171513110f0d0b09 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x161412100e0c0a08
+#            d14:                 0x171513110f0d0b09
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x09'08 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x11'10 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'16 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf8027		ld2 {v7.8b, v8.8b}, [x1], #16
-#    v7: 0x00000000000000001513110f0d0b0907 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000161412100e0c0a08 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1513110f0d0b0907
+#             d8:                 0x161412100e0c0a08
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0a'09 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0e'0d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x16'15 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c40841e		ld2 {v30.8h, v31.8h}, [x0]
-#   v30: 0x1d1c1918000000000000feff0085ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x1f1e1b1a17000000000000ffff000002 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c1918000000000000feff0085ff01 (0.004990, 0.002487, 0.000, 0.000, 0.000, nan, 7.927e-06, nan)
+#            v31: 0x1f1e1b1a17000000000000ffff000002 (0.006950, 0.003468, 0.001709, 0.000, 0.000, 1.520e-05, nan, 1.192e-07)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1700'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc28424		ld2 {v4.8h, v5.8h}, [x1], x2
-#    v4: 0x3433302f2c2b28272423201f1c1b1817 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x363532312e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v4: 0x3433302f2c2b28272423201f1c1b1817 (0.2625, 0.1307, 0.06512, 0.03244, 0.01616, 0.008049, 0.004009, 0.001997)
+#             v5: 0x363532312e2d2a29262522211e1d1a19 (0.3879, 0.1935, 0.09650, 0.04813, 0.02400, 0.01197, 0.005970, 0.002977)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1a19'1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1e1d'1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2221'201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625'2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2a29'2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2e2d'2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3231'302f <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3635'3433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf842d		ld2 {v13.8h, v14.8h}, [x1], #32
-#   v13: 0x33322f2e2b2a272623221f1e1b1a1716 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x353431302d2c2928252421201d1c1918 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x33322f2e2b2a272623221f1e1b1a1716 (0.2249, 0.1122, 0.05597, 0.02792, 0.01393, 0.006950, 0.003468, 0.001730)
+#            v14: 0x353431302d2c2928252421201d1c1918 (0.3252, 0.1621, 0.08081, 0.04028, 0.02008, 0.01001, 0.004990, 0.002487)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928'2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d601005		ld2 {v5.b, v6.b}[12], [x0]
-#    v5: 0x363532012e2d2a29262522211e1d1a19 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x1f1e1dff1b1a19181700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x363532012e2d2a29262522211e1d1a19
+#             v6: 0x1f1e1dff1b1a19181700000000000000
+#                          ╙───────────────────────── 0xff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de21c30		ld2 {v16.b, v17.b}[7], [x1], x2
-#   v16: 0x4544434241403f3e363c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x4544434241403f3e363c3b3a39383736
+#            v17: 0x00000000000000003700ffff00850201
+#                                    ╙─────────────── 0x37'36 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff083d		ld2 {v29.b, v30.b}[2], [x1], #2
-#   v29: 0x0706050403020100fffefdfcfb35f9f8 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x1d1c1918000000000000feff0036ff01 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfb35f9f8
+#            v30: 0x1d1c1918000000000000feff0036ff01
+#                                              ╙───── 0x36'35 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60840b		ld2 {v11.d, v12.d}[1], [x0]
-#   v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.487e+303, ...)
+#            v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.289e-317, ...)
+#                                  ╙───────────────── 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2843a		ld2 {v26.d, v27.d}[0], [x1], x2
-#   v26: 0x00000000000000003e3d3c3b3a393837 (d26: 6.80687e-09) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000464544434241403f (d27: 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x00000000000000003e3d3c3b3a393837 (..., 6.807e-09)
+#            v27: 0x0000000000000000464544434241403f (..., 3.370e+30)
+#                                                  ╙─ 0x464544434241403f'3e3d3c3b3a393837 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff8439		ld2 {v25.d, v26.d}[0], [x1], #16
-#   v25: 0x07060504fffefdfc3d3c3b3a39383736 (d25: 1.00298e-13) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x00000000000000004544434241403f3e (d26: 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x07060504fffefdfc3d3c3b3a39383736 (..., 1.003e-13)
+#            v26: 0x00000000000000004544434241403f3e (..., 4.899e+25)
+#                                                  ╙─ 0x4544434241403f3e'3d3c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d605812		ld2 {v18.h, v19.h}[7], [x0]
-#   v18: 0xff01000000000000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00020000000000008b8b8b8b8b8b8b8b <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0xff01000000000000000000feff0000ff (nan, ...)
+#            v19: 0x00020000000000008b8b8b8b8b8b8b8b (1.192e-07, ...)
+#                      ╙───────────────────────────── 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de24831		ld2 {v17.h, v18.h}[5], [x1], x2
-#   v17: 0x00000000474600003700ffff00850201 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0xff01000049480000000000feff0000ff <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v17: 0x00000000474600003700ffff00850201 (..., 7.273, ...)
+#            v18: 0xff01000049480000000000feff0000ff (..., 10.56, ...)
+#                              ╙───────────────────── 0x4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff503e		ld2 {v30.h, v31.h}[2], [x1], #4
-#   v30: 0x1d1c191800000000000046450036ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x1f1e1b1a1700000000004847ff000002 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c191800000000000046450036ff01 (..., 6.270, ...)
+#            v31: 0x1f1e1b1a1700000000004847ff000002 (..., 8.555, ...)
+#                                          ╙───────── 0x4847'4645 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60901d		ld2 {v29.s, v30.s}[3], [x0]
-#   v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xff00008500000000000046450036ff01 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.751e-40, ...)
+#            v30: 0xff00008500000000000046450036ff01 (-1.701e+38, ...)
+#                          ╙───────────────────────── 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2803c		ld2 {v28.s, v29.s}[0], [x1], x2
-#   v28: 0x0000000000000000000000004c4b4a49 (s28: 5.32913e+07) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0002ff0103020100fffefdfc504f4e4d (s29: 1.39121e+10) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000000000000000004c4b4a49 (..., 5.329e+07)
+#            v29: 0x0002ff0103020100fffefdfc504f4e4d (..., 1.391e+10)
+#                                                  ╙─ 0x504f4e4d'4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff9026		ld2 {v6.s, v7.s}[1], [x1], #8
-#    v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.32570e+07, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.46117e+09, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.326e+07, ...)
+#             v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.461e+09, ...)
+#                                          ╙───────── 0x4f4e4d4c'4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60c01a		ld2r {v26.16b, v27.16b}, [x0]
-#   v26: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x01010101010101010101010101010101
+#            v27: 0xffffffffffffffffffffffffffffffff
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2c035		ld2r {v21.16b, v22.16b}, [x1], x2
-#   v21: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x51515151515151515151515151515151 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x50505050505050505050505050505050
+#            v22: 0x51515151515151515151515151515151
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x51'50 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffc025		ld2r {v5.16b, v6.16b}, [x1], #2
-#    v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x50505050505050505050505050505050 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f
+#             v6: 0x50505050505050505050505050505050
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x50'4f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60cc1a		ld2r {v26.1d, v27.1d}, [x0]
-#   v26: 0x0000000000000000ff0000850002ff01 (d26: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000000000000000fffeff (d27: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-5.487e+303)
+#            d27:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2cc2e		ld2r {v14.1d, v15.1d}, [x1], x2
-#   v14: 0x00000000000000005857565554535251 (d14: 3.67814e+117) <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x0000000000000000605f5e5d5c5b5a59 (d15: 1.68234e+156) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x5857565554535251 (3.678e+117)
+#            d15:                 0x605f5e5d5c5b5a59 (1.682e+156)
+#                                                  ╙─ 0x605f5e5d5c5b5a59'5857565554535251 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffcc37		ld2r {v23.1d, v24.1d}, [x1], #16
-#   v23: 0x00000000000000005756555453525150 (d23: 5.37096e+112) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00000000000000005f5e5d5c5b5a5958 (d24: 2.48489e+151) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x5756555453525150 (5.371e+112)
+#            d24:                 0x5f5e5d5c5b5a5958 (2.485e+151)
+#                                                  ╙─ 0x5f5e5d5c5b5a5958'5756555453525150 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60cc0b		ld2r {v11.2d, v12.2d}, [x0]
-#   v11: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v12: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#                                  ╙───────────────╨─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2cc3d		ld2r {v29.2d, v30.2d}, [x1], x2
-#   v29: 0x67666564636261606766656463626160 (1.24732e+190, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.76650e+228, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x67666564636261606766656463626160 (1.247e+190, 1.247e+190)
+#            v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.766e+228, 5.766e+228)
+#                                  ╙───────────────╨─ 0x6f6e6d6c6b6a6968'6766656463626160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffcc2f		ld2r {v15.2d, v16.2d}, [x1], #16
-#   v15: 0x666564636261605f666564636261605f (1.81795e+185, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.50866e+223, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x666564636261605f666564636261605f (1.818e+185, 1.818e+185)
+#            v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.509e+223, 8.509e+223)
+#                                  ╙───────────────╨─ 0x6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60c81a		ld2r {v26.2s, v27.2s}, [x0]
-#   v26: 0x00000000000000000002ff010002ff01 (s26: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000ff000085ff000085 (s27: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d27:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#                                          ╙───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2c836		ld2r {v22.2s, v23.2s}, [x1], x2
-#   v22: 0x00000000000000007271706f7271706f (s22: 4.78220e+30) <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000007675747376757473 (s23: 1.24460e+33) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x7271706f7271706f (4.782e+30, 4.782e+30)
+#            d23:                 0x7675747376757473 (1.245e+33, 1.245e+33)
+#                                          ╙───────╨─ 0x76757473'7271706f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffc822		ld2r {v2.2s, v3.2s}, [x1], #8
-#    v2: 0x000000000000000071706f6e71706f6e (s2: 1.19058e+30) <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x00000000000000007574737275747372 (s3: 3.09878e+32) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x71706f6e71706f6e (1.191e+30, 1.191e+30)
+#             d3:                 0x7574737275747372 (3.099e+32, 3.099e+32)
+#                                          ╙───────╨─ 0x75747372'71706f6e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60c402		ld2r {v2.4h, v3.4h}, [x0]
-#    v2: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#             d3:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                                      ╙───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2c429		ld2r {v9.4h, v10.4h}, [x1], x2
-#    v9: 0x00000000000000007776777677767776 <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000007978797879787978 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7776777677767776 (3.056e+04, 3.056e+04, 3.056e+04, 3.056e+04)
+#            d10:                 0x7978797879787978 (4.480e+04, 4.480e+04, 4.480e+04, 4.480e+04)
+#                                      ╙───╨───╨───╨─ 0x7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffc426		ld2r {v6.4h, v7.4h}, [x1], #4
-#    v6: 0x00000000000000007675767576757675 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000007877787778777877 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x7675767576757675 (2.645e+04, 2.645e+04, 2.645e+04, 2.645e+04)
+#             d7:                 0x7877787778777877 (3.658e+04, 3.658e+04, 3.658e+04, 3.658e+04)
+#                                      ╙───╨───╨───╨─ 0x7877'7675 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60c807		ld2r {v7.4s, v8.4s}, [x0]
-#    v7: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#             v8: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#                          ╙───────╨───────╨───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2c833		ld2r {v19.4s, v20.4s}, [x1], x2
-#   v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (..., 5.22300e+36, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (..., -1.17085e-38, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (5.223e+36, 5.223e+36, 5.223e+36, 5.223e+36)
+#            v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (-1.171e-38, -1.171e-38, -1.171e-38, -1.171e-38)
+#                          ╙───────╨───────╨───────╨─ 0x807f7e7d'7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffc835		ld2r {v21.4s, v22.4s}, [x1], #8
-#   v21: 0x7b7a79787b7a79787b7a79787b7a7978 (..., 1.30054e+36, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (..., 3.38275e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x7b7a79787b7a79787b7a79787b7a7978 (1.301e+36, 1.301e+36, 1.301e+36, 1.301e+36)
+#            v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (3.383e+38, 3.383e+38, 3.383e+38, 3.383e+38)
+#                          ╙───────╨───────╨───────╨─ 0x7f7e7d7c'7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60c01a		ld2r {v26.8b, v27.8b}, [x0]
-#   v26: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#            d27:                 0xffffffffffffffff
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2c034		ld2r {v20.8b, v21.8b}, [x1], x2
-#   v20: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x00000000000000008181818181818181 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x8080808080808080
+#            d21:                 0x8181818181818181
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x81'80 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffc02b		ld2r {v11.8b, v12.8b}, [x1], #2
-#   v11: 0x00000000000000007f7f7f7f7f7f7f7f <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x00000000000000008080808080808080 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x7f7f7f7f7f7f7f7f
+#            d12:                 0x8080808080808080
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x80'7f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60c40c		ld2r {v12.8h, v13.8h}, [x0]
-#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v13: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2c426		ld2r {v6.8h, v7.8h}, [x1], x2
-#    v6: 0x82818281828182818281828182818281 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x84838483848384838483848384838483 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x82818281828182818281828182818281 (-3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05)
+#             v7: 0x84838483848384838483848384838483 (-6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8483'8281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffc439		ld2r {v25.8h, v26.8h}, [x1], #4
-#   v25: 0x81808180818081808180818081808180 <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x83828382838283828382838283828382 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x81808180818081808180818081808180 (-2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05)
+#            v26: 0x83828382838283828382838283828382 (-5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c404014		ld3 {v20.16b, v21.16b, v22.16b}, [x0]
-#   v20: 0x2d2a2724211e1b1800000000fe000001 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x2e2b2825221f1c1900000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x2f2c292623201d1a1700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2d2a2724211e1b1800000000fe000001
+#            v21: 0x2e2b2825221f1c1900000000ffff85ff
+#            v22: 0x2f2c292623201d1a1700000000ff0002
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x20'1f'1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x23'22'21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2c'2b'2a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f'2e'2d <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2403c		ld3 {v28.16b, v29.16b, v30.16b}, [x1], x2
-#   v28: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v29: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#            v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x89'88'87 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8c'8b'8a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8f'8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x95'94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x98'97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa1'a0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa4'a3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa7'a6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xaa'a9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xad'ac'ab <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb3'b2'b1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf4034		ld3 {v20.16b, v21.16b, v22.16b}, [x1], #48
-#   v20: 0xb0adaaa7a4a19e9b9895928f8c898683 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0xb1aeaba8a5a29f9c999693908d8a8784 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0xb2afaca9a6a3a09d9a9794918e8b8885 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0xb0adaaa7a4a19e9b9895928f8c898683
+#            v21: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v22: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x85'84'83 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x88'87'86 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8b'8a'89 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8e'8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x91'90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x94'93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x97'96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9a'99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa3'a2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa6'a5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa9'a8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xac'ab'aa <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb2'b1'b0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c404c15		ld3 {v21.2d, v22.2d, v23.2d}, [x0]
-#   v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.56775e-159, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x27262524232221200000000000fffeff (4.28794e-120, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x2f2e2d2c2b2a29281700000000000000 (1.98829e-81, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.568e-159, -5.487e+303)
+#            v22: 0x27262524232221200000000000fffeff (4.288e-120, 8.289e-317)
+#            v23: 0x2f2e2d2c2b2a29281700000000000000 (1.988e-81, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928'2726252423222120'1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc24c32		ld3 {v18.2d, v19.2d, v20.2d}, [x1], x2
-#   v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.07279e+90, -8.31108e-26) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.47908e+129, -3.90391e+13) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.10851e+168, -1.92941e+52) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.073e+90, -8.311e-26)
+#            v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.479e+129, -3.904e+13)
+#            v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.109e+168, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb'dad9d8d7d6d5d4d3'd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf4c3b		ld3 {v27.2d, v28.2d, v29.2d}, [x1], #48
-#   v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.30639e+86, -1.21867e-30) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.56908e+124, -5.62003e+08) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.03668e+163, -2.82942e+47) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.306e+86, -1.219e-30)
+#            v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.569e+124, -5.620e+08)
+#            v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.037e+163, -2.829e+47)
+#                                  ║               ╙─ 0xc9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe1e0dfdedddcdbda'd9d8d7d6d5d4d3d2'd1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c404807		ld3 {v7.2s, v8.2s, v9.2s}, [x0]
-#    v7: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x000000000000000000000000ff000085 (..., 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x00000000000000001700000000fffeff (..., 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x000000000002ff01 (0.000, 2.751e-40)
+#             d8:                 0x00000000ff000085 (0.000, -1.701e+38)
+#             d9:                 0x1700000000fffeff (4.136e-25, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc24834		ld3 {v20.2s, v21.2s, v22.2s}, [x1], x2
-#   v20: 0x0000000000000000f1f0efeee5e4e3e2 (..., -2.38613e+30, -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x0000000000000000f5f4f3f2e9e8e7e6 (..., -6.21029e+32, -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x0000000000000000f9f8f7f6edecebea (..., -1.61590e+35, -9.16546e+27) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xf1f0efeee5e4e3e2 (-2.386e+30, -1.351e+23)
+#            d21:                 0xf5f4f3f2e9e8e7e6 (-6.210e+32, -3.520e+25)
+#            d22:                 0xf9f8f7f6edecebea (-1.616e+35, -9.165e+27)
+#                                          ║       ╙─ 0xedecebea'e9e8e7e6'e5e4e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf483a		ld3 {v26.2s, v27.2s, v28.2s}, [x1], #24
-#   v26: 0x0000000000000000f0efeeede4e3e2e1 (..., -5.94046e+29, -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000f4f3f2f1e8e7e6e5 (..., -1.54621e+32, -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x0000000000000000f8f7f6f5ecebeae9 (..., -4.02346e+34, -2.28166e+27) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xf0efeeede4e3e2e1 (-5.940e+29, -3.363e+22)
+#            d27:                 0xf4f3f2f1e8e7e6e5 (-1.546e+32, -8.761e+24)
+#            d28:                 0xf8f7f6f5ecebeae9 (-4.023e+34, -2.282e+27)
+#                                          ║       ╙─ 0xecebeae9'e8e7e6e5'e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40441b		ld3 {v27.4h, v28.4h, v29.4h}, [x0]
-#   v27: 0x000000000000000000000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x000000000000000000000000feff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000001700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00000000ff00ff01 (0.000, 0.000, nan, nan)
+#            d28:                 0x00000000feff0002 (0.000, 0.000, nan, 1.192e-07)
+#            d29:                 0x1700000000ff0085 (0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                                      ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2443c		ld3 {v28.4h, v29.4h, v30.4h}, [x1], x2
-#   v28: 0x00000000000000000c0b060500fffaf9 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000000e0d08070201fcfb <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000100f0a090403fefd <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x0c0b060500fffaf9 (0.0002468, 9.185e-05, 1.520e-05, -5.712e+04)
+#            d29:                 0x0e0d08070201fcfb (0.0003693, 0.0001229, 3.058e-05, nan)
+#            d30:                 0x100f0a090403fefd (0.0004954, 0.0001842, 6.121e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0403'0201'00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0a09'0807'0605 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x100f'0e0d'0c0b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf4427		ld3 {v7.4h, v8.4h, v9.4h}, [x1], #24
-#    v7: 0x00000000000000000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000d0c07060100fbfa <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x00000000000000000f0e09080302fdfc <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x0b0a0504fffef9f8 (0.0002148, 7.653e-05, nan, -4.890e+04)
+#             d8:                 0x0d0c07060100fbfa (0.0003080, 0.0001072, 1.526e-05, -6.534e+04)
+#             d9:                 0x0f0e09080302fdfc (0.0004306, 0.0001535, 4.590e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfdfc'fbfa'f9f8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0302'0100'fffe <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0908'0706'0504 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0f0e'0d0c'0b0a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c404802		ld3 {v2.4s, v3.4s, v4.4s}, [x0]
-#    v2: 0x272625241b1a1918000000000002ff01 (2.30573e-15, 1.27467e-22, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.04532e-13, 3.34819e-20, 0.00000, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x2f2e2d2c232221201700000000fffeff (1.58413e-10, 8.78905e-18, 4.13590e-25, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x272625241b1a1918000000000002ff01 (2.306e-15, 1.275e-22, 0.000, 2.751e-40)
+#             v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.045e-13, 3.348e-20, 0.000, -1.701e+38)
+#             v4: 0x2f2e2d2c232221201700000000fffeff (1.584e-10, 8.789e-18, 4.136e-25, 2.351e-38)
+#                          ║       ║       ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120'1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c'2b2a2928'27262524 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc24838		ld3 {v24.4s, v25.4s, v26.4s}, [x1], x2
-#   v24: 0x373635342b2a29281f1e1d1c13121110 (1.08604e-05, 6.04532e-13, 3.34819e-20, 1.84362e-27) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x3b3a39382f2e2d2c2322212017161514 (0.00284155, 1.58413e-10, 8.78905e-18, 4.84942e-25) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x3f3e3d3c33323130272625241b1a1918 (0.743122, 4.14886e-08, 2.30573e-15, 1.27467e-22) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x373635342b2a29281f1e1d1c13121110 (1.086e-05, 6.045e-13, 3.348e-20, 1.844e-27)
+#            v25: 0x3b3a39382f2e2d2c2322212017161514 (0.002842, 1.584e-10, 8.789e-18, 4.849e-25)
+#            v26: 0x3f3e3d3c33323130272625241b1a1918 (0.7431, 4.149e-08, 2.306e-15, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918'17161514'13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x33323130'2f2e2d2c'2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf482b		ld3 {v11.4s, v12.4s, v13.4s}, [x1], #48
-#   v11: 0x363534332a2928271e1d1c1b1211100f (2.70015e-06, 1.50241e-13, 8.31732e-21, 4.57737e-28) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x3a3938372e2d2c2b2221201f16151413 (0.000706557, 3.93749e-11, 2.18366e-18, 1.20425e-25) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x3e3d3c3b3231302f262524231a191817 (0.184800, 1.03137e-08, 5.72948e-16, 3.16591e-23) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0x363534332a2928271e1d1c1b1211100f (2.700e-06, 1.502e-13, 8.317e-21, 4.577e-28)
+#            v12: 0x3a3938372e2d2c2b2221201f16151413 (0.0007066, 3.937e-11, 2.184e-18, 1.204e-25)
+#            v13: 0x3e3d3c3b3231302f262524231a191817 (0.1848, 1.031e-08, 5.729e-16, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817'16151413'1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x26252423'2221201f'1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3231302f'2e2d2c2b'2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3e3d3c3b'3a393837'36353433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40401d		ld3 {v29.8b, v30.8b, v31.8b}, [x0]
-#   v29: 0x000000000000000000000000fe000001 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x000000000000000000000000ffff85ff <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000000000001700000000ff0002 <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x00000000fe000001
+#            d30:                 0x00000000ffff85ff
+#            d31:                 0x1700000000ff0002
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc24021		ld3 {v1.8b, v2.8b, v3.8b}, [x1], x2
-#    v1: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x00000000000000005653504d4a474441 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x54514e4b4845423f
+#             d2:                 0x55524f4c49464340
+#             d3:                 0x5653504d4a474441
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x41'40'3f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x44'43'42 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x47'46'45 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x4a'49'48 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4d'4c'4b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x50'4f'4e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x53'52'51 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x56'55'54 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf402c		ld3 {v12.8b, v13.8b, v14.8b}, [x1], #24
-#   v12: 0x000000000000000053504d4a4744413e <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x000000000000000054514e4b4845423f <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x000000000000000055524f4c49464340 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x53504d4a4744413e
+#            d13:                 0x54514e4b4845423f
+#            d14:                 0x55524f4c49464340
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40'3f'3e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x43'42'41 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x46'45'44 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x49'48'47 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4c'4b'4a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x4f'4e'4d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x52'51'50 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x55'54'53 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c404416		ld3 {v22.8h, v23.8h, v24.8h}, [x0]
-#   v22: 0x2b2a25241f1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x2d2c272621201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x2b2a25241f1e191800000000ff00ff01 (0.05597, 0.02008, 0.006950, 0.002487, 0.000, 0.000, nan, nan)
+#            v23: 0x2d2c272621201b1a00000000feff0002 (0.08081, 0.02792, 0.01001, 0.003468, 0.000, 0.000, nan, 1.192e-07)
+#            v24: 0x2f2e292823221d1c1700000000ff0085 (0.1122, 0.04028, 0.01393, 0.004990, 0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2322'2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2928'2726'2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2442d		ld3 {v13.8h, v14.8h, v15.8h}, [x1], x2
-#   v13: 0x81807b7a75746f6e696863625d5c5756 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x83827d7c777671706b6a65645f5e5958 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x85847f7e797873726d6c676661605b5a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e696863625d5c5756 (-2.289e-05, 6.125e+04, 2.234e+04, 7608., 2768., 945.0, 343.0, 117.4)
+#            v14: 0x83827d7c777671706b6a65645f5e5958 (-5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5, 171.0)
+#            v15: 0x85847f7e797873726d6c676661605b5a (-8.416e-05, nan, 4.480e+04, 1.525e+04, 5552., 1894., 688.0, 235.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5b5a'5958'5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6160'5f5e'5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6766'6564'6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6d6c'6b6a'6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7372'7170'6f6e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7978'7776'7574 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8584'8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf443c		ld3 {v28.8h, v29.8h, v30.8h}, [x1], #48
-#   v28: 0x807f7a7974736e6d686762615c5b5655 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x82817c7b7675706f6a6964635e5d5857 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x84837e7d787772716c6b6665605f5a59 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x807f7a7974736e6d686762615c5b5655 (-7.570e-06, 5.302e+04, 1.822e+04, 6580., 2254., 816.5, 278.8, 101.3)
+#            v29: 0x82817c7b7675706f6a6964635e5d5857 (-3.821e-05, nan, 2.645e+04, 9080., 3282., 1123., 407.2, 138.9)
+#            v30: 0x84837e7d787772716c6b6665605f5a59 (-6.884e-05, nan, 3.658e+04, 1.319e+04, 4524., 1637., 559.5, 203.1)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5a59'5857'5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f'5e5d'5c5b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6665'6463'6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6c6b'6a69'6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7271'706f'6e6d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7877'7675'7473 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7e7d'7c7b'7a79 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8483'8281'807f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d402c15		ld3 {v21.b, v22.b, v23.b}[11], [x0]
-#   v21: 0x0000000001000000f5f4f3f2e9e8e7e6 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x2b2a2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x2d2c272602201b1a00000000feff0002 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x0000000001000000f5f4f3f2e9e8e7e6
+#            v22: 0x2b2a2524ff1e191800000000ff00ff01
+#            v23: 0x2d2c272602201b1a00000000feff0002
+#                            ╙─────────────────────── 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc22425		ld3 {v5.b, v6.b, v7.b}[9], [x1], x2
-#    v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x82818281828186818281828182818281 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000087000b0a0504fffef9f8 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f
+#             v6: 0x82818281828186818281828182818281
+#             v7: 0x00000000000087000b0a0504fffef9f8
+#                                ╙─────────────────── 0x87'86'85 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddf2037		ld3 {v23.b, v24.b, v25.b}[0], [x1], #3
-#   v23: 0x2d2c272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x2f2e292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x3b3a39382f2e2d2c2322212017161586 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0x2d2c272602201b1a00000000feff0084
+#            v24: 0x2f2e292823221d1c1700000000ff0085
+#            v25: 0x3b3a39382f2e2d2c2322212017161586
+#                                                  ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40a410		ld3 {v16.d, v17.d, v18.d}[0], [x0]
-#   v16: 0x6e6d6c6b6a696867ff0000850002ff01 (d16: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000474600000000000000fffeff (d17: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0xd2d1d0cfcecdcccb1700000000000000 (d18: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6e6d6c6b6a696867ff0000850002ff01 (..., -5.487e+303)
+#            v17: 0x00000000474600000000000000fffeff (..., 8.289e-317)
+#            v18: 0xd2d1d0cfcecdcccb1700000000000000 (..., 6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2a43e		ld3 {v30.d, v31.d, v0.d}[0], [x1], x2
-#   v30: 0x84837e7d787772718e8d8c8b8a898887 (d30: -1.41807e-238) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x0000000000000000969594939291908f (d31: -7.04826e-200) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (d0: -3.29099e-161) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84837e7d787772718e8d8c8b8a898887 (..., -1.418e-238)
+#            v31: 0x0000000000000000969594939291908f (..., -7.048e-200)
+#             v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (..., -3.291e-161)
+#                                                  ╙─ 0x9e9d9c9b9a999897'969594939291908f'8e8d8c8b8a898887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfa43c		ld3 {v28.d, v29.d, v30.d}[1], [x1], #24
-#   v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.09028e-243, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x9594939291908f8e6a6964635e5d5857 (-1.02545e-204, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.85140e-166, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.090e-243, ...)
+#            v29: 0x9594939291908f8e6a6964635e5d5857 (-1.025e-204, ...)
+#            v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.851e-166, ...)
+#                                  ╙───────────────── 0x9d9c9b9a99989796'9594939291908f8e'8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40700d		ld3 {v13.h, v14.h, v15.h}[2], [x0]
-#   v13: 0x81807b7a75746f6e6968ff015d5c5756 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x83827d7c777671706b6a00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x85847f7e797873726d6c008561605b5a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e6968ff015d5c5756 (..., nan, ...)
+#            v14: 0x83827d7c777671706b6a00025f5e5958 (..., 1.192e-07, ...)
+#            v15: 0x85847f7e797873726d6c008561605b5a (..., 7.927e-06, ...)
+#                                          ╙───────── 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc27836		ld3 {v22.h, v23.h, v24.h}[7], [x1], x2
-#   v22: 0x9f9e2524ff1e191800000000ff00ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0xa1a0272602201b1a00000000feff0084 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0xa3a2292823221d1c1700000000ff0085 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x9f9e2524ff1e191800000000ff00ff01 (-0.007439, ...)
+#            v23: 0xa1a0272602201b1a00000000feff0084 (-0.01099, ...)
+#            v24: 0xa3a2292823221d1c1700000000ff0085 (-0.01491, ...)
+#                      ╙───────────────────────────── 0xa3a2'a1a0'9f9e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddf782e		ld3 {v14.h, v15.h, v16.h}[3], [x1], #6
-#   v14: 0x83827d7c777671709e9d00025f5e5958 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x85847f7e79787372a09f008561605b5a <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x6e6d6c6b6a696867a2a100850002ff01 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0x83827d7c777671709e9d00025f5e5958 (..., -0.006458, ...)
+#            v15: 0x85847f7e79787372a09f008561605b5a (..., -0.009026, ...)
+#            v16: 0x6e6d6c6b6a696867a2a100850002ff01 (..., -0.01295, ...)
+#                                      ╙───────────── 0xa2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40b016		ld3 {v22.s, v23.s, v24.s}[3], [x0]
-#   v22: 0x0002ff01ff1e191800000000ff00ff01 (2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0xff00008502201b1a00000000feff0084 (-1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00fffeff23221d1c1700000000ff0085 (2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x0002ff01ff1e191800000000ff00ff01 (2.751e-40, ...)
+#            v23: 0xff00008502201b1a00000000feff0084 (-1.701e+38, ...)
+#            v24: 0x00fffeff23221d1c1700000000ff0085 (2.351e-38, ...)
+#                          ╙───────────────────────── 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2a03e		ld3 {v30.s, v31.s, v0.s}[2], [x1], x2
-#   v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.14938e-15, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000aaa9a8a7969594939291908f (..., -3.01375e-13, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.89780e-11, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.149e-15, ...)
+#            v31: 0x00000000aaa9a8a7969594939291908f (..., -3.014e-13, ...)
+#             v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.898e-11, ...)
+#                                  ╙───────────────── 0xaeadacab'aaa9a8a7'a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfb02c		ld3 {v12.s, v13.s, v14.s}[1], [x1], #12
-#   v12: 0x0000000000000000a5a4a3a24744413e (..., -2.85603e-16, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.48978e-14, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.96304e-11, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000a5a4a3a24744413e (..., -2.856e-16, ...)
+#            v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.490e-14, ...)
+#            v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.963e-11, ...)
+#                                          ╙───────── 0xadacabaa'a9a8a7a6'a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40e018		ld3r {v24.16b, v25.16b, v26.16b}, [x0]
-#   v24: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x01010101010101010101010101010101
+#            v25: 0xffffffffffffffffffffffffffffffff
+#            v26: 0x02020202020202020202020202020202
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2e038		ld3r {v24.16b, v25.16b, v26.16b}, [x1], x2
-#   v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#            v25: 0xafafafafafafafafafafafafafafafaf
+#            v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfe023		ld3r {v3.16b, v4.16b, v5.16b}, [x1], #3
-#    v3: 0xadadadadadadadadadadadadadadadad <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0xafafafafafafafafafafafafafafafaf <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v3: 0xadadadadadadadadadadadadadadadad
+#             v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#             v5: 0xafafafafafafafafafafafafafafafaf
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40ec04		ld3r {v4.1d, v5.1d, v6.1d}, [x0]
-#    v4: 0x0000000000000000ff0000850002ff01 (d4: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000fffeff (d5: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000001700000000000000 (d6: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01 (-5.487e+303)
+#             d5:                 0x0000000000fffeff (8.289e-317)
+#             d6:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2ec27		ld3r {v7.1d, v8.1d, v9.1d}, [x1], x2
-#    v7: 0x0000000000000000b7b6b5b4b3b2b1b0 (d7: -2.60696e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000bfbebdbcbbbab9b8 (d8: -0.120083) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x0000000000000000c7c6c5c4c3c2c1c0 (d9: -6.05398e+37) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xb7b6b5b4b3b2b1b0 (-2.607e-40)
+#             d8:                 0xbfbebdbcbbbab9b8 (-0.1201)
+#             d9:                 0xc7c6c5c4c3c2c1c0 (-6.054e+37)
+#                                                  ╙─ 0xc7c6c5c4c3c2c1c0'bfbebdbcbbbab9b8'b7b6b5b4b3b2b1b0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfec31		ld3r {v17.1d, v18.1d, v19.1d}, [x1], #24
-#   v17: 0x0000000000000000b6b5b4b3b2b1b0af (d17: -3.80205e-45) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x0000000000000000bebdbcbbbab9b8b7 (d18: -1.77248e-06) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x0000000000000000c6c5c4c3c2c1c0bf (d19: -8.83040e+32) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xb6b5b4b3b2b1b0af (-3.802e-45)
+#            d18:                 0xbebdbcbbbab9b8b7 (-1.772e-06)
+#            d19:                 0xc6c5c4c3c2c1c0bf (-8.830e+32)
+#                                                  ╙─ 0xc6c5c4c3c2c1c0bf'bebdbcbbbab9b8b7'b6b5b4b3b2b1b0af <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40ec10		ld3r {v16.2d, v17.2d, v18.2d}, [x0]
-#   v16: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v17: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v18: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#                                  ╙───────────────╨─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2ec34		ld3r {v20.2d, v21.2d, v22.2d}, [x1], x2
-#   v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.11344e+71, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.05087e+110, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.54613e+148, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.113e+71, -4.113e+71)
+#            v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.051e+110, -2.051e+110)
+#            v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.546e+148, -9.546e+148)
+#                                  ╙───────────────╨─ 0xdedddcdbdad9d8d7'd6d5d4d3d2d1d0cf'cecdcccbcac9c8c7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfec2e		ld3r {v14.2d, v15.2d, v16.2d}, [x1], #24
-#   v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.06516e+66, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.98548e+105, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.40766e+144, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.065e+66, -6.065e+66)
+#            v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.985e+105, -2.985e+105)
+#            v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.408e+144, -1.408e+144)
+#                                  ╙───────────────╨─ 0xdddcdbdad9d8d7d6'd5d4d3d2d1d0cfce'cdcccbcac9c8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40e80a		ld3r {v10.2s, v11.2s, v12.2s}, [x0]
-#   v10: 0x00000000000000000002ff010002ff01 (s10: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x0000000000000000ff000085ff000085 (s11: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x000000000000000000fffeff00fffeff (s12: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d11:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#            d12:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#                                          ╙───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2e820		ld3r {v0.2s, v1.2s, v2.2s}, [x1], x2
-#    v0: 0x0000000000000000e1e0dfdee1e0dfde (s0: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x0000000000000000e5e4e3e2e5e4e3e2 (s1: -1.35113e+23) <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x0000000000000000e9e8e7e6e9e8e7e6 (s2: -3.51957e+25) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#             d1:                 0xe5e4e3e2e5e4e3e2 (-1.351e+23, -1.351e+23)
+#             d2:                 0xe9e8e7e6e9e8e7e6 (-3.520e+25, -3.520e+25)
+#                                          ╙───────╨─ 0xe9e8e7e6'e5e4e3e2'e1e0dfde <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfe837		ld3r {v23.2s, v24.2s, v25.2s}, [x1], #12
-#   v23: 0x0000000000000000e0dfdedde0dfdedd (s23: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000e4e3e2e1e4e3e2e1 (s24: -3.36301e+22) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x0000000000000000e8e7e6e5e8e7e6e5 (s25: -8.76101e+24) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#            d24:                 0xe4e3e2e1e4e3e2e1 (-3.363e+22, -3.363e+22)
+#            d25:                 0xe8e7e6e5e8e7e6e5 (-8.761e+24, -8.761e+24)
+#                                          ╙───────╨─ 0xe8e7e6e5'e4e3e2e1'e0dfdedd <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40e416		ld3r {v22.4h, v23.4h, v24.4h}, [x0]
-#   v22: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d23:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d24:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                                      ╙───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2e426		ld3r {v6.4h, v7.4h, v8.4h}, [x1], x2
-#    v6: 0x0000000000000000eae9eae9eae9eae9 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x0000000000000000ecebecebecebeceb <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000eeedeeedeeedeeed <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d6:                 0xeae9eae9eae9eae9 (-3538., -3538., -3538., -3538.)
+#             d7:                 0xecebecebecebeceb (-5036., -5036., -5036., -5036.)
+#             d8:                 0xeeedeeedeeedeeed (-7092., -7092., -7092., -7092.)
+#                                      ╙───╨───╨───╨─ 0xeeed'eceb'eae9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfe427		ld3r {v7.4h, v8.4h, v9.4h}, [x1], #6
-#    v7: 0x0000000000000000e9e8e9e8e9e8e9e8 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x0000000000000000ebeaebeaebeaebea <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x0000000000000000edecedecedecedec <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xe9e8e9e8e9e8e9e8 (-3024., -3024., -3024., -3024.)
+#             d8:                 0xebeaebeaebeaebea (-4052., -4052., -4052., -4052.)
+#             d9:                 0xedecedecedecedec (-6064., -6064., -6064., -6064.)
+#                                      ╙───╨───╨───╨─ 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40e81a		ld3r {v26.4s, v27.4s, v28.4s}, [x0]
-#   v26: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v27: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v28: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#                          ╙───────╨───────╨───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2e820		ld3r {v0.4s, v1.4s, v2.4s}, [x1], x2
-#    v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (..., -2.38613e+30, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (..., -6.21029e+32, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (..., -1.61590e+35, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (-2.386e+30, -2.386e+30, -2.386e+30, -2.386e+30)
+#             v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (-6.210e+32, -6.210e+32, -6.210e+32, -6.210e+32)
+#             v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (-1.616e+35, -1.616e+35, -1.616e+35, -1.616e+35)
+#                          ╙───────╨───────╨───────╨─ 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfe83e		ld3r {v30.4s, v31.4s, v0.4s}, [x1], #12
-#   v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (..., -5.94046e+29, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (..., -1.54621e+32, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (..., -4.02346e+34, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (-5.940e+29, -5.940e+29, -5.940e+29, -5.940e+29)
+#            v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (-1.546e+32, -1.546e+32, -1.546e+32, -1.546e+32)
+#             v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (-4.023e+34, -4.023e+34, -4.023e+34, -4.023e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d40e002		ld3r {v2.8b, v3.8b, v4.8b}, [x0]
-#    v2: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x0101010101010101
+#             d3:                 0xffffffffffffffff
+#             d4:                 0x0202020202020202
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dc2e02a		ld3r {v10.8b, v11.8b, v12.8b}, [x1], x2
-#   v10: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000000000fbfbfbfbfbfbfbfb <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xf9f9f9f9f9f9f9f9
+#            d11:                 0xfafafafafafafafa
+#            d12:                 0xfbfbfbfbfbfbfbfb
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfb'fa'f9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0ddfe03c		ld3r {v28.8b, v29.8b, v30.8b}, [x1], #3
-#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d40e406		ld3r {v6.8h, v7.8h, v8.8h}, [x0]
-#    v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v7: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#             v8: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dc2e43d		ld3r {v29.8h, v30.8h, v31.8h}, [x1], x2
-#   v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4ddfe427		ld3r {v7.8h, v8.8h, v9.8h}, [x1], #6
-#    v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#             v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v9: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xfffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c400003		ld4 {v3.16b, v4.16b, v5.16b, v6.16b}, [x0]
-#    v3: 0x3c3834302c2824201c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x3d3935312d2925211d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x3e3a36322e2a26221e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x3f3b37332f2b27231f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x3c3834302c2824201c18000000ff8501
+#             v4: 0x3d3935312d2925211d19000000fe00ff
+#             v5: 0x3e3a36322e2a26221e1a000000ff0002
+#             v6: 0x3f3b37332f2b27231f1b17000000ff00
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc20022		ld4 {v2.16b, v3.16b, v4.16b, v5.16b}, [x1], x2
-#    v2: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x3f3b37332f2b27231f1b17130f0b0703 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x3c3834302c2824201c1814100c080400
+#             v3: 0x3d3935312d2925211d1915110d090501
+#             v4: 0x3e3a36322e2a26221e1a16120e0a0602
+#             v5: 0x3f3b37332f2b27231f1b17130f0b0703
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x03'02'01'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x07'06'05'04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0b'0a'09'08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0f'0e'0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x13'12'11'10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'16'15'14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf0025		ld4 {v5.16b, v6.16b, v7.16b, v8.16b}, [x1], #64
-#    v5: 0x3b37332f2b27231f1b17130f0b0703ff <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x3c3834302c2824201c1814100c080400 <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x3d3935312d2925211d1915110d090501 <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x3e3a36322e2a26221e1a16120e0a0602 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3b37332f2b27231f1b17130f0b0703ff
+#             v6: 0x3c3834302c2824201c1814100c080400
+#             v7: 0x3d3935312d2925211d1915110d090501
+#             v8: 0x3e3a36322e2a26221e1a16120e0a0602
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1e'1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22'21'20'1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x26'25'24'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a'29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2e'2d'2c'2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x32'31'30'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x36'35'34'33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3a'39'38'37 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3e'3d'3c'3b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c400c12		ld4 {v18.2d, v19.2d, v20.2d, v21.2d}, [x0]
-#   v18: 0x2726252423222120ff0000850002ff01 (4.28794e-120, -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.98829e-81, 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x37363534333231301700000000000000 (9.95833e-43, 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.000461414, 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2726252423222120ff0000850002ff01 (4.288e-120, -5.487e+303)
+#            v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.988e-81, 8.289e-317)
+#            v20: 0x37363534333231301700000000000000 (9.958e-43, 6.689e-198)
+#            v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.0004614, 8.568e-159)
+#                                  ║               ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938'3736353433323130'2f2e2d2c2b2a2928'2726252423222120 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc20c24		ld4 {v4.2d, v5.2d, v6.2d, v7.2d}, [x1], x2
-#    v4: 0x666564636261605f464544434241403f (1.81795e+185, 3.36984e+30) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.50866e+223, 1.57975e+69) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x767574737271706f565554535251504f (4.22243e+262, 7.82703e+107) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.97467e+301, 3.66628e+146) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v4: 0x666564636261605f464544434241403f (1.818e+185, 3.370e+30)
+#             v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.509e+223, 1.580e+69)
+#             v6: 0x767574737271706f565554535251504f (4.222e+262, 7.827e+107)
+#             v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.975e+301, 3.666e+146)
+#                                  ║               ╙─ 0x5e5d5c5b5a595857'565554535251504f'4e4d4c4b4a494847'464544434241403f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7e7d7c7b7a797877'767574737271706f'6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf0c3d		ld4 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1], #64
-#   v29: 0x6564636261605f5e4544434241403f3e (2.64379e+180, 4.89923e+25) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.25402e+219, 2.32790e+64) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x7574737271706f6e5554535251504f4e (6.14144e+257, 1.13810e+103) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.91053e+296, 5.40301e+141) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x6564636261605f5e4544434241403f3e (2.644e+180, 4.899e+25)
+#            v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.254e+219, 2.328e+64)
+#            v31: 0x7574737271706f6e5554535251504f4e (6.141e+257, 1.138e+103)
+#             v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.911e+296, 5.403e+141)
+#                                  ║               ╙─ 0x5d5c5b5a59585756'5554535251504f4e'4d4c4b4a49484746'4544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7d7c7b7a79787776'7574737271706f6e'6d6c6b6a69686766'6564636261605f5e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40081b		ld4 {v27.2s, v28.2s, v29.2s, v30.2s}, [x0]
-#   v27: 0x0000000000000000000000000002ff01 (..., 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x000000000000000017000000ff000085 (..., 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000001b1a191800fffeff (..., 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000001f1e1d1c00000000 (..., 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x000000000002ff01 (0.000, 2.751e-40)
+#            d28:                 0x17000000ff000085 (4.136e-25, -1.701e+38)
+#            d29:                 0x1b1a191800fffeff (1.275e-22, 2.351e-38)
+#            d30:                 0x1f1e1d1c00000000 (3.348e-20, 0.000)
+#                                          ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc20838		ld4 {v24.2s, v25.2s, v26.2s, v27.2s}, [x1], x2
-#   v24: 0x000000000000000091908f8e81807f7e (..., -2.28077e-28, -4.72027e-38) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000009594939285848382 (..., -6.00095e-26, -1.24615e-35) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x00000000000000009998979689888786 (..., -1.57777e-23, -3.28683e-33) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000009d9c9b9a8d8c8b8a (..., -4.14537e-21, -8.66176e-31) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x91908f8e81807f7e (-2.281e-28, -4.720e-38)
+#            d25:                 0x9594939285848382 (-6.001e-26, -1.246e-35)
+#            d26:                 0x9998979689888786 (-1.578e-23, -3.287e-33)
+#            d27:                 0x9d9c9b9a8d8c8b8a (-4.145e-21, -8.662e-31)
+#                                          ║       ╙─ 0x8d8c8b8a'89888786'85848382'81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9d9c9b9a'99989796'95949392'91908f8e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf0824		ld4 {v4.2s, v5.2s, v6.2s, v7.2s}, [x1], #32
-#    v4: 0x0000000000000000908f8e8d807f7e7d (..., -5.66232e-29, -1.17085e-38) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000009493929184838281 (..., -1.49010e-26, -3.09178e-36) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000009897969588878685 (..., -3.91846e-24, -8.15664e-34) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000009c9b9a998c8b8a89 (..., -1.02970e-21, -2.14997e-31) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x908f8e8d807f7e7d (-5.662e-29, -1.171e-38)
+#             d5:                 0x9493929184838281 (-1.490e-26, -3.092e-36)
+#             d6:                 0x9897969588878685 (-3.918e-24, -8.157e-34)
+#             d7:                 0x9c9b9a998c8b8a89 (-1.030e-21, -2.150e-31)
+#                                          ║       ╙─ 0x8c8b8a89'88878685'84838281'807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99'98979695'94939291'908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c400410		ld4 {v16.4h, v17.4h, v18.4h, v19.4h}, [x0]
-#   v16: 0x000000000000000019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000001b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000001d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000001f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0x19180000feffff01 (0.002487, 0.000, nan, nan)
+#            d17:                 0x1b1a000000ff0002 (0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            d18:                 0x1d1c000000000085 (0.004990, 0.000, 0.000, 7.927e-06)
+#            d19:                 0x1f1e17000000ff00 (0.006950, 0.001709, 0.000, nan)
+#                                      ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc20437		ld4 {v23.4h, v24.4h, v25.4h, v26.4h}, [x1], x2
-#   v23: 0x0000000000000000b6b5aeada6a59e9d <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000b8b7b0afa8a7a09f <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x0000000000000000bab9b2b1aaa9a2a1 <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x0000000000000000bcbbb4b3acaba4a3 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xb6b5aeada6a59e9d (-0.4192, -0.1043, -0.02596, -0.006458)
+#            d24:                 0xb8b7b0afa8a7a09f (-0.5894, -0.1464, -0.03635, -0.009026)
+#            d25:                 0xbab9b2b1aaa9a2a1 (-0.8403, -0.2091, -0.05203, -0.01295)
+#            d26:                 0xbcbbb4b3acaba4a3 (-1.183, -0.2937, -0.07294, -0.01811)
+#                                      ║   ║   ║   ╙─ 0xa4a3'a2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xacab'aaa9'a8a7'a6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb4b3'b2b1'b0af'aead <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbcbb'bab9'b8b7'b6b5 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf0422		ld4 {v2.4h, v3.4h, v4.4h, v5.4h}, [x1], #32
-#    v2: 0x0000000000000000b5b4adaca5a49d9c <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x0000000000000000b7b6afaea7a69f9e <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x0000000000000000b9b8b1b0a9a8a1a0 <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0000000000000000bbbab3b2abaaa3a2 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xb5b4adaca5a49d9c (-0.3564, -0.08862, -0.02203, -0.005478)
+#             d3:                 0xb7b6afaea7a69f9e (-0.4819, -0.1200, -0.02988, -0.007439)
+#             d4:                 0xb9b8b1b0a9a8a1a0 (-0.7148, -0.1777, -0.04419, -0.01099)
+#             d5:                 0xbbbab3b2abaaa3a2 (-0.9658, -0.2405, -0.05988, -0.01491)
+#                                      ║   ║   ║   ╙─ 0xa3a2'a1a0'9f9e'9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xabaa'a9a8'a7a6'a5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb3b2'b1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba'b9b8'b7b6'b5b4 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c400807		ld4 {v7.4s, v8.4s, v9.4s, v10.4s}, [x0]
-#    v7: 0x3332313023222120000000000002ff01 (4.14886e-08, 8.78905e-18, 0.00000, 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x373635342726252417000000ff000085 (1.08604e-05, 2.30573e-15, 4.13590e-25, -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x3b3a39382b2a29281b1a191800fffeff (0.00284155, 6.04532e-13, 1.27467e-22, 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.743122, 1.58413e-10, 3.34819e-20, 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x3332313023222120000000000002ff01 (4.149e-08, 8.789e-18, 0.000, 2.751e-40)
+#             v8: 0x373635342726252417000000ff000085 (1.086e-05, 2.306e-15, 4.136e-25, -1.701e+38)
+#             v9: 0x3b3a39382b2a29281b1a191800fffeff (0.002842, 6.045e-13, 1.275e-22, 2.351e-38)
+#            v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.7431, 1.584e-10, 3.348e-20, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2f2e2d2c'2b2a2928'27262524'23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534'33323130 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc2083c		ld4 {v28.4s, v29.4s, v30.4s, v31.4s}, [x1], x2
-#   v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.47890e+29, -3.21185e+19, -6.93919e+09, -1.49017) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.84962e+31, -8.37048e+21, -1.81093e+12, -389.514) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.00179e+34, -2.18077e+24, -4.72428e+14, -101772.) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.60629e+36, -5.67986e+26, -1.23202e+17, -2.65799e+07) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#            v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.850e+31, -8.370e+21, -1.811e+12, -389.5)
+#            v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.002e+34, -2.181e+24, -4.724e+14, -1.018e+05)
+#            v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.606e+36, -5.680e+26, -1.232e+17, -2.658e+07)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf083d		ld4 {v29.4s, v30.4s, v31.4s, v0.4s}, [x1], #64
-#   v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.68172e+28, -7.99345e+18, -1.72638e+09, -0.370581) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.58428e+30, -2.08336e+21, -4.50576e+11, -96.8765) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.49430e+33, -5.42822e+23, -1.17555e+14, -25314.4) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.48966e+35, -1.41390e+26, -3.06592e+16, -6.61207e+06) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.682e+28, -7.993e+18, -1.726e+09, -0.3706)
+#            v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.584e+30, -2.083e+21, -4.506e+11, -96.88)
+#            v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.494e+33, -5.428e+23, -1.176e+14, -2.531e+04)
+#             v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.490e+35, -1.414e+26, -3.066e+16, -6.612e+06)
+#                          ║       ║       ║       ╙─ 0xcac9c8c7'c6c5c4c3'c2c1c0bf'bebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdad9d8d7'd6d5d4d3'd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xeae9e8e7'e6e5e4e3'e2e1e0df'dedddcdb <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfaf9f8f7'f6f5f4f3'f2f1f0ef'eeedeceb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c40000f		ld4 {v15.8b, v16.8b, v17.8b, v18.8b}, [x0]
-#   v15: 0x00000000000000001c18000000ff8501 <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x00000000000000001d19000000fe00ff <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000001e1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000001f1b17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#            d15:                 0x1c18000000ff8501
+#            d16:                 0x1d19000000fe00ff
+#            d17:                 0x1e1a000000ff0002
+#            d18:                 0x1f1b17000000ff00
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cc2003b		ld4 {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
-#   v27: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000001a16120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x17130f0b0703fffb
+#            d28:                 0x1814100c080400fc
+#            d29:                 0x1915110d090501fd
+#            d30:                 0x1a16120e0a0602fe
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfe'fd'fc'fb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0cdf0025		ld4 {v5.8b, v6.8b, v7.8b, v8.8b}, [x1], #32
-#    v5: 0x000000000000000016120e0a0602fefa <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x000000000000000017130f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000001814100c080400fc <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000001915110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x16120e0a0602fefa
+#             d6:                 0x17130f0b0703fffb
+#             d7:                 0x1814100c080400fc
+#             d8:                 0x1915110d090501fd
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfd'fc'fb'fa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x01'00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x05'04'03'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x09'08'07'06 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0d'0c'0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x11'10'0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14'13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x19'18'17'16 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c400419		ld4 {v25.8h, v26.8h, v27.8h, v28.8h}, [x0]
-#   v25: 0x393831302928212019180000feffff01 <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x3b3a33322b2a23221b1a000000ff0002 <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x3d3c35342d2c25241d1c000000000085 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x3f3e37362f2e27261f1e17000000ff00 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831302928212019180000feffff01 (0.6523, 0.1621, 0.04028, 0.01001, 0.002487, 0.000, nan, nan)
+#            v26: 0x3b3a33322b2a23221b1a000000ff0002 (0.9033, 0.2249, 0.05597, 0.01393, 0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            v27: 0x3d3c35342d2c25241d1c000000000085 (1.309, 0.3252, 0.08081, 0.02008, 0.004990, 0.000, 0.000, 7.927e-06)
+#            v28: 0x3f3e37362f2e27261f1e17000000ff00 (1.811, 0.4507, 0.1122, 0.02792, 0.006950, 0.001709, 0.000, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726'2524'2322'2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2f2e'2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3736'3534'3332'3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e'3d3c'3b3a'3938 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cc20422		ld4 {v2.8h, v3.8h, v4.8h, v5.8h}, [x1], x2
-#    v2: 0x53524b4a43423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x55544d4c45443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x57564f4e47463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x59585150494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x53524b4a43423b3a33322b2a23221b1a (58.56, 14.58, 3.629, 0.9033, 0.2249, 0.05597, 0.01393, 0.003468)
+#             v3: 0x55544d4c45443d3c35342d2c25241d1c (85.25, 21.19, 5.266, 1.309, 0.3252, 0.08081, 0.02008, 0.004990)
+#             v4: 0x57564f4e47463f3e37362f2e27261f1e (117.4, 29.22, 7.273, 1.811, 0.4507, 0.1122, 0.02792, 0.006950)
+#             v5: 0x59585150494841403938313029282120 (171.0, 42.50, 10.56, 2.625, 0.6523, 0.1621, 0.04028, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120'1f1e'1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2928'2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3130'2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3938'3736'3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4140'3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948'4746'4544'4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5150'4f4e'4d4c'4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5958'5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4cdf0434		ld4 {v20.8h, v21.8h, v22.8h, v23.8h}, [x1], #64
-#   v20: 0x52514a4942413a3932312a2922211a19 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x54534c4b44433c3b34332c2b24231c1b <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x56554e4d46453e3d36352e2d26251e1d <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x5857504f4847403f3837302f2827201f <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2922211a19 (50.53, 12.57, 3.127, 0.7778, 0.1935, 0.04813, 0.01197, 0.002977)
+#            v21: 0x54534c4b44433c3b34332c2b24231c1b (69.19, 17.17, 4.262, 1.058, 0.2625, 0.06512, 0.01616, 0.004009)
+#            v22: 0x56554e4d46453e3d36352e2d26251e1d (101.3, 25.20, 6.270, 1.560, 0.3879, 0.09650, 0.02400, 0.005970)
+#            v23: 0x5857504f4847403f3837302f2827201f (138.9, 34.47, 8.555, 2.123, 0.5269, 0.1307, 0.03244, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f'1e1d'1c1b'1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2827'2625'2423'2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x302f'2e2d'2c2b'2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3837'3635'3433'3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x403f'3e3d'3c3b'3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847'4645'4443'4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x504f'4e4d'4c4b'4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5857'5655'5453'5251 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d602c14		ld4 {v20.b, v21.b, v22.b, v23.b}[3], [x0]
-#   v20: 0x52514a4942413a3932312a2901211a19 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x54534c4b44433c3b34332c2bff231c1b <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x56554e4d46453e3d36352e2d02251e1d <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x5857504f4847403f3837302f0027201f <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2901211a19
+#            v21: 0x54534c4b44433c3b34332c2bff231c1b
+#            v22: 0x56554e4d46453e3d36352e2d02251e1d
+#            v23: 0x5857504f4847403f3837302f0027201f
+#                                            ╙─────── 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de22c2c		ld4 {v12.b, v13.b, v14.b, v15.b}[3], [x1], x2
-#   v12: 0x0000000000000000fbfbfbfb59fbfbfb <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x81807b7a75746f6ea9a8a7a65a5c5756 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x00000000000000001c1800005cff8501 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000fbfbfbfb59fbfbfb
+#            v13: 0x81807b7a75746f6ea9a8a7a65a5c5756
+#            v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6
+#            v15: 0x00000000000000001c1800005cff8501
+#                                            ╙─────── 0x5c'5b'5a'59 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dff383b		ld4 {v27.b, v28.b, v29.b, v30.b}[6], [x1], #4
-#   v27: 0x3d3c35342d2c25241d58000000000085 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x3f3e37362f2e27261f5917000000ff00 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000195a110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000001a5b120e0a0602fe <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x3d3c35342d2c25241d58000000000085
+#            v28: 0x3f3e37362f2e27261f5917000000ff00
+#            v29: 0x0000000000000000195a110d090501fd
+#            v30: 0x00000000000000001a5b120e0a0602fe
+#                                      ╙───────────── 0x5b'5a'59'58 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60a41c		ld4 {v28.d, v29.d, v30.d, v31.d}[1], [x0]
-#   v28: 0xff0000850002ff011f5917000000ff00 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000fffeff195a110d090501fd (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x17000000000000001a5b120e0a0602fe (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff0000850002ff011f5917000000ff00 (-5.487e+303, ...)
+#            v29: 0x0000000000fffeff195a110d090501fd (8.289e-317, ...)
+#            v30: 0x17000000000000001a5b120e0a0602fe (6.689e-198, ...)
+#            v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.568e-159, ...)
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2a42f		ld4 {v15.d, v16.d, v17.d, v18.d}[1], [x1], x2
-#   v15: 0x636261605f5e5d5c1c1800005cff8501 (5.54935e+170, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x6b6a6968676665641d19000000fe00ff (2.71346e+209, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.28953e+248, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x7b7a7978777675741f1b17000000ff00 (6.29888e+286, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x636261605f5e5d5c1c1800005cff8501 (5.549e+170, ...)
+#            v16: 0x6b6a6968676665641d19000000fe00ff (2.713e+209, ...)
+#            v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.290e+248, ...)
+#            v18: 0x7b7a7978777675741f1b17000000ff00 (6.299e+286, ...)
+#                                  ╙───────────────── 0x7b7a797877767574'737271706f6e6d6c'6b6a696867666564'636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffa430		ld4 {v16.d, v17.d, v18.d, v19.d}[1], [x1], #32
-#   v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.00514e+165, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x6a696867666564631e1a000000ff0002 (3.98304e+204, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.86056e+243, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x7a797877767574731f1e17000000ff00 (9.24687e+281, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.005e+165, ...)
+#            v17: 0x6a696867666564631e1a000000ff0002 (3.983e+204, ...)
+#            v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.861e+243, ...)
+#            v19: 0x7a797877767574731f1e17000000ff00 (9.247e+281, ...)
+#                                  ╙───────────────── 0x7a79787776757473'7271706f6e6d6c6b'6a69686766656463'6261605f5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d607002		ld4 {v2.h, v3.h, v4.h, v5.h}[6], [x0]
-#    v2: 0x5352ff0143423b3a33322b2a23221b1a <- 0x~~~~~~~~~~~~~~~~
-#    v3: 0x5554000245443d3c35342d2c25241d1c <- 0x~~~~~~~~~~~~~~~~
-#    v4: 0x5756008547463f3e37362f2e27261f1e <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x5958ff00494841403938313029282120 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x5352ff0143423b3a33322b2a23221b1a (..., nan, ...)
+#             v3: 0x5554000245443d3c35342d2c25241d1c (..., 1.192e-07, ...)
+#             v4: 0x5756008547463f3e37362f2e27261f1e (..., 7.927e-06, ...)
+#             v5: 0x5958ff00494841403938313029282120 (..., nan, ...)
+#                          ╙───────────────────────── 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de27825		ld4 {v5.h, v6.h, v7.h, v8.h}[3], [x1], x2
-#    v5: 0x5958ff00494841407c7b313029282120 <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000007e7d0f0b0703fffb <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x0000000000000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5958ff00494841407c7b313029282120 (..., nan, ...)
+#             v6: 0x00000000000000007e7d0f0b0703fffb (..., nan, ...)
+#             v7: 0x0000000000000000807f100c080400fc (..., -7.570e-06, ...)
+#             v8: 0x00000000000000008281110d090501fd (..., -3.821e-05, ...)
+#                                      ╙───────────── 0x8281'807f'7e7d'7c7b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dff7027		ld4 {v7.h, v8.h, v9.h, v10.h}[6], [x1], #8
-#    v7: 0x00007b7a00000000807f100c080400fc <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00007d7c000000008281110d090501fd <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x3b3a7f7e2b2a29281b1a191800fffeff <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x00007b7a00000000807f100c080400fc (..., 6.125e+04, ...)
+#             v8: 0x00007d7c000000008281110d090501fd (..., nan, ...)
+#             v9: 0x3b3a7f7e2b2a29281b1a191800fffeff (..., nan, ...)
+#            v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 (..., -2.289e-05, ...)
+#                          ╙───────────────────────── 0x8180'7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60b006		ld4 {v6.s, v7.s, v8.s, v9.s}[1], [x0]
-#    v6: 0x00000000000000000002ff010703fffb (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00007b7a00000000ff000085080400fc (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00007d7c0000000000fffeff090501fd (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x00000000000000000002ff010703fffb (..., 2.751e-40, ...)
+#             v7: 0x00007b7a00000000ff000085080400fc (..., -1.701e+38, ...)
+#             v8: 0x00007d7c0000000000fffeff090501fd (..., 2.351e-38, ...)
+#             v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.000, ...)
+#                                          ╙───────── 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2a039		ld4 {v25.s, v26.s, v27.s, v28.s}[2], [x1], x2
-#   v25: 0x393831308584838219180000feffff01 (..., -1.24615e-35, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.28683e-33, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.66176e-31, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.28077e-28, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831308584838219180000feffff01 (..., -1.246e-35, ...)
+#            v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.287e-33, ...)
+#            v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.662e-31, ...)
+#            v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.281e-28, ...)
+#                                  ╙───────────────── 0x91908f8e'8d8c8b8a'89888786'85848382 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffb028		ld4 {v8.s, v9.s, v10.s, v11.s}[3], [x1], #16
-#    v8: 0x848382810000000000fffeff090501fd (-3.09178e-36, ...) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x888786852b2a29280000000000fffeff (-8.15664e-34, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.14997e-31, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x908f8e8d00000000fafafafafafafafa (-5.66232e-29, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x848382810000000000fffeff090501fd (-3.092e-36, ...)
+#             v9: 0x888786852b2a29280000000000fffeff (-8.157e-34, ...)
+#            v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.150e-31, ...)
+#            v11: 0x908f8e8d00000000fafafafafafafafa (-5.662e-29, ...)
+#                          ╙───────────────────────── 0x908f8e8d'8c8b8a89'88878685'84838281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60e00e		ld4r {v14.16b, v15.16b, v16.16b, v17.16b}, [x0]
-#   v14: 0x01010101010101010101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0xffffffffffffffffffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x02020202020202020202020202020202 <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x01010101010101010101010101010101
+#            v15: 0xffffffffffffffffffffffffffffffff
+#            v16: 0x02020202020202020202020202020202
+#            v17: 0x00000000000000000000000000000000
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2e02d		ld4r {v13.16b, v14.16b, v15.16b, v16.16b}, [x1], x2
-#   v13: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
-#   v15: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0x94949494949494949494949494949494 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x91919191919191919191919191919191
+#            v14: 0x92929292929292929292929292929292
+#            v15: 0x93939393939393939393939393939393
+#            v16: 0x94949494949494949494949494949494
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x94'93'92'91 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffe029		ld4r {v9.16b, v10.16b, v11.16b, v12.16b}, [x1], #4
-#    v9: 0x90909090909090909090909090909090 <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x91919191919191919191919191919191 <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x92929292929292929292929292929292 <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x93939393939393939393939393939393 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             v9: 0x90909090909090909090909090909090
+#            v10: 0x91919191919191919191919191919191
+#            v11: 0x92929292929292929292929292929292
+#            v12: 0x93939393939393939393939393939393
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x93'92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60ec08		ld4r {v8.1d, v9.1d, v10.1d, v11.1d}, [x0]
-#    v8: 0x0000000000000000ff0000850002ff01 (d8: -5.48682e+303) <- 0x~~~~~~~~~~~~~~~~
-#    v9: 0x00000000000000000000000000fffeff (d9: 8.28892e-317) <- 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000001700000000000000 (d10: 6.68887e-198) <- 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000001f1e1d1c1b1a1918 (d11: 8.56775e-159) <- 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xff0000850002ff01 (-5.487e+303)
+#             d9:                 0x0000000000fffeff (8.289e-317)
+#            d10:                 0x1700000000000000 (6.689e-198)
+#            d11:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2ec24		ld4r {v4.1d, v5.1d, v6.1d, v7.1d}, [x1], x2
-#    v4: 0x00000000000000009b9a999897969594 (d4: -1.05028e-175) <- 0x~~~~~~~~~~~~~~~~
-#    v5: 0x0000000000000000a3a2a1a09f9e9d9c (d5: -5.00653e-137) <- 0x~~~~~~~~~~~~~~~~
-#    v6: 0x0000000000000000abaaa9a8a7a6a5a4 (d6: -2.43801e-98) <- 0x~~~~~~~~~~~~~~~~
-#    v7: 0x0000000000000000b3b2b1b0afaeadac (d7: -1.16334e-59) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x9b9a999897969594 (-1.050e-175)
+#             d5:                 0xa3a2a1a09f9e9d9c (-5.007e-137)
+#             d6:                 0xabaaa9a8a7a6a5a4 (-2.438e-98)
+#             d7:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac'abaaa9a8a7a6a5a4'a3a2a1a09f9e9d9c'9b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffec3a		ld4r {v26.1d, v27.1d, v28.1d, v29.1d}, [x1], #32
-#   v26: 0x00000000000000009a99989796959493 (d26: -1.54211e-180) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0x0000000000000000a2a1a09f9e9d9c9b (d27: -7.22772e-142) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x0000000000000000aaa9a8a7a6a5a4a3 (d28: -3.58004e-103) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000b2b1b0afaeadacab (d29: -1.67978e-64) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x9a99989796959493 (-1.542e-180)
+#            d27:                 0xa2a1a09f9e9d9c9b (-7.228e-142)
+#            d28:                 0xaaa9a8a7a6a5a4a3 (-3.580e-103)
+#            d29:                 0xb2b1b0afaeadacab (-1.680e-64)
+#                                                  ╙─ 0xb2b1b0afaeadacab'aaa9a8a7a6a5a4a3'a2a1a09f9e9d9c9b'9a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60ec13		ld4r {v19.2d, v20.2d, v21.2d, v22.2d}, [x0]
-#   v19: 0xff0000850002ff01ff0000850002ff01 (-5.48682e+303, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x0000000000fffeff0000000000fffeff (8.28892e-317, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x17000000000000001700000000000000 (6.68887e-198, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.56775e-159, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v20: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v21: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#            v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.568e-159, 8.568e-159)
+#                                  ╙───────────────╨─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2ec3c		ld4r {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], x2
-#   v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.31108e-26, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.90391e+13, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.92941e+52, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.07279e+90, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.311e-26, -8.311e-26)
+#            v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.904e+13, -3.904e+13)
+#            v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.929e+52, -1.929e+52)
+#            v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.073e+90, -9.073e+90)
+#                                  ╙───────────────╨─ 0xd2d1d0cfcecdcccb'cac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffec2f		ld4r {v15.2d, v16.2d, v17.2d, v18.2d}, [x1], #32
-#   v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.21867e-30, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.62003e+08, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.82942e+47, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.30639e+86, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.219e-30, -1.219e-30)
+#            v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.620e+08, -5.620e+08)
+#            v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.829e+47, -2.829e+47)
+#            v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.306e+86, -1.306e+86)
+#                                  ╙───────────────╨─ 0xd1d0cfcecdcccbca'c9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60e81f		ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [x0]
-#   v31: 0x00000000000000000002ff010002ff01 (s31: 2.75149e-40) <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x0000000000000000ff000085ff000085 (s0: -1.70144e+38) <- 0x~~~~~~~~~~~~~~~~
-#    v1: 0x000000000000000000fffeff00fffeff (s1: 2.35095e-38) <- 0x~~~~~~~~~~~~~~~~
-#    v2: 0x00000000000000000000000000000000 (s2: 0.00000) <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#             d0:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#             d1:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#             d2:                 0x0000000000000000 (0.000, 0.000)
+#                                          ╙───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2e83c		ld4r {v28.2s, v29.2s, v30.2s, v31.2s}, [x1], x2
-#   v28: 0x0000000000000000d5d4d3d2d5d4d3d2 (s28: -2.92508e+13) <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000d9d8d7d6d9d8d7d6 (s29: -7.62949e+15) <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000dddcdbdadddcdbda (s30: -1.98932e+18) <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x0000000000000000e1e0dfdee1e0dfde (s31: -5.18525e+20) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xd5d4d3d2d5d4d3d2 (-2.925e+13, -2.925e+13)
+#            d29:                 0xd9d8d7d6d9d8d7d6 (-7.629e+15, -7.629e+15)
+#            d30:                 0xdddcdbdadddcdbda (-1.989e+18, -1.989e+18)
+#            d31:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#                                          ╙───────╨─ 0xe1e0dfde'dddcdbda'd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffe82b		ld4r {v11.2s, v12.2s, v13.2s, v14.2s}, [x1], #16
-#   v11: 0x0000000000000000d4d3d2d1d4d3d2d1 (s11: -7.27820e+12) <- 0x~~~~~~~~~~~~~~~~
-#   v12: 0x0000000000000000d8d7d6d5d8d7d6d5 (s12: -1.89854e+15) <- 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0000000000000000dcdbdad9dcdbdad9 (s13: -4.95069e+17) <- 0x~~~~~~~~~~~~~~~~
-#   v14: 0x0000000000000000e0dfdedde0dfdedd (s14: -1.29053e+20) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xd4d3d2d1d4d3d2d1 (-7.278e+12, -7.278e+12)
+#            d12:                 0xd8d7d6d5d8d7d6d5 (-1.899e+15, -1.899e+15)
+#            d13:                 0xdcdbdad9dcdbdad9 (-4.951e+17, -4.951e+17)
+#            d14:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#                                          ╙───────╨─ 0xe0dfdedd'dcdbdad9'd8d7d6d5'd4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60e413		ld4r {v19.4h, v20.4h, v21.4h, v22.4h}, [x0]
-#   v19: 0x0000000000000000ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000002000200020002 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x00000000000000000085008500850085 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x0000000000000000ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d20:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d21:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            d22:                 0xff00ff00ff00ff00 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2e436		ld4r {v22.4h, v23.4h, v24.4h, v25.4h}, [x1], x2
-#   v22: 0x0000000000000000e2e1e2e1e2e1e2e1 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x0000000000000000e4e3e4e3e4e3e4e3 <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x0000000000000000e6e5e6e5e6e5e6e5 <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x0000000000000000e8e7e8e7e8e7e8e7 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xe2e1e2e1e2e1e2e1 (-880.5, -880.5, -880.5, -880.5)
+#            d23:                 0xe4e3e4e3e4e3e4e3 (-1251., -1251., -1251., -1251.)
+#            d24:                 0xe6e5e6e5e6e5e6e5 (-1765., -1765., -1765., -1765.)
+#            d25:                 0xe8e7e8e7e8e7e8e7 (-2510., -2510., -2510., -2510.)
+#                                      ╙───╨───╨───╨─ 0xe8e7'e6e5'e4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffe434		ld4r {v20.4h, v21.4h, v22.4h, v23.4h}, [x1], #8
-#   v20: 0x0000000000000000e1e0e1e0e1e0e1e0 <- 0x~~~~~~~~~~~~~~~~
-#   v21: 0x0000000000000000e3e2e3e2e3e2e3e2 <- 0x~~~~~~~~~~~~~~~~
-#   v22: 0x0000000000000000e5e4e5e4e5e4e5e4 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x0000000000000000e7e6e7e6e7e6e7e6 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xe1e0e1e0e1e0e1e0 (-752.0, -752.0, -752.0, -752.0)
+#            d21:                 0xe3e2e3e2e3e2e3e2 (-1009., -1009., -1009., -1009.)
+#            d22:                 0xe5e4e5e4e5e4e5e4 (-1508., -1508., -1508., -1508.)
+#            d23:                 0xe7e6e7e6e7e6e7e6 (-2022., -2022., -2022., -2022.)
+#                                      ╙───╨───╨───╨─ 0xe7e6'e5e4'e3e2'e1e0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60e810		ld4r {v16.4s, v17.4s, v18.4s, v19.4s}, [x0]
-#   v16: 0x0002ff010002ff010002ff010002ff01 (..., 2.75149e-40, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v17: 0xff000085ff000085ff000085ff000085 (..., -1.70144e+38, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00fffeff00fffeff00fffeff00fffeff (..., 2.35095e-38, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 (..., 0.00000, ...) <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v17: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v18: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#            v19: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ╙───────╨───────╨───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2e839		ld4r {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
-#   v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (..., -5.67986e+26, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0xefeeedecefeeedecefeeedecefeeedec (..., -1.47890e+29, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (..., -3.84962e+31, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (..., -1.00179e+34, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (-5.680e+26, -5.680e+26, -5.680e+26, -5.680e+26)
+#            v26: 0xefeeedecefeeedecefeeedecefeeedec (-1.479e+29, -1.479e+29, -1.479e+29, -1.479e+29)
+#            v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (-3.850e+31, -3.850e+31, -3.850e+31, -3.850e+31)
+#            v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (-1.002e+34, -1.002e+34, -1.002e+34, -1.002e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf7f6f5f4'f3f2f1f0'efeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffe837		ld4r {v23.4s, v24.4s, v25.4s, v26.4s}, [x1], #16
-#   v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (..., -1.41390e+26, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0xeeedecebeeedecebeeedecebeeedeceb (..., -3.68172e+28, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (..., -9.58428e+30, ...) <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (..., -2.49430e+33, ...) <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (-1.414e+26, -1.414e+26, -1.414e+26, -1.414e+26)
+#            v24: 0xeeedecebeeedecebeeedecebeeedeceb (-3.682e+28, -3.682e+28, -3.682e+28, -3.682e+28)
+#            v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (-9.584e+30, -9.584e+30, -9.584e+30, -9.584e+30)
+#            v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (-2.494e+33, -2.494e+33, -2.494e+33, -2.494e+33)
+#                          ╙───────╨───────╨───────╨─ 0xf6f5f4f3'f2f1f0ef'eeedeceb'eae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d60e016		ld4r {v22.8b, v23.8b, v24.8b, v25.8b}, [x0]
-#   v22: 0x00000000000000000101010101010101 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0x0000000000000000ffffffffffffffff <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00000000000000000202020202020202 <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x0101010101010101
+#            d23:                 0xffffffffffffffff
+#            d24:                 0x0202020202020202
+#            d25:                 0x0000000000000000
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0de2e03b		ld4r {v27.8b, v28.8b, v29.8b, v30.8b}, [x1], x2
-#   v27: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000fafafafafafafafa <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xf7f7f7f7f7f7f7f7
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8'f7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dffe03d		ld4r {v29.8b, v30.8b, v31.8b, v0.8b}, [x1], #4
-#   v29: 0x0000000000000000f6f6f6f6f6f6f6f6 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x0000000000000000f7f7f7f7f7f7f7f7 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0x0000000000000000f8f8f8f8f8f8f8f8 <- 0x~~~~~~~~~~~~~~~~
-#    v0: 0x0000000000000000f9f9f9f9f9f9f9f9 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xf6f6f6f6f6f6f6f6
+#            d30:                 0xf7f7f7f7f7f7f7f7
+#            d31:                 0xf8f8f8f8f8f8f8f8
+#             d0:                 0xf9f9f9f9f9f9f9f9
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xf9'f8'f7'f6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d60e41c		ld4r {v28.8h, v29.8h, v30.8h, v31.8h}, [x0]
-#   v28: 0xff01ff01ff01ff01ff01ff01ff01ff01 <- 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00020002000200020002000200020002 <- 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00850085008500850085008500850085 <- 0x~~~~~~~~~~~~~~~~
-#   v31: 0xff00ff00ff00ff00ff00ff00ff00ff00 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v29: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            v30: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            v31: 0xff00ff00ff00ff00ff00ff00ff00ff00 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4de2e439		ld4r {v25.8h, v26.8h, v27.8h, v28.8h}, [x1], x2
-#   v25: 0xfbfafbfafbfafbfafbfafbfafbfafbfa <- 0x~~~~~~~~~~~~~~~~
-#   v26: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc <- 0x~~~~~~~~~~~~~~~~
-#   v27: 0xfffefffefffefffefffefffefffefffe <- 0x~~~~~~~~~~~~~~~~
-#   v28: 0x01000100010001000100010001000100 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#            v26: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v27: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v28: 0x01000100010001000100010001000100 (1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0100'fffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dffe436		ld4r {v22.8h, v23.8h, v24.8h, v25.8h}, [x1], #8
-#   v22: 0xfaf9faf9faf9faf9faf9faf9faf9faf9 <- 0x~~~~~~~~~~~~~~~~
-#   v23: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb <- 0x~~~~~~~~~~~~~~~~
-#   v24: 0xfefdfefdfefdfefdfefdfefdfefdfefd <- 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00ff00ff00ff00ff00ff00ff00ff00ff <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0xfaf9faf9faf9faf9faf9faf9faf9faf9 (-5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04)
+#            v23: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v24: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v25: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4e3a94fd		mla v29.16b, v7.16b, v26.16b
-#   v29: 0x0002000200020002e73aed42f34af952
+#            v29: 0x0002000200020002e73aed42f34af952
 0x~~~~~~~~~~~~~~~~  0eae9486		mla v6.2s, v4.2s, v14.2s
-#    v6: 0x0000000000000000dcbb11e0e6481e68
+#             v6: 0x0000000000000000dcbb11e0e6481e68
 0x~~~~~~~~~~~~~~~~  2f800969		mla v9.2s, v11.2s, v0.s[2]
-#    v9: 0x00000000000000000000000000fffeff
+#             v9: 0x00000000000000000000000000fffeff
 0x~~~~~~~~~~~~~~~~  0e799625		mla v5.4h, v17.4h, v25.4h
-#    v5: 0x0000000000000000a4a2261ba09e2217
+#             v5: 0x0000000000000000a4a2261ba09e2217
 0x~~~~~~~~~~~~~~~~  2f7b00f8		mla v24.4h, v7.4h, v11.h[3]
-#   v24: 0x000000000000000082b3330de36793c1
+#            v24: 0x000000000000000082b3330de36793c1
 0x~~~~~~~~~~~~~~~~  4ea4946c		mla v12.4s, v3.4s, v4.4s
-#   v12: 0x00000000000000006f49f4f5e911f705
+#            v12: 0x00000000000000006f49f4f5e911f705
 0x~~~~~~~~~~~~~~~~  6fa708ea		mla v10.4s, v7.4s, v7.s[3]
-#   v10: 0x00000000000000001700000000000000
+#            v10: 0x00000000000000001700000000000000
 0x~~~~~~~~~~~~~~~~  0e299603		mla v3.8b, v16.8b, v9.8b
-#    v3: 0x000000000000000035342d2c25221f1b
+#             v3: 0x000000000000000035342d2c25221f1b
 0x~~~~~~~~~~~~~~~~  4e7296d3		mla v19.8h, v22.8h, v18.8h
-#   v19: 0xfe070c07fe070c07fe070c07fe070c07
+#            v19: 0xfe070c07fe070c07fe070c07fe070c07
 0x~~~~~~~~~~~~~~~~  6f400046		mla v6.8h, v2.8h, v0.h[0]
-#    v6: 0x0000000000000000dcbb11e0e6481e68
+#             v6: 0x0000000000000000dcbb11e0e6481e68
 0x~~~~~~~~~~~~~~~~  6e2b9557		mls v23.16b, v10.16b, v11.16b
-#   v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+#            v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
 0x~~~~~~~~~~~~~~~~  2eb697ee		mls v14.2s, v31.2s, v22.2s
-#   v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+#            v14: 0x0000000000000000d8e1d7ddd8e1d7dd
 0x~~~~~~~~~~~~~~~~  2fa149bc		mls v28.2s, v13.2s, v1.s[3]
-#   v28: 0x00000000000000000100010001000100
+#            v28: 0x00000000000000000100010001000100
 0x~~~~~~~~~~~~~~~~  2e6d9662		mls v2.4h, v19.4h, v13.4h
-#    v2: 0x0000000000000000ac03d811ac03d811
+#             v2: 0x0000000000000000ac03d811ac03d811
 0x~~~~~~~~~~~~~~~~  2f6c49f2		mls v18.4h, v15.4h, v12.h[6]
-#   v18: 0x000000000000000000fffeff00fffeff
+#            v18: 0x000000000000000000fffeff00fffeff
 0x~~~~~~~~~~~~~~~~  6eb09566		mls v6.4s, v11.4s, v16.4s
-#    v6: 0x00000000000000006347100f6cd41c97
+#             v6: 0x00000000000000006347100f6cd41c97
 0x~~~~~~~~~~~~~~~~  6f8a4a17		mls v23.4s, v16.4s, v10.s[2]
-#   v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+#            v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
 0x~~~~~~~~~~~~~~~~  2e3795ba		mls v26.8b, v13.8b, v23.8b
-#   v26: 0x0000000000000000bd4365396d436539
+#            v26: 0x0000000000000000bd4365396d436539
 0x~~~~~~~~~~~~~~~~  6e6c954a		mls v10.8h, v10.8h, v12.8h
-#   v10: 0x00000000000000008800000000000000
+#            v10: 0x00000000000000008800000000000000
 0x~~~~~~~~~~~~~~~~  6f7e480e		mls v14.8h, v0.8h, v14.h[7]
-#   v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+#            v14: 0x0000000000000000d8e1d7ddd8e1d7dd
 0x~~~~~~~~~~~~~~~~  5e070436		mov b22, v1.b[3]
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e1805a7		mov d7, v13.d[1]
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e0a06ba		mov h26, v21.h[2]
-#   v26: 0x0000000000000000000000000000e3e2
+#            v26: 0x0000000000000000000000000000e3e2
 0x~~~~~~~~~~~~~~~~  5e04067a		mov s26, v19.s[0]
-#   v26: 0x000000000000000000000000fe070c07
+#            v26: 0x000000000000000000000000fe070c07
 0x~~~~~~~~~~~~~~~~  4eab1d7a		mov v26.16b, v11.16b
-#   v26: 0x0000000000000000d4d3d2d1d4d3d2d1
+#            v26: 0x0000000000000000d4d3d2d1d4d3d2d1
 0x~~~~~~~~~~~~~~~~  0ea01c14		mov v20.8b, v0.8b
-#   v20: 0x0000000000000000f9f9f9f9f9f9f9f9
+#            v20: 0x0000000000000000f9f9f9f9f9f9f9f9
 0x~~~~~~~~~~~~~~~~  6e1b24d3		mov v19.b[13], v6.b[4]
-#   v19: 0xfe070f07fe070c07fe070c07fe070c07
+#            v19: 0xfe070f07fe070c07fe070c07fe070c07
 0x~~~~~~~~~~~~~~~~  4e1b1e64		mov v4.b[13], w19
-#    v4: 0x00000000000000009b9a999897969594
+#             v4: 0x00000000000000009b9a999897969594
 0x~~~~~~~~~~~~~~~~  6e18050b		mov v11.d[1], v8.d[0]
-#   v11: 0xff0000850002ff01d4d3d2d1d4d3d2d1
+#            v11: 0xff0000850002ff01d4d3d2d1d4d3d2d1
 0x~~~~~~~~~~~~~~~~  4e081fc3		mov v3.d[0], x30
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e12757d		mov v29.h[4], v11.h[7]
-#   v29: 0x000200020002ff00e73aed42f34af952
+#            v29: 0x000200020002ff00e73aed42f34af952
 0x~~~~~~~~~~~~~~~~  4e1a1cc2		mov v2.h[6], w6
-#    v2: 0x0000000c00000000ac03d811ac03d811
+#             v2: 0x0000ffff00000000ac03d811ac03d811
 0x~~~~~~~~~~~~~~~~  6e0444b6		mov v22.s[0], v5.s[2]
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e1c1d18		mov v24.s[3], w8
-#   v24: 0x000000000000000082b3330de36793c1
+#            v24: 0x000000000000000082b3330de36793c1
 0x~~~~~~~~~~~~~~~~  0e1c3c32		mov w18, v1.s[3]
-#   x18: 0x0000000000000000
+#            x18: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  4e083ebc		mov x28, v21.d[0]
-#   x28: 0xe3e2e3e2e3e2e3e2
+#            x28: 0xe3e2e3e2e3e2e3e2
 0x~~~~~~~~~~~~~~~~  2f03e4f8		movi d24, #0xffff0000ffffff
-#   v24: 0x000000000000000000ffff0000ffffff
+#            v24: 0x000000000000000000ffff0000ffffff
 0x~~~~~~~~~~~~~~~~  4f04e41d		movi v29.16b, #0x80
-#   v29: 0x80808080808080808080808080808080
+#            v29: 0x80808080808080808080808080808080
 0x~~~~~~~~~~~~~~~~  6f06e6cc		movi v12.2d, #0xffff00ff00ffff00
-#   v12: 0xffff00ff00ffff00ffff00ff00ffff00
+#            v12: 0xffff00ff00ffff00ffff00ff00ffff00
 0x~~~~~~~~~~~~~~~~  0f07658c		movi v12.2s, #0xec, lsl #24
-#   v12: 0x0000000000000000ec000000ec000000
+#            v12: 0x0000000000000000ec000000ec000000
 0x~~~~~~~~~~~~~~~~  0f02d58a		movi v10.2s, #0x4c, msl #16
-#   v10: 0x0000000000000000004cffff004cffff
+#            v10: 0x0000000000000000004cffff004cffff
 0x~~~~~~~~~~~~~~~~  0f06841a		movi v26.4h, #0xc0, lsl #0
-#   v26: 0x000000000000000000c000c000c000c0
+#            v26: 0x000000000000000000c000c000c000c0
 0x~~~~~~~~~~~~~~~~  4f044718		movi v24.4s, #0x98, lsl #16
-#   v24: 0x00980000009800000098000000980000
+#            v24: 0x00980000009800000098000000980000
 0x~~~~~~~~~~~~~~~~  4f06d7c1		movi v1.4s, #0xde, msl #16
-#    v1: 0x00deffff00deffff00deffff00deffff
+#             v1: 0x00deffff00deffff00deffff00deffff
 0x~~~~~~~~~~~~~~~~  0f02e5b5		movi v21.8b, #0x4d
-#   v21: 0x00000000000000004d4d4d4d4d4d4d4d
+#            v21: 0x00000000000000004d4d4d4d4d4d4d4d
 0x~~~~~~~~~~~~~~~~  4f03853d		movi v29.8h, #0x69, lsl #0
-#   v29: 0x00690069006900690069006900690069
+#            v29: 0x00690069006900690069006900690069
 0x~~~~~~~~~~~~~~~~  4e319de1		mul v1.16b, v15.16b, v17.16b
-#    v1: 0x4700008e4b00007a4700008e4b00007a
+#             v1: 0x4700008e4b00007a4700008e4b00007a
 0x~~~~~~~~~~~~~~~~  0ebd9e75		mul v21.2s, v19.2s, v29.2s
-#   v21: 0x00000000000000001fc2eedf1fc2eedf
+#            v21: 0x00000000000000001fc2eedf1fc2eedf
 0x~~~~~~~~~~~~~~~~  0f8380b3		mul v19.2s, v5.2s, v3.s[0]
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e629d7d		mul v29.4h, v11.4h, v2.4h
-#   v29: 0x0000000000000000427957e1427957e1
+#            v29: 0x0000000000000000427957e1427957e1
 0x~~~~~~~~~~~~~~~~  0f4080e2		mul v2.4h, v7.4h, v0.h[0]
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb09f59		mul v25.4s, v26.4s, v16.4s
-#   v25: 0x000000000000000042ff40c042ff40c0
+#            v25: 0x000000000000000042ff40c042ff40c0
 0x~~~~~~~~~~~~~~~~  4f8f88da		mul v26.4s, v6.4s, v15.s[2]
-#   v26: 0x00000000000000009d2fa76ed8a575fe
+#            v26: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  0e3f9deb		mul v11.8b, v15.8b, v31.8b
-#   v11: 0x0000000000000000470049004b004d00
+#            v11: 0x0000000000000000470049004b004d00
 0x~~~~~~~~~~~~~~~~  4e6f9ff4		mul v20.8h, v31.8h, v15.8h
-#   v20: 0x48004a004c004e0048004a004c004e00
+#            v20: 0x48004a004c004e0048004a004c004e00
 0x~~~~~~~~~~~~~~~~  4f4988bd		mul v29.8h, v5.8h, v9.h[4]
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e205aad		mvn v13.16b, v21.16b
-#   v13: 0xffffffffffffffffe03d1120e03d1120
+#            v13: 0xffffffffffffffffe03d1120e03d1120
 0x~~~~~~~~~~~~~~~~  2e205a7c		mvn v28.8b, v19.8b
-#   v28: 0x0000000000000000ffffffffffffffff
+#            v28: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2f052719		mvni v25.2s, #0xb8, lsl #8
-#   v25: 0x0000000000000000ffff47ffffff47ff
+#            v25: 0x0000000000000000ffff47ffffff47ff
 0x~~~~~~~~~~~~~~~~  2f03d591		mvni v17.2s, #0x6c, msl #16
-#   v17: 0x0000000000000000ff930000ff930000
+#            v17: 0x0000000000000000ff930000ff930000
 0x~~~~~~~~~~~~~~~~  2f02851d		mvni v29.4h, #0x48, lsl #0
-#   v29: 0x0000000000000000ffb7ffb7ffb7ffb7
+#            v29: 0x0000000000000000ffb7ffb7ffb7ffb7
 0x~~~~~~~~~~~~~~~~  6f034754		mvni v20.4s, #0x7a, lsl #16
-#   v20: 0xff85ffffff85ffffff85ffffff85ffff
+#            v20: 0xff85ffffff85ffffff85ffffff85ffff
 0x~~~~~~~~~~~~~~~~  6f00c7c0		mvni v0.4s, #0x1e, msl #8
-#    v0: 0xffffe100ffffe100ffffe100ffffe100
+#             v0: 0xffffe100ffffe100ffffe100ffffe100
 0x~~~~~~~~~~~~~~~~  6f0187df		mvni v31.8h, #0x3e, lsl #0
-#   v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
+#            v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
 0x~~~~~~~~~~~~~~~~  7ee0b979		neg d25, d11
-#   v25: 0x0000000000000000b8ffb6ffb4ffb300
+#            v25: 0x0000000000000000b8ffb6ffb4ffb300
 0x~~~~~~~~~~~~~~~~  6e20b924		neg v4.16b, v9.16b
-#    v4: 0x00000000000000000000000000010201
+#             v4: 0x00000000000000000000000000010201
 0x~~~~~~~~~~~~~~~~  6ee0bb2b		neg v11.2d, v25.2d
-#   v11: 0x0000000000000000470049004b004d00
+#            v11: 0x0000000000000000470049004b004d00
 0x~~~~~~~~~~~~~~~~  2ea0ba47		neg v7.2s, v18.2s
-#    v7: 0x0000000000000000ff000101ff000101
+#             v7: 0x0000000000000000ff000101ff000101
 0x~~~~~~~~~~~~~~~~  2e60b9e7		neg v7.4h, v15.4h
-#    v7: 0x00000000000000004648484a4a4c4c4e
+#             v7: 0x00000000000000004648484a4a4c4c4e
 0x~~~~~~~~~~~~~~~~  6ea0ba51		neg v17.4s, v18.4s
-#   v17: 0x0000000000000000ff000101ff000101
+#            v17: 0x0000000000000000ff000101ff000101
 0x~~~~~~~~~~~~~~~~  2e20ba34		neg v20.8b, v17.8b
-#   v20: 0x00000000000000000100ffff0100ffff
+#            v20: 0x00000000000000000100ffff0100ffff
 0x~~~~~~~~~~~~~~~~  6e60b960		neg v0.8h, v11.8h
-#    v0: 0x0000000000000000b900b700b500b300
+#             v0: 0x0000000000000000b900b700b500b300
 0x~~~~~~~~~~~~~~~~  4eff1d6d		orn v13.16b, v11.16b, v31.16b
-#   v13: 0x003e003e003e003e473e493e4b3e4d3e
+#            v13: 0x003e003e003e003e473e493e4b3e4d3e
 0x~~~~~~~~~~~~~~~~  0ef61e16		orn v22.8b, v16.8b, v22.8b
-#   v22: 0x0000000000000000ffffffffffffffff
+#            v22: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4eb71e31		orr v17.16b, v17.16b, v23.16b
-#   v17: 0xfcfbfcfbfcfbfcfbfffbfdfbfffbfdfb
+#            v17: 0xfcfbfcfbfcfbfcfbfffbfdfbfffbfdfb
 0x~~~~~~~~~~~~~~~~  0f071468		orr v8.2s, #0xe3, lsl #0
-#    v8: 0x0000000000000000ff0000e70002ffe3
+#             v8: 0x0000000000000000ff0000e70002ffe3
 0x~~~~~~~~~~~~~~~~  0f04b6eb		orr v11.4h, #0x97, lsl #8
-#   v11: 0x0000000000000000d700df00df00df00
+#            v11: 0x0000000000000000d700df00df00df00
 0x~~~~~~~~~~~~~~~~  4f051567		orr v7.4s, #0xab, lsl #0
-#    v7: 0x000000ab000000ab464848eb4a4c4cef
+#             v7: 0x000000ab000000ab464848eb4a4c4cef
 0x~~~~~~~~~~~~~~~~  0ea31c88		orr v8.8b, v4.8b, v3.8b
-#    v8: 0x00000000000000000000000000010201
+#             v8: 0x00000000000000000000000000010201
 0x~~~~~~~~~~~~~~~~  4f05b61f		orr v31.8h, #0xb0, lsl #8
-#   v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
+#            v31: 0xffc1ffc1ffc1ffc1ffc1ffc1ffc1ffc1
 0x~~~~~~~~~~~~~~~~  6e379e4b		pmul v11.16b, v18.16b, v23.16b
-#   v11: 0x000000000000000000a9a8a900a9a8a9
+#            v11: 0x000000000000000000a9a8a900a9a8a9
 0x~~~~~~~~~~~~~~~~  2e259f08		pmul v8.8b, v24.8b, v5.8b
-#    v8: 0x00000000000000000030000000100000
+#             v8: 0x00000000000000000030000000100000
 0x~~~~~~~~~~~~~~~~  0e36e258		pmull v24.8h, v18.8b, v22.8b
-#   v24: 0x0000555555aa55550000555555aa5555
+#            v24: 0x0000555555aa55550000555555aa5555
 0x~~~~~~~~~~~~~~~~  4e35e06d		pmull2 v13.8h, v3.16b, v21.16b
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb54156		raddhn v22.2s, v10.2d, v21.2d
-#   v22: 0x000000000000000000000000200feede
+#            v22: 0x000000000000000000000000200feede
 0x~~~~~~~~~~~~~~~~  2e6d41a5		raddhn v5.4h, v13.4s, v13.4s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3a422a		raddhn v10.8b, v17.8h, v26.8h
-#   v10: 0x0000000000000000fdfdfdfd9da5d974
+#            v10: 0x0000000000000000fdfdfdfd9da5d974
 0x~~~~~~~~~~~~~~~~  6e2d43a9		raddhn2 v9.16b, v29.8h, v13.8h
-#    v9: 0x00000000000000000000000000fffeff
+#             v9: 0x00000000000000000000000000fffeff
 0x~~~~~~~~~~~~~~~~  6eba42fb		raddhn2 v27.4s, v23.2d, v26.2d
-#   v27: 0xfcfbfcfc8e2ba46bfffefffefffefffe
+#            v27: 0xfcfbfcfc8e2ba46bfffefffefffefffe
 0x~~~~~~~~~~~~~~~~  6e6743a0		raddhn2 v0.8h, v29.4s, v7.4s
-#    v0: 0x0000000046004a04b900b700b500b300
+#             v0: 0x0000000046004a04b900b700b500b300
 0x~~~~~~~~~~~~~~~~  6e6059f6		rbit v22.16b, v15.16b
-#   v22: 0x9d1ded6dad2dcd4d9d1ded6dad2dcd4d
+#            v22: 0x9d1ded6dad2dcd4d9d1ded6dad2dcd4d
 0x~~~~~~~~~~~~~~~~  2e60587e		rbit v30.8b, v3.8b
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e201b7f		rev16 v31.16b, v27.16b
-#   v31: 0xfbfcfcfc2b8e6ba4fefffefffefffeff
+#            v31: 0xfbfcfcfc2b8e6ba4fefffefffefffeff
 0x~~~~~~~~~~~~~~~~  0e201b4c		rev16 v12.8b, v26.8b
-#   v12: 0x00000000000000002f9d6ea7a5d8fe75
+#            v12: 0x00000000000000002f9d6ea7a5d8fe75
 0x~~~~~~~~~~~~~~~~  6e200885		rev32 v5.16b, v4.16b
-#    v5: 0x00000000000000000000000001020100
+#             v5: 0x00000000000000000000000001020100
 0x~~~~~~~~~~~~~~~~  2e600b50		rev32 v16.4h, v26.4h
-#   v16: 0x0000000000000000a76e9d2f75fed8a5
+#            v16: 0x0000000000000000a76e9d2f75fed8a5
 0x~~~~~~~~~~~~~~~~  2e200874		rev32 v20.8b, v3.8b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e600b94		rev32 v20.8h, v28.8h
-#   v20: 0x0000000000000000ffffffffffffffff
+#            v20: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e200a69		rev64 v9.16b, v19.16b
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea00a05		rev64 v5.2s, v16.2s
-#    v5: 0x000000000000000075fed8a5a76e9d2f
+#             v5: 0x000000000000000075fed8a5a76e9d2f
 0x~~~~~~~~~~~~~~~~  0e600be7		rev64 v7.4h, v31.4h
-#    v7: 0x0000000000000000fefffefffefffeff
+#             v7: 0x0000000000000000fefffefffefffeff
 0x~~~~~~~~~~~~~~~~  4ea00b4f		rev64 v15.4s, v26.4s
-#   v15: 0x0000000000000000d8a575fe9d2fa76e
+#            v15: 0x0000000000000000d8a575fe9d2fa76e
 0x~~~~~~~~~~~~~~~~  0e200939		rev64 v25.8b, v9.8b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6008ab		rev64 v11.8h, v5.8h
-#   v11: 0x00000000000000009d2fa76ed8a575fe
+#            v11: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  0f3f8db2		rshrn v18.2s, v13.2d, #1
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f1e8fd9		rshrn v25.4h, v30.4s, #2
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f088d2d		rshrn v13.8b, v9.8h, #8
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f088cc3		rshrn2 v3.16b, v6.8h, #8
-#    v3: 0x0000000063106d1d0000000000000000
+#             v3: 0x0000000063106d1d0000000000000000
 0x~~~~~~~~~~~~~~~~  4f278fa0		rshrn2 v0.4s, v29.2d, #25
-#    v0: 0x00000000dbffdc00b900b700b500b300
+#             v0: 0x00000000dbffdc00b900b700b500b300
 0x~~~~~~~~~~~~~~~~  4f118f5b		rshrn2 v27.8h, v26.4s, #15
-#   v27: 0x000000003a5fb14bfffefffefffefffe
+#            v27: 0x000000003a5fb14bfffefffefffefffe
 0x~~~~~~~~~~~~~~~~  2ea4632f		rsubhn v15.2s, v25.2d, v4.2d
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e636137		rsubhn v23.4h, v9.4s, v3.4s
-#   v23: 0x000000000000000000009cf000000000
+#            v23: 0x000000000000000000009cf000000000
 0x~~~~~~~~~~~~~~~~  2e3863c6		rsubhn v6.8b, v30.8h, v24.8h
-#    v6: 0x000000000000000000abaaab00abaaab
+#             v6: 0x000000000000000000abaaab00abaaab
 0x~~~~~~~~~~~~~~~~  6e346304		rsubhn2 v4.16b, v24.8h, v20.8h
-#    v4: 0x00555655005556550000000000010201
+#             v4: 0x00555655005556550000000000010201
 0x~~~~~~~~~~~~~~~~  6eb662e1		rsubhn2 v1.4s, v23.2d, v22.2d
-#    v1: 0x62e2129262e2af824700008e4b00007a
+#             v1: 0x62e2129262e2af824700008e4b00007a
 0x~~~~~~~~~~~~~~~~  6e746053		rsubhn2 v19.8h, v2.4s, v20.4s
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e397d3c		saba v28.16b, v9.16b, v25.16b
-#   v28: 0x0000000000000000ffffffffffffffff
+#            v28: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  0eb47f89		saba v9.2s, v28.2s, v20.2s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e767ed1		saba v17.4h, v22.4h, v22.4h
-#   v17: 0x0000000000000000fffbfdfbfffbfdfb
+#            v17: 0x0000000000000000fffbfdfbfffbfdfb
 0x~~~~~~~~~~~~~~~~  4ebb7cbd		saba v29.4s, v5.4s, v27.4s
-#   v29: 0x000000003a5fb14b75b7d85e58486286
+#            v29: 0x000000003a5fb14b75b7d85e58486286
 0x~~~~~~~~~~~~~~~~  0e327eb4		saba v20.8b, v21.8b, v18.8b
-#   v20: 0x00000000000000001e3d11201e3d1120
+#            v20: 0x00000000000000001e3d11201e3d1120
 0x~~~~~~~~~~~~~~~~  4e7e7e3b		saba v27.8h, v17.8h, v30.8h
-#   v27: 0x000000003a5fb14b0003020300030203
+#            v27: 0x000000003a5fb14b0003020300030203
 0x~~~~~~~~~~~~~~~~  0ea751b4		sabal v20.2d, v13.2s, v7.2s
-#   v20: 0x00000000010001011e3d11201f3d1221
+#            v20: 0x00000000010001011e3d11201f3d1221
 0x~~~~~~~~~~~~~~~~  0e645184		sabal v4.4s, v12.4h, v4.4h
-#    v4: 0x005585f20055c4fc00005a290001058d
+#             v4: 0x005585f20055c4fc00005a290001058d
 0x~~~~~~~~~~~~~~~~  0e345317		sabal v23.8h, v24.8b, v20.8b
-#   v23: 0x001e003d0044003500369d8300430034
+#            v23: 0x001e003d0044003500369d8300430034
 0x~~~~~~~~~~~~~~~~  4eb252ba		sabal2 v26.2d, v21.4s, v18.4s
-#   v26: 0x00000000000000009d2fa76ed8a575fe
+#            v26: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  4e68539b		sabal2 v27.4s, v28.8h, v8.8h
-#   v27: 0x000000003a5fb14b0003020300030203
+#            v27: 0x000000003a5fb14b0003020300030203
 0x~~~~~~~~~~~~~~~~  4e35520c		sabal2 v12.8h, v16.16b, v21.16b
-#   v12: 0x00000000000000002f9d6ea7a5d8fe75
+#            v12: 0x00000000000000002f9d6ea7a5d8fe75
 0x~~~~~~~~~~~~~~~~  4e2d75e0		sabd v0.16b, v15.16b, v13.16b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ebe74ef		sabd v15.2s, v7.2s, v30.2s
-#   v15: 0x00000000000000000100010101000101
+#            v15: 0x00000000000000000100010101000101
 0x~~~~~~~~~~~~~~~~  0e6c7631		sabd v17.4h, v17.4h, v12.4h
-#   v17: 0x00000000000000002fa270ac5a23007a
+#            v17: 0x00000000000000002fa270ac5a23007a
 0x~~~~~~~~~~~~~~~~  4eb67487		sabd v7.4s, v4.4s, v22.4s
-#    v7: 0x633798855327f7af62e26cbc52d33840
+#             v7: 0x633798855327f7af62e26cbc52d33840
 0x~~~~~~~~~~~~~~~~  0e3a7477		sabd v23.8b, v3.8b, v26.8b
-#   v23: 0x0000000000000000632f596e285b7502
+#            v23: 0x0000000000000000632f596e285b7502
 0x~~~~~~~~~~~~~~~~  4e657794		sabd v20.8h, v28.8h, v5.8h
-#   v20: 0x000000000000000075ff275a589162d0
+#            v20: 0x000000000000000075ff275a589162d0
 0x~~~~~~~~~~~~~~~~  0eb472db		sabdl v27.2d, v22.2s, v20.2s
-#   v27: 0x00000000d8e139ed00000000ab639583
+#            v27: 0x00000000d8e139ed00000000ab639583
 0x~~~~~~~~~~~~~~~~  0e77729f		sabdl v31.4s, v20.4h, v23.4h
-#   v31: 0x000012d0000032140000303600001232
+#            v31: 0x000012d0000032140000303600001232
 0x~~~~~~~~~~~~~~~~  0e3b7280		sabdl v0.8h, v20.8b, v27.8b
-#    v0: 0x007500010027005a00ad00d200cd004d
+#             v0: 0x007500010027005a00ad00d200cd004d
 0x~~~~~~~~~~~~~~~~  4ea3717f		sabdl2 v31.2d, v11.4s, v3.4s
-#   v31: 0x00000000000000000000000063106d1d
+#            v31: 0x00000000000000000000000063106d1d
 0x~~~~~~~~~~~~~~~~  4e7b717a		sabdl2 v26.4s, v11.8h, v27.8h
-#   v26: 0x00000000000000000000271f000039ed
+#            v26: 0x00000000000000000000271f000039ed
 0x~~~~~~~~~~~~~~~~  4e327106		sabdl2 v6.8h, v8.16b, v18.16b
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea06b48		sadalp v8.1d, v26.2s
-#    v8: 0x0000000000000000003000000010610c
+#             v8: 0x0000000000000000003000000010610c
 0x~~~~~~~~~~~~~~~~  4ea06b4c		sadalp v12.2d, v26.4s
-#   v12: 0x00000000000000002f9d6ea7a5d95f81
+#            v12: 0x00000000000000002f9d6ea7a5d95f81
 0x~~~~~~~~~~~~~~~~  0e606b4c		sadalp v12.2s, v26.4h
-#   v12: 0x00000000000000002f9d95c6a5d9996e
+#            v12: 0x00000000000000002f9d95c6a5d9996e
 0x~~~~~~~~~~~~~~~~  0e206824		sadalp v4.4h, v1.8b
-#    v4: 0x0000000000000000004759b7004c0607
+#             v4: 0x0000000000000000004759b7004c0607
 0x~~~~~~~~~~~~~~~~  4e606a2f		sadalp v15.4s, v17.8h
-#   v15: 0x00000000000000000100a14f01005b9e
+#            v15: 0x00000000000000000100a14f01005b9e
 0x~~~~~~~~~~~~~~~~  4e206b35		sadalp v21.8h, v25.16b
-#   v21: 0x00000000000000001fc2eedf1fc2eedf
+#            v21: 0x00000000000000001fc2eedf1fc2eedf
 0x~~~~~~~~~~~~~~~~  0eae0145		saddl v5.2d, v10.2s, v14.2s
-#    v5: 0xffffffffd6dfd5daffffffff7687b151
+#             v5: 0xffffffffd6dfd5daffffffff7687b151
 0x~~~~~~~~~~~~~~~~  0e6f0072		saddl v18.4s, v3.4h, v15.4h
-#   v18: 0x00000100ffffa14f0000010000005b9e
+#            v18: 0x00000100ffffa14f0000010000005b9e
 0x~~~~~~~~~~~~~~~~  0e37004f		saddl v15.8h, v2.8b, v23.8b
-#   v15: 0x0063002f0059006e0028005b00750002
+#            v15: 0x0063002f0059006e0028005b00750002
 0x~~~~~~~~~~~~~~~~  4ebb0210		saddl2 v16.2d, v16.4s, v27.4s
-#   v16: 0x0000000000000000ffffffffd8e139ed
+#            v16: 0x0000000000000000ffffffffd8e139ed
 0x~~~~~~~~~~~~~~~~  4e600306		saddl2 v6.4s, v24.8h, v0.8h
-#    v6: 0x0000007500005556000055d1000055af
+#             v6: 0x0000007500005556000055d1000055af
 0x~~~~~~~~~~~~~~~~  4e3c0287		saddl2 v7.8h, v20.16b, v28.16b
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea02b2a		saddlp v10.1d, v25.2s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea02a0f		saddlp v15.2d, v16.4s
-#   v15: 0x0000000000000000ffffffffd8e139ec
+#            v15: 0x0000000000000000ffffffffd8e139ec
 0x~~~~~~~~~~~~~~~~  0e602952		saddlp v18.2s, v10.4h
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e202b5d		saddlp v29.4h, v26.8b
-#   v29: 0x00000000000000000000004600000026
+#            v29: 0x00000000000000000000004600000026
 0x~~~~~~~~~~~~~~~~  4e60282a		saddlp v10.4s, v1.8h
-#   v10: 0x00007574000012640000478e00004b7a
+#            v10: 0x00007574000012640000478e00004b7a
 0x~~~~~~~~~~~~~~~~  4e202aa0		saddlp v0.8h, v21.16b
-#    v0: 0x0000000000000000ffe1ffcdffe1ffcd
+#             v0: 0x0000000000000000ffe1ffcdffe1ffcd
 0x~~~~~~~~~~~~~~~~  4eb038ec		saddlv d12, v7.4s
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e303b8e		saddlv h14, v28.16b
-#   v14: 0x0000000000000000000000000000fff8
+#            v14: 0x0000000000000000000000000000fff8
 0x~~~~~~~~~~~~~~~~  0e303bde		saddlv h30, v30.8b
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e70387b		saddlv s27, v3.4h
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e703a10		saddlv s16, v16.8h
-#   v16: 0x000000000000000000000000000012cc
+#            v16: 0x000000000000000000000000000012cc
 0x~~~~~~~~~~~~~~~~  0eb21178		saddw v24.2d, v11.2d, v18.2s
-#   v24: 0x00000000000000009d2fa76ed8a575fe
+#            v24: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  0e66118d		saddw v13.4s, v12.4s, v6.4h
-#   v13: 0x00000000000055d100000000000055af
+#            v13: 0x00000000000055d100000000000055af
 0x~~~~~~~~~~~~~~~~  0e271273		saddw v19.8h, v19.8h, v7.8b
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eba113b		saddw2 v27.2d, v9.2d, v26.4s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7512f3		saddw2 v19.4s, v23.4s, v21.8h
-#   v19: 0x0000000000000000632f596e285b7502
+#            v19: 0x0000000000000000632f596e285b7502
 0x~~~~~~~~~~~~~~~~  4e3e132f		saddw2 v15.8h, v25.8h, v30.16b
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e290487		shadd v7.16b, v4.16b, v9.16b
-#    v7: 0x000000000000000000232cdb00260303
+#             v7: 0x000000000000000000232cdb00260303
 0x~~~~~~~~~~~~~~~~  0eb8073d		shadd v29.2s, v25.2s, v24.2s
-#   v29: 0x0000000000000000ce97d3b7ec52baff
+#            v29: 0x0000000000000000ce97d3b7ec52baff
 0x~~~~~~~~~~~~~~~~  0e6d055f		shadd v31.4h, v10.4h, v13.4h
-#   v31: 0x0000000000000000000023c700005094
+#            v31: 0x0000000000000000000023c700005094
 0x~~~~~~~~~~~~~~~~  4ea80615		shadd v21.4s, v16.4s, v8.4s
-#   v21: 0x000000000000000000180000000839ec
+#            v21: 0x000000000000000000180000000839ec
 0x~~~~~~~~~~~~~~~~  0e3607ae		shadd v14.8b, v29.8b, v22.8b
-#   v14: 0x0000000000000000b5dae012cc3fc326
+#            v14: 0x0000000000000000b5dae012cc3fc326
 0x~~~~~~~~~~~~~~~~  4e740713		shadd v19.8h, v24.8h, v20.8h
-#   v19: 0x00000000000000000997e764189b6c67
+#            v19: 0x00000000000000000997e764189b6c67
 0x~~~~~~~~~~~~~~~~  5f575736		shl d22, d25, #23
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0f5625		shl v5.16b, v17.16b, #7
-#    v5: 0x00000000000000008000000000800000
+#             v5: 0x00000000000000008000000000800000
 0x~~~~~~~~~~~~~~~~  4f555482		shl v2.2d, v4.2d, #21
-#    v2: 0x000000000000000036e00980c0e00000
+#             v2: 0x000000000000000036e00980c0e00000
 0x~~~~~~~~~~~~~~~~  0f3a5464		shl v4.2s, v3.2s, #26
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f185783		shl v3.4h, v28.4h, #8
-#    v3: 0x0000000000000000ff00ff00ff00ff00
+#             v3: 0x0000000000000000ff00ff00ff00ff00
 0x~~~~~~~~~~~~~~~~  4f3857e4		shl v4.4s, v31.4s, #24
-#    v4: 0x0000000000000000c700000094000000
+#             v4: 0x0000000000000000c700000094000000
 0x~~~~~~~~~~~~~~~~  0f0a5612		shl v18.8b, v16.8b, #2
-#   v18: 0x00000000000000000000000000004830
+#            v18: 0x00000000000000000000000000004830
 0x~~~~~~~~~~~~~~~~  4f135560		shl v0.8h, v11.8h, #3
-#    v0: 0x0000000000000000e9783b70c528aff0
+#             v0: 0x0000000000000000e9783b70c528aff0
 0x~~~~~~~~~~~~~~~~  2ea13b05		shll v5.2d, v24.2s, #32
-#    v5: 0x9d2fa76e00000000d8a575fe00000000
+#             v5: 0x9d2fa76e00000000d8a575fe00000000
 0x~~~~~~~~~~~~~~~~  2e613a9a		shll v26.4s, v20.4h, #16
-#   v26: 0x75ff0000275a00005891000062d00000
+#            v26: 0x75ff0000275a00005891000062d00000
 0x~~~~~~~~~~~~~~~~  2e213925		shll v5.8h, v9.8b, #8
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea13b95		shll2 v21.2d, v28.4s, #32
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e613836		shll2 v22.4s, v1.8h, #16
-#   v22: 0x62e200001292000062e20000af820000
+#            v22: 0x62e200001292000062e20000af820000
 0x~~~~~~~~~~~~~~~~  6e213b3e		shll2 v30.8h, v25.16b, #8
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f248425		shrn v5.2s, v1.2d, #28
-#    v5: 0x00000000000000002e212926700008e4
+#             v5: 0x00000000000000002e212926700008e4
 0x~~~~~~~~~~~~~~~~  0f19865d		shrn v29.4h, v18.4s, #7
-#   v29: 0x00000000000000000000000000000090
+#            v29: 0x00000000000000000000000000000090
 0x~~~~~~~~~~~~~~~~  0f0e87b1		shrn v17.8b, v29.8h, #2
-#   v17: 0x00000000000000000000000000000024
+#            v17: 0x00000000000000000000000000000024
 0x~~~~~~~~~~~~~~~~  4f0d87c5		shrn2 v5.16b, v30.8h, #3
-#    v5: 0x00000000000000002e212926700008e4
+#             v5: 0x00000000000000002e212926700008e4
 0x~~~~~~~~~~~~~~~~  4f3f8438		shrn2 v24.4s, v1.2d, #1
-#   v24: 0x317157c12580003d9d2fa76ed8a575fe
+#            v24: 0x317157c12580003d9d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  4f1085c5		shrn2 v5.8h, v14.4s, #16
-#    v5: 0x00000000b5dacc3f2e212926700008e4
+#             v5: 0x00000000b5dacc3f2e212926700008e4
 0x~~~~~~~~~~~~~~~~  4e3726de		shsub v30.16b, v22.16b, v23.16b
-#   v30: 0x31f1000009c90000ffd9d3c9c393c5ff
+#            v30: 0x31f1000009c90000ffd9d3c9c393c5ff
 0x~~~~~~~~~~~~~~~~  0eb92776		shsub v22.2s, v27.2s, v25.2s
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6126cd		shsub v13.4h, v22.4h, v1.4h
-#   v13: 0x0000000000000000dc80ffb9da80ffc3
+#            v13: 0x0000000000000000dc80ffb9da80ffc3
 0x~~~~~~~~~~~~~~~~  4eb7250a		shsub v10.4s, v8.4s, v23.4s
-#   v10: 0x0000000000000000ce805349ebda7605
+#            v10: 0x0000000000000000ce805349ebda7605
 0x~~~~~~~~~~~~~~~~  0e3f2526		shsub v6.8b, v9.8b, v31.8b
-#    v6: 0x00000000000000000000ee1c0000d836
+#             v6: 0x00000000000000000000ee1c0000d836
 0x~~~~~~~~~~~~~~~~  4e6827e8		shsub v8.8h, v31.8h, v8.8h
-#    v8: 0x0000000000000000ffe811e3fff8f7c4
+#             v8: 0x0000000000000000ffe811e3fff8f7c4
 0x~~~~~~~~~~~~~~~~  7f5457b3		sli d19, d29, #20
-#   v19: 0x000000000000000000000000090b6c67
+#            v19: 0x000000000000000000000000090b6c67
 0x~~~~~~~~~~~~~~~~  6f085709		sli v9.16b, v24.16b, #0
-#    v9: 0x317157c12580003d9d2fa76ed8a575fe
+#             v9: 0x317157c12580003d9d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  6f4a5536		sli v22.2d, v9.2d, #10
-#   v22: 0xc55f04960000f400be9dbb6295d7f800
+#            v22: 0xc55f04960000f400be9dbb6295d7f800
 0x~~~~~~~~~~~~~~~~  2f34576b		sli v11.2s, v27.2s, #20
-#   v11: 0x0000000000000000000fa76e000575fe
+#            v11: 0x0000000000000000000fa76e000575fe
 0x~~~~~~~~~~~~~~~~  2f1555f0		sli v16.4h, v15.4h, #5
-#   v16: 0x0000000000000000000000000000000c
+#            v16: 0x0000000000000000000000000000000c
 0x~~~~~~~~~~~~~~~~  6f395508		sli v8.4s, v8.4s, #25
-#    v8: 0x0000000000000000c7e811e389f8f7c4
+#             v8: 0x0000000000000000c7e811e389f8f7c4
 0x~~~~~~~~~~~~~~~~  2f0857ca		sli v10.8b, v30.8b, #0
-#   v10: 0x0000000000000000ffd9d3c9c393c5ff
+#            v10: 0x0000000000000000ffd9d3c9c393c5ff
 0x~~~~~~~~~~~~~~~~  6f165787		sli v7.8h, v28.8h, #6
-#    v7: 0x0000000000000000ffe3ffdbffe6ffc3
+#             v7: 0x0000000000000000ffe3ffdbffe6ffc3
 0x~~~~~~~~~~~~~~~~  4e216512		smax v18.16b, v8.16b, v1.16b
-#   v18: 0x6200120062000000470011e34b00007a
+#            v18: 0x6200120062000000470011e34b00007a
 0x~~~~~~~~~~~~~~~~  0ea164be		smax v30.2s, v5.2s, v1.2s
-#   v30: 0x00000000000000004700008e700008e4
+#            v30: 0x00000000000000004700008e700008e4
 0x~~~~~~~~~~~~~~~~  0e736731		smax v17.4h, v25.4h, v19.4h
-#   v17: 0x000000000000000000000000090b6c67
+#            v17: 0x000000000000000000000000090b6c67
 0x~~~~~~~~~~~~~~~~  4ebf6701		smax v1.4s, v24.4s, v31.4s
-#    v1: 0x317157c12580003d000023c700005094
+#             v1: 0x317157c12580003d000023c700005094
 0x~~~~~~~~~~~~~~~~  0e386711		smax v17.8b, v24.8b, v24.8b
-#   v17: 0x00000000000000009d2fa76ed8a575fe
+#            v17: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  4e6a674b		smax v11.8h, v26.8h, v10.8h
-#   v11: 0x75ff0000275a00005891000062d00000
+#            v11: 0x75ff0000275a00005891000062d00000
 0x~~~~~~~~~~~~~~~~  4e27a5cc		smaxp v12.16b, v14.16b, v7.16b
-#   v12: 0x00000000ffffffff00000000da123f26
+#            v12: 0x00000000ffffffff00000000da123f26
 0x~~~~~~~~~~~~~~~~  0ea6a71f		smaxp v31.2s, v24.2s, v6.2s
-#   v31: 0x00000000000000000000ee1cd8a575fe
+#            v31: 0x00000000000000000000ee1cd8a575fe
 0x~~~~~~~~~~~~~~~~  0e6aa7aa		smaxp v10.4h, v29.4h, v10.4h
-#   v10: 0x0000000000000000ffd9c5ff00000090
+#            v10: 0x0000000000000000ffd9c5ff00000090
 0x~~~~~~~~~~~~~~~~  4ea7a572		smaxp v18.4s, v11.4s, v7.4s
-#   v18: 0x00000000ffe6ffc375ff000062d00000
+#            v18: 0x00000000ffe6ffc375ff000062d00000
 0x~~~~~~~~~~~~~~~~  0e32a415		smaxp v21.8b, v0.8b, v18.8b
-#   v21: 0x000000000000000075006200787028f0
+#            v21: 0x000000000000000075006200787028f0
 0x~~~~~~~~~~~~~~~~  4e6fa51a		smaxp v26.8h, v8.8h, v15.8h
-#   v26: 0x00000000000000000000000011e3f7c4
+#            v26: 0x00000000000000000000000011e3f7c4
 0x~~~~~~~~~~~~~~~~  4e30a8a4		smaxv b4, v5.16b
-#    v4: 0x00000000000000000000000000000070
+#             v4: 0x00000000000000000000000000000070
 0x~~~~~~~~~~~~~~~~  0e30a817		smaxv b23, v0.8b
-#   v23: 0x00000000000000000000000000000078
+#            v23: 0x00000000000000000000000000000078
 0x~~~~~~~~~~~~~~~~  0e70a806		smaxv h6, v0.4h
-#    v6: 0x00000000000000000000000000003b70
+#             v6: 0x00000000000000000000000000003b70
 0x~~~~~~~~~~~~~~~~  4e70a918		smaxv h24, v8.8h
-#   v24: 0x000000000000000000000000000011e3
+#            v24: 0x000000000000000000000000000011e3
 0x~~~~~~~~~~~~~~~~  4eb0aa03		smaxv s3, v16.4s
-#    v3: 0x0000000000000000000000000000000c
+#             v3: 0x0000000000000000000000000000000c
 0x~~~~~~~~~~~~~~~~  4e326d18		smin v24.16b, v8.16b, v18.16b
-#   v24: 0x00000000ffe6ffc3c7e800e389d0f7c4
+#            v24: 0x00000000ffe6ffc3c7e800e389d0f7c4
 0x~~~~~~~~~~~~~~~~  0eb76d1d		smin v29.2s, v8.2s, v23.2s
-#   v29: 0x0000000000000000c7e811e389f8f7c4
+#            v29: 0x0000000000000000c7e811e389f8f7c4
 0x~~~~~~~~~~~~~~~~  0e756d66		smin v6.4h, v11.4h, v21.4h
-#    v6: 0x00000000000000005891000062d00000
+#             v6: 0x00000000000000005891000062d00000
 0x~~~~~~~~~~~~~~~~  4eaf6ef8		smin v24.4s, v23.4s, v15.4s
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e246e08		smin v8.8b, v16.8b, v4.8b
-#    v8: 0x0000000000000000000000000000000c
+#             v8: 0x0000000000000000000000000000000c
 0x~~~~~~~~~~~~~~~~  4e6a6c2c		smin v12.8h, v1.8h, v10.8h
-#   v12: 0x0000000000000000ffd9c5ff00000090
+#            v12: 0x0000000000000000ffd9c5ff00000090
 0x~~~~~~~~~~~~~~~~  4e3cae4d		sminp v13.16b, v18.16b, v28.16b
-#   v13: 0x00000000ffffffff0000e6c3ff00d000
+#            v13: 0x00000000ffffffff0000e6c3ff00d000
 0x~~~~~~~~~~~~~~~~  0eb0af96		sminp v22.2s, v28.2s, v16.2s
-#   v22: 0x000000000000000000000000ffffffff
+#            v22: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  0e65ad8f		sminp v15.4h, v12.4h, v5.4h
-#   v15: 0x0000000000000000292608e4c5ff0000
+#            v15: 0x0000000000000000292608e4c5ff0000
 0x~~~~~~~~~~~~~~~~  4ea8ae2f		sminp v15.4s, v17.4s, v8.4s
-#   v15: 0x0000000000000000000000009d2fa76e
+#            v15: 0x0000000000000000000000009d2fa76e
 0x~~~~~~~~~~~~~~~~  0e26ac55		sminp v21.8b, v2.8b, v6.8b
-#   v21: 0x00000000000000009100d000e080c000
+#            v21: 0x00000000000000009100d000e080c000
 0x~~~~~~~~~~~~~~~~  4e66ad95		sminp v21.8h, v12.8h, v6.8h
-#   v21: 0x000000000000000000000000c5ff0000
+#            v21: 0x000000000000000000000000c5ff0000
 0x~~~~~~~~~~~~~~~~  4e31a8c8		sminv b8, v6.16b
-#    v8: 0x00000000000000000000000000000091
+#             v8: 0x00000000000000000000000000000091
 0x~~~~~~~~~~~~~~~~  0e31aa46		sminv b6, v18.8b
-#    v6: 0x000000000000000000000000000000d0
+#             v6: 0x000000000000000000000000000000d0
 0x~~~~~~~~~~~~~~~~  0e71a834		sminv h20, v1.4h
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e71aa27		sminv h7, v17.8h
-#    v7: 0x00000000000000000000000000009d2f
+#             v7: 0x00000000000000000000000000009d2f
 0x~~~~~~~~~~~~~~~~  4eb1a895		sminv s21, v4.4s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eb581d8		smlal v24.2d, v14.2s, v21.2s
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f8e287f		smlal v31.2d, v3.2s, v14.s[2]
-#   v31: 0x00000000000000000000ee1cd8a575fe
+#            v31: 0x00000000000000000000ee1cd8a575fe
 0x~~~~~~~~~~~~~~~~  0e758287		smlal v7.4s, v20.4h, v21.4h
-#    v7: 0x00000000000000000000000000009d2f
+#             v7: 0x00000000000000000000000000009d2f
 0x~~~~~~~~~~~~~~~~  0f792213		smlal v19.4s, v16.4h, v9.h[3]
-#   v19: 0x0000000000000000000000000906ca9b
+#            v19: 0x0000000000000000000000000906ca9b
 0x~~~~~~~~~~~~~~~~  0e2181dd		smlal v29.8h, v14.8b, v1.8b
-#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+#            v29: 0x00000000fba0fbfec7e811e376e8e7bc
 0x~~~~~~~~~~~~~~~~  4eb0835e		smlal2 v30.2d, v26.4s, v16.4s
-#   v30: 0x00000000000000004700008e700008e4
+#            v30: 0x00000000000000004700008e700008e4
 0x~~~~~~~~~~~~~~~~  4f8123df		smlal2 v31.2d, v30.4s, v1.s[0]
-#   v31: 0x00000000000000000000ee1cd8a575fe
+#            v31: 0x00000000000000000000ee1cd8a575fe
 0x~~~~~~~~~~~~~~~~  4e6380d1		smlal2 v17.4s, v6.8h, v3.8h
-#   v17: 0x00000000000000009d2fa76ed8a575fe
+#            v17: 0x00000000000000009d2fa76ed8a575fe
 0x~~~~~~~~~~~~~~~~  4f752beb		smlal2 v11.4s, v31.8h, v5.h[7]
-#   v11: 0x75ff0000275a00005891000062d00000
+#            v11: 0x75ff0000275a00005891000062d00000
 0x~~~~~~~~~~~~~~~~  4e3d821e		smlal2 v30.8h, v16.16b, v29.16b
-#   v30: 0x00000000000000004700008e700008e4
+#            v30: 0x00000000000000004700008e700008e4
 0x~~~~~~~~~~~~~~~~  0eb1a281		smlsl v1.2d, v20.2s, v17.2s
-#    v1: 0x317157c12580003d000023c700005094
+#             v1: 0x317157c12580003d000023c700005094
 0x~~~~~~~~~~~~~~~~  0fa5699d		smlsl v29.2d, v12.2s, v5.s[3]
-#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+#            v29: 0x00000000fba0fbfec7e811e376e8e7bc
 0x~~~~~~~~~~~~~~~~  0e61a340		smlsl v0.4s, v26.4h, v1.4h
-#    v0: 0x0000000000000000e9783b70c7c032a0
+#             v0: 0x0000000000000000e9783b70c7c032a0
 0x~~~~~~~~~~~~~~~~  0f5668a3		smlsl v3.4s, v5.4h, v6.h[5]
-#    v3: 0x0000000000000000000000000000000c
+#             v3: 0x0000000000000000000000000000000c
 0x~~~~~~~~~~~~~~~~  0e3aa004		smlsl v4.8h, v0.8b, v26.8b
-#    v4: 0x000000000000000003c9f8c001c2e9f0
+#             v4: 0x000000000000000003c9f8c001c2e9f0
 0x~~~~~~~~~~~~~~~~  4ea5a1ce		smlsl2 v14.2d, v14.4s, v5.4s
-#   v14: 0x0000000000000000b5dae012cc3fc326
+#            v14: 0x0000000000000000b5dae012cc3fc326
 0x~~~~~~~~~~~~~~~~  4fa060af		smlsl2 v15.2d, v5.4s, v0.s[1]
-#   v15: 0x0000000000000000f9797b018bdbc6de
+#            v15: 0x0000000000000000f9797b018bdbc6de
 0x~~~~~~~~~~~~~~~~  4e7fa23d		smlsl2 v29.4s, v17.8h, v31.8h
-#   v29: 0x00000000fba0fbfec7e811e376e8e7bc
+#            v29: 0x00000000fba0fbfec7e811e376e8e7bc
 0x~~~~~~~~~~~~~~~~  4f6969e6		smlsl2 v6.4s, v15.8h, v9.h[6]
-#    v6: 0x000000000000000000000000000000d0
+#             v6: 0x000000000000000000000000000000d0
 0x~~~~~~~~~~~~~~~~  4e2fa1fe		smlsl2 v30.8h, v15.16b, v15.16b
-#   v30: 0x00000000000000004700008e700008e4
+#            v30: 0x00000000000000004700008e700008e4
 0x~~~~~~~~~~~~~~~~  0e072cd5		smov w21, v6.b[3]
-#   x21: 0x0000000000000000
+#            w21:         0x00000000
 0x~~~~~~~~~~~~~~~~  0e1e2f4d		smov w13, v26.h[7]
-#   x13: 0x0000000000000000
+#            w13:         0x00000000
 0x~~~~~~~~~~~~~~~~  4e0f2e18		smov x24, v16.b[7]
-#   x24: 0x0000000000000000
+#            x24: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  4e0e2c87		smov x7, v4.h[3]
-#    x7: 0x00000000000003c9
+#             x7: 0x00000000000003c9
 0x~~~~~~~~~~~~~~~~  4e0c2cfd		smov x29, v7.s[1]
-#   x29: 0x0000000000000000
+#            x29: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  0eb1c3a4		smull v4.2d, v29.2s, v17.2s
-#    v4: 0x15a6d000c90fc48aedb876b6692ad888
+#             v4: 0x15a6d000c90fc48aedb876b6692ad888
 0x~~~~~~~~~~~~~~~~  0f86aabe		smull v30.2d, v21.2s, v6.s[2]
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e77c0b7		smull v23.4s, v5.4h, v23.4h
-#   v23: 0x00000000000000000000000000042ae0
+#            v23: 0x00000000000000000000000000042ae0
 0x~~~~~~~~~~~~~~~~  0f52a128		smull v8.4s, v9.4h, v2.h[1]
-#    v8: 0x185dc92015d7004009b45060e2e7be40
+#             v8: 0x185dc92015d7004009b45060e2e7be40
 0x~~~~~~~~~~~~~~~~  0e21c23f		smull v31.8h, v17.8b, v1.8b
-#   v31: 0x00000000f3d5e78200000000249000d8
+#            v31: 0x00000000f3d5e78200000000249000d8
 0x~~~~~~~~~~~~~~~~  4eb7c063		smull2 v3.2d, v3.4s, v23.4s
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4fa6a3af		smull2 v15.2d, v29.4s, v6.s[1]
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7ec293		smull2 v19.4s, v20.8h, v30.8h
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f47a946		smull2 v6.4s, v10.8h, v7.h[4]
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e3bc119		smull2 v25.8h, v8.16b, v27.16b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e2079e3		sqabs b3, b15
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0792e		sqabs d14, d9
-#   v14: 0x000000000000000062d05891275a8a02
+#            v14: 0x000000000000000062d05891275a8a02
 0x~~~~~~~~~~~~~~~~  5e607b9f		sqabs h31, h28
-#   v31: 0x00000000000000000000000000000001
+#            v31: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  5ea07808		sqabs s8, s0
-#    v8: 0x000000000000000000000000383fcd60
+#             v8: 0x000000000000000000000000383fcd60
 0x~~~~~~~~~~~~~~~~  4e2078ee		sqabs v14.16b, v7.16b
-#   v14: 0x0000000000000000000000000000632f
+#            v14: 0x0000000000000000000000000000632f
 0x~~~~~~~~~~~~~~~~  4ee07a77		sqabs v23.2d, v19.2d
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea07b0a		sqabs v10.2s, v24.2s
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 0x~~~~~~~~~~~~~~~~  0e607a7f		sqabs v31.4h, v19.4h
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 0x~~~~~~~~~~~~~~~~  4ea07817		sqabs v23.4s, v0.4s
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 0x~~~~~~~~~~~~~~~~  0e207afd		sqabs v29.8b, v23.8b
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 0x~~~~~~~~~~~~~~~~  4e607ab1		sqabs v17.8h, v21.8h
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 0x~~~~~~~~~~~~~~~~  5e2d0ee9		sqadd b9, b23, b13
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 0x~~~~~~~~~~~~~~~~  5efa0f22		sqadd d2, d25, d26
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 0x~~~~~~~~~~~~~~~~  5e790fa7		sqadd h7, h29, h25
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 0x~~~~~~~~~~~~~~~~  5eb80ceb		sqadd s11, s7, s24
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 0x~~~~~~~~~~~~~~~~  4e3d0e14		sqadd v20.16b, v16.16b, v29.16b
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 0x~~~~~~~~~~~~~~~~  4efc0fd7		sqadd v23.2d, v30.2d, v28.2d
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 0x~~~~~~~~~~~~~~~~  0ea20e68		sqadd v8.2s, v19.2s, v2.2s
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 0x~~~~~~~~~~~~~~~~  0e7f0d94		sqadd v20.4h, v12.4h, v31.4h
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 0x~~~~~~~~~~~~~~~~  4eb10dee		sqadd v14.4s, v15.4s, v17.4s
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 0x~~~~~~~~~~~~~~~~  0e2d0fa2		sqadd v2.8b, v29.8b, v13.8b
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 0x~~~~~~~~~~~~~~~~  4e6e0e67		sqadd v7.8h, v19.8h, v14.8h
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 0x~~~~~~~~~~~~~~~~  5ebe90af		sqdmlal d15, s5, s30
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 0x~~~~~~~~~~~~~~~~  5fa23958		sqdmlal d24, s10, v2.s[3]
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 0x~~~~~~~~~~~~~~~~  5e689269		sqdmlal s9, h19, h8
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 0x~~~~~~~~~~~~~~~~  5f7c302e		sqdmlal s14, h1, v12.h[3]
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 0x~~~~~~~~~~~~~~~~  0ebf90be		sqdmlal v30.2d, v5.2s, v31.2s
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 0x~~~~~~~~~~~~~~~~  0faa31d9		sqdmlal v25.2d, v14.2s, v10.s[1]
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 0x~~~~~~~~~~~~~~~~  0e709233		sqdmlal v19.4s, v17.4h, v16.4h
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 0x~~~~~~~~~~~~~~~~  0f5830a8		sqdmlal v8.4s, v5.4h, v8.h[1]
-#    v8: 0x0672308605c005640fa6a0001322041c
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 0x~~~~~~~~~~~~~~~~  4ea392e1		sqdmlal2 v1.2d, v23.4s, v3.4s
-#    v1: 0x317157c12580003d000023c700005094
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 0x~~~~~~~~~~~~~~~~  4f893013		sqdmlal2 v19.2d, v0.4s, v9.s[0]
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 0x~~~~~~~~~~~~~~~~  4e6b92da		sqdmlal2 v26.4s, v22.8h, v11.8h
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 0x~~~~~~~~~~~~~~~~  4f4d3b86		sqdmlal2 v6.4s, v28.8h, v13.h[4]
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 0x~~~~~~~~~~~~~~~~  5eb4b3aa		sqdmlsl d10, s29, s20
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 0x~~~~~~~~~~~~~~~~  5faa712a		sqdmlsl d10, s9, v10.s[1]
-#   v10: 0x0000000000000000ffffffc0b8e66400
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 0x~~~~~~~~~~~~~~~~  5e78b13e		sqdmlsl s30, h9, h24
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 0x~~~~~~~~~~~~~~~~  5f56730d		sqdmlsl s13, h24, v6.h[1]
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 0x~~~~~~~~~~~~~~~~  0eb4b15b		sqdmlsl v27.2d, v10.2s, v20.2s
-#   v27: 0xffffffffece2ff800000004ffccf8000
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 0x~~~~~~~~~~~~~~~~  0fa37af7		sqdmlsl v23.2d, v23.2s, v3.s[3]
-#   v23: 0x0000000000000000ffffffffffffffff
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 0x~~~~~~~~~~~~~~~~  0e7db227		sqdmlsl v7.4s, v17.4h, v29.4h
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 0x~~~~~~~~~~~~~~~~  0f437ab6		sqdmlsl v22.4s, v21.4h, v3.h[4]
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 0x~~~~~~~~~~~~~~~~  4eb6b0ec		sqdmlsl2 v12.2d, v7.4s, v22.4s
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 0x~~~~~~~~~~~~~~~~  4f887334		sqdmlsl2 v20.2d, v25.4s, v8.s[0]
-#   v20: 0x0000000000000000ffd9c5ff00000090
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 0x~~~~~~~~~~~~~~~~  4e72b359		sqdmlsl2 v25.4s, v26.8h, v18.8h
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 0x~~~~~~~~~~~~~~~~  4f457279		sqdmlsl2 v25.4s, v19.8h, v5.h[0]
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 0x~~~~~~~~~~~~~~~~  5e6cb771		sqdmulh h17, h27, h12
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 0x~~~~~~~~~~~~~~~~  5f4bc0b0		sqdmulh h16, h5, v11.h[0]
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 0x~~~~~~~~~~~~~~~~  5eb0b661		sqdmulh s1, s19, s16
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 0x~~~~~~~~~~~~~~~~  5f82c201		sqdmulh s1, s16, v2.s[0]
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 0x~~~~~~~~~~~~~~~~  0ea8b43c		sqdmulh v28.2s, v1.2s, v8.2s
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 0x~~~~~~~~~~~~~~~~  0f83c11c		sqdmulh v28.2s, v8.2s, v3.s[0]
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 0x~~~~~~~~~~~~~~~~  0e65b72b		sqdmulh v11.4h, v25.4h, v5.4h
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 0x~~~~~~~~~~~~~~~~  0f58c9de		sqdmulh v30.4h, v14.4h, v8.h[5]
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 0x~~~~~~~~~~~~~~~~  4eadb6b9		sqdmulh v25.4s, v21.4s, v13.4s
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 0x~~~~~~~~~~~~~~~~  4faac857		sqdmulh v23.4s, v2.4s, v10.s[3]
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 0x~~~~~~~~~~~~~~~~  4e77b4ba		sqdmulh v26.8h, v5.8h, v23.8h
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 0x~~~~~~~~~~~~~~~~  4f74c2c4		sqdmulh v4.8h, v22.8h, v4.h[3]
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 0x~~~~~~~~~~~~~~~~  5ebad059		sqdmull d25, s2, s26
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 0x~~~~~~~~~~~~~~~~  5fa5b1de		sqdmull d30, s14, v5.s[1]
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 0x~~~~~~~~~~~~~~~~  5e6bd25d		sqdmull s29, h18, h11
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 0x~~~~~~~~~~~~~~~~  5f67b9ab		sqdmull s11, h13, v7.h[6]
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 0x~~~~~~~~~~~~~~~~  0ea8d137		sqdmull v23.2d, v9.2s, v8.2s
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 0x~~~~~~~~~~~~~~~~  0fa4b3b2		sqdmull v18.2d, v29.2s, v4.s[1]
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 0x~~~~~~~~~~~~~~~~  0e67d311		sqdmull v17.4s, v24.4h, v7.4h
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 0x~~~~~~~~~~~~~~~~  0f55b1e8		sqdmull v8.4s, v15.4h, v5.h[1]
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 0x~~~~~~~~~~~~~~~~  4ea2d1dc		sqdmull2 v28.2d, v14.4s, v2.4s
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 0x~~~~~~~~~~~~~~~~  4f8dbb01		sqdmull2 v1.2d, v24.4s, v13.s[2]
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 0x~~~~~~~~~~~~~~~~  4e7fd22b		sqdmull2 v11.4s, v17.8h, v31.8h
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 0x~~~~~~~~~~~~~~~~  4f7bb281		sqdmull2 v1.4s, v20.8h, v11.h[3]
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 0x~~~~~~~~~~~~~~~~  7e207802		sqneg b2, b0
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 0x~~~~~~~~~~~~~~~~  7ee07858		sqneg d24, d2
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 0x~~~~~~~~~~~~~~~~  7e60787d		sqneg h29, h3
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 0x~~~~~~~~~~~~~~~~  7ea07924		sqneg s4, s9
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 0x~~~~~~~~~~~~~~~~  6e207bae		sqneg v14.16b, v29.16b
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 0x~~~~~~~~~~~~~~~~  6ee0799e		sqneg v30.2d, v12.2d
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 0x~~~~~~~~~~~~~~~~  2ea07b5c		sqneg v28.2s, v26.2s
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 0x~~~~~~~~~~~~~~~~  2e607884		sqneg v4.4h, v4.4h
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 0x~~~~~~~~~~~~~~~~  6ea07909		sqneg v9.4s, v8.4s
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 0x~~~~~~~~~~~~~~~~  2e207a94		sqneg v20.8b, v20.8b
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 0x~~~~~~~~~~~~~~~~  6e60795b		sqneg v27.8h, v10.8h
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 0x~~~~~~~~~~~~~~~~  7e60b707		sqrdmulh h7, h24, h0
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 0x~~~~~~~~~~~~~~~~  5f64d86e		sqrdmulh h14, h3, v4.h[6]
-#   v14: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7eb8b67b		sqrdmulh s27, s19, s24
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 0x~~~~~~~~~~~~~~~~  5f84d2bf		sqrdmulh s31, s21, v4.s[0]
-#   v31: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2ea1b732		sqrdmulh v18.2s, v25.2s, v1.2s
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 0x~~~~~~~~~~~~~~~~  0f8dd0b6		sqrdmulh v22.2s, v5.2s, v13.s[0]
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 0x~~~~~~~~~~~~~~~~  2e69b716		sqrdmulh v22.4h, v24.4h, v9.4h
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 0x~~~~~~~~~~~~~~~~  0f6cd84d		sqrdmulh v13.4h, v2.4h, v12.h[6]
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 0x~~~~~~~~~~~~~~~~  6ea2b769		sqrdmulh v9.4s, v27.4s, v2.4s
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 0x~~~~~~~~~~~~~~~~  4fa7d2e3		sqrdmulh v3.4s, v23.4s, v7.s[1]
-#    v3: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e67b402		sqrdmulh v2.8h, v0.8h, v7.8h
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 0x~~~~~~~~~~~~~~~~  4f68d130		sqrdmulh v16.8h, v9.8h, v8.h[2]
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 0x~~~~~~~~~~~~~~~~  5e2d5ea8		sqrshl b8, b21, b13
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 0x~~~~~~~~~~~~~~~~  5ef45cfd		sqrshl d29, d7, d20
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 0x~~~~~~~~~~~~~~~~  5e6a5ddc		sqrshl h28, h14, h10
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 0x~~~~~~~~~~~~~~~~  5ea25e5a		sqrshl s26, s18, s2
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 0x~~~~~~~~~~~~~~~~  4e3a5ff2		sqrshl v18.16b, v31.16b, v26.16b
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 0x~~~~~~~~~~~~~~~~  4ee05c9c		sqrshl v28.2d, v4.2d, v0.2d
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 0x~~~~~~~~~~~~~~~~  0ea05cc3		sqrshl v3.2s, v6.2s, v0.2s
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 0x~~~~~~~~~~~~~~~~  0e765e41		sqrshl v1.4h, v18.4h, v22.4h
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 0x~~~~~~~~~~~~~~~~  4ea75f30		sqrshl v16.4s, v25.4s, v7.4s
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 0x~~~~~~~~~~~~~~~~  0e255ea0		sqrshl v0.8b, v21.8b, v5.8b
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 0x~~~~~~~~~~~~~~~~  4e685e7e		sqrshl v30.8h, v19.8h, v8.8h
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 0x~~~~~~~~~~~~~~~~  5f0c9ea6		sqrshrn b6, h21, #4
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 0x~~~~~~~~~~~~~~~~  5f159e2e		sqrshrn h14, s17, #11
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 0x~~~~~~~~~~~~~~~~  5f369f79		sqrshrn s25, d27, #10
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 0x~~~~~~~~~~~~~~~~  0f2e9da6		sqrshrn v6.2s, v13.2d, #18
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 0x~~~~~~~~~~~~~~~~  0f119d25		sqrshrn v5.4h, v9.4s, #15
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 0x~~~~~~~~~~~~~~~~  0f0f9d93		sqrshrn v19.8b, v12.8h, #1
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 0x~~~~~~~~~~~~~~~~  4f099eb3		sqrshrn2 v19.16b, v21.8h, #7
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 0x~~~~~~~~~~~~~~~~  4f339f1d		sqrshrn2 v29.4s, v24.2d, #13
-#   v29: 0x00000000000000007fffffffffffffff
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 0x~~~~~~~~~~~~~~~~  4f169c4c		sqrshrn2 v12.8h, v2.4s, #10
-#   v12: 0x0000000000000040ffd9c5ff00000090
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 0x~~~~~~~~~~~~~~~~  7f0b8d30		sqrshrun b16, h9, #5
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 0x~~~~~~~~~~~~~~~~  7f118f03		sqrshrun h3, s24, #15
-#    v3: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7f388e50		sqrshrun s16, d18, #8
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 0x~~~~~~~~~~~~~~~~  2f388efc		sqrshrun v28.2s, v23.2d, #8
-#   v28: 0x0000000000000000000000000e598315
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 0x~~~~~~~~~~~~~~~~  2f168f3f		sqrshrun v31.4h, v25.4s, #10
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 0x~~~~~~~~~~~~~~~~  2f0e8ef3		sqrshrun v19.8b, v23.8h, #2
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 0x~~~~~~~~~~~~~~~~  6f088c18		sqrshrun2 v24.16b, v0.8h, #8
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 0x~~~~~~~~~~~~~~~~  6f298c36		sqrshrun2 v22.4s, v1.2d, #23
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 0x~~~~~~~~~~~~~~~~  6f138ebc		sqrshrun2 v28.8h, v21.4s, #13
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 0x~~~~~~~~~~~~~~~~  5e284ea6		sqshl b6, b21, b8
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 0x~~~~~~~~~~~~~~~~  5f0a774b		sqshl b11, b26, #2
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 0x~~~~~~~~~~~~~~~~  5ee44c1d		sqshl d29, d0, d4
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 0x~~~~~~~~~~~~~~~~  5f6374f5		sqshl d21, d7, #35
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 0x~~~~~~~~~~~~~~~~  5e714f34		sqshl h20, h25, h17
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 0x~~~~~~~~~~~~~~~~  5f187414		sqshl h20, h0, #8
-#   v20: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  5ea44dbd		sqshl s29, s13, s4
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 0x~~~~~~~~~~~~~~~~  5f34756a		sqshl s10, s11, #20
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 0x~~~~~~~~~~~~~~~~  4e3c4e48		sqshl v8.16b, v18.16b, v28.16b
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 0x~~~~~~~~~~~~~~~~  4f0a77bd		sqshl v29.16b, v29.16b, #2
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 0x~~~~~~~~~~~~~~~~  4ef04fe8		sqshl v8.2d, v31.2d, v16.2d
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 0x~~~~~~~~~~~~~~~~  4f6575c7		sqshl v7.2d, v14.2d, #37
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 0x~~~~~~~~~~~~~~~~  0ea74f40		sqshl v0.2s, v26.2s, v7.2s
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 0x~~~~~~~~~~~~~~~~  0f337565		sqshl v5.2s, v11.2s, #19
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 0x~~~~~~~~~~~~~~~~  0e604fcb		sqshl v11.4h, v30.4h, v0.4h
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 0x~~~~~~~~~~~~~~~~  0f177641		sqshl v1.4h, v18.4h, #7
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 0x~~~~~~~~~~~~~~~~  4ebe4c76		sqshl v22.4s, v3.4s, v30.4s
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 0x~~~~~~~~~~~~~~~~  4f3c75f0		sqshl v16.4s, v15.4s, #28
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 0x~~~~~~~~~~~~~~~~  0e394f86		sqshl v6.8b, v28.8b, v25.8b
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 0x~~~~~~~~~~~~~~~~  0f0875e0		sqshl v0.8b, v15.8b, #0
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 0x~~~~~~~~~~~~~~~~  4e7e4e06		sqshl v6.8h, v16.8h, v30.8h
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 0x~~~~~~~~~~~~~~~~  4f1e7683		sqshl v3.8h, v20.8h, #14
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 0x~~~~~~~~~~~~~~~~  7f0e65cd		sqshlu b13, b14, #6
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 0x~~~~~~~~~~~~~~~~  7f6c6600		sqshlu d0, d16, #44
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 0x~~~~~~~~~~~~~~~~  7f1f67a5		sqshlu h5, h29, #15
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 0x~~~~~~~~~~~~~~~~  7f2d651d		sqshlu s29, s8, #13
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 0x~~~~~~~~~~~~~~~~  6f0a669b		sqshlu v27.16b, v20.16b, #2
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 0x~~~~~~~~~~~~~~~~  6f4b6598		sqshlu v24.2d, v12.2d, #11
-#   v24: 0x00000000000200000000000000000000
+#            v24: 0x00000000000200000000000000000000
 0x~~~~~~~~~~~~~~~~  2f36666c		sqshlu v12.2s, v19.2s, #22
-#   v12: 0x000000000000000000000000ffffffff
+#            v12: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  2f1b6588		sqshlu v8.4h, v12.4h, #11
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f286472		sqshlu v18.4s, v3.4s, #8
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f096543		sqshlu v3.8b, v10.8b, #1
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f14671e		sqshlu v30.8h, v24.8h, #4
-#   v30: 0x00000000002000000000000000000000
+#            v30: 0x00000000002000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f0f9781		sqshrn b1, h28, #1
-#    v1: 0x00000000000000000000000000000080
+#             v1: 0x00000000000000000000000000000080
 0x~~~~~~~~~~~~~~~~  5f1694ff		sqshrn h31, s7, #10
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f289544		sqshrn s4, d10, #24
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f23942a		sqshrn v10.2s, v1.2d, #29
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f1295a3		sqshrn v3.4h, v13.4s, #14
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0994db		sqshrn v27.8b, v6.8h, #7
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0f96ee		sqshrn2 v14.16b, v23.8h, #1
-#   v14: 0x0000000000077f7f0000000000000000
+#            v14: 0x0000000000077f7f0000000000000000
 0x~~~~~~~~~~~~~~~~  4f2596d9		sqshrn2 v25.4s, v22.2d, #27
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f16959f		sqshrn2 v31.8h, v12.4s, #10
-#   v31: 0x000000000000ffff0000000000000000
+#            v31: 0x000000000000ffff0000000000000000
 0x~~~~~~~~~~~~~~~~  7f0f8409		sqshrun b9, h0, #1
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f1984cb		sqshrun h11, s6, #7
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f33858d		sqshrun s13, d12, #13
-#   v13: 0x0000000000000000000000000007ffff
+#            v13: 0x0000000000000000000000000007ffff
 0x~~~~~~~~~~~~~~~~  2f3f87ca		sqshrun v10.2s, v30.2d, #1
-#   v10: 0x00000000000000000010000000000000
+#            v10: 0x00000000000000000010000000000000
 0x~~~~~~~~~~~~~~~~  2f15847f		sqshrun v31.4h, v3.4s, #11
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0887dc		sqshrun v28.8b, v30.8h, #8
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0d8770		sqshrun2 v16.16b, v27.8h, #3
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f2e85db		sqshrun2 v27.4s, v14.2d, #18
-#   v27: 0x00000001000000000000000000000000
+#            v27: 0x00000001000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1f85d7		sqshrun2 v23.8h, v14.4s, #1
-#   v23: 0x0000ffff000000000000000e59831500
+#            v23: 0x0000ffff000000000000000e59831500
 0x~~~~~~~~~~~~~~~~  5e2b2fb3		sqsub b19, b29, b11
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee62ff5		sqsub d21, d31, d6
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e732d52		sqsub h18, h10, h19
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ea02ca6		sqsub s6, s5, s0
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e202ed5		sqsub v21.16b, v22.16b, v0.16b
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ef12d56		sqsub v22.2d, v10.2d, v17.2d
-#   v22: 0x00000000000000000010000000000000
+#            v22: 0x00000000000000000010000000000000
 0x~~~~~~~~~~~~~~~~  0ea22ea8		sqsub v8.2s, v21.2s, v2.2s
-#    v8: 0x000000000000000000000000ffff000f
+#             v8: 0x000000000000000000000000ffff000f
 0x~~~~~~~~~~~~~~~~  0e7b2f32		sqsub v18.4h, v25.4h, v27.4h
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea62c6d		sqsub v13.4s, v3.4s, v6.4s
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e302fbc		sqsub v28.8b, v29.8b, v16.8b
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6a2cd1		sqsub v17.8h, v6.8h, v10.8h
-#   v17: 0x0000000000000000fff0000000000000
+#            v17: 0x0000000000000000fff0000000000000
 0x~~~~~~~~~~~~~~~~  5e214b5b		sqxtn b27, h26
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5e614971		sqxtn h17, s11
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ea14bf6		sqxtn s22, d31
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea148ba		sqxtn v26.2s, v5.2d
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6148ed		sqxtn v13.4h, v7.4s
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e214a73		sqxtn v19.8b, v19.8h
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e214873		sqxtn2 v19.16b, v3.8h
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea14837		sqxtn2 v23.4s, v1.2d
-#   v23: 0x00000000000000800000000e59831500
+#            v23: 0x00000000000000800000000e59831500
 0x~~~~~~~~~~~~~~~~  4e61486d		sqxtn2 v13.8h, v3.4s
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e21293a		sqxtun b26, h9
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e612993		sqxtun h19, s12
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ea128c3		sqxtun s3, d6
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea12b5d		sqxtun v29.2s, v26.2d
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e61295a		sqxtun v26.4h, v10.4s
-#   v26: 0x000000000000000000000000ffff0000
+#            v26: 0x000000000000000000000000ffff0000
 0x~~~~~~~~~~~~~~~~  2e212ba7		sqxtun v7.8b, v29.8h
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e2129d5		sqxtun2 v21.16b, v14.8h
-#   v21: 0x000007ff000000000000000000000000
+#            v21: 0x000007ff000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea129f8		sqxtun2 v24.4s, v15.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e61283e		sqxtun2 v30.8h, v1.4s
-#   v30: 0x00000000000000800000000000000000
+#            v30: 0x00000000000000800000000000000000
 0x~~~~~~~~~~~~~~~~  4e2f1635		srhadd v21.16b, v17.16b, v15.16b
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ebd16bc		srhadd v28.2s, v21.2s, v29.2s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e7e1429		srhadd v9.4h, v1.4h, v30.4h
-#    v9: 0x00000000000000000000000000000040
+#             v9: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  4ea21418		srhadd v24.4s, v0.4s, v2.4s
-#   v24: 0x00000000000000000000000000007ff9
+#            v24: 0x00000000000000000000000000007ff9
 0x~~~~~~~~~~~~~~~~  0e2f1626		srhadd v6.8b, v17.8b, v15.8b
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7514e5		srhadd v5.8h, v7.8h, v21.8h
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f4f45ce		sri d14, d14, #49
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0c4517		sri v23.16b, v8.16b, #4
-#   v23: 0x0000000000000080000000005f8f1000
+#            v23: 0x0000000000000080000000005f8f1000
 0x~~~~~~~~~~~~~~~~  6f6c45b4		sri v20.2d, v13.2d, #20
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f284450		sri v16.2s, v2.2s, #24
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f1546e5		sri v5.4h, v23.4h, #11
-#    v5: 0x000000000000000000000000000b0002
+#             v5: 0x000000000000000000000000000b0002
 0x~~~~~~~~~~~~~~~~  6f2945fb		sri v27.4s, v15.4s, #23
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0c47b3		sri v19.8b, v29.8b, #4
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1d47a7		sri v7.8h, v29.8h, #3
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5efa5522		srshl d2, d9, d26
-#    v2: 0x00000000000000000000000000000040
+#             v2: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  4e2b563d		srshl v29.16b, v17.16b, v11.16b
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee455e8		srshl v8.2d, v15.2d, v4.2d
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea85639		srshl v25.2s, v17.2s, v8.2s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6754f3		srshl v19.4h, v7.4h, v7.4h
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb1544d		srshl v13.4s, v2.4s, v17.4s
-#   v13: 0x00000000000000000000000000000040
+#            v13: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  0e3554d6		srshl v22.8b, v6.8b, v21.8b
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e64562a		srshl v10.8h, v17.8h, v4.8h
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f532655		srshr d21, d18, #45
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f092563		srshr v3.16b, v11.16b, #7
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f4b2755		srshr v21.2d, v26.2d, #53
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f2424ab		srshr v11.2s, v5.2s, #28
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f142647		srshr v7.4h, v18.4h, #12
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f222467		srshr v7.4s, v3.4s, #30
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0a244e		srshr v14.8b, v2.8b, #6
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  4f1d2695		srshr v21.8h, v20.8h, #3
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f4137d5		srsra d21, d30, #63
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0a37db		srsra v27.16b, v30.16b, #6
-#   v27: 0x00000000000000fe0000000000000000
+#            v27: 0x00000000000000fe0000000000000000
 0x~~~~~~~~~~~~~~~~  4f653594		srsra v20.2d, v12.2d, #27
-#   v20: 0x00000000000000000000000000000020
+#            v20: 0x00000000000000000000000000000020
 0x~~~~~~~~~~~~~~~~  0f3b3620		srsra v0.2s, v17.2s, #5
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f11360e		srsra v14.4h, v16.4h, #15
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  4f2c3472		srsra v18.4s, v3.4s, #20
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0f3435		srsra v21.8b, v1.8b, #1
-#   v21: 0x000000000000000000000000000000c0
+#            v21: 0x000000000000000000000000000000c0
 0x~~~~~~~~~~~~~~~~  4f1e373f		srsra v31.8h, v25.8h, #2
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee945a1		sshl d1, d13, d9
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2f47f1		sshl v17.16b, v31.16b, v15.16b
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee0460d		sshl v13.2d, v16.2d, v0.2d
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eb644e0		sshl v0.2s, v7.2s, v22.2s
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e644677		sshl v23.4h, v19.4h, v4.4h
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eab44a5		sshl v5.4s, v5.4s, v11.4s
-#    v5: 0x000000000000000000000000000b0002
+#             v5: 0x000000000000000000000000000b0002
 0x~~~~~~~~~~~~~~~~  0e274777		sshl v23.8b, v27.8b, v7.8b
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e65455d		sshl v29.8h, v10.8h, v5.8h
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f37a440		sshll v0.2d, v2.2s, #23
-#    v0: 0x00000000000000000000000020000000
+#             v0: 0x00000000000000000000000020000000
 0x~~~~~~~~~~~~~~~~  0f18a50b		sshll v11.4s, v8.4h, #8
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f09a7a4		sshll v4.8h, v29.8b, #1
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f2ea48a		sshll2 v10.2d, v4.4s, #14
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f16a7fa		sshll2 v26.4s, v31.8h, #6
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0ca743		sshll2 v3.8h, v26.16b, #4
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f6c06b3		sshr d19, d21, #20
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f0b06ef		sshr v15.16b, v23.16b, #5
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f5a05d1		sshr v17.2d, v14.2d, #38
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f2907a3		sshr v3.2s, v29.2s, #23
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f1c0777		sshr v23.4h, v27.4h, #4
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f3c047c		sshr v28.4s, v3.4s, #4
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0a044e		sshr v14.8b, v2.8b, #6
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  4f1a0503		sshr v3.8h, v8.8h, #6
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f54178c		ssra d12, d28, #44
-#   v12: 0x000000000000000000000000ffffffff
+#            v12: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  4f0c17fd		ssra v29.16b, v31.16b, #4
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f681403		ssra v3.2d, v0.2d, #24
-#    v3: 0x00000000000000000000000000000020
+#             v3: 0x00000000000000000000000000000020
 0x~~~~~~~~~~~~~~~~  0f3a178e		ssra v14.2s, v28.2s, #6
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  0f191512		ssra v18.4h, v8.4h, #7
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f2815df		ssra v31.4s, v14.4s, #24
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f0b175c		ssra v28.8b, v26.8b, #5
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f121529		ssra v9.8h, v9.8h, #14
-#    v9: 0x00000000000000000000000000000040
+#             v9: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  0ea321cd		ssubl v13.2d, v14.2s, v3.2s
-#   v13: 0x0000000000000000ffffffffffffffe1
+#            v13: 0x0000000000000000ffffffffffffffe1
 0x~~~~~~~~~~~~~~~~  0e682205		ssubl v5.4s, v16.4h, v8.4h
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e262380		ssubl v0.8h, v28.8b, v6.8b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb921a5		ssubl2 v5.2d, v13.4s, v25.4s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e7121e3		ssubl2 v3.4s, v15.8h, v17.8h
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2e21ef		ssubl2 v15.8h, v15.16b, v14.16b
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eba32f9		ssubw v25.2d, v23.2d, v26.2s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e783255		ssubw v21.4s, v18.4s, v24.4h
-#   v21: 0x000000000000000000000000ffff8007
+#            v21: 0x000000000000000000000000ffff8007
 0x~~~~~~~~~~~~~~~~  0e2332de		ssubw v30.8h, v22.8h, v3.8b
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ebc3310		ssubw2 v16.2d, v24.2d, v28.4s
-#   v16: 0x00000000000000000000000000007ff9
+#            v16: 0x00000000000000000000000000007ff9
 0x~~~~~~~~~~~~~~~~  4e6f317f		ssubw2 v31.4s, v11.4s, v15.8h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e303104		ssubw2 v4.8h, v8.8h, v16.16b
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4c002012		st1 {v18.16b, v19.16b, v20.16b, v21.16b}, [x0]
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#     v21<127:0>: 0x000000000000000000000000ffff8007
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x07 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x80 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v20<127:0>: 0x00000000000000000000000000000020
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82202a		st1 {v10.16b, v11.16b, v12.16b, v13.16b}, [x1], x2
-#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v12: 0x000000000000000000000000ffffffff -> 0x~~~~~~~~~~~~~~~~
-#   v13: 0x0000000000000000ffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v13<127:0>: 0x0000000000000000ffffffffffffffe1
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xe1 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v12<127:0>: 0x000000000000000000000000ffffffff
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v11<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v10<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f203b		st1 {v27.16b, v28.16b, v29.16b, v30.16b}, [x1], #64
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v30<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v29<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v28<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xfe -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c006010		st1 {v16.16b, v17.16b, v18.16b}, [x0]
-#   v16: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v17<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v16<127:0>: 0x00000000000000000000000000007ff9
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xf9 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x7f -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c826035		st1 {v21.16b, v22.16b, v23.16b}, [x1], x2
-#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v22<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v21<127:0>: 0x000000000000000000000000ffff8007
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x07 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x80 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f6029		st1 {v9.16b, v10.16b, v11.16b}, [x1], #48
-#    v9: 0x00000000000000000000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v11<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v10<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v9<127:0>: 0x00000000000000000000000000000040
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00a007		st1 {v7.16b, v8.16b}, [x0]
-#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v8<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v7<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82a03a		st1 {v26.16b, v27.16b}, [x1], x2
-#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xfe -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#     v26<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c9fa036		st1 {v22.16b, v23.16b}, [x1], #32
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c007017		st1 {v23.16b}, [x0]
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82703c		st1 {v28.16b}, [x1], x2
-#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c9f7022		st1 {v2.16b}, [x1], #16
-#    v2: 0x00000000000000000000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c002c1d		st1 {v29.1d, v30.1d, v31.1d, v0.1d}, [x0]
-#   v29:                 0x0000000000000000 (d29: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v31:                 0x0000000000000000 (d31: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#       v0<63:0>:                 0x0000000000000000 (0.000)
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+#      v31<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v30<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v29<63:0>:                 0x0000000000000000 (0.000)
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 0x~~~~~~~~~~~~~~~~  0c822c2c		st1 {v12.1d, v13.1d, v14.1d, v15.1d}, [x1], x2
-#   v12:                 0x00000000ffffffff (d12: 2.12200e-314) -> 0x~~~~~~~~~~~~~~~~
-#   v13:                 0xffffffffffffffe1 (d13: nan) -> 0x~~~~~~~~~~~~~~~~
-#   v14:                 0x0000000000000001 (d14: 4.94066e-324) -> 0x~~~~~~~~~~~~~~~~
-#   v15:                 0x0000000000000000 (d15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v15<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v14<63:0>:                 0x0000000000000001 (4.941e-324)
+#                                                  ╙─ 0x0000000000000001 -> 0x~~~~~~~~~~~~~~~~
+#      v13<63:0>:                 0xffffffffffffffe1 (nan)
+#                                                  ╙─ 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
+#      v12<63:0>:                 0x00000000ffffffff (2.122e-314)
+#                                                  ╙─ 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f2c3e		st1 {v30.1d, v31.1d, v0.1d, v1.1d}, [x1], #32
-#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v31:                 0x0000000000000000 (d31: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v1:                 0x0000000000000000 (d1: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v1<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#       v0<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v31<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v30<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c006c10		st1 {v16.1d, v17.1d, v18.1d}, [x0]
-#   v16:                 0x0000000000007ff9 (d16: 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
-#   v17:                 0x0000000000000000 (d17: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v18:                 0x0000000000000000 (d18: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#      v18<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v17<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v16<63:0>:                 0x0000000000007ff9 (1.619e-319)
+#                                                  ╙─ 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c826c23		st1 {v3.1d, v4.1d, v5.1d}, [x1], x2
-#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v4:                 0x0000000000000000 (d4: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v5:                 0x0000000000000000 (d5: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v5<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#       v4<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#       v3<63:0>:                 0x0000000000000000 (0.000)
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+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f6c2e		st1 {v14.1d, v15.1d, v16.1d}, [x1], #24
-#   v14:                 0x0000000000000001 (d14: 4.94066e-324) -> 0x~~~~~~~~~~~~~~~~
-#   v15:                 0x0000000000000000 (d15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v16:                 0x0000000000007ff9 (d16: 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v16<63:0>:                 0x0000000000007ff9 (1.619e-319)
+#                                                  ╙─ 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#      v15<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v14<63:0>:                 0x0000000000000001 (4.941e-324)
+#                                                  ╙─ 0x0000000000000001 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c00ac12		st1 {v18.1d, v19.1d}, [x0]
-#   v18:                 0x0000000000000000 (d18: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v19:                 0x0000000000000000 (d19: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#      v19<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v18<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c82ac25		st1 {v5.1d, v6.1d}, [x1], x2
-#    v5:                 0x0000000000000000 (d5: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v6<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#       v5<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9fac22		st1 {v2.1d, v3.1d}, [x1], #16
-#    v2:                 0x0000000000000040 (d2: 3.16202e-322) -> 0x~~~~~~~~~~~~~~~~
-#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v3<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#       v2<63:0>:                 0x0000000000000040 (3.162e-322)
+#                                                  ╙─ 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c007c04		st1 {v4.1d}, [x0]
-#    v4:                 0x0000000000000000 (d4: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#       v4<63:0>:                 0x0000000000000000 (0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c827c3b		st1 {v27.1d}, [x1], x2
-#   v27:                 0x0000000000000000 (d27: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v27<63:0>:                 0x0000000000000000 (0.000)
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+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f7c37		st1 {v23.1d}, [x1], #8
-#   v23:                 0x0000000000000000 (d23: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v23<63:0>:                 0x0000000000000000 (0.000)
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 0x~~~~~~~~~~~~~~~~  4c002c02		st1 {v2.2d, v3.2d, v4.2d, v5.2d}, [x0]
-#    v2: 0x00000000000000000000000000000040 (0.00000, 3.16202e-322) -> 0x~~~~~~~~~~~~~~~~
-#    v3: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v4: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#      v5<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v4<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v3<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v2<127:0>: 0x00000000000000000000000000000040 (0.000, 3.162e-322)
+#                                  ║               ╙─ 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c822c36		st1 {v22.2d, v23.2d, v24.2d, v25.2d}, [x1], x2
-#   v22: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v25<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v24<127:0>: 0x00000000000000000000000000007ff9 (0.000, 1.619e-319)
+#                                  ║               ╙─ 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v22<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f2c3c		st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x1], #64
-#   v28: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v30: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v31: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v30<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c006c11		st1 {v17.2d, v18.2d, v19.2d}, [x0]
-#   v17: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v17<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c826c30		st1 {v16.2d, v17.2d, v18.2d}, [x1], x2
-#   v16: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v17<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v16<127:0>: 0x00000000000000000000000000007ff9 (0.000, 1.619e-319)
+#                                  ║               ╙─ 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f6c36		st1 {v22.2d, v23.2d, v24.2d}, [x1], #48
-#   v22: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c00ac15		st1 {v21.2d, v22.2d}, [x0]
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 0x~~~~~~~~~~~~~~~~  4c82ac26		st1 {v6.2d, v7.2d}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9fac3b		st1 {v27.2d, v28.2d}, [x1], #32
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 0x~~~~~~~~~~~~~~~~  4c007c15		st1 {v21.2d}, [x0]
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 0x~~~~~~~~~~~~~~~~  4c827c3d		st1 {v29.2d}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9f7c34		st1 {v20.2d}, [x1], #16
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 0x~~~~~~~~~~~~~~~~  0c002816		st1 {v22.2s, v23.2s, v24.2s, v25.2s}, [x0]
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 0x~~~~~~~~~~~~~~~~  0c822828		st1 {v8.2s, v9.2s, v10.2s, v11.2s}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  0c9f282f		st1 {v15.2s, v16.2s, v17.2s, v18.2s}, [x1], #32
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 0x~~~~~~~~~~~~~~~~  0c006802		st1 {v2.2s, v3.2s, v4.2s}, [x0]
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-#    v3:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c826837		st1 {v23.2s, v24.2s, v25.2s}, [x1], x2
-#   v23:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v24:                 0x0000000000007ff9 (..., 0.00000, 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f6827		st1 {v7.2s, v8.2s, v9.2s}, [x1], #24
-#    v7:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v8:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c00a81c		st1 {v28.2s, v29.2s}, [x0]
-#   v28:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c82a83d		st1 {v29.2s, v30.2s}, [x1], x2
-#   v29:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9fa837		st1 {v23.2s, v24.2s}, [x1], #16
-#   v23:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v24:                 0x0000000000007ff9 (..., 0.00000, 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c007806		st1 {v6.2s}, [x0]
-#    v6:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c82782b		st1 {v11.2s}, [x1], x2
-#   v11:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f7831		st1 {v17.2s}, [x1], #8
-#   v17:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c002406		st1 {v6.4h, v7.4h, v8.4h, v9.4h}, [x0]
-#    v6:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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-#    v8:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c822429		st1 {v9.4h, v10.4h, v11.4h, v12.4h}, [x1], x2
-#    v9:                 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f2439		st1 {v25.4h, v26.4h, v27.4h, v28.4h}, [x1], #32
-#   v25:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v26:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c00640b		st1 {v11.4h, v12.4h, v13.4h}, [x0]
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-#   v13:                 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c82642a		st1 {v10.4h, v11.4h, v12.4h}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  0c9f642c		st1 {v12.4h, v13.4h, v14.4h}, [x1], #24
-#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
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-#   v14:                 0x0000000000000001 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c00a40d		st1 {v13.4h, v14.4h}, [x0]
-#   v13:                 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
-#   v14:                 0x0000000000000001 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c82a42f		st1 {v15.4h, v16.4h}, [x1], x2
-#   v15:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9fa435		st1 {v21.4h, v22.4h}, [x1], #16
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 0x~~~~~~~~~~~~~~~~  0c007410		st1 {v16.4h}, [x0]
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 0x~~~~~~~~~~~~~~~~  0c827428		st1 {v8.4h}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  0c9f743e		st1 {v30.4h}, [x1], #8
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 0x~~~~~~~~~~~~~~~~  4c002803		st1 {v3.4s, v4.4s, v5.4s, v6.4s}, [x0]
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 0x~~~~~~~~~~~~~~~~  4c822839		st1 {v25.4s, v26.4s, v27.4s, v28.4s}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9f2825		st1 {v5.4s, v6.4s, v7.4s, v8.4s}, [x1], #64
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 0x~~~~~~~~~~~~~~~~  4c00681f		st1 {v31.4s, v0.4s, v1.4s}, [x0]
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 0x~~~~~~~~~~~~~~~~  4c82683e		st1 {v30.4s, v31.4s, v0.4s}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9f6826		st1 {v6.4s, v7.4s, v8.4s}, [x1], #48
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 0x~~~~~~~~~~~~~~~~  4c00a811		st1 {v17.4s, v18.4s}, [x0]
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 0x~~~~~~~~~~~~~~~~  4c82a83f		st1 {v31.4s, v0.4s}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9fa821		st1 {v1.4s, v2.4s}, [x1], #32
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 0x~~~~~~~~~~~~~~~~  4c00781a		st1 {v26.4s}, [x0]
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 0x~~~~~~~~~~~~~~~~  4c82782f		st1 {v15.4s}, [x1], x2
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 0x~~~~~~~~~~~~~~~~  4c9f782d		st1 {v13.4s}, [x1], #16
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 0x~~~~~~~~~~~~~~~~  0c00201a		st1 {v26.8b, v27.8b, v28.8b, v29.8b}, [x0]
-#   v26:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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-#   v28:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c82202a		st1 {v10.8b, v11.8b, v12.8b, v13.8b}, [x1], x2
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+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v11<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v10<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f202f		st1 {v15.8b, v16.8b, v17.8b, v18.8b}, [x1], #32
-#   v15:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v17:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v18:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v18<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v17<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v16<63:0>:                 0x0000000000007ff9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xf9 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x7f -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v15<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c006013		st1 {v19.8b, v20.8b, v21.8b}, [x0]
-#   v19:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20:                 0x0000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#   v21:                 0x00000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
+#      v21<63:0>:                 0x00000000ffff8007
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x07 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x80 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v20<63:0>:                 0x0000000000000020
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v19<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c82603f		st1 {v31.8b, v0.8b, v1.8b}, [x1], x2
-#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v1<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#       v0<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v31<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f6029		st1 {v9.8b, v10.8b, v11.8b}, [x1], #24
-#    v9:                 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#   v10:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v11<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#      v10<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#       v9<63:0>:                 0x0000000000000040
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c00a00c		st1 {v12.8b, v13.8b}, [x0]
-#   v12:                 0x00000000ffffffff -> 0x~~~~~~~~~~~~~~~~
-#   v13:                 0xffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
+#      v13<63:0>:                 0xffffffffffffffe1
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xe1 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#      v12<63:0>:                 0x00000000ffffffff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c82a022		st1 {v2.8b, v3.8b}, [x1], x2
-#    v2:                 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#    v3:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v3<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#       v2<63:0>:                 0x0000000000000040
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9fa020		st1 {v0.8b, v1.8b}, [x1], #16
-#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v1<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#       v0<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c007010		st1 {v16.8b}, [x0]
-#   v16:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#      v16<63:0>:                 0x0000000000007ff9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xf9 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x7f -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c827039		st1 {v25.8b}, [x1], x2
-#   v25:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v25<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f703f		st1 {v31.8b}, [x1], #8
-#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v31<63:0>:                 0x0000000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c002404		st1 {v4.8h, v5.8h, v6.8h, v7.8h}, [x0]
-#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v5<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#      v4<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c822423		st1 {v3.8h, v4.8h, v5.8h, v6.8h}, [x1], x2
-#    v3: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c9f243a		st1 {v26.8h, v27.8h, v28.8h, v29.8h}, [x1], #64
-#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v28: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (0.000, 0.000, 0.000, 1.514e-05, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x00fe -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v26<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
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+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00640a		st1 {v10.8h, v11.8h, v12.8h}, [x0]
-#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v11: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v12: 0x000000000000000000000000ffffffff -> 0x~~~~~~~~~~~~~~~~
+#     v12<127:0>: 0x000000000000000000000000ffffffff (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, nan, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v11<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v10<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c826435		st1 {v21.8h, v22.8h, v23.8h}, [x1], x2
-#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v22<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v21<127:0>: 0x000000000000000000000000ffff8007 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, nan, -4.172e-07)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x8007 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f6432		st1 {v18.8h, v19.8h, v20.8h}, [x1], #48
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v20<127:0>: 0x00000000000000000000000000000020 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 1.907e-06)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0020 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00a41a		st1 {v26.8h, v27.8h}, [x0]
-#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (0.000, 0.000, 0.000, 1.514e-05, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x00fe -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v26<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c82a438		st1 {v24.8h, v25.8h}, [x1], x2
-#   v24: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v25<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v24<127:0>: 0x00000000000000000000000000007ff9 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x7ff9 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9fa431		st1 {v17.8h, v18.8h}, [x1], #32
-#   v17: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v17<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c00741d		st1 {v29.8h}, [x0]
-#   v29: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c827433		st1 {v19.8h}, [x1], x2
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f7437		st1 {v23.8h}, [x1], #16
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d001c13		st1 {v19.b}[15], [x0]
-#   v19: 0x00                               -> 0x~~~~~~~~~~~~~~~~
+#     v19<127:0>: 0x00000000000000000000000000000000
+#                    ╙─────────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d820439		st1 {v25.b}[9], [x1], x2
-#   v25:             0x00                   -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v25<127:0>: 0x00000000000000000000000000000000
+#                                ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d9f0024		st1 {v4.b}[8], [x1], #1
-#    v4:               0x00                 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v4<127:0>: 0x00000000000000000000000000000000
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d00840d		st1 {v13.d}[0], [x0]
-#   v13:                 0xffffffffffffffe1 (d13: nan) -> 0x~~~~~~~~~~~~~~~~
+#     v13<127:0>: 0x0000000000000000ffffffffffffffe1 (..., nan)
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 0x~~~~~~~~~~~~~~~~  0d82843e		st1 {v30.d}[0], [x1], x2
-#   v30:                 0x0000000000000000 (d30: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0d9f8423		st1 {v3.d}[0], [x1], #8
-#    v3:                 0x0000000000000000 (d3: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v3<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0d004016		st1 {v22.h}[0], [x0]
-#   v22:                             0x0000 -> 0x~~~~~~~~~~~~~~~~
+#     v22<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d82583f		st1 {v31.h}[7], [x1], x2
-#   v31: 0x0000                             -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
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 0x~~~~~~~~~~~~~~~~  0d9f5837		st1 {v23.h}[3], [x1], #2
-#   v23:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v23<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                      ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0d008000		st1 {v0.s}[0], [x0]
-#    v0:                         0x00000000 (s0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#      v0<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d82902b		st1 {v11.s}[3], [x1], x2
-#   v11: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4d9f9038		st1 {v24.s}[3], [x1], #4
-#   v24: 0x00000000                         (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c008007		st2 {v7.16b, v8.16b}, [x0]
-#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c828025		st2 {v5.16b, v6.16b}, [x1], x2
-#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v6: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c9f8032		st2 {v18.16b, v19.16b}, [x1], #32
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c008c0e		st2 {v14.2d, v15.2d}, [x0]
-#   v14: 0x00000000000000000000000000000001 (0.00000, 4.94066e-324) -> 0x~~~~~~~~~~~~~~~~
-#   v15: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#     v14<127:0>: 0x00000000000000000000000000000001 (0.000, 4.941e-324)
+#     v15<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000001 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c828c27		st2 {v7.2d, v8.2d}, [x1], x2
-#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#      v8<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c9f8c38		st2 {v24.2d, v25.2d}, [x1], #32
-#   v24: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#     v25<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c008816		st2 {v22.2s, v23.2s}, [x0]
-#   v22:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v23:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#      v22<63:0>:                 0x0000000000000000 (0.000, 0.000)
+#      v23<63:0>:                 0x0000000000000000 (0.000, 0.000)
+#                                          ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c828824		st2 {v4.2s, v5.2s}, [x1], x2
-#    v4:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v5:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#       v5<63:0>:                 0x0000000000000000 (0.000, 0.000)
+#                                          ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f8822		st2 {v2.2s, v3.2s}, [x1], #16
-#    v2:                 0x0000000000000040 (..., 0.00000, 8.96831e-44) -> 0x~~~~~~~~~~~~~~~~
-#    v3:                 0x0000000000000000 (..., 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#       v3<63:0>:                 0x0000000000000000 (0.000, 0.000)
+#                                          ║       ╙─ 0x00000000'00000040 -> 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c008417		st2 {v23.4h, v24.4h}, [x0]
-#   v23:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v24:                 0x0000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
+#      v23<63:0>:                 0x0000000000000000 (0.000, 0.000, 0.000, 0.000)
+#      v24<63:0>:                 0x0000000000007ff9 (0.000, 0.000, 0.000, nan)
+#                                      ║   ║   ║   ╙─ 0x7ff9'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c828428		st2 {v8.4h, v9.4h}, [x1], x2
-#    v8:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v9:                 0x0000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x0040'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c9f8427		st2 {v7.4h, v8.4h}, [x1], #16
-#    v7:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v8:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v7<63:0>:                 0x0000000000000000 (0.000, 0.000, 0.000, 0.000)
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+#                                      ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c008811		st2 {v17.4s, v18.4s}, [x0]
-#   v17: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#     v17<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#     v18<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c828826		st2 {v6.4s, v7.4s}, [x1], x2
-#    v6: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v7: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#      v7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f883a		st2 {v26.4s, v27.4s}, [x1], #32
-#   v26: 0x00000000000000000000000000000000 (0.00000, 0.00000, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000fe0000000000000000 (0.00000, 3.55930e-43, 0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#     v27<127:0>: 0x00000000000000fe0000000000000000 (0.000, 3.559e-43, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x000000fe'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c00801f		st2 {v31.8b, v0.8b}, [x0]
-#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#      v31<63:0>:                 0x0000000000000000
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+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c828020		st2 {v0.8b, v1.8b}, [x1], x2
-#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v1:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#       v0<63:0>:                 0x0000000000000000
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+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f8035		st2 {v21.8b, v22.8b}, [x1], #16
-#   v21:                 0x00000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
-#   v22:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v21<63:0>:                 0x00000000ffff8007
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+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'07 -> 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'ff -> 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c008407		st2 {v7.8h, v8.8h}, [x0]
-#    v7: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v8: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c828436		st2 {v22.8h, v23.8h}, [x1], x2
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f8424		st2 {v4.8h, v5.8h}, [x1], #32
-#    v4: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v5: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0c82403d		st3 {v29.8b, v30.8b, v31.8b}, [x1], x2
-#   v29:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v30:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  0c9f403e		st3 {v30.8b, v31.8b, v0.8b}, [x1], #24
-#   v30:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v31:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    v0:                 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c004408		st3 {v8.8h, v9.8h, v10.8h}, [x0]
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-#    v9: 0x00000000000000000000000000000040 -> 0x~~~~~~~~~~~~~~~~
-#   v10: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c824432		st3 {v18.8h, v19.8h, v20.8h}, [x1], x2
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#     v19<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
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+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c9f4432		st3 {v18.8h, v19.8h, v20.8h}, [x1], #48
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#     v20<127:0>: 0x00000000000000000000000000000020 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 1.907e-06)
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+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d00281f		st3 {v31.b, v0.b, v1.b}[10], [x0]
-#   v31:           0x00                     -> 0x~~~~~~~~~~~~~~~~
-#    v0:           0x00                     -> 0x~~~~~~~~~~~~~~~~
-#    v1:           0x00                     -> 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000
+#      v0<127:0>: 0x00000000000000000000000000000000
+#      v1<127:0>: 0x00000000000000000000000000000000
+#                              ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d823424		st3 {v4.b, v5.b, v6.b}[5], [x1], x2
-#    v4:                     0x00           -> 0x~~~~~~~~~~~~~~~~
-#    v5:                     0x00           -> 0x~~~~~~~~~~~~~~~~
-#    v6:                     0x00           -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v4<127:0>: 0x00000000000000000000000000000000
+#      v5<127:0>: 0x00000000000000000000000000000000
+#      v6<127:0>: 0x00000000000000000000000000000000
+#                                        ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d9f2425		st3 {v5.b, v6.b, v7.b}[1], [x1], #3
-#    v5:                             0x00   -> 0x~~~~~~~~~~~~~~~~
-#    v6:                             0x00   -> 0x~~~~~~~~~~~~~~~~
-#    v7:                             0x00   -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v5<127:0>: 0x00000000000000000000000000000000
+#      v6<127:0>: 0x00000000000000000000000000000000
+#      v7<127:0>: 0x00000000000000000000000000000000
+#                                                ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d00a405		st3 {v5.d, v6.d, v7.d}[0], [x0]
-#    v5:                 0x0000000000000000 (d5: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#      v5<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
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+#      v7<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d82a426		st3 {v6.d, v7.d, v8.d}[0], [x1], x2
-#    v6:                 0x0000000000000000 (d6: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#      v7<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#      v8<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d9fa420		st3 {v0.d, v1.d, v2.d}[0], [x1], #24
-#    v0:                 0x0000000000000000 (d0: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v1:                 0x0000000000000000 (d1: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v2:                 0x0000000000000040 (d2: 3.16202e-322) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#      v2<127:0>: 0x00000000000000000000000000000040 (..., 3.162e-322)
+#                                                  ╙─ 0x0000000000000040'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d00701f		st3 {v31.h, v0.h, v1.h}[2], [x0]
-#   v31:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
-#    v0:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
-#    v1:                     0x0000         -> 0x~~~~~~~~~~~~~~~~
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+#      v1<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                          ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d82682e		st3 {v14.h, v15.h, v16.h}[5], [x1], x2
-#   v14:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
-#   v15:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
-#   v16:         0x0000                     -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v14<127:0>: 0x00000000000000000000000000000001 (..., 0.000, ...)
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+#     v16<127:0>: 0x00000000000000000000000000007ff9 (..., 0.000, ...)
+#                              ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d9f7035		st3 {v21.h, v22.h, v23.h}[6], [x1], #6
-#   v21:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
-#   v22:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
-#   v23:     0x0000                         -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v21<127:0>: 0x000000000000000000000000ffff8007 (..., 0.000, ...)
+#     v22<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v23<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                          ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d00a015		st3 {v21.s, v22.s, v23.s}[0], [x0]
-#   v21:                         0xffff8007 (s21: nan) -> 0x~~~~~~~~~~~~~~~~
-#   v22:                         0x00000000 (s22: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v23:                         0x00000000 (s23: 0.00000) -> 0x~~~~~~~~~~~~~~~~
+#     v21<127:0>: 0x000000000000000000000000ffff8007 (..., nan)
+#     v22<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#     v23<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x00000000'00000000'ffff8007 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d82b02b		st3 {v11.s, v12.s, v13.s}[1], [x1], x2
-#   v11:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v12:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v13:                 0xffffffff         (..., nan, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v11<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v12<127:0>: 0x000000000000000000000000ffffffff (..., 0.000, ...)
+#     v13<127:0>: 0x0000000000000000ffffffffffffffe1 (..., nan, ...)
+#                                          ╙───────── 0xffffffff'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d9fa02f		st3 {v15.s, v16.s, v17.s}[0], [x1], #12
-#   v15:                         0x00000000 (s15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v16:                         0x00007ff9 (s16: 4.59079e-41) -> 0x~~~~~~~~~~~~~~~~
-#   v17:                         0x00000000 (s17: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v15<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#     v16<127:0>: 0x00000000000000000000000000007ff9 (..., 4.591e-41)
+#     v17<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x00000000'00007ff9'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c000016		st4 {v22.16b, v23.16b, v24.16b, v25.16b}, [x0]
-#   v22: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v23: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v24: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#     v22<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'7f'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4c820038		st4 {v24.16b, v25.16b, v26.16b, v27.16b}, [x1], x2
-#   v24: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
-#   v25: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v26: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v27: 0x00000000000000fe0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xfe'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c9f002f		st4 {v15.16b, v16.16b, v17.16b, v18.16b}, [x1], #64
-#   v15: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#   v16: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
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-#    x1: 0x~~~~~~~~~~~~~~~~
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 0x~~~~~~~~~~~~~~~~  4c000c10		st4 {v16.2d, v17.2d, v18.2d, v19.2d}, [x0]
-#   v16: 0x00000000000000000000000000007ff9 (0.00000, 1.61861e-319) -> 0x~~~~~~~~~~~~~~~~
-#   v17: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#   v19: 0x00000000000000000000000000000000 (0.00000, 0.00000) -> 0x~~~~~~~~~~~~~~~~
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+#     v19<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
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+#      v4<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v5<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0da2a427		st4 {v7.d, v8.d, v9.d, v10.d}[0], [x1], x2
-#    v7:                 0x0000000000000000 (d7: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v8:                 0x0000000000000000 (d8: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    v9:                 0x0000000000000040 (d9: 3.16202e-322) -> 0x~~~~~~~~~~~~~~~~
-#   v10:                 0x0000000000000000 (d10: 0.00000) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v7<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#      v8<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#      v9<127:0>: 0x00000000000000000000000000000040 (..., 3.162e-322)
+#     v10<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000'0000000000000040'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dbfa43f		st4 {v31.d, v0.d, v1.d, v2.d}[1], [x1], #32
-#   v31: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v0: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v1: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v2: 0x0000000000000000                 (0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v31<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v0<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v1<127:0>: 0x00000000000000000000000000000000 (0.000, ...)
+#      v2<127:0>: 0x00000000000000000000000000000040 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0d206802		st4 {v2.h, v3.h, v4.h, v5.h}[1], [x0]
-#    v2:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
-#    v3:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
-#    v4:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
-#    v5:                         0x0000     -> 0x~~~~~~~~~~~~~~~~
+#      v2<127:0>: 0x00000000000000000000000000000040 (..., 0.000, ...)
+#      v3<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#      v4<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#      v5<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                              ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0da2783b		st4 {v27.h, v28.h, v29.h, v30.h}[3], [x1], x2
-#   v27:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#   v28:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#   v29:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#   v30:                 0x0000             -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (..., 0.000, ...)
+#     v28<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v29<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v30<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                      ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4dbf6038		st4 {v24.h, v25.h, v26.h, v27.h}[4], [x1], #8
-#   v24:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
-#   v25:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
-#   v26:             0x0000                 -> 0x~~~~~~~~~~~~~~~~
-#   v27:             0x00fe                 -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v24<127:0>: 0x00000000000000000000000000007ff9 (..., 0.000, ...)
+#     v25<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v26<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (..., 1.514e-05, ...)
+#                                  ╙───────────────── 0x00fe'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4d20a012		st4 {v18.s, v19.s, v20.s, v21.s}[2], [x0]
-#   v18:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v19:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v20:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v21:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
+#     v18<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v19<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v20<127:0>: 0x00000000000000000000000000000020 (..., 0.000, ...)
+#     v21<127:0>: 0x000000000000000000000000ffff8007 (..., 0.000, ...)
+#                                  ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  4da2a026		st4 {v6.s, v7.s, v8.s, v9.s}[2], [x1], x2
-#    v6:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v7:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v8:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    v9:         0x00000000                 (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#      v6<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#      v7<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#      v8<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#      v9<127:0>: 0x00000000000000000000000000000040 (..., 0.000, ...)
+#                                  ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  0dbfb039		st4 {v25.s, v26.s, v27.s, v28.s}[1], [x1], #16
-#   v25:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v26:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v27:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#   v28:                 0x00000000         (..., 0.00000, ...) -> 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
+#     v25<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v26<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#     v27<127:0>: 0x00000000000000fe0000000000000000 (..., 0.000, ...)
+#     v28<127:0>: 0x00000000000000000000000000000000 (..., 0.000, ...)
+#                                          ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  7ee2862c		sub d12, d17, d2
-#   v12: 0x0000000000000000ffffffffffffffc0
+#            v12: 0x0000000000000000ffffffffffffffc0
 0x~~~~~~~~~~~~~~~~  6e288714		sub v20.16b, v24.16b, v8.16b
-#   v20: 0x00000000000000000000000000007ff9
+#            v20: 0x00000000000000000000000000007ff9
 0x~~~~~~~~~~~~~~~~  6ee587a8		sub v8.2d, v29.2d, v5.2d
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb88782		sub v2.2s, v28.2s, v24.2s
-#    v2: 0x000000000000000000000000ffff8007
+#             v2: 0x000000000000000000000000ffff8007
 0x~~~~~~~~~~~~~~~~  2e648558		sub v24.4h, v10.4h, v4.4h
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb1849c		sub v28.4s, v4.4s, v17.4s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e228770		sub v16.8b, v27.8b, v2.8b
-#   v16: 0x000000000000000000000000010180f9
+#            v16: 0x000000000000000000000000010180f9
 0x~~~~~~~~~~~~~~~~  6e6d8554		sub v20.8h, v10.8h, v13.8h
-#   v20: 0x0000000000000000000100010001001f
+#            v20: 0x0000000000000000000100010001001f
 0x~~~~~~~~~~~~~~~~  0ead61c5		subhn v5.2s, v14.2d, v13.2d
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e6860aa		subhn v10.4h, v5.4s, v8.4s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e366146		subhn v6.8b, v10.8h, v22.8h
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2960cb		subhn2 v11.16b, v6.8h, v9.8h
-#   v11: 0x00000000000000ff0000000000000000
+#            v11: 0x00000000000000ff0000000000000000
 0x~~~~~~~~~~~~~~~~  4eb86259		subhn2 v25.4s, v18.2d, v24.2d
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6162b4		subhn2 v20.8h, v21.4s, v1.4s
-#   v20: 0x000000000000ffff000100010001001f
+#            v20: 0x000000000000ffff000100010001001f
 0x~~~~~~~~~~~~~~~~  5e203979		suqadd b25, b11
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5ee0382d		suqadd d13, d1
-#   v13: 0x0000000000000000ffffffffffffffe1
+#            v13: 0x0000000000000000ffffffffffffffe1
 0x~~~~~~~~~~~~~~~~  5e603920		suqadd h0, h9
-#    v0: 0x00000000000000000000000000000040
+#             v0: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  5ea03916		suqadd s22, s8
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e203b78		suqadd v24.16b, v27.16b
-#   v24: 0x000000000000007f0000000000000000
+#            v24: 0x000000000000007f0000000000000000
 0x~~~~~~~~~~~~~~~~  4ee039da		suqadd v26.2d, v14.2d
-#   v26: 0x00000000000000000000000000000001
+#            v26: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  0ea03947		suqadd v7.2s, v10.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e603999		suqadd v25.4h, v12.4h
-#   v25: 0x00000000000000007fff7fff7fff7fff
+#            v25: 0x00000000000000007fff7fff7fff7fff
 0x~~~~~~~~~~~~~~~~  4ea03864		suqadd v4.4s, v3.4s
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e203a4e		suqadd v14.8b, v18.8b
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  4e60391f		suqadd v31.8h, v8.8h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f20a690		sxtl v16.2d, v20.2s
-#   v16: 0x0000000000010001000000000001001f
+#            v16: 0x0000000000010001000000000001001f
 0x~~~~~~~~~~~~~~~~  0f10a79b		sxtl v27.4s, v28.4h
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f08a6c0		sxtl v0.8h, v22.8b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f20a4e6		sxtl2 v6.2d, v7.4s
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f10a769		sxtl2 v9.4s, v27.8h
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f08a610		sxtl2 v16.8h, v16.16b
-#   v16: 0x00000000000000000000000100000001
+#            v16: 0x00000000000000000000000100000001
 0x~~~~~~~~~~~~~~~~  4e166239		tbl v25.16b, {v17.16b, v18.16b, v19.16b, v20.16b}, v22.16b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e0441bc		tbl v28.16b, {v13.16b, v14.16b, v15.16b}, v4.16b
-#   v28: 0xe1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1
+#            v28: 0xe1e1e1e1e1e1e1e1e1e1e1e1e1e1e1e1
 0x~~~~~~~~~~~~~~~~  4e022003		tbl v3.16b, {v0.16b, v1.16b}, v2.16b
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e0401f4		tbl v20.16b, {v15.16b}, v4.16b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1462e7		tbl v7.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v20.8b
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1f4028		tbl v8.8b, {v1.16b, v2.16b, v3.16b}, v31.8b
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e102328		tbl v8.8b, {v25.16b, v26.16b}, v16.8b
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1e026b		tbl v11.8b, {v19.16b}, v30.8b
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e057339		tbx v25.16b, {v25.16b, v26.16b, v27.16b, v28.16b}, v5.16b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e1853b5		tbx v21.16b, {v29.16b, v30.16b, v31.16b}, v24.16b
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e013206		tbx v6.16b, {v16.16b, v17.16b}, v1.16b
-#    v6: 0x01010101010101010101010101010101
+#             v6: 0x01010101010101010101010101010101
 0x~~~~~~~~~~~~~~~~  4e14106d		tbx v13.16b, {v3.16b}, v20.16b
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e0973b8		tbx v24.8b, {v29.16b, v30.16b, v31.16b, v0.16b}, v9.8b
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1a5131		tbx v17.8b, {v9.16b, v10.16b, v11.16b}, v26.8b
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e153065		tbx v5.8b, {v3.16b, v4.16b}, v21.8b
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1d1170		tbx v16.8b, {v11.16b}, v29.8b
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e0c2b13		trn1 v19.16b, v24.16b, v12.16b
-#   v19: 0x0000000000000000ff00ff00ff00c000
+#            v19: 0x0000000000000000ff00ff00ff00c000
 0x~~~~~~~~~~~~~~~~  4eca28e2		trn1 v2.2d, v7.2d, v10.2d
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e952816		trn1 v22.2s, v0.2s, v21.2s
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e5429ec		trn1 v12.4h, v15.4h, v20.4h
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e892a3e		trn1 v30.4s, v17.4s, v9.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e1d2a6c		trn1 v12.8b, v19.8b, v29.8b
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e492917		trn1 v23.8h, v8.8h, v9.8h
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e196bdc		trn2 v28.16b, v30.16b, v25.16b
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ec76b67		trn2 v7.2d, v27.2d, v7.2d
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e936a1e		trn2 v30.2s, v16.2s, v19.2s
-#   v30: 0x0000000000000000ff00ff0000000000
+#            v30: 0x0000000000000000ff00ff0000000000
 0x~~~~~~~~~~~~~~~~  0e5968d8		trn2 v24.4h, v6.4h, v25.4h
-#   v24: 0x00000000000000000000010100000101
+#            v24: 0x00000000000000000000010100000101
 0x~~~~~~~~~~~~~~~~  4e8b6a62		trn2 v2.4s, v19.4s, v11.4s
-#    v2: 0x000000000000000000000000ff00ff00
+#             v2: 0x000000000000000000000000ff00ff00
 0x~~~~~~~~~~~~~~~~  0e126b79		trn2 v25.8b, v27.8b, v18.8b
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e4f688c		trn2 v12.8h, v4.8h, v15.8h
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e3c7d9f		uaba v31.16b, v12.16b, v28.16b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eae7cb2		uaba v18.2s, v5.2s, v14.2s
-#   v18: 0x00000000000000000000000000000001
+#            v18: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  2e757e89		uaba v9.4h, v20.4h, v21.4h
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea27e86		uaba v6.4s, v20.4s, v2.4s
-#    v6: 0x01010101010101010101010100020001
+#             v6: 0x01010101010101010101010100020001
 0x~~~~~~~~~~~~~~~~  2e257d90		uaba v16.8b, v12.8b, v5.8b
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7e7f4f		uaba v15.8h, v26.8h, v30.8h
-#   v15: 0x0000000000000000ff00ff0000000001
+#            v15: 0x0000000000000000ff00ff0000000001
 0x~~~~~~~~~~~~~~~~  2eaf524a		uabal v10.2d, v18.2s, v15.2s
-#   v10: 0x00000000ff00ff000000000000000000
+#            v10: 0x00000000ff00ff000000000000000000
 0x~~~~~~~~~~~~~~~~  2e67527e		uabal v30.4s, v19.4h, v7.4h
-#   v30: 0x0000ff000000ff00ff01fe000000c000
+#            v30: 0x0000ff000000ff00ff01fe000000c000
 0x~~~~~~~~~~~~~~~~  2e205364		uabal v4.8h, v27.8b, v0.8b
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea25193		uabal2 v19.2d, v12.4s, v2.4s
-#   v19: 0x0000000000000000ff00ff00ff00c000
+#            v19: 0x0000000000000000ff00ff00ff00c000
 0x~~~~~~~~~~~~~~~~  6e6c50ba		uabal2 v26.4s, v5.8h, v12.8h
-#   v26: 0x00000000000000000000000000000001
+#            v26: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  6e3c5293		uabal2 v19.8h, v20.16b, v28.16b
-#   v19: 0x0000000000000000ff00ff00ff00c000
+#            v19: 0x0000000000000000ff00ff00ff00c000
 0x~~~~~~~~~~~~~~~~  6e357492		uabd v18.16b, v4.16b, v21.16b
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb076be		uabd v30.2s, v21.2s, v16.2s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e797788		uabd v8.4h, v28.4h, v25.4h
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb5759c		uabd v28.4s, v12.4s, v21.4s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3c7613		uabd v19.8b, v16.8b, v28.8b
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7d7589		uabd v9.8h, v12.8h, v29.8h
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea8701a		uabdl v26.2d, v0.2s, v8.2s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e7973fd		uabdl v29.4s, v31.4h, v25.4h
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e2e73bb		uabdl v27.8h, v29.8b, v14.8b
-#   v27: 0x00000000000000000000000000000001
+#            v27: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  6ea87294		uabdl2 v20.2d, v20.4s, v8.4s
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7271f6		uabdl2 v22.4s, v15.8h, v18.8h
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e377249		uabdl2 v9.8h, v18.16b, v23.16b
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea069e9		uadalp v9.1d, v15.2s
-#    v9: 0x000000000000000000000000ff00ff01
+#             v9: 0x000000000000000000000000ff00ff01
 0x~~~~~~~~~~~~~~~~  6ea0698e		uadalp v14.2d, v12.4s
-#   v14: 0x00000000000000000000000000000001
+#            v14: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  2e60699c		uadalp v28.2s, v12.4h
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e206a20		uadalp v0.4h, v17.8b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e606ba1		uadalp v1.4s, v29.8h
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e206acf		uadalp v15.8h, v22.16b
-#   v15: 0x0000000000000000ff00ff0000000001
+#            v15: 0x0000000000000000ff00ff0000000001
 0x~~~~~~~~~~~~~~~~  2ebb0281		uaddl v1.2d, v20.2s, v27.2s
-#    v1: 0x00000000000000000000000000000001
+#             v1: 0x00000000000000000000000000000001
 0x~~~~~~~~~~~~~~~~  2e65033f		uaddl v31.4s, v25.4h, v5.4h
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e23006c		uaddl v12.8h, v3.8b, v3.8b
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea602e5		uaddl2 v5.2d, v23.4s, v6.4s
-#    v5: 0x00000000010101010000000001010101
+#             v5: 0x00000000010101010000000001010101
 0x~~~~~~~~~~~~~~~~  6e7900a1		uaddl2 v1.4s, v5.8h, v25.8h
-#    v1: 0x00000000000000000000010100000101
+#             v1: 0x00000000000000000000010100000101
 0x~~~~~~~~~~~~~~~~  6e3c03d6		uaddl2 v22.8h, v30.16b, v28.16b
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea02927		uaddlp v7.1d, v9.2s
-#    v7: 0x000000000000000000000000ff00ff01
+#             v7: 0x000000000000000000000000ff00ff01
 0x~~~~~~~~~~~~~~~~  6ea0289a		uaddlp v26.2d, v4.4s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e60283c		uaddlp v28.2s, v1.4h
-#   v28: 0x00000000000000000000010100000101
+#            v28: 0x00000000000000000000010100000101
 0x~~~~~~~~~~~~~~~~  2e202bf4		uaddlp v20.4h, v31.8b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e602a30		uaddlp v16.4s, v17.8h
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e202846		uaddlp v6.8h, v2.16b
-#    v6: 0x00000000000000000000000000ff00ff
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 0x~~~~~~~~~~~~~~~~  6eb03adc		uaddlv d28, v22.4s
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 0x~~~~~~~~~~~~~~~~  6e303a60		uaddlv h0, v19.16b
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 0x~~~~~~~~~~~~~~~~  2e303bde		uaddlv h30, v30.8b
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 0x~~~~~~~~~~~~~~~~  2e703a58		uaddlv s24, v18.4h
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 0x~~~~~~~~~~~~~~~~  6e70380a		uaddlv s10, v0.8h
-#   v10: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2eae1229		uaddw v9.2d, v17.2d, v14.2s
-#    v9: 0x00000000000000000000000000000001
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 0x~~~~~~~~~~~~~~~~  2e631329		uaddw v9.4s, v25.4s, v3.4h
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 0x~~~~~~~~~~~~~~~~  2e201032		uaddw v18.8h, v1.8h, v0.8b
-#   v18: 0x00000000000000000000010100000101
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 0x~~~~~~~~~~~~~~~~  6ea610b2		uaddw2 v18.2d, v5.2d, v6.4s
-#   v18: 0x00000000010101010000000001010101
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 0x~~~~~~~~~~~~~~~~  6e6b11f1		uaddw2 v17.4s, v15.4s, v11.8h
-#   v17: 0x0000000000000000ff00ff0000000001
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 0x~~~~~~~~~~~~~~~~  6e27117d		uaddw2 v29.8h, v11.8h, v7.16b
-#   v29: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e23052d		uhadd v13.16b, v9.16b, v3.16b
-#   v13: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2eb80731		uhadd v17.2s, v25.2s, v24.2s
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 0x~~~~~~~~~~~~~~~~  2e6d06f9		uhadd v25.4h, v23.4h, v13.4h
-#   v25: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6eb00680		uhadd v0.4s, v20.4s, v16.4s
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 0x~~~~~~~~~~~~~~~~  2e3904a5		uhadd v5.8b, v5.8b, v25.8b
-#    v5: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e7207a3		uhadd v3.8h, v29.8h, v18.8h
-#    v3: 0x00000000008000800000000000800080
+#             v3: 0x00000000008000800000000000800080
 0x~~~~~~~~~~~~~~~~  6e2d26c1		uhsub v1.16b, v22.16b, v13.16b
-#    v1: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2ebe27ce		uhsub v14.2s, v30.2s, v30.2s
-#   v14: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e7125dd		uhsub v29.4h, v14.4h, v17.4h
-#   v29: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6eb224ba		uhsub v26.4s, v5.4s, v18.4s
-#   v26: 0x00000000ff7f7f7f00000000ff7f7f7f
+#            v26: 0x00000000ff7f7f7f00000000ff7f7f7f
 0x~~~~~~~~~~~~~~~~  2e2c24e3		uhsub v3.8b, v7.8b, v12.8b
-#    v3: 0x0000000000000000000000007f007f00
+#             v3: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6e6526b9		uhsub v25.8h, v21.8h, v5.8h
-#   v25: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e26659c		umax v28.16b, v12.16b, v6.16b
-#   v28: 0x00000000000000000000000000ff00ff
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 0x~~~~~~~~~~~~~~~~  2eba6674		umax v20.2s, v19.2s, v26.2s
-#   v20: 0x000000000000000000000000ff7f7f7f
+#            v20: 0x000000000000000000000000ff7f7f7f
 0x~~~~~~~~~~~~~~~~  2e7267e0		umax v0.4h, v31.4h, v18.4h
-#    v0: 0x00000000000000000000000001010101
+#             v0: 0x00000000000000000000000001010101
 0x~~~~~~~~~~~~~~~~  6ebc66a6		umax v6.4s, v21.4s, v28.4s
-#    v6: 0x00000000000000000000000000ff00ff
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 0x~~~~~~~~~~~~~~~~  2e346440		umax v0.8b, v2.8b, v20.8b
-#    v0: 0x000000000000000000000000ff7fff7f
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 0x~~~~~~~~~~~~~~~~  6e766564		umax v4.8h, v11.8h, v22.8h
-#    v4: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e3da4c1		umaxp v1.16b, v6.16b, v29.16b
-#    v1: 0x0000000000000000000000000000ffff
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 0x~~~~~~~~~~~~~~~~  2ebba633		umaxp v19.2s, v17.2s, v27.2s
-#   v19: 0x00000000000000000000000100000000
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 0x~~~~~~~~~~~~~~~~  2e67a615		umaxp v21.4h, v16.4h, v7.4h
-#   v21: 0x00000000000000000000ff0100000000
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 0x~~~~~~~~~~~~~~~~  6ebda689		umaxp v9.4s, v20.4s, v29.4s
-#    v9: 0x000000000000000000000000ff7f7f7f
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 0x~~~~~~~~~~~~~~~~  2e30a42d		umaxp v13.8b, v1.8b, v16.8b
-#   v13: 0x000000000000000000000000000000ff
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 0x~~~~~~~~~~~~~~~~  6e7aa6f3		umaxp v19.8h, v23.8h, v26.8h
-#   v19: 0x0000ff7f0000ff7f0000000000000000
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 0x~~~~~~~~~~~~~~~~  6e30abd1		umaxv b17, v30.16b
-#   v17: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e30a997		umaxv b23, v12.8b
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 0x~~~~~~~~~~~~~~~~  2e70a9ff		umaxv h31, v15.4h
-#   v31: 0x0000000000000000000000000000ff00
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 0x~~~~~~~~~~~~~~~~  6e70ab2f		umaxv h15, v25.8h
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 0x~~~~~~~~~~~~~~~~  6eb0aab2		umaxv s18, v21.4s
-#   v18: 0x0000000000000000000000000000ff01
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 0x~~~~~~~~~~~~~~~~  6e326c16		umin v22.16b, v0.16b, v18.16b
-#   v22: 0x0000000000000000000000000000ff01
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 0x~~~~~~~~~~~~~~~~  2eb06ea1		umin v1.2s, v21.2s, v16.2s
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 0x~~~~~~~~~~~~~~~~  2e796c91		umin v17.4h, v4.4h, v25.4h
-#   v17: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6ead6f58		umin v24.4s, v26.4s, v13.4s
-#   v24: 0x000000000000000000000000000000ff
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 0x~~~~~~~~~~~~~~~~  2e256c34		umin v20.8b, v1.8b, v5.8b
-#   v20: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e776f3a		umin v26.8h, v25.8h, v23.8h
-#   v26: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e37ac25		uminp v5.16b, v1.16b, v23.16b
-#    v5: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2ebeaf47		uminp v7.2s, v26.2s, v30.2s
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 0x~~~~~~~~~~~~~~~~  2e79aca9		uminp v9.4h, v5.4h, v25.4h
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 0x~~~~~~~~~~~~~~~~  6ea1ad57		uminp v23.4s, v10.4s, v1.4s
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 0x~~~~~~~~~~~~~~~~  2e2eafa4		uminp v4.8b, v29.8b, v14.8b
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 0x~~~~~~~~~~~~~~~~  6e6eac15		uminp v21.8h, v0.8h, v14.8h
-#   v21: 0x0000000000000000000000000000ff7f
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 0x~~~~~~~~~~~~~~~~  6e31aa20		uminv b0, v17.16b
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 0x~~~~~~~~~~~~~~~~  2e31abe0		uminv b0, v31.8b
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 0x~~~~~~~~~~~~~~~~  2e71a818		uminv h24, v0.4h
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 0x~~~~~~~~~~~~~~~~  6e71a9dd		uminv h29, v14.8h
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 0x~~~~~~~~~~~~~~~~  6eb1a87e		uminv s30, v3.4s
-#   v30: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2eb8816b		umlal v11.2d, v11.2s, v24.2s
-#   v11: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2fab2a1e		umlal v30.2d, v16.2s, v11.s[3]
-#   v30: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e7a8120		umlal v0.4s, v9.4h, v26.4h
-#    v0: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2f4c2b14		umlal v20.4s, v24.4h, v12.h[4]
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 0x~~~~~~~~~~~~~~~~  2e2682b0		umlal v16.8h, v21.8b, v6.8b
-#   v16: 0x00000000000000000000000000007e81
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 0x~~~~~~~~~~~~~~~~  6eb78271		umlal2 v17.2d, v19.4s, v23.4s
-#   v17: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6f8823c5		umlal2 v5.2d, v30.4s, v8.s[0]
-#    v5: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e6f8110		umlal2 v16.4s, v8.8h, v15.8h
-#   v16: 0x00000000000000000000000000007e81
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 0x~~~~~~~~~~~~~~~~  6f512b4f		umlal2 v15.4s, v26.8h, v1.h[5]
-#   v15: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e31803e		umlal2 v30.8h, v1.16b, v17.16b
-#   v30: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2ebca272		umlsl v18.2d, v19.2s, v28.2s
-#   v18: 0x0000000000000000000000000000ff01
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 0x~~~~~~~~~~~~~~~~  2f8860e7		umlsl v7.2d, v7.2s, v8.s[0]
-#    v7: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e64a118		umlsl v24.4s, v8.4h, v4.4h
-#   v24: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2f4c6ad2		umlsl v18.4s, v22.4h, v12.h[4]
-#   v18: 0x0000000000000000000000000000ff01
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 0x~~~~~~~~~~~~~~~~  2e34a1dc		umlsl v28.8h, v14.8b, v20.8b
-#   v28: 0x00000000000000000000000000ff00ff
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 0x~~~~~~~~~~~~~~~~  6ea9a00b		umlsl2 v11.2d, v0.4s, v9.4s
-#   v11: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6f896a1a		umlsl2 v26.2d, v16.4s, v9.s[2]
-#   v26: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e69a163		umlsl2 v3.4s, v11.8h, v9.8h
-#    v3: 0x0000000000000000000000007f007f00
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 0x~~~~~~~~~~~~~~~~  6f496b2a		umlsl2 v10.4s, v25.8h, v9.h[4]
-#   v10: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e3ca218		umlsl2 v24.8h, v16.16b, v28.16b
-#   v24: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  4e183f3e		mov x30, v25.d[1]
-#    lr: 0x0000000000000000
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 0x~~~~~~~~~~~~~~~~  2ebdc14c		umull v12.2d, v10.2s, v29.2s
-#   v12: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2fa5abd6		umull v22.2d, v30.2s, v5.s[3]
-#   v22: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e79c007		umull v7.4s, v0.4h, v25.4h
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 0x~~~~~~~~~~~~~~~~  2f63a1ab		umull v11.4s, v13.4h, v3.h[2]
-#   v11: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e2ac219		umull v25.8h, v16.8b, v10.8b
-#   v25: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6ebac071		umull2 v17.2d, v3.4s, v26.4s
-#   v17: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6fa2a97a		umull2 v26.2d, v11.4s, v2.s[3]
-#   v26: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e77c22c		umull2 v12.4s, v17.8h, v23.8h
-#   v12: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6f61a3e4		umull2 v4.4s, v31.8h, v1.h[2]
-#    v4: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e31c185		umull2 v5.8h, v12.16b, v17.16b
-#    v5: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7e3c0c9e		uqadd b30, b4, b28
-#   v30: 0x000000000000000000000000000000ff
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 0x~~~~~~~~~~~~~~~~  7ef00e9b		uqadd d27, d20, d16
-#   v27: 0x00000000000000000000000000007e81
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 0x~~~~~~~~~~~~~~~~  7e7c0dc7		uqadd h7, h14, h28
-#    v7: 0x000000000000000000000000000000ff
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 0x~~~~~~~~~~~~~~~~  7ea40e3c		uqadd s28, s17, s4
-#   v28: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e350ed3		uqadd v19.16b, v22.16b, v21.16b
-#   v19: 0x0000000000000000000000000000ff7f
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 0x~~~~~~~~~~~~~~~~  6eeb0c90		uqadd v16.2d, v4.2d, v11.2d
-#   v16: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2ea40dd4		uqadd v20.2s, v14.2s, v4.2s
-#   v20: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e700c05		uqadd v5.4h, v0.4h, v16.4h
-#    v5: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6ea90ff5		uqadd v21.4s, v31.4s, v9.4s
-#   v21: 0x0000000000000000000000000000ff00
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 0x~~~~~~~~~~~~~~~~  2e230f17		uqadd v23.8b, v24.8b, v3.8b
-#   v23: 0x0000000000000000000000007f007f00
+#            v23: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6e6b0f71		uqadd v17.8h, v27.8h, v11.8h
-#   v17: 0x00000000000000000000000000007e81
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 0x~~~~~~~~~~~~~~~~  7e2a5eca		uqrshl b10, b22, b10
-#   v10: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7eeb5cbd		uqrshl d29, d5, d11
-#   v29: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7e7e5f1b		uqrshl h27, h24, h30
-#   v27: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7ea85daa		uqrshl s10, s13, s8
-#   v10: 0x000000000000000000000000000000ff
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 0x~~~~~~~~~~~~~~~~  6e2e5e49		uqrshl v9.16b, v18.16b, v14.16b
-#    v9: 0x0000000000000000000000000000ff01
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 0x~~~~~~~~~~~~~~~~  6ef15df8		uqrshl v24.2d, v15.2d, v17.2d
-#   v24: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2ebb5dc4		uqrshl v4.2s, v14.2s, v27.2s
-#    v4: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e685caf		uqrshl v15.4h, v5.4h, v8.4h
-#   v15: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6ea05fb5		uqrshl v21.4s, v29.4s, v0.4s
-#   v21: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e295f10		uqrshl v16.8b, v24.8b, v9.8b
-#   v16: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e6f5c02		uqrshl v2.8h, v0.8h, v15.8h
-#    v2: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7f0c9f4b		uqrshrn b11, h26, #4
-#   v11: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7f1b9fc7		uqrshrn h7, s30, #5
-#    v7: 0x00000000000000000000000000000008
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 0x~~~~~~~~~~~~~~~~  7f2b9d0a		uqrshrn s10, d8, #21
-#   v10: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2f359ccf		uqrshrn v15.2s, v6.2d, #11
-#   v15: 0x00000000000000000000000000001fe0
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 0x~~~~~~~~~~~~~~~~  2f149f45		uqrshrn v5.4h, v26.4s, #12
-#    v5: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2f0b9f3c		uqrshrn v28.8b, v25.8h, #5
-#   v28: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6f0e9fd9		uqrshrn2 v25.16b, v30.8h, #2
-#   v25: 0x00000000000000400000000000000000
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 0x~~~~~~~~~~~~~~~~  6f209dd5		uqrshrn2 v21.4s, v14.2d, #32
-#   v21: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6f1e9ced		uqrshrn2 v13.8h, v7.4s, #2
-#   v13: 0x000000000000000200000000000000ff
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 0x~~~~~~~~~~~~~~~~  7e374c0d		uqshl b13, b0, b23
-#   v13: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7f0c7629		uqshl b9, b17, #4
-#    v9: 0x000000000000000000000000000000ff
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 0x~~~~~~~~~~~~~~~~  7ee44cd7		uqshl d23, d6, d4
-#   v23: 0x00000000000000000000000000ff00ff
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 0x~~~~~~~~~~~~~~~~  7f6c7568		uqshl d8, d11, #44
-#    v8: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7e6f4db3		uqshl h19, h13, h15
-#   v19: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7f167759		uqshl h25, h26, #6
-#   v25: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7eaa4f04		uqshl s4, s24, s10
-#    v4: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7f2175d3		uqshl s19, s14, #1
-#   v19: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e394fce		uqshl v14.16b, v30.16b, v25.16b
-#   v14: 0x000000000000000000000000000000ff
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 0x~~~~~~~~~~~~~~~~  6f0d7546		uqshl v6.16b, v10.16b, #5
-#    v6: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6ee74d12		uqshl v18.2d, v8.2d, v7.2d
-#   v18: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6f5275d9		uqshl v25.2d, v14.2d, #18
-#   v25: 0x00000000000000000000000003fc0000
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 0x~~~~~~~~~~~~~~~~  2eb74e19		uqshl v25.2s, v16.2s, v23.2s
-#   v25: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2f3f75ed		uqshl v13.2s, v15.2s, #31
-#   v13: 0x000000000000000000000000ffffffff
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 0x~~~~~~~~~~~~~~~~  2e6f4f1c		uqshl v28.4h, v24.4h, v15.4h
-#   v28: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2f117624		uqshl v4.4h, v17.4h, #1
-#    v4: 0x0000000000000000000000000000fd02
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 0x~~~~~~~~~~~~~~~~  6eb74fe9		uqshl v9.4s, v31.4s, v23.4s
-#    v9: 0x00000000000000000000000000007f80
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 0x~~~~~~~~~~~~~~~~  6f3f7792		uqshl v18.4s, v28.4s, #31
-#   v18: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2e2f4ebf		uqshl v31.8b, v21.8b, v15.8b
-#   v31: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  2f0976a6		uqshl v6.8b, v21.8b, #1
-#    v6: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6e714c5c		uqshl v28.8h, v2.8h, v17.8h
-#   v28: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  6f1e7518		uqshl v24.8h, v8.8h, #14
-#   v24: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7f099775		uqshrn b21, h27, #7
-#   v21: 0x00000000000000000000000000000000
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 0x~~~~~~~~~~~~~~~~  7f15975c		uqshrn h28, s26, #11
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f2f97ed		uqshrn s13, d31, #17
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f389615		uqshrn v21.2s, v16.2d, #8
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f1e9718		uqshrn v24.4h, v24.4s, #2
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f089425		uqshrn v5.8b, v1.8h, #8
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0a97b0		uqshrn2 v16.16b, v29.8h, #6
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f3f94c2		uqshrn2 v2.4s, v6.2d, #1
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f129550		uqshrn2 v16.8h, v10.4s, #14
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e3a2e9c		uqsub b28, b20, b26
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eea2ce0		uqsub d0, d7, d10
-#    v0: 0x00000000000000000000000000000008
+#             v0: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  7e672f1a		uqsub h26, h24, h7
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eb02ef7		uqsub s23, s23, s16
-#   v23: 0x00000000000000000000000000ff00ff
+#            v23: 0x00000000000000000000000000ff00ff
 0x~~~~~~~~~~~~~~~~  6e382e0e		uqsub v14.16b, v16.16b, v24.16b
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee62e2b		uqsub v11.2d, v17.2d, v6.2d
-#   v11: 0x00000000000000000000000000007e81
+#            v11: 0x00000000000000000000000000007e81
 0x~~~~~~~~~~~~~~~~  2ea82d4a		uqsub v10.2s, v10.2s, v8.2s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e6c2de9		uqsub v9.4h, v15.4h, v12.4h
-#    v9: 0x00000000000000000000000000001fe0
+#             v9: 0x00000000000000000000000000001fe0
 0x~~~~~~~~~~~~~~~~  6ea72e57		uqsub v23.4s, v18.4s, v7.4s
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e312e69		uqsub v9.8b, v19.8b, v17.8b
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e662c54		uqsub v20.8h, v2.8h, v6.8h
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e214a7d		uqxtn b29, h19
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e6149a0		uqxtn h0, s13
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ea14ada		uqxtn s26, d22
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea14be5		uqxtn v5.2s, v31.2d
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e614a7e		uqxtn v30.4h, v19.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e21484f		uqxtn v15.8b, v2.8h
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21487d		uqxtn2 v29.16b, v3.8h
-#   v29: 0x000000000000ffff0000000000000000
+#            v29: 0x000000000000ffff0000000000000000
 0x~~~~~~~~~~~~~~~~  6ea14a2d		uqxtn2 v13.4s, v17.2d
-#   v13: 0x0000000000007e810000000000000000
+#            v13: 0x0000000000007e810000000000000000
 0x~~~~~~~~~~~~~~~~  6e61497c		uqxtn2 v28.8h, v11.4s
-#   v28: 0x0000000000007e810000000000000000
+#            v28: 0x0000000000007e810000000000000000
 0x~~~~~~~~~~~~~~~~  0ea1c9f7		urecpe v23.2s, v15.2s
-#   v23: 0x0000000000000000ffffffffffffffff
+#            v23: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4ea1c8fb		urecpe v27.4s, v7.4s
-#   v27: 0xffffffffffffffffffffffffffffffff
+#            v27: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e3b15e2		urhadd v2.16b, v15.16b, v27.16b
-#    v2: 0x80808080808080808080808080808080
+#             v2: 0x80808080808080808080808080808080
 0x~~~~~~~~~~~~~~~~  2eb2142f		urhadd v15.2s, v1.2s, v18.2s
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e7a1491		urhadd v17.4h, v4.4h, v26.4h
-#   v17: 0x00000000000000000000000000007e81
+#            v17: 0x00000000000000000000000000007e81
 0x~~~~~~~~~~~~~~~~  6eae1762		urhadd v2.4s, v27.4s, v14.4s
-#    v2: 0x80000000800000008000000080000000
+#             v2: 0x80000000800000008000000080000000
 0x~~~~~~~~~~~~~~~~  2e2e1625		urhadd v5.8b, v17.8b, v14.8b
-#    v5: 0x00000000000000000000000000003f41
+#             v5: 0x00000000000000000000000000003f41
 0x~~~~~~~~~~~~~~~~  6e79145e		urhadd v30.8h, v2.8h, v25.8h
-#   v30: 0x40000000400000004000000040000000
+#            v30: 0x40000000400000004000000040000000
 0x~~~~~~~~~~~~~~~~  7efe5784		urshl d4, d28, d30
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e3357ed		urshl v13.16b, v31.16b, v19.16b
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ef556ee		urshl v14.2d, v23.2d, v21.2d
-#   v14: 0x0000000000000000ffffffffffffffff
+#            v14: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ea854ea		urshl v10.2s, v7.2s, v8.2s
-#   v10: 0x00000000000000000000000000000008
+#            v10: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  2e7c56af		urshl v15.4h, v21.4h, v28.4h
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb7551e		urshl v30.4s, v8.4s, v23.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e25569f		urshl v31.8b, v20.8b, v5.8b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7e577e		urshl v30.8h, v27.8h, v30.8h
-#   v30: 0xffffffffffffffffffffffffffffffff
+#            v30: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7f4f25a4		urshr d4, d13, #49
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0f2682		urshr v2.16b, v20.16b, #1
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f4d256d		urshr v13.2d, v11.2d, #51
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f3627f5		urshr v21.2s, v31.2s, #10
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f152635		urshr v21.4h, v17.4h, #11
-#   v21: 0x00000000000000000000000000000010
+#            v21: 0x00000000000000000000000000000010
 0x~~~~~~~~~~~~~~~~  6f3f26c4		urshr v4.4s, v22.4s, #1
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f092420		urshr v0.8b, v1.8b, #7
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1f268d		urshr v13.8h, v20.8h, #1
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea1ca14		ursqrte v20.2s, v16.2s
-#   v20: 0x0000000000000000ffffffffffffffff
+#            v20: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ea1c91c		ursqrte v28.4s, v8.4s
-#   v28: 0xffffffffffffffffffffffffffffffff
+#            v28: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7f53361b		ursra d27, d16, #45
-#   v27: 0x0000000000000000ffffffffffffffff
+#            v27: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6f0d3632		ursra v18.16b, v17.16b, #3
-#   v18: 0x00000000000000000000000000001010
+#            v18: 0x00000000000000000000000000001010
 0x~~~~~~~~~~~~~~~~  6f46379a		ursra v26.2d, v28.2d, #58
-#   v26: 0x00000000000000400000000000000040
+#            v26: 0x00000000000000400000000000000040
 0x~~~~~~~~~~~~~~~~  2f2136c8		ursra v8.2s, v22.2s, #31
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f19349f		ursra v31.4h, v4.4h, #7
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f3e35ff		ursra v31.4s, v15.4s, #2
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0b3423		ursra v3.8b, v1.8b, #5
-#    v3: 0x0000000000000000000000007f007f00
+#             v3: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6f1335d2		ursra v18.8h, v14.8h, #13
-#   v18: 0x00000000000000000008000800081018
+#            v18: 0x00000000000000000008000800081018
 0x~~~~~~~~~~~~~~~~  7ef0441f		ushl d31, d0, d16
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e2244c0		ushl v0.16b, v6.16b, v2.16b
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ef24432		ushl v18.2d, v1.2d, v18.2d
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ebd44fb		ushl v27.2s, v7.2s, v29.2s
-#   v27: 0x00000000000000000000000000000008
+#            v27: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  2e6d45ce		ushl v14.4h, v14.4h, v13.4h
-#   v14: 0x0000000000000000ffffffffffffffff
+#            v14: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ea94496		ushl v22.4s, v4.4s, v9.4s
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e3b46d7		ushl v23.8b, v22.8b, v27.8b
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e684735		ushl v21.8h, v25.8h, v8.8h
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f35a40b		ushll v11.2d, v0.2s, #21
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f18a622		ushll v2.4s, v17.4h, #8
-#    v2: 0x000000000000000000000000007e8100
+#             v2: 0x000000000000000000000000007e8100
 0x~~~~~~~~~~~~~~~~  2f09a5cb		ushll v11.8h, v14.8b, #1
-#   v11: 0x01fe01fe01fe01fe01fe01fe01fe01fe
+#            v11: 0x01fe01fe01fe01fe01fe01fe01fe01fe
 0x~~~~~~~~~~~~~~~~  6f27a7a8		ushll2 v8.2d, v29.4s, #7
-#    v8: 0x000000000000000000000000007fff80
+#             v8: 0x000000000000000000000000007fff80
 0x~~~~~~~~~~~~~~~~  6f12a53d		ushll2 v29.4s, v9.8h, #2
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0ea705		ushll2 v5.8h, v24.16b, #6
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7f4b077c		ushr d28, d27, #53
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f090521		ushr v1.16b, v9.16b, #7
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f550702		ushr v2.2d, v24.2d, #43
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f35073e		ushr v30.2s, v25.2s, #11
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f14074a		ushr v10.4h, v26.4h, #12
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f2204a4		ushr v4.4s, v5.4s, #30
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f0f045e		ushr v30.8b, v2.8b, #1
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f1e0586		ushr v6.8h, v12.8h, #2
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e2038b3		usqadd b19, b5
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ee03849		usqadd d9, d2
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e603a02		usqadd h2, h16
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ea03870		usqadd s16, s3
-#   v16: 0x0000000000000000000000007f007f00
+#            v16: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  6e203bbf		usqadd v31.16b, v29.16b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee03948		usqadd v8.2d, v10.2d
-#    v8: 0x000000000000000000000000007fff80
+#             v8: 0x000000000000000000000000007fff80
 0x~~~~~~~~~~~~~~~~  2ea03932		usqadd v18.2s, v9.2s
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e6039d8		usqadd v24.4h, v14.4h
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea03bca		usqadd v10.4s, v30.4s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e203a90		usqadd v16.8b, v20.8b
-#   v16: 0x0000000000000000000000007e007e00
+#            v16: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  6e603a0c		usqadd v12.8h, v16.8h
-#   v12: 0x0000000000000000000000007e007e00
+#            v12: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  7f5b177c		usra d28, d27, #37
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f0b16c5		usra v5.16b, v22.16b, #5
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f5f1662		usra v2.2d, v19.2d, #33
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f2b1400		usra v0.2s, v0.2s, #21
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f1414c7		usra v7.4h, v6.4h, #12
-#    v7: 0x00000000000000000000000000000008
+#             v7: 0x00000000000000000000000000000008
 0x~~~~~~~~~~~~~~~~  6f371624		usra v4.4s, v17.4s, #9
-#    v4: 0x0000000000000000000000000000003f
+#             v4: 0x0000000000000000000000000000003f
 0x~~~~~~~~~~~~~~~~  2f091589		usra v9.8b, v12.8b, #7
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f121763		usra v3.8h, v27.8h, #14
-#    v3: 0x0000000000000000000000007f007f00
+#             v3: 0x0000000000000000000000007f007f00
 0x~~~~~~~~~~~~~~~~  2ebe219d		usubl v29.2d, v12.2s, v30.2s
-#   v29: 0x0000000000000000000000007e007e00
+#            v29: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  2e66239d		usubl v29.4s, v28.4h, v6.4h
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e2e208c		usubl v12.8h, v4.8b, v14.8b
-#   v12: 0xff01ff01ff01ff01ff01ff01ff01ff40
+#            v12: 0xff01ff01ff01ff01ff01ff01ff01ff40
 0x~~~~~~~~~~~~~~~~  6eb12301		usubl2 v1.2d, v24.4s, v17.4s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e632024		usubl2 v4.4s, v1.8h, v3.8h
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e272097		usubl2 v23.8h, v4.16b, v7.16b
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ebe3289		usubw v9.2d, v20.2d, v30.2s
-#    v9: 0x0000000000000000ffffffffffffffff
+#             v9: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e773214		usubw v20.4s, v16.4s, v23.4h
-#   v20: 0x0000000000000000000000007e007e00
+#            v20: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  2e3d3119		usubw v25.8h, v8.8h, v29.8b
-#   v25: 0x000000000000000000000000007fff80
+#            v25: 0x000000000000000000000000007fff80
 0x~~~~~~~~~~~~~~~~  6ea633b2		usubw2 v18.2d, v29.2d, v6.4s
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7430c6		usubw2 v6.4s, v6.4s, v20.8h
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e303092		usubw2 v18.8h, v4.8h, v16.16b
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f20a6bb		uxtl v27.2d, v21.2s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f10a7e0		uxtl v0.4s, v31.4h
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f08a55b		uxtl v27.8h, v10.8b
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f20a606		uxtl2 v6.2d, v16.4s
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f10a696		uxtl2 v22.4s, v20.8h
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f08a6b4		uxtl2 v20.8h, v21.16b
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e11193e		uzp1 v30.16b, v9.16b, v17.16b
-#   v30: 0x000000000000008100000000ffffffff
+#            v30: 0x000000000000008100000000ffffffff
 0x~~~~~~~~~~~~~~~~  4edc1b47		uzp1 v7.2d, v26.2d, v28.2d
-#    v7: 0x00000000000000000000000000000040
+#             v7: 0x00000000000000000000000000000040
 0x~~~~~~~~~~~~~~~~  0e961a1a		uzp1 v26.2s, v16.2s, v22.2s
-#   v26: 0x0000000000000000000000007e007e00
+#            v26: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  0e461a6e		uzp1 v14.4h, v19.4h, v6.4h
-#   v14: 0x00000000000000000000000000000000
+#            v14: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e9e1af1		uzp1 v17.4s, v23.4s, v30.4s
-#   v17: 0x00000081ffffffff0000000000000000
+#            v17: 0x00000081ffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  0e0d1b7c		uzp1 v28.8b, v27.8b, v13.8b
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e4c1831		uzp1 v17.8h, v1.8h, v12.8h
-#   v17: 0xff01ff01ff01ff400000000000000000
+#            v17: 0xff01ff01ff01ff400000000000000000
 0x~~~~~~~~~~~~~~~~  4e1a5a48		uzp2 v8.16b, v18.16b, v26.16b
-#    v8: 0x0000000000007e7e0000000000000000
+#             v8: 0x0000000000007e7e0000000000000000
 0x~~~~~~~~~~~~~~~~  4ed85ad5		uzp2 v21.2d, v22.2d, v24.2d
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e825ab4		uzp2 v20.2s, v21.2s, v2.2s
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e465bf0		uzp2 v16.4h, v31.4h, v6.4h
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e885979		uzp2 v25.4s, v11.4s, v8.4s
-#   v25: 0x000000000000000001fe01fe01fe01fe
+#            v25: 0x000000000000000001fe01fe01fe01fe
 0x~~~~~~~~~~~~~~~~  0e0d5bff		uzp2 v31.8b, v31.8b, v13.8b
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e415a28		uzp2 v8.8h, v17.8h, v1.8h
-#    v8: 0x0000000000000000ff01ff0100000000
+#             v8: 0x0000000000000000ff01ff0100000000
 0x~~~~~~~~~~~~~~~~  0ea12b51		xtn v17.2s, v26.2d
-#   v17: 0x0000000000000000000000007e007e00
+#            v17: 0x0000000000000000000000007e007e00
 0x~~~~~~~~~~~~~~~~  0e612803		xtn v3.4h, v0.4s
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e212912		xtn v18.8b, v8.8h
-#   v18: 0x00000000000000000000000001010000
+#            v18: 0x00000000000000000000000001010000
 0x~~~~~~~~~~~~~~~~  4e212800		xtn2 v0.16b, v0.8h
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea1288f		xtn2 v15.4s, v4.2d
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e612a5f		xtn2 v31.8h, v18.4s
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e063936		zip1 v22.16b, v9.16b, v6.16b
-#   v22: 0x00ff00ff00ff00ff00ff00ff00ff00ff
+#            v22: 0x00ff00ff00ff00ff00ff00ff00ff00ff
 0x~~~~~~~~~~~~~~~~  4ec23977		zip1 v23.2d, v11.2d, v2.2d
-#   v23: 0x000000000000000001fe01fe01fe01fe
+#            v23: 0x000000000000000001fe01fe01fe01fe
 0x~~~~~~~~~~~~~~~~  0e893a1a		zip1 v26.2s, v16.2s, v9.2s
-#   v26: 0x0000000000000000ffffffff00000000
+#            v26: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  0e473921		zip1 v1.4h, v9.4h, v7.4h
-#    v1: 0x00000000000000000000ffff0040ffff
+#             v1: 0x00000000000000000000ffff0040ffff
 0x~~~~~~~~~~~~~~~~  4e943bc0		zip1 v0.4s, v30.4s, v20.4s
-#    v0: 0x000000000000000000000000ffffffff
+#             v0: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  0e0f3a3e		zip1 v30.8b, v17.8b, v15.8b
-#   v30: 0x0000000000000000007e0000007e0000
+#            v30: 0x0000000000000000007e0000007e0000
 0x~~~~~~~~~~~~~~~~  4e423911		zip1 v17.8h, v8.8h, v2.8h
-#   v17: 0x0000ff010000ff010000000000000000
+#            v17: 0x0000ff010000ff010000000000000000
 0x~~~~~~~~~~~~~~~~  4e0b7957		zip2 v23.16b, v10.16b, v11.16b
-#   v23: 0x0100fe000100fe000100fe000100fe00
+#            v23: 0x0100fe000100fe000100fe000100fe00
 0x~~~~~~~~~~~~~~~~  4ece78de		zip2 v30.2d, v6.2d, v14.2d
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e957949		zip2 v9.2s, v10.2s, v21.2s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e5d7b08		zip2 v8.4h, v24.4h, v29.4h
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e977aa0		zip2 v0.4s, v21.4s, v23.4s
-#    v0: 0x0100fe00000000000100fe0000000000
+#             v0: 0x0100fe00000000000100fe0000000000
 0x~~~~~~~~~~~~~~~~  0e1e7af9		zip2 v25.8b, v23.8b, v30.8b
-#   v25: 0x00000000000000000001000000fe0000
+#            v25: 0x00000000000000000001000000fe0000
 0x~~~~~~~~~~~~~~~~  4e5e7947		zip2 v7.8h, v10.8h, v30.8h
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee8d723		fabd v3.2d, v25.2d, v8.2d
-#    v3: 0x00000000000000000001000000fe0000
+#             v3: 0x00000000000000000001000000fe0000
 0x~~~~~~~~~~~~~~~~  2eabd76e		fabd v14.2s, v27.2s, v11.2s
-#   v14: 0x000000000000000001fe01fe01fe01fe
+#            v14: 0x000000000000000001fe01fe01fe01fe
 0x~~~~~~~~~~~~~~~~  6eb2d6c9		fabd v9.4s, v22.4s, v18.4s
-#    v9: 0x00ff00ff00ff00ff00ff00ff0002ff01
+#             v9: 0x00ff00ff00ff00ff00ff00ff0002ff01
 0x~~~~~~~~~~~~~~~~  4ee0fba1		fabs v1.2d, v29.2d
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0faa6		fabs v6.2s, v21.2s
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea0fb2c		fabs v12.4s, v25.4s
-#   v12: 0x00000000000000000001000000fe0000
+#            v12: 0x00000000000000000001000000fe0000
 0x~~~~~~~~~~~~~~~~  6e60ecb2		facge v18.2d, v5.2d, v0.2d
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e26ed6f		facge v15.2s, v11.2s, v6.2s
-#   v15: 0x0000000000000000ffffffffffffffff
+#            v15: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e39ed5e		facge v30.4s, v10.4s, v25.4s
-#   v30: 0xffffffffffffffff0000000000000000
+#            v30: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  6effee1c		facgt v28.2d, v16.2d, v31.2d
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea4ec2f		facgt v15.2s, v1.2s, v4.2s
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eaaec76		facgt v22.4s, v3.4s, v10.4s
-#   v22: 0x0000000000000000ffffffffffffffff
+#            v22: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e78d547		fadd v7.2d, v10.2d, v24.2d
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e27d6ea		fadd v10.2s, v23.2s, v7.2s
-#   v10: 0x00000000000000000100fe000100fe00
+#            v10: 0x00000000000000000100fe000100fe00
 0x~~~~~~~~~~~~~~~~  4e2bd6d0		fadd v16.4s, v22.4s, v11.4s
-#   v16: 0x01fe01fe01fe01feffffffffffffffff
+#            v16: 0x01fe01fe01fe01feffffffffffffffff
 0x~~~~~~~~~~~~~~~~  7e70db9b		faddp d27, v28.2d
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7e30daf4		faddp s20, v23.2s
-#   v20: 0x0000000000000000000000000180fe00
+#            v20: 0x0000000000000000000000000180fe00
 0x~~~~~~~~~~~~~~~~  6e6bd495		faddp v21.2d, v4.2d, v11.2d
-#   v21: 0x020e01fe01fe01fe0000000000000000
+#            v21: 0x020e01fe01fe01fe0000000000000000
 0x~~~~~~~~~~~~~~~~  2e21d75f		faddp v31.2s, v26.2s, v1.2s
-#   v31: 0x000000000000000000000000ffffffff
+#            v31: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  6e3cd76d		faddp v13.4s, v27.4s, v28.4s
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e74e5b1		fcmeq v17.2d, v13.2d, v20.2d
-#   v17: 0xffffffffffffffff0000000000000000
+#            v17: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  4ee0da18		fcmeq v24.2d, v16.2d, #0.0
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e2ae63a		fcmeq v26.2s, v17.2s, v10.2s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0d898		fcmeq v24.2s, v4.2s, #0.0
-#   v24: 0x0000000000000000ffffffffffffffff
+#            v24: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e2ee488		fcmeq v8.4s, v4.4s, v14.4s
-#    v8: 0xffffffffffffffff0000000000000000
+#             v8: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  4ea0db3a		fcmeq v26.4s, v25.4s, #0.0
-#   v26: 0xffffffffffffffff0000000000000000
+#            v26: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  6e60e41b		fcmge v27.2d, v0.2d, v0.2d
-#   v27: 0xffffffffffffffffffffffffffffffff
+#            v27: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6ee0cbd6		fcmge v22.2d, v30.2d, #0.0
-#   v22: 0x0000000000000000ffffffffffffffff
+#            v22: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2e39e6a7		fcmge v7.2s, v21.2s, v25.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea0c9ef		fcmge v15.2s, v15.2s, #0.0
-#   v15: 0x0000000000000000ffffffffffffffff
+#            v15: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e3be49d		fcmge v29.4s, v4.4s, v27.4s
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea0cab6		fcmge v22.4s, v21.4s, #0.0
-#   v22: 0xffffffffffffffffffffffffffffffff
+#            v22: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6eefe741		fcmgt v1.2d, v26.2d, v15.2d
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee0caef		fcmgt v15.2d, v23.2d, #0.0
-#   v15: 0xffffffffffffffffffffffffffffffff
+#            v15: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ea6e615		fcmgt v21.2s, v16.2s, v6.2s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0c9a1		fcmgt v1.2s, v13.2s, #0.0
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb9e40e		fcmgt v14.4s, v0.4s, v25.4s
-#   v14: 0xffffffff00000000ffffffff00000000
+#            v14: 0xffffffff00000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  4ea0c90d		fcmgt v13.4s, v8.4s, #0.0
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee0d8c4		fcmle v4.2d, v6.2d, #0.0
-#    v4: 0xffffffffffffffffffffffffffffffff
+#             v4: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  2ea0dbf8		fcmle v24.2s, v31.2s, #0.0
-#   v24: 0x0000000000000000ffffffff00000000
+#            v24: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  6ea0dae8		fcmle v8.4s, v23.4s, #0.0
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee0e867		fcmlt v7.2d, v3.2d, #0.0
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea0eaaf		fcmlt v15.2s, v21.2s, #0.0
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea0e841		fcmlt v1.4s, v2.4s, #0.0
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e61c906		fcvtas v6.2d, v8.2d
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21c921		fcvtas v1.2s, v9.2s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21ca68		fcvtas v8.4s, v19.4s
-#    v8: 0x00000000000000000000000000000000
+#             v8: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e61cbe5		fcvtau v5.2d, v31.2d
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e21cbbc		fcvtau v28.2s, v29.2s
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21cb4b		fcvtau v11.4s, v26.4s
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e617b28		fcvtl v8.2d, v25.2s
-#    v8: 0x37a0000000000000381fc00000000000
+#             v8: 0x37a0000000000000381fc00000000000
 0x~~~~~~~~~~~~~~~~  0e2179db		fcvtl v27.4s, v14.4h
-#   v27: 0xffffe000ffffe0000000000000000000
+#            v27: 0xffffe000ffffe0000000000000000000
 0x~~~~~~~~~~~~~~~~  4e6178c1		fcvtl2 v1.2d, v6.4s
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e217938		fcvtl2 v24.4s, v9.8h
-#   v24: 0x377f0000377f0000377f0000377f0000
+#            v24: 0x377f0000377f0000377f0000377f0000
 0x~~~~~~~~~~~~~~~~  4e61bb09		fcvtms v9.2d, v24.2d
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21b967		fcvtms v7.2s, v11.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21bab7		fcvtms v23.4s, v21.4s
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e61b82d		fcvtmu v13.2d, v1.2d
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e21b99a		fcvtmu v26.2s, v12.2s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21bab5		fcvtmu v21.4s, v21.4s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e61682b		fcvtn v11.2s, v1.2d
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e216848		fcvtn v8.4h, v2.4s
-#    v8: 0x37a00000000000000000000000000000
+#             v8: 0x37a00000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e616bb8		fcvtn2 v24.4s, v29.2d
-#   v24: 0x0000000000000000377f0000377f0000
+#            v24: 0x0000000000000000377f0000377f0000
 0x~~~~~~~~~~~~~~~~  4e216944		fcvtn2 v4.8h, v10.4s
-#    v4: 0x0000000000000000ffffffffffffffff
+#             v4: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e61a959		fcvtns v25.2d, v10.2d
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21a904		fcvtns v4.2s, v8.2s
-#    v4: 0x00000000000000000000000000000000
+#             v4: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21ab7d		fcvtns v29.4s, v27.4s
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e61ab72		fcvtnu v18.2d, v27.2d
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e21a9cb		fcvtnu v11.2s, v14.2s
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21aabb		fcvtnu v27.4s, v21.4s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee1a8b7		fcvtps v23.2d, v5.2d
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea1a9f8		fcvtps v24.2s, v15.2s
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea1aa65		fcvtps v5.4s, v19.4s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee1aaa3		fcvtpu v3.2d, v21.2d
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea1aaa3		fcvtpu v3.2s, v21.2s
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea1a8e0		fcvtpu v0.4s, v7.4s
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e61697d		fcvtxn v29.2s, v11.2d
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e616b3f		fcvtxn2 v31.4s, v25.2d
-#   v31: 0x000000000000000000000000ffffffff
+#            v31: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  4ee1ba33		fcvtzs v19.2d, v17.2d
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f40ff0c		fcvtzs v12.2d, v24.2d, #64
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea1b849		fcvtzs v9.2s, v2.2s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f23fe85		fcvtzs v5.2s, v20.2s, #29
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea1bb35		fcvtzs v21.4s, v25.4s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f3afc3a		fcvtzs v26.4s, v1.4s, #6
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee1bb2d		fcvtzu v13.2d, v25.2d
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f60fdbc		fcvtzu v28.2d, v13.2d, #32
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea1b8da		fcvtzu v26.2s, v6.2s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f31fd49		fcvtzu v9.2s, v10.2s, #15
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea1b8de		fcvtzu v30.4s, v6.4s
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f2efed3		fcvtzu v19.4s, v22.4s, #18
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e6ffd0f		fdiv v15.2d, v8.2d, v15.2d
-#   v15: 0x7ff00000000000007ff8000000000000
+#            v15: 0x7ff00000000000007ff8000000000000
 0x~~~~~~~~~~~~~~~~  2e3afd2c		fdiv v12.2s, v9.2s, v26.2s
-#   v12: 0x00000000000000007fc000007fc00000
+#            v12: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  6e33fed3		fdiv v19.4s, v22.4s, v19.4s
-#   v19: 0xffffffffffffffffffffffffffffffff
+#            v19: 0xffffffffffffffffffffffffffffffff
 0x~~~~~~~~~~~~~~~~  4e68f4f3		fmax v19.2d, v7.2d, v8.2d
-#   v19: 0x37a00000000000000000000000000000
+#            v19: 0x37a00000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e3df599		fmax v25.2s, v12.2s, v29.2s
-#   v25: 0x00000000000000007fc000007fc00000
+#            v25: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  4e25f5e6		fmax v6.4s, v15.4s, v5.4s
-#    v6: 0x7ff00000000000007ff8000000000000
+#             v6: 0x7ff00000000000007ff8000000000000
 0x~~~~~~~~~~~~~~~~  4e74c510		fmaxnm v16.2d, v8.2d, v20.2d
-#   v16: 0x37a0000000000000000000000180fe00
+#            v16: 0x37a0000000000000000000000180fe00
 0x~~~~~~~~~~~~~~~~  0e39c74f		fmaxnm v15.2s, v26.2s, v25.2s
-#   v15: 0x00000000000000000000000000000000
+#            v15: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e30c5d7		fmaxnm v23.4s, v14.4s, v16.4s
-#   v23: 0x37a0000000000000000000000180fe00
+#            v23: 0x37a0000000000000000000000180fe00
 0x~~~~~~~~~~~~~~~~  7e70ca66		fmaxnmp d6, v19.2d
-#    v6: 0x000000000000000037a0000000000000
+#             v6: 0x000000000000000037a0000000000000
 0x~~~~~~~~~~~~~~~~  7e30cb5b		fmaxnmp s27, v26.2s
-#   v27: 0x00000000000000000000000000000000
+#            v27: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e77c588		fmaxnmp v8.2d, v12.2d, v23.2d
-#    v8: 0x37a00000000000007fc000007fc00000
+#             v8: 0x37a00000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  2e36c72d		fmaxnmp v13.2s, v25.2s, v22.2s
-#   v13: 0x0000000000000000ffffffff7fc00000
+#            v13: 0x0000000000000000ffffffff7fc00000
 0x~~~~~~~~~~~~~~~~  6e31c56f		fmaxnmp v15.4s, v11.4s, v17.4s
-#   v15: 0xffffffff000000000000000000000000
+#            v15: 0xffffffff000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e30ca7b		fmaxnmv s27, v19.4s
-#   v27: 0x00000000000000000000000037a00000
+#            v27: 0x00000000000000000000000037a00000
 0x~~~~~~~~~~~~~~~~  7e70f9d4		fmaxp d20, v14.2d
-#   v20: 0x0000000000000000ffffffff00000000
+#            v20: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  7e30f852		fmaxp s18, v2.2s
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e7ff6e9		fmaxp v9.2d, v23.2d, v31.2d
-#    v9: 0x00000000ffffffff37a0000000000000
+#             v9: 0x00000000ffffffff37a0000000000000
 0x~~~~~~~~~~~~~~~~  2e3ff6c7		fmaxp v7.2s, v22.2s, v31.2s
-#    v7: 0x0000000000000000ffffffffffffffff
+#             v7: 0x0000000000000000ffffffffffffffff
 0x~~~~~~~~~~~~~~~~  6e3df4f2		fmaxp v18.4s, v7.4s, v29.4s
-#   v18: 0x000000000000000000000000ffffffff
+#            v18: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  6e30fbbf		fmaxv s31, v29.4s
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee2f4a2		fmin v2.2d, v5.2d, v2.2d
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eaaf63f		fmin v31.2s, v17.2s, v10.2s
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eb0f48a		fmin v10.4s, v4.4s, v16.4s
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee5c4d5		fminnm v21.2d, v6.2d, v5.2d
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0eaec656		fminnm v22.2s, v18.2s, v14.2s
-#   v22: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ea3c7f9		fminnm v25.4s, v31.4s, v3.4s
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ef0c829		fminnmp d9, v1.2d
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eb0ca95		fminnmp s21, v20.2s
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ef3c6b0		fminnmp v16.2d, v21.2d, v19.2d
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2eb9c7f0		fminnmp v16.2s, v31.2s, v25.2s
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eafc61a		fminnmp v26.4s, v16.4s, v15.4s
-#   v26: 0x00000000000000000000000000000000
+#            v26: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb0c883		fminnmv s3, v4.4s
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7ef0fb58		fminp d24, v26.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7eb0fa27		fminp s7, v17.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee3f677		fminp v23.2d, v19.2d, v3.2d
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea9f6bd		fminp v29.2s, v21.2s, v9.2s
-#   v29: 0x00000000000000000000000000000000
+#            v29: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb5f700		fminp v0.4s, v24.4s, v21.4s
-#    v0: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6eb0f919		fminv s25, v8.4s
-#   v25: 0x0000000000000000000000007fc00000
+#            v25: 0x0000000000000000000000007fc00000
 0x~~~~~~~~~~~~~~~~  5fc91817		fmla d23, d0, v9.d[2]
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5f8711f7		fmla s23, s15, v7.s[0]
-#   v23: 0x00000000000000000000000000000000
+#            v23: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e66cd71		fmla v17.2d, v11.2d, v6.2d
-#   v17: 0xffffffffffffffff0000000000000000
+#            v17: 0xffffffffffffffff0000000000000000
 0x~~~~~~~~~~~~~~~~  4fcb13de		fmla v30.2d, v30.2d, v11.d[0]
-#   v30: 0x00000000000000000000000000000000
+#            v30: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e26cd93		fmla v19.2s, v12.2s, v6.2s
-#   v19: 0x00000000000000007fc000007fc00000
+#            v19: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  0f891238		fmla v24.2s, v17.2s, v9.s[0]
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e2bcd70		fmla v16.4s, v11.4s, v11.4s
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f891afb		fmla v27.4s, v23.4s, v9.s[2]
-#   v27: 0x00000000000000000000000037a00000
+#            v27: 0x00000000000000000000000037a00000
 0x~~~~~~~~~~~~~~~~  5fc653db		fmls d27, d30, v6.d[0]
-#   v27: 0x00000000000000000000000037a00000
+#            v27: 0x00000000000000000000000037a00000
 0x~~~~~~~~~~~~~~~~  5f825215		fmls s21, s16, v2.s[0]
-#   v21: 0x00000000000000000000000000000000
+#            v21: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ef5ce65		fmls v5.2d, v19.2d, v21.2d
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4fcc53d2		fmls v18.2d, v30.2d, v12.d[0]
-#   v18: 0x000000000000000000000000ffffffff
+#            v18: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  0ea7ce05		fmls v5.2s, v16.2s, v7.2s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0fab5243		fmls v3.2s, v18.2s, v11.s[1]
-#    v3: 0x0000000000000000000000007fffffff
+#             v3: 0x0000000000000000000000007fffffff
 0x~~~~~~~~~~~~~~~~  4ebeccbb		fmls v27.4s, v5.4s, v30.4s
-#   v27: 0x00000000000000000000000037a00000
+#            v27: 0x00000000000000000000000037a00000
 0x~~~~~~~~~~~~~~~~  4fa45a9a		fmls v26.4s, v20.4s, v4.s[3]
-#   v26: 0x00000000000000007fffffff00000000
+#            v26: 0x00000000000000007fffffff00000000
 0x~~~~~~~~~~~~~~~~  6f06f6ce		fmov v14.2d, #0xd6 (-0.3438)
-#   v14: 0xbfd6000000000000bfd6000000000000
+#            v14: 0xbfd6000000000000bfd6000000000000
 0x~~~~~~~~~~~~~~~~  0f03f5ba		fmov v26.2s, #0x6d (0.9062)
-#   v26: 0x00000000000000003f6800003f680000
+#            v26: 0x00000000000000003f6800003f680000
 0x~~~~~~~~~~~~~~~~  4f04f69f		fmov v31.4s, #0x94 (-5.0000)
-#   v31: 0xc0a00000c0a00000c0a00000c0a00000
+#            v31: 0xc0a00000c0a00000c0a00000c0a00000
 0x~~~~~~~~~~~~~~~~  9eaf033c		fmov v28.D[1], x25
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  9eae0052		fmov x18, v2.D[1]
-#   x18: 0x0000000000000000
+#            x18: 0x0000000000000000
 0x~~~~~~~~~~~~~~~~  5fc1988c		fmul d12, d4, v1.d[2]
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  5faf983e		fmul s30, s1, v15.s[3]
-#   v30: 0x000000000000000000000000ffffffff
+#            v30: 0x000000000000000000000000ffffffff
 0x~~~~~~~~~~~~~~~~  6e75dc19		fmul v25.2d, v0.2d, v21.2d
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4fca9b0a		fmul v10.2d, v24.2d, v10.d[2]
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e30df07		fmul v7.2s, v24.2s, v16.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0f849a01		fmul v1.2s, v16.2s, v4.s[2]
-#    v1: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e39df85		fmul v5.4s, v28.4s, v25.4s
-#    v5: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4f88906b		fmul v11.4s, v3.4s, v8.s[0]
-#   v11: 0x7fc000007fc000007fc000007fffffff
+#            v11: 0x7fc000007fc000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  7fc3993c		fmulx d28, d9, v3.d[2]
-#   v28: 0x00000000000000000000000000000000
+#            v28: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  7faf92b9		fmulx s25, s21, v15.s[1]
-#   v25: 0x00000000000000000000000000000000
+#            v25: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e68df9f		fmulx v31.2d, v28.2d, v8.2d
-#   v31: 0x00000000000000000000000000000000
+#            v31: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6fc692a3		fmulx v3.2d, v21.2d, v6.d[0]
-#    v3: 0x00000000000000000000000000000000
+#             v3: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e20dc29		fmulx v9.2s, v1.2s, v0.2s
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f869370		fmulx v16.2s, v27.2s, v6.s[0]
-#   v16: 0x00000000000000000000000000000000
+#            v16: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e25dc82		fmulx v2.4s, v4.4s, v5.4s
-#    v2: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6f8490f2		fmulx v18.4s, v7.4s, v4.s[0]
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee0fb21		fneg v1.2d, v25.2d
-#    v1: 0x80000000000000008000000000000000
+#             v1: 0x80000000000000008000000000000000
 0x~~~~~~~~~~~~~~~~  2ea0fbee		fneg v14.2s, v31.2s
-#   v14: 0x00000000000000008000000080000000
+#            v14: 0x00000000000000008000000080000000
 0x~~~~~~~~~~~~~~~~  6ea0f885		fneg v5.4s, v4.4s
-#    v5: 0x80000000800000008000000080000000
+#             v5: 0x80000000800000008000000080000000
 0x~~~~~~~~~~~~~~~~  4ee1d992		frecpe v18.2d, v12.2d
-#   v18: 0x7ff00000000000007ff0000000000000
+#            v18: 0x7ff00000000000007ff0000000000000
 0x~~~~~~~~~~~~~~~~  0ea1daca		frecpe v10.2s, v22.2s
-#   v10: 0x00000000000000007f8000007f800000
+#            v10: 0x00000000000000007f8000007f800000
 0x~~~~~~~~~~~~~~~~  4ea1d8c5		frecpe v5.4s, v6.4s
-#    v5: 0x7f8000007f800000474c80007f800000
+#             v5: 0x7f8000007f800000474c80007f800000
 0x~~~~~~~~~~~~~~~~  4e7afcf6		frecps v22.2d, v7.2d, v26.2d
-#   v22: 0x40000000000000004000000000000000
+#            v22: 0x40000000000000004000000000000000
 0x~~~~~~~~~~~~~~~~  0e22ff7f		frecps v31.2s, v27.2s, v2.2s
-#   v31: 0x00000000000000004000000040000000
+#            v31: 0x00000000000000004000000040000000
 0x~~~~~~~~~~~~~~~~  4e3bfcd2		frecps v18.4s, v6.4s, v27.4s
-#   v18: 0x40000000400000004000000040000000
+#            v18: 0x40000000400000004000000040000000
 0x~~~~~~~~~~~~~~~~  6e6189ba		frinta v26.2d, v13.2d
-#   v26: 0x0000000000000000ffffffff7fc00000
+#            v26: 0x0000000000000000ffffffff7fc00000
 0x~~~~~~~~~~~~~~~~  2e218b4f		frinta v15.2s, v26.2s
-#   v15: 0x0000000000000000ffffffff7fc00000
+#            v15: 0x0000000000000000ffffffff7fc00000
 0x~~~~~~~~~~~~~~~~  6e218a0d		frinta v13.4s, v16.4s
-#   v13: 0x00000000000000000000000000000000
+#            v13: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee19989		frinti v9.2d, v12.2d
-#    v9: 0x00000000000000000000000000000000
+#             v9: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea19a65		frinti v5.2s, v19.2s
-#    v5: 0x00000000000000007fc000007fc00000
+#             v5: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  6ea1996f		frinti v15.4s, v11.4s
-#   v15: 0x7fc000007fc000007fc000007fffffff
+#            v15: 0x7fc000007fc000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  4e619bb1		frintm v17.2d, v29.2d
-#   v17: 0x00000000000000000000000000000000
+#            v17: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21997e		frintm v30.2s, v11.2s
-#   v30: 0x00000000000000007fc000007fffffff
+#            v30: 0x00000000000000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  4e219a81		frintm v1.4s, v20.4s
-#    v1: 0x0000000000000000ffffffff00000000
+#             v1: 0x0000000000000000ffffffff00000000
 0x~~~~~~~~~~~~~~~~  4e6188d8		frintn v24.2d, v6.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e218a2c		frintn v12.2s, v17.2s
-#   v12: 0x00000000000000000000000000000000
+#            v12: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21897d		frintn v29.4s, v11.4s
-#   v29: 0x7fc000007fc000007fc000007fffffff
+#            v29: 0x7fc000007fc000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  4ee188ea		frintp v10.2d, v7.2d
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea18a4c		frintp v12.2s, v18.2s
-#   v12: 0x00000000000000004000000040000000
+#            v12: 0x00000000000000004000000040000000
 0x~~~~~~~~~~~~~~~~  4ea18bfa		frintp v26.4s, v31.4s
-#   v26: 0x00000000000000004000000040000000
+#            v26: 0x00000000000000004000000040000000
 0x~~~~~~~~~~~~~~~~  6e6199b8		frintx v24.2d, v13.2d
-#   v24: 0x00000000000000000000000000000000
+#            v24: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2e219927		frintx v7.2s, v9.2s
-#    v7: 0x00000000000000000000000000000000
+#             v7: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e219ab2		frintx v18.4s, v21.4s
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4ee19b33		frintz v19.2d, v25.2d
-#   v19: 0x00000000000000000000000000000000
+#            v19: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0ea1990f		frintz v15.2s, v8.2s
-#   v15: 0x00000000000000007fc000007fc00000
+#            v15: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  4ea19874		frintz v20.4s, v3.4s
-#   v20: 0x00000000000000000000000000000000
+#            v20: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ee1d8b7		frsqrte v23.2d, v5.2d
-#   v23: 0x7ff00000000000002006900000000000
+#            v23: 0x7ff00000000000002006900000000000
 0x~~~~~~~~~~~~~~~~  2ea1d8e9		frsqrte v9.2s, v7.2s
-#    v9: 0x00000000000000007f8000007f800000
+#             v9: 0x00000000000000007f8000007f800000
 0x~~~~~~~~~~~~~~~~  6ea1d923		frsqrte v3.4s, v9.4s
-#    v3: 0x7f8000007f8000000000000000000000
+#             v3: 0x7f8000007f8000000000000000000000
 0x~~~~~~~~~~~~~~~~  4eefff99		frsqrts v25.2d, v28.2d, v15.2d
-#   v25: 0x3ff80000000000003ff8000000000000
+#            v25: 0x3ff80000000000003ff8000000000000
 0x~~~~~~~~~~~~~~~~  0eaaff49		frsqrts v9.2s, v26.2s, v10.2s
-#    v9: 0x00000000000000003fc000003fc00000
+#             v9: 0x00000000000000003fc000003fc00000
 0x~~~~~~~~~~~~~~~~  4eaafc25		frsqrts v5.4s, v1.4s, v10.4s
-#    v5: 0x3fc000003fc000007fffffff3fc00000
+#             v5: 0x3fc000003fc000007fffffff3fc00000
 0x~~~~~~~~~~~~~~~~  6ee1fa46		fsqrt v6.2d, v18.2d
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2ea1fa46		fsqrt v6.2s, v18.2s
-#    v6: 0x00000000000000000000000000000000
+#             v6: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  6ea1fbe0		fsqrt v0.4s, v31.4s
-#    v0: 0x00000000000000003fb504f33fb504f3
+#             v0: 0x00000000000000003fb504f33fb504f3
 0x~~~~~~~~~~~~~~~~  4effd7df		fsub v31.2d, v30.2d, v31.2d
-#   v31: 0x00000000000000007fc000007fffffff
+#            v31: 0x00000000000000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  0ea6d50b		fsub v11.2s, v8.2s, v6.2s
-#   v11: 0x00000000000000007fc000007fc00000
+#            v11: 0x00000000000000007fc000007fc00000
 0x~~~~~~~~~~~~~~~~  4ebfd410		fsub v16.4s, v0.4s, v31.4s
-#   v16: 0x00000000000000007fc000007fffffff
+#            v16: 0x00000000000000007fc000007fffffff
 0x~~~~~~~~~~~~~~~~  4e61dbf9		scvtf v25.2d, v31.2d
-#   v25: 0x000000000000000043dff00000200000
+#            v25: 0x000000000000000043dff00000200000
 0x~~~~~~~~~~~~~~~~  4f53e5aa		scvtf v10.2d, v13.2d, #45
-#   v10: 0x00000000000000000000000000000000
+#            v10: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  0e21d9ea		scvtf v10.2s, v15.2s
-#   v10: 0x00000000000000004eff80004eff8000
+#            v10: 0x00000000000000004eff80004eff8000
 0x~~~~~~~~~~~~~~~~  0f25e492		scvtf v18.2s, v4.2s, #27
-#   v18: 0x00000000000000000000000000000000
+#            v18: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  4e21d8b1		scvtf v17.4s, v5.4s
-#   v17: 0x4e7f00004e7f00004f0000004e7f0000
+#            v17: 0x4e7f00004e7f00004f0000004e7f0000
 0x~~~~~~~~~~~~~~~~  4f28e72b		scvtf v11.4s, v25.4s, #24
-#   v11: 0x00000000000000004287bfe03e000000
+#            v11: 0x00000000000000004287bfe03e000000
 0x~~~~~~~~~~~~~~~~  6e61d869		ucvtf v9.2d, v3.2d
-#    v9: 0x43dfe000001fe0000000000000000000
+#             v9: 0x43dfe000001fe0000000000000000000
 0x~~~~~~~~~~~~~~~~  6f52e7da		ucvtf v26.2d, v30.2d, #46
-#   v26: 0x000000000000000040fff00000200000
+#            v26: 0x000000000000000040fff00000200000
 0x~~~~~~~~~~~~~~~~  2e21d88b		ucvtf v11.2s, v4.2s
-#   v11: 0x00000000000000000000000000000000
+#            v11: 0x00000000000000000000000000000000
 0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25
-#   v29: 0x7fc000007fc000000000000000000000
+#            v29: 0x7fc000007fc000000000000000000000
 0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s
-#   v22: 0x4effe000000000004e001a4000000000
+#            v22: 0x4effe000000000004e001a4000000000
 0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25
-#   v18: 0x4207bfc03d7f00000000000000000000
+#            v18: 0x4207bfc03d7f00000000000000000000
+0x~~~~~~~~~~~~~~~~  e5810c0c		str p12, [x0, #11, mul vl]
+#      p12<15:0>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p12<31:16>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p12<47:32>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p12<63:48>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p12<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5810c0d		str p13, [x0, #11, mul vl]
+#      p13<15:0>: 0b 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p13<31:16>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p13<47:32>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p13<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p13<79:64>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5810c0e		str p14, [x0, #11, mul vl]
+#      p14<15:0>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p14<31:16>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p14<47:32>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p14<63:48>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p14<79:64>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5810c0f		str p15, [x0, #11, mul vl]
+#      p15<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p15<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 -> 0x~~~~~~~~~~~~~~~~
+#     p15<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 -> 0x~~~~~~~~~~~~~~~~
+#     p15<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 -> 0x~~~~~~~~~~~~~~~~
+#     p15<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85810c08		ldr p8, [x0, #11, mul vl]
+#       p8<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#      p8<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85810c09		ldr p9, [x0, #11, mul vl]
+#       p9<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#      p9<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85810c0a		ldr p10, [x0, #11, mul vl]
+#      p10<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#     p10<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85810c0b		ldr p11, [x0, #11, mul vl]
+#      p11<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#     p11<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5814c00		str z0, [x0, #11, mul vl]
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3 -> 0x~~~~~~~~~~~~~~~~
+#    z0<255:128>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<383:256>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<511:384>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5814c01		str z1, [x0, #11, mul vl]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<383:256>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<639:512>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5814c02		str z2, [x0, #11, mul vl]
+#      z2<127:0>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<383:256>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5814c03		str z3, [x0, #11, mul vl]
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<255:128>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<383:256>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<511:384>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<639:512>: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85814c14		ldr z20, [x0, #11, mul vl]
+#     z20<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85814c15		ldr z21, [x0, #11, mul vl]
+#     z21<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85814c16		ldr z22, [x0, #11, mul vl]
+#     z22<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  85814c17		ldr z23, [x0, #11, mul vl]
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e403e800		st1b {z0.b}, p2, [x0, #3, mul vl]
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ║ ╙─ 0xf3 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ╙─── 0x04 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ╙───── 0xb5 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ╙───────── 0xf3 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ╙─────────── 0x04 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ╙───────────── 0xb5 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<255:128>: 0x00000000000000000000000000000000
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<383:256>: 0x00000000000000000000000000000000
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ║ ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ║ ╙─── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ║   ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ║ ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ║ ╙─────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ║ ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ║ ╙─────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4a3e401		st1h {z1.h}, p1, [x0, #3, mul vl]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000 (..., 0.000, 0.000, ..., nan, nan, ..., 0.000)
+#                          ║   ║       ║   ║       ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0xffff -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000, 0.000, ..., 0.000, 0.000)
+#                      ║   ║       ║   ║       ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, ..., 0.000, 0.000, ..., 0.000)
+#                          ║   ║       ║   ║       ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000, 0.000, ..., 0.000, 0.000)
+#                      ║   ║       ║   ║       ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5434402		st1w {z2.s}, p1, [x0, x3, lsl #2]
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5e3e803		st1d {z3.d}, p2, [x0, #3, mul vl]
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7f8000007f800000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a403a414		ld1b {z20.b}, p1/z, [x0, #3, mul vl]
+#     z20<127:0>: 0x7f000000008000000000000000000000
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ╙───────────────────── 0x80 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x7f <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x2f000000000029000000000023000000
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4a24815		ld1h {z21.h}, p2/z, [x0, x2, lsl #1]
+#     z21<127:0>: 0x0d0c0b0a09080706050403020100fffe (0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 (...)
+#
+#   z21<639:512>: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a543a416		ld1w {z22.s}, p1/z, [x0, #3, mul vl]
+#     z22<127:0>: 0x7f800000000000000000000000000000 (inf, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x7f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (...)
+#
+#   z22<511:384>: 0x2f2e0000000000000000000023220000 (1.583e-10, ..., 0.000, 8.782e-18)
+#                          ║               ║       ╙─ 0x23220000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e0000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5e3a417		ld1d {z23.d}, p1/z, [x0, #3, mul vl]
+#     z23<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (...)
+#
+#   z23<511:384>: 0x00000000000000000000000023220000 (..., 2.912e-315)
+#                                                  ╙─ 0x0000000023220000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e423e402		st1b {z2.h}, p1, [x0, #3, mul vl]
+#      z2<127:0>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e443e803		st1b {z3.s}, p2, [x0, #3, mul vl]
+#      z3<127:0>: 0x7f8000007f8000000000000000000000
+#                          ║       ║       ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z3<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z3<383:256>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z3<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e463e804		st1b {z4.d}, p2, [x0, #3, mul vl]
+#      z4<127:0>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4c3e400		st1h {z0.s}, p1, [x0, #3, mul vl]
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3
+#                          ║               ║       ╙─ 0x04f3 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x04f3 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4e24401		st1h {z1.d}, p1, [x0, x2, lsl #1]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000
+#                                                  ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e563e402		st1w {z2.d}, p1, [x0, #3, mul vl]
+#      z2<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4224414		ld1b {z20.h}, p1/z, [x0, x2]
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#                          ║   ║       ║   ║       ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000230022000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a443a415		ld1b {z21.s}, p1/z, [x0, #3, mul vl]
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a463a416		ld1b {z22.d}, p1/z, [x0, #3, mul vl]
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4c3a817		ld1h {z23.s}, p2/z, [x0, #3, mul vl]
+#     z23<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4e3a818		ld1h {z24.d}, p2/z, [x0, #3, mul vl]
+#     z24<127:0>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a563a414		ld1w {z20.d}, p1/z, [x0, #3, mul vl]
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5c3a415		ld1sb {z21.h}, p1/z, [x0, #3, mul vl]
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5a3a416		ld1sb {z22.s}, p1/z, [x0, #3, mul vl]
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5824817		ld1sb {z23.d}, p2/z, [x0, x2]
+#     z23<127:0>: 0x0000000000000000000000000000007f
+#                                  ║               ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a523a818		ld1sh {z24.s}, p2/z, [x0, #3, mul vl]
+#     z24<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a503a414		ld1sh {z20.d}, p1/z, [x0, #3, mul vl]
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a483a415		ld1sw {z21.d}, p1/z, [x0, #3, mul vl]
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e432f000		st2b {z0.b, z1.b}, p4, [x0, #4, mul vl]
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3
+#      z1<127:0>: 0x0000000000000000ffffffff00000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'f3 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'04 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'b5 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'3f -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0xff'f3 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0xff'b5 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0xff'3f -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<255:128>: 0x00000000000000000000000000000000
+#    z1<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<383:256>: 0x00000000000000000000000000000000
+#    z1<383:256>: 0x00000000000000000000000000000000
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ╙─────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<511:384>: 0x00000000000000000000000000000000
+#    z1<511:384>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000
+#    z1<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4b2f001		st2h {z1.h, z2.h}, p4, [x0, #4, mul vl]
+#      z1<127:0>: 0x0000000000000000ffffffff00000000 (0.000, 0.000, 0.000, 0.000, nan, nan, 0.000, 0.000)
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, nan, nan, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'ffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'ffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5226c02		st2w {z2.s, z3.s}, p3, [x0, x2, lsl #2]
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f800000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x7f800000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z3<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#                                  ║       ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ║       ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5b2f003		st2d {z3.d, z4.d}, p4, [x0, #4, mul vl]
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#      z4<127:0>: 0x00000000000000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'7f8000007f800000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z3<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a422d414		ld2b {z20.b, z21.b}, p5/z, [x0, x2]
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x000000000000002f0000290000230000
+#   z21<255:128>: 0x00000000000000002e00000000002200
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x22'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x2e'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x0000007f007f00000000000000000000
+#   z21<383:256>: 0x00000000800000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x80'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<511:384>: 0x00000000000000000000000000000000
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4a2f815		ld2h {z21.h, z22.h}, p6/z, [x0, #4, mul vl]
+#     z21<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#     z22<127:0>: 0x000000007f807f800000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a522f816		ld2w {z22.s, z23.s}, p6/z, [x0, #4, mul vl]
+#     z22<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#     z23<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f800000'7f800000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5a2f417		ld2d {z23.d, z24.d}, p5/z, [x0, #4, mul vl]
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#     z24<127:0>: 0x00000000000000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'7f8000007f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z24<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e451f004		st3b {z4.b, z5.b, z6.b}, p4, [x0, #3, mul vl]
+#      z4<127:0>: 0x00000000000000000000000000000000
+#      z5<127:0>: 0x3fc000003fc000007fffffff3fc00000
+#      z6<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'c0'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'3f'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0x00'ff'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'ff'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'7f'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'c0'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'c0'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'3f'00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<255:128>: 0x00000000000000000000000000000000
+#    z5<255:128>: 0x00000000000000000000000000000000
+#    z6<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<383:256>: 0x00000000000000000000000000000000
+#    z5<383:256>: 0x00000000000000000000000000000000
+#    z6<383:256>: 0x00000000000000000000000000000000
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ╙─────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<511:384>: 0x00000000000000000000000000000000
+#    z5<511:384>: 0x00000000000000000000000000000000
+#    z6<511:384>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#    z4<639:512>: 0x00000000000000000000000000000000
+#    z5<639:512>: 0x00000000000000000000000000000000
+#    z6<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e4d1f005		st3h {z5.h, z6.h, z7.h}, p4, [x0, #3, mul vl]
+#      z5<127:0>: 0x3fc000003fc000007fffffff3fc00000 (1.938, 0.000, 1.938, 0.000, nan, nan, 1.938, 0.000)
+#      z6<127:0>: 0x00000000000000000000000000000000 (1.938, 0.000, 1.938, 0.000, nan, nan, 1.938, 0.000)
+#      z7<127:0>: 0x00000000000000000000000000000000 (1.938, 0.000, 1.938, 0.000, nan, nan, 1.938, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'3fc0 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'ffff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'7fff -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'3fc0 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'3fc0 -> 0x~~~~~~~~~~~~~~~~
+#    z5<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z6<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z7<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z5<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z6<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z7<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z5<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z6<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z7<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z5<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z6<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z7<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e551ec06		st3w {z6.s, z7.s, z8.s}, p3, [x0, #3, mul vl]
+#      z6<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z8<127:0>: 0x37a00000000000007fc000007fc00000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x7fc00000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x37a00000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z6<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z7<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z8<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z6<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z7<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z8<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#                                  ║       ║       ╙─ 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ║       ╙───────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z6<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z7<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z8<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5c27007		st3d {z7.d, z8.d, z9.d}, p4, [x0, x2, lsl #3]
+#      z7<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#      z8<127:0>: 0x37a00000000000007fc000007fc00000 (0.000, 0.000)
+#      z9<127:0>: 0x43dfe000001fe0000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'7fc000007fc00000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x43dfe000001fe000'37a0000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z7<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z8<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z9<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z7<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z8<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z9<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z7<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z8<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z9<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z7<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z8<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z9<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a441f418		ld3b {z24.b, z25.b, z26.b}, p5/z, [x0, #3, mul vl]
+#     z24<127:0>: 0x0000000000000000000000ff00000000
+#     z25<127:0>: 0xa000000000000000000000ffc0000000
+#     z26<127:0>: 0x3700000000000000000000007f000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x7f'c0'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'ff'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x37'a0'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<639:512>: 0x00000000000000000000000000000000
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4c2d819		ld3h {z25.h, z26.h, z27.h}, p6/z, [x0, x2, lsl #1]
+#     z25<127:0>: 0x292823221d1c17160000000000000000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z26<127:0>: 0x2b2a25241f1e191813120d0c07060100 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z27<127:0>: 0x2d2c272621201b1a1514000009080000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0100'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0908'0706'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0d0c'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514'1312'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1b1a'1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2120'1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x595853524d4c474641403b3a35342f2e (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z26<255:128>: 0x5b5a55544f4e494843423d3c37363130 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z27<255:128>: 0x5d5c575651504b4a45443f3e39383332 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3332'3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3938'3736'3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544'4342'4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4b4a'4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5150'4f4e'4d4c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c'5b5a'5958 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x898883827d7c777671706b6a65645f5e (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z26<383:256>: 0x8b8a85847f7e797873726d6c67666160 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z27<383:256>: 0x8d8c878681807b7a75746f6e69686362 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x6362'6160'5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6968'6766'6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6f6e'6d6c'6b6a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x7574'7372'7170 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7b7a'7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x8180'7f7e'7d7c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x8786'8584'8382 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8d8c'8b8a'8988 <- 0x~~~~~~~~~~~~~~~~
+#   z25<511:384>: 0xb9b8b3b2adaca7a6a1a09b9a95948f8e (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#   z26<511:384>: 0xbbbab5b4afaea9a8a3a29d9c97969190 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#   z27<511:384>: 0xbdbcb7b6b1b0abaaa5a49f9e99989392 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x9392'9190'8f8e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x9998'9796'9594 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x9f9e'9d9c'9b9a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xa5a4'a3a2'a1a0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xabaa'a9a8'a7a6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xb1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xb7b6'b5b4'b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xbdbc'bbba'b9b8 <- 0x~~~~~~~~~~~~~~~~
+#   z25<639:512>: 0xe9e8e3e2dddcd7d6d1d0cbcac5c4bfbe (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#   z26<639:512>: 0xebeae5e4dfded9d8d3d2cdccc7c6c1c0 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#   z27<639:512>: 0xedece7e6e1e0dbdad5d4cfcec9c8c3c2 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xc3c2'c1c0'bfbe <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xc9c8'c7c6'c5c4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xcfce'cdcc'cbca <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd5d4'd3d2'd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xdbda'd9d8'd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xe1e0'dfde'dddc <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xe7e6'e5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a541f81a		ld3w {z26.s, z27.s, z28.s}, p6/z, [x0, #3, mul vl]
+#     z26<127:0>: 0x00000000000000000000ffff00000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z27<127:0>: 0x00000000000000007fff000000000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z28<127:0>: 0x37a0000000000000000000007fc00000 (0.000, 0.000, 9.183e-41, 0.000)
+#                          ║       ║       ║       ╙─ 0x7fc00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'7fff0000'0000ffff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x37a00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5c1f41b		ld3d {z27.d, z28.d, z29.d}, p5/z, [x0, #3, mul vl]
+#     z27<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000ffff7fc00000 (0.000, 0.000)
+#     z29<127:0>: 0x37a0000000000000000000007fff0000 (0.000, 0.000)
+#                                  ║               ╙─ 0x000000007fff0000'0000ffff7fc00000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x37a0000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e471f01f		st4b {z31.b, z0.b, z1.b, z2.b}, p4, [x0, #4, mul vl]
+#     z31<127:0>: 0x00000000000000007fc000007fffffff
+#      z0<127:0>: 0x00000000000000003fb504f33fb504f3
+#      z1<127:0>: 0x0000000000000000ffffffff00000000
+#      z2<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'f3'ff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'04'ff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'b5'ff -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'3f'7f -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0x00'ff'f3'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'ff'b5'c0 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'ff'3f'7f -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#   z31<255:128>: 0x00000000000000000000000000000000
+#    z0<255:128>: 0x00000000000000000000000000000000
+#    z1<255:128>: 0x00000000000000000000000000000000
+#    z2<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙─ 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#   z31<383:256>: 0x00000000000000000000000000000000
+#    z0<383:256>: 0x00000000000000000000000000000000
+#    z1<383:256>: 0x00000000000000000000000000000000
+#    z2<383:256>: 0x00000000000000000000000000000000
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙─ 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ║ ╙───────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ║ ╙─────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ║ ╙───────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ║ ╙─────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#   z31<511:384>: 0x00000000000000000000000000000000
+#    z0<511:384>: 0x00000000000000000000000000000000
+#    z1<511:384>: 0x00000000000000000000000000000000
+#    z2<511:384>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║   ╙───────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00'00 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'04f3 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'3fb5 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'ffff'04f3 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'ffff'3fb5 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7f80'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x7f80'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e571ec01		st4w {z1.s, z2.s, z3.s, z4.s}, p3, [x0, #4, mul vl]
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+#                          ║       ║               ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'7f800000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'7f800000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
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+#    z4<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
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+#    z4<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#                                  ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ║       ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  e5e27002		st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]
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+#                                  ║               ╙─ 0x7fffffff3fc00000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3fc000003fc00000'0000000000000000'7f8000007f800000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
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+#    z5<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
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+#    z4<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a461f419		ld4b {z25.b, z26.b, z27.b, z28.b}, p5/z, [x0, #4, mul vl]
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+#     z26<127:0>: 0x00000000000000000000000400000000
+#     z27<127:0>: 0x0080000000800000000000ff00000000
+#     z28<127:0>: 0x007f0000007f0000000000ff00000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0xff'ff'04'f3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#   z27<255:128>: 0x00000000000000000000000000000000
+#   z28<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#   z27<383:256>: 0x00000000000000000000000000000000
+#   z28<383:256>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#   z27<511:384>: 0x00000000000000000000000000000000
+#   z28<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#   z27<639:512>: 0x00000000000000000000000000000000
+#   z28<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a4e1f81a		ld4h {z26.h, z27.h, z28.h, z29.h}, p6/z, [x0, #4, mul vl]
+#     z26<127:0>: 0x00000000000000003fb504f300000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z27<127:0>: 0x7f8000007f800000ffffffff00000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'ffff'04f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'ffff'3fb5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a562d81b		ld4w {z27.s, z28.s, z29.s, z30.s}, p6/z, [x0, x2, lsl #2]
+#     z27<127:0>: 0x2f2e2d2c000000000000000000000000 (1.584e-10, 0.000, 0.000, 0.000)
+#     z28<127:0>: 0x33323130000000007f80000000000000 (1.584e-10, 0.000, 0.000, 0.000)
+#     z29<127:0>: 0x00000000000000000000000007060504 (1.584e-10, 0.000, 0.000, 0.000)
+#     z30<127:0>: 0x00000000000000007f8000000b0a0908 (1.584e-10, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7f800000'00000000'7f800000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z29<255:128>: 0x00000000000000005756555400000000 (0.000, 0.000, 0.000, 0.000)
+#   z30<255:128>: 0x00000000000000005b5a595800000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5b5a5958'57565554'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<383:256>: 0xafaeadac9f9e9d9c8f8e8d8c7f7e7d7c (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z28<383:256>: 0xb3b2b1b0a3a2a1a09392919083828180 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z29<383:256>: 0xb7b6b5b4a7a6a5a49796959487868584 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z30<383:256>: 0xbbbab9b8abaaa9a89b9a99988b8a8988 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#                          ║       ║       ║       ╙─ 0x8b8a8988'87868584'83828180'7f7e7d7c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x9b9a9998'97969594'93929190'8f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xabaaa9a8'a7a6a5a4'a3a2a1a0'9f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xbbbab9b8'b7b6b5b4'b3b2b1b0'afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   z27<511:384>: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z28<511:384>: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z29<511:384>: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z30<511:384>: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#   z27<639:512>: 0x2f2e2d2c1f1e1d1c0f0e0d0cfffefdfc (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z28<639:512>: 0x33323130232221201312111003020100 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z29<639:512>: 0x37363534272625241716151407060504 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z30<639:512>: 0x3b3a39382b2a29281b1a19180b0a0908 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'03020100'fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1b1a1918'17161514'13121110'0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928'27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3b3a3938'37363534'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+0x~~~~~~~~~~~~~~~~  a5e1f41c		ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]
+#     z28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z29<127:0>: 0x000000007f8000000000000000000000 (0.000, 0.000)
+#     z30<127:0>: 0x000000000000000000000000ffff04f3 (0.000, 0.000)
+#     z31<127:0>: 0x000000007f80000000000000ffff3fb5 (0.000, 0.000)
+#                                  ║               ╙─ 0x00000000ffff3fb5'00000000ffff04f3'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x000000007f800000'0000000000000000'000000007f800000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z30<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z31<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
 0x~~~~~~~~~~~~~~~~  d65f03c0		ret
 # Branch to 0x~~~~~~~~~~~~~~~~.
diff --git a/test/test-trace-reference/log-branch b/test/test-trace-reference/log-branch
index 88a4e994..fff3143f 100644
--- a/test/test-trace-reference/log-branch
+++ b/test/test-trace-reference/log-branch
@@ -1,595 +1,3190 @@
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   x19: 0x0000000000000086 -> 0x~~~~~~~~~~~~~~~~
-#   w20<7:0>:          0x04 -> 0x~~~~~~~~~~~~~~~~
-#   w21<7:0>:          0x03 -> 0x~~~~~~~~~~~~~~~~
-#   w22<15:0>:       0x0004 -> 0x~~~~~~~~~~~~~~~~
-#   w23<15:0>:       0x0100 -> 0x~~~~~~~~~~~~~~~~
-#   w14:         0x00000000 -> 0x~~~~~~~~~~~~~~~~
-#   w15:         0x00000082 -> 0x~~~~~~~~~~~~~~~~
-#   x16: 0x000000000000000c -> 0x~~~~~~~~~~~~~~~~
-#   x17: 0x00000000ffffff7b -> 0x~~~~~~~~~~~~~~~~
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
-#   w18:         0x00000060 -> 0x~~~~~~~~~~~~~~~~
-#   w19:         0x00000086 -> 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000000000304 -> 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 -> 0x~~~~~~~~~~~~~~~~
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
-#   w22:         0x00000004 -> 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 -> 0x~~~~~~~~~~~~~~~~
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
-#   w24<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
-#   w25<7:0>:          0x00 -> 0x~~~~~~~~~~~~~~~~
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
-#   w26<15:0>:       0xfcff -> 0x~~~~~~~~~~~~~~~~
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
-#   w27<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
-#   w28:         0xfffeffff -> 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000000000000 -> 0x~~~~~~~~~~~~~~~~
-#    w2<7:0>:          0x01 -> 0x~~~~~~~~~~~~~~~~
-#    w3<7:0>:          0xff -> 0x~~~~~~~~~~~~~~~~
-#    w4<15:0>:       0x0001 -> 0x~~~~~~~~~~~~~~~~
-#    w5<15:0>:       0x8500 -> 0x~~~~~~~~~~~~~~~~
-#   v18: 0x00000000000000000000000000000000 -> 0x~~~~~~~~~~~~~~~~
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-#   v20: 0x00000000000000000000000000000020 -> 0x~~~~~~~~~~~~~~~~
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-#   v13: 0x0000000000000000ffffffffffffffe1 -> 0x~~~~~~~~~~~~~~~~
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-#   v16: 0x00000000000000000000000000007ff9 -> 0x~~~~~~~~~~~~~~~~
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-#   v21: 0x000000000000000000000000ffff8007 -> 0x~~~~~~~~~~~~~~~~
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-#   v15:                 0x0000000000000000 (d15: 0.00000) -> 0x~~~~~~~~~~~~~~~~
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diff --git a/test/test-trace-reference/log-branch-colour b/test/test-trace-reference/log-branch-colour
index 80207575..92faa1fd 100644
--- a/test/test-trace-reference/log-branch-colour
+++ b/test/test-trace-reference/log-branch-colour
@@ -1,595 +1,3190 @@
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#     v12<127:0>: 0x000000000000000000000000ffffffff (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, nan, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xffff -> 0x~~~~~~~~~~~~~~~~
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+#     v10<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 -> 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z1<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#    z0<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z1<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#    z3<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 -> 0x~~~~~~~~~~~~~~~~
+#      z1<127:0>: 0x0000000000000000ffffffff00000000 (0.000, 0.000, ..., 0.000)
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (0.000, 0.000, ..., 0.000)
+#      z4<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'7f800000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'7f800000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#    z4<255:128>: 0x00000000000000000000000000000000 (0.000, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z2<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z3<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#    z4<383:256>: 0x00000000000000000000000000000000 (..., 0.000, 0.000, 0.000)
+#                                  ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ║       ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#    z1<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#    z4<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 -> 0x~~~~~~~~~~~~~~~~
+#      z2<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#      z3<127:0>: 0x7f8000007f8000000000000000000000 (0.000, 0.000)
+#      z4<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#      z5<127:0>: 0x3fc000003fc000007fffffff3fc00000 (0.000, 0.000)
+#                                  ║               ╙─ 0x7fffffff3fc00000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3fc000003fc00000'0000000000000000'7f8000007f800000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z3<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z3<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z3<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#    z2<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z3<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z4<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#    z5<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 -> 0x~~~~~~~~~~~~~~~~
diff --git a/test/test-trace-reference/log-cpufeatures b/test/test-trace-reference/log-cpufeatures
index d02ec067..804c06f5 100644
--- a/test/test-trace-reference/log-cpufeatures
+++ b/test/test-trace-reference/log-cpufeatures
@@ -2383,3 +2383,69 @@
 0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25                // Needs: FP, NEON
 0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s                    // Needs: FP, NEON
 0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25                // Needs: FP, NEON
+0x~~~~~~~~~~~~~~~~  e5810c0c		str p12, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5810c0d		str p13, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5810c0e		str p14, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5810c0f		str p15, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  85810c08		ldr p8, [x0, #11, mul vl]               // Needs: SVE
+0x~~~~~~~~~~~~~~~~  85810c09		ldr p9, [x0, #11, mul vl]               // Needs: SVE
+0x~~~~~~~~~~~~~~~~  85810c0a		ldr p10, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  85810c0b		ldr p11, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5814c00		str z0, [x0, #11, mul vl]               // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5814c01		str z1, [x0, #11, mul vl]               // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5814c02		str z2, [x0, #11, mul vl]               // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5814c03		str z3, [x0, #11, mul vl]               // Needs: SVE
+0x~~~~~~~~~~~~~~~~  85814c14		ldr z20, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  85814c15		ldr z21, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  85814c16		ldr z22, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  85814c17		ldr z23, [x0, #11, mul vl]              // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e403e800		st1b {z0.b}, p2, [x0, #3, mul vl]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e4a3e401		st1h {z1.h}, p1, [x0, #3, mul vl]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5434402		st1w {z2.s}, p1, [x0, x3, lsl #2]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5e3e803		st1d {z3.d}, p2, [x0, #3, mul vl]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a403a414		ld1b {z20.b}, p1/z, [x0, #3, mul vl]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a4a24815		ld1h {z21.h}, p2/z, [x0, x2, lsl #1]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a543a416		ld1w {z22.s}, p1/z, [x0, #3, mul vl]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a5e3a417		ld1d {z23.d}, p1/z, [x0, #3, mul vl]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e423e402		st1b {z2.h}, p1, [x0, #3, mul vl]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e443e803		st1b {z3.s}, p2, [x0, #3, mul vl]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e463e804		st1b {z4.d}, p2, [x0, #3, mul vl]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e4c3e400		st1h {z0.s}, p1, [x0, #3, mul vl]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e4e24401		st1h {z1.d}, p1, [x0, x2, lsl #1]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e563e402		st1w {z2.d}, p1, [x0, #3, mul vl]       // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a4224414		ld1b {z20.h}, p1/z, [x0, x2]            // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a443a415		ld1b {z21.s}, p1/z, [x0, #3, mul vl]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a463a416		ld1b {z22.d}, p1/z, [x0, #3, mul vl]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a4c3a817		ld1h {z23.s}, p2/z, [x0, #3, mul vl]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a4e3a818		ld1h {z24.d}, p2/z, [x0, #3, mul vl]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a563a414		ld1w {z20.d}, p1/z, [x0, #3, mul vl]    // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a5c3a415		ld1sb {z21.h}, p1/z, [x0, #3, mul vl]   // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a5a3a416		ld1sb {z22.s}, p1/z, [x0, #3, mul vl]   // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a5824817		ld1sb {z23.d}, p2/z, [x0, x2]           // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a523a818		ld1sh {z24.s}, p2/z, [x0, #3, mul vl]   // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a503a414		ld1sh {z20.d}, p1/z, [x0, #3, mul vl]   // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a483a415		ld1sw {z21.d}, p1/z, [x0, #3, mul vl]   // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e432f000		st2b {z0.b, z1.b}, p4, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e4b2f001		st2h {z1.h, z2.h}, p4, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5226c02		st2w {z2.s, z3.s}, p3, [x0, x2, lsl #2]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5b2f003		st2d {z3.d, z4.d}, p4, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a422d414		ld2b {z20.b, z21.b}, p5/z, [x0, x2]     // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a4a2f815		ld2h {z21.h, z22.h}, p6/z, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a522f816		ld2w {z22.s, z23.s}, p6/z, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a5a2f417		ld2d {z23.d, z24.d}, p5/z, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e451f004		st3b {z4.b, z5.b, z6.b}, p4, [x0, #3, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e4d1f005		st3h {z5.h, z6.h, z7.h}, p4, [x0, #3, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e551ec06		st3w {z6.s, z7.s, z8.s}, p3, [x0, #3, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5c27007		st3d {z7.d, z8.d, z9.d}, p4, [x0, x2, lsl #3]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a441f418		ld3b {z24.b, z25.b, z26.b}, p5/z, [x0, #3, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a4c2d819		ld3h {z25.h, z26.h, z27.h}, p6/z, [x0, x2, lsl #1]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a541f81a		ld3w {z26.s, z27.s, z28.s}, p6/z, [x0, #3, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a5c1f41b		ld3d {z27.d, z28.d, z29.d}, p5/z, [x0, #3, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e471f01f		st4b {z31.b, z0.b, z1.b, z2.b}, p4, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e4f1f000		st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e571ec01		st4w {z1.s, z2.s, z3.s, z4.s}, p3, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  e5e27002		st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a461f419		ld4b {z25.b, z26.b, z27.b, z28.b}, p5/z, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a4e1f81a		ld4h {z26.h, z27.h, z28.h, z29.h}, p6/z, [x0, #4, mul vl]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a562d81b		ld4w {z27.s, z28.s, z29.s, z30.s}, p6/z, [x0, x2, lsl #2]  // Needs: SVE
+0x~~~~~~~~~~~~~~~~  a5e1f41c		ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]  // Needs: SVE
diff --git a/test/test-trace-reference/log-cpufeatures-colour b/test/test-trace-reference/log-cpufeatures-colour
index c98361ab..58f04790 100644
--- a/test/test-trace-reference/log-cpufeatures-colour
+++ b/test/test-trace-reference/log-cpufeatures-colour
@@ -2383,3 +2383,69 @@
 0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25                FP, NEON
 0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s                    FP, NEON
 0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25                FP, NEON
+0x~~~~~~~~~~~~~~~~  e5810c0c		str p12, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  e5810c0d		str p13, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  e5810c0e		str p14, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  e5810c0f		str p15, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  85810c08		ldr p8, [x0, #11, mul vl]               SVE
+0x~~~~~~~~~~~~~~~~  85810c09		ldr p9, [x0, #11, mul vl]               SVE
+0x~~~~~~~~~~~~~~~~  85810c0a		ldr p10, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  85810c0b		ldr p11, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  e5814c00		str z0, [x0, #11, mul vl]               SVE
+0x~~~~~~~~~~~~~~~~  e5814c01		str z1, [x0, #11, mul vl]               SVE
+0x~~~~~~~~~~~~~~~~  e5814c02		str z2, [x0, #11, mul vl]               SVE
+0x~~~~~~~~~~~~~~~~  e5814c03		str z3, [x0, #11, mul vl]               SVE
+0x~~~~~~~~~~~~~~~~  85814c14		ldr z20, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  85814c15		ldr z21, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  85814c16		ldr z22, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  85814c17		ldr z23, [x0, #11, mul vl]              SVE
+0x~~~~~~~~~~~~~~~~  e403e800		st1b {z0.b}, p2, [x0, #3, mul vl]       SVE
+0x~~~~~~~~~~~~~~~~  e4a3e401		st1h {z1.h}, p1, [x0, #3, mul vl]       SVE
+0x~~~~~~~~~~~~~~~~  e5434402		st1w {z2.s}, p1, [x0, x3, lsl #2]       SVE
+0x~~~~~~~~~~~~~~~~  e5e3e803		st1d {z3.d}, p2, [x0, #3, mul vl]       SVE
+0x~~~~~~~~~~~~~~~~  a403a414		ld1b {z20.b}, p1/z, [x0, #3, mul vl]    SVE
+0x~~~~~~~~~~~~~~~~  a4a24815		ld1h {z21.h}, p2/z, [x0, x2, lsl #1]    SVE
+0x~~~~~~~~~~~~~~~~  a543a416		ld1w {z22.s}, p1/z, [x0, #3, mul vl]    SVE
+0x~~~~~~~~~~~~~~~~  a5e3a417		ld1d {z23.d}, p1/z, [x0, #3, mul vl]    SVE
+0x~~~~~~~~~~~~~~~~  e423e402		st1b {z2.h}, p1, [x0, #3, mul vl]       SVE
+0x~~~~~~~~~~~~~~~~  e443e803		st1b {z3.s}, p2, [x0, #3, mul vl]       SVE
+0x~~~~~~~~~~~~~~~~  e463e804		st1b {z4.d}, p2, [x0, #3, mul vl]       SVE
+0x~~~~~~~~~~~~~~~~  e4c3e400		st1h {z0.s}, p1, [x0, #3, mul vl]       SVE
+0x~~~~~~~~~~~~~~~~  e4e24401		st1h {z1.d}, p1, [x0, x2, lsl #1]       SVE
+0x~~~~~~~~~~~~~~~~  e563e402		st1w {z2.d}, p1, [x0, #3, mul vl]       SVE
+0x~~~~~~~~~~~~~~~~  a4224414		ld1b {z20.h}, p1/z, [x0, x2]            SVE
+0x~~~~~~~~~~~~~~~~  a443a415		ld1b {z21.s}, p1/z, [x0, #3, mul vl]    SVE
+0x~~~~~~~~~~~~~~~~  a463a416		ld1b {z22.d}, p1/z, [x0, #3, mul vl]    SVE
+0x~~~~~~~~~~~~~~~~  a4c3a817		ld1h {z23.s}, p2/z, [x0, #3, mul vl]    SVE
+0x~~~~~~~~~~~~~~~~  a4e3a818		ld1h {z24.d}, p2/z, [x0, #3, mul vl]    SVE
+0x~~~~~~~~~~~~~~~~  a563a414		ld1w {z20.d}, p1/z, [x0, #3, mul vl]    SVE
+0x~~~~~~~~~~~~~~~~  a5c3a415		ld1sb {z21.h}, p1/z, [x0, #3, mul vl]   SVE
+0x~~~~~~~~~~~~~~~~  a5a3a416		ld1sb {z22.s}, p1/z, [x0, #3, mul vl]   SVE
+0x~~~~~~~~~~~~~~~~  a5824817		ld1sb {z23.d}, p2/z, [x0, x2]           SVE
+0x~~~~~~~~~~~~~~~~  a523a818		ld1sh {z24.s}, p2/z, [x0, #3, mul vl]   SVE
+0x~~~~~~~~~~~~~~~~  a503a414		ld1sh {z20.d}, p1/z, [x0, #3, mul vl]   SVE
+0x~~~~~~~~~~~~~~~~  a483a415		ld1sw {z21.d}, p1/z, [x0, #3, mul vl]   SVE
+0x~~~~~~~~~~~~~~~~  e432f000		st2b {z0.b, z1.b}, p4, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e4b2f001		st2h {z1.h, z2.h}, p4, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e5226c02		st2w {z2.s, z3.s}, p3, [x0, x2, lsl #2]  SVE
+0x~~~~~~~~~~~~~~~~  e5b2f003		st2d {z3.d, z4.d}, p4, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  a422d414		ld2b {z20.b, z21.b}, p5/z, [x0, x2]     SVE
+0x~~~~~~~~~~~~~~~~  a4a2f815		ld2h {z21.h, z22.h}, p6/z, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  a522f816		ld2w {z22.s, z23.s}, p6/z, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  a5a2f417		ld2d {z23.d, z24.d}, p5/z, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e451f004		st3b {z4.b, z5.b, z6.b}, p4, [x0, #3, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e4d1f005		st3h {z5.h, z6.h, z7.h}, p4, [x0, #3, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e551ec06		st3w {z6.s, z7.s, z8.s}, p3, [x0, #3, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e5c27007		st3d {z7.d, z8.d, z9.d}, p4, [x0, x2, lsl #3]  SVE
+0x~~~~~~~~~~~~~~~~  a441f418		ld3b {z24.b, z25.b, z26.b}, p5/z, [x0, #3, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  a4c2d819		ld3h {z25.h, z26.h, z27.h}, p6/z, [x0, x2, lsl #1]  SVE
+0x~~~~~~~~~~~~~~~~  a541f81a		ld3w {z26.s, z27.s, z28.s}, p6/z, [x0, #3, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  a5c1f41b		ld3d {z27.d, z28.d, z29.d}, p5/z, [x0, #3, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e471f01f		st4b {z31.b, z0.b, z1.b, z2.b}, p4, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e4f1f000		st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e571ec01		st4w {z1.s, z2.s, z3.s, z4.s}, p3, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  e5e27002		st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]  SVE
+0x~~~~~~~~~~~~~~~~  a461f419		ld4b {z25.b, z26.b, z27.b, z28.b}, p5/z, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  a4e1f81a		ld4h {z26.h, z27.h, z28.h, z29.h}, p6/z, [x0, #4, mul vl]  SVE
+0x~~~~~~~~~~~~~~~~  a562d81b		ld4w {z27.s, z28.s, z29.s, z30.s}, p6/z, [x0, x2, lsl #2]  SVE
+0x~~~~~~~~~~~~~~~~  a5e1f41c		ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]  SVE
diff --git a/test/test-trace-reference/log-cpufeatures-custom b/test/test-trace-reference/log-cpufeatures-custom
index fa43cbaa..1e572f28 100644
--- a/test/test-trace-reference/log-cpufeatures-custom
+++ b/test/test-trace-reference/log-cpufeatures-custom
@@ -2383,3 +2383,69 @@
 0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25                ### {FP, NEON} ###
 0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s                    ### {FP, NEON} ###
 0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25                ### {FP, NEON} ###
+0x~~~~~~~~~~~~~~~~  e5810c0c		str p12, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5810c0d		str p13, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5810c0e		str p14, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5810c0f		str p15, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  85810c08		ldr p8, [x0, #11, mul vl]               ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  85810c09		ldr p9, [x0, #11, mul vl]               ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  85810c0a		ldr p10, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  85810c0b		ldr p11, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5814c00		str z0, [x0, #11, mul vl]               ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5814c01		str z1, [x0, #11, mul vl]               ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5814c02		str z2, [x0, #11, mul vl]               ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5814c03		str z3, [x0, #11, mul vl]               ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  85814c14		ldr z20, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  85814c15		ldr z21, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  85814c16		ldr z22, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  85814c17		ldr z23, [x0, #11, mul vl]              ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e403e800		st1b {z0.b}, p2, [x0, #3, mul vl]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e4a3e401		st1h {z1.h}, p1, [x0, #3, mul vl]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5434402		st1w {z2.s}, p1, [x0, x3, lsl #2]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5e3e803		st1d {z3.d}, p2, [x0, #3, mul vl]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a403a414		ld1b {z20.b}, p1/z, [x0, #3, mul vl]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a4a24815		ld1h {z21.h}, p2/z, [x0, x2, lsl #1]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a543a416		ld1w {z22.s}, p1/z, [x0, #3, mul vl]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a5e3a417		ld1d {z23.d}, p1/z, [x0, #3, mul vl]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e423e402		st1b {z2.h}, p1, [x0, #3, mul vl]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e443e803		st1b {z3.s}, p2, [x0, #3, mul vl]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e463e804		st1b {z4.d}, p2, [x0, #3, mul vl]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e4c3e400		st1h {z0.s}, p1, [x0, #3, mul vl]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e4e24401		st1h {z1.d}, p1, [x0, x2, lsl #1]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e563e402		st1w {z2.d}, p1, [x0, #3, mul vl]       ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a4224414		ld1b {z20.h}, p1/z, [x0, x2]            ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a443a415		ld1b {z21.s}, p1/z, [x0, #3, mul vl]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a463a416		ld1b {z22.d}, p1/z, [x0, #3, mul vl]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a4c3a817		ld1h {z23.s}, p2/z, [x0, #3, mul vl]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a4e3a818		ld1h {z24.d}, p2/z, [x0, #3, mul vl]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a563a414		ld1w {z20.d}, p1/z, [x0, #3, mul vl]    ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a5c3a415		ld1sb {z21.h}, p1/z, [x0, #3, mul vl]   ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a5a3a416		ld1sb {z22.s}, p1/z, [x0, #3, mul vl]   ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a5824817		ld1sb {z23.d}, p2/z, [x0, x2]           ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a523a818		ld1sh {z24.s}, p2/z, [x0, #3, mul vl]   ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a503a414		ld1sh {z20.d}, p1/z, [x0, #3, mul vl]   ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a483a415		ld1sw {z21.d}, p1/z, [x0, #3, mul vl]   ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e432f000		st2b {z0.b, z1.b}, p4, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e4b2f001		st2h {z1.h, z2.h}, p4, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5226c02		st2w {z2.s, z3.s}, p3, [x0, x2, lsl #2]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5b2f003		st2d {z3.d, z4.d}, p4, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a422d414		ld2b {z20.b, z21.b}, p5/z, [x0, x2]     ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a4a2f815		ld2h {z21.h, z22.h}, p6/z, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a522f816		ld2w {z22.s, z23.s}, p6/z, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a5a2f417		ld2d {z23.d, z24.d}, p5/z, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e451f004		st3b {z4.b, z5.b, z6.b}, p4, [x0, #3, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e4d1f005		st3h {z5.h, z6.h, z7.h}, p4, [x0, #3, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e551ec06		st3w {z6.s, z7.s, z8.s}, p3, [x0, #3, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5c27007		st3d {z7.d, z8.d, z9.d}, p4, [x0, x2, lsl #3]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a441f418		ld3b {z24.b, z25.b, z26.b}, p5/z, [x0, #3, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a4c2d819		ld3h {z25.h, z26.h, z27.h}, p6/z, [x0, x2, lsl #1]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a541f81a		ld3w {z26.s, z27.s, z28.s}, p6/z, [x0, #3, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a5c1f41b		ld3d {z27.d, z28.d, z29.d}, p5/z, [x0, #3, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e471f01f		st4b {z31.b, z0.b, z1.b, z2.b}, p4, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e4f1f000		st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e571ec01		st4w {z1.s, z2.s, z3.s, z4.s}, p3, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  e5e27002		st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a461f419		ld4b {z25.b, z26.b, z27.b, z28.b}, p5/z, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a4e1f81a		ld4h {z26.h, z27.h, z28.h, z29.h}, p6/z, [x0, #4, mul vl]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a562d81b		ld4w {z27.s, z28.s, z29.s, z30.s}, p6/z, [x0, x2, lsl #2]  ### {SVE} ###
+0x~~~~~~~~~~~~~~~~  a5e1f41c		ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]  ### {SVE} ###
diff --git a/test/test-trace-reference/log-disasm b/test/test-trace-reference/log-disasm
index 9486236c..583328a3 100644
--- a/test/test-trace-reference/log-disasm
+++ b/test/test-trace-reference/log-disasm
@@ -2384,4 +2384,70 @@
 0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25
 0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s
 0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25
+0x~~~~~~~~~~~~~~~~  e5810c0c		str p12, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5810c0d		str p13, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5810c0e		str p14, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5810c0f		str p15, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85810c08		ldr p8, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85810c09		ldr p9, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85810c0a		ldr p10, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85810c0b		ldr p11, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5814c00		str z0, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5814c01		str z1, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5814c02		str z2, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5814c03		str z3, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85814c14		ldr z20, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85814c15		ldr z21, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85814c16		ldr z22, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85814c17		ldr z23, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e403e800		st1b {z0.b}, p2, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e4a3e401		st1h {z1.h}, p1, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e5434402		st1w {z2.s}, p1, [x0, x3, lsl #2]
+0x~~~~~~~~~~~~~~~~  e5e3e803		st1d {z3.d}, p2, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a403a414		ld1b {z20.b}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4a24815		ld1h {z21.h}, p2/z, [x0, x2, lsl #1]
+0x~~~~~~~~~~~~~~~~  a543a416		ld1w {z22.s}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5e3a417		ld1d {z23.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e423e402		st1b {z2.h}, p1, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e443e803		st1b {z3.s}, p2, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e463e804		st1b {z4.d}, p2, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e4c3e400		st1h {z0.s}, p1, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e4e24401		st1h {z1.d}, p1, [x0, x2, lsl #1]
+0x~~~~~~~~~~~~~~~~  e563e402		st1w {z2.d}, p1, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4224414		ld1b {z20.h}, p1/z, [x0, x2]
+0x~~~~~~~~~~~~~~~~  a443a415		ld1b {z21.s}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a463a416		ld1b {z22.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4c3a817		ld1h {z23.s}, p2/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4e3a818		ld1h {z24.d}, p2/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a563a414		ld1w {z20.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5c3a415		ld1sb {z21.h}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5a3a416		ld1sb {z22.s}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5824817		ld1sb {z23.d}, p2/z, [x0, x2]
+0x~~~~~~~~~~~~~~~~  a523a818		ld1sh {z24.s}, p2/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a503a414		ld1sh {z20.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a483a415		ld1sw {z21.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e432f000		st2b {z0.b, z1.b}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e4b2f001		st2h {z1.h, z2.h}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e5226c02		st2w {z2.s, z3.s}, p3, [x0, x2, lsl #2]
+0x~~~~~~~~~~~~~~~~  e5b2f003		st2d {z3.d, z4.d}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a422d414		ld2b {z20.b, z21.b}, p5/z, [x0, x2]
+0x~~~~~~~~~~~~~~~~  a4a2f815		ld2h {z21.h, z22.h}, p6/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a522f816		ld2w {z22.s, z23.s}, p6/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a5a2f417		ld2d {z23.d, z24.d}, p5/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e451f004		st3b {z4.b, z5.b, z6.b}, p4, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e4d1f005		st3h {z5.h, z6.h, z7.h}, p4, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e551ec06		st3w {z6.s, z7.s, z8.s}, p3, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e5c27007		st3d {z7.d, z8.d, z9.d}, p4, [x0, x2, lsl #3]
+0x~~~~~~~~~~~~~~~~  a441f418		ld3b {z24.b, z25.b, z26.b}, p5/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4c2d819		ld3h {z25.h, z26.h, z27.h}, p6/z, [x0, x2, lsl #1]
+0x~~~~~~~~~~~~~~~~  a541f81a		ld3w {z26.s, z27.s, z28.s}, p6/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5c1f41b		ld3d {z27.d, z28.d, z29.d}, p5/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e471f01f		st4b {z31.b, z0.b, z1.b, z2.b}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e4f1f000		st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e571ec01		st4w {z1.s, z2.s, z3.s, z4.s}, p3, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e5e27002		st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]
+0x~~~~~~~~~~~~~~~~  a461f419		ld4b {z25.b, z26.b, z27.b, z28.b}, p5/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a4e1f81a		ld4h {z26.h, z27.h, z28.h, z29.h}, p6/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a562d81b		ld4w {z27.s, z28.s, z29.s, z30.s}, p6/z, [x0, x2, lsl #2]
+0x~~~~~~~~~~~~~~~~  a5e1f41c		ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]
 0x~~~~~~~~~~~~~~~~  d65f03c0		ret
diff --git a/test/test-trace-reference/log-disasm-colour b/test/test-trace-reference/log-disasm-colour
index 9486236c..583328a3 100644
--- a/test/test-trace-reference/log-disasm-colour
+++ b/test/test-trace-reference/log-disasm-colour
@@ -2384,4 +2384,70 @@
 0x~~~~~~~~~~~~~~~~  2f27e47d		ucvtf v29.2s, v3.2s, #25
 0x~~~~~~~~~~~~~~~~  6e21daf6		ucvtf v22.4s, v23.4s
 0x~~~~~~~~~~~~~~~~  6f27e532		ucvtf v18.4s, v9.4s, #25
+0x~~~~~~~~~~~~~~~~  e5810c0c		str p12, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5810c0d		str p13, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5810c0e		str p14, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5810c0f		str p15, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85810c08		ldr p8, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85810c09		ldr p9, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85810c0a		ldr p10, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85810c0b		ldr p11, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5814c00		str z0, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5814c01		str z1, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5814c02		str z2, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e5814c03		str z3, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85814c14		ldr z20, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85814c15		ldr z21, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85814c16		ldr z22, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  85814c17		ldr z23, [x0, #11, mul vl]
+0x~~~~~~~~~~~~~~~~  e403e800		st1b {z0.b}, p2, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e4a3e401		st1h {z1.h}, p1, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e5434402		st1w {z2.s}, p1, [x0, x3, lsl #2]
+0x~~~~~~~~~~~~~~~~  e5e3e803		st1d {z3.d}, p2, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a403a414		ld1b {z20.b}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4a24815		ld1h {z21.h}, p2/z, [x0, x2, lsl #1]
+0x~~~~~~~~~~~~~~~~  a543a416		ld1w {z22.s}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5e3a417		ld1d {z23.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e423e402		st1b {z2.h}, p1, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e443e803		st1b {z3.s}, p2, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e463e804		st1b {z4.d}, p2, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e4c3e400		st1h {z0.s}, p1, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e4e24401		st1h {z1.d}, p1, [x0, x2, lsl #1]
+0x~~~~~~~~~~~~~~~~  e563e402		st1w {z2.d}, p1, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4224414		ld1b {z20.h}, p1/z, [x0, x2]
+0x~~~~~~~~~~~~~~~~  a443a415		ld1b {z21.s}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a463a416		ld1b {z22.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4c3a817		ld1h {z23.s}, p2/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4e3a818		ld1h {z24.d}, p2/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a563a414		ld1w {z20.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5c3a415		ld1sb {z21.h}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5a3a416		ld1sb {z22.s}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5824817		ld1sb {z23.d}, p2/z, [x0, x2]
+0x~~~~~~~~~~~~~~~~  a523a818		ld1sh {z24.s}, p2/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a503a414		ld1sh {z20.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a483a415		ld1sw {z21.d}, p1/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e432f000		st2b {z0.b, z1.b}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e4b2f001		st2h {z1.h, z2.h}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e5226c02		st2w {z2.s, z3.s}, p3, [x0, x2, lsl #2]
+0x~~~~~~~~~~~~~~~~  e5b2f003		st2d {z3.d, z4.d}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a422d414		ld2b {z20.b, z21.b}, p5/z, [x0, x2]
+0x~~~~~~~~~~~~~~~~  a4a2f815		ld2h {z21.h, z22.h}, p6/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a522f816		ld2w {z22.s, z23.s}, p6/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a5a2f417		ld2d {z23.d, z24.d}, p5/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e451f004		st3b {z4.b, z5.b, z6.b}, p4, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e4d1f005		st3h {z5.h, z6.h, z7.h}, p4, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e551ec06		st3w {z6.s, z7.s, z8.s}, p3, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e5c27007		st3d {z7.d, z8.d, z9.d}, p4, [x0, x2, lsl #3]
+0x~~~~~~~~~~~~~~~~  a441f418		ld3b {z24.b, z25.b, z26.b}, p5/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a4c2d819		ld3h {z25.h, z26.h, z27.h}, p6/z, [x0, x2, lsl #1]
+0x~~~~~~~~~~~~~~~~  a541f81a		ld3w {z26.s, z27.s, z28.s}, p6/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  a5c1f41b		ld3d {z27.d, z28.d, z29.d}, p5/z, [x0, #3, mul vl]
+0x~~~~~~~~~~~~~~~~  e471f01f		st4b {z31.b, z0.b, z1.b, z2.b}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e4f1f000		st4h {z0.h, z1.h, z2.h, z3.h}, p4, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e571ec01		st4w {z1.s, z2.s, z3.s, z4.s}, p3, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  e5e27002		st4d {z2.d, z3.d, z4.d, z5.d}, p4, [x0, x2, lsl #3]
+0x~~~~~~~~~~~~~~~~  a461f419		ld4b {z25.b, z26.b, z27.b, z28.b}, p5/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a4e1f81a		ld4h {z26.h, z27.h, z28.h, z29.h}, p6/z, [x0, #4, mul vl]
+0x~~~~~~~~~~~~~~~~  a562d81b		ld4w {z27.s, z28.s, z29.s, z30.s}, p6/z, [x0, x2, lsl #2]
+0x~~~~~~~~~~~~~~~~  a5e1f41c		ld4d {z28.d, z29.d, z30.d, z31.d}, p5/z, [x0, #4, mul vl]
 0x~~~~~~~~~~~~~~~~  d65f03c0		ret
diff --git a/test/test-trace-reference/log-regs b/test/test-trace-reference/log-regs
index ed0d0c45..0894e3d3 100644
--- a/test/test-trace-reference/log-regs
+++ b/test/test-trace-reference/log-regs
@@ -1,740 +1,794 @@
-#    x0: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0300003000300303
-#    x4: 0x0400004000400404
-#    x5: 0x0500005000500505
-#    x6: 0x0600006000600606
-#    x7: 0x0700007000700707
-#    x8: 0x0800008000800808
-#    x9: 0x0900009000900909
-#   x10: 0x0a0000a000a00a0a
-#   x11: 0x0b0000b000b00b0b
-#   x12: 0x0c0000c000c00c0c
-#   x13: 0x0d0000d000d00d0d
-#   x14: 0x0e0000e000e00e0e
-#   x15: 0x0f0000f000f00f0f
-#   x16: 0x1000010001001010
-#   x17: 0x1100011001101111
-#   x18: 0x1200012001201212
-#   x19: 0x1300013001301313
-#   x20: 0x1400014001401414
-#   x21: 0x1500015001501515
-#   x22: 0x1600016001601616
-#   x23: 0x1700017001701717
-#   x24: 0x1800018001801818
-#   x25: 0x1900019001901919
-#   x26: 0x1a0001a001a01a1a
-#   x27: 0x1b0001b001b01b1b
-#   x28: 0x1c0001c001c01c1c
-#   x29: 0x1d0001d001d01d1d
-#    lr: 0x0000000000000000
-#    sp: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000900909
-#    x6: 0x0f0000f000f00f0f
-#    x9: 0x0000000001501515
-#   x12: 0x1b0001b001b01b1b
-#   x15: 0x0000000002102121
-#   x18: 0x2700027002702727
-#   x21: 0x0000000002d02d2d
-#   x24: 0x3300033003303333
-#   x27: 0x0000000001c01c1c
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000700707
-#    x8: 0x0000000000000000
-#   x11: 0x0000000001b01b1b
-#   x13: 0x0700007000700707
-#   x15: 0x0000000000000080
-#   x18: 0x0000013000130013
-#   x21: 0x0000000002d02d2c
-#   x23: 0x1700017001701716
-#   x25: 0x0000000000200202
-#   x28: 0x1d0001d001d01d1d
-#    x3: 0x0000000000000000
-#    x6: 0x0700007000700707
-#   x17: 0x0000000000130014
-#   x17: 0x0000000000130013
-#   x19: 0x1400014001401414
-#   x19: 0x1400014001401415
-#   x21: 0x0000000001601616
-#   x21: 0x00000000fe9fe9e9
-#   x23: 0xccfffccffccfcccc
-#   x23: 0x3300033003303333
-#   x25: 0x0000000000000006
-#   x27: 0x0000000000000002
-#   x29: 0x0000000000000020
-#    x3: 0x0000000000000005
-#   x13: 0x0000000000e00e0e
-#   x13: 0x00000000ff1ff1f2
-#   x15: 0x1000010001001010
-#   x15: 0xeffffefffeffeff0
-#   x17: 0x00000000e963b635
-#   x20: 0x00000000ad83ccb8
-#   x23: 0x000000003ed5525d
-#   x26: 0x00000000bc365145
-#    x4: 0x0000000000000070
-#    x7: 0x00000000b096abf4
-#   x13: 0x0000000000e00e0e
-#   x13: 0x00000000feffeff0
-#   x16: 0x0000013000130013
-#   x16: 0x00000000e963b635
-#   x19: 0x0000000000000000
-#   x19: 0x0000000000000001
-#   x20: 0x0000000000000001
-#   x20: 0x0000000000000000
-#   x21: 0x0000000000000000
-#   x21: 0x00000000ffffffff
-#   x22: 0x0000000000000000
-#   x22: 0xffffffffffffffff
-#   x23: 0x0000000003303333
-#   x23: 0x0000000000000007
-#   x26: 0x1d0001d001d01d1e
-#   x26: 0x0000000000000002
-#   x29: 0x00000000fffffffa
-#   x29: 0x0000000000000000
-#    x4: 0x0000000000700707
-#    x4: 0xf8ffff8fff8ff8f8
-#    x7: 0x00000000feafeaeb
-#    x7: 0x0000000000000000
-#   x10: 0xe4fffe4ffe4fe4e5
-#   x10: 0x0000000001b01b1b
-#   x13: 0x0000000001e01e01
-#   x16: 0xfffffecf168f49d9
-#   x19: 0x00000000ffffffff
-#   x22: 0x3300033003303334
-#   x25: 0x0000000001000000
-#   x28: 0x0000000000000000
-#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
-#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
-#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000019590
-#    x7: 0x0000000000000340
-#    x9: 0x0000000070000000
-#   x12: 0x2c2a28262422201e
-#   x15: 0x0000000000000040
-#   x17: 0x0000000000000000
-#   x19: 0x0000000000000080
-#   x22: 0x0000000000302010
-#   x25: 0x00000000371b0900
-#   x29: 0x0000000000000100
-#    x5: 0x00000000feb67b00
-#    x8: 0xffffce5f00000000
-#   x11: 0x000000002422201e
-#   x13: 0x0000000000000001
-#   x15: 0x0000000000000082
-#   x16: 0x0000000000000083
-#   x17: 0x00000000ffffff7b
-#   x18: 0xffffffffffffff7a
-#   x19: 0x0000000000000086
-#   x20: 0x0000000000000087
-#   x22: 0x000000001b0e0500
-#   x26: 0xe3e9eff5fbff0100
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000001498500
-#    x8: 0x000000008fffffff
-#   x10: 0xffffffffdbdddfe1
-#   x12: 0x00000000ffffffff
-#   x14: 0xffffffffffffff7e
-#   x16: 0x0000000000000085
-#   x18: 0xffffffffffffff7a
-#   x20: 0x00000000fffffbfc
-#   x22: 0xfffffffffcfdfeff
-#   x24: 0x00000000c8e4f6ff
-#   x26: 0xfffffffffcfdfeff
-#   x28: 0x00000000fffeffff
-#    x3: 0xfffffffffeb67bff
-#    x6: 0x000000008fffffff
-#    x9: 0xffffffffffffffff
-#   x12: 0x0000000080000000
-#   x14: 0x4100000000000000
-#   x16: 0x000000007bffffff
-#   x18: 0x8600000000000000
-#   x20: 0x0000000000000304
-#   x22: 0x0000000002030001
-#   x24: 0x0000000000091b37
-#   x26: 0x0000000006040200
-#   x29: 0x0000000000020000
-#    x4: 0x0000000071498500
-#    x7: 0x000000008fffffff
-#   x10: 0x00000000a422201d
-#   x13: 0x40ffffffffffff7d
-#   x16: 0x000000000000000c
-#   x18: 0x0000000000000060
-#   x22: 0x0000000000000004
-#   x24: 0xffffffffffffff09
-#   x26: 0x00000000fffffcff
-#   x29: 0x0000000000000000
-#   x12: 0x1080ffffffffffde
-#   x24: 0x0000000000000001
-#   x27: 0x0000000000000001
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000001
-#    x6: 0x0000000000000001
-#    x8: 0x0000000000000001
-#   x10: 0x0000000000000001
-#   x12: 0x0000000000000001
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000001
-#    x9: 0x0000000000000001
-#   x12: 0x0000000000000001
-#   x14: 0x0000000000000001
-#   x16: 0x0000000000000001
-#   x18: 0x0000000000000001
-#   x20: 0x0000000000000001
-#   x22: 0x0000000000000001
-#   x24: 0x00000000371b0c01
-#   x27: 0x00000000fffeffff
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x5: 0xffffffff70000002
-#    x8: 0x0000000000000001
-#   x10: 0x000000000000001e
-#   x12: 0x00000000ffffff7d
-#   x14: 0x0000000000000082
-#   x16: 0x00000000ffffff7b
-#   x18: 0x0000000000000086
-#   x24: 0x0000000000040000
-#   x26: 0x0000000001fff000
-#   x28: 0x0000000000000000
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000000
-#    x6: 0x000000000000003f
-#    x8: 0x0000000000000000
-#   x11: 0x0000000000000000
-#   x22: 0x0000000000000000
-#   x28: 0x0000000000000000
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000002
-#    x6: 0x000000000000ffff
-#    x8: 0x0000000000000001
-#   x10: 0x0000000000000000
-#    x3: 0x0000000000000000
-#   x18: 0x0000000000000000
-#   x29: 0x0000000000000000
-#    x9: 0x0000000000000000
-#    lr: 0x0000000000000000
-#   x16: 0x0000000000000000
-#   x18: 0x0000000000000000
-#   x26: 0x0000000000000009
-#   x25: 0x0000000000000000
-#    x9: 0x0000000000000009
-#   x19: 0x0000000000000007
-#    x6: 0x0000000000000008
-#   x22: 0x0000000000000008
-#   x29: 0x0000000000000000
-#   x26: 0x0000000000000000
-#   x13: 0x0000000000000000
-#    x5: 0x0000000000000000
-#   x21: 0x0000000000000014
-#   x18: 0x0000000000000000
-#    x8: 0x0000000000000000
-#   x17: 0x0000000000000000
-#   x29: 0x0000000000000000
-#   x25: 0x0000000000000000
-#    lr: 0x0000000000000000
-#   x27: 0x0000000000000000
-#   x15: 0x0000000000000001
-#   x16: 0x0000000000000009
-#   x13: 0x000000000000001b
-#    x3: 0x000000000000001d
-#   x26: 0x0000000000000001
-#   x27: 0x0000000000000001
-#   x29: 0x0000000000000001
-#    x6: 0x000000000000000c
-#   x25: 0x0000000000000000
-#    x9: 0x0000000000000000
-#   x17: 0x0000000000000000
-#   x19: 0x0000000000000000
-#   x22: 0x0000000000000000
-#   x14: 0x0000000000000018
-#    x3: 0x0000000000000000
-#   x11: 0x0000000000000000
-#    x7: 0x0000000000000000
-#   x18: 0x0000000000000000
-#   x14: 0x0000000000000000
-#   x22: 0x0000000000000000
-#    x8: 0x0000000000000000
-#    x7: 0x0000000000000018
-#   x22: 0x00008a4396000000
-#   x18: 0x0000000000000001
-#   x18: 0x0000000000000000
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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+#            x24: 0x0000000000091b37
+#            w26:         0x06040200
+#            x29: 0x0000000000020000
+#             w4:         0x71498500
+#             x7: 0x000000008fffffff
+#            w10:         0xa422201d
+#            x13: 0x40ffffffffffff7d
+#            w16:         0x0000000c
+#            x18: 0x0000000000000060
+#            w22:         0x00000004
+#            x24: 0xffffffffffffff09
+#            w26:         0xfffffcff
+#            x29: 0x0000000000000000
+#            x12: 0x1080ffffffffffde
+#            w24:         0x00000001
+#            w27:         0x00000001
+#             w2:         0x00000001
+#             w4:         0x00000001
+#             w6:         0x00000001
+#             w8:         0x00000001
+#            w10:         0x00000001
+#            w12:         0x00000001
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000001
+#             w9:         0x00000001
+#            w12:         0x00000001
+#            w14:         0x00000001
+#            w16:         0x00000001
+#            w18:         0x00000001
+#            w20:         0x00000001
+#            w22:         0x00000001
+#            w24:         0x371b0c01
+#            x27: 0x00000000fffeffff
+#             w2:         0xfeb67bfe
+#             x5: 0xffffffff70000002
+#             w8:         0x00000001
+#            x10: 0x000000000000001e
+#            w12:         0xffffff7d
+#            x14: 0x0000000000000082
+#            w16:         0xffffff7b
+#            x18: 0x0000000000000086
+#            w24:         0x00040000
+#            x26: 0x0000000001fff000
+#            w28:         0x00000000
+#             x2: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000000
+#             x6: 0x000000000000003f
+#             w8:         0x00000000
+#            x11: 0x0000000000000000
+#            x22: 0x0000000000000000
+#            w28:         0x00000000
+#             x2: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000002
+#             x6: 0x000000000000ffff
+#             w8:         0x00000001
+#            x10: 0x0000000000000000
+#             x3: 0x0000000000000000
+#            w18:         0x00000000
+#            w29:         0x00000000
+#             x9: 0x0000000000000000
+#             lr: 0x0000000000000000
+#            w16:         0x00000000
+#            w18:         0x00000000
+#            x26: 0xffffffffffffffff
+#            x25: 0x0000000000000000
+#             w9:         0x7fffffff
+#            w19:         0xffffffff
+#             x6: 0x7fffffffffffffff
+#            x22: 0xffffffffffffffff
+#            w29:         0x00000000
+#            w26:         0x00000000
+#            x13: 0x0000000000000000
+#             x5: 0x0000000000000000
+#            w21:         0x7fffffff
+#            w18:         0x00000000
+#             x8: 0x0000000000000000
+#            x17: 0x0000000000000000
+#            w29:         0x00000000
+#            w25:         0x00000000
+#             lr: 0x0000000000000000
+#            x27: 0x0000000000000000
+#            w15:         0x00000001
+#            w16:         0x00000000
+#            x13: 0x7fffffffffffffff
+#             x3: 0x0000000000000000
+#            w26:         0x00000000
+#            x27: 0x0000000000000000
+#            x29: 0x0000000000000001
+#             w6:         0x7fffffff
+#            w25:         0x00000000
+#             w9:         0x00000000
+#            w17:         0x00000000
+#            x19: 0x0000000000000000
+#            x22: 0x0000000000000000
+#            x14: 0x0000000000000000
+#             x3: 0x0000000000000000
+#            w11:         0x00000000
+#             w7:         0x00000000
+#            w18:         0x00000000
+#            w14:         0x00000000
+#            x22: 0x0000000000000000
+#             x8: 0x0000000000000000
+#             x7: 0x0000000000000000
+#            x22: 0x0000000000000000
+#            w18:         0x00000001
+#            x18: 0x0000000000000000
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x18: 0x0000000000000000
+#            x28: 0xe3e2e3e2e3e2e3e2
+#            w21:         0x00000000
+#            w13:         0x00000000
+#            x24: 0x0000000000000000
+#             x7: 0x00000000000003c9
+#            x29: 0x0000000000000000
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
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+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             lr: 0x0000000000000000
+#            x18: 0x0000000000000000
diff --git a/test/test-trace-reference/log-regs-colour b/test/test-trace-reference/log-regs-colour
index d989326b..0df9f2e5 100644
--- a/test/test-trace-reference/log-regs-colour
+++ b/test/test-trace-reference/log-regs-colour
@@ -1,740 +1,794 @@
-#    x0: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0300003000300303
-#    x4: 0x0400004000400404
-#    x5: 0x0500005000500505
-#    x6: 0x0600006000600606
-#    x7: 0x0700007000700707
-#    x8: 0x0800008000800808
-#    x9: 0x0900009000900909
-#   x10: 0x0a0000a000a00a0a
-#   x11: 0x0b0000b000b00b0b
-#   x12: 0x0c0000c000c00c0c
-#   x13: 0x0d0000d000d00d0d
-#   x14: 0x0e0000e000e00e0e
-#   x15: 0x0f0000f000f00f0f
-#   x16: 0x1000010001001010
-#   x17: 0x1100011001101111
-#   x18: 0x1200012001201212
-#   x19: 0x1300013001301313
-#   x20: 0x1400014001401414
-#   x21: 0x1500015001501515
-#   x22: 0x1600016001601616
-#   x23: 0x1700017001701717
-#   x24: 0x1800018001801818
-#   x25: 0x1900019001901919
-#   x26: 0x1a0001a001a01a1a
-#   x27: 0x1b0001b001b01b1b
-#   x28: 0x1c0001c001c01c1c
-#   x29: 0x1d0001d001d01d1d
-#    lr: 0x0000000000000000
-#    sp: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000900909
-#    x6: 0x0f0000f000f00f0f
-#    x9: 0x0000000001501515
-#   x12: 0x1b0001b001b01b1b
-#   x15: 0x0000000002102121
-#   x18: 0x2700027002702727
-#   x21: 0x0000000002d02d2d
-#   x24: 0x3300033003303333
-#   x27: 0x0000000001c01c1c
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000700707
-#    x8: 0x0000000000000000
-#   x11: 0x0000000001b01b1b
-#   x13: 0x0700007000700707
-#   x15: 0x0000000000000080
-#   x18: 0x0000013000130013
-#   x21: 0x0000000002d02d2c
-#   x23: 0x1700017001701716
-#   x25: 0x0000000000200202
-#   x28: 0x1d0001d001d01d1d
-#    x3: 0x0000000000000000
-#    x6: 0x0700007000700707
-#   x17: 0x0000000000130014
-#   x17: 0x0000000000130013
-#   x19: 0x1400014001401414
-#   x19: 0x1400014001401415
-#   x21: 0x0000000001601616
-#   x21: 0x00000000fe9fe9e9
-#   x23: 0xccfffccffccfcccc
-#   x23: 0x3300033003303333
-#   x25: 0x0000000000000006
-#   x27: 0x0000000000000002
-#   x29: 0x0000000000000020
-#    x3: 0x0000000000000005
-#   x13: 0x0000000000e00e0e
-#   x13: 0x00000000ff1ff1f2
-#   x15: 0x1000010001001010
-#   x15: 0xeffffefffeffeff0
-#   x17: 0x00000000e963b635
-#   x20: 0x00000000ad83ccb8
-#   x23: 0x000000003ed5525d
-#   x26: 0x00000000bc365145
-#    x4: 0x0000000000000070
-#    x7: 0x00000000b096abf4
-#   x13: 0x0000000000e00e0e
-#   x13: 0x00000000feffeff0
-#   x16: 0x0000013000130013
-#   x16: 0x00000000e963b635
-#   x19: 0x0000000000000000
-#   x19: 0x0000000000000001
-#   x20: 0x0000000000000001
-#   x20: 0x0000000000000000
-#   x21: 0x0000000000000000
-#   x21: 0x00000000ffffffff
-#   x22: 0x0000000000000000
-#   x22: 0xffffffffffffffff
-#   x23: 0x0000000003303333
-#   x23: 0x0000000000000007
-#   x26: 0x1d0001d001d01d1e
-#   x26: 0x0000000000000002
-#   x29: 0x00000000fffffffa
-#   x29: 0x0000000000000000
-#    x4: 0x0000000000700707
-#    x4: 0xf8ffff8fff8ff8f8
-#    x7: 0x00000000feafeaeb
-#    x7: 0x0000000000000000
-#   x10: 0xe4fffe4ffe4fe4e5
-#   x10: 0x0000000001b01b1b
-#   x13: 0x0000000001e01e01
-#   x16: 0xfffffecf168f49d9
-#   x19: 0x00000000ffffffff
-#   x22: 0x3300033003303334
-#   x25: 0x0000000001000000
-#   x28: 0x0000000000000000
-#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
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diff --git a/test/test-trace-reference/log-state b/test/test-trace-reference/log-state
index fe9bca9a..8113a01d 100644
--- a/test/test-trace-reference/log-state
+++ b/test/test-trace-reference/log-state
@@ -1,97 +1,310 @@
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+#      p5<63:48>: 0b 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0
+#      p5<79:64>: 0b 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1
+#       p6<15:0>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<31:16>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<47:32>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<63:48>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p6<79:64>: 0b 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#       p7<15:0>: 0b 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
+#      p7<31:16>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1
+#      p7<47:32>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1
+#      p7<63:48>: 0b 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#      p7<79:64>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#       p8<15:0>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+#      p8<31:16>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 0 1 1 1
+#      p8<47:32>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p8<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 1
+#      p8<79:64>: 0b 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#       p9<15:0>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
+#      p9<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#      p9<47:32>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0
+#      p9<63:48>: 0b 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
+#      p9<79:64>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1
+#      p10<15:0>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p10<31:16>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#     p10<47:32>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#     p10<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p10<79:64>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#      p11<15:0>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
+#     p11<31:16>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+#     p11<47:32>: 0b 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
+#     p11<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#     p11<79:64>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0
+#      p12<15:0>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p12<31:16>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p12<47:32>: 0b 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
+#     p12<63:48>: 0b 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
+#     p12<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
+#      p13<15:0>: 0b 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<31:16>: 0b 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<47:32>: 0b 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
+#     p13<63:48>: 0b 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
+#     p13<79:64>: 0b 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
+#      p14<15:0>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<31:16>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<47:32>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<63:48>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p14<79:64>: 0b 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#      p15<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
+#     p15<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
+#     p15<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
+#     p15<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
+#     p15<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
+#      FFR<15:0>: 0b 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
+#     FFR<31:16>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<47:32>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<63:48>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#     FFR<79:64>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#             w3:         0x00900909
+#             x6: 0x0f0000f000f00f0f
 # NZCV: N:0 Z:0 C:0 V:0
-#    x9: 0x0000000001501515
+#             w9:         0x01501515
 # NZCV: N:0 Z:0 C:0 V:0
-#   x12: 0x1b0001b001b01b1b
-#   x15: 0x0000000002102121
-#   x18: 0x2700027002702727
+#            x12: 0x1b0001b001b01b1b
+#            w15:         0x02102121
+#            x18: 0x2700027002702727
 # NZCV: N:0 Z:0 C:0 V:0
-#   x21: 0x0000000002d02d2d
+#            w21:         0x02d02d2d
 # NZCV: N:0 Z:0 C:0 V:0
-#   x24: 0x3300033003303333
-#   x27: 0x0000000001c01c1c
-#    x2: 0x~~~~~~~~~~~~~~~~
+#            x24: 0x3300033003303333
+#            w27:         0x01c01c1c
+#             x2: 0x~~~~~~~~~~~~~~~~
 # NZCV: N:0 Z:0 C:0 V:0
-#    x5: 0x0000000000700707
+#             w5:         0x00700707
 # NZCV: N:0 Z:1 C:0 V:0
-#    x8: 0x0000000000000000
-#   x11: 0x0000000001b01b1b
-#   x13: 0x0700007000700707
-#   x15: 0x0000000000000080
-#   x18: 0x0000013000130013
-#   x21: 0x0000000002d02d2c
-#   x23: 0x1700017001701716
-#   x25: 0x0000000000200202
-#   x28: 0x1d0001d001d01d1d
+#             x8: 0x0000000000000000
+#            w11:         0x01b01b1b
+#            x13: 0x0700007000700707
+#            w15:         0x00000080
+#            x18: 0x0000013000130013
+#            w21:         0x02d02d2c
+#            x23: 0x1700017001701716
+#            w25:         0x00200202
+#            x28: 0x1d0001d001d01d1d
 # NZCV: N:0 Z:1 C:0 V:0
-#    x3: 0x0000000000000000
+#             w3:         0x00000000
 # NZCV: N:0 Z:0 C:0 V:0
-#    x6: 0x0700007000700707
+#             x6: 0x0700007000700707
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:0 V:0
@@ -104,2989 +317,5897 @@
 # NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:1
 # NZCV: N:1 Z:0 C:0 V:0
-#   x17: 0x0000000000130014
-#   x17: 0x0000000000130013
-#   x19: 0x1400014001401414
-#   x19: 0x1400014001401415
-#   x21: 0x0000000001601616
-#   x21: 0x00000000fe9fe9e9
-#   x23: 0xccfffccffccfcccc
-#   x23: 0x3300033003303333
-#   x25: 0x0000000000000006
-#   x27: 0x0000000000000002
-#   x29: 0x0000000000000020
-#    x3: 0x0000000000000005
+#            w17:         0x00130014
+#            w17:         0x00130013
+#            x19: 0x1400014001401414
+#            x19: 0x1400014001401415
+#            w21:         0x01601616
+#            w21:         0xfe9fe9e9
+#            x23: 0xccfffccffccfcccc
+#            x23: 0x3300033003303333
+#            w25:         0x00000006
+#            x27: 0x0000000000000002
+#            w29:         0x00000020
+#             x3: 0x0000000000000005
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:0
 # NZCV: N:1 Z:0 C:0 V:0
-#   x13: 0x0000000000e00e0e
-#   x13: 0x00000000ff1ff1f2
-#   x15: 0x1000010001001010
-#   x15: 0xeffffefffeffeff0
-#   x17: 0x00000000e963b635
-#   x20: 0x00000000ad83ccb8
-#   x23: 0x000000003ed5525d
-#   x26: 0x00000000bc365145
-#    x4: 0x0000000000000070
-#    x7: 0x00000000b096abf4
-#   x13: 0x0000000000e00e0e
-#   x13: 0x00000000feffeff0
-#   x16: 0x0000013000130013
-#   x16: 0x00000000e963b635
-#   x19: 0x0000000000000000
-#   x19: 0x0000000000000001
-#   x20: 0x0000000000000001
-#   x20: 0x0000000000000000
-#   x21: 0x0000000000000000
-#   x21: 0x00000000ffffffff
-#   x22: 0x0000000000000000
-#   x22: 0xffffffffffffffff
-#   x23: 0x0000000003303333
-#   x23: 0x0000000000000007
-#   x26: 0x1d0001d001d01d1e
-#   x26: 0x0000000000000002
-#   x29: 0x00000000fffffffa
-#   x29: 0x0000000000000000
-#    x4: 0x0000000000700707
-#    x4: 0xf8ffff8fff8ff8f8
-#    x7: 0x00000000feafeaeb
-#    x7: 0x0000000000000000
-#   x10: 0xe4fffe4ffe4fe4e5
-#   x10: 0x0000000001b01b1b
-#   x13: 0x0000000001e01e01
-#   x16: 0xfffffecf168f49d9
-#   x19: 0x00000000ffffffff
-#   x22: 0x3300033003303334
-#   x25: 0x0000000001000000
-#   x28: 0x0000000000000000
-#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
-#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
-#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000019590
-#    x7: 0x0000000000000340
-#    x9: 0x0000000070000000
-#   x12: 0x2c2a28262422201e
-#   x15: 0x0000000000000040
-#   x17: 0x0000000000000000
-#   x19: 0x0000000000000080
-#   x22: 0x0000000000302010
-#   x25: 0x00000000371b0900
-#   x29: 0x0000000000000100
-#    x5: 0x00000000feb67b00
-#    x8: 0xffffce5f00000000
-#   x11: 0x000000002422201e
-#   x13: 0x0000000000000001
-#   x15: 0x0000000000000082
-#   x16: 0x0000000000000083
-#   x17: 0x00000000ffffff7b
-#   x18: 0xffffffffffffff7a
-#   x19: 0x0000000000000086
-#   x20: 0x0000000000000087
-#   x22: 0x000000001b0e0500
-#   x26: 0xe3e9eff5fbff0100
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000001498500
-#    x8: 0x000000008fffffff
-#   x10: 0xffffffffdbdddfe1
-#   x12: 0x00000000ffffffff
-#   x14: 0xffffffffffffff7e
+#            w13:         0x00e00e0e
+#            w13:         0xff1ff1f2
+#            x15: 0x1000010001001010
+#            x15: 0xeffffefffeffeff0
+#            w17:         0xe963b635
+#            w20:         0xad83ccb8
+#            w23:         0x3ed5525d
+#            w26:         0xbc365145
+#             w4:         0x00000070
+#             w7:         0xb096abf4
+#            w13:         0x00e00e0e
+#            w13:         0xfeffeff0
+#            x16: 0x0000013000130013
+#            x16: 0x00000000e963b635
+#            w19:         0x00000000
+#            w19:         0x00000001
+#            x20: 0x0000000000000001
+#            x20: 0x0000000000000000
+#            w21:         0x00000000
+#            w21:         0xffffffff
+#            x22: 0x0000000000000000
+#            x22: 0xffffffffffffffff
+#            w23:         0x03303333
+#            w23:         0x00000007
+#            x26: 0x1d0001d001d01d1e
+#            x26: 0x0000000000000002
+#            w29:         0xfffffffa
+#            w29:         0x00000000
+#             x4: 0x0000000000700707
+#             x4: 0xf8ffff8fff8ff8f8
+#             w7:         0xfeafeaeb
+#             w7:         0x00000000
+#            x10: 0xe4fffe4ffe4fe4e5
+#            x10: 0x0000000001b01b1b
+#            w13:         0x01e01e01
+#            x16: 0xfffffecf168f49d9
+#            w19:         0xffffffff
+#            x22: 0x3300033003303334
+#            w25:         0x01000000
+#            x28: 0x0000000000000000
+#             w3:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#             x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w8:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w10:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            w13:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            w15:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            w16:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            w17:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#            w18:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#            w19:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w20:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            w23:         0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x17161514 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000003020100
+#                                  ╙─ 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000007060504
+#                                  ╙─ 0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000033323130
+#                                  ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000037363534
+#                                  ╙─ 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000043424140
+#                                  ╙─ 0x43424140 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000047464544
+#                                  ╙─ 0x47464544 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x43424140 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            w29:         0x4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000058
+#                                  ╙─ 0x58 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w3:         0x0000005a
+#                                  ╙─ 0x5a <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x0000005a
+#                                  ╙─ 0x5a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x0000005c
+#                                  ╙─ 0x5c <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00005d5c
+#                                  ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00006160
+#                                  ╙─ 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00006160
+#                                  ╙─ 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00006564
+#                                  ╙─ 0x6564 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000064
+#                                  ╙─ 0x64 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000066
+#                                  ╙─ 0x66 <- 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000066
+#                                  ╙─ 0x66 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000068
+#                                  ╙─ 0x68 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00006968
+#                                  ╙─ 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00006d6c
+#                                  ╙─ 0x6d6c <- 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000006d6c
+#                                  ╙─ 0x6d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000007170
+#                                  ╙─ 0x7170 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0000000003020100
+#                                  ╙─ 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0000000073727170
+#                                  ╙─ 0x73727170 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x11: 0x000000007b7a7978
+#                                  ╙─ 0x7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#            w12:         0x0a090807 <- 0x~~~~~~~~~~~~~~~~
+#            x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#            w14:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            w15:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            w16:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#            w17:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#            w18:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            x19: 0x0000000000000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            w20:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#            x21: 0x0000000000000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#            x22: 0x000000000a090807
+#                                  ╙─ 0x0a090807 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            w27:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w2:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00019590
+#             x7: 0x0000000000000340
+#             w9:         0x70000000
+#            x12: 0x2c2a28262422201e
+#            w15:         0x00000040
+#            x17: 0x0000000000000000
+#            w19:         0x00000080
+#            x22: 0x0000000000302010
+#            w25:         0x371b0900
+#            x29: 0x0000000000000100
+#             w5:         0xfeb67b00
+#             x8: 0xffffce5f00000000
+#            w11:         0x2422201e
+#            x13: 0x0000000000000001
+#            x15: 0x0000000000000082
+#            x16: 0x0000000000000083
+#            x17: 0x00000000ffffff7b
+#            x18: 0xffffffffffffff7a
+#            x19: 0x0000000000000086
+#            x20: 0x0000000000000087
+#            w22:         0x1b0e0500
+#            x26: 0xe3e9eff5fbff0100
+#             w2:         0x00010000
+#             x5: 0x0000000001498500
+#             w8:         0x8fffffff
+#            x10: 0xffffffffdbdddfe1
+#            w12:         0xffffffff
+#            x14: 0xffffffffffffff7e
 # NZCV: N:0 Z:0 C:0 V:0
-#   x16: 0x0000000000000085
+#            w16:         0x00000085
 # NZCV: N:1 Z:0 C:0 V:0
-#   x18: 0xffffffffffffff7a
-#   x20: 0x00000000fffffbfc
-#   x22: 0xfffffffffcfdfeff
+#            x18: 0xffffffffffffff7a
+#            w20:         0xfffffbfc
+#            x22: 0xfffffffffcfdfeff
 # NZCV: N:1 Z:0 C:0 V:0
-#   x24: 0x00000000c8e4f6ff
+#            w24:         0xc8e4f6ff
 # NZCV: N:1 Z:0 C:0 V:0
-#   x26: 0xfffffffffcfdfeff
-#   x28: 0x00000000fffeffff
-#    x3: 0xfffffffffeb67bff
-#    x6: 0x000000008fffffff
-#    x9: 0xffffffffffffffff
-#   x12: 0x0000000080000000
-#   x14: 0x4100000000000000
-#   x16: 0x000000007bffffff
-#   x18: 0x8600000000000000
-#   x20: 0x0000000000000304
-#   x22: 0x0000000002030001
-#   x24: 0x0000000000091b37
-#   x26: 0x0000000006040200
-#   x29: 0x0000000000020000
-#    x4: 0x0000000071498500
-#    x7: 0x000000008fffffff
+#            x26: 0xfffffffffcfdfeff
+#            w28:         0xfffeffff
+#             x3: 0xfffffffffeb67bff
+#             w6:         0x8fffffff
+#             x9: 0xffffffffffffffff
+#            w12:         0x80000000
+#            x14: 0x4100000000000000
+#            w16:         0x7bffffff
+#            x18: 0x8600000000000000
+#            w20:         0x00000304
+#            x22: 0x0000000002030001
+#            x24: 0x0000000000091b37
+#            w26:         0x06040200
+#            x29: 0x0000000000020000
+#             w4:         0x71498500
+#             x7: 0x000000008fffffff
 # NZCV: N:1 Z:0 C:0 V:1
-#   x10: 0x00000000a422201d
+#            w10:         0xa422201d
 # NZCV: N:0 Z:0 C:1 V:0
-#   x13: 0x40ffffffffffff7d
-#   x16: 0x000000000000000c
-#   x18: 0x0000000000000060
-#   x22: 0x0000000000000004
-#   x24: 0xffffffffffffff09
-#   x26: 0x00000000fffffcff
-#   x29: 0x0000000000000000
-#   x12: 0x1080ffffffffffde
-#   x24: 0x0000000000000001
-#   x27: 0x0000000000000001
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000001
-#    x6: 0x0000000000000001
-#    x8: 0x0000000000000001
-#   x10: 0x0000000000000001
-#   x12: 0x0000000000000001
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000001
-#    x9: 0x0000000000000001
-#   x12: 0x0000000000000001
-#   x14: 0x0000000000000001
-#   x16: 0x0000000000000001
-#   x18: 0x0000000000000001
-#   x20: 0x0000000000000001
-#   x22: 0x0000000000000001
-#   x24: 0x00000000371b0c01
-#   x27: 0x00000000fffeffff
+#            x13: 0x40ffffffffffff7d
+#            w16:         0x0000000c
+#            x18: 0x0000000000000060
+#            w22:         0x00000004
+#            x24: 0xffffffffffffff09
+#            w26:         0xfffffcff
+#            x29: 0x0000000000000000
+#            x12: 0x1080ffffffffffde
+#            w24:         0x00000001
+#            w27:         0x00000001
+#             w2:         0x00000001
+#             w4:         0x00000001
+#             w6:         0x00000001
+#             w8:         0x00000001
+#            w10:         0x00000001
+#            w12:         0x00000001
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000001
+#             w9:         0x00000001
+#            w12:         0x00000001
+#            w14:         0x00000001
+#            w16:         0x00000001
+#            w18:         0x00000001
+#            w20:         0x00000001
+#            w22:         0x00000001
+#            w24:         0x371b0c01
+#            x27: 0x00000000fffeffff
 # NZCV: N:1 Z:0 C:1 V:0
-#    x2: 0x~~~~~~~~~~~~~~~~
+#             w2:         0xfeb67bfe
 # NZCV: N:1 Z:0 C:0 V:0
-#    x5: 0xffffffff70000002
-#    x8: 0x0000000000000001
-#   x10: 0x000000000000001e
-#   x12: 0x00000000ffffff7d
-#   x14: 0x0000000000000082
-#   x16: 0x00000000ffffff7b
-#   x18: 0x0000000000000086
+#             x5: 0xffffffff70000002
+#             w8:         0x00000001
+#            x10: 0x000000000000001e
+#            w12:         0xffffff7d
+#            x14: 0x0000000000000082
+#            w16:         0xffffff7b
+#            x18: 0x0000000000000086
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:1 C:0 V:0
-#   x24: 0x0000000000040000
-#   x26: 0x0000000001fff000
-#   x28: 0x0000000000000000
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000000
-#    x6: 0x000000000000003f
-#    x8: 0x0000000000000000
-#   x11: 0x0000000000000000
-#   x22: 0x0000000000000000
-#   x28: 0x0000000000000000
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000002
-#    x6: 0x000000000000ffff
-#    x8: 0x0000000000000001
-#   x10: 0x0000000000000000
+#            w24:         0x00040000
+#            x26: 0x0000000001fff000
+#            w28:         0x00000000
+#             x2: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000000
+#             x6: 0x000000000000003f
+#             w8:         0x00000000
+#            x11: 0x0000000000000000
+#            x22: 0x0000000000000000
+#            w28:         0x00000000
+#             x2: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000002
+#             x6: 0x000000000000ffff
+#             w8:         0x00000001
+#            x10: 0x0000000000000000
 # NZCV: N:0 Z:1 C:1 V:0
-#    x3: 0x0000000000000000
+#             x3: 0x0000000000000000
 # NZCV: N:1 Z:0 C:0 V:0
-#   v13: 0x00000000000000004036e00cd9b7e45b
-#    v8: 0x00000000000000000000000041c5851e
-#    v1: 0x00000000000000003ff587933f9e0419 (d1: 1.34560)
-#   v25: 0x000000000000000000000000410a4396 (s25: 8.64150)
-#    v1: 0x0000000000000000ffffffffffffffff
-#    v4: 0x00000000000000000000000000000000
-#    v2: 0x00000000000000000000000000000000
-#   v12: 0x000000000000000000000000ffffffff
-#   v13: 0x0000000000000000404633d07142f43a (d13: 44.4048)
-#   v27: 0x000000000000000000000000424094fe (s27: 48.1455)
+#            v13: 0x0000000000000000490ffff1110487fe
+#             v8: 0x0000000000000000000000000e02aff8
+#             d1:                 0x47f000007f823c00 (3.403e+38)
+#            s25:                         0x02825400 (1.915e-37)
+#             v1: 0x0000000000000000ffffffffffffffff
+#             v4: 0x00000000000000000000000000000000
+#             v2: 0x00000000000000000000000000000000
+#            v12: 0x000000000000000000000000ffffffff
+#            d13:                 0x494002008a13204c (7.140e+44)
+#            s27:                         0x0e029fa8 (1.610e-30)
 # NZCV: N:0 Z:0 C:0 V:0
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:0
 # NZCV: N:0 Z:1 C:1 V:0
-#   v19: 0x00000000000000000000000000000000
-#    v0: 0x00000000000000000000000000000000
-#    v1: 0x00000000000000000000000000000000
-#   v22: 0x00000000000000000000000000000000
-#   v27: 0x0000000000000000ffffffffffffffff
-#   v31: 0x0000000000000000ffffffffffffffff
-#   v31: 0x00000000000000000000000000000000
-#    v1: 0x000000000000000000000000ffffffff
-#   v18: 0x00000000000000000000000000000000
-#    v3: 0x00000000000000000000000000000000
-#   v11: 0x000000000000000000000000ffffffff
-#   v17: 0x000000000000000000000000ffffffff
-#   v24: 0x00000000000000000000000000000000
-#   v11: 0x00000000000000000000000000000000
-#    v5: 0x00000000000000000000000000000000
-#   v18: 0x00000000000000000000000000000000
-# NZCV: N:0 Z:0 C:1 V:0
+#            v19: 0x00000000000000000000000000000000
+#             v0: 0x00000000000000000000000000000000
+#             v1: 0x00000000000000000000000000000000
+#            v22: 0x00000000000000000000000000000000
+#            v27: 0x0000000000000000ffffffffffffffff
+#            v31: 0x0000000000000000ffffffffffffffff
+#            v31: 0x000000000000000000000000ffffffff
+#             v1: 0x000000000000000000000000ffffffff
+#            v18: 0x00000000000000000000000000000000
+#             v3: 0x0000000000000000ffffffffffffffff
+#            v11: 0x000000000000000000000000ffffffff
+#            v17: 0x00000000000000000000000000000000
+#            v24: 0x0000000000000000ffffffffffffffff
+#            v11: 0x00000000000000000000000000000000
+#             v5: 0x00000000000000000000000000000000
+#            v18: 0x000000000000000000000000ffffffff
+# NZCV: N:0 Z:0 C:1 V:1
 # NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 # NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:0
 # NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:1 C:1 V:0
-#   v10: 0x00000000000000000000000000000000 (d10: 0.00000)
-#   v22: 0x00000000000000000000000000000000 (s22: 0.00000)
-#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
-#   v11: 0x00000000000000000000000000000000 (d11: 0.00000)
-#    v8: 0x00000000000000000000000000004a0e
-#   v12: 0x0000000000000000000000000000ffff
-#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
-#   v27: 0x0000000000000000000000004072c000 (s27: 3.79297)
-#   v28: 0x00000000000000000000000000000016
-#    v3: 0x00000000000000000000000000000000
-#   x18: 0x0000000000000000
-#   x29: 0x0000000000000000
-#    x9: 0x0000000000000000
-#    lr: 0x0000000000000000
-#   v14: 0x00000000000000000000000000000000
-#   v31: 0x00000000000000000000000000000000
-#   x16: 0x0000000000000000
-#   x18: 0x0000000000000000
-#   x26: 0x0000000000000009
-#   x25: 0x0000000000000000
-#   v30: 0x00000000000000000000000000000000
-#   v12: 0x00000000000000000000000000000012
-#    x9: 0x0000000000000009
-#   x19: 0x0000000000000007
-#    x6: 0x0000000000000008
-#   x22: 0x0000000000000008
-#   v27: 0x00000000000000000000000000000000
-#    v8: 0x00000000000000000000000000000000
-#   x29: 0x0000000000000000
-#   x26: 0x0000000000000000
-#   x13: 0x0000000000000000
-#    x5: 0x0000000000000000
-#   v30: 0x00000000000000000000000000000014
-#   v10: 0x00000000000000000000000000000000
-#   x21: 0x0000000000000014
-#   x18: 0x0000000000000000
-#    x8: 0x0000000000000000
-#   x17: 0x0000000000000000
-#    v0: 0x0000000000000000000000000000001c
-#    v6: 0x00000000000000000000000000000009
-#   x29: 0x0000000000000000
-#   x25: 0x0000000000000000
-#    lr: 0x0000000000000000
-#   x27: 0x0000000000000000
-#   v11: 0x00000000000000000000000000000000
-#   v29: 0x00000000000000000000000000000019
-#   x15: 0x0000000000000001
-#   x16: 0x0000000000000009
-#   x13: 0x000000000000001b
-#    x3: 0x000000000000001d
-#   v24: 0x00000000000000000000000000000001
-#   v14: 0x00000000000000000000000000000001
-#   x26: 0x0000000000000001
-#   x27: 0x0000000000000001
-#   x29: 0x0000000000000001
-#   v12: 0x00000000000000000000000000000001
-#   v15: 0x00000000000000000000000000000000
-#   v13: 0x00000000000000000000000000000000
-#    v8: 0x00000000000000000000000000000000
-#   v31: 0x00000000000000000000000000000000
-#    x6: 0x000000000000000c
-#   x25: 0x0000000000000000
-#    x9: 0x0000000000000000
-#   x17: 0x0000000000000000
-#   x19: 0x0000000000000000
-#   x22: 0x0000000000000000
-#   x14: 0x0000000000000018
-#    x3: 0x0000000000000000
-#   v28: 0x00000000000000000000000000000000
-#    v0: 0x00000000000000000000000000000000
-#    v2: 0x00000000000000000000000000000000
-#    v4: 0x00000000000000000000000000000000
-#   x11: 0x0000000000000000
-#    x7: 0x0000000000000000
-#   x18: 0x0000000000000000
-#   x14: 0x0000000000000000
-#   x22: 0x0000000000000000
-#    x8: 0x0000000000000000
-#    x7: 0x0000000000000018
-#   x22: 0x00008a4396000000
-#    v6: 0x00000000000000007ff0000000000000 (d6: inf)
-#   v26: 0x00000000000000000000000000000000 (s26: 0.00000)
-#   v18: 0x00000000000000000000000000000014 (d18: 9.88131e-323)
-#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
-#   v12: 0x00000000000000000000000000000000 (d12: 0.00000)
-#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
-#   v28: 0x00000000000000000000000000000000 (d28: 0.00000)
-#    v6: 0x00000000000000000000000000000000 (s6: 0.00000)
-#   v20: 0x00000000000000000000000000000014 (d20: 9.88131e-323)
-#    v7: 0x00000000000000000000000000000000 (s7: 0.00000)
-#   v19: 0x00000000000000000000000000000001 (d19: 4.94066e-324)
-#    v0: 0x000000000000000000000000ffffffff (s0: nan)
-#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
-#    v2: 0x00000000000000000000000000000000
-#    v8: 0x0000000000000000c004000000000000 (d8: -2.50000)
-#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
-#   v25: 0x00000000000000000000000000000001
-#   v21: 0x00000000000000000000000040380000 (s21: 2.87500)
-#   x18: 0x0000000000000001
-#   x18: 0x0000000000000000
-#   v20: 0x00000000000000000000000000000001 (d20: 4.94066e-324)
-#    v5: 0x00000000000000000000000000000000 (s5: 0.00000)
-#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
-#   v25: 0x000000000000000000000000ffffffff (s25: nan)
-#    v4: 0x00000000000000000000000000000000
-#   v14: 0x000000000000000000000000ffffffff
-#   v15: 0x000000000000000080000000ffffffff (d15: -2.12200e-314)
-#   v14: 0x0000000000000000000000007fffffff (s14: nan)
-#    v0: 0x00000000000000008000000000000000 (d0: -0.00000)
-#    v0: 0x00000000000000000000000080000014 (s0: -2.80260e-44)
-#   v19: 0x00000000000000008000000040380000 (d19: -5.32312e-315)
-#   v29: 0x00000000000000000000000080000000 (s29: -0.00000)
-#   v31: 0x00000000000000000000000000000000 (d31: 0.00000)
-#   v18: 0x0000000000000000000000007fffffff (s18: nan)
-#    v7: 0x00000000000000007ff0000000000000
-#   v29: 0x000000000000000000000000ffffffff
-#   v11: 0x00000000000000004000000000000000
-#   v18: 0x000000000000000000000000ffffffff
-#   v15: 0x00000000000000007fe0000000000000
-#    v5: 0x0000000000000000000000007f000000
-#   v16: 0x00000000000000000000000000000000 (d16: 0.00000)
-#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
-#   v19: 0x00000000000000000000000000000000 (d19: 0.00000)
-#   v14: 0x00000000000000000000000040400000 (s14: 3.00000)
-#   v20: 0x00000000000000000000000000000000 (d20: 0.00000)
-#    v1: 0x00000000000000000000000000000000 (s1: 0.00000)
-#   v30: 0x00000000000000000000000000000000 (d30: 0.00000)
-#   v24: 0x00000000000000000000000000000000 (s24: 0.00000)
-#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
-#   v13: 0x00000000000000000000000000000000 (s13: 0.00000)
-#   v13: 0x00000000000000000000000000000000 (d13: 0.00000)
-#   v17: 0x00000000000000000000000000000000 (s17: 0.00000)
-#    v0: 0x0000000000000000c000000000000000 (d0: -2.00000)
-#   v15: 0x000000000000000000000000ffffffff (s15: nan)
-#   v21: 0x00000000000000007ff0000000000000
-#   v17: 0x000000000000000000000000ffffffff
-#    v4: 0x00000000000000003ff8000000000000
-#   v14: 0x0000000000000000000000003fc00000
-#   v14: 0x00000000000000001f5ffffffff00000 (d14: 1.45671e-157)
-#    v4: 0x000000000000000000000000fff00000 (s4: nan)
-#   v13: 0x0000000000000000fff0000000000000 (d13: -inf)
-#    v3: 0x00000000000000000000000000000000 (s3: 0.00000)
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-#   v26: 0x00000000000000000000000000000000
-#    v6: 0x00000000000000004022000000000000 (d6: 9.00000)
-#    v5: 0x00000000000000003f90000000000000 (d5: 0.0156250)
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-#   v15: 0x00000000000000000000000000000000 (d15: 0.00000)
-#    v7: 0x00000000000000007ff00000c9800000
-#    v8: 0x0000000000000000c004000000000000
-#   v29: 0x00000000000000000000000000000000 (s29: 0.00000)
-#   v15: 0x0000000000000000000000003c200000 (s15: 0.00976562)
-#   v27: 0x0000000000000000000000003f800000 (s27: 1.00000)
-#   v26: 0x0000000000000000000000003c7fffff (s26: 0.0156250)
-#    v0: 0x000000000000000043d00a0e21904c71
-#    v5: 0x00000000000000000000000000000000
-#   v30: 0x00000000000000003ff0000000000000 (d30: 1.00000)
-#    v3: 0x00000000000000000000000000000000 (d3: 0.00000)
-#   v28: 0x00000000000000004034000000000000 (d28: 20.0000)
-#   v27: 0x00000000000000000000000000000000 (d27: 0.00000)
-#   v11: 0x00000000000000004000000000000000
-#    v0: 0x000000000000000043d00a0e4783c64c
-#   v20: 0x00000000000000000000000000000000 (s20: 0.00000)
-#   v21: 0x00000000000000000000000046160000 (s21: 9600.00)
-#    v6: 0x00000000000000000000000041d80000 (s6: 27.0000)
-#    v7: 0x00000000000000000000000038ff0000 (s7: 0.000121593)
-#   v19: 0x000000000000000043d00a0e4783c64c
-#   v16: 0x00000000000000004000000000000000
-#    v0: 0x00000000000000000000000000000000
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-#   v10: 0x000000000000000000000000ffffffff
-#   v31: 0x403ba7b141b670b1403ef2e47d0325e4
-#   v10: 0x403ba7b141b670b15f9ef2e47cf325e4
-#   v15: 0x000000000000000063300a0d4773c64c
-#   v27: 0x0000000000000000403ef2e441e225e3
-#   v25: 0x00000000000000004044000000000000
-#   v13: 0x00000000000000000000000037feffff
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-#   v10: 0x00000000000000000000000082900a0d
-#   v10: 0x0000000000000000000000003ff03c7f
-#   v31: 0x00000000000000000000000000000000
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-#   v14: 0x000000000000000043d00a0e4783c64c
-#    v3: 0x000000007400000000000000c4000000
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-#   v22: 0x00000000000000003c7fffff3ff00000
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0b0a09080706050403020100fffefdfc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfb <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xeb <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xdb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x0a09080706050403020100fffefdfcfb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xeb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x3a393837363534333231302f2e2d2c2b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x2a292827262524232221201f1e1d1c1b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x1a191817161514131211100f0e0d0c0b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x393837363534333231302f2e2d2c2b2a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x292827262524232221201f1e1d1c1b1a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x191817161514131211100f0e0d0c0b0a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x595857565554535251504f4e4d4c4b4a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x59 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ╙───────────────── 0x403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x2827262524232221 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x302f2e2d2c2b2a29 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x4847464544434241 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x4746454443424140 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ╙───────── 0x5f5e5d5c <- 0x~~~~~~~~~~~~~~~~
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+#                                          ╙───────── 0x57565554 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ╙───────── 0x6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
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+#                                          ╙───────── 0x5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x5251504f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x56555453 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x8281807f <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x7a797877 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7e7d7c7b <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x7271706f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x85848382 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x79787776 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7d7c7b7a <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x71706f6e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x75747372 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x91908f8e <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x89888786 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8d8c8b8a <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x94939291 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x98979695 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x97969594 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9b9a9998 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x1918 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
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+#                                      ║   ║   ║   ╙─ 0xb5b4 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ╙───────────── 0xbbba <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xadac <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xafae <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xa5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa7a6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa9a8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xabaa <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9f9e <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa1a0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa3a2 <- 0x~~~~~~~~~~~~~~~~
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+#             d4:                 0xbab9b8b7b6b5b4b3 (-0.8403, -0.5894, -0.4192, -0.2937)
+#                                      ║   ║   ║   ╙─ 0xb4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb6b5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb8b7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbab9 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xacab <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xaead <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb0af <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb2b1 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xa4a3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa8a7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xaaa9 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x9c9b <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa09f <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa2a1 <- 0x~~~~~~~~~~~~~~~~
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+#             d0:                 0x1700000000000000 (0.001709, 0.000, 0.000, 0.000)
+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xcccb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcecd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd0cf <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xc4c3 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0xc8c7 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xbcbb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbebd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc0bf <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc2c1 <- 0x~~~~~~~~~~~~~~~~
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+#             d5:                 0xd1d0cfcecdcccbca (-46.50, -31.22, -23.19, -15.58)
+#                                      ║   ║   ║   ╙─ 0xcbca <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcdcc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xcfce <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xc9c8c7c6c5c4c3c2 (-11.56, -7.773, -5.766, -3.879)
+#                                      ║   ║   ║   ╙─ 0xc3c2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xc5c4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc7c6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc9c8 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xc1c0bfbebdbcbbba (-2.875, -1.936, -1.434, -0.9658)
+#                                      ║   ║   ║   ╙─ 0xbbba <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbdbc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xbfbe <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc1c0 <- 0x~~~~~~~~~~~~~~~~
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+#             d4:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xe1e0dfdedddcdbda (-752.0, -503.5, -375.0, -251.2)
+#                                      ║   ║   ║   ╙─ 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xd9d8d7d6d5d4d3d2 (-187.0, -125.4, -93.25, -62.56)
+#                                      ║   ║   ║   ╙─ 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d24:                 0xe0dfdedddcdbdad9 (-623.5, -439.2, -310.8, -219.1)
+#                                      ║   ║   ║   ╙─ 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xd8d7d6d5d4d3d2d1 (-154.9, -109.3, -77.19, -54.53)
+#                                      ║   ║   ║   ╙─ 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe8e7e6e5e4e3e2e1 (-2510., -1765., -1251., -880.5)
+#                                      ║   ║   ║   ╙─ 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d14:                 0xe7e6e5e4e3e2e1e0 (-2022., -1508., -1009., -752.0)
+#                                      ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x3f3e3d3c3b3a39383736353433323130 (0.7431, 0.002842, 1.086e-05, 4.149e-08)
+#                          ║       ║       ║       ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            v31: 0x27262524232221201f1e1d1c1b1a1918 (2.306e-15, 8.789e-18, 3.348e-20, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x17161514131211100f0e0d0c0b0a0908 (4.849e-25, 1.844e-27, 7.004e-30, 2.658e-32)
+#                          ║       ║       ║       ╙─ 0x0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x17161514 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.008e-34, 3.820e-37, nan, -2.606e+36)
+#                          ║       ║       ║       ╙─ 0xfbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.002e+34, -3.850e+31, -1.479e+29, -5.680e+26)
+#                          ║       ║       ║       ╙─ 0xebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xefeeedec <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf7f6f5f4 <- 0x~~~~~~~~~~~~~~~~
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+#            d14:                 0xb9b8b7b6b5b4b3b2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xb3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xb4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xb5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xb6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0xb1b0afaeadacabaa
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xaa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xab <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xac <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xad <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xae <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xaf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb1 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xa9a8a7a6a5a4a3a2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xa4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xa5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xc9c8c7c6c5c4c3c2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xc1c0bfbebdbcbbba
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xc8c7c6c5c4c3c2c1
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xc0bfbebdbcbbbab9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d31:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xd0cfcecdcccbcac9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xcfcecdcccbcac9c8
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x3f3e3d3c3b3a39383736353433323130 (1.811, 1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0f0e0d0c0b0a09080706050403020100 (0.0004306, 0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 (nan, nan, -6.534e+04, -4.890e+04, -3.261e+04, -2.438e+04, -1.627e+04, -1.216e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf1f0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf3f2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf5f4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf7f6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfbfa <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfdfc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 (-8120., -6064., -4052., -3024., -2022., -1508., -1009., -752.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe9e8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xebea <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xedec <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xefee <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 (-503.5, -375.0, -251.2, -187.0, -125.4, -93.25, -62.56, -46.50)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b0a09080706050403020100ff (0.0003693, 0.0002468, 0.0001842, 0.0001229, 9.185e-05, 6.121e-05, 3.058e-05, 1.520e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0201 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0605 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0807 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0a09 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0c0b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0e0d <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef (nan, nan, -5.712e+04, -4.067e+04, -2.850e+04, -2.027e+04, -1.422e+04, -1.010e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf0ef <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf2f1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf4f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf6f5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf8f7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfcfb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfefd <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df (-7092., -5036., -3538., -2510., -1765., -1251., -880.5, -623.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xeae9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xeceb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xeeed <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf (-439.2, -310.8, -219.1, -154.9, -109.3, -77.19, -54.53, -38.47)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3e3d3c3b3a393837363534333231302f (1.560, 1.058, 0.7778, 0.5269, 0.3879, 0.2625, 0.1935, 0.1307)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x302f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3433 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3635 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3837 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3c3b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2e2d2c2b2a292827262524232221201f (0.09650, 0.06512, 0.04813, 0.03244, 0.02400, 0.01616, 0.01197, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2e2d <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1e1d1c1b1a191817161514131211100f (0.005970, 0.004009, 0.002977, 0.001997, 0.001485, 0.0009947, 0.0007405, 0.0004954)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x100f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1211 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1413 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1615 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1e1d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a393837363534333231302f2e (1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x5d5c5b5a595857565554535251504f4e (343.0, 235.2, 171.0, 117.4, 85.25, 58.56, 42.50, 29.22)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4f4e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5150 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5554 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5958 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5b5a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857565554535251504f4e4d (278.8, 203.1, 138.9, 101.3, 69.19, 50.53, 34.47, 25.20)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4e4d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x504f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5251 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5453 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5857 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5a59 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5c5b <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x4c4b4a494847464544434241403f3e3d (17.17, 12.57, 8.555, 6.270, 4.262, 3.127, 2.123, 1.560)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x403f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4443 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4645 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4c4b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v9: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a696867666564636261605f5e5d (4524., 3282., 2254., 1637., 1123., 816.5, 559.5, 407.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5e5d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6463 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6665 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6a69 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6c6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x6b6a696867666564636261605f5e5d5c (3796., 2768., 1894., 1380., 945.0, 688.0, 471.5, 343.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6766 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6b6a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a39383736353433323130012e
+#                                                ╙─── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef
+#                                            ╙─────── 0x6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a6b6867666564636261605f5e5d
+#                          ╙───────────────────────── 0x6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.487e+303, ...)
+#                                  ╙───────────────── 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x737271706f6e6d6c636261605f5e5d5c (1.290e+248, ...)
+#                                  ╙───────────────── 0x737271706f6e6d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x7271706f6e6d6c6b2726252423222120 (1.861e+243, ...)
+#                                  ╙───────────────── 0x7271706f6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3aff013736353433323130012e (..., nan, ...)
+#                              ╙───────────────────── 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d37473d0cf (..., 1.822e+04, ...)
+#                                              ╙───── 0x7473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857737254535251504f4e4d (..., 1.525e+04, ...)
+#                                  ╙───────────────── 0x7372 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.751e-40, ...)
+#                                  ╙───────────────── 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.999e+33, ...)
+#                                  ╙───────────────── 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.245e+33, ...)
+#                                  ╙───────────────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x01010101010101010101010101010101
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x77777777777777777777777777777777
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x77 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x76767676767676767676767676767676
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x76 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7e7d7c7b7a797877 (1.975e+301)
+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x7d7c7b7a79787776 (2.911e+296)
+#                                                  ╙─ 0x7d7c7b7a79787776 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#                                  ╙───────────────╨─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8584838281807f7e8584838281807f7e (-4.414e-282, -4.414e-282)
+#                                  ╙───────────────╨─ 0x8584838281807f7e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84838281807f7e7d84838281807f7e7d (-6.406e-287, -6.406e-287)
+#                                  ╙───────────────╨─ 0x84838281807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#                                          ╙───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x8887868588878685 (-8.157e-34, -8.157e-34)
+#                                          ╙───────╨─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x8786858487868584 (-2.024e-34, -2.024e-34)
+#                                          ╙───────╨─ 0x87868584 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8988898889888988 (-0.0001688, -0.0001688, -0.0001688, -0.0001688)
+#                                      ╙───╨───╨───╨─ 0x8988 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x8887888788878887 (-0.0001382, -0.0001382, -0.0001382, -0.0001382)
+#                                      ╙───╨───╨───╨─ 0x8887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#                          ╙───────╨───────╨───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (-2.150e-31, -2.150e-31, -2.150e-31, -2.150e-31)
+#                          ╙───────╨───────╨───────╨─ 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0x8b8a89888b8a89888b8a89888b8a8988 (-5.336e-32, -5.336e-32, -5.336e-32, -5.336e-32)
+#                          ╙───────╨───────╨───────╨─ 0x8b8a8988 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x8c8c8c8c8c8c8c8c
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x8b8b8b8b8b8b8b8b
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c (-0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8d8c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b (-0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8c8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1e1c1a18000000000000ffff00850201
+#            v22: 0x1f1d1b1917000000000000feff0000ff
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x17'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1b'1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f'1e <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#            v22: 0xacaaa8a6a4a2a09e9c9a98969492908e
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x92'91 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x98'97 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa4'a3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaa'a9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xac'ab <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c
+#            v13: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x8f'8e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x95'94 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa1'a0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa7'a6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xa9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xab'aa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0x1700000000000000ff0000850002ff01 (6.689e-198, -5.487e+303)
+#            v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.568e-159, 8.289e-317)
+#                                  ║               ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.703e+18, -1.163e-59)
+#             v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.314e+57, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4'b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcbcac9c8c7c6c5c4'c3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.904e+13, -1.680e-64)
+#            v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.929e+52, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3'b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00fffeff0002ff01 (2.351e-38, 2.751e-40)
+#            d28:                 0x00000000ff000085 (0.000, -1.701e+38)
+#                                          ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xd6d5d4d3cecdcccb (-1.176e+14, -1.726e+09)
+#             d3:                 0xdad9d8d7d2d1d0cf (-3.066e+16, -4.506e+11)
+#                                          ║       ╙─ 0xd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xdad9d8d7'd6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xd5d4d3d2cdcccbca (-2.925e+13, -4.295e+08)
+#            d13:                 0xd9d8d7d6d1d0cfce (-7.629e+15, -1.121e+11)
+#                                          ║       ╙─ 0xd1d0cfce'cdcccbca <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x0000feff0085ff01 (0.000, nan, 7.927e-06, nan)
+#            d10:                 0x000000ffff000002 (0.000, 1.520e-05, nan, 1.192e-07)
+#                                      ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe7e6e3e2dfdedbda (-2022., -1009., -503.5, -251.2)
+#            d24:                 0xe9e8e5e4e1e0dddc (-3024., -1508., -752.0, -375.0)
+#                                      ║   ║   ║   ╙─ 0xdddc'dbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe1e0'dfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe9e8'e7e6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe6e5e2e1dedddad9 (-1765., -880.5, -439.2, -219.1)
+#             d2:                 0xe8e7e4e3e0dfdcdb (-2510., -1251., -623.5, -310.8)
+#                                      ║   ║   ║   ╙─ 0xdcdb'dad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe0df'dedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7'e6e5 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x1b1a19180000000000fffeff0002ff01 (1.275e-22, 0.000, 2.351e-38, 2.751e-40)
+#            v21: 0x1f1e1d1c1700000000000000ff000085 (3.348e-20, 4.136e-25, 0.000, -1.701e+38)
+#                          ║       ║       ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.540e-36, -1.047e+37, -1.546e+32, -2.282e+27)
+#            v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.063e-34, 2.351e-38, -4.023e+34, -5.940e+29)
+#                          ║       ║       ║       ╙─ 0xf0efeeed'ecebeae9 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf8f7f6f5'f4f3f2f1 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffefd'fcfbfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x08070605'04030201 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.820e-37, -2.606e+36, -3.850e+31, -5.680e+26)
+#            v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.008e-34, nan, -1.002e+34, -1.479e+29)
+#                          ║       ║       ║       ╙─ 0xefeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf7f6f5f4'f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xfffefdfc'fbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504'03020100 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000ffff00850201
+#            d18:                 0x000000feff0000ff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x161412100e0c0a08
+#            d14:                 0x171513110f0d0b09
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x09'08 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x11'10 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'16 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1513110f0d0b0907
+#             d8:                 0x161412100e0c0a08
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0a'09 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0e'0d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x16'15 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c1918000000000000feff0085ff01 (0.004990, 0.002487, 0.000, 0.000, 0.000, nan, 7.927e-06, nan)
+#            v31: 0x1f1e1b1a17000000000000ffff000002 (0.006950, 0.003468, 0.001709, 0.000, 0.000, 1.520e-05, nan, 1.192e-07)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1700'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x3433302f2c2b28272423201f1c1b1817 (0.2625, 0.1307, 0.06512, 0.03244, 0.01616, 0.008049, 0.004009, 0.001997)
+#             v5: 0x363532312e2d2a29262522211e1d1a19 (0.3879, 0.1935, 0.09650, 0.04813, 0.02400, 0.01197, 0.005970, 0.002977)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1a19'1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1e1d'1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2221'201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625'2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2a29'2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2e2d'2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3231'302f <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3635'3433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x33322f2e2b2a272623221f1e1b1a1716 (0.2249, 0.1122, 0.05597, 0.02792, 0.01393, 0.006950, 0.003468, 0.001730)
+#            v14: 0x353431302d2c2928252421201d1c1918 (0.3252, 0.1621, 0.08081, 0.04028, 0.02008, 0.01001, 0.004990, 0.002487)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928'2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x363532012e2d2a29262522211e1d1a19
+#             v6: 0x1f1e1dff1b1a19181700000000000000
+#                          ╙───────────────────────── 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x4544434241403f3e363c3b3a39383736
+#            v17: 0x00000000000000003700ffff00850201
+#                                    ╙─────────────── 0x37'36 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfb35f9f8
+#            v30: 0x1d1c1918000000000000feff0036ff01
+#                                              ╙───── 0x36'35 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.487e+303, ...)
+#            v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.289e-317, ...)
+#                                  ╙───────────────── 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x00000000000000003e3d3c3b3a393837 (..., 6.807e-09)
+#            v27: 0x0000000000000000464544434241403f (..., 3.370e+30)
+#                                                  ╙─ 0x464544434241403f'3e3d3c3b3a393837 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x07060504fffefdfc3d3c3b3a39383736 (..., 1.003e-13)
+#            v26: 0x00000000000000004544434241403f3e (..., 4.899e+25)
+#                                                  ╙─ 0x4544434241403f3e'3d3c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0xff01000000000000000000feff0000ff (nan, ...)
+#            v19: 0x00020000000000008b8b8b8b8b8b8b8b (1.192e-07, ...)
+#                      ╙───────────────────────────── 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x00000000474600003700ffff00850201 (..., 7.273, ...)
+#            v18: 0xff01000049480000000000feff0000ff (..., 10.56, ...)
+#                              ╙───────────────────── 0x4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c191800000000000046450036ff01 (..., 6.270, ...)
+#            v31: 0x1f1e1b1a1700000000004847ff000002 (..., 8.555, ...)
+#                                          ╙───────── 0x4847'4645 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.751e-40, ...)
+#            v30: 0xff00008500000000000046450036ff01 (-1.701e+38, ...)
+#                          ╙───────────────────────── 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000000000000000004c4b4a49 (..., 5.329e+07)
+#            v29: 0x0002ff0103020100fffefdfc504f4e4d (..., 1.391e+10)
+#                                                  ╙─ 0x504f4e4d'4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.326e+07, ...)
+#             v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.461e+09, ...)
+#                                          ╙───────── 0x4f4e4d4c'4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x01010101010101010101010101010101
+#            v27: 0xffffffffffffffffffffffffffffffff
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x50505050505050505050505050505050
+#            v22: 0x51515151515151515151515151515151
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x51'50 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f
+#             v6: 0x50505050505050505050505050505050
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x50'4f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-5.487e+303)
+#            d27:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x5857565554535251 (3.678e+117)
+#            d15:                 0x605f5e5d5c5b5a59 (1.682e+156)
+#                                                  ╙─ 0x605f5e5d5c5b5a59'5857565554535251 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x5756555453525150 (5.371e+112)
+#            d24:                 0x5f5e5d5c5b5a5958 (2.485e+151)
+#                                                  ╙─ 0x5f5e5d5c5b5a5958'5756555453525150 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v12: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#                                  ╙───────────────╨─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x67666564636261606766656463626160 (1.247e+190, 1.247e+190)
+#            v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.766e+228, 5.766e+228)
+#                                  ╙───────────────╨─ 0x6f6e6d6c6b6a6968'6766656463626160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x666564636261605f666564636261605f (1.818e+185, 1.818e+185)
+#            v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.509e+223, 8.509e+223)
+#                                  ╙───────────────╨─ 0x6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d27:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#                                          ╙───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x7271706f7271706f (4.782e+30, 4.782e+30)
+#            d23:                 0x7675747376757473 (1.245e+33, 1.245e+33)
+#                                          ╙───────╨─ 0x76757473'7271706f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x71706f6e71706f6e (1.191e+30, 1.191e+30)
+#             d3:                 0x7574737275747372 (3.099e+32, 3.099e+32)
+#                                          ╙───────╨─ 0x75747372'71706f6e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#             d3:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                                      ╙───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7776777677767776 (3.056e+04, 3.056e+04, 3.056e+04, 3.056e+04)
+#            d10:                 0x7978797879787978 (4.480e+04, 4.480e+04, 4.480e+04, 4.480e+04)
+#                                      ╙───╨───╨───╨─ 0x7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x7675767576757675 (2.645e+04, 2.645e+04, 2.645e+04, 2.645e+04)
+#             d7:                 0x7877787778777877 (3.658e+04, 3.658e+04, 3.658e+04, 3.658e+04)
+#                                      ╙───╨───╨───╨─ 0x7877'7675 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#             v8: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#                          ╙───────╨───────╨───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (5.223e+36, 5.223e+36, 5.223e+36, 5.223e+36)
+#            v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (-1.171e-38, -1.171e-38, -1.171e-38, -1.171e-38)
+#                          ╙───────╨───────╨───────╨─ 0x807f7e7d'7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x7b7a79787b7a79787b7a79787b7a7978 (1.301e+36, 1.301e+36, 1.301e+36, 1.301e+36)
+#            v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (3.383e+38, 3.383e+38, 3.383e+38, 3.383e+38)
+#                          ╙───────╨───────╨───────╨─ 0x7f7e7d7c'7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#            d27:                 0xffffffffffffffff
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x8080808080808080
+#            d21:                 0x8181818181818181
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x81'80 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x7f7f7f7f7f7f7f7f
+#            d12:                 0x8080808080808080
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x80'7f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v13: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x82818281828182818281828182818281 (-3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05)
+#             v7: 0x84838483848384838483848384838483 (-6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8483'8281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x81808180818081808180818081808180 (-2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05)
+#            v26: 0x83828382838283828382838283828382 (-5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2d2a2724211e1b1800000000fe000001
+#            v21: 0x2e2b2825221f1c1900000000ffff85ff
+#            v22: 0x2f2c292623201d1a1700000000ff0002
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x20'1f'1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x23'22'21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2c'2b'2a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f'2e'2d <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v29: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#            v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x89'88'87 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8c'8b'8a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8f'8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x95'94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x98'97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa1'a0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa4'a3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa7'a6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xaa'a9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xad'ac'ab <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb3'b2'b1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0xb0adaaa7a4a19e9b9895928f8c898683
+#            v21: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v22: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x85'84'83 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x88'87'86 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8b'8a'89 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8e'8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x91'90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x94'93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x97'96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9a'99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa3'a2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa6'a5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa9'a8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xac'ab'aa <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb2'b1'b0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.568e-159, -5.487e+303)
+#            v22: 0x27262524232221200000000000fffeff (4.288e-120, 8.289e-317)
+#            v23: 0x2f2e2d2c2b2a29281700000000000000 (1.988e-81, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928'2726252423222120'1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.073e+90, -8.311e-26)
+#            v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.479e+129, -3.904e+13)
+#            v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.109e+168, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb'dad9d8d7d6d5d4d3'd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.306e+86, -1.219e-30)
+#            v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.569e+124, -5.620e+08)
+#            v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.037e+163, -2.829e+47)
+#                                  ║               ╙─ 0xc9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe1e0dfdedddcdbda'd9d8d7d6d5d4d3d2'd1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x000000000002ff01 (0.000, 2.751e-40)
+#             d8:                 0x00000000ff000085 (0.000, -1.701e+38)
+#             d9:                 0x1700000000fffeff (4.136e-25, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xf1f0efeee5e4e3e2 (-2.386e+30, -1.351e+23)
+#            d21:                 0xf5f4f3f2e9e8e7e6 (-6.210e+32, -3.520e+25)
+#            d22:                 0xf9f8f7f6edecebea (-1.616e+35, -9.165e+27)
+#                                          ║       ╙─ 0xedecebea'e9e8e7e6'e5e4e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xf0efeeede4e3e2e1 (-5.940e+29, -3.363e+22)
+#            d27:                 0xf4f3f2f1e8e7e6e5 (-1.546e+32, -8.761e+24)
+#            d28:                 0xf8f7f6f5ecebeae9 (-4.023e+34, -2.282e+27)
+#                                          ║       ╙─ 0xecebeae9'e8e7e6e5'e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00000000ff00ff01 (0.000, 0.000, nan, nan)
+#            d28:                 0x00000000feff0002 (0.000, 0.000, nan, 1.192e-07)
+#            d29:                 0x1700000000ff0085 (0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                                      ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x0c0b060500fffaf9 (0.0002468, 9.185e-05, 1.520e-05, -5.712e+04)
+#            d29:                 0x0e0d08070201fcfb (0.0003693, 0.0001229, 3.058e-05, nan)
+#            d30:                 0x100f0a090403fefd (0.0004954, 0.0001842, 6.121e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0403'0201'00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0a09'0807'0605 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x100f'0e0d'0c0b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x0b0a0504fffef9f8 (0.0002148, 7.653e-05, nan, -4.890e+04)
+#             d8:                 0x0d0c07060100fbfa (0.0003080, 0.0001072, 1.526e-05, -6.534e+04)
+#             d9:                 0x0f0e09080302fdfc (0.0004306, 0.0001535, 4.590e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfdfc'fbfa'f9f8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0302'0100'fffe <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0908'0706'0504 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0f0e'0d0c'0b0a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x272625241b1a1918000000000002ff01 (2.306e-15, 1.275e-22, 0.000, 2.751e-40)
+#             v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.045e-13, 3.348e-20, 0.000, -1.701e+38)
+#             v4: 0x2f2e2d2c232221201700000000fffeff (1.584e-10, 8.789e-18, 4.136e-25, 2.351e-38)
+#                          ║       ║       ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120'1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c'2b2a2928'27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x373635342b2a29281f1e1d1c13121110 (1.086e-05, 6.045e-13, 3.348e-20, 1.844e-27)
+#            v25: 0x3b3a39382f2e2d2c2322212017161514 (0.002842, 1.584e-10, 8.789e-18, 4.849e-25)
+#            v26: 0x3f3e3d3c33323130272625241b1a1918 (0.7431, 4.149e-08, 2.306e-15, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918'17161514'13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x33323130'2f2e2d2c'2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0x363534332a2928271e1d1c1b1211100f (2.700e-06, 1.502e-13, 8.317e-21, 4.577e-28)
+#            v12: 0x3a3938372e2d2c2b2221201f16151413 (0.0007066, 3.937e-11, 2.184e-18, 1.204e-25)
+#            v13: 0x3e3d3c3b3231302f262524231a191817 (0.1848, 1.031e-08, 5.729e-16, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817'16151413'1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x26252423'2221201f'1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3231302f'2e2d2c2b'2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3e3d3c3b'3a393837'36353433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x00000000fe000001
+#            d30:                 0x00000000ffff85ff
+#            d31:                 0x1700000000ff0002
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x54514e4b4845423f
+#             d2:                 0x55524f4c49464340
+#             d3:                 0x5653504d4a474441
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x41'40'3f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x44'43'42 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x47'46'45 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x4a'49'48 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4d'4c'4b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x50'4f'4e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x53'52'51 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x56'55'54 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x53504d4a4744413e
+#            d13:                 0x54514e4b4845423f
+#            d14:                 0x55524f4c49464340
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40'3f'3e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x43'42'41 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x46'45'44 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x49'48'47 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4c'4b'4a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x4f'4e'4d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x52'51'50 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x55'54'53 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x2b2a25241f1e191800000000ff00ff01 (0.05597, 0.02008, 0.006950, 0.002487, 0.000, 0.000, nan, nan)
+#            v23: 0x2d2c272621201b1a00000000feff0002 (0.08081, 0.02792, 0.01001, 0.003468, 0.000, 0.000, nan, 1.192e-07)
+#            v24: 0x2f2e292823221d1c1700000000ff0085 (0.1122, 0.04028, 0.01393, 0.004990, 0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2322'2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2928'2726'2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e696863625d5c5756 (-2.289e-05, 6.125e+04, 2.234e+04, 7608., 2768., 945.0, 343.0, 117.4)
+#            v14: 0x83827d7c777671706b6a65645f5e5958 (-5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5, 171.0)
+#            v15: 0x85847f7e797873726d6c676661605b5a (-8.416e-05, nan, 4.480e+04, 1.525e+04, 5552., 1894., 688.0, 235.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5b5a'5958'5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6160'5f5e'5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6766'6564'6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6d6c'6b6a'6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7372'7170'6f6e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7978'7776'7574 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8584'8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x807f7a7974736e6d686762615c5b5655 (-7.570e-06, 5.302e+04, 1.822e+04, 6580., 2254., 816.5, 278.8, 101.3)
+#            v29: 0x82817c7b7675706f6a6964635e5d5857 (-3.821e-05, nan, 2.645e+04, 9080., 3282., 1123., 407.2, 138.9)
+#            v30: 0x84837e7d787772716c6b6665605f5a59 (-6.884e-05, nan, 3.658e+04, 1.319e+04, 4524., 1637., 559.5, 203.1)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5a59'5857'5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f'5e5d'5c5b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6665'6463'6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6c6b'6a69'6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7271'706f'6e6d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7877'7675'7473 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7e7d'7c7b'7a79 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8483'8281'807f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x0000000001000000f5f4f3f2e9e8e7e6
+#            v22: 0x2b2a2524ff1e191800000000ff00ff01
+#            v23: 0x2d2c272602201b1a00000000feff0002
+#                            ╙─────────────────────── 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f
+#             v6: 0x82818281828186818281828182818281
+#             v7: 0x00000000000087000b0a0504fffef9f8
+#                                ╙─────────────────── 0x87'86'85 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0x2d2c272602201b1a00000000feff0084
+#            v24: 0x2f2e292823221d1c1700000000ff0085
+#            v25: 0x3b3a39382f2e2d2c2322212017161586
+#                                                  ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6e6d6c6b6a696867ff0000850002ff01 (..., -5.487e+303)
+#            v17: 0x00000000474600000000000000fffeff (..., 8.289e-317)
+#            v18: 0xd2d1d0cfcecdcccb1700000000000000 (..., 6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84837e7d787772718e8d8c8b8a898887 (..., -1.418e-238)
+#            v31: 0x0000000000000000969594939291908f (..., -7.048e-200)
+#             v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (..., -3.291e-161)
+#                                                  ╙─ 0x9e9d9c9b9a999897'969594939291908f'8e8d8c8b8a898887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.090e-243, ...)
+#            v29: 0x9594939291908f8e6a6964635e5d5857 (-1.025e-204, ...)
+#            v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.851e-166, ...)
+#                                  ╙───────────────── 0x9d9c9b9a99989796'9594939291908f8e'8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e6968ff015d5c5756 (..., nan, ...)
+#            v14: 0x83827d7c777671706b6a00025f5e5958 (..., 1.192e-07, ...)
+#            v15: 0x85847f7e797873726d6c008561605b5a (..., 7.927e-06, ...)
+#                                          ╙───────── 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x9f9e2524ff1e191800000000ff00ff01 (-0.007439, ...)
+#            v23: 0xa1a0272602201b1a00000000feff0084 (-0.01099, ...)
+#            v24: 0xa3a2292823221d1c1700000000ff0085 (-0.01491, ...)
+#                      ╙───────────────────────────── 0xa3a2'a1a0'9f9e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0x83827d7c777671709e9d00025f5e5958 (..., -0.006458, ...)
+#            v15: 0x85847f7e79787372a09f008561605b5a (..., -0.009026, ...)
+#            v16: 0x6e6d6c6b6a696867a2a100850002ff01 (..., -0.01295, ...)
+#                                      ╙───────────── 0xa2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x0002ff01ff1e191800000000ff00ff01 (2.751e-40, ...)
+#            v23: 0xff00008502201b1a00000000feff0084 (-1.701e+38, ...)
+#            v24: 0x00fffeff23221d1c1700000000ff0085 (2.351e-38, ...)
+#                          ╙───────────────────────── 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.149e-15, ...)
+#            v31: 0x00000000aaa9a8a7969594939291908f (..., -3.014e-13, ...)
+#             v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.898e-11, ...)
+#                                  ╙───────────────── 0xaeadacab'aaa9a8a7'a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000a5a4a3a24744413e (..., -2.856e-16, ...)
+#            v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.490e-14, ...)
+#            v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.963e-11, ...)
+#                                          ╙───────── 0xadacabaa'a9a8a7a6'a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x01010101010101010101010101010101
+#            v25: 0xffffffffffffffffffffffffffffffff
+#            v26: 0x02020202020202020202020202020202
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#            v25: 0xafafafafafafafafafafafafafafafaf
+#            v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v3: 0xadadadadadadadadadadadadadadadad
+#             v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#             v5: 0xafafafafafafafafafafafafafafafaf
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01 (-5.487e+303)
+#             d5:                 0x0000000000fffeff (8.289e-317)
+#             d6:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xb7b6b5b4b3b2b1b0 (-2.607e-40)
+#             d8:                 0xbfbebdbcbbbab9b8 (-0.1201)
+#             d9:                 0xc7c6c5c4c3c2c1c0 (-6.054e+37)
+#                                                  ╙─ 0xc7c6c5c4c3c2c1c0'bfbebdbcbbbab9b8'b7b6b5b4b3b2b1b0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xb6b5b4b3b2b1b0af (-3.802e-45)
+#            d18:                 0xbebdbcbbbab9b8b7 (-1.772e-06)
+#            d19:                 0xc6c5c4c3c2c1c0bf (-8.830e+32)
+#                                                  ╙─ 0xc6c5c4c3c2c1c0bf'bebdbcbbbab9b8b7'b6b5b4b3b2b1b0af <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v17: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v18: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#                                  ╙───────────────╨─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.113e+71, -4.113e+71)
+#            v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.051e+110, -2.051e+110)
+#            v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.546e+148, -9.546e+148)
+#                                  ╙───────────────╨─ 0xdedddcdbdad9d8d7'd6d5d4d3d2d1d0cf'cecdcccbcac9c8c7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.065e+66, -6.065e+66)
+#            v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.985e+105, -2.985e+105)
+#            v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.408e+144, -1.408e+144)
+#                                  ╙───────────────╨─ 0xdddcdbdad9d8d7d6'd5d4d3d2d1d0cfce'cdcccbcac9c8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d11:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#            d12:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#                                          ╙───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#             d1:                 0xe5e4e3e2e5e4e3e2 (-1.351e+23, -1.351e+23)
+#             d2:                 0xe9e8e7e6e9e8e7e6 (-3.520e+25, -3.520e+25)
+#                                          ╙───────╨─ 0xe9e8e7e6'e5e4e3e2'e1e0dfde <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#            d24:                 0xe4e3e2e1e4e3e2e1 (-3.363e+22, -3.363e+22)
+#            d25:                 0xe8e7e6e5e8e7e6e5 (-8.761e+24, -8.761e+24)
+#                                          ╙───────╨─ 0xe8e7e6e5'e4e3e2e1'e0dfdedd <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d23:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d24:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                                      ╙───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0xeae9eae9eae9eae9 (-3538., -3538., -3538., -3538.)
+#             d7:                 0xecebecebecebeceb (-5036., -5036., -5036., -5036.)
+#             d8:                 0xeeedeeedeeedeeed (-7092., -7092., -7092., -7092.)
+#                                      ╙───╨───╨───╨─ 0xeeed'eceb'eae9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xe9e8e9e8e9e8e9e8 (-3024., -3024., -3024., -3024.)
+#             d8:                 0xebeaebeaebeaebea (-4052., -4052., -4052., -4052.)
+#             d9:                 0xedecedecedecedec (-6064., -6064., -6064., -6064.)
+#                                      ╙───╨───╨───╨─ 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v27: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v28: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#                          ╙───────╨───────╨───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (-2.386e+30, -2.386e+30, -2.386e+30, -2.386e+30)
+#             v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (-6.210e+32, -6.210e+32, -6.210e+32, -6.210e+32)
+#             v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (-1.616e+35, -1.616e+35, -1.616e+35, -1.616e+35)
+#                          ╙───────╨───────╨───────╨─ 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (-5.940e+29, -5.940e+29, -5.940e+29, -5.940e+29)
+#            v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (-1.546e+32, -1.546e+32, -1.546e+32, -1.546e+32)
+#             v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (-4.023e+34, -4.023e+34, -4.023e+34, -4.023e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x0101010101010101
+#             d3:                 0xffffffffffffffff
+#             d4:                 0x0202020202020202
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xf9f9f9f9f9f9f9f9
+#            d11:                 0xfafafafafafafafa
+#            d12:                 0xfbfbfbfbfbfbfbfb
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfb'fa'f9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v7: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#             v8: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#             v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v9: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xfffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v3: 0x3c3834302c2824201c18000000ff8501
+#             v4: 0x3d3935312d2925211d19000000fe00ff
+#             v5: 0x3e3a36322e2a26221e1a000000ff0002
+#             v6: 0x3f3b37332f2b27231f1b17000000ff00
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x3c3834302c2824201c1814100c080400
+#             v3: 0x3d3935312d2925211d1915110d090501
+#             v4: 0x3e3a36322e2a26221e1a16120e0a0602
+#             v5: 0x3f3b37332f2b27231f1b17130f0b0703
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x03'02'01'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x07'06'05'04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0b'0a'09'08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0f'0e'0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x13'12'11'10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'16'15'14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3b37332f2b27231f1b17130f0b0703ff
+#             v6: 0x3c3834302c2824201c1814100c080400
+#             v7: 0x3d3935312d2925211d1915110d090501
+#             v8: 0x3e3a36322e2a26221e1a16120e0a0602
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1e'1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22'21'20'1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x26'25'24'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a'29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2e'2d'2c'2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x32'31'30'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x36'35'34'33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3a'39'38'37 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3e'3d'3c'3b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2726252423222120ff0000850002ff01 (4.288e-120, -5.487e+303)
+#            v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.988e-81, 8.289e-317)
+#            v20: 0x37363534333231301700000000000000 (9.958e-43, 6.689e-198)
+#            v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.0004614, 8.568e-159)
+#                                  ║               ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938'3736353433323130'2f2e2d2c2b2a2928'2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x666564636261605f464544434241403f (1.818e+185, 3.370e+30)
+#             v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.509e+223, 1.580e+69)
+#             v6: 0x767574737271706f565554535251504f (4.222e+262, 7.827e+107)
+#             v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.975e+301, 3.666e+146)
+#                                  ║               ╙─ 0x5e5d5c5b5a595857'565554535251504f'4e4d4c4b4a494847'464544434241403f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7e7d7c7b7a797877'767574737271706f'6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x6564636261605f5e4544434241403f3e (2.644e+180, 4.899e+25)
+#            v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.254e+219, 2.328e+64)
+#            v31: 0x7574737271706f6e5554535251504f4e (6.141e+257, 1.138e+103)
+#             v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.911e+296, 5.403e+141)
+#                                  ║               ╙─ 0x5d5c5b5a59585756'5554535251504f4e'4d4c4b4a49484746'4544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7d7c7b7a79787776'7574737271706f6e'6d6c6b6a69686766'6564636261605f5e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x000000000002ff01 (0.000, 2.751e-40)
+#            d28:                 0x17000000ff000085 (4.136e-25, -1.701e+38)
+#            d29:                 0x1b1a191800fffeff (1.275e-22, 2.351e-38)
+#            d30:                 0x1f1e1d1c00000000 (3.348e-20, 0.000)
+#                                          ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x91908f8e81807f7e (-2.281e-28, -4.720e-38)
+#            d25:                 0x9594939285848382 (-6.001e-26, -1.246e-35)
+#            d26:                 0x9998979689888786 (-1.578e-23, -3.287e-33)
+#            d27:                 0x9d9c9b9a8d8c8b8a (-4.145e-21, -8.662e-31)
+#                                          ║       ╙─ 0x8d8c8b8a'89888786'85848382'81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9d9c9b9a'99989796'95949392'91908f8e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x908f8e8d807f7e7d (-5.662e-29, -1.171e-38)
+#             d5:                 0x9493929184838281 (-1.490e-26, -3.092e-36)
+#             d6:                 0x9897969588878685 (-3.918e-24, -8.157e-34)
+#             d7:                 0x9c9b9a998c8b8a89 (-1.030e-21, -2.150e-31)
+#                                          ║       ╙─ 0x8c8b8a89'88878685'84838281'807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99'98979695'94939291'908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d16:                 0x19180000feffff01 (0.002487, 0.000, nan, nan)
+#            d17:                 0x1b1a000000ff0002 (0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            d18:                 0x1d1c000000000085 (0.004990, 0.000, 0.000, 7.927e-06)
+#            d19:                 0x1f1e17000000ff00 (0.006950, 0.001709, 0.000, nan)
+#                                      ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xb6b5aeada6a59e9d (-0.4192, -0.1043, -0.02596, -0.006458)
+#            d24:                 0xb8b7b0afa8a7a09f (-0.5894, -0.1464, -0.03635, -0.009026)
+#            d25:                 0xbab9b2b1aaa9a2a1 (-0.8403, -0.2091, -0.05203, -0.01295)
+#            d26:                 0xbcbbb4b3acaba4a3 (-1.183, -0.2937, -0.07294, -0.01811)
+#                                      ║   ║   ║   ╙─ 0xa4a3'a2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xacab'aaa9'a8a7'a6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb4b3'b2b1'b0af'aead <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbcbb'bab9'b8b7'b6b5 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xb5b4adaca5a49d9c (-0.3564, -0.08862, -0.02203, -0.005478)
+#             d3:                 0xb7b6afaea7a69f9e (-0.4819, -0.1200, -0.02988, -0.007439)
+#             d4:                 0xb9b8b1b0a9a8a1a0 (-0.7148, -0.1777, -0.04419, -0.01099)
+#             d5:                 0xbbbab3b2abaaa3a2 (-0.9658, -0.2405, -0.05988, -0.01491)
+#                                      ║   ║   ║   ╙─ 0xa3a2'a1a0'9f9e'9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xabaa'a9a8'a7a6'a5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb3b2'b1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba'b9b8'b7b6'b5b4 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x3332313023222120000000000002ff01 (4.149e-08, 8.789e-18, 0.000, 2.751e-40)
+#             v8: 0x373635342726252417000000ff000085 (1.086e-05, 2.306e-15, 4.136e-25, -1.701e+38)
+#             v9: 0x3b3a39382b2a29281b1a191800fffeff (0.002842, 6.045e-13, 1.275e-22, 2.351e-38)
+#            v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.7431, 1.584e-10, 3.348e-20, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2f2e2d2c'2b2a2928'27262524'23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534'33323130 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#            v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.850e+31, -8.370e+21, -1.811e+12, -389.5)
+#            v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.002e+34, -2.181e+24, -4.724e+14, -1.018e+05)
+#            v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.606e+36, -5.680e+26, -1.232e+17, -2.658e+07)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.682e+28, -7.993e+18, -1.726e+09, -0.3706)
+#            v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.584e+30, -2.083e+21, -4.506e+11, -96.88)
+#            v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.494e+33, -5.428e+23, -1.176e+14, -2.531e+04)
+#             v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.490e+35, -1.414e+26, -3.066e+16, -6.612e+06)
+#                          ║       ║       ║       ╙─ 0xcac9c8c7'c6c5c4c3'c2c1c0bf'bebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdad9d8d7'd6d5d4d3'd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xeae9e8e7'e6e5e4e3'e2e1e0df'dedddcdb <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfaf9f8f7'f6f5f4f3'f2f1f0ef'eeedeceb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d15:                 0x1c18000000ff8501
+#            d16:                 0x1d19000000fe00ff
+#            d17:                 0x1e1a000000ff0002
+#            d18:                 0x1f1b17000000ff00
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x17130f0b0703fffb
+#            d28:                 0x1814100c080400fc
+#            d29:                 0x1915110d090501fd
+#            d30:                 0x1a16120e0a0602fe
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfe'fd'fc'fb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x16120e0a0602fefa
+#             d6:                 0x17130f0b0703fffb
+#             d7:                 0x1814100c080400fc
+#             d8:                 0x1915110d090501fd
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfd'fc'fb'fa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x01'00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x05'04'03'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x09'08'07'06 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0d'0c'0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x11'10'0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14'13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x19'18'17'16 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831302928212019180000feffff01 (0.6523, 0.1621, 0.04028, 0.01001, 0.002487, 0.000, nan, nan)
+#            v26: 0x3b3a33322b2a23221b1a000000ff0002 (0.9033, 0.2249, 0.05597, 0.01393, 0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            v27: 0x3d3c35342d2c25241d1c000000000085 (1.309, 0.3252, 0.08081, 0.02008, 0.004990, 0.000, 0.000, 7.927e-06)
+#            v28: 0x3f3e37362f2e27261f1e17000000ff00 (1.811, 0.4507, 0.1122, 0.02792, 0.006950, 0.001709, 0.000, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726'2524'2322'2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2f2e'2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3736'3534'3332'3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e'3d3c'3b3a'3938 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x53524b4a43423b3a33322b2a23221b1a (58.56, 14.58, 3.629, 0.9033, 0.2249, 0.05597, 0.01393, 0.003468)
+#             v3: 0x55544d4c45443d3c35342d2c25241d1c (85.25, 21.19, 5.266, 1.309, 0.3252, 0.08081, 0.02008, 0.004990)
+#             v4: 0x57564f4e47463f3e37362f2e27261f1e (117.4, 29.22, 7.273, 1.811, 0.4507, 0.1122, 0.02792, 0.006950)
+#             v5: 0x59585150494841403938313029282120 (171.0, 42.50, 10.56, 2.625, 0.6523, 0.1621, 0.04028, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120'1f1e'1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2928'2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3130'2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3938'3736'3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4140'3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948'4746'4544'4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5150'4f4e'4d4c'4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5958'5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2922211a19 (50.53, 12.57, 3.127, 0.7778, 0.1935, 0.04813, 0.01197, 0.002977)
+#            v21: 0x54534c4b44433c3b34332c2b24231c1b (69.19, 17.17, 4.262, 1.058, 0.2625, 0.06512, 0.01616, 0.004009)
+#            v22: 0x56554e4d46453e3d36352e2d26251e1d (101.3, 25.20, 6.270, 1.560, 0.3879, 0.09650, 0.02400, 0.005970)
+#            v23: 0x5857504f4847403f3837302f2827201f (138.9, 34.47, 8.555, 2.123, 0.5269, 0.1307, 0.03244, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f'1e1d'1c1b'1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2827'2625'2423'2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x302f'2e2d'2c2b'2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3837'3635'3433'3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x403f'3e3d'3c3b'3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847'4645'4443'4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x504f'4e4d'4c4b'4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5857'5655'5453'5251 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2901211a19
+#            v21: 0x54534c4b44433c3b34332c2bff231c1b
+#            v22: 0x56554e4d46453e3d36352e2d02251e1d
+#            v23: 0x5857504f4847403f3837302f0027201f
+#                                            ╙─────── 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000fbfbfbfb59fbfbfb
+#            v13: 0x81807b7a75746f6ea9a8a7a65a5c5756
+#            v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6
+#            v15: 0x00000000000000001c1800005cff8501
+#                                            ╙─────── 0x5c'5b'5a'59 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x3d3c35342d2c25241d58000000000085
+#            v28: 0x3f3e37362f2e27261f5917000000ff00
+#            v29: 0x0000000000000000195a110d090501fd
+#            v30: 0x00000000000000001a5b120e0a0602fe
+#                                      ╙───────────── 0x5b'5a'59'58 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff0000850002ff011f5917000000ff00 (-5.487e+303, ...)
+#            v29: 0x0000000000fffeff195a110d090501fd (8.289e-317, ...)
+#            v30: 0x17000000000000001a5b120e0a0602fe (6.689e-198, ...)
+#            v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.568e-159, ...)
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x636261605f5e5d5c1c1800005cff8501 (5.549e+170, ...)
+#            v16: 0x6b6a6968676665641d19000000fe00ff (2.713e+209, ...)
+#            v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.290e+248, ...)
+#            v18: 0x7b7a7978777675741f1b17000000ff00 (6.299e+286, ...)
+#                                  ╙───────────────── 0x7b7a797877767574'737271706f6e6d6c'6b6a696867666564'636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.005e+165, ...)
+#            v17: 0x6a696867666564631e1a000000ff0002 (3.983e+204, ...)
+#            v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.861e+243, ...)
+#            v19: 0x7a797877767574731f1e17000000ff00 (9.247e+281, ...)
+#                                  ╙───────────────── 0x7a79787776757473'7271706f6e6d6c6b'6a69686766656463'6261605f5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x5352ff0143423b3a33322b2a23221b1a (..., nan, ...)
+#             v3: 0x5554000245443d3c35342d2c25241d1c (..., 1.192e-07, ...)
+#             v4: 0x5756008547463f3e37362f2e27261f1e (..., 7.927e-06, ...)
+#             v5: 0x5958ff00494841403938313029282120 (..., nan, ...)
+#                          ╙───────────────────────── 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5958ff00494841407c7b313029282120 (..., nan, ...)
+#             v6: 0x00000000000000007e7d0f0b0703fffb (..., nan, ...)
+#             v7: 0x0000000000000000807f100c080400fc (..., -7.570e-06, ...)
+#             v8: 0x00000000000000008281110d090501fd (..., -3.821e-05, ...)
+#                                      ╙───────────── 0x8281'807f'7e7d'7c7b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x00007b7a00000000807f100c080400fc (..., 6.125e+04, ...)
+#             v8: 0x00007d7c000000008281110d090501fd (..., nan, ...)
+#             v9: 0x3b3a7f7e2b2a29281b1a191800fffeff (..., nan, ...)
+#            v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 (..., -2.289e-05, ...)
+#                          ╙───────────────────────── 0x8180'7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x00000000000000000002ff010703fffb (..., 2.751e-40, ...)
+#             v7: 0x00007b7a00000000ff000085080400fc (..., -1.701e+38, ...)
+#             v8: 0x00007d7c0000000000fffeff090501fd (..., 2.351e-38, ...)
+#             v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.000, ...)
+#                                          ╙───────── 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831308584838219180000feffff01 (..., -1.246e-35, ...)
+#            v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.287e-33, ...)
+#            v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.662e-31, ...)
+#            v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.281e-28, ...)
+#                                  ╙───────────────── 0x91908f8e'8d8c8b8a'89888786'85848382 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x848382810000000000fffeff090501fd (-3.092e-36, ...)
+#             v9: 0x888786852b2a29280000000000fffeff (-8.157e-34, ...)
+#            v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.150e-31, ...)
+#            v11: 0x908f8e8d00000000fafafafafafafafa (-5.662e-29, ...)
+#                          ╙───────────────────────── 0x908f8e8d'8c8b8a89'88878685'84838281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0x01010101010101010101010101010101
+#            v15: 0xffffffffffffffffffffffffffffffff
+#            v16: 0x02020202020202020202020202020202
+#            v17: 0x00000000000000000000000000000000
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x91919191919191919191919191919191
+#            v14: 0x92929292929292929292929292929292
+#            v15: 0x93939393939393939393939393939393
+#            v16: 0x94949494949494949494949494949494
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x94'93'92'91 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v9: 0x90909090909090909090909090909090
+#            v10: 0x91919191919191919191919191919191
+#            v11: 0x92929292929292929292929292929292
+#            v12: 0x93939393939393939393939393939393
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x93'92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xff0000850002ff01 (-5.487e+303)
+#             d9:                 0x0000000000fffeff (8.289e-317)
+#            d10:                 0x1700000000000000 (6.689e-198)
+#            d11:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x9b9a999897969594 (-1.050e-175)
+#             d5:                 0xa3a2a1a09f9e9d9c (-5.007e-137)
+#             d6:                 0xabaaa9a8a7a6a5a4 (-2.438e-98)
+#             d7:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac'abaaa9a8a7a6a5a4'a3a2a1a09f9e9d9c'9b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x9a99989796959493 (-1.542e-180)
+#            d27:                 0xa2a1a09f9e9d9c9b (-7.228e-142)
+#            d28:                 0xaaa9a8a7a6a5a4a3 (-3.580e-103)
+#            d29:                 0xb2b1b0afaeadacab (-1.680e-64)
+#                                                  ╙─ 0xb2b1b0afaeadacab'aaa9a8a7a6a5a4a3'a2a1a09f9e9d9c9b'9a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v20: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v21: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#            v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.568e-159, 8.568e-159)
+#                                  ╙───────────────╨─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.311e-26, -8.311e-26)
+#            v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.904e+13, -3.904e+13)
+#            v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.929e+52, -1.929e+52)
+#            v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.073e+90, -9.073e+90)
+#                                  ╙───────────────╨─ 0xd2d1d0cfcecdcccb'cac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.219e-30, -1.219e-30)
+#            v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.620e+08, -5.620e+08)
+#            v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.829e+47, -2.829e+47)
+#            v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.306e+86, -1.306e+86)
+#                                  ╙───────────────╨─ 0xd1d0cfcecdcccbca'c9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#             d0:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#             d1:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#             d2:                 0x0000000000000000 (0.000, 0.000)
+#                                          ╙───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xd5d4d3d2d5d4d3d2 (-2.925e+13, -2.925e+13)
+#            d29:                 0xd9d8d7d6d9d8d7d6 (-7.629e+15, -7.629e+15)
+#            d30:                 0xdddcdbdadddcdbda (-1.989e+18, -1.989e+18)
+#            d31:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#                                          ╙───────╨─ 0xe1e0dfde'dddcdbda'd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xd4d3d2d1d4d3d2d1 (-7.278e+12, -7.278e+12)
+#            d12:                 0xd8d7d6d5d8d7d6d5 (-1.899e+15, -1.899e+15)
+#            d13:                 0xdcdbdad9dcdbdad9 (-4.951e+17, -4.951e+17)
+#            d14:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#                                          ╙───────╨─ 0xe0dfdedd'dcdbdad9'd8d7d6d5'd4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d20:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d21:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            d22:                 0xff00ff00ff00ff00 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xe2e1e2e1e2e1e2e1 (-880.5, -880.5, -880.5, -880.5)
+#            d23:                 0xe4e3e4e3e4e3e4e3 (-1251., -1251., -1251., -1251.)
+#            d24:                 0xe6e5e6e5e6e5e6e5 (-1765., -1765., -1765., -1765.)
+#            d25:                 0xe8e7e8e7e8e7e8e7 (-2510., -2510., -2510., -2510.)
+#                                      ╙───╨───╨───╨─ 0xe8e7'e6e5'e4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xe1e0e1e0e1e0e1e0 (-752.0, -752.0, -752.0, -752.0)
+#            d21:                 0xe3e2e3e2e3e2e3e2 (-1009., -1009., -1009., -1009.)
+#            d22:                 0xe5e4e5e4e5e4e5e4 (-1508., -1508., -1508., -1508.)
+#            d23:                 0xe7e6e7e6e7e6e7e6 (-2022., -2022., -2022., -2022.)
+#                                      ╙───╨───╨───╨─ 0xe7e6'e5e4'e3e2'e1e0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v17: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v18: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#            v19: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ╙───────╨───────╨───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (-5.680e+26, -5.680e+26, -5.680e+26, -5.680e+26)
+#            v26: 0xefeeedecefeeedecefeeedecefeeedec (-1.479e+29, -1.479e+29, -1.479e+29, -1.479e+29)
+#            v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (-3.850e+31, -3.850e+31, -3.850e+31, -3.850e+31)
+#            v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (-1.002e+34, -1.002e+34, -1.002e+34, -1.002e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf7f6f5f4'f3f2f1f0'efeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (-1.414e+26, -1.414e+26, -1.414e+26, -1.414e+26)
+#            v24: 0xeeedecebeeedecebeeedecebeeedeceb (-3.682e+28, -3.682e+28, -3.682e+28, -3.682e+28)
+#            v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (-9.584e+30, -9.584e+30, -9.584e+30, -9.584e+30)
+#            v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (-2.494e+33, -2.494e+33, -2.494e+33, -2.494e+33)
+#                          ╙───────╨───────╨───────╨─ 0xf6f5f4f3'f2f1f0ef'eeedeceb'eae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x0101010101010101
+#            d23:                 0xffffffffffffffff
+#            d24:                 0x0202020202020202
+#            d25:                 0x0000000000000000
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xf7f7f7f7f7f7f7f7
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8'f7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xf6f6f6f6f6f6f6f6
+#            d30:                 0xf7f7f7f7f7f7f7f7
+#            d31:                 0xf8f8f8f8f8f8f8f8
+#             d0:                 0xf9f9f9f9f9f9f9f9
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xf9'f8'f7'f6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v29: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            v30: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            v31: 0xff00ff00ff00ff00ff00ff00ff00ff00 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#            v26: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v27: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v28: 0x01000100010001000100010001000100 (1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0100'fffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0xfaf9faf9faf9faf9faf9faf9faf9faf9 (-5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04)
+#            v23: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v24: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v25: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0002000200020002e73aed42f34af952
+#             v6: 0x0000000000000000dcbb11e0e6481e68
+#             v9: 0x00000000000000000000000000fffeff
+#             v5: 0x0000000000000000a4a2261ba09e2217
+#            v24: 0x000000000000000082b3330de36793c1
+#            v12: 0x00000000000000006f49f4f5e911f705
+#            v10: 0x00000000000000001700000000000000
+#             v3: 0x000000000000000035342d2c25221f1b
+#            v19: 0xfe070c07fe070c07fe070c07fe070c07
+#             v6: 0x0000000000000000dcbb11e0e6481e68
+#            v23: 0xfcfbfcfbfcfbfcfbf0fbfcfbfcfbfcfb
+#            v14: 0x0000000000000000d8e1d7ddd8e1d7dd
+#            v28: 0x00000000000000000100010001000100
+#             v2: 0x0000000000000000ac03d811ac03d811
+#            v18: 0x000000000000000000fffeff00fffeff
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+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x0000000000000000000000000000007f
+#                                  ║               ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x000000000000002f0000290000230000
+#   z21<255:128>: 0x00000000000000002e00000000002200
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x22'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x2e'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x0000007f007f00000000000000000000
+#   z21<383:256>: 0x00000000800000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x80'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<511:384>: 0x00000000000000000000000000000000
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#     z22<127:0>: 0x000000007f807f800000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#     z23<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f800000'7f800000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#     z24<127:0>: 0x00000000000000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'7f8000007f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z24<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x0000000000000000000000ff00000000
+#     z25<127:0>: 0xa000000000000000000000ffc0000000
+#     z26<127:0>: 0x3700000000000000000000007f000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x7f'c0'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'ff'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x37'a0'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<639:512>: 0x00000000000000000000000000000000
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z25<127:0>: 0x292823221d1c17160000000000000000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z26<127:0>: 0x2b2a25241f1e191813120d0c07060100 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z27<127:0>: 0x2d2c272621201b1a1514000009080000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0100'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0908'0706'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0d0c'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514'1312'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1b1a'1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2120'1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x595853524d4c474641403b3a35342f2e (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z26<255:128>: 0x5b5a55544f4e494843423d3c37363130 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z27<255:128>: 0x5d5c575651504b4a45443f3e39383332 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3332'3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3938'3736'3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544'4342'4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4b4a'4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5150'4f4e'4d4c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c'5b5a'5958 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x898883827d7c777671706b6a65645f5e (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z26<383:256>: 0x8b8a85847f7e797873726d6c67666160 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z27<383:256>: 0x8d8c878681807b7a75746f6e69686362 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x6362'6160'5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6968'6766'6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6f6e'6d6c'6b6a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x7574'7372'7170 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7b7a'7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x8180'7f7e'7d7c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x8786'8584'8382 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8d8c'8b8a'8988 <- 0x~~~~~~~~~~~~~~~~
+#   z25<511:384>: 0xb9b8b3b2adaca7a6a1a09b9a95948f8e (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#   z26<511:384>: 0xbbbab5b4afaea9a8a3a29d9c97969190 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#   z27<511:384>: 0xbdbcb7b6b1b0abaaa5a49f9e99989392 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x9392'9190'8f8e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x9998'9796'9594 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x9f9e'9d9c'9b9a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xa5a4'a3a2'a1a0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xabaa'a9a8'a7a6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xb1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xb7b6'b5b4'b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xbdbc'bbba'b9b8 <- 0x~~~~~~~~~~~~~~~~
+#   z25<639:512>: 0xe9e8e3e2dddcd7d6d1d0cbcac5c4bfbe (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#   z26<639:512>: 0xebeae5e4dfded9d8d3d2cdccc7c6c1c0 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#   z27<639:512>: 0xedece7e6e1e0dbdad5d4cfcec9c8c3c2 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xc3c2'c1c0'bfbe <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xc9c8'c7c6'c5c4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xcfce'cdcc'cbca <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd5d4'd3d2'd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xdbda'd9d8'd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xe1e0'dfde'dddc <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xe7e6'e5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#     z26<127:0>: 0x00000000000000000000ffff00000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z27<127:0>: 0x00000000000000007fff000000000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z28<127:0>: 0x37a0000000000000000000007fc00000 (0.000, 0.000, 9.183e-41, 0.000)
+#                          ║       ║       ║       ╙─ 0x7fc00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'7fff0000'0000ffff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x37a00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z27<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000ffff7fc00000 (0.000, 0.000)
+#     z29<127:0>: 0x37a0000000000000000000007fff0000 (0.000, 0.000)
+#                                  ║               ╙─ 0x000000007fff0000'0000ffff7fc00000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x37a0000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z25<127:0>: 0x0000000000000000000000f300000000
+#     z26<127:0>: 0x00000000000000000000000400000000
+#     z27<127:0>: 0x0080000000800000000000ff00000000
+#     z28<127:0>: 0x007f0000007f0000000000ff00000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0xff'ff'04'f3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#   z27<255:128>: 0x00000000000000000000000000000000
+#   z28<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#   z27<383:256>: 0x00000000000000000000000000000000
+#   z28<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#   z27<511:384>: 0x00000000000000000000000000000000
+#   z28<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#   z27<639:512>: 0x00000000000000000000000000000000
+#   z28<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z26<127:0>: 0x00000000000000003fb504f300000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z27<127:0>: 0x7f8000007f800000ffffffff00000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'ffff'04f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'ffff'3fb5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#     z27<127:0>: 0x2f2e2d2c000000000000000000000000 (1.584e-10, 0.000, 0.000, 0.000)
+#     z28<127:0>: 0x33323130000000007f80000000000000 (1.584e-10, 0.000, 0.000, 0.000)
+#     z29<127:0>: 0x00000000000000000000000007060504 (1.584e-10, 0.000, 0.000, 0.000)
+#     z30<127:0>: 0x00000000000000007f8000000b0a0908 (1.584e-10, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7f800000'00000000'7f800000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
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+#   z30<255:128>: 0x00000000000000005b5a595800000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5b5a5958'57565554'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<383:256>: 0xafaeadac9f9e9d9c8f8e8d8c7f7e7d7c (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z28<383:256>: 0xb3b2b1b0a3a2a1a09392919083828180 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z29<383:256>: 0xb7b6b5b4a7a6a5a49796959487868584 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z30<383:256>: 0xbbbab9b8abaaa9a89b9a99988b8a8988 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#                          ║       ║       ║       ╙─ 0x8b8a8988'87868584'83828180'7f7e7d7c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x9b9a9998'97969594'93929190'8f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xabaaa9a8'a7a6a5a4'a3a2a1a0'9f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xbbbab9b8'b7b6b5b4'b3b2b1b0'afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   z27<511:384>: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z28<511:384>: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z29<511:384>: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z30<511:384>: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#   z27<639:512>: 0x2f2e2d2c1f1e1d1c0f0e0d0cfffefdfc (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z28<639:512>: 0x33323130232221201312111003020100 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z29<639:512>: 0x37363534272625241716151407060504 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z30<639:512>: 0x3b3a39382b2a29281b1a19180b0a0908 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'03020100'fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1b1a1918'17161514'13121110'0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928'27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3b3a3938'37363534'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#     z28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z29<127:0>: 0x000000007f8000000000000000000000 (0.000, 0.000)
+#     z30<127:0>: 0x000000000000000000000000ffff04f3 (0.000, 0.000)
+#     z31<127:0>: 0x000000007f80000000000000ffff3fb5 (0.000, 0.000)
+#                                  ║               ╙─ 0x00000000ffff3fb5'00000000ffff04f3'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x000000007f800000'0000000000000000'000000007f800000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z30<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z31<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
diff --git a/test/test-trace-reference/log-state-colour b/test/test-trace-reference/log-state-colour
index 54dc558d..0f1b75e4 100644
--- a/test/test-trace-reference/log-state-colour
+++ b/test/test-trace-reference/log-state-colour
@@ -1,97 +1,310 @@
-#    x0: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0300003000300303
-#    x4: 0x0400004000400404
-#    x5: 0x0500005000500505
-#    x6: 0x0600006000600606
-#    x7: 0x0700007000700707
-#    x8: 0x0800008000800808
-#    x9: 0x0900009000900909
-#   x10: 0x0a0000a000a00a0a
-#   x11: 0x0b0000b000b00b0b
-#   x12: 0x0c0000c000c00c0c
-#   x13: 0x0d0000d000d00d0d
-#   x14: 0x0e0000e000e00e0e
-#   x15: 0x0f0000f000f00f0f
-#   x16: 0x1000010001001010
-#   x17: 0x1100011001101111
-#   x18: 0x1200012001201212
-#   x19: 0x1300013001301313
-#   x20: 0x1400014001401414
-#   x21: 0x1500015001501515
-#   x22: 0x1600016001601616
-#   x23: 0x1700017001701717
-#   x24: 0x1800018001801818
-#   x25: 0x1900019001901919
-#   x26: 0x1a0001a001a01a1a
-#   x27: 0x1b0001b001b01b1b
-#   x28: 0x1c0001c001c01c1c
-#   x29: 0x1d0001d001d01d1d
-#    lr: 0x0000000000000000
-#    sp: 0x~~~~~~~~~~~~~~~~
-#    v0: 0x00055555005555550000000000000000
-#    v1: 0x3ff0d2c63fcb514c3ff587933f9e0419
-#    v2: 0x4000d2c6404b514c40058793401e0419
-#    v3: 0x401570fb40385373401025ae406d0626
-#    v4: 0x4010d2c640cb514c40158793409e0419
-#    v5: 0x401fbc2d4090d04a401ae97840c5851f
-#    v6: 0x402570fb40b85373402025ae40ed0626
-#    v7: 0x402783f4415f16c34022d6a1410a4396
-#    v8: 0x4020d2c6414b514c40258793411e0419
-#    v9: 0x402d6dd3416491c9402838864131c49c
-#   v10: 0x402fbc2d4110d04a402ae9784145851f
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+#     FFR<79:64>: 0b 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
+#             w3:         0x00900909
+#             x6: 0x0f0000f000f00f0f
 # NZCV: N:0 Z:0 C:0 V:0
-#    x9: 0x0000000001501515
+#             w9:         0x01501515
 # NZCV: N:0 Z:0 C:0 V:0
-#   x12: 0x1b0001b001b01b1b
-#   x15: 0x0000000002102121
-#   x18: 0x2700027002702727
+#            x12: 0x1b0001b001b01b1b
+#            w15:         0x02102121
+#            x18: 0x2700027002702727
 # NZCV: N:0 Z:0 C:0 V:0
-#   x21: 0x0000000002d02d2d
+#            w21:         0x02d02d2d
 # NZCV: N:0 Z:0 C:0 V:0
-#   x24: 0x3300033003303333
-#   x27: 0x0000000001c01c1c
-#    x2: 0x~~~~~~~~~~~~~~~~
+#            x24: 0x3300033003303333
+#            w27:         0x01c01c1c
+#             x2: 0x~~~~~~~~~~~~~~~~
 # NZCV: N:0 Z:0 C:0 V:0
-#    x5: 0x0000000000700707
+#             w5:         0x00700707
 # NZCV: N:0 Z:1 C:0 V:0
-#    x8: 0x0000000000000000
-#   x11: 0x0000000001b01b1b
-#   x13: 0x0700007000700707
-#   x15: 0x0000000000000080
-#   x18: 0x0000013000130013
-#   x21: 0x0000000002d02d2c
-#   x23: 0x1700017001701716
-#   x25: 0x0000000000200202
-#   x28: 0x1d0001d001d01d1d
+#             x8: 0x0000000000000000
+#            w11:         0x01b01b1b
+#            x13: 0x0700007000700707
+#            w15:         0x00000080
+#            x18: 0x0000013000130013
+#            w21:         0x02d02d2c
+#            x23: 0x1700017001701716
+#            w25:         0x00200202
+#            x28: 0x1d0001d001d01d1d
 # NZCV: N:0 Z:1 C:0 V:0
-#    x3: 0x0000000000000000
+#             w3:         0x00000000
 # NZCV: N:0 Z:0 C:0 V:0
-#    x6: 0x0700007000700707
+#             x6: 0x0700007000700707
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:0 V:0
@@ -104,2989 +317,5897 @@
 # NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:1
 # NZCV: N:1 Z:0 C:0 V:0
-#   x17: 0x0000000000130014
-#   x17: 0x0000000000130013
-#   x19: 0x1400014001401414
-#   x19: 0x1400014001401415
-#   x21: 0x0000000001601616
-#   x21: 0x00000000fe9fe9e9
-#   x23: 0xccfffccffccfcccc
-#   x23: 0x3300033003303333
-#   x25: 0x0000000000000006
-#   x27: 0x0000000000000002
-#   x29: 0x0000000000000020
-#    x3: 0x0000000000000005
+#            w17:         0x00130014
+#            w17:         0x00130013
+#            x19: 0x1400014001401414
+#            x19: 0x1400014001401415
+#            w21:         0x01601616
+#            w21:         0xfe9fe9e9
+#            x23: 0xccfffccffccfcccc
+#            x23: 0x3300033003303333
+#            w25:         0x00000006
+#            x27: 0x0000000000000002
+#            w29:         0x00000020
+#             x3: 0x0000000000000005
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:0
 # NZCV: N:1 Z:0 C:0 V:0
-#   x13: 0x0000000000e00e0e
-#   x13: 0x00000000ff1ff1f2
-#   x15: 0x1000010001001010
-#   x15: 0xeffffefffeffeff0
-#   x17: 0x00000000e963b635
-#   x20: 0x00000000ad83ccb8
-#   x23: 0x000000003ed5525d
-#   x26: 0x00000000bc365145
-#    x4: 0x0000000000000070
-#    x7: 0x00000000b096abf4
-#   x13: 0x0000000000e00e0e
-#   x13: 0x00000000feffeff0
-#   x16: 0x0000013000130013
-#   x16: 0x00000000e963b635
-#   x19: 0x0000000000000000
-#   x19: 0x0000000000000001
-#   x20: 0x0000000000000001
-#   x20: 0x0000000000000000
-#   x21: 0x0000000000000000
-#   x21: 0x00000000ffffffff
-#   x22: 0x0000000000000000
-#   x22: 0xffffffffffffffff
-#   x23: 0x0000000003303333
-#   x23: 0x0000000000000007
-#   x26: 0x1d0001d001d01d1e
-#   x26: 0x0000000000000002
-#   x29: 0x00000000fffffffa
-#   x29: 0x0000000000000000
-#    x4: 0x0000000000700707
-#    x4: 0xf8ffff8fff8ff8f8
-#    x7: 0x00000000feafeaeb
-#    x7: 0x0000000000000000
-#   x10: 0xe4fffe4ffe4fe4e5
-#   x10: 0x0000000001b01b1b
-#   x13: 0x0000000001e01e01
-#   x16: 0xfffffecf168f49d9
-#   x19: 0x00000000ffffffff
-#   x22: 0x3300033003303334
-#   x25: 0x0000000001000000
-#   x28: 0x0000000000000000
-#    x3: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x13: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x15: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   x16: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#   x17: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x18: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x19: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000013121110 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000017161514 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000033323130 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000037363534 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0000000047464544 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000043424140 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x29: 0x000000004b4a4948 <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000058 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x3: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005a <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x4: 0x000000000000005c <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000005d5c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000006160 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x6: 0x0000000000006564 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000064 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x7: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000066 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x8: 0x0000000000000068 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000006968 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x9: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000006d6c <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x10: 0x0000000000007170 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x11: 0x0000000073727170 <- 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#    x1: 0x~~~~~~~~~~~~~~~~
-#   x11: 0x000000007b7a7978 <- 0x~~~~~~~~~~~~~~~~
-#   x12: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
-#   x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
-#   x14: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x15: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x16: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x17: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x18: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x19: 0x0000000000000001 <- 0x~~~~~~~~~~~~~~~~
-#   x20: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x21: 0x0000000000000403 <- 0x~~~~~~~~~~~~~~~~
-#   x22: 0x000000000a090807 <- 0x~~~~~~~~~~~~~~~~
-#   x23: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x24: 0x0000000007060504 <- 0x~~~~~~~~~~~~~~~~
-#   x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
-#   x27: 0x0000000003020100 <- 0x~~~~~~~~~~~~~~~~
-#   x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
-#   x29: 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
-#    x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
-#    x3: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x4: 0x0000000000000100 <- 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000000019590
-#    x7: 0x0000000000000340
-#    x9: 0x0000000070000000
-#   x12: 0x2c2a28262422201e
-#   x15: 0x0000000000000040
-#   x17: 0x0000000000000000
-#   x19: 0x0000000000000080
-#   x22: 0x0000000000302010
-#   x25: 0x00000000371b0900
-#   x29: 0x0000000000000100
-#    x5: 0x00000000feb67b00
-#    x8: 0xffffce5f00000000
-#   x11: 0x000000002422201e
-#   x13: 0x0000000000000001
-#   x15: 0x0000000000000082
-#   x16: 0x0000000000000083
-#   x17: 0x00000000ffffff7b
-#   x18: 0xffffffffffffff7a
-#   x19: 0x0000000000000086
-#   x20: 0x0000000000000087
-#   x22: 0x000000001b0e0500
-#   x26: 0xe3e9eff5fbff0100
-#    x2: 0x~~~~~~~~~~~~~~~~
-#    x5: 0x0000000001498500
-#    x8: 0x000000008fffffff
-#   x10: 0xffffffffdbdddfe1
-#   x12: 0x00000000ffffffff
-#   x14: 0xffffffffffffff7e
+#            w13:         0x00e00e0e
+#            w13:         0xff1ff1f2
+#            x15: 0x1000010001001010
+#            x15: 0xeffffefffeffeff0
+#            w17:         0xe963b635
+#            w20:         0xad83ccb8
+#            w23:         0x3ed5525d
+#            w26:         0xbc365145
+#             w4:         0x00000070
+#             w7:         0xb096abf4
+#            w13:         0x00e00e0e
+#            w13:         0xfeffeff0
+#            x16: 0x0000013000130013
+#            x16: 0x00000000e963b635
+#            w19:         0x00000000
+#            w19:         0x00000001
+#            x20: 0x0000000000000001
+#            x20: 0x0000000000000000
+#            w21:         0x00000000
+#            w21:         0xffffffff
+#            x22: 0x0000000000000000
+#            x22: 0xffffffffffffffff
+#            w23:         0x03303333
+#            w23:         0x00000007
+#            x26: 0x1d0001d001d01d1e
+#            x26: 0x0000000000000002
+#            w29:         0xfffffffa
+#            w29:         0x00000000
+#             x4: 0x0000000000700707
+#             x4: 0xf8ffff8fff8ff8f8
+#             w7:         0xfeafeaeb
+#             w7:         0x00000000
+#            x10: 0xe4fffe4ffe4fe4e5
+#            x10: 0x0000000001b01b1b
+#            w13:         0x01e01e01
+#            x16: 0xfffffecf168f49d9
+#            w19:         0xffffffff
+#            x22: 0x3300033003303334
+#            w25:         0x01000000
+#            x28: 0x0000000000000000
+#             w3:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#             x4: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w8:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w10:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x12: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            w13:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x14: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            w15:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            w16:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            w17:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#            w18:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#            w19:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w20:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            x21: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x22: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            w23:         0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x17161514 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x1716151413121110 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x25: 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000003020100
+#                                  ╙─ 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000007060504
+#                                  ╙─ 0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000033323130
+#                                  ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000037363534
+#                                  ╙─ 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x27: 0x0000000043424140
+#                                  ╙─ 0x43424140 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0000000047464544
+#                                  ╙─ 0x47464544 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x43424140 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            w29:         0x4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x2: 0x~~~~~~~~~~~~~~~~ <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000058
+#                                  ╙─ 0x58 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w3:         0x0000005a
+#                                  ╙─ 0x5a <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x0000005a
+#                                  ╙─ 0x5a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w4:         0x0000005c
+#                                  ╙─ 0x5c <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00005d5c
+#                                  ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00006160
+#                                  ╙─ 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00006160
+#                                  ╙─ 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w6:         0x00006564
+#                                  ╙─ 0x6564 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000064
+#                                  ╙─ 0x64 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w7:         0x00000066
+#                                  ╙─ 0x66 <- 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000066
+#                                  ╙─ 0x66 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x8: 0x0000000000000068
+#                                  ╙─ 0x68 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00006968
+#                                  ╙─ 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             w9:         0x00006d6c
+#                                  ╙─ 0x6d6c <- 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000006d6c
+#                                  ╙─ 0x6d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x10: 0x0000000000007170
+#                                  ╙─ 0x7170 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0000000003020100
+#                                  ╙─ 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x11: 0x0000000073727170
+#                                  ╙─ 0x73727170 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            x11: 0x000000007b7a7978
+#                                  ╙─ 0x7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#            w12:         0x0a090807 <- 0x~~~~~~~~~~~~~~~~
+#            x13: 0x161514131211100f <- 0x~~~~~~~~~~~~~~~~
+#            w14:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            w15:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            w16:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#            w17:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#            w18:         0x00000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            x19: 0x0000000000000001
+#                                  ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            w20:         0x00000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#            x21: 0x0000000000000403
+#                                  ╙─ 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#            x22: 0x000000000a090807
+#                                  ╙─ 0x0a090807 <- 0x~~~~~~~~~~~~~~~~
+#            w23:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            w24:         0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            x25: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            x26: 0x0f0e0d0c0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#            w27:         0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#            x28: 0x0706050403020100 <- 0x~~~~~~~~~~~~~~~~
+#            w29:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w2:         0x00000000
+#                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             w3:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w4:         0x00000100
+#                                  ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#             w5:         0x00019590
+#             x7: 0x0000000000000340
+#             w9:         0x70000000
+#            x12: 0x2c2a28262422201e
+#            w15:         0x00000040
+#            x17: 0x0000000000000000
+#            w19:         0x00000080
+#            x22: 0x0000000000302010
+#            w25:         0x371b0900
+#            x29: 0x0000000000000100
+#             w5:         0xfeb67b00
+#             x8: 0xffffce5f00000000
+#            w11:         0x2422201e
+#            x13: 0x0000000000000001
+#            x15: 0x0000000000000082
+#            x16: 0x0000000000000083
+#            x17: 0x00000000ffffff7b
+#            x18: 0xffffffffffffff7a
+#            x19: 0x0000000000000086
+#            x20: 0x0000000000000087
+#            w22:         0x1b0e0500
+#            x26: 0xe3e9eff5fbff0100
+#             w2:         0x00010000
+#             x5: 0x0000000001498500
+#             w8:         0x8fffffff
+#            x10: 0xffffffffdbdddfe1
+#            w12:         0xffffffff
+#            x14: 0xffffffffffffff7e
 # NZCV: N:0 Z:0 C:0 V:0
-#   x16: 0x0000000000000085
+#            w16:         0x00000085
 # NZCV: N:1 Z:0 C:0 V:0
-#   x18: 0xffffffffffffff7a
-#   x20: 0x00000000fffffbfc
-#   x22: 0xfffffffffcfdfeff
+#            x18: 0xffffffffffffff7a
+#            w20:         0xfffffbfc
+#            x22: 0xfffffffffcfdfeff
 # NZCV: N:1 Z:0 C:0 V:0
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-#   x16: 0x000000000000000c
-#   x18: 0x0000000000000060
-#   x22: 0x0000000000000004
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 # NZCV: N:1 Z:0 C:0 V:0
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-#    x8: 0x0000000000000001
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 # NZCV: N:0 Z:0 C:0 V:0
 # NZCV: N:0 Z:1 C:0 V:0
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-#   x28: 0x0000000000000000
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-# NZCV: N:0 Z:0 C:1 V:0
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-# NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:1
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0b0a09080706050403020100fffefdfc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfb <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xeb <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xdb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x0a09080706050403020100fffefdfcfb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xeb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x3a393837363534333231302f2e2d2c2b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x2a292827262524232221201f1e1d1c1b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x1a191817161514131211100f0e0d0c0b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x393837363534333231302f2e2d2c2b2a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x292827262524232221201f1e1d1c1b1a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x191817161514131211100f0e0d0c0b0a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x595857565554535251504f4e4d4c4b4a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x59 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x5857565554535251504f4e4d4c4b4a49
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x49 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x4847464544434241403f3e3d3c3b3a39
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ╙───────── 0x7e7d7c7b <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x9c9b <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xdad9 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
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+#            v29: 0x3f3e3d3c3b3a39383736353433323130 (0.7431, 0.002842, 1.086e-05, 4.149e-08)
+#                          ║       ║       ║       ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
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+#                          ║       ║       ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x0b0a0908 <- 0x~~~~~~~~~~~~~~~~
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+#            v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.008e-34, 3.820e-37, nan, -2.606e+36)
+#                          ║       ║       ║       ╙─ 0xfbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.002e+34, -3.850e+31, -1.479e+29, -5.680e+26)
+#                          ║       ║       ║       ╙─ 0xebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xefeeedec <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf7f6f5f4 <- 0x~~~~~~~~~~~~~~~~
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+#             v7: 0x262524232221201f1e1d1c1b1a191817 (5.729e-16, 2.184e-18, 8.317e-21, 3.166e-23)
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+#                          ║       ║       ╙───────── 0x1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
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+#             v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.502e-35, 9.478e-38, -1.688e+38, -6.490e+35)
+#                          ║       ║       ║       ╙─ 0xfaf9f8f7 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0xeae9e8e7 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
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+#             v2: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
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+#            v24: 0x565554535251504f4e4d4c4b4a494847 (5.864e+13, 2.247e+11, 8.611e+08, 3.298e+06)
+#                          ║       ║       ║       ╙─ 0x4a494847 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x4e4d4c4b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x5251504f <- 0x~~~~~~~~~~~~~~~~
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+#            v23: 0x464544434241403f3e3d3c3b3a393837 (1.263e+04, 48.31, 0.1848, 0.0007066)
+#                          ║       ║       ║       ╙─ 0x3a393837 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x4241403f <- 0x~~~~~~~~~~~~~~~~
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+#            v22: 0x363534333231302f2e2d2c2b2a292827 (2.700e-06, 1.031e-08, 3.937e-11, 1.502e-13)
+#                          ║       ║       ║       ╙─ 0x2a292827 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x3231302f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x36353433 <- 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xc0bfbebdbcbbbab9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d31:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xd0cfcecdcccbcac9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xcfcecdcccbcac9c8
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x3f3e3d3c3b3a39383736353433323130 (1.811, 1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0f0e0d0c0b0a09080706050403020100 (0.0004306, 0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 (nan, nan, -6.534e+04, -4.890e+04, -3.261e+04, -2.438e+04, -1.627e+04, -1.216e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf1f0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf3f2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf5f4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf7f6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfbfa <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfdfc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 (-8120., -6064., -4052., -3024., -2022., -1508., -1009., -752.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe9e8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xebea <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xedec <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xefee <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 (-503.5, -375.0, -251.2, -187.0, -125.4, -93.25, -62.56, -46.50)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b0a09080706050403020100ff (0.0003693, 0.0002468, 0.0001842, 0.0001229, 9.185e-05, 6.121e-05, 3.058e-05, 1.520e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0201 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0605 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0807 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0a09 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0c0b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0e0d <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef (nan, nan, -5.712e+04, -4.067e+04, -2.850e+04, -2.027e+04, -1.422e+04, -1.010e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf0ef <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf2f1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf4f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf6f5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf8f7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfcfb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfefd <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df (-7092., -5036., -3538., -2510., -1765., -1251., -880.5, -623.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xeae9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xeceb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xeeed <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf (-439.2, -310.8, -219.1, -154.9, -109.3, -77.19, -54.53, -38.47)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3e3d3c3b3a393837363534333231302f (1.560, 1.058, 0.7778, 0.5269, 0.3879, 0.2625, 0.1935, 0.1307)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x302f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3433 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3635 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3837 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3c3b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2e2d2c2b2a292827262524232221201f (0.09650, 0.06512, 0.04813, 0.03244, 0.02400, 0.01616, 0.01197, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2e2d <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1e1d1c1b1a191817161514131211100f (0.005970, 0.004009, 0.002977, 0.001997, 0.001485, 0.0009947, 0.0007405, 0.0004954)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x100f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1211 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1413 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1615 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1e1d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a393837363534333231302f2e (1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x5d5c5b5a595857565554535251504f4e (343.0, 235.2, 171.0, 117.4, 85.25, 58.56, 42.50, 29.22)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4f4e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5150 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5554 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5958 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5b5a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857565554535251504f4e4d (278.8, 203.1, 138.9, 101.3, 69.19, 50.53, 34.47, 25.20)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4e4d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x504f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5251 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5453 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5857 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5a59 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5c5b <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x4c4b4a494847464544434241403f3e3d (17.17, 12.57, 8.555, 6.270, 4.262, 3.127, 2.123, 1.560)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x403f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4443 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4645 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4c4b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v9: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a696867666564636261605f5e5d (4524., 3282., 2254., 1637., 1123., 816.5, 559.5, 407.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5e5d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6463 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6665 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6a69 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6c6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x6b6a696867666564636261605f5e5d5c (3796., 2768., 1894., 1380., 945.0, 688.0, 471.5, 343.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6766 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6b6a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a39383736353433323130012e
+#                                                ╙─── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef
+#                                            ╙─────── 0x6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a6b6867666564636261605f5e5d
+#                          ╙───────────────────────── 0x6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.487e+303, ...)
+#                                  ╙───────────────── 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x737271706f6e6d6c636261605f5e5d5c (1.290e+248, ...)
+#                                  ╙───────────────── 0x737271706f6e6d6c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x7271706f6e6d6c6b2726252423222120 (1.861e+243, ...)
+#                                  ╙───────────────── 0x7271706f6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3aff013736353433323130012e (..., nan, ...)
+#                              ╙───────────────────── 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d37473d0cf (..., 1.822e+04, ...)
+#                                              ╙───── 0x7473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857737254535251504f4e4d (..., 1.525e+04, ...)
+#                                  ╙───────────────── 0x7372 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.751e-40, ...)
+#                                  ╙───────────────── 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.999e+33, ...)
+#                                  ╙───────────────── 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.245e+33, ...)
+#                                  ╙───────────────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x01010101010101010101010101010101
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x77777777777777777777777777777777
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x77 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x76767676767676767676767676767676
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x76 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7e7d7c7b7a797877 (1.975e+301)
+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x7d7c7b7a79787776 (2.911e+296)
+#                                                  ╙─ 0x7d7c7b7a79787776 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#                                  ╙───────────────╨─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8584838281807f7e8584838281807f7e (-4.414e-282, -4.414e-282)
+#                                  ╙───────────────╨─ 0x8584838281807f7e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84838281807f7e7d84838281807f7e7d (-6.406e-287, -6.406e-287)
+#                                  ╙───────────────╨─ 0x84838281807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#                                          ╙───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x8887868588878685 (-8.157e-34, -8.157e-34)
+#                                          ╙───────╨─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x8786858487868584 (-2.024e-34, -2.024e-34)
+#                                          ╙───────╨─ 0x87868584 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8988898889888988 (-0.0001688, -0.0001688, -0.0001688, -0.0001688)
+#                                      ╙───╨───╨───╨─ 0x8988 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x8887888788878887 (-0.0001382, -0.0001382, -0.0001382, -0.0001382)
+#                                      ╙───╨───╨───╨─ 0x8887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#                          ╙───────╨───────╨───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (-2.150e-31, -2.150e-31, -2.150e-31, -2.150e-31)
+#                          ╙───────╨───────╨───────╨─ 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0x8b8a89888b8a89888b8a89888b8a8988 (-5.336e-32, -5.336e-32, -5.336e-32, -5.336e-32)
+#                          ╙───────╨───────╨───────╨─ 0x8b8a8988 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x8c8c8c8c8c8c8c8c
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x8b8b8b8b8b8b8b8b
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c (-0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8d8c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b (-0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8c8b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1e1c1a18000000000000ffff00850201
+#            v22: 0x1f1d1b1917000000000000feff0000ff
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x17'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1b'1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f'1e <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#            v22: 0xacaaa8a6a4a2a09e9c9a98969492908e
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x92'91 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x98'97 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa4'a3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaa'a9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xac'ab <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c
+#            v13: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x8f'8e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x95'94 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa1'a0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa7'a6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xa9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xab'aa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0x1700000000000000ff0000850002ff01 (6.689e-198, -5.487e+303)
+#            v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.568e-159, 8.289e-317)
+#                                  ║               ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.703e+18, -1.163e-59)
+#             v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.314e+57, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4'b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcbcac9c8c7c6c5c4'c3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.904e+13, -1.680e-64)
+#            v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.929e+52, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3'b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00fffeff0002ff01 (2.351e-38, 2.751e-40)
+#            d28:                 0x00000000ff000085 (0.000, -1.701e+38)
+#                                          ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xd6d5d4d3cecdcccb (-1.176e+14, -1.726e+09)
+#             d3:                 0xdad9d8d7d2d1d0cf (-3.066e+16, -4.506e+11)
+#                                          ║       ╙─ 0xd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xdad9d8d7'd6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xd5d4d3d2cdcccbca (-2.925e+13, -4.295e+08)
+#            d13:                 0xd9d8d7d6d1d0cfce (-7.629e+15, -1.121e+11)
+#                                          ║       ╙─ 0xd1d0cfce'cdcccbca <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x0000feff0085ff01 (0.000, nan, 7.927e-06, nan)
+#            d10:                 0x000000ffff000002 (0.000, 1.520e-05, nan, 1.192e-07)
+#                                      ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe7e6e3e2dfdedbda (-2022., -1009., -503.5, -251.2)
+#            d24:                 0xe9e8e5e4e1e0dddc (-3024., -1508., -752.0, -375.0)
+#                                      ║   ║   ║   ╙─ 0xdddc'dbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe1e0'dfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe9e8'e7e6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe6e5e2e1dedddad9 (-1765., -880.5, -439.2, -219.1)
+#             d2:                 0xe8e7e4e3e0dfdcdb (-2510., -1251., -623.5, -310.8)
+#                                      ║   ║   ║   ╙─ 0xdcdb'dad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe0df'dedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7'e6e5 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x1b1a19180000000000fffeff0002ff01 (1.275e-22, 0.000, 2.351e-38, 2.751e-40)
+#            v21: 0x1f1e1d1c1700000000000000ff000085 (3.348e-20, 4.136e-25, 0.000, -1.701e+38)
+#                          ║       ║       ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.540e-36, -1.047e+37, -1.546e+32, -2.282e+27)
+#            v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.063e-34, 2.351e-38, -4.023e+34, -5.940e+29)
+#                          ║       ║       ║       ╙─ 0xf0efeeed'ecebeae9 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf8f7f6f5'f4f3f2f1 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffefd'fcfbfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x08070605'04030201 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.820e-37, -2.606e+36, -3.850e+31, -5.680e+26)
+#            v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.008e-34, nan, -1.002e+34, -1.479e+29)
+#                          ║       ║       ║       ╙─ 0xefeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf7f6f5f4'f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xfffefdfc'fbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504'03020100 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000ffff00850201
+#            d18:                 0x000000feff0000ff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x161412100e0c0a08
+#            d14:                 0x171513110f0d0b09
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x09'08 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x11'10 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'16 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1513110f0d0b0907
+#             d8:                 0x161412100e0c0a08
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0a'09 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0e'0d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x16'15 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c1918000000000000feff0085ff01 (0.004990, 0.002487, 0.000, 0.000, 0.000, nan, 7.927e-06, nan)
+#            v31: 0x1f1e1b1a17000000000000ffff000002 (0.006950, 0.003468, 0.001709, 0.000, 0.000, 1.520e-05, nan, 1.192e-07)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1700'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x3433302f2c2b28272423201f1c1b1817 (0.2625, 0.1307, 0.06512, 0.03244, 0.01616, 0.008049, 0.004009, 0.001997)
+#             v5: 0x363532312e2d2a29262522211e1d1a19 (0.3879, 0.1935, 0.09650, 0.04813, 0.02400, 0.01197, 0.005970, 0.002977)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1a19'1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1e1d'1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2221'201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625'2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2a29'2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2e2d'2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3231'302f <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3635'3433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x33322f2e2b2a272623221f1e1b1a1716 (0.2249, 0.1122, 0.05597, 0.02792, 0.01393, 0.006950, 0.003468, 0.001730)
+#            v14: 0x353431302d2c2928252421201d1c1918 (0.3252, 0.1621, 0.08081, 0.04028, 0.02008, 0.01001, 0.004990, 0.002487)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928'2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x363532012e2d2a29262522211e1d1a19
+#             v6: 0x1f1e1dff1b1a19181700000000000000
+#                          ╙───────────────────────── 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x4544434241403f3e363c3b3a39383736
+#            v17: 0x00000000000000003700ffff00850201
+#                                    ╙─────────────── 0x37'36 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfb35f9f8
+#            v30: 0x1d1c1918000000000000feff0036ff01
+#                                              ╙───── 0x36'35 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.487e+303, ...)
+#            v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.289e-317, ...)
+#                                  ╙───────────────── 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x00000000000000003e3d3c3b3a393837 (..., 6.807e-09)
+#            v27: 0x0000000000000000464544434241403f (..., 3.370e+30)
+#                                                  ╙─ 0x464544434241403f'3e3d3c3b3a393837 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x07060504fffefdfc3d3c3b3a39383736 (..., 1.003e-13)
+#            v26: 0x00000000000000004544434241403f3e (..., 4.899e+25)
+#                                                  ╙─ 0x4544434241403f3e'3d3c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0xff01000000000000000000feff0000ff (nan, ...)
+#            v19: 0x00020000000000008b8b8b8b8b8b8b8b (1.192e-07, ...)
+#                      ╙───────────────────────────── 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x00000000474600003700ffff00850201 (..., 7.273, ...)
+#            v18: 0xff01000049480000000000feff0000ff (..., 10.56, ...)
+#                              ╙───────────────────── 0x4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c191800000000000046450036ff01 (..., 6.270, ...)
+#            v31: 0x1f1e1b1a1700000000004847ff000002 (..., 8.555, ...)
+#                                          ╙───────── 0x4847'4645 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.751e-40, ...)
+#            v30: 0xff00008500000000000046450036ff01 (-1.701e+38, ...)
+#                          ╙───────────────────────── 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000000000000000004c4b4a49 (..., 5.329e+07)
+#            v29: 0x0002ff0103020100fffefdfc504f4e4d (..., 1.391e+10)
+#                                                  ╙─ 0x504f4e4d'4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.326e+07, ...)
+#             v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.461e+09, ...)
+#                                          ╙───────── 0x4f4e4d4c'4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x01010101010101010101010101010101
+#            v27: 0xffffffffffffffffffffffffffffffff
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x50505050505050505050505050505050
+#            v22: 0x51515151515151515151515151515151
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x51'50 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f
+#             v6: 0x50505050505050505050505050505050
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x50'4f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-5.487e+303)
+#            d27:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x5857565554535251 (3.678e+117)
+#            d15:                 0x605f5e5d5c5b5a59 (1.682e+156)
+#                                                  ╙─ 0x605f5e5d5c5b5a59'5857565554535251 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x5756555453525150 (5.371e+112)
+#            d24:                 0x5f5e5d5c5b5a5958 (2.485e+151)
+#                                                  ╙─ 0x5f5e5d5c5b5a5958'5756555453525150 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v12: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#                                  ╙───────────────╨─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x67666564636261606766656463626160 (1.247e+190, 1.247e+190)
+#            v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.766e+228, 5.766e+228)
+#                                  ╙───────────────╨─ 0x6f6e6d6c6b6a6968'6766656463626160 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0x666564636261605f666564636261605f (1.818e+185, 1.818e+185)
+#            v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.509e+223, 8.509e+223)
+#                                  ╙───────────────╨─ 0x6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d27:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#                                          ╙───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x7271706f7271706f (4.782e+30, 4.782e+30)
+#            d23:                 0x7675747376757473 (1.245e+33, 1.245e+33)
+#                                          ╙───────╨─ 0x76757473'7271706f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x71706f6e71706f6e (1.191e+30, 1.191e+30)
+#             d3:                 0x7574737275747372 (3.099e+32, 3.099e+32)
+#                                          ╙───────╨─ 0x75747372'71706f6e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#             d3:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                                      ╙───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7776777677767776 (3.056e+04, 3.056e+04, 3.056e+04, 3.056e+04)
+#            d10:                 0x7978797879787978 (4.480e+04, 4.480e+04, 4.480e+04, 4.480e+04)
+#                                      ╙───╨───╨───╨─ 0x7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x7675767576757675 (2.645e+04, 2.645e+04, 2.645e+04, 2.645e+04)
+#             d7:                 0x7877787778777877 (3.658e+04, 3.658e+04, 3.658e+04, 3.658e+04)
+#                                      ╙───╨───╨───╨─ 0x7877'7675 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#             v8: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#                          ╙───────╨───────╨───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (5.223e+36, 5.223e+36, 5.223e+36, 5.223e+36)
+#            v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (-1.171e-38, -1.171e-38, -1.171e-38, -1.171e-38)
+#                          ╙───────╨───────╨───────╨─ 0x807f7e7d'7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x7b7a79787b7a79787b7a79787b7a7978 (1.301e+36, 1.301e+36, 1.301e+36, 1.301e+36)
+#            v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (3.383e+38, 3.383e+38, 3.383e+38, 3.383e+38)
+#                          ╙───────╨───────╨───────╨─ 0x7f7e7d7c'7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#            d27:                 0xffffffffffffffff
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x8080808080808080
+#            d21:                 0x8181818181818181
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x81'80 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x7f7f7f7f7f7f7f7f
+#            d12:                 0x8080808080808080
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x80'7f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v13: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x82818281828182818281828182818281 (-3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05)
+#             v7: 0x84838483848384838483848384838483 (-6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8483'8281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x81808180818081808180818081808180 (-2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05)
+#            v26: 0x83828382838283828382838283828382 (-5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2d2a2724211e1b1800000000fe000001
+#            v21: 0x2e2b2825221f1c1900000000ffff85ff
+#            v22: 0x2f2c292623201d1a1700000000ff0002
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x20'1f'1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x23'22'21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2c'2b'2a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f'2e'2d <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v29: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#            v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x89'88'87 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8c'8b'8a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8f'8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x95'94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x98'97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa1'a0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa4'a3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa7'a6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xaa'a9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xad'ac'ab <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb3'b2'b1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0xb0adaaa7a4a19e9b9895928f8c898683
+#            v21: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v22: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x85'84'83 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x88'87'86 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8b'8a'89 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8e'8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x91'90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x94'93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x97'96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9a'99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa3'a2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa6'a5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa9'a8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xac'ab'aa <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb2'b1'b0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.568e-159, -5.487e+303)
+#            v22: 0x27262524232221200000000000fffeff (4.288e-120, 8.289e-317)
+#            v23: 0x2f2e2d2c2b2a29281700000000000000 (1.988e-81, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928'2726252423222120'1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.073e+90, -8.311e-26)
+#            v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.479e+129, -3.904e+13)
+#            v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.109e+168, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb'dad9d8d7d6d5d4d3'd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.306e+86, -1.219e-30)
+#            v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.569e+124, -5.620e+08)
+#            v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.037e+163, -2.829e+47)
+#                                  ║               ╙─ 0xc9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe1e0dfdedddcdbda'd9d8d7d6d5d4d3d2'd1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x000000000002ff01 (0.000, 2.751e-40)
+#             d8:                 0x00000000ff000085 (0.000, -1.701e+38)
+#             d9:                 0x1700000000fffeff (4.136e-25, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xf1f0efeee5e4e3e2 (-2.386e+30, -1.351e+23)
+#            d21:                 0xf5f4f3f2e9e8e7e6 (-6.210e+32, -3.520e+25)
+#            d22:                 0xf9f8f7f6edecebea (-1.616e+35, -9.165e+27)
+#                                          ║       ╙─ 0xedecebea'e9e8e7e6'e5e4e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xf0efeeede4e3e2e1 (-5.940e+29, -3.363e+22)
+#            d27:                 0xf4f3f2f1e8e7e6e5 (-1.546e+32, -8.761e+24)
+#            d28:                 0xf8f7f6f5ecebeae9 (-4.023e+34, -2.282e+27)
+#                                          ║       ╙─ 0xecebeae9'e8e7e6e5'e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00000000ff00ff01 (0.000, 0.000, nan, nan)
+#            d28:                 0x00000000feff0002 (0.000, 0.000, nan, 1.192e-07)
+#            d29:                 0x1700000000ff0085 (0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                                      ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x0c0b060500fffaf9 (0.0002468, 9.185e-05, 1.520e-05, -5.712e+04)
+#            d29:                 0x0e0d08070201fcfb (0.0003693, 0.0001229, 3.058e-05, nan)
+#            d30:                 0x100f0a090403fefd (0.0004954, 0.0001842, 6.121e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0403'0201'00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0a09'0807'0605 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x100f'0e0d'0c0b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x0b0a0504fffef9f8 (0.0002148, 7.653e-05, nan, -4.890e+04)
+#             d8:                 0x0d0c07060100fbfa (0.0003080, 0.0001072, 1.526e-05, -6.534e+04)
+#             d9:                 0x0f0e09080302fdfc (0.0004306, 0.0001535, 4.590e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfdfc'fbfa'f9f8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0302'0100'fffe <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0908'0706'0504 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0f0e'0d0c'0b0a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x272625241b1a1918000000000002ff01 (2.306e-15, 1.275e-22, 0.000, 2.751e-40)
+#             v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.045e-13, 3.348e-20, 0.000, -1.701e+38)
+#             v4: 0x2f2e2d2c232221201700000000fffeff (1.584e-10, 8.789e-18, 4.136e-25, 2.351e-38)
+#                          ║       ║       ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120'1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c'2b2a2928'27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x373635342b2a29281f1e1d1c13121110 (1.086e-05, 6.045e-13, 3.348e-20, 1.844e-27)
+#            v25: 0x3b3a39382f2e2d2c2322212017161514 (0.002842, 1.584e-10, 8.789e-18, 4.849e-25)
+#            v26: 0x3f3e3d3c33323130272625241b1a1918 (0.7431, 4.149e-08, 2.306e-15, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918'17161514'13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x33323130'2f2e2d2c'2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v11: 0x363534332a2928271e1d1c1b1211100f (2.700e-06, 1.502e-13, 8.317e-21, 4.577e-28)
+#            v12: 0x3a3938372e2d2c2b2221201f16151413 (0.0007066, 3.937e-11, 2.184e-18, 1.204e-25)
+#            v13: 0x3e3d3c3b3231302f262524231a191817 (0.1848, 1.031e-08, 5.729e-16, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817'16151413'1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x26252423'2221201f'1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3231302f'2e2d2c2b'2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3e3d3c3b'3a393837'36353433 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x00000000fe000001
+#            d30:                 0x00000000ffff85ff
+#            d31:                 0x1700000000ff0002
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x54514e4b4845423f
+#             d2:                 0x55524f4c49464340
+#             d3:                 0x5653504d4a474441
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x41'40'3f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x44'43'42 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x47'46'45 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x4a'49'48 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4d'4c'4b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x50'4f'4e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x53'52'51 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x56'55'54 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x53504d4a4744413e
+#            d13:                 0x54514e4b4845423f
+#            d14:                 0x55524f4c49464340
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40'3f'3e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x43'42'41 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x46'45'44 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x49'48'47 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4c'4b'4a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x4f'4e'4d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x52'51'50 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x55'54'53 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x2b2a25241f1e191800000000ff00ff01 (0.05597, 0.02008, 0.006950, 0.002487, 0.000, 0.000, nan, nan)
+#            v23: 0x2d2c272621201b1a00000000feff0002 (0.08081, 0.02792, 0.01001, 0.003468, 0.000, 0.000, nan, 1.192e-07)
+#            v24: 0x2f2e292823221d1c1700000000ff0085 (0.1122, 0.04028, 0.01393, 0.004990, 0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2322'2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2928'2726'2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e696863625d5c5756 (-2.289e-05, 6.125e+04, 2.234e+04, 7608., 2768., 945.0, 343.0, 117.4)
+#            v14: 0x83827d7c777671706b6a65645f5e5958 (-5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5, 171.0)
+#            v15: 0x85847f7e797873726d6c676661605b5a (-8.416e-05, nan, 4.480e+04, 1.525e+04, 5552., 1894., 688.0, 235.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5b5a'5958'5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6160'5f5e'5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6766'6564'6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6d6c'6b6a'6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7372'7170'6f6e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7978'7776'7574 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8584'8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x807f7a7974736e6d686762615c5b5655 (-7.570e-06, 5.302e+04, 1.822e+04, 6580., 2254., 816.5, 278.8, 101.3)
+#            v29: 0x82817c7b7675706f6a6964635e5d5857 (-3.821e-05, nan, 2.645e+04, 9080., 3282., 1123., 407.2, 138.9)
+#            v30: 0x84837e7d787772716c6b6665605f5a59 (-6.884e-05, nan, 3.658e+04, 1.319e+04, 4524., 1637., 559.5, 203.1)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5a59'5857'5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f'5e5d'5c5b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6665'6463'6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6c6b'6a69'6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7271'706f'6e6d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7877'7675'7473 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7e7d'7c7b'7a79 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8483'8281'807f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v21: 0x0000000001000000f5f4f3f2e9e8e7e6
+#            v22: 0x2b2a2524ff1e191800000000ff00ff01
+#            v23: 0x2d2c272602201b1a00000000feff0002
+#                            ╙─────────────────────── 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f
+#             v6: 0x82818281828186818281828182818281
+#             v7: 0x00000000000087000b0a0504fffef9f8
+#                                ╙─────────────────── 0x87'86'85 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0x2d2c272602201b1a00000000feff0084
+#            v24: 0x2f2e292823221d1c1700000000ff0085
+#            v25: 0x3b3a39382f2e2d2c2322212017161586
+#                                                  ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6e6d6c6b6a696867ff0000850002ff01 (..., -5.487e+303)
+#            v17: 0x00000000474600000000000000fffeff (..., 8.289e-317)
+#            v18: 0xd2d1d0cfcecdcccb1700000000000000 (..., 6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84837e7d787772718e8d8c8b8a898887 (..., -1.418e-238)
+#            v31: 0x0000000000000000969594939291908f (..., -7.048e-200)
+#             v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (..., -3.291e-161)
+#                                                  ╙─ 0x9e9d9c9b9a999897'969594939291908f'8e8d8c8b8a898887 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.090e-243, ...)
+#            v29: 0x9594939291908f8e6a6964635e5d5857 (-1.025e-204, ...)
+#            v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.851e-166, ...)
+#                                  ╙───────────────── 0x9d9c9b9a99989796'9594939291908f8e'8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e6968ff015d5c5756 (..., nan, ...)
+#            v14: 0x83827d7c777671706b6a00025f5e5958 (..., 1.192e-07, ...)
+#            v15: 0x85847f7e797873726d6c008561605b5a (..., 7.927e-06, ...)
+#                                          ╙───────── 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x9f9e2524ff1e191800000000ff00ff01 (-0.007439, ...)
+#            v23: 0xa1a0272602201b1a00000000feff0084 (-0.01099, ...)
+#            v24: 0xa3a2292823221d1c1700000000ff0085 (-0.01491, ...)
+#                      ╙───────────────────────────── 0xa3a2'a1a0'9f9e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0x83827d7c777671709e9d00025f5e5958 (..., -0.006458, ...)
+#            v15: 0x85847f7e79787372a09f008561605b5a (..., -0.009026, ...)
+#            v16: 0x6e6d6c6b6a696867a2a100850002ff01 (..., -0.01295, ...)
+#                                      ╙───────────── 0xa2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0x0002ff01ff1e191800000000ff00ff01 (2.751e-40, ...)
+#            v23: 0xff00008502201b1a00000000feff0084 (-1.701e+38, ...)
+#            v24: 0x00fffeff23221d1c1700000000ff0085 (2.351e-38, ...)
+#                          ╙───────────────────────── 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.149e-15, ...)
+#            v31: 0x00000000aaa9a8a7969594939291908f (..., -3.014e-13, ...)
+#             v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.898e-11, ...)
+#                                  ╙───────────────── 0xaeadacab'aaa9a8a7'a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000a5a4a3a24744413e (..., -2.856e-16, ...)
+#            v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.490e-14, ...)
+#            v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.963e-11, ...)
+#                                          ╙───────── 0xadacabaa'a9a8a7a6'a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v24: 0x01010101010101010101010101010101
+#            v25: 0xffffffffffffffffffffffffffffffff
+#            v26: 0x02020202020202020202020202020202
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#            v25: 0xafafafafafafafafafafafafafafafaf
+#            v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v3: 0xadadadadadadadadadadadadadadadad
+#             v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#             v5: 0xafafafafafafafafafafafafafafafaf
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01 (-5.487e+303)
+#             d5:                 0x0000000000fffeff (8.289e-317)
+#             d6:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xb7b6b5b4b3b2b1b0 (-2.607e-40)
+#             d8:                 0xbfbebdbcbbbab9b8 (-0.1201)
+#             d9:                 0xc7c6c5c4c3c2c1c0 (-6.054e+37)
+#                                                  ╙─ 0xc7c6c5c4c3c2c1c0'bfbebdbcbbbab9b8'b7b6b5b4b3b2b1b0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xb6b5b4b3b2b1b0af (-3.802e-45)
+#            d18:                 0xbebdbcbbbab9b8b7 (-1.772e-06)
+#            d19:                 0xc6c5c4c3c2c1c0bf (-8.830e+32)
+#                                                  ╙─ 0xc6c5c4c3c2c1c0bf'bebdbcbbbab9b8b7'b6b5b4b3b2b1b0af <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v17: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v18: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#                                  ╙───────────────╨─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.113e+71, -4.113e+71)
+#            v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.051e+110, -2.051e+110)
+#            v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.546e+148, -9.546e+148)
+#                                  ╙───────────────╨─ 0xdedddcdbdad9d8d7'd6d5d4d3d2d1d0cf'cecdcccbcac9c8c7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.065e+66, -6.065e+66)
+#            v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.985e+105, -2.985e+105)
+#            v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.408e+144, -1.408e+144)
+#                                  ╙───────────────╨─ 0xdddcdbdad9d8d7d6'd5d4d3d2d1d0cfce'cdcccbcac9c8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d11:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#            d12:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#                                          ╙───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#             d1:                 0xe5e4e3e2e5e4e3e2 (-1.351e+23, -1.351e+23)
+#             d2:                 0xe9e8e7e6e9e8e7e6 (-3.520e+25, -3.520e+25)
+#                                          ╙───────╨─ 0xe9e8e7e6'e5e4e3e2'e1e0dfde <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#            d24:                 0xe4e3e2e1e4e3e2e1 (-3.363e+22, -3.363e+22)
+#            d25:                 0xe8e7e6e5e8e7e6e5 (-8.761e+24, -8.761e+24)
+#                                          ╙───────╨─ 0xe8e7e6e5'e4e3e2e1'e0dfdedd <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d23:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d24:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                                      ╙───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0xeae9eae9eae9eae9 (-3538., -3538., -3538., -3538.)
+#             d7:                 0xecebecebecebeceb (-5036., -5036., -5036., -5036.)
+#             d8:                 0xeeedeeedeeedeeed (-7092., -7092., -7092., -7092.)
+#                                      ╙───╨───╨───╨─ 0xeeed'eceb'eae9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xe9e8e9e8e9e8e9e8 (-3024., -3024., -3024., -3024.)
+#             d8:                 0xebeaebeaebeaebea (-4052., -4052., -4052., -4052.)
+#             d9:                 0xedecedecedecedec (-6064., -6064., -6064., -6064.)
+#                                      ╙───╨───╨───╨─ 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v27: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v28: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#                          ╙───────╨───────╨───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (-2.386e+30, -2.386e+30, -2.386e+30, -2.386e+30)
+#             v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (-6.210e+32, -6.210e+32, -6.210e+32, -6.210e+32)
+#             v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (-1.616e+35, -1.616e+35, -1.616e+35, -1.616e+35)
+#                          ╙───────╨───────╨───────╨─ 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (-5.940e+29, -5.940e+29, -5.940e+29, -5.940e+29)
+#            v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (-1.546e+32, -1.546e+32, -1.546e+32, -1.546e+32)
+#             v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (-4.023e+34, -4.023e+34, -4.023e+34, -4.023e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x0101010101010101
+#             d3:                 0xffffffffffffffff
+#             d4:                 0x0202020202020202
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xf9f9f9f9f9f9f9f9
+#            d11:                 0xfafafafafafafafa
+#            d12:                 0xfbfbfbfbfbfbfbfb
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfb'fa'f9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v7: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#             v8: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#             v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v9: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xfffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v3: 0x3c3834302c2824201c18000000ff8501
+#             v4: 0x3d3935312d2925211d19000000fe00ff
+#             v5: 0x3e3a36322e2a26221e1a000000ff0002
+#             v6: 0x3f3b37332f2b27231f1b17000000ff00
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x3c3834302c2824201c1814100c080400
+#             v3: 0x3d3935312d2925211d1915110d090501
+#             v4: 0x3e3a36322e2a26221e1a16120e0a0602
+#             v5: 0x3f3b37332f2b27231f1b17130f0b0703
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x03'02'01'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x07'06'05'04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0b'0a'09'08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0f'0e'0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x13'12'11'10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'16'15'14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3b37332f2b27231f1b17130f0b0703ff
+#             v6: 0x3c3834302c2824201c1814100c080400
+#             v7: 0x3d3935312d2925211d1915110d090501
+#             v8: 0x3e3a36322e2a26221e1a16120e0a0602
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1e'1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22'21'20'1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x26'25'24'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a'29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2e'2d'2c'2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x32'31'30'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x36'35'34'33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3a'39'38'37 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3e'3d'3c'3b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2726252423222120ff0000850002ff01 (4.288e-120, -5.487e+303)
+#            v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.988e-81, 8.289e-317)
+#            v20: 0x37363534333231301700000000000000 (9.958e-43, 6.689e-198)
+#            v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.0004614, 8.568e-159)
+#                                  ║               ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938'3736353433323130'2f2e2d2c2b2a2928'2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x666564636261605f464544434241403f (1.818e+185, 3.370e+30)
+#             v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.509e+223, 1.580e+69)
+#             v6: 0x767574737271706f565554535251504f (4.222e+262, 7.827e+107)
+#             v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.975e+301, 3.666e+146)
+#                                  ║               ╙─ 0x5e5d5c5b5a595857'565554535251504f'4e4d4c4b4a494847'464544434241403f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7e7d7c7b7a797877'767574737271706f'6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x6564636261605f5e4544434241403f3e (2.644e+180, 4.899e+25)
+#            v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.254e+219, 2.328e+64)
+#            v31: 0x7574737271706f6e5554535251504f4e (6.141e+257, 1.138e+103)
+#             v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.911e+296, 5.403e+141)
+#                                  ║               ╙─ 0x5d5c5b5a59585756'5554535251504f4e'4d4c4b4a49484746'4544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7d7c7b7a79787776'7574737271706f6e'6d6c6b6a69686766'6564636261605f5e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x000000000002ff01 (0.000, 2.751e-40)
+#            d28:                 0x17000000ff000085 (4.136e-25, -1.701e+38)
+#            d29:                 0x1b1a191800fffeff (1.275e-22, 2.351e-38)
+#            d30:                 0x1f1e1d1c00000000 (3.348e-20, 0.000)
+#                                          ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x91908f8e81807f7e (-2.281e-28, -4.720e-38)
+#            d25:                 0x9594939285848382 (-6.001e-26, -1.246e-35)
+#            d26:                 0x9998979689888786 (-1.578e-23, -3.287e-33)
+#            d27:                 0x9d9c9b9a8d8c8b8a (-4.145e-21, -8.662e-31)
+#                                          ║       ╙─ 0x8d8c8b8a'89888786'85848382'81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9d9c9b9a'99989796'95949392'91908f8e <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x908f8e8d807f7e7d (-5.662e-29, -1.171e-38)
+#             d5:                 0x9493929184838281 (-1.490e-26, -3.092e-36)
+#             d6:                 0x9897969588878685 (-3.918e-24, -8.157e-34)
+#             d7:                 0x9c9b9a998c8b8a89 (-1.030e-21, -2.150e-31)
+#                                          ║       ╙─ 0x8c8b8a89'88878685'84838281'807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99'98979695'94939291'908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d16:                 0x19180000feffff01 (0.002487, 0.000, nan, nan)
+#            d17:                 0x1b1a000000ff0002 (0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            d18:                 0x1d1c000000000085 (0.004990, 0.000, 0.000, 7.927e-06)
+#            d19:                 0x1f1e17000000ff00 (0.006950, 0.001709, 0.000, nan)
+#                                      ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xb6b5aeada6a59e9d (-0.4192, -0.1043, -0.02596, -0.006458)
+#            d24:                 0xb8b7b0afa8a7a09f (-0.5894, -0.1464, -0.03635, -0.009026)
+#            d25:                 0xbab9b2b1aaa9a2a1 (-0.8403, -0.2091, -0.05203, -0.01295)
+#            d26:                 0xbcbbb4b3acaba4a3 (-1.183, -0.2937, -0.07294, -0.01811)
+#                                      ║   ║   ║   ╙─ 0xa4a3'a2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xacab'aaa9'a8a7'a6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb4b3'b2b1'b0af'aead <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbcbb'bab9'b8b7'b6b5 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xb5b4adaca5a49d9c (-0.3564, -0.08862, -0.02203, -0.005478)
+#             d3:                 0xb7b6afaea7a69f9e (-0.4819, -0.1200, -0.02988, -0.007439)
+#             d4:                 0xb9b8b1b0a9a8a1a0 (-0.7148, -0.1777, -0.04419, -0.01099)
+#             d5:                 0xbbbab3b2abaaa3a2 (-0.9658, -0.2405, -0.05988, -0.01491)
+#                                      ║   ║   ║   ╙─ 0xa3a2'a1a0'9f9e'9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xabaa'a9a8'a7a6'a5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb3b2'b1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba'b9b8'b7b6'b5b4 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x3332313023222120000000000002ff01 (4.149e-08, 8.789e-18, 0.000, 2.751e-40)
+#             v8: 0x373635342726252417000000ff000085 (1.086e-05, 2.306e-15, 4.136e-25, -1.701e+38)
+#             v9: 0x3b3a39382b2a29281b1a191800fffeff (0.002842, 6.045e-13, 1.275e-22, 2.351e-38)
+#            v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.7431, 1.584e-10, 3.348e-20, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2f2e2d2c'2b2a2928'27262524'23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534'33323130 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#            v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.850e+31, -8.370e+21, -1.811e+12, -389.5)
+#            v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.002e+34, -2.181e+24, -4.724e+14, -1.018e+05)
+#            v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.606e+36, -5.680e+26, -1.232e+17, -2.658e+07)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.682e+28, -7.993e+18, -1.726e+09, -0.3706)
+#            v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.584e+30, -2.083e+21, -4.506e+11, -96.88)
+#            v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.494e+33, -5.428e+23, -1.176e+14, -2.531e+04)
+#             v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.490e+35, -1.414e+26, -3.066e+16, -6.612e+06)
+#                          ║       ║       ║       ╙─ 0xcac9c8c7'c6c5c4c3'c2c1c0bf'bebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdad9d8d7'd6d5d4d3'd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xeae9e8e7'e6e5e4e3'e2e1e0df'dedddcdb <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfaf9f8f7'f6f5f4f3'f2f1f0ef'eeedeceb <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d15:                 0x1c18000000ff8501
+#            d16:                 0x1d19000000fe00ff
+#            d17:                 0x1e1a000000ff0002
+#            d18:                 0x1f1b17000000ff00
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x17130f0b0703fffb
+#            d28:                 0x1814100c080400fc
+#            d29:                 0x1915110d090501fd
+#            d30:                 0x1a16120e0a0602fe
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfe'fd'fc'fb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x16120e0a0602fefa
+#             d6:                 0x17130f0b0703fffb
+#             d7:                 0x1814100c080400fc
+#             d8:                 0x1915110d090501fd
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfd'fc'fb'fa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x01'00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x05'04'03'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x09'08'07'06 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0d'0c'0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x11'10'0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14'13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x19'18'17'16 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831302928212019180000feffff01 (0.6523, 0.1621, 0.04028, 0.01001, 0.002487, 0.000, nan, nan)
+#            v26: 0x3b3a33322b2a23221b1a000000ff0002 (0.9033, 0.2249, 0.05597, 0.01393, 0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            v27: 0x3d3c35342d2c25241d1c000000000085 (1.309, 0.3252, 0.08081, 0.02008, 0.004990, 0.000, 0.000, 7.927e-06)
+#            v28: 0x3f3e37362f2e27261f1e17000000ff00 (1.811, 0.4507, 0.1122, 0.02792, 0.006950, 0.001709, 0.000, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726'2524'2322'2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2f2e'2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3736'3534'3332'3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e'3d3c'3b3a'3938 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x53524b4a43423b3a33322b2a23221b1a (58.56, 14.58, 3.629, 0.9033, 0.2249, 0.05597, 0.01393, 0.003468)
+#             v3: 0x55544d4c45443d3c35342d2c25241d1c (85.25, 21.19, 5.266, 1.309, 0.3252, 0.08081, 0.02008, 0.004990)
+#             v4: 0x57564f4e47463f3e37362f2e27261f1e (117.4, 29.22, 7.273, 1.811, 0.4507, 0.1122, 0.02792, 0.006950)
+#             v5: 0x59585150494841403938313029282120 (171.0, 42.50, 10.56, 2.625, 0.6523, 0.1621, 0.04028, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120'1f1e'1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2928'2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3130'2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3938'3736'3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4140'3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948'4746'4544'4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5150'4f4e'4d4c'4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5958'5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2922211a19 (50.53, 12.57, 3.127, 0.7778, 0.1935, 0.04813, 0.01197, 0.002977)
+#            v21: 0x54534c4b44433c3b34332c2b24231c1b (69.19, 17.17, 4.262, 1.058, 0.2625, 0.06512, 0.01616, 0.004009)
+#            v22: 0x56554e4d46453e3d36352e2d26251e1d (101.3, 25.20, 6.270, 1.560, 0.3879, 0.09650, 0.02400, 0.005970)
+#            v23: 0x5857504f4847403f3837302f2827201f (138.9, 34.47, 8.555, 2.123, 0.5269, 0.1307, 0.03244, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f'1e1d'1c1b'1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2827'2625'2423'2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x302f'2e2d'2c2b'2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3837'3635'3433'3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x403f'3e3d'3c3b'3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847'4645'4443'4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x504f'4e4d'4c4b'4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5857'5655'5453'5251 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2901211a19
+#            v21: 0x54534c4b44433c3b34332c2bff231c1b
+#            v22: 0x56554e4d46453e3d36352e2d02251e1d
+#            v23: 0x5857504f4847403f3837302f0027201f
+#                                            ╙─────── 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000fbfbfbfb59fbfbfb
+#            v13: 0x81807b7a75746f6ea9a8a7a65a5c5756
+#            v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6
+#            v15: 0x00000000000000001c1800005cff8501
+#                                            ╙─────── 0x5c'5b'5a'59 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v27: 0x3d3c35342d2c25241d58000000000085
+#            v28: 0x3f3e37362f2e27261f5917000000ff00
+#            v29: 0x0000000000000000195a110d090501fd
+#            v30: 0x00000000000000001a5b120e0a0602fe
+#                                      ╙───────────── 0x5b'5a'59'58 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff0000850002ff011f5917000000ff00 (-5.487e+303, ...)
+#            v29: 0x0000000000fffeff195a110d090501fd (8.289e-317, ...)
+#            v30: 0x17000000000000001a5b120e0a0602fe (6.689e-198, ...)
+#            v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.568e-159, ...)
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x636261605f5e5d5c1c1800005cff8501 (5.549e+170, ...)
+#            v16: 0x6b6a6968676665641d19000000fe00ff (2.713e+209, ...)
+#            v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.290e+248, ...)
+#            v18: 0x7b7a7978777675741f1b17000000ff00 (6.299e+286, ...)
+#                                  ╙───────────────── 0x7b7a797877767574'737271706f6e6d6c'6b6a696867666564'636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.005e+165, ...)
+#            v17: 0x6a696867666564631e1a000000ff0002 (3.983e+204, ...)
+#            v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.861e+243, ...)
+#            v19: 0x7a797877767574731f1e17000000ff00 (9.247e+281, ...)
+#                                  ╙───────────────── 0x7a79787776757473'7271706f6e6d6c6b'6a69686766656463'6261605f5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v2: 0x5352ff0143423b3a33322b2a23221b1a (..., nan, ...)
+#             v3: 0x5554000245443d3c35342d2c25241d1c (..., 1.192e-07, ...)
+#             v4: 0x5756008547463f3e37362f2e27261f1e (..., 7.927e-06, ...)
+#             v5: 0x5958ff00494841403938313029282120 (..., nan, ...)
+#                          ╙───────────────────────── 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5958ff00494841407c7b313029282120 (..., nan, ...)
+#             v6: 0x00000000000000007e7d0f0b0703fffb (..., nan, ...)
+#             v7: 0x0000000000000000807f100c080400fc (..., -7.570e-06, ...)
+#             v8: 0x00000000000000008281110d090501fd (..., -3.821e-05, ...)
+#                                      ╙───────────── 0x8281'807f'7e7d'7c7b <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v7: 0x00007b7a00000000807f100c080400fc (..., 6.125e+04, ...)
+#             v8: 0x00007d7c000000008281110d090501fd (..., nan, ...)
+#             v9: 0x3b3a7f7e2b2a29281b1a191800fffeff (..., nan, ...)
+#            v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 (..., -2.289e-05, ...)
+#                          ╙───────────────────────── 0x8180'7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v6: 0x00000000000000000002ff010703fffb (..., 2.751e-40, ...)
+#             v7: 0x00007b7a00000000ff000085080400fc (..., -1.701e+38, ...)
+#             v8: 0x00007d7c0000000000fffeff090501fd (..., 2.351e-38, ...)
+#             v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.000, ...)
+#                                          ╙───────── 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831308584838219180000feffff01 (..., -1.246e-35, ...)
+#            v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.287e-33, ...)
+#            v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.662e-31, ...)
+#            v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.281e-28, ...)
+#                                  ╙───────────────── 0x91908f8e'8d8c8b8a'89888786'85848382 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v8: 0x848382810000000000fffeff090501fd (-3.092e-36, ...)
+#             v9: 0x888786852b2a29280000000000fffeff (-8.157e-34, ...)
+#            v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.150e-31, ...)
+#            v11: 0x908f8e8d00000000fafafafafafafafa (-5.662e-29, ...)
+#                          ╙───────────────────────── 0x908f8e8d'8c8b8a89'88878685'84838281 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v14: 0x01010101010101010101010101010101
+#            v15: 0xffffffffffffffffffffffffffffffff
+#            v16: 0x02020202020202020202020202020202
+#            v17: 0x00000000000000000000000000000000
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x91919191919191919191919191919191
+#            v14: 0x92929292929292929292929292929292
+#            v15: 0x93939393939393939393939393939393
+#            v16: 0x94949494949494949494949494949494
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x94'93'92'91 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             v9: 0x90909090909090909090909090909090
+#            v10: 0x91919191919191919191919191919191
+#            v11: 0x92929292929292929292929292929292
+#            v12: 0x93939393939393939393939393939393
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x93'92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xff0000850002ff01 (-5.487e+303)
+#             d9:                 0x0000000000fffeff (8.289e-317)
+#            d10:                 0x1700000000000000 (6.689e-198)
+#            d11:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x9b9a999897969594 (-1.050e-175)
+#             d5:                 0xa3a2a1a09f9e9d9c (-5.007e-137)
+#             d6:                 0xabaaa9a8a7a6a5a4 (-2.438e-98)
+#             d7:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac'abaaa9a8a7a6a5a4'a3a2a1a09f9e9d9c'9b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x9a99989796959493 (-1.542e-180)
+#            d27:                 0xa2a1a09f9e9d9c9b (-7.228e-142)
+#            d28:                 0xaaa9a8a7a6a5a4a3 (-3.580e-103)
+#            d29:                 0xb2b1b0afaeadacab (-1.680e-64)
+#                                                  ╙─ 0xb2b1b0afaeadacab'aaa9a8a7a6a5a4a3'a2a1a09f9e9d9c9b'9a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v20: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v21: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#            v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.568e-159, 8.568e-159)
+#                                  ╙───────────────╨─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.311e-26, -8.311e-26)
+#            v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.904e+13, -3.904e+13)
+#            v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.929e+52, -1.929e+52)
+#            v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.073e+90, -9.073e+90)
+#                                  ╙───────────────╨─ 0xd2d1d0cfcecdcccb'cac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.219e-30, -1.219e-30)
+#            v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.620e+08, -5.620e+08)
+#            v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.829e+47, -2.829e+47)
+#            v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.306e+86, -1.306e+86)
+#                                  ╙───────────────╨─ 0xd1d0cfcecdcccbca'c9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#             d0:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#             d1:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#             d2:                 0x0000000000000000 (0.000, 0.000)
+#                                          ╙───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xd5d4d3d2d5d4d3d2 (-2.925e+13, -2.925e+13)
+#            d29:                 0xd9d8d7d6d9d8d7d6 (-7.629e+15, -7.629e+15)
+#            d30:                 0xdddcdbdadddcdbda (-1.989e+18, -1.989e+18)
+#            d31:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#                                          ╙───────╨─ 0xe1e0dfde'dddcdbda'd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xd4d3d2d1d4d3d2d1 (-7.278e+12, -7.278e+12)
+#            d12:                 0xd8d7d6d5d8d7d6d5 (-1.899e+15, -1.899e+15)
+#            d13:                 0xdcdbdad9dcdbdad9 (-4.951e+17, -4.951e+17)
+#            d14:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#                                          ╙───────╨─ 0xe0dfdedd'dcdbdad9'd8d7d6d5'd4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d20:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d21:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            d22:                 0xff00ff00ff00ff00 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xe2e1e2e1e2e1e2e1 (-880.5, -880.5, -880.5, -880.5)
+#            d23:                 0xe4e3e4e3e4e3e4e3 (-1251., -1251., -1251., -1251.)
+#            d24:                 0xe6e5e6e5e6e5e6e5 (-1765., -1765., -1765., -1765.)
+#            d25:                 0xe8e7e8e7e8e7e8e7 (-2510., -2510., -2510., -2510.)
+#                                      ╙───╨───╨───╨─ 0xe8e7'e6e5'e4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xe1e0e1e0e1e0e1e0 (-752.0, -752.0, -752.0, -752.0)
+#            d21:                 0xe3e2e3e2e3e2e3e2 (-1009., -1009., -1009., -1009.)
+#            d22:                 0xe5e4e5e4e5e4e5e4 (-1508., -1508., -1508., -1508.)
+#            d23:                 0xe7e6e7e6e7e6e7e6 (-2022., -2022., -2022., -2022.)
+#                                      ╙───╨───╨───╨─ 0xe7e6'e5e4'e3e2'e1e0 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v16: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v17: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v18: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#            v19: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ╙───────╨───────╨───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (-5.680e+26, -5.680e+26, -5.680e+26, -5.680e+26)
+#            v26: 0xefeeedecefeeedecefeeedecefeeedec (-1.479e+29, -1.479e+29, -1.479e+29, -1.479e+29)
+#            v27: 0xf3f2f1f0f3f2f1f0f3f2f1f0f3f2f1f0 (-3.850e+31, -3.850e+31, -3.850e+31, -3.850e+31)
+#            v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (-1.002e+34, -1.002e+34, -1.002e+34, -1.002e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf7f6f5f4'f3f2f1f0'efeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (-1.414e+26, -1.414e+26, -1.414e+26, -1.414e+26)
+#            v24: 0xeeedecebeeedecebeeedecebeeedeceb (-3.682e+28, -3.682e+28, -3.682e+28, -3.682e+28)
+#            v25: 0xf2f1f0eff2f1f0eff2f1f0eff2f1f0ef (-9.584e+30, -9.584e+30, -9.584e+30, -9.584e+30)
+#            v26: 0xf6f5f4f3f6f5f4f3f6f5f4f3f6f5f4f3 (-2.494e+33, -2.494e+33, -2.494e+33, -2.494e+33)
+#                          ╙───────╨───────╨───────╨─ 0xf6f5f4f3'f2f1f0ef'eeedeceb'eae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x0101010101010101
+#            d23:                 0xffffffffffffffff
+#            d24:                 0x0202020202020202
+#            d25:                 0x0000000000000000
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xf7f7f7f7f7f7f7f7
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8'f7 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xf6f6f6f6f6f6f6f6
+#            d30:                 0xf7f7f7f7f7f7f7f7
+#            d31:                 0xf8f8f8f8f8f8f8f8
+#             d0:                 0xf9f9f9f9f9f9f9f9
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xf9'f8'f7'f6 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v29: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            v30: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            v31: 0xff00ff00ff00ff00ff00ff00ff00ff00 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#            v26: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v27: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v28: 0x01000100010001000100010001000100 (1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05, 1.526e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0100'fffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v22: 0xfaf9faf9faf9faf9faf9faf9faf9faf9 (-5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04, -5.712e+04)
+#            v23: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v24: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v25: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#             x1: 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0002000200020002e73aed42f34af952
+#             v6: 0x0000000000000000dcbb11e0e6481e68
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+#       p8<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#      p8<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p8<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#       p9<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#      p9<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p9<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p10<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#     p10<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p10<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#      p11<15:0>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<31:16>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 <- 0x~~~~~~~~~~~~~~~~
+#     p11<47:32>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<63:48>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     p11<79:64>: 0b 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x7f000000008000000000000000000000
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ╙───────────────────── 0x80 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x7f <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x2f000000000029000000000023000000
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ║   ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ║   ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ║ ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║   ╙─────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x0d0c0b0a09080706050403020100fffe (0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 (...)
+#
+#   z21<639:512>: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x7f800000000000000000000000000000 (inf, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x7f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (...)
+#
+#   z22<511:384>: 0x2f2e0000000000000000000023220000 (1.583e-10, ..., 0.000, 8.782e-18)
+#                          ║               ║       ╙─ 0x23220000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e0000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (...)
+#
+#   z23<511:384>: 0x00000000000000000000000023220000 (..., 2.912e-315)
+#                                                  ╙─ 0x0000000023220000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#                          ║   ║       ║   ║       ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000230022000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x0000000000000000000000000000007f
+#                                  ║               ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x000000000000002f0000290000230000
+#   z21<255:128>: 0x00000000000000002e00000000002200
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x22'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x2e'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x0000007f007f00000000000000000000
+#   z21<383:256>: 0x00000000800000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x80'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<511:384>: 0x00000000000000000000000000000000
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#     z22<127:0>: 0x000000007f807f800000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#     z23<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f800000'7f800000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#     z24<127:0>: 0x00000000000000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'7f8000007f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z24<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x0000000000000000000000ff00000000
+#     z25<127:0>: 0xa000000000000000000000ffc0000000
+#     z26<127:0>: 0x3700000000000000000000007f000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x7f'c0'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'ff'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x37'a0'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<639:512>: 0x00000000000000000000000000000000
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z25<127:0>: 0x292823221d1c17160000000000000000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z26<127:0>: 0x2b2a25241f1e191813120d0c07060100 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0100'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0908'0706'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0d0c'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514'1312'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1b1a'1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2120'1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x595853524d4c474641403b3a35342f2e (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
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+#   z27<255:128>: 0x5d5c575651504b4a45443f3e39383332 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3332'3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3938'3736'3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544'4342'4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4b4a'4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5150'4f4e'4d4c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c'5b5a'5958 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x898883827d7c777671706b6a65645f5e (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z26<383:256>: 0x8b8a85847f7e797873726d6c67666160 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x6362'6160'5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6968'6766'6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6f6e'6d6c'6b6a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x7574'7372'7170 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7b7a'7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x8180'7f7e'7d7c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x8786'8584'8382 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8d8c'8b8a'8988 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x9392'9190'8f8e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x9998'9796'9594 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x9f9e'9d9c'9b9a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xa5a4'a3a2'a1a0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xabaa'a9a8'a7a6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xb1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xb7b6'b5b4'b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xbdbc'bbba'b9b8 <- 0x~~~~~~~~~~~~~~~~
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+#   z27<639:512>: 0xedece7e6e1e0dbdad5d4cfcec9c8c3c2 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xc3c2'c1c0'bfbe <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xc9c8'c7c6'c5c4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xcfce'cdcc'cbca <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd5d4'd3d2'd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xdbda'd9d8'd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xe1e0'dfde'dddc <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xe7e6'e5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#     z26<127:0>: 0x00000000000000000000ffff00000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z27<127:0>: 0x00000000000000007fff000000000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z28<127:0>: 0x37a0000000000000000000007fc00000 (0.000, 0.000, 9.183e-41, 0.000)
+#                          ║       ║       ║       ╙─ 0x7fc00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'7fff0000'0000ffff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x37a00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z27<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000ffff7fc00000 (0.000, 0.000)
+#     z29<127:0>: 0x37a0000000000000000000007fff0000 (0.000, 0.000)
+#                                  ║               ╙─ 0x000000007fff0000'0000ffff7fc00000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x37a0000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z25<127:0>: 0x0000000000000000000000f300000000
+#     z26<127:0>: 0x00000000000000000000000400000000
+#     z27<127:0>: 0x0080000000800000000000ff00000000
+#     z28<127:0>: 0x007f0000007f0000000000ff00000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0xff'ff'04'f3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#   z27<255:128>: 0x00000000000000000000000000000000
+#   z28<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#   z27<383:256>: 0x00000000000000000000000000000000
+#   z28<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#   z27<511:384>: 0x00000000000000000000000000000000
+#   z28<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#   z27<639:512>: 0x00000000000000000000000000000000
+#   z28<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z26<127:0>: 0x00000000000000003fb504f300000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z27<127:0>: 0x7f8000007f800000ffffffff00000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#     z29<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 1.927, 7.552e-05, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'ffff'04f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'ffff'3fb5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#     z27<127:0>: 0x2f2e2d2c000000000000000000000000 (1.584e-10, 0.000, 0.000, 0.000)
+#     z28<127:0>: 0x33323130000000007f80000000000000 (1.584e-10, 0.000, 0.000, 0.000)
+#     z29<127:0>: 0x00000000000000000000000007060504 (1.584e-10, 0.000, 0.000, 0.000)
+#     z30<127:0>: 0x00000000000000007f8000000b0a0908 (1.584e-10, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7f800000'00000000'7f800000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z29<255:128>: 0x00000000000000005756555400000000 (0.000, 0.000, 0.000, 0.000)
+#   z30<255:128>: 0x00000000000000005b5a595800000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5b5a5958'57565554'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<383:256>: 0xafaeadac9f9e9d9c8f8e8d8c7f7e7d7c (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z28<383:256>: 0xb3b2b1b0a3a2a1a09392919083828180 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z29<383:256>: 0xb7b6b5b4a7a6a5a49796959487868584 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#   z30<383:256>: 0xbbbab9b8abaaa9a89b9a99988b8a8988 (-3.177e-10, -6.718e-20, -1.406e-29, 3.383e+38)
+#                          ║       ║       ║       ╙─ 0x8b8a8988'87868584'83828180'7f7e7d7c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x9b9a9998'97969594'93929190'8f8e8d8c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xabaaa9a8'a7a6a5a4'a3a2a1a0'9f9e9d9c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xbbbab9b8'b7b6b5b4'b3b2b1b0'afaeadac <- 0x~~~~~~~~~~~~~~~~
+#   z27<511:384>: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z28<511:384>: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z29<511:384>: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#   z30<511:384>: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#   z27<639:512>: 0x2f2e2d2c1f1e1d1c0f0e0d0cfffefdfc (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z28<639:512>: 0x33323130232221201312111003020100 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z29<639:512>: 0x37363534272625241716151407060504 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#   z30<639:512>: 0x3b3a39382b2a29281b1a19180b0a0908 (1.584e-10, 3.348e-20, 7.004e-30, nan)
+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'03020100'fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1b1a1918'17161514'13121110'0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928'27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3b3a3938'37363534'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#     z28<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z29<127:0>: 0x000000007f8000000000000000000000 (0.000, 0.000)
+#     z30<127:0>: 0x000000000000000000000000ffff04f3 (0.000, 0.000)
+#     z31<127:0>: 0x000000007f80000000000000ffff3fb5 (0.000, 0.000)
+#                                  ║               ╙─ 0x00000000ffff3fb5'00000000ffff04f3'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x000000007f800000'0000000000000000'000000007f800000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z30<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z31<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
diff --git a/test/test-trace-reference/log-sysregs b/test/test-trace-reference/log-sysregs
index 7f3fa5ed..5ab304ff 100644
--- a/test/test-trace-reference/log-sysregs
+++ b/test/test-trace-reference/log-sysregs
@@ -35,14 +35,14 @@
 # NZCV: N:0 Z:1 C:1 V:0
 # NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:0 V:0
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:0
 # NZCV: N:0 Z:1 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 # NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 # NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:0
 # NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:1 C:1 V:0
diff --git a/test/test-trace-reference/log-sysregs-colour b/test/test-trace-reference/log-sysregs-colour
index f2ee4def..50a79a30 100644
--- a/test/test-trace-reference/log-sysregs-colour
+++ b/test/test-trace-reference/log-sysregs-colour
@@ -35,14 +35,14 @@
 # NZCV: N:0 Z:1 C:1 V:0
 # NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:0 V:0
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:0
 # NZCV: N:0 Z:1 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 # NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:0
+# NZCV: N:0 Z:0 C:1 V:1
 # NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:0 C:1 V:0
 # NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:0
-# NZCV: N:0 Z:0 C:1 V:1
+# NZCV: N:1 Z:0 C:0 V:0
 # NZCV: N:0 Z:1 C:1 V:0
diff --git a/test/test-trace-reference/log-vregs b/test/test-trace-reference/log-vregs
index 11b2de91..60df96af 100644
--- a/test/test-trace-reference/log-vregs
+++ b/test/test-trace-reference/log-vregs
@@ -1,2304 +1,5371 @@
-#    v0: 0x00055555005555550000000000000000
-#    v1: 0x3ff0d2c63fcb514c3ff587933f9e0419
-#    v2: 0x4000d2c6404b514c40058793401e0419
-#    v3: 0x401570fb40385373401025ae406d0626
-#    v4: 0x4010d2c640cb514c40158793409e0419
-#    v5: 0x401fbc2d4090d04a401ae97840c5851f
-#    v6: 0x402570fb40b85373402025ae40ed0626
-#    v7: 0x402783f4415f16c34022d6a1410a4396
-#    v8: 0x4020d2c6414b514c40258793411e0419
-#    v9: 0x402d6dd3416491c9402838864131c49c
-#   v10: 0x402fbc2d4110d04a402ae9784145851f
-#   v11: 0x4028cf3e410c10f7402d9a6b415945a2
-#   v12: 0x403570fb41385373403025ae416d0626
-#   v13: 0x40342b7d41d5360140317e2841806354
-#   v14: 0x403783f441df16c34032d6a1418a4396
-#   v15: 0x40317a4f41c1768240342f1a419423d7
-#   v16: 0x4030d2c641cb514c40358793419e0419
-#   v17: 0x4033b55841f2b10e4036e00d41a7e45b
-#   v18: 0x403d6dd341e491c94038388641b1c49c
-#   v19: 0x403cc5aa41eef18b403990ff41bba4de
-#   v20: 0x403fbc2d4190d04a403ae97841c5851f
-#   v21: 0x403914a7419a3034403c41f241cf6561
-#   v22: 0x4038cf3e418c10f7403d9a6b41d945a2
-#   v23: 0x403ba7b141b670b1403ef2e441e325e4
-#   v24: 0x404570fb41b85373404025ae41ed0626
-#   v25: 0x404584be41a3b3324040d1eb41f6e667
-#   v26: 0x40442b7d4255360140417e2842006354
-#   v27: 0x40477f314250062040422a6442055375
-#   v28: 0x404783f4425f16c34042d6a1420a4396
-#   v29: 0x4046d78b425a66e2404382de420f33b7
-#   v30: 0x40417a4f4241768240442f1a421423d7
-#   v31: 0x40418e02424c46ad4044db57421913f8
-#   v13: 0x00000000000000004036e00cd9b7e45b
-#    v8: 0x00000000000000000000000041c5851e
-#    v1: 0x00000000000000003ff587933f9e0419 (d1: 1.34560)
-#   v25: 0x000000000000000000000000410a4396 (s25: 8.64150)
-#    v1: 0x0000000000000000ffffffffffffffff
-#    v4: 0x00000000000000000000000000000000
-#    v2: 0x00000000000000000000000000000000
-#   v12: 0x000000000000000000000000ffffffff
-#   v13: 0x0000000000000000404633d07142f43a (d13: 44.4048)
-#   v27: 0x000000000000000000000000424094fe (s27: 48.1455)
-#   v19: 0x00000000000000000000000000000000
-#    v0: 0x00000000000000000000000000000000
-#    v1: 0x00000000000000000000000000000000
-#   v22: 0x00000000000000000000000000000000
-#   v27: 0x0000000000000000ffffffffffffffff
-#   v31: 0x0000000000000000ffffffffffffffff
-#   v31: 0x00000000000000000000000000000000
-#    v1: 0x000000000000000000000000ffffffff
-#   v18: 0x00000000000000000000000000000000
-#    v3: 0x00000000000000000000000000000000
-#   v11: 0x000000000000000000000000ffffffff
-#   v17: 0x000000000000000000000000ffffffff
-#   v24: 0x00000000000000000000000000000000
-#   v11: 0x00000000000000000000000000000000
-#    v5: 0x00000000000000000000000000000000
-#   v18: 0x00000000000000000000000000000000
-#   v10: 0x00000000000000000000000000000000 (d10: 0.00000)
-#   v22: 0x00000000000000000000000000000000 (s22: 0.00000)
-#    v4: 0x00000000000000000000000000000000 (d4: 0.00000)
-#   v11: 0x00000000000000000000000000000000 (d11: 0.00000)
-#    v8: 0x00000000000000000000000000004a0e
-#   v12: 0x0000000000000000000000000000ffff
-#   v12: 0x00000000000000000000000000000000 (s12: 0.00000)
-#   v27: 0x0000000000000000000000004072c000 (s27: 3.79297)
-#   v28: 0x00000000000000000000000000000016
-#    v3: 0x00000000000000000000000000000000
-#   v14: 0x00000000000000000000000000000000
-#   v31: 0x00000000000000000000000000000000
-#   v30: 0x00000000000000000000000000000000
-#   v12: 0x00000000000000000000000000000012
-#   v27: 0x00000000000000000000000000000000
-#    v8: 0x00000000000000000000000000000000
-#   v30: 0x00000000000000000000000000000014
-#   v10: 0x00000000000000000000000000000000
-#    v0: 0x0000000000000000000000000000001c
-#    v6: 0x00000000000000000000000000000009
-#   v11: 0x00000000000000000000000000000000
-#   v29: 0x00000000000000000000000000000019
-#   v24: 0x00000000000000000000000000000001
-#   v14: 0x00000000000000000000000000000001
-#   v12: 0x00000000000000000000000000000001
-#   v15: 0x00000000000000000000000000000000
-#   v13: 0x00000000000000000000000000000000
-#    v8: 0x00000000000000000000000000000000
-#   v31: 0x00000000000000000000000000000000
-#   v28: 0x00000000000000000000000000000000
-#    v0: 0x00000000000000000000000000000000
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+#                    ║ ╙───────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfb <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xeb <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xdb <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0x0a09080706050403020100fffefdfcfb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xeb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x3a393837363534333231302f2e2d2c2b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x2a292827262524232221201f1e1d1c1b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x1a191817161514131211100f0e0d0c0b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x393837363534333231302f2e2d2c2b2a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x292827262524232221201f1e1d1c1b1a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x191817161514131211100f0e0d0c0b0a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x595857565554535251504f4e4d4c4b4a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x59 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x494847464544434241403f3e3d3c3b3a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x49 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x5857565554535251504f4e4d4c4b4a49
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x49 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x4847464544434241403f3e3d3c3b3a39
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x6867666564636261605f5e5d5c5b5a59
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x59 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x5a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x5b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x5c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x5d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x5e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x5f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x60 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x61 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x62 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x63 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x64 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x65 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x66 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x67 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x68 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x67666564636261605f5e5d5c5b5a5958
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x59 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x5a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x5b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x5c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x5d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x5e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x5f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x60 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x61 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x62 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x63 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x64 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x65 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x66 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x67 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x7f7e7d7c7b7a7978 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x7776757473727170 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x868584838281807f <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x767574737271706f <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x6e6d6c6b6a696867 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x969594939291908f <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x9d9c9b9a99989796 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x9594939291908f8e <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xadacabaaa9a8a7a6 (-1.126e-88)
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+#                                                  ╙─ 0xacabaaa9a8a7a6a5 <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0xa4a3a2a1a09f9e9d <- 0x~~~~~~~~~~~~~~~~
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+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xb4b3b2b1b0afaead (-8.033e-55)
+#                                                  ╙─ 0xb4b3b2b1b0afaead <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#            v31: 0x3f3e3d3c3b3a39383736353433323130 (0.0004614, 9.958e-43)
+#                                  ║               ╙─ 0x3736353433323130 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x2f2e2d2c2b2a29282726252423222120 (1.988e-81, 4.288e-120)
+#                                  ║               ╙─ 0x2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xf3f2f1f0efeeedecebeae9e8e7e6e5e4 (-3.391e+250, -7.078e+211)
+#                                  ║               ╙─ 0xebeae9e8e7e6e5e4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xf3f2f1f0efeeedec <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xe3e2e1e0dfdedddcdbdad9d8d7d6d5d4 (-1.459e+173, -3.049e+134)
+#                                  ║               ╙─ 0xdbdad9d8d7d6d5d4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe3e2e1e0dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0xd3d2d1d0cfcecdcccbcac9c8c7c6c5c4 (-6.281e+95, -1.314e+57)
+#                                  ║               ╙─ 0xcbcac9c8c7c6c5c4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xd3d2d1d0cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0xc3c2c1c0bfbebdbcbbbab9b8b7b6b5b4 (-2.703e+18, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xc3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0xf2f1f0efeeedecebeae9e8e7e6e5e4e3 (-4.900e+245, -1.040e+207)
+#                                  ║               ╙─ 0xeae9e8e7e6e5e4e3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xf2f1f0efeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0xe2e1e0dfdedddcdbdad9d8d7d6d5d4d3 (-2.109e+168, -4.479e+129)
+#                                  ║               ╙─ 0xdad9d8d7d6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0xd2d1d0cfcecdcccbcac9c8c7c6c5c4c3 (-9.073e+90, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0xc2c1c0bfbebdbcbbbab9b8b7b6b5b4b3 (-3.904e+13, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xc2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.988e-81, 4.288e-120)
+#                                  ║               ╙─ 0x2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2221201f1e1d1c1b1a19181716151413 (2.743e-144, 5.906e-183)
+#                                  ║               ╙─ 0x1a19181716151413 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2221201f1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1211100f0e0d0c0b0a09080706050403 (1.180e-221, 2.544e-260)
+#                                  ║               ╙─ 0x0a09080706050403 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1211100f0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x020100fffefdfcfbfaf9f8f7f6f5f4f3 (5.078e-299, -2.414e+284)
+#                                  ║               ╙─ 0xfaf9f8f7f6f5f4f3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x020100fffefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x21201f1e1d1c1b1a1918171615141312 (3.940e-149, 8.651e-188)
+#                                  ║               ╙─ 0x1918171615141312 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x21201f1e1d1c1b1a <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x11100f0e0d0c0b0a0908070605040302 (1.695e-226, 3.726e-265)
+#                                  ║               ╙─ 0x0908070605040302 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x11100f0e0d0c0b0a <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0100fffefdfcfbfaf9f8f7f6f5f4f3f2 (7.747e-304, -3.541e+279)
+#                                  ║               ╙─ 0xf9f8f7f6f5f4f3f2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0100fffefdfcfbfa <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000 (8.568e-159, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x41403f3e3d3c3b3a3938373635343332 (2.130e+06, 4.664e-33)
+#                                  ║               ╙─ 0x3938373635343332 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x41403f3e3d3c3b3a <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x31302f2e2d2c2b2a2928272625242322 (9.160e-72, 2.009e-110)
+#                                  ║               ╙─ 0x2928272625242322 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x31302f2e2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x403f3e3d3c3b3a393837363534333231 (31.24, 6.821e-38)
+#                                  ║               ╙─ 0x3837363534333231 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x403f3e3d3c3b3a39 <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x302f2e2d2c2b2a292827262524232221 (1.346e-76, 2.938e-115)
+#                                  ║               ╙─ 0x2827262524232221 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x302f2e2d2c2b2a29 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (8.289e-317, -5.487e+303)
+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000fffeff <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x504f4e4d4c4b4a494847464544434241 (7.250e+78, 1.584e+40)
+#                                  ║               ╙─ 0x4847464544434241 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x504f4e4d4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x4f4e4d4c4b4a49484746454443424140 (1.071e+74, 2.313e+35)
+#                                  ║               ╙─ 0x4746454443424140 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x4f4e4d4c4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x1f1e1d1c1b1a1918 (3.348e-20, 1.275e-22)
+#                                          ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x1700000000000000 (4.136e-25, 0.000)
+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x6f6e6d6c6b6a6968 (7.379e+28, 2.834e+26)
+#                                          ║       ╙─ 0x6b6a6968 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x6f6e6d6c <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x63626160 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x67666564 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x5b5a5958 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x5f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x5756555453525150 (2.357e+14, 9.033e+11)
+#                                          ║       ╙─ 0x53525150 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x57565554 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x6a696867 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x666564636261605f (2.708e+23, 1.039e+21)
+#                                          ║       ╙─ 0x6261605f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x66656463 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x5a595857 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x565554535251504f (5.864e+13, 2.247e+11)
+#                                          ║       ╙─ 0x5251504f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x56555453 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x1700000000000000 (4.136e-25, 0.000)
+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x8281807f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x86858483 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x7a797877 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7e7d7c7b <- 0x~~~~~~~~~~~~~~~~
+#             d8:                 0x767574737271706f (1.245e+33, 4.782e+30)
+#                                          ║       ╙─ 0x7271706f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8584838281807f7e (-1.246e-35, -4.720e-38)
+#                                          ║       ╙─ 0x81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x85848382 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x79787776 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7d7c7b7a <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x7574737271706f6e (3.099e+32, 1.191e+30)
+#                                          ║       ╙─ 0x71706f6e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x75747372 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x0000000000fffeff (0.000, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x9594939291908f8e (-6.001e-26, -2.281e-28)
+#                                          ║       ╙─ 0x91908f8e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x95949392 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x8d8c8b8a89888786 (-8.662e-31, -3.287e-33)
+#                                          ║       ╙─ 0x89888786 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8d8c8b8a <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x94939291908f8e8d (-1.490e-26, -5.662e-29)
+#                                          ║       ╙─ 0x908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x94939291 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0x8c8b8a8988878685 (-2.150e-31, -8.157e-34)
+#                                          ║       ╙─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-1.701e+38, 2.751e-40)
+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x9c9b9a9998979695 (-1.030e-21, -3.918e-24)
+#                                          ║       ╙─ 0x98979695 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x9b9a999897969594 (-2.558e-22, -9.731e-25)
+#                                          ║       ╙─ 0x97969594 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9b9a9998 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x1f1e1d1c1b1a1918 (0.006950, 0.004990, 0.003468, 0.002487)
+#                                      ║   ║   ║   ╙─ 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            d18:                 0x1700000000000000 (0.001709, 0.000, 0.000, 0.000)
+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xbbbab9b8b7b6b5b4 (-0.9658, -0.7148, -0.4819, -0.3564)
+#                                      ║   ║   ║   ╙─ 0xb5b4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb7b6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb9b8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xadac <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xafae <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb1b0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb3b2 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xa5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa7a6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa9a8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xabaa <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9f9e <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa1a0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa3a2 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xb4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb6b5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb8b7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbab9 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xacab <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xaead <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb0af <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb2b1 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xa4a3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa8a7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xaaa9 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xa2a1a09f9e9d9c9b (-0.01295, -0.009026, -0.006458, -0.004498)
+#                                      ║   ║   ║   ╙─ 0x9c9b <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa09f <- 0x~~~~~~~~~~~~~~~~
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+#             d0:                 0x1700000000000000 (0.001709, 0.000, 0.000, 0.000)
+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xcccb <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xc4c3 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0xc8c7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xcac9 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xbcbb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbebd <- 0x~~~~~~~~~~~~~~~~
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+#                                      ╙───────────── 0xc2c1 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xcbca <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcdcc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xcfce <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xc3c2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xc5c4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc7c6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc9c8 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xc1c0bfbebdbcbbba (-2.875, -1.936, -1.434, -0.9658)
+#                                      ║   ║   ║   ╙─ 0xbbba <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbdbc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xbfbe <- 0x~~~~~~~~~~~~~~~~
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+#             d4:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xe1e0dfdedddcdbda (-752.0, -503.5, -375.0, -251.2)
+#                                      ║   ║   ║   ╙─ 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xd9d8d7d6d5d4d3d2 (-187.0, -125.4, -93.25, -62.56)
+#                                      ║   ║   ║   ╙─ 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0xe0dfdedddcdbdad9 (-623.5, -439.2, -310.8, -219.1)
+#                                      ║   ║   ║   ╙─ 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xd8d7d6d5d4d3d2d1 (-154.9, -109.3, -77.19, -54.53)
+#                                      ║   ║   ║   ╙─ 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe8e7e6e5e4e3e2e1 (-2510., -1765., -1251., -880.5)
+#                                      ║   ║   ║   ╙─ 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0xe7e6e5e4e3e2e1e0 (-2022., -1508., -1009., -752.0)
+#                                      ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x3f3e3d3c3b3a39383736353433323130 (0.7431, 0.002842, 1.086e-05, 4.149e-08)
+#                          ║       ║       ║       ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            v31: 0x27262524232221201f1e1d1c1b1a1918 (2.306e-15, 8.789e-18, 3.348e-20, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x17161514131211100f0e0d0c0b0a0908 (4.849e-25, 1.844e-27, 7.004e-30, 2.658e-32)
+#                          ║       ║       ║       ╙─ 0x0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x17161514 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.008e-34, 3.820e-37, nan, -2.606e+36)
+#                          ║       ║       ║       ╙─ 0xfbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.002e+34, -3.850e+31, -1.479e+29, -5.680e+26)
+#                          ║       ║       ║       ╙─ 0xebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xefeeedec <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf7f6f5f4 <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x262524232221201f1e1d1c1b1a191817 (5.729e-16, 2.184e-18, 8.317e-21, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2221201f <- 0x~~~~~~~~~~~~~~~~
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+#             v6: 0x161514131211100f0e0d0c0b0a090807 (1.204e-25, 4.577e-28, 1.739e-30, 6.598e-33)
+#                          ║       ║       ║       ╙─ 0x0a090807 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
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+#             v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.502e-35, 9.478e-38, -1.688e+38, -6.490e+35)
+#                          ║       ║       ║       ╙─ 0xfaf9f8f7 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfefdfcfb <- 0x~~~~~~~~~~~~~~~~
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+#             v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.494e+33, -9.584e+30, -3.682e+28, -1.414e+26)
+#                          ║       ║       ║       ╙─ 0xeae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf6f5f4f3 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x565554535251504f4e4d4c4b4a494847 (5.864e+13, 2.247e+11, 8.611e+08, 3.298e+06)
+#                          ║       ║       ║       ╙─ 0x4a494847 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x4e4d4c4b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x5251504f <- 0x~~~~~~~~~~~~~~~~
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+#            v23: 0x464544434241403f3e3d3c3b3a393837 (1.263e+04, 48.31, 0.1848, 0.0007066)
+#                          ║       ║       ║       ╙─ 0x3a393837 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x3e3d3c3b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x4241403f <- 0x~~~~~~~~~~~~~~~~
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+#            v22: 0x363534333231302f2e2d2c2b2a292827 (2.700e-06, 1.031e-08, 3.937e-11, 1.502e-13)
+#                          ║       ║       ║       ╙─ 0x2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x2e2d2c2b <- 0x~~~~~~~~~~~~~~~~
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+#            v17: 0x5554535251504f4e4d4c4b4a49484746 (1.459e+13, 5.592e+10, 2.142e+08, 8.203e+05)
+#                          ║       ║       ║       ╙─ 0x49484746 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x4d4c4b4a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x51504f4e <- 0x~~~~~~~~~~~~~~~~
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+#            v16: 0x4544434241403f3e3d3c3b3a39383736 (3140., 12.02, 0.04595, 0.0001757)
+#                          ║       ║       ║       ╙─ 0x39383736 <- 0x~~~~~~~~~~~~~~~~
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+#            v15: 0x3534333231302f2e2d2c2b2a29282726 (6.713e-07, 2.564e-09, 9.787e-12, 3.734e-14)
+#                          ║       ║       ║       ╙─ 0x29282726 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x2d2c2b2a <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x31302f2e <- 0x~~~~~~~~~~~~~~~~
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+#            v21: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#            v31: 0x7574737271706f6e6d6c6b6a69686766 (3.099e+32, 1.191e+30, 4.573e+27, 1.756e+25)
+#                          ║       ║       ║       ╙─ 0x69686766 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x6d6c6b6a <- 0x~~~~~~~~~~~~~~~~
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+#            v30: 0x6564636261605f5e5d5c5b5a59585756 (6.741e+22, 2.587e+20, 9.924e+17, 3.806e+15)
+#                          ║       ║       ║       ╙─ 0x59585756 <- 0x~~~~~~~~~~~~~~~~
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+#            v12: 0x74737271706f6e6d6c6b6a6968676665 (7.715e+31, 2.964e+29, 1.138e+27, 4.371e+24)
+#                          ║       ║       ║       ╙─ 0x68676665 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x6c6b6a69 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x74737271 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0x64636261605f5e5d5c5b5a5958575655 (1.678e+22, 6.438e+19, 2.470e+17, 9.471e+14)
+#                          ║       ║       ║       ╙─ 0x58575655 <- 0x~~~~~~~~~~~~~~~~
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+#            v15: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
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+#            v12: 0x84838281807f7e7d7c7b7a7978777675 (-3.092e-36, -1.171e-38, 5.223e+36, 2.008e+34)
+#                          ║       ║       ║       ╙─ 0x78777675 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x84838281 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0x838281807f7e7d7c7b7a797877767574 (-7.670e-37, 3.383e+38, 1.301e+36, 4.999e+33)
+#                          ║       ║       ║       ╙─ 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f7e7d7c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x83828180 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x1f1e1d1c1b1a1918
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x1700000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#            d18:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xa3a2a1a09f9e9d9c
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x9c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x9d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x9e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x9f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x9b9a999897969594
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x94 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x95 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x96 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x97 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x98 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x99 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x9a <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x9b <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x939291908f8e8d8c
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x8d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x8e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x8f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x90 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x91 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x92 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x93 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x8b8a898887868584
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x84 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x86 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x87 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x88 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x89 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x8a <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x8b <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xa2a1a09f9e9d9c9b
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x9b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x9c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x9d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x9e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x9f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x9a99989796959493
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x93 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x94 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x95 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x96 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x97 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x98 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x99 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x9a <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x9291908f8e8d8c8b
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x8c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x8d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x8e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x8f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x90 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x91 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x92 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x8a89888786858483
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x83 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x84 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x86 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x87 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x88 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x89 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x8a <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x1700000000000000
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xbab9b8b7b6b5b4b3
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xb4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xb5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xb6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xb7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xba <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xb2b1b0afaeadacab
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xab <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xac <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xad <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xae <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xaf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb2 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xaaa9a8a7a6a5a4a3
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xa4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xa5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xa6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xaa <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0xb9b8b7b6b5b4b3b2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xb3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xb4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xb5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xb6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xb7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0xb1b0afaeadacabaa
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xaa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xab <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xac <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xad <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xae <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xaf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xb0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xb1 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xa9a8a7a6a5a4a3a2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xa2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xa3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xa4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xa5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xa6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xa7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xa8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xa9 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x0000000000fffeff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xc9c8c7c6c5c4c3c2
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xc1c0bfbebdbcbbba
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xc8c7c6c5c4c3c2c1
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xc0bfbebdbcbbbab9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xd0cfcecdcccbcac9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xcfcecdcccbcac9c8
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0x3f3e3d3c3b3a39383736353433323130 (1.811, 1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0f0e0d0c0b0a09080706050403020100 (0.0004306, 0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 (nan, nan, -6.534e+04, -4.890e+04, -3.261e+04, -2.438e+04, -1.627e+04, -1.216e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf1f0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf3f2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf5f4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf7f6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfbfa <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfdfc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 (-8120., -6064., -4052., -3024., -2022., -1508., -1009., -752.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe9e8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xebea <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xedec <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xefee <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 (-503.5, -375.0, -251.2, -187.0, -125.4, -93.25, -62.56, -46.50)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b0a09080706050403020100ff (0.0003693, 0.0002468, 0.0001842, 0.0001229, 9.185e-05, 6.121e-05, 3.058e-05, 1.520e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0201 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0605 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0807 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0a09 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0c0b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0e0d <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef (nan, nan, -5.712e+04, -4.067e+04, -2.850e+04, -2.027e+04, -1.422e+04, -1.010e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf0ef <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf2f1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf4f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf6f5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf8f7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfcfb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfefd <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df (-7092., -5036., -3538., -2510., -1765., -1251., -880.5, -623.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xeae9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xeceb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xeeed <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf (-439.2, -310.8, -219.1, -154.9, -109.3, -77.19, -54.53, -38.47)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3e3d3c3b3a393837363534333231302f (1.560, 1.058, 0.7778, 0.5269, 0.3879, 0.2625, 0.1935, 0.1307)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x302f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3433 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3635 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3837 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3c3b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2e2d2c2b2a292827262524232221201f (0.09650, 0.06512, 0.04813, 0.03244, 0.02400, 0.01616, 0.01197, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2e2d <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1e1d1c1b1a191817161514131211100f (0.005970, 0.004009, 0.002977, 0.001997, 0.001485, 0.0009947, 0.0007405, 0.0004954)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x100f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1211 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1413 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1615 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1e1d <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a393837363534333231302f2e (1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x5d5c5b5a595857565554535251504f4e (343.0, 235.2, 171.0, 117.4, 85.25, 58.56, 42.50, 29.22)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4f4e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5150 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5554 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5958 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5b5a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857565554535251504f4e4d (278.8, 203.1, 138.9, 101.3, 69.19, 50.53, 34.47, 25.20)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4e4d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x504f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5251 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5453 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5857 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5a59 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5c5b <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x4c4b4a494847464544434241403f3e3d (17.17, 12.57, 8.555, 6.270, 4.262, 3.127, 2.123, 1.560)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x403f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4443 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4645 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4c4b <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a696867666564636261605f5e5d (4524., 3282., 2254., 1637., 1123., 816.5, 559.5, 407.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5e5d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6463 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6665 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6a69 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6c6b <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x6b6a696867666564636261605f5e5d5c (3796., 2768., 1894., 1380., 945.0, 688.0, 471.5, 343.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6766 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6b6a <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a39383736353433323130012e
+#                                                ╙─── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef
+#                                            ╙─────── 0x6c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a6b6867666564636261605f5e5d
+#                          ╙───────────────────────── 0x6b <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.487e+303, ...)
+#                                  ╙───────────────── 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x737271706f6e6d6c636261605f5e5d5c (1.290e+248, ...)
+#                                  ╙───────────────── 0x737271706f6e6d6c <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x7271706f6e6d6c6b2726252423222120 (1.861e+243, ...)
+#                                  ╙───────────────── 0x7271706f6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3aff013736353433323130012e (..., nan, ...)
+#                              ╙───────────────────── 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d37473d0cf (..., 1.822e+04, ...)
+#                                              ╙───── 0x7473 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857737254535251504f4e4d (..., 1.525e+04, ...)
+#                                  ╙───────────────── 0x7372 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.751e-40, ...)
+#                                  ╙───────────────── 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.999e+33, ...)
+#                                  ╙───────────────── 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#             v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.245e+33, ...)
+#                                  ╙───────────────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x01010101010101010101010101010101
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x77777777777777777777777777777777
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x77 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x76767676767676767676767676767676
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x76 <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7e7d7c7b7a797877 (1.975e+301)
+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x7d7c7b7a79787776 (2.911e+296)
+#                                                  ╙─ 0x7d7c7b7a79787776 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#                                  ╙───────────────╨─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8584838281807f7e8584838281807f7e (-4.414e-282, -4.414e-282)
+#                                  ╙───────────────╨─ 0x8584838281807f7e <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84838281807f7e7d84838281807f7e7d (-6.406e-287, -6.406e-287)
+#                                  ╙───────────────╨─ 0x84838281807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#                                          ╙───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x8887868588878685 (-8.157e-34, -8.157e-34)
+#                                          ╙───────╨─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x8786858487868584 (-2.024e-34, -2.024e-34)
+#                                          ╙───────╨─ 0x87868584 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8988898889888988 (-0.0001688, -0.0001688, -0.0001688, -0.0001688)
+#                                      ╙───╨───╨───╨─ 0x8988 <- 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x8887888788878887 (-0.0001382, -0.0001382, -0.0001382, -0.0001382)
+#                                      ╙───╨───╨───╨─ 0x8887 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#                          ╙───────╨───────╨───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (-2.150e-31, -2.150e-31, -2.150e-31, -2.150e-31)
+#                          ╙───────╨───────╨───────╨─ 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0x8b8a89888b8a89888b8a89888b8a8988 (-5.336e-32, -5.336e-32, -5.336e-32, -5.336e-32)
+#                          ╙───────╨───────╨───────╨─ 0x8b8a8988 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x8c8c8c8c8c8c8c8c
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x8b8b8b8b8b8b8b8b
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c (-0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8d8c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b (-0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8c8b <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1e1c1a18000000000000ffff00850201
+#            v22: 0x1f1d1b1917000000000000feff0000ff
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x17'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1b'1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f'1e <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#            v22: 0xacaaa8a6a4a2a09e9c9a98969492908e
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x92'91 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x98'97 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa4'a3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaa'a9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xac'ab <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c
+#            v13: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x8f'8e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x95'94 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa1'a0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa7'a6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xa9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xab'aa <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x1700000000000000ff0000850002ff01 (6.689e-198, -5.487e+303)
+#            v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.568e-159, 8.289e-317)
+#                                  ║               ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.703e+18, -1.163e-59)
+#             v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.314e+57, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4'b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcbcac9c8c7c6c5c4'c3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.904e+13, -1.680e-64)
+#            v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.929e+52, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3'b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00fffeff0002ff01 (2.351e-38, 2.751e-40)
+#            d28:                 0x00000000ff000085 (0.000, -1.701e+38)
+#                                          ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xd6d5d4d3cecdcccb (-1.176e+14, -1.726e+09)
+#             d3:                 0xdad9d8d7d2d1d0cf (-3.066e+16, -4.506e+11)
+#                                          ║       ╙─ 0xd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xdad9d8d7'd6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xd5d4d3d2cdcccbca (-2.925e+13, -4.295e+08)
+#            d13:                 0xd9d8d7d6d1d0cfce (-7.629e+15, -1.121e+11)
+#                                          ║       ╙─ 0xd1d0cfce'cdcccbca <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x0000feff0085ff01 (0.000, nan, 7.927e-06, nan)
+#            d10:                 0x000000ffff000002 (0.000, 1.520e-05, nan, 1.192e-07)
+#                                      ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe7e6e3e2dfdedbda (-2022., -1009., -503.5, -251.2)
+#            d24:                 0xe9e8e5e4e1e0dddc (-3024., -1508., -752.0, -375.0)
+#                                      ║   ║   ║   ╙─ 0xdddc'dbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe1e0'dfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe9e8'e7e6 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe6e5e2e1dedddad9 (-1765., -880.5, -439.2, -219.1)
+#             d2:                 0xe8e7e4e3e0dfdcdb (-2510., -1251., -623.5, -310.8)
+#                                      ║   ║   ║   ╙─ 0xdcdb'dad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe0df'dedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7'e6e5 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x1b1a19180000000000fffeff0002ff01 (1.275e-22, 0.000, 2.351e-38, 2.751e-40)
+#            v21: 0x1f1e1d1c1700000000000000ff000085 (3.348e-20, 4.136e-25, 0.000, -1.701e+38)
+#                          ║       ║       ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.540e-36, -1.047e+37, -1.546e+32, -2.282e+27)
+#            v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.063e-34, 2.351e-38, -4.023e+34, -5.940e+29)
+#                          ║       ║       ║       ╙─ 0xf0efeeed'ecebeae9 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf8f7f6f5'f4f3f2f1 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffefd'fcfbfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x08070605'04030201 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.820e-37, -2.606e+36, -3.850e+31, -5.680e+26)
+#            v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.008e-34, nan, -1.002e+34, -1.479e+29)
+#                          ║       ║       ║       ╙─ 0xefeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf7f6f5f4'f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xfffefdfc'fbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504'03020100 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000ffff00850201
+#            d18:                 0x000000feff0000ff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x161412100e0c0a08
+#            d14:                 0x171513110f0d0b09
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x09'08 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x11'10 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'16 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1513110f0d0b0907
+#             d8:                 0x161412100e0c0a08
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0a'09 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0e'0d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x16'15 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c1918000000000000feff0085ff01 (0.004990, 0.002487, 0.000, 0.000, 0.000, nan, 7.927e-06, nan)
+#            v31: 0x1f1e1b1a17000000000000ffff000002 (0.006950, 0.003468, 0.001709, 0.000, 0.000, 1.520e-05, nan, 1.192e-07)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1700'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x3433302f2c2b28272423201f1c1b1817 (0.2625, 0.1307, 0.06512, 0.03244, 0.01616, 0.008049, 0.004009, 0.001997)
+#             v5: 0x363532312e2d2a29262522211e1d1a19 (0.3879, 0.1935, 0.09650, 0.04813, 0.02400, 0.01197, 0.005970, 0.002977)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1a19'1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1e1d'1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2221'201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625'2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2a29'2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2e2d'2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3231'302f <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3635'3433 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x33322f2e2b2a272623221f1e1b1a1716 (0.2249, 0.1122, 0.05597, 0.02792, 0.01393, 0.006950, 0.003468, 0.001730)
+#            v14: 0x353431302d2c2928252421201d1c1918 (0.3252, 0.1621, 0.08081, 0.04028, 0.02008, 0.01001, 0.004990, 0.002487)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928'2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x363532012e2d2a29262522211e1d1a19
+#             v6: 0x1f1e1dff1b1a19181700000000000000
+#                          ╙───────────────────────── 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x4544434241403f3e363c3b3a39383736
+#            v17: 0x00000000000000003700ffff00850201
+#                                    ╙─────────────── 0x37'36 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfb35f9f8
+#            v30: 0x1d1c1918000000000000feff0036ff01
+#                                              ╙───── 0x36'35 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.487e+303, ...)
+#            v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.289e-317, ...)
+#                                  ╙───────────────── 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x00000000000000003e3d3c3b3a393837 (..., 6.807e-09)
+#            v27: 0x0000000000000000464544434241403f (..., 3.370e+30)
+#                                                  ╙─ 0x464544434241403f'3e3d3c3b3a393837 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x07060504fffefdfc3d3c3b3a39383736 (..., 1.003e-13)
+#            v26: 0x00000000000000004544434241403f3e (..., 4.899e+25)
+#                                                  ╙─ 0x4544434241403f3e'3d3c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0xff01000000000000000000feff0000ff (nan, ...)
+#            v19: 0x00020000000000008b8b8b8b8b8b8b8b (1.192e-07, ...)
+#                      ╙───────────────────────────── 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x00000000474600003700ffff00850201 (..., 7.273, ...)
+#            v18: 0xff01000049480000000000feff0000ff (..., 10.56, ...)
+#                              ╙───────────────────── 0x4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c191800000000000046450036ff01 (..., 6.270, ...)
+#            v31: 0x1f1e1b1a1700000000004847ff000002 (..., 8.555, ...)
+#                                          ╙───────── 0x4847'4645 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.751e-40, ...)
+#            v30: 0xff00008500000000000046450036ff01 (-1.701e+38, ...)
+#                          ╙───────────────────────── 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000000000000000004c4b4a49 (..., 5.329e+07)
+#            v29: 0x0002ff0103020100fffefdfc504f4e4d (..., 1.391e+10)
+#                                                  ╙─ 0x504f4e4d'4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.326e+07, ...)
+#             v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.461e+09, ...)
+#                                          ╙───────── 0x4f4e4d4c'4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x01010101010101010101010101010101
+#            v27: 0xffffffffffffffffffffffffffffffff
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x50505050505050505050505050505050
+#            v22: 0x51515151515151515151515151515151
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x51'50 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f
+#             v6: 0x50505050505050505050505050505050
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x50'4f <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-5.487e+303)
+#            d27:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x5857565554535251 (3.678e+117)
+#            d15:                 0x605f5e5d5c5b5a59 (1.682e+156)
+#                                                  ╙─ 0x605f5e5d5c5b5a59'5857565554535251 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x5756555453525150 (5.371e+112)
+#            d24:                 0x5f5e5d5c5b5a5958 (2.485e+151)
+#                                                  ╙─ 0x5f5e5d5c5b5a5958'5756555453525150 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v12: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#                                  ╙───────────────╨─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x67666564636261606766656463626160 (1.247e+190, 1.247e+190)
+#            v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.766e+228, 5.766e+228)
+#                                  ╙───────────────╨─ 0x6f6e6d6c6b6a6968'6766656463626160 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x666564636261605f666564636261605f (1.818e+185, 1.818e+185)
+#            v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.509e+223, 8.509e+223)
+#                                  ╙───────────────╨─ 0x6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d27:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#                                          ╙───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x7271706f7271706f (4.782e+30, 4.782e+30)
+#            d23:                 0x7675747376757473 (1.245e+33, 1.245e+33)
+#                                          ╙───────╨─ 0x76757473'7271706f <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x71706f6e71706f6e (1.191e+30, 1.191e+30)
+#             d3:                 0x7574737275747372 (3.099e+32, 3.099e+32)
+#                                          ╙───────╨─ 0x75747372'71706f6e <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#             d3:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                                      ╙───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7776777677767776 (3.056e+04, 3.056e+04, 3.056e+04, 3.056e+04)
+#            d10:                 0x7978797879787978 (4.480e+04, 4.480e+04, 4.480e+04, 4.480e+04)
+#                                      ╙───╨───╨───╨─ 0x7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x7675767576757675 (2.645e+04, 2.645e+04, 2.645e+04, 2.645e+04)
+#             d7:                 0x7877787778777877 (3.658e+04, 3.658e+04, 3.658e+04, 3.658e+04)
+#                                      ╙───╨───╨───╨─ 0x7877'7675 <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#             v8: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#                          ╙───────╨───────╨───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (5.223e+36, 5.223e+36, 5.223e+36, 5.223e+36)
+#            v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (-1.171e-38, -1.171e-38, -1.171e-38, -1.171e-38)
+#                          ╙───────╨───────╨───────╨─ 0x807f7e7d'7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x7b7a79787b7a79787b7a79787b7a7978 (1.301e+36, 1.301e+36, 1.301e+36, 1.301e+36)
+#            v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (3.383e+38, 3.383e+38, 3.383e+38, 3.383e+38)
+#                          ╙───────╨───────╨───────╨─ 0x7f7e7d7c'7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#            d27:                 0xffffffffffffffff
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x8080808080808080
+#            d21:                 0x8181818181818181
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x81'80 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x7f7f7f7f7f7f7f7f
+#            d12:                 0x8080808080808080
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x80'7f <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v13: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x82818281828182818281828182818281 (-3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05)
+#             v7: 0x84838483848384838483848384838483 (-6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8483'8281 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x81808180818081808180818081808180 (-2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05)
+#            v26: 0x83828382838283828382838283828382 (-5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2d2a2724211e1b1800000000fe000001
+#            v21: 0x2e2b2825221f1c1900000000ffff85ff
+#            v22: 0x2f2c292623201d1a1700000000ff0002
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x20'1f'1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x23'22'21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2c'2b'2a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f'2e'2d <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v29: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#            v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x89'88'87 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8c'8b'8a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8f'8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x95'94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x98'97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa1'a0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa4'a3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa7'a6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xaa'a9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xad'ac'ab <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb3'b2'b1 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0xb0adaaa7a4a19e9b9895928f8c898683
+#            v21: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v22: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x85'84'83 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x88'87'86 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8b'8a'89 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8e'8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x91'90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x94'93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x97'96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9a'99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa3'a2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa6'a5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa9'a8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xac'ab'aa <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb2'b1'b0 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.568e-159, -5.487e+303)
+#            v22: 0x27262524232221200000000000fffeff (4.288e-120, 8.289e-317)
+#            v23: 0x2f2e2d2c2b2a29281700000000000000 (1.988e-81, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928'2726252423222120'1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.073e+90, -8.311e-26)
+#            v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.479e+129, -3.904e+13)
+#            v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.109e+168, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb'dad9d8d7d6d5d4d3'd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.306e+86, -1.219e-30)
+#            v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.569e+124, -5.620e+08)
+#            v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.037e+163, -2.829e+47)
+#                                  ║               ╙─ 0xc9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe1e0dfdedddcdbda'd9d8d7d6d5d4d3d2'd1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x000000000002ff01 (0.000, 2.751e-40)
+#             d8:                 0x00000000ff000085 (0.000, -1.701e+38)
+#             d9:                 0x1700000000fffeff (4.136e-25, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xf1f0efeee5e4e3e2 (-2.386e+30, -1.351e+23)
+#            d21:                 0xf5f4f3f2e9e8e7e6 (-6.210e+32, -3.520e+25)
+#            d22:                 0xf9f8f7f6edecebea (-1.616e+35, -9.165e+27)
+#                                          ║       ╙─ 0xedecebea'e9e8e7e6'e5e4e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xf0efeeede4e3e2e1 (-5.940e+29, -3.363e+22)
+#            d27:                 0xf4f3f2f1e8e7e6e5 (-1.546e+32, -8.761e+24)
+#            d28:                 0xf8f7f6f5ecebeae9 (-4.023e+34, -2.282e+27)
+#                                          ║       ╙─ 0xecebeae9'e8e7e6e5'e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00000000ff00ff01 (0.000, 0.000, nan, nan)
+#            d28:                 0x00000000feff0002 (0.000, 0.000, nan, 1.192e-07)
+#            d29:                 0x1700000000ff0085 (0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                                      ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x0c0b060500fffaf9 (0.0002468, 9.185e-05, 1.520e-05, -5.712e+04)
+#            d29:                 0x0e0d08070201fcfb (0.0003693, 0.0001229, 3.058e-05, nan)
+#            d30:                 0x100f0a090403fefd (0.0004954, 0.0001842, 6.121e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0403'0201'00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0a09'0807'0605 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x100f'0e0d'0c0b <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x0b0a0504fffef9f8 (0.0002148, 7.653e-05, nan, -4.890e+04)
+#             d8:                 0x0d0c07060100fbfa (0.0003080, 0.0001072, 1.526e-05, -6.534e+04)
+#             d9:                 0x0f0e09080302fdfc (0.0004306, 0.0001535, 4.590e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfdfc'fbfa'f9f8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0302'0100'fffe <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0908'0706'0504 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0f0e'0d0c'0b0a <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x272625241b1a1918000000000002ff01 (2.306e-15, 1.275e-22, 0.000, 2.751e-40)
+#             v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.045e-13, 3.348e-20, 0.000, -1.701e+38)
+#             v4: 0x2f2e2d2c232221201700000000fffeff (1.584e-10, 8.789e-18, 4.136e-25, 2.351e-38)
+#                          ║       ║       ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120'1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c'2b2a2928'27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x373635342b2a29281f1e1d1c13121110 (1.086e-05, 6.045e-13, 3.348e-20, 1.844e-27)
+#            v25: 0x3b3a39382f2e2d2c2322212017161514 (0.002842, 1.584e-10, 8.789e-18, 4.849e-25)
+#            v26: 0x3f3e3d3c33323130272625241b1a1918 (0.7431, 4.149e-08, 2.306e-15, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918'17161514'13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x33323130'2f2e2d2c'2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0x363534332a2928271e1d1c1b1211100f (2.700e-06, 1.502e-13, 8.317e-21, 4.577e-28)
+#            v12: 0x3a3938372e2d2c2b2221201f16151413 (0.0007066, 3.937e-11, 2.184e-18, 1.204e-25)
+#            v13: 0x3e3d3c3b3231302f262524231a191817 (0.1848, 1.031e-08, 5.729e-16, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817'16151413'1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x26252423'2221201f'1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3231302f'2e2d2c2b'2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3e3d3c3b'3a393837'36353433 <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x00000000fe000001
+#            d30:                 0x00000000ffff85ff
+#            d31:                 0x1700000000ff0002
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x54514e4b4845423f
+#             d2:                 0x55524f4c49464340
+#             d3:                 0x5653504d4a474441
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x41'40'3f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x44'43'42 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x47'46'45 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x4a'49'48 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4d'4c'4b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x50'4f'4e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x53'52'51 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x56'55'54 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x53504d4a4744413e
+#            d13:                 0x54514e4b4845423f
+#            d14:                 0x55524f4c49464340
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40'3f'3e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x43'42'41 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x46'45'44 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x49'48'47 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4c'4b'4a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x4f'4e'4d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x52'51'50 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x55'54'53 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x2b2a25241f1e191800000000ff00ff01 (0.05597, 0.02008, 0.006950, 0.002487, 0.000, 0.000, nan, nan)
+#            v23: 0x2d2c272621201b1a00000000feff0002 (0.08081, 0.02792, 0.01001, 0.003468, 0.000, 0.000, nan, 1.192e-07)
+#            v24: 0x2f2e292823221d1c1700000000ff0085 (0.1122, 0.04028, 0.01393, 0.004990, 0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2322'2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2928'2726'2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e696863625d5c5756 (-2.289e-05, 6.125e+04, 2.234e+04, 7608., 2768., 945.0, 343.0, 117.4)
+#            v14: 0x83827d7c777671706b6a65645f5e5958 (-5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5, 171.0)
+#            v15: 0x85847f7e797873726d6c676661605b5a (-8.416e-05, nan, 4.480e+04, 1.525e+04, 5552., 1894., 688.0, 235.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5b5a'5958'5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6160'5f5e'5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6766'6564'6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6d6c'6b6a'6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7372'7170'6f6e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7978'7776'7574 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8584'8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x807f7a7974736e6d686762615c5b5655 (-7.570e-06, 5.302e+04, 1.822e+04, 6580., 2254., 816.5, 278.8, 101.3)
+#            v29: 0x82817c7b7675706f6a6964635e5d5857 (-3.821e-05, nan, 2.645e+04, 9080., 3282., 1123., 407.2, 138.9)
+#            v30: 0x84837e7d787772716c6b6665605f5a59 (-6.884e-05, nan, 3.658e+04, 1.319e+04, 4524., 1637., 559.5, 203.1)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5a59'5857'5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f'5e5d'5c5b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6665'6463'6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6c6b'6a69'6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7271'706f'6e6d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7877'7675'7473 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7e7d'7c7b'7a79 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8483'8281'807f <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x0000000001000000f5f4f3f2e9e8e7e6
+#            v22: 0x2b2a2524ff1e191800000000ff00ff01
+#            v23: 0x2d2c272602201b1a00000000feff0002
+#                            ╙─────────────────────── 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f
+#             v6: 0x82818281828186818281828182818281
+#             v7: 0x00000000000087000b0a0504fffef9f8
+#                                ╙─────────────────── 0x87'86'85 <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0x2d2c272602201b1a00000000feff0084
+#            v24: 0x2f2e292823221d1c1700000000ff0085
+#            v25: 0x3b3a39382f2e2d2c2322212017161586
+#                                                  ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6e6d6c6b6a696867ff0000850002ff01 (..., -5.487e+303)
+#            v17: 0x00000000474600000000000000fffeff (..., 8.289e-317)
+#            v18: 0xd2d1d0cfcecdcccb1700000000000000 (..., 6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84837e7d787772718e8d8c8b8a898887 (..., -1.418e-238)
+#            v31: 0x0000000000000000969594939291908f (..., -7.048e-200)
+#             v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (..., -3.291e-161)
+#                                                  ╙─ 0x9e9d9c9b9a999897'969594939291908f'8e8d8c8b8a898887 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.090e-243, ...)
+#            v29: 0x9594939291908f8e6a6964635e5d5857 (-1.025e-204, ...)
+#            v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.851e-166, ...)
+#                                  ╙───────────────── 0x9d9c9b9a99989796'9594939291908f8e'8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e6968ff015d5c5756 (..., nan, ...)
+#            v14: 0x83827d7c777671706b6a00025f5e5958 (..., 1.192e-07, ...)
+#            v15: 0x85847f7e797873726d6c008561605b5a (..., 7.927e-06, ...)
+#                                          ╙───────── 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x9f9e2524ff1e191800000000ff00ff01 (-0.007439, ...)
+#            v23: 0xa1a0272602201b1a00000000feff0084 (-0.01099, ...)
+#            v24: 0xa3a2292823221d1c1700000000ff0085 (-0.01491, ...)
+#                      ╙───────────────────────────── 0xa3a2'a1a0'9f9e <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x83827d7c777671709e9d00025f5e5958 (..., -0.006458, ...)
+#            v15: 0x85847f7e79787372a09f008561605b5a (..., -0.009026, ...)
+#            v16: 0x6e6d6c6b6a696867a2a100850002ff01 (..., -0.01295, ...)
+#                                      ╙───────────── 0xa2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x0002ff01ff1e191800000000ff00ff01 (2.751e-40, ...)
+#            v23: 0xff00008502201b1a00000000feff0084 (-1.701e+38, ...)
+#            v24: 0x00fffeff23221d1c1700000000ff0085 (2.351e-38, ...)
+#                          ╙───────────────────────── 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.149e-15, ...)
+#            v31: 0x00000000aaa9a8a7969594939291908f (..., -3.014e-13, ...)
+#             v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.898e-11, ...)
+#                                  ╙───────────────── 0xaeadacab'aaa9a8a7'a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000a5a4a3a24744413e (..., -2.856e-16, ...)
+#            v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.490e-14, ...)
+#            v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.963e-11, ...)
+#                                          ╙───────── 0xadacabaa'a9a8a7a6'a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x01010101010101010101010101010101
+#            v25: 0xffffffffffffffffffffffffffffffff
+#            v26: 0x02020202020202020202020202020202
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#            v25: 0xafafafafafafafafafafafafafafafaf
+#            v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0xadadadadadadadadadadadadadadadad
+#             v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#             v5: 0xafafafafafafafafafafafafafafafaf
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01 (-5.487e+303)
+#             d5:                 0x0000000000fffeff (8.289e-317)
+#             d6:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xb7b6b5b4b3b2b1b0 (-2.607e-40)
+#             d8:                 0xbfbebdbcbbbab9b8 (-0.1201)
+#             d9:                 0xc7c6c5c4c3c2c1c0 (-6.054e+37)
+#                                                  ╙─ 0xc7c6c5c4c3c2c1c0'bfbebdbcbbbab9b8'b7b6b5b4b3b2b1b0 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xb6b5b4b3b2b1b0af (-3.802e-45)
+#            d18:                 0xbebdbcbbbab9b8b7 (-1.772e-06)
+#            d19:                 0xc6c5c4c3c2c1c0bf (-8.830e+32)
+#                                                  ╙─ 0xc6c5c4c3c2c1c0bf'bebdbcbbbab9b8b7'b6b5b4b3b2b1b0af <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v17: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v18: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#                                  ╙───────────────╨─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.113e+71, -4.113e+71)
+#            v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.051e+110, -2.051e+110)
+#            v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.546e+148, -9.546e+148)
+#                                  ╙───────────────╨─ 0xdedddcdbdad9d8d7'd6d5d4d3d2d1d0cf'cecdcccbcac9c8c7 <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.065e+66, -6.065e+66)
+#            v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.985e+105, -2.985e+105)
+#            v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.408e+144, -1.408e+144)
+#                                  ╙───────────────╨─ 0xdddcdbdad9d8d7d6'd5d4d3d2d1d0cfce'cdcccbcac9c8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d11:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#            d12:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#                                          ╙───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#             d1:                 0xe5e4e3e2e5e4e3e2 (-1.351e+23, -1.351e+23)
+#             d2:                 0xe9e8e7e6e9e8e7e6 (-3.520e+25, -3.520e+25)
+#                                          ╙───────╨─ 0xe9e8e7e6'e5e4e3e2'e1e0dfde <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#            d24:                 0xe4e3e2e1e4e3e2e1 (-3.363e+22, -3.363e+22)
+#            d25:                 0xe8e7e6e5e8e7e6e5 (-8.761e+24, -8.761e+24)
+#                                          ╙───────╨─ 0xe8e7e6e5'e4e3e2e1'e0dfdedd <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d23:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d24:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                                      ╙───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0xeae9eae9eae9eae9 (-3538., -3538., -3538., -3538.)
+#             d7:                 0xecebecebecebeceb (-5036., -5036., -5036., -5036.)
+#             d8:                 0xeeedeeedeeedeeed (-7092., -7092., -7092., -7092.)
+#                                      ╙───╨───╨───╨─ 0xeeed'eceb'eae9 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xe9e8e9e8e9e8e9e8 (-3024., -3024., -3024., -3024.)
+#             d8:                 0xebeaebeaebeaebea (-4052., -4052., -4052., -4052.)
+#             d9:                 0xedecedecedecedec (-6064., -6064., -6064., -6064.)
+#                                      ╙───╨───╨───╨─ 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v27: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v28: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#                          ╙───────╨───────╨───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (-2.386e+30, -2.386e+30, -2.386e+30, -2.386e+30)
+#             v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (-6.210e+32, -6.210e+32, -6.210e+32, -6.210e+32)
+#             v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (-1.616e+35, -1.616e+35, -1.616e+35, -1.616e+35)
+#                          ╙───────╨───────╨───────╨─ 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (-5.940e+29, -5.940e+29, -5.940e+29, -5.940e+29)
+#            v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (-1.546e+32, -1.546e+32, -1.546e+32, -1.546e+32)
+#             v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (-4.023e+34, -4.023e+34, -4.023e+34, -4.023e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x0101010101010101
+#             d3:                 0xffffffffffffffff
+#             d4:                 0x0202020202020202
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xf9f9f9f9f9f9f9f9
+#            d11:                 0xfafafafafafafafa
+#            d12:                 0xfbfbfbfbfbfbfbfb
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfb'fa'f9 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v7: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#             v8: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#             v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v9: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xfffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x3c3834302c2824201c18000000ff8501
+#             v4: 0x3d3935312d2925211d19000000fe00ff
+#             v5: 0x3e3a36322e2a26221e1a000000ff0002
+#             v6: 0x3f3b37332f2b27231f1b17000000ff00
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x3c3834302c2824201c1814100c080400
+#             v3: 0x3d3935312d2925211d1915110d090501
+#             v4: 0x3e3a36322e2a26221e1a16120e0a0602
+#             v5: 0x3f3b37332f2b27231f1b17130f0b0703
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x03'02'01'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x07'06'05'04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0b'0a'09'08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0f'0e'0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x13'12'11'10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'16'15'14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3b37332f2b27231f1b17130f0b0703ff
+#             v6: 0x3c3834302c2824201c1814100c080400
+#             v7: 0x3d3935312d2925211d1915110d090501
+#             v8: 0x3e3a36322e2a26221e1a16120e0a0602
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1e'1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22'21'20'1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x26'25'24'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a'29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2e'2d'2c'2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x32'31'30'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x36'35'34'33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3a'39'38'37 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3e'3d'3c'3b <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2726252423222120ff0000850002ff01 (4.288e-120, -5.487e+303)
+#            v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.988e-81, 8.289e-317)
+#            v20: 0x37363534333231301700000000000000 (9.958e-43, 6.689e-198)
+#            v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.0004614, 8.568e-159)
+#                                  ║               ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938'3736353433323130'2f2e2d2c2b2a2928'2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x666564636261605f464544434241403f (1.818e+185, 3.370e+30)
+#             v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.509e+223, 1.580e+69)
+#             v6: 0x767574737271706f565554535251504f (4.222e+262, 7.827e+107)
+#             v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.975e+301, 3.666e+146)
+#                                  ║               ╙─ 0x5e5d5c5b5a595857'565554535251504f'4e4d4c4b4a494847'464544434241403f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7e7d7c7b7a797877'767574737271706f'6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x6564636261605f5e4544434241403f3e (2.644e+180, 4.899e+25)
+#            v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.254e+219, 2.328e+64)
+#            v31: 0x7574737271706f6e5554535251504f4e (6.141e+257, 1.138e+103)
+#             v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.911e+296, 5.403e+141)
+#                                  ║               ╙─ 0x5d5c5b5a59585756'5554535251504f4e'4d4c4b4a49484746'4544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7d7c7b7a79787776'7574737271706f6e'6d6c6b6a69686766'6564636261605f5e <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x000000000002ff01 (0.000, 2.751e-40)
+#            d28:                 0x17000000ff000085 (4.136e-25, -1.701e+38)
+#            d29:                 0x1b1a191800fffeff (1.275e-22, 2.351e-38)
+#            d30:                 0x1f1e1d1c00000000 (3.348e-20, 0.000)
+#                                          ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x91908f8e81807f7e (-2.281e-28, -4.720e-38)
+#            d25:                 0x9594939285848382 (-6.001e-26, -1.246e-35)
+#            d26:                 0x9998979689888786 (-1.578e-23, -3.287e-33)
+#            d27:                 0x9d9c9b9a8d8c8b8a (-4.145e-21, -8.662e-31)
+#                                          ║       ╙─ 0x8d8c8b8a'89888786'85848382'81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9d9c9b9a'99989796'95949392'91908f8e <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x908f8e8d807f7e7d (-5.662e-29, -1.171e-38)
+#             d5:                 0x9493929184838281 (-1.490e-26, -3.092e-36)
+#             d6:                 0x9897969588878685 (-3.918e-24, -8.157e-34)
+#             d7:                 0x9c9b9a998c8b8a89 (-1.030e-21, -2.150e-31)
+#                                          ║       ╙─ 0x8c8b8a89'88878685'84838281'807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99'98979695'94939291'908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0x19180000feffff01 (0.002487, 0.000, nan, nan)
+#            d17:                 0x1b1a000000ff0002 (0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            d18:                 0x1d1c000000000085 (0.004990, 0.000, 0.000, 7.927e-06)
+#            d19:                 0x1f1e17000000ff00 (0.006950, 0.001709, 0.000, nan)
+#                                      ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xb6b5aeada6a59e9d (-0.4192, -0.1043, -0.02596, -0.006458)
+#            d24:                 0xb8b7b0afa8a7a09f (-0.5894, -0.1464, -0.03635, -0.009026)
+#            d25:                 0xbab9b2b1aaa9a2a1 (-0.8403, -0.2091, -0.05203, -0.01295)
+#            d26:                 0xbcbbb4b3acaba4a3 (-1.183, -0.2937, -0.07294, -0.01811)
+#                                      ║   ║   ║   ╙─ 0xa4a3'a2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xacab'aaa9'a8a7'a6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb4b3'b2b1'b0af'aead <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbcbb'bab9'b8b7'b6b5 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xb5b4adaca5a49d9c (-0.3564, -0.08862, -0.02203, -0.005478)
+#             d3:                 0xb7b6afaea7a69f9e (-0.4819, -0.1200, -0.02988, -0.007439)
+#             d4:                 0xb9b8b1b0a9a8a1a0 (-0.7148, -0.1777, -0.04419, -0.01099)
+#             d5:                 0xbbbab3b2abaaa3a2 (-0.9658, -0.2405, -0.05988, -0.01491)
+#                                      ║   ║   ║   ╙─ 0xa3a2'a1a0'9f9e'9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xabaa'a9a8'a7a6'a5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb3b2'b1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba'b9b8'b7b6'b5b4 <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x3332313023222120000000000002ff01 (4.149e-08, 8.789e-18, 0.000, 2.751e-40)
+#             v8: 0x373635342726252417000000ff000085 (1.086e-05, 2.306e-15, 4.136e-25, -1.701e+38)
+#             v9: 0x3b3a39382b2a29281b1a191800fffeff (0.002842, 6.045e-13, 1.275e-22, 2.351e-38)
+#            v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.7431, 1.584e-10, 3.348e-20, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2f2e2d2c'2b2a2928'27262524'23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534'33323130 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#            v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.850e+31, -8.370e+21, -1.811e+12, -389.5)
+#            v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.002e+34, -2.181e+24, -4.724e+14, -1.018e+05)
+#            v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.606e+36, -5.680e+26, -1.232e+17, -2.658e+07)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.682e+28, -7.993e+18, -1.726e+09, -0.3706)
+#            v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.584e+30, -2.083e+21, -4.506e+11, -96.88)
+#            v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.494e+33, -5.428e+23, -1.176e+14, -2.531e+04)
+#             v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.490e+35, -1.414e+26, -3.066e+16, -6.612e+06)
+#                          ║       ║       ║       ╙─ 0xcac9c8c7'c6c5c4c3'c2c1c0bf'bebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdad9d8d7'd6d5d4d3'd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xeae9e8e7'e6e5e4e3'e2e1e0df'dedddcdb <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfaf9f8f7'f6f5f4f3'f2f1f0ef'eeedeceb <- 0x~~~~~~~~~~~~~~~~
+#            d15:                 0x1c18000000ff8501
+#            d16:                 0x1d19000000fe00ff
+#            d17:                 0x1e1a000000ff0002
+#            d18:                 0x1f1b17000000ff00
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x17130f0b0703fffb
+#            d28:                 0x1814100c080400fc
+#            d29:                 0x1915110d090501fd
+#            d30:                 0x1a16120e0a0602fe
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfe'fd'fc'fb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x16120e0a0602fefa
+#             d6:                 0x17130f0b0703fffb
+#             d7:                 0x1814100c080400fc
+#             d8:                 0x1915110d090501fd
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfd'fc'fb'fa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x01'00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x05'04'03'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x09'08'07'06 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0d'0c'0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x11'10'0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14'13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x19'18'17'16 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831302928212019180000feffff01 (0.6523, 0.1621, 0.04028, 0.01001, 0.002487, 0.000, nan, nan)
+#            v26: 0x3b3a33322b2a23221b1a000000ff0002 (0.9033, 0.2249, 0.05597, 0.01393, 0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            v27: 0x3d3c35342d2c25241d1c000000000085 (1.309, 0.3252, 0.08081, 0.02008, 0.004990, 0.000, 0.000, 7.927e-06)
+#            v28: 0x3f3e37362f2e27261f1e17000000ff00 (1.811, 0.4507, 0.1122, 0.02792, 0.006950, 0.001709, 0.000, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726'2524'2322'2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2f2e'2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3736'3534'3332'3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e'3d3c'3b3a'3938 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x53524b4a43423b3a33322b2a23221b1a (58.56, 14.58, 3.629, 0.9033, 0.2249, 0.05597, 0.01393, 0.003468)
+#             v3: 0x55544d4c45443d3c35342d2c25241d1c (85.25, 21.19, 5.266, 1.309, 0.3252, 0.08081, 0.02008, 0.004990)
+#             v4: 0x57564f4e47463f3e37362f2e27261f1e (117.4, 29.22, 7.273, 1.811, 0.4507, 0.1122, 0.02792, 0.006950)
+#             v5: 0x59585150494841403938313029282120 (171.0, 42.50, 10.56, 2.625, 0.6523, 0.1621, 0.04028, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120'1f1e'1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2928'2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3130'2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3938'3736'3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4140'3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948'4746'4544'4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5150'4f4e'4d4c'4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5958'5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2922211a19 (50.53, 12.57, 3.127, 0.7778, 0.1935, 0.04813, 0.01197, 0.002977)
+#            v21: 0x54534c4b44433c3b34332c2b24231c1b (69.19, 17.17, 4.262, 1.058, 0.2625, 0.06512, 0.01616, 0.004009)
+#            v22: 0x56554e4d46453e3d36352e2d26251e1d (101.3, 25.20, 6.270, 1.560, 0.3879, 0.09650, 0.02400, 0.005970)
+#            v23: 0x5857504f4847403f3837302f2827201f (138.9, 34.47, 8.555, 2.123, 0.5269, 0.1307, 0.03244, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f'1e1d'1c1b'1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2827'2625'2423'2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x302f'2e2d'2c2b'2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3837'3635'3433'3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x403f'3e3d'3c3b'3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847'4645'4443'4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x504f'4e4d'4c4b'4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5857'5655'5453'5251 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2901211a19
+#            v21: 0x54534c4b44433c3b34332c2bff231c1b
+#            v22: 0x56554e4d46453e3d36352e2d02251e1d
+#            v23: 0x5857504f4847403f3837302f0027201f
+#                                            ╙─────── 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000fbfbfbfb59fbfbfb
+#            v13: 0x81807b7a75746f6ea9a8a7a65a5c5756
+#            v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6
+#            v15: 0x00000000000000001c1800005cff8501
+#                                            ╙─────── 0x5c'5b'5a'59 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x3d3c35342d2c25241d58000000000085
+#            v28: 0x3f3e37362f2e27261f5917000000ff00
+#            v29: 0x0000000000000000195a110d090501fd
+#            v30: 0x00000000000000001a5b120e0a0602fe
+#                                      ╙───────────── 0x5b'5a'59'58 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff0000850002ff011f5917000000ff00 (-5.487e+303, ...)
+#            v29: 0x0000000000fffeff195a110d090501fd (8.289e-317, ...)
+#            v30: 0x17000000000000001a5b120e0a0602fe (6.689e-198, ...)
+#            v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.568e-159, ...)
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x636261605f5e5d5c1c1800005cff8501 (5.549e+170, ...)
+#            v16: 0x6b6a6968676665641d19000000fe00ff (2.713e+209, ...)
+#            v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.290e+248, ...)
+#            v18: 0x7b7a7978777675741f1b17000000ff00 (6.299e+286, ...)
+#                                  ╙───────────────── 0x7b7a797877767574'737271706f6e6d6c'6b6a696867666564'636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.005e+165, ...)
+#            v17: 0x6a696867666564631e1a000000ff0002 (3.983e+204, ...)
+#            v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.861e+243, ...)
+#            v19: 0x7a797877767574731f1e17000000ff00 (9.247e+281, ...)
+#                                  ╙───────────────── 0x7a79787776757473'7271706f6e6d6c6b'6a69686766656463'6261605f5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x5352ff0143423b3a33322b2a23221b1a (..., nan, ...)
+#             v3: 0x5554000245443d3c35342d2c25241d1c (..., 1.192e-07, ...)
+#             v4: 0x5756008547463f3e37362f2e27261f1e (..., 7.927e-06, ...)
+#             v5: 0x5958ff00494841403938313029282120 (..., nan, ...)
+#                          ╙───────────────────────── 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5958ff00494841407c7b313029282120 (..., nan, ...)
+#             v6: 0x00000000000000007e7d0f0b0703fffb (..., nan, ...)
+#             v7: 0x0000000000000000807f100c080400fc (..., -7.570e-06, ...)
+#             v8: 0x00000000000000008281110d090501fd (..., -3.821e-05, ...)
+#                                      ╙───────────── 0x8281'807f'7e7d'7c7b <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x00007b7a00000000807f100c080400fc (..., 6.125e+04, ...)
+#             v8: 0x00007d7c000000008281110d090501fd (..., nan, ...)
+#             v9: 0x3b3a7f7e2b2a29281b1a191800fffeff (..., nan, ...)
+#            v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 (..., -2.289e-05, ...)
+#                          ╙───────────────────────── 0x8180'7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x00000000000000000002ff010703fffb (..., 2.751e-40, ...)
+#             v7: 0x00007b7a00000000ff000085080400fc (..., -1.701e+38, ...)
+#             v8: 0x00007d7c0000000000fffeff090501fd (..., 2.351e-38, ...)
+#             v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.000, ...)
+#                                          ╙───────── 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831308584838219180000feffff01 (..., -1.246e-35, ...)
+#            v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.287e-33, ...)
+#            v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.662e-31, ...)
+#            v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.281e-28, ...)
+#                                  ╙───────────────── 0x91908f8e'8d8c8b8a'89888786'85848382 <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0x848382810000000000fffeff090501fd (-3.092e-36, ...)
+#             v9: 0x888786852b2a29280000000000fffeff (-8.157e-34, ...)
+#            v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.150e-31, ...)
+#            v11: 0x908f8e8d00000000fafafafafafafafa (-5.662e-29, ...)
+#                          ╙───────────────────────── 0x908f8e8d'8c8b8a89'88878685'84838281 <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x01010101010101010101010101010101
+#            v15: 0xffffffffffffffffffffffffffffffff
+#            v16: 0x02020202020202020202020202020202
+#            v17: 0x00000000000000000000000000000000
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x91919191919191919191919191919191
+#            v14: 0x92929292929292929292929292929292
+#            v15: 0x93939393939393939393939393939393
+#            v16: 0x94949494949494949494949494949494
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x94'93'92'91 <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0x90909090909090909090909090909090
+#            v10: 0x91919191919191919191919191919191
+#            v11: 0x92929292929292929292929292929292
+#            v12: 0x93939393939393939393939393939393
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x93'92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xff0000850002ff01 (-5.487e+303)
+#             d9:                 0x0000000000fffeff (8.289e-317)
+#            d10:                 0x1700000000000000 (6.689e-198)
+#            d11:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x9b9a999897969594 (-1.050e-175)
+#             d5:                 0xa3a2a1a09f9e9d9c (-5.007e-137)
+#             d6:                 0xabaaa9a8a7a6a5a4 (-2.438e-98)
+#             d7:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac'abaaa9a8a7a6a5a4'a3a2a1a09f9e9d9c'9b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x9a99989796959493 (-1.542e-180)
+#            d27:                 0xa2a1a09f9e9d9c9b (-7.228e-142)
+#            d28:                 0xaaa9a8a7a6a5a4a3 (-3.580e-103)
+#            d29:                 0xb2b1b0afaeadacab (-1.680e-64)
+#                                                  ╙─ 0xb2b1b0afaeadacab'aaa9a8a7a6a5a4a3'a2a1a09f9e9d9c9b'9a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v20: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v21: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#            v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.568e-159, 8.568e-159)
+#                                  ╙───────────────╨─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.311e-26, -8.311e-26)
+#            v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.904e+13, -3.904e+13)
+#            v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.929e+52, -1.929e+52)
+#            v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.073e+90, -9.073e+90)
+#                                  ╙───────────────╨─ 0xd2d1d0cfcecdcccb'cac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.219e-30, -1.219e-30)
+#            v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.620e+08, -5.620e+08)
+#            v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.829e+47, -2.829e+47)
+#            v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.306e+86, -1.306e+86)
+#                                  ╙───────────────╨─ 0xd1d0cfcecdcccbca'c9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#             d0:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#             d1:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#             d2:                 0x0000000000000000 (0.000, 0.000)
+#                                          ╙───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xd5d4d3d2d5d4d3d2 (-2.925e+13, -2.925e+13)
+#            d29:                 0xd9d8d7d6d9d8d7d6 (-7.629e+15, -7.629e+15)
+#            d30:                 0xdddcdbdadddcdbda (-1.989e+18, -1.989e+18)
+#            d31:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#                                          ╙───────╨─ 0xe1e0dfde'dddcdbda'd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xd4d3d2d1d4d3d2d1 (-7.278e+12, -7.278e+12)
+#            d12:                 0xd8d7d6d5d8d7d6d5 (-1.899e+15, -1.899e+15)
+#            d13:                 0xdcdbdad9dcdbdad9 (-4.951e+17, -4.951e+17)
+#            d14:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#                                          ╙───────╨─ 0xe0dfdedd'dcdbdad9'd8d7d6d5'd4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d20:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d21:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            d22:                 0xff00ff00ff00ff00 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
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+#            d23:                 0xe4e3e4e3e4e3e4e3 (-1251., -1251., -1251., -1251.)
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+#                                      ╙───╨───╨───╨─ 0xe8e7'e6e5'e4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xe1e0e1e0e1e0e1e0 (-752.0, -752.0, -752.0, -752.0)
+#            d21:                 0xe3e2e3e2e3e2e3e2 (-1009., -1009., -1009., -1009.)
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+#                                      ╙───╨───╨───╨─ 0xe7e6'e5e4'e3e2'e1e0 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────╨───────╨───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────╨───────╨───────╨─ 0xf7f6f5f4'f3f2f1f0'efeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────╨───────╨───────╨─ 0xf6f5f4f3'f2f1f0ef'eeedeceb'eae9e8e7 <- 0x~~~~~~~~~~~~~~~~
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+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
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+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8'f7 <- 0x~~~~~~~~~~~~~~~~
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+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xf9'f8'f7'f6 <- 0x~~~~~~~~~~~~~~~~
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+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0100'fffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
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+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
+#
+#   z22<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x0000000000000000000000000000007f
+#                                  ║               ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
+#
+#   z23<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#
+#   z24<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
+#
+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
+#
+#   z21<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#     z21<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║   ║ ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<255:128>: 0x000000000000002f0000290000230000
+#   z21<255:128>: 0x00000000000000002e00000000002200
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+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x2e'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x0000007f007f00000000000000000000
+#   z21<383:256>: 0x00000000800000000000000000000000
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+#                    ║ ║ ║ ╙───────────────────────── 0x00'7f <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z20<511:384>: 0x00000000000000000000000000000000
+#   z21<511:384>: 0x00000000000000000000000000000000
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f800000'7f800000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#     z24<127:0>: 0x00000000000000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'7f8000007f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z24<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x0000000000000000000000ff00000000
+#     z25<127:0>: 0xa000000000000000000000ffc0000000
+#     z26<127:0>: 0x3700000000000000000000007f000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x7f'c0'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'ff'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x37'a0'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<639:512>: 0x00000000000000000000000000000000
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z25<127:0>: 0x292823221d1c17160000000000000000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z26<127:0>: 0x2b2a25241f1e191813120d0c07060100 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z27<127:0>: 0x2d2c272621201b1a1514000009080000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0100'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0908'0706'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0d0c'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514'1312'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1b1a'1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2120'1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x595853524d4c474641403b3a35342f2e (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z26<255:128>: 0x5b5a55544f4e494843423d3c37363130 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z27<255:128>: 0x5d5c575651504b4a45443f3e39383332 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3332'3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3938'3736'3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544'4342'4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4b4a'4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5150'4f4e'4d4c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c'5b5a'5958 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x898883827d7c777671706b6a65645f5e (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z26<383:256>: 0x8b8a85847f7e797873726d6c67666160 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z27<383:256>: 0x8d8c878681807b7a75746f6e69686362 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x6362'6160'5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6968'6766'6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6f6e'6d6c'6b6a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x7574'7372'7170 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7b7a'7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x8180'7f7e'7d7c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x8786'8584'8382 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8d8c'8b8a'8988 <- 0x~~~~~~~~~~~~~~~~
+#   z25<511:384>: 0xb9b8b3b2adaca7a6a1a09b9a95948f8e (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#   z26<511:384>: 0xbbbab5b4afaea9a8a3a29d9c97969190 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#   z27<511:384>: 0xbdbcb7b6b1b0abaaa5a49f9e99989392 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x9392'9190'8f8e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x9998'9796'9594 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x9f9e'9d9c'9b9a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xa5a4'a3a2'a1a0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xabaa'a9a8'a7a6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xb1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xb7b6'b5b4'b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xbdbc'bbba'b9b8 <- 0x~~~~~~~~~~~~~~~~
+#   z25<639:512>: 0xe9e8e3e2dddcd7d6d1d0cbcac5c4bfbe (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#   z26<639:512>: 0xebeae5e4dfded9d8d3d2cdccc7c6c1c0 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#   z27<639:512>: 0xedece7e6e1e0dbdad5d4cfcec9c8c3c2 (-3024., -1009., -375.0, -125.4, -46.50, -15.58, -5.766, -1.936)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xc3c2'c1c0'bfbe <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xc9c8'c7c6'c5c4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xcfce'cdcc'cbca <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd5d4'd3d2'd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xdbda'd9d8'd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xe1e0'dfde'dddc <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xe7e6'e5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#     z26<127:0>: 0x00000000000000000000ffff00000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z27<127:0>: 0x00000000000000007fff000000000000 (0.000, 0.000, 9.183e-41, 0.000)
+#     z28<127:0>: 0x37a0000000000000000000007fc00000 (0.000, 0.000, 9.183e-41, 0.000)
+#                          ║       ║       ║       ╙─ 0x7fc00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'7fff0000'0000ffff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x37a00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z26<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z27<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z27<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#     z28<127:0>: 0x00000000000000000000ffff7fc00000 (0.000, 0.000)
+#     z29<127:0>: 0x37a0000000000000000000007fff0000 (0.000, 0.000)
+#                                  ║               ╙─ 0x000000007fff0000'0000ffff7fc00000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x37a0000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z27<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z28<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#     z26<127:0>: 0x00000000000000000000000400000000
+#     z27<127:0>: 0x0080000000800000000000ff00000000
+#     z28<127:0>: 0x007f0000007f0000000000ff00000000
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+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x7f'80'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z25<639:512>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'ffff'3fb5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ╙───────── 0x7f800000'00000000'7f800000'00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x5b5a5958'57565554'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x0b0a0908'07060504'03020100'fffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1b1a1918'17161514'13121110'0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928'27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3b3a3938'37363534'33323130'2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x00000000ffff3fb5'00000000ffff04f3'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x000000007f800000'0000000000000000'000000007f800000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#   z31<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z29<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z30<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z31<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z28<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z29<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z30<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z31<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
diff --git a/test/test-trace-reference/log-vregs-colour b/test/test-trace-reference/log-vregs-colour
index 0b71fc90..31d1c24c 100644
--- a/test/test-trace-reference/log-vregs-colour
+++ b/test/test-trace-reference/log-vregs-colour
@@ -1,2304 +1,5371 @@
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0b0a09080706050403020100fffefdfc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xfbfaf9f8f7f6f5f4f3f2f1f0efeeedec
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfb <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xebeae9e8e7e6e5e4e3e2e1e0dfdedddc
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xeb <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0xdbdad9d8d7d6d5d4d3d2d1d0cfce0001
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xdb <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0x0a09080706050403020100fffefdfcfb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xfc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xfd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x05 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x06 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x09 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x0a <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfaf9f8f7f6f5f4f3f2f1f0efeeedeceb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xeb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xec <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xed <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xee <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xef <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xf0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xf1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xf2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xf3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xf4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xf5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xf6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xf7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xf8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xf9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xfa <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xeae9e8e7e6e5e4e3e2e1e0dfdedddcdb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xdb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xdc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xdd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xde <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xdf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xe0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xe1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xe2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xe3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xe4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xe5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xe6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xe7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xe8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xe9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xea <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0xdad9d8d7d6d5d4d3d2d1d0cfcecdcccb
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0xd1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xd2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xd3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xd4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xd5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xd6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xd7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xd8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xd9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xda <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2f2e2d2c2b2a29282726252423222120
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x1f1e1d1c1b1a19181700000000000000
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x0000000000fffeffff0000850002ff01
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x3a393837363534333231302f2e2d2c2b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3a <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x2a292827262524232221201f1e1d1c1b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x1a191817161514131211100f0e0d0c0b
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x393837363534333231302f2e2d2c2b2a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x2a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x2d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x2e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x31 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x32 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x35 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x36 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x39 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x292827262524232221201f1e1d1c1b1a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x25 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x28 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x29 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x191817161514131211100f0e0d0c0b0a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x0a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x0e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x11 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x12 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x15 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x16 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x19 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1e <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x0000000000fffeffff0000850002ff01
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xfe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x595857565554535251504f4e4d4c4b4a
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x4a <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x59 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x3a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x3b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x3c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x3d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x3e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x3f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x40 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x41 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x42 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x43 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x44 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x45 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x46 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x47 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x48 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x49 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x4a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x4b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x4c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x4d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x4e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x4f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x50 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x51 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x52 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x53 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x54 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x55 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x56 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x57 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x58 <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
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+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x5a <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x2726252423222120 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x2726252423222120 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x0908070605040302 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0xf9f8f7f6f5f4f3f2 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x1700000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x5a595857 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x5251504f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x56555453 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x8281807f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x86858483 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x7a797877 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7e7d7c7b <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x7271706f <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x85848382 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x79787776 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x7d7c7b7a <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x71706f6e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x75747372 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x91908f8e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x95949392 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x89888786 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8d8c8b8a <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x94939291 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x98979695 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99 <- 0x~~~~~~~~~~~~~~~~
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+#                                          ║       ╙─ 0x97969594 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9b9a9998 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x1918 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ╙───────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
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+#            d17:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xb5b4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb7b6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb9b8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xadac <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xafae <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb1b0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb3b2 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xa5a4 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0xa9a8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xabaa <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0x9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9f9e <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa1a0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa3a2 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xbab9b8b7b6b5b4b3 (-0.8403, -0.5894, -0.4192, -0.2937)
+#                                      ║   ║   ║   ╙─ 0xb4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xb6b5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb8b7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbab9 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xacab <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xaead <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb0af <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xb2b1 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xa4a3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xa6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa8a7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xaaa9 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xa2a1a09f9e9d9c9b (-0.01295, -0.009026, -0.006458, -0.004498)
+#                                      ║   ║   ║   ╙─ 0x9c9b <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xa09f <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xa2a1 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0x1700000000000000 (0.001709, 0.000, 0.000, 0.000)
+#                                      ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            d30:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xcccb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcecd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xc4c3 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ╙───────── 0xc8c7 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xcac9 <- 0x~~~~~~~~~~~~~~~~
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+#                                      ║   ║   ║   ╙─ 0xbcbb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbebd <- 0x~~~~~~~~~~~~~~~~
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+#                                      ╙───────────── 0xc2c1 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0xd1d0cfcecdcccbca (-46.50, -31.22, -23.19, -15.58)
+#                                      ║   ║   ║   ╙─ 0xcbca <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xcdcc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xcfce <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xc9c8c7c6c5c4c3c2 (-11.56, -7.773, -5.766, -3.879)
+#                                      ║   ║   ║   ╙─ 0xc3c2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xc5c4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xc7c6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xc9c8 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xc1c0bfbebdbcbbba (-2.875, -1.936, -1.434, -0.9658)
+#                                      ║   ║   ║   ╙─ 0xbbba <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xbdbc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xbfbe <- 0x~~~~~~~~~~~~~~~~
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+#             d4:                 0x0000000000fffeff (0.000, 0.000, 1.520e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xe1e0dfdedddcdbda (-752.0, -503.5, -375.0, -251.2)
+#                                      ║   ║   ║   ╙─ 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#             d3:                 0xd9d8d7d6d5d4d3d2 (-187.0, -125.4, -93.25, -62.56)
+#                                      ║   ║   ║   ╙─ 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0xe0dfdedddcdbdad9 (-623.5, -439.2, -310.8, -219.1)
+#                                      ║   ║   ║   ╙─ 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xd8d7d6d5d4d3d2d1 (-154.9, -109.3, -77.19, -54.53)
+#                                      ║   ║   ║   ╙─ 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (nan, 7.927e-06, 1.192e-07, nan)
+#                                      ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe8e7e6e5e4e3e2e1 (-2510., -1765., -1251., -880.5)
+#                                      ║   ║   ║   ╙─ 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0xe7e6e5e4e3e2e1e0 (-2022., -1508., -1009., -752.0)
+#                                      ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x3f3e3d3c3b3a39383736353433323130 (0.7431, 0.002842, 1.086e-05, 4.149e-08)
+#                          ║       ║       ║       ╙─ 0x33323130 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x37363534 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3b3a3938 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            v31: 0x27262524232221201f1e1d1c1b1a1918 (2.306e-15, 8.789e-18, 3.348e-20, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x17161514131211100f0e0d0c0b0a0908 (4.849e-25, 1.844e-27, 7.004e-30, 2.658e-32)
+#                          ║       ║       ║       ╙─ 0x0b0a0908 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0f0e0d0c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x17161514 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfbfaf9f8 (1.008e-34, 3.820e-37, nan, -2.606e+36)
+#                          ║       ║       ║       ╙─ 0xfbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfffefdfc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x03020100 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xf7f6f5f4f3f2f1f0efeeedecebeae9e8 (-1.002e+34, -3.850e+31, -1.479e+29, -5.680e+26)
+#                          ║       ║       ║       ╙─ 0xebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xefeeedec <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf7f6f5f4 <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x262524232221201f1e1d1c1b1a191817 (5.729e-16, 2.184e-18, 8.317e-21, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2221201f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x26252423 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x161514131211100f0e0d0c0b0a090807 (1.204e-25, 4.577e-28, 1.739e-30, 6.598e-33)
+#                          ║       ║       ║       ╙─ 0x0a090807 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0e0d0c0b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x16151413 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x06050403020100fffefdfcfbfaf9f8f7 (2.502e-35, 9.478e-38, -1.688e+38, -6.490e+35)
+#                          ║       ║       ║       ╙─ 0xfaf9f8f7 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xfefdfcfb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x020100ff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x06050403 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xf6f5f4f3f2f1f0efeeedecebeae9e8e7 (-2.494e+33, -9.584e+30, -3.682e+28, -1.414e+26)
+#                          ║       ║       ║       ╙─ 0xeae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xeeedeceb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xf2f1f0ef <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xf6f5f4f3 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2f2e2d2c2b2a29282726252423222120 (1.584e-10, 6.045e-13, 2.306e-15, 8.789e-18)
+#                          ║       ║       ║       ╙─ 0x23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1f1e1d1c1b1a19181700000000000000 (3.348e-20, 1.275e-22, 4.136e-25, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x0000000000fffeffff0000850002ff01 (0.000, 2.351e-38, -1.701e+38, 2.751e-40)
+#                          ║       ║       ║       ╙─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xff000085 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x565554535251504f4e4d4c4b4a494847 (5.864e+13, 2.247e+11, 8.611e+08, 3.298e+06)
+#                          ║       ║       ║       ╙─ 0x4a494847 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x4e4d4c4b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x5251504f <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x56555453 <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0x464544434241403f3e3d3c3b3a393837 (1.263e+04, 48.31, 0.1848, 0.0007066)
+#                          ║       ║       ║       ╙─ 0x3a393837 <- 0x~~~~~~~~~~~~~~~~
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+#                                    ║ ║ ║ ║ ║ ╙───── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xc8c7c6c5c4c3c2c1
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc1 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc2 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xc3 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xc4 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xc5 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xc6 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xc7 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xc0bfbebdbcbbbab9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xb9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xba <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xbb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xbc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xbd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xbe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xbf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xc0 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0xff0000850002ff01
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xff <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xd0cfcecdcccbcac9
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xd0 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xcfcecdcccbcac9c8
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xc8 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xc9 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xca <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xcb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xcc <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0xcd <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0xce <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0xcf <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0x3f3e3d3c3b3a39383736353433323130 (1.811, 1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x0f0e0d0c0b0a09080706050403020100 (0.0004306, 0.0003080, 0.0002148, 0.0001535, 0.0001072, 7.653e-05, 4.590e-05, 1.526e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0100 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0302 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0504 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0706 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0908 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0b0a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0d0c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0xfffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 (nan, nan, -6.534e+04, -4.890e+04, -3.261e+04, -2.438e+04, -1.627e+04, -1.216e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf1f0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf3f2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf5f4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf7f6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfbfa <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfdfc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfffe <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0xefeeedecebeae9e8e7e6e5e4e3e2e1e0 (-8120., -6064., -4052., -3024., -2022., -1508., -1009., -752.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe1e0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe3e2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe5e4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe7e6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe9e8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xebea <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xedec <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xefee <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0xdfdedddcdbdad9d8d7d6d5d4d3d2d1d0 (-503.5, -375.0, -251.2, -187.0, -125.4, -93.25, -62.56, -46.50)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd1d0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd3d2 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd5d4 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd7d6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd9d8 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdbda <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdddc <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdfde <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b0a09080706050403020100ff (0.0003693, 0.0002468, 0.0001842, 0.0001229, 9.185e-05, 6.121e-05, 3.058e-05, 1.520e-05)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0201 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0403 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0605 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0807 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0a09 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0c0b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0e0d <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f3f2f1f0ef (nan, nan, -5.712e+04, -4.067e+04, -2.850e+04, -2.027e+04, -1.422e+04, -1.010e+04)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xf0ef <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xf2f1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xf4f3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xf6f5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xf8f7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xfcfb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xfefd <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xeeedecebeae9e8e7e6e5e4e3e2e1e0df (-7092., -5036., -3538., -2510., -1765., -1251., -880.5, -623.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xe0df <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xe2e1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xe4e3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xe6e5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xe8e7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xeae9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xeceb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xeeed <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xdedddcdbdad9d8d7d6d5d4d3d2d1d0cf (-439.2, -310.8, -219.1, -154.9, -109.3, -77.19, -54.53, -38.47)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xd0cf <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xd2d1 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0xd4d3 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xd6d5 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xd8d7 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xdad9 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xdcdb <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xdedd <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x2f2e2d2c2b2a29282726252423222120 (0.1122, 0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3e3d3c3b3a393837363534333231302f (1.560, 1.058, 0.7778, 0.5269, 0.3879, 0.2625, 0.1935, 0.1307)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x302f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3433 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3635 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3837 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3c3b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x2e2d2c2b2a292827262524232221201f (0.09650, 0.06512, 0.04813, 0.03244, 0.02400, 0.01616, 0.01197, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2e2d <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x1e1d1c1b1a191817161514131211100f (0.005970, 0.004009, 0.002977, 0.001997, 0.001485, 0.0009947, 0.0007405, 0.0004954)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x100f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1211 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1413 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1615 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1e1d <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a393837363534333231302f2e (1.309, 0.9033, 0.6523, 0.4507, 0.3252, 0.2249, 0.1621, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x3736 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x3938 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3d3c <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2d2c2b2a292827262524232221201f1e (0.08081, 0.05597, 0.04028, 0.02792, 0.02008, 0.01393, 0.01001, 0.006950)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x1d1c1b1a191817161514131211100f0e (0.004990, 0.003468, 0.002487, 0.001730, 0.001240, 0.0008631, 0.0006180, 0.0004306)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0f0e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1110 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1312 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x1f1e1d1c1b1a19181700000000000000 (0.006950, 0.004990, 0.003468, 0.002487, 0.001709, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x5d5c5b5a595857565554535251504f4e (343.0, 235.2, 171.0, 117.4, 85.25, 58.56, 42.50, 29.22)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4f4e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5150 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5554 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5958 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5b5a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857565554535251504f4e4d (278.8, 203.1, 138.9, 101.3, 69.19, 50.53, 34.47, 25.20)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x4e4d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x504f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x5251 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x5453 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5857 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5a59 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5c5b <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x4c4b4a494847464544434241403f3e3d (17.17, 12.57, 8.555, 6.270, 4.262, 3.127, 2.123, 1.560)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3e3d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x403f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4443 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4645 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4c4b <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0x0000000000fffeffff0000850002ff01 (0.000, 0.000, 1.520e-05, nan, nan, 7.927e-06, 1.192e-07, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0002 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xfeff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x00ff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a696867666564636261605f5e5d (4524., 3282., 2254., 1637., 1123., 816.5, 559.5, 407.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5e5d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6463 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6665 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6a69 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6c6b <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x6b6a696867666564636261605f5e5d5c (3796., 2768., 1894., 1380., 945.0, 688.0, 471.5, 343.0)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6160 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x6766 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x6b6a <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3a39383736353433323130012e
+#                                                ╙─── 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xfefdfcfbfaf9f8f7f6f5f4f36cf1f0ef
+#                                            ╙─────── 0x6c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x6c6b6a6b6867666564636261605f5e5d
+#                          ╙───────────────────────── 0x6b <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d3d2d1d0cf (-5.487e+303, ...)
+#                                  ╙───────────────── 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x737271706f6e6d6c636261605f5e5d5c (1.290e+248, ...)
+#                                  ╙───────────────── 0x737271706f6e6d6c <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x7271706f6e6d6c6b2726252423222120 (1.861e+243, ...)
+#                                  ╙───────────────── 0x7271706f6e6d6c6b <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x3d3c3b3aff013736353433323130012e (..., nan, ...)
+#                              ╙───────────────────── 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0xff0000850002ff01d6d5d4d37473d0cf (..., 1.822e+04, ...)
+#                                              ╙───── 0x7473 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5c5b5a595857737254535251504f4e4d (..., 1.525e+04, ...)
+#                                  ╙───────────────── 0x7372 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x4d4c4b4a0002ff014544434241403f3e (..., 2.751e-40, ...)
+#                                  ╙───────────────── 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x0e0d0c0b7776757406050403020100ff (..., 4.999e+33, ...)
+#                                  ╙───────────────── 0x77767574 <- 0x~~~~~~~~~~~~~~~~
+#             v1: 0x0000000076757473e8e7e6e5e4e3e2e1 (..., 1.245e+33, ...)
+#                                  ╙───────────────── 0x76757473 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x01010101010101010101010101010101
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x77777777777777777777777777777777
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x77 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x76767676767676767676767676767676
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x76 <- 0x~~~~~~~~~~~~~~~~
+#            d25:                 0xff0000850002ff01 (-5.487e+303)
+#                                                  ╙─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7e7d7c7b7a797877 (1.975e+301)
+#                                                  ╙─ 0x7e7d7c7b7a797877 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x7d7c7b7a79787776 (2.911e+296)
+#                                                  ╙─ 0x7d7c7b7a79787776 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#                                  ╙───────────────╨─ 0xff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8584838281807f7e8584838281807f7e (-4.414e-282, -4.414e-282)
+#                                  ╙───────────────╨─ 0x8584838281807f7e <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84838281807f7e7d84838281807f7e7d (-6.406e-287, -6.406e-287)
+#                                  ╙───────────────╨─ 0x84838281807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#                                          ╙───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x8887868588878685 (-8.157e-34, -8.157e-34)
+#                                          ╙───────╨─ 0x88878685 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x8786858487868584 (-2.024e-34, -2.024e-34)
+#                                          ╙───────╨─ 0x87868584 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x8988898889888988 (-0.0001688, -0.0001688, -0.0001688, -0.0001688)
+#                                      ╙───╨───╨───╨─ 0x8988 <- 0x~~~~~~~~~~~~~~~~
+#            d21:                 0x8887888788878887 (-0.0001382, -0.0001382, -0.0001382, -0.0001382)
+#                                      ╙───╨───╨───╨─ 0x8887 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#                          ╙───────╨───────╨───────╨─ 0x0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x8c8b8a898c8b8a898c8b8a898c8b8a89 (-2.150e-31, -2.150e-31, -2.150e-31, -2.150e-31)
+#                          ╙───────╨───────╨───────╨─ 0x8c8b8a89 <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0x8b8a89888b8a89888b8a89888b8a8988 (-5.336e-32, -5.336e-32, -5.336e-32, -5.336e-32)
+#                          ╙───────╨───────╨───────╨─ 0x8b8a8988 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x01 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x8c8c8c8c8c8c8c8c
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8c <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0x8b8b8b8b8b8b8b8b
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x8b <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x8d8c8d8c8d8c8d8c8d8c8d8c8d8c8d8c (-0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386, -0.0003386)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8d8c <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x8c8b8c8b8c8b8c8b8c8b8c8b8c8b8c8b (-0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773, -0.0002773)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8c8b <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1e1c1a18000000000000ffff00850201
+#            v22: 0x1f1d1b1917000000000000feff0000ff
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x17'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x1b'1a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x1f'1e <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#            v22: 0xacaaa8a6a4a2a09e9c9a98969492908e
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x92'91 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x98'97 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa4'a3 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaa'a9 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xac'ab <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xaaa8a6a4a2a09e9c9a98969492908e8c
+#            v13: 0xaba9a7a5a3a19f9d9b99979593918f8d
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x8f'8e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x95'94 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa1'a0 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xa7'a6 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xa9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xab'aa <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x1700000000000000ff0000850002ff01 (6.689e-198, -5.487e+303)
+#            v15: 0x1f1e1d1c1b1a19180000000000fffeff (8.568e-159, 8.289e-317)
+#                                  ║               ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0xc3c2c1c0bfbebdbcb3b2b1b0afaeadac (-2.703e+18, -1.163e-59)
+#             v1: 0xcbcac9c8c7c6c5c4bbbab9b8b7b6b5b4 (-1.314e+57, -5.659e-21)
+#                                  ║               ╙─ 0xbbbab9b8b7b6b5b4'b3b2b1b0afaeadac <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcbcac9c8c7c6c5c4'c3c2c1c0bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xc2c1c0bfbebdbcbbb2b1b0afaeadacab (-3.904e+13, -1.680e-64)
+#            v13: 0xcac9c8c7c6c5c4c3bab9b8b7b6b5b4b3 (-1.929e+52, -8.311e-26)
+#                                  ║               ╙─ 0xbab9b8b7b6b5b4b3'b2b1b0afaeadacab <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00fffeff0002ff01 (2.351e-38, 2.751e-40)
+#            d28:                 0x00000000ff000085 (0.000, -1.701e+38)
+#                                          ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xd6d5d4d3cecdcccb (-1.176e+14, -1.726e+09)
+#             d3:                 0xdad9d8d7d2d1d0cf (-3.066e+16, -4.506e+11)
+#                                          ║       ╙─ 0xd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xdad9d8d7'd6d5d4d3 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0xd5d4d3d2cdcccbca (-2.925e+13, -4.295e+08)
+#            d13:                 0xd9d8d7d6d1d0cfce (-7.629e+15, -1.121e+11)
+#                                          ║       ╙─ 0xd1d0cfce'cdcccbca <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x0000feff0085ff01 (0.000, nan, 7.927e-06, nan)
+#            d10:                 0x000000ffff000002 (0.000, 1.520e-05, nan, 1.192e-07)
+#                                      ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe7e6e3e2dfdedbda (-2022., -1009., -503.5, -251.2)
+#            d24:                 0xe9e8e5e4e1e0dddc (-3024., -1508., -752.0, -375.0)
+#                                      ║   ║   ║   ╙─ 0xdddc'dbda <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe1e0'dfde <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe5e4'e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe9e8'e7e6 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0xe6e5e2e1dedddad9 (-1765., -880.5, -439.2, -219.1)
+#             d2:                 0xe8e7e4e3e0dfdcdb (-2510., -1251., -623.5, -310.8)
+#                                      ║   ║   ║   ╙─ 0xdcdb'dad9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xe0df'dedd <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xe4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xe8e7'e6e5 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x1b1a19180000000000fffeff0002ff01 (1.275e-22, 0.000, 2.351e-38, 2.751e-40)
+#            v21: 0x1f1e1d1c1700000000000000ff000085 (3.348e-20, 4.136e-25, 0.000, -1.701e+38)
+#                          ║       ║       ║       ╙─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00fffeff <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v10: 0x04030201fcfbfaf9f4f3f2f1ecebeae9 (1.540e-36, -1.047e+37, -1.546e+32, -2.282e+27)
+#            v11: 0x0807060500fffefdf8f7f6f5f0efeeed (4.063e-34, 2.351e-38, -4.023e+34, -5.940e+29)
+#                          ║       ║       ║       ╙─ 0xf0efeeed'ecebeae9 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf8f7f6f5'f4f3f2f1 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00fffefd'fcfbfaf9 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x08070605'04030201 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x03020100fbfaf9f8f3f2f1f0ebeae9e8 (3.820e-37, -2.606e+36, -3.850e+31, -5.680e+26)
+#            v25: 0x07060504fffefdfcf7f6f5f4efeeedec (1.008e-34, nan, -1.002e+34, -1.479e+29)
+#                          ║       ║       ║       ╙─ 0xefeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xf7f6f5f4'f3f2f1f0 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xfffefdfc'fbfaf9f8 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x07060504'03020100 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0x0000ffff00850201
+#            d18:                 0x000000feff0000ff
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0xff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0xfe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#            d13:                 0x161412100e0c0a08
+#            d14:                 0x171513110f0d0b09
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x09'08 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x11'10 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'16 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x1513110f0d0b0907
+#             d8:                 0x161412100e0c0a08
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x0a'09 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0e'0d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x16'15 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c1918000000000000feff0085ff01 (0.004990, 0.002487, 0.000, 0.000, 0.000, nan, 7.927e-06, nan)
+#            v31: 0x1f1e1b1a17000000000000ffff000002 (0.006950, 0.003468, 0.001709, 0.000, 0.000, 1.520e-05, nan, 1.192e-07)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0xff00'0085 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x1700'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x3433302f2c2b28272423201f1c1b1817 (0.2625, 0.1307, 0.06512, 0.03244, 0.01616, 0.008049, 0.004009, 0.001997)
+#             v5: 0x363532312e2d2a29262522211e1d1a19 (0.3879, 0.1935, 0.09650, 0.04813, 0.02400, 0.01197, 0.005970, 0.002977)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1a19'1817 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1e1d'1c1b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2221'201f <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2625'2423 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2a29'2827 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2e2d'2c2b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3231'302f <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3635'3433 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x33322f2e2b2a272623221f1e1b1a1716 (0.2249, 0.1122, 0.05597, 0.02792, 0.01393, 0.006950, 0.003468, 0.001730)
+#            v14: 0x353431302d2c2928252421201d1c1918 (0.3252, 0.1621, 0.08081, 0.04028, 0.02008, 0.01001, 0.004990, 0.002487)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2928'2726 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x363532012e2d2a29262522211e1d1a19
+#             v6: 0x1f1e1dff1b1a19181700000000000000
+#                          ╙───────────────────────── 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x4544434241403f3e363c3b3a39383736
+#            v17: 0x00000000000000003700ffff00850201
+#                                    ╙─────────────── 0x37'36 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0706050403020100fffefdfcfb35f9f8
+#            v30: 0x1d1c1918000000000000feff0036ff01
+#                                              ╙───── 0x36'35 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01f8f7f6f5f0efeeed (-5.487e+303, ...)
+#            v12: 0x0000000000fffeffd5d4d3d2cdcccbca (8.289e-317, ...)
+#                                  ╙───────────────── 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x00000000000000003e3d3c3b3a393837 (..., 6.807e-09)
+#            v27: 0x0000000000000000464544434241403f (..., 3.370e+30)
+#                                                  ╙─ 0x464544434241403f'3e3d3c3b3a393837 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x07060504fffefdfc3d3c3b3a39383736 (..., 1.003e-13)
+#            v26: 0x00000000000000004544434241403f3e (..., 4.899e+25)
+#                                                  ╙─ 0x4544434241403f3e'3d3c3b3a39383736 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0xff01000000000000000000feff0000ff (nan, ...)
+#            v19: 0x00020000000000008b8b8b8b8b8b8b8b (1.192e-07, ...)
+#                      ╙───────────────────────────── 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v17: 0x00000000474600003700ffff00850201 (..., 7.273, ...)
+#            v18: 0xff01000049480000000000feff0000ff (..., 10.56, ...)
+#                              ╙───────────────────── 0x4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x1d1c191800000000000046450036ff01 (..., 6.270, ...)
+#            v31: 0x1f1e1b1a1700000000004847ff000002 (..., 8.555, ...)
+#                                          ╙───────── 0x4847'4645 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x0002ff0103020100fffefdfcfb35f9f8 (2.751e-40, ...)
+#            v30: 0xff00008500000000000046450036ff01 (-1.701e+38, ...)
+#                          ╙───────────────────────── 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x0000000000000000000000004c4b4a49 (..., 5.329e+07)
+#            v29: 0x0002ff0103020100fffefdfc504f4e4d (..., 1.391e+10)
+#                                                  ╙─ 0x504f4e4d'4c4b4a49 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x1f1e1dff1b1a19184b4a494800000000 (..., 1.326e+07, ...)
+#             v7: 0x00000000000000004f4e4d4c0d0b0907 (..., 3.461e+09, ...)
+#                                          ╙───────── 0x4f4e4d4c'4b4a4948 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x01010101010101010101010101010101
+#            v27: 0xffffffffffffffffffffffffffffffff
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x50505050505050505050505050505050
+#            v22: 0x51515151515151515151515151515151
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x51'50 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f4f
+#             v6: 0x50505050505050505050505050505050
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x50'4f <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xff0000850002ff01 (-5.487e+303)
+#            d27:                 0x0000000000fffeff (8.289e-317)
+#                                                  ╙─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d14:                 0x5857565554535251 (3.678e+117)
+#            d15:                 0x605f5e5d5c5b5a59 (1.682e+156)
+#                                                  ╙─ 0x605f5e5d5c5b5a59'5857565554535251 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0x5756555453525150 (5.371e+112)
+#            d24:                 0x5f5e5d5c5b5a5958 (2.485e+151)
+#                                                  ╙─ 0x5f5e5d5c5b5a5958'5756555453525150 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v12: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#                                  ╙───────────────╨─ 0x0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x67666564636261606766656463626160 (1.247e+190, 1.247e+190)
+#            v30: 0x6f6e6d6c6b6a69686f6e6d6c6b6a6968 (5.766e+228, 5.766e+228)
+#                                  ╙───────────────╨─ 0x6f6e6d6c6b6a6968'6766656463626160 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x666564636261605f666564636261605f (1.818e+185, 1.818e+185)
+#            v16: 0x6e6d6c6b6a6968676e6d6c6b6a696867 (8.509e+223, 8.509e+223)
+#                                  ╙───────────────╨─ 0x6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d27:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#                                          ╙───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x7271706f7271706f (4.782e+30, 4.782e+30)
+#            d23:                 0x7675747376757473 (1.245e+33, 1.245e+33)
+#                                          ╙───────╨─ 0x76757473'7271706f <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x71706f6e71706f6e (1.191e+30, 1.191e+30)
+#             d3:                 0x7574737275747372 (3.099e+32, 3.099e+32)
+#                                          ╙───────╨─ 0x75747372'71706f6e <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#             d3:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                                      ╙───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d9:                 0x7776777677767776 (3.056e+04, 3.056e+04, 3.056e+04, 3.056e+04)
+#            d10:                 0x7978797879787978 (4.480e+04, 4.480e+04, 4.480e+04, 4.480e+04)
+#                                      ╙───╨───╨───╨─ 0x7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0x7675767576757675 (2.645e+04, 2.645e+04, 2.645e+04, 2.645e+04)
+#             d7:                 0x7877787778777877 (3.658e+04, 3.658e+04, 3.658e+04, 3.658e+04)
+#                                      ╙───╨───╨───╨─ 0x7877'7675 <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#             v8: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#                          ╙───────╨───────╨───────╨─ 0xff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0x7c7b7a797c7b7a797c7b7a797c7b7a79 (5.223e+36, 5.223e+36, 5.223e+36, 5.223e+36)
+#            v20: 0x807f7e7d807f7e7d807f7e7d807f7e7d (-1.171e-38, -1.171e-38, -1.171e-38, -1.171e-38)
+#                          ╙───────╨───────╨───────╨─ 0x807f7e7d'7c7b7a79 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x7b7a79787b7a79787b7a79787b7a7978 (1.301e+36, 1.301e+36, 1.301e+36, 1.301e+36)
+#            v22: 0x7f7e7d7c7f7e7d7c7f7e7d7c7f7e7d7c (3.383e+38, 3.383e+38, 3.383e+38, 3.383e+38)
+#                          ╙───────╨───────╨───────╨─ 0x7f7e7d7c'7b7a7978 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x0101010101010101
+#            d27:                 0xffffffffffffffff
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0x8080808080808080
+#            d21:                 0x8181818181818181
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x81'80 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0x7f7f7f7f7f7f7f7f
+#            d12:                 0x8080808080808080
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x80'7f <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v13: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x82818281828182818281828182818281 (-3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05, -3.821e-05)
+#             v7: 0x84838483848384838483848384838483 (-6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05, -6.884e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8483'8281 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x81808180818081808180818081808180 (-2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05, -2.289e-05)
+#            v26: 0x83828382838283828382838283828382 (-5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05, -5.352e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x2d2a2724211e1b1800000000fe000001
+#            v21: 0x2e2b2825221f1c1900000000ffff85ff
+#            v22: 0x2f2c292623201d1a1700000000ff0002
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x20'1f'1e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x23'22'21 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x2c'2b'2a <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x2f'2e'2d <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v29: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#            v30: 0xb3b0adaaa7a4a19e9b9895928f8c8986
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x89'88'87 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8c'8b'8a <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8f'8e'8d <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x95'94'93 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x98'97'96 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9b'9a'99 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9e'9d'9c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa1'a0'9f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa4'a3'a2 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa7'a6'a5 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xaa'a9'a8 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xad'ac'ab <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb3'b2'b1 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0xb0adaaa7a4a19e9b9895928f8c898683
+#            v21: 0xb1aeaba8a5a29f9c999693908d8a8784
+#            v22: 0xb2afaca9a6a3a09d9a9794918e8b8885
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x85'84'83 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x88'87'86 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x8b'8a'89 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x8e'8d'8c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x91'90'8f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x94'93'92 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x97'96'95 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x9a'99'98 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x9d'9c'9b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0xa0'9f'9e <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0xa3'a2'a1 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0xa6'a5'a4 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0xa9'a8'a7 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0xac'ab'aa <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0xb2'b1'b0 <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x1f1e1d1c1b1a1918ff0000850002ff01 (8.568e-159, -5.487e+303)
+#            v22: 0x27262524232221200000000000fffeff (4.288e-120, 8.289e-317)
+#            v23: 0x2f2e2d2c2b2a29281700000000000000 (1.988e-81, 6.689e-198)
+#                                  ║               ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x2f2e2d2c2b2a2928'2726252423222120'1f1e1d1c1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0xd2d1d0cfcecdcccbbab9b8b7b6b5b4b3 (-9.073e+90, -8.311e-26)
+#            v19: 0xdad9d8d7d6d5d4d3c2c1c0bfbebdbcbb (-4.479e+129, -3.904e+13)
+#            v20: 0xe2e1e0dfdedddcdbcac9c8c7c6c5c4c3 (-2.109e+168, -1.929e+52)
+#                                  ║               ╙─ 0xcac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe2e1e0dfdedddcdb'dad9d8d7d6d5d4d3'd2d1d0cfcecdcccb <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0xd1d0cfcecdcccbcab9b8b7b6b5b4b3b2 (-1.306e+86, -1.219e-30)
+#            v28: 0xd9d8d7d6d5d4d3d2c1c0bfbebdbcbbba (-6.569e+124, -5.620e+08)
+#            v29: 0xe1e0dfdedddcdbdac9c8c7c6c5c4c3c2 (-3.037e+163, -2.829e+47)
+#                                  ║               ╙─ 0xc9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0xe1e0dfdedddcdbda'd9d8d7d6d5d4d3d2'd1d0cfcecdcccbca <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x000000000002ff01 (0.000, 2.751e-40)
+#             d8:                 0x00000000ff000085 (0.000, -1.701e+38)
+#             d9:                 0x1700000000fffeff (4.136e-25, 2.351e-38)
+#                                          ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xf1f0efeee5e4e3e2 (-2.386e+30, -1.351e+23)
+#            d21:                 0xf5f4f3f2e9e8e7e6 (-6.210e+32, -3.520e+25)
+#            d22:                 0xf9f8f7f6edecebea (-1.616e+35, -9.165e+27)
+#                                          ║       ╙─ 0xedecebea'e9e8e7e6'e5e4e3e2 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0xf0efeeede4e3e2e1 (-5.940e+29, -3.363e+22)
+#            d27:                 0xf4f3f2f1e8e7e6e5 (-1.546e+32, -8.761e+24)
+#            d28:                 0xf8f7f6f5ecebeae9 (-4.023e+34, -2.282e+27)
+#                                          ║       ╙─ 0xecebeae9'e8e7e6e5'e4e3e2e1 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x00000000ff00ff01 (0.000, 0.000, nan, nan)
+#            d28:                 0x00000000feff0002 (0.000, 0.000, nan, 1.192e-07)
+#            d29:                 0x1700000000ff0085 (0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                                      ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0x0c0b060500fffaf9 (0.0002468, 9.185e-05, 1.520e-05, -5.712e+04)
+#            d29:                 0x0e0d08070201fcfb (0.0003693, 0.0001229, 3.058e-05, nan)
+#            d30:                 0x100f0a090403fefd (0.0004954, 0.0001842, 6.121e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0403'0201'00ff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0a09'0807'0605 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x100f'0e0d'0c0b <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0x0b0a0504fffef9f8 (0.0002148, 7.653e-05, nan, -4.890e+04)
+#             d8:                 0x0d0c07060100fbfa (0.0003080, 0.0001072, 1.526e-05, -6.534e+04)
+#             d9:                 0x0f0e09080302fdfc (0.0004306, 0.0001535, 4.590e-05, nan)
+#                                      ║   ║   ║   ╙─ 0xfdfc'fbfa'f9f8 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0302'0100'fffe <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x0908'0706'0504 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x0f0e'0d0c'0b0a <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x272625241b1a1918000000000002ff01 (2.306e-15, 1.275e-22, 0.000, 2.751e-40)
+#             v3: 0x2b2a29281f1e1d1c00000000ff000085 (6.045e-13, 3.348e-20, 0.000, -1.701e+38)
+#             v4: 0x2f2e2d2c232221201700000000fffeff (1.584e-10, 8.789e-18, 4.136e-25, 2.351e-38)
+#                          ║       ║       ║       ╙─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x17000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x23222120'1f1e1d1c'1b1a1918 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x2f2e2d2c'2b2a2928'27262524 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x373635342b2a29281f1e1d1c13121110 (1.086e-05, 6.045e-13, 3.348e-20, 1.844e-27)
+#            v25: 0x3b3a39382f2e2d2c2322212017161514 (0.002842, 1.584e-10, 8.789e-18, 4.849e-25)
+#            v26: 0x3f3e3d3c33323130272625241b1a1918 (0.7431, 4.149e-08, 2.306e-15, 1.275e-22)
+#                          ║       ║       ║       ╙─ 0x1b1a1918'17161514'13121110 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x27262524'23222120'1f1e1d1c <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x33323130'2f2e2d2c'2b2a2928 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534 <- 0x~~~~~~~~~~~~~~~~
+#            v11: 0x363534332a2928271e1d1c1b1211100f (2.700e-06, 1.502e-13, 8.317e-21, 4.577e-28)
+#            v12: 0x3a3938372e2d2c2b2221201f16151413 (0.0007066, 3.937e-11, 2.184e-18, 1.204e-25)
+#            v13: 0x3e3d3c3b3231302f262524231a191817 (0.1848, 1.031e-08, 5.729e-16, 3.166e-23)
+#                          ║       ║       ║       ╙─ 0x1a191817'16151413'1211100f <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x26252423'2221201f'1e1d1c1b <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x3231302f'2e2d2c2b'2a292827 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3e3d3c3b'3a393837'36353433 <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0x00000000fe000001
+#            d30:                 0x00000000ffff85ff
+#            d31:                 0x1700000000ff0002
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x00'85'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0xff'ff'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x17'00'00 <- 0x~~~~~~~~~~~~~~~~
+#             d1:                 0x54514e4b4845423f
+#             d2:                 0x55524f4c49464340
+#             d3:                 0x5653504d4a474441
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x41'40'3f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x44'43'42 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x47'46'45 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x4a'49'48 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4d'4c'4b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x50'4f'4e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x53'52'51 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x56'55'54 <- 0x~~~~~~~~~~~~~~~~
+#            d12:                 0x53504d4a4744413e
+#            d13:                 0x54514e4b4845423f
+#            d14:                 0x55524f4c49464340
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x40'3f'3e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x43'42'41 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x46'45'44 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x49'48'47 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x4c'4b'4a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x4f'4e'4d <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x52'51'50 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x55'54'53 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x2b2a25241f1e191800000000ff00ff01 (0.05597, 0.02008, 0.006950, 0.002487, 0.000, 0.000, nan, nan)
+#            v23: 0x2d2c272621201b1a00000000feff0002 (0.08081, 0.02792, 0.01001, 0.003468, 0.000, 0.000, nan, 1.192e-07)
+#            v24: 0x2f2e292823221d1c1700000000ff0085 (0.1122, 0.04028, 0.01393, 0.004990, 0.001709, 0.000, 1.520e-05, 7.927e-06)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x00ff'feff'ff00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1700'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2322'2120'1f1e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2928'2726'2524 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e696863625d5c5756 (-2.289e-05, 6.125e+04, 2.234e+04, 7608., 2768., 945.0, 343.0, 117.4)
+#            v14: 0x83827d7c777671706b6a65645f5e5958 (-5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5, 171.0)
+#            v15: 0x85847f7e797873726d6c676661605b5a (-8.416e-05, nan, 4.480e+04, 1.525e+04, 5552., 1894., 688.0, 235.2)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5b5a'5958'5756 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6160'5f5e'5d5c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6766'6564'6362 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6d6c'6b6a'6968 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7372'7170'6f6e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7978'7776'7574 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8584'8382'8180 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x807f7a7974736e6d686762615c5b5655 (-7.570e-06, 5.302e+04, 1.822e+04, 6580., 2254., 816.5, 278.8, 101.3)
+#            v29: 0x82817c7b7675706f6a6964635e5d5857 (-3.821e-05, nan, 2.645e+04, 9080., 3282., 1123., 407.2, 138.9)
+#            v30: 0x84837e7d787772716c6b6665605f5a59 (-6.884e-05, nan, 3.658e+04, 1.319e+04, 4524., 1637., 559.5, 203.1)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x5a59'5857'5655 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x605f'5e5d'5c5b <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6665'6463'6261 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x6c6b'6a69'6867 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7271'706f'6e6d <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7877'7675'7473 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x7e7d'7c7b'7a79 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8483'8281'807f <- 0x~~~~~~~~~~~~~~~~
+#            v21: 0x0000000001000000f5f4f3f2e9e8e7e6
+#            v22: 0x2b2a2524ff1e191800000000ff00ff01
+#            v23: 0x2d2c272602201b1a00000000feff0002
+#                            ╙─────────────────────── 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x4f4f4f4f4f4f854f4f4f4f4f4f4f4f4f
+#             v6: 0x82818281828186818281828182818281
+#             v7: 0x00000000000087000b0a0504fffef9f8
+#                                ╙─────────────────── 0x87'86'85 <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0x2d2c272602201b1a00000000feff0084
+#            v24: 0x2f2e292823221d1c1700000000ff0085
+#            v25: 0x3b3a39382f2e2d2c2322212017161586
+#                                                  ╙─ 0x86'85'84 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6e6d6c6b6a696867ff0000850002ff01 (..., -5.487e+303)
+#            v17: 0x00000000474600000000000000fffeff (..., 8.289e-317)
+#            v18: 0xd2d1d0cfcecdcccb1700000000000000 (..., 6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x84837e7d787772718e8d8c8b8a898887 (..., -1.418e-238)
+#            v31: 0x0000000000000000969594939291908f (..., -7.048e-200)
+#             v0: 0xc3c2c1c0bfbebdbc9e9d9c9b9a999897 (..., -3.291e-161)
+#                                                  ╙─ 0x9e9d9c9b9a999897'969594939291908f'8e8d8c8b8a898887 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0x8d8c8b8a89888786686762615c5b5655 (-2.090e-243, ...)
+#            v29: 0x9594939291908f8e6a6964635e5d5857 (-1.025e-204, ...)
+#            v30: 0x9d9c9b9a999897968e8d8c8b8a898887 (-4.851e-166, ...)
+#                                  ╙───────────────── 0x9d9c9b9a99989796'9594939291908f8e'8d8c8b8a89888786 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x81807b7a75746f6e6968ff015d5c5756 (..., nan, ...)
+#            v14: 0x83827d7c777671706b6a00025f5e5958 (..., 1.192e-07, ...)
+#            v15: 0x85847f7e797873726d6c008561605b5a (..., 7.927e-06, ...)
+#                                          ╙───────── 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x9f9e2524ff1e191800000000ff00ff01 (-0.007439, ...)
+#            v23: 0xa1a0272602201b1a00000000feff0084 (-0.01099, ...)
+#            v24: 0xa3a2292823221d1c1700000000ff0085 (-0.01491, ...)
+#                      ╙───────────────────────────── 0xa3a2'a1a0'9f9e <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x83827d7c777671709e9d00025f5e5958 (..., -0.006458, ...)
+#            v15: 0x85847f7e79787372a09f008561605b5a (..., -0.009026, ...)
+#            v16: 0x6e6d6c6b6a696867a2a100850002ff01 (..., -0.01295, ...)
+#                                      ╙───────────── 0xa2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#            v22: 0x0002ff01ff1e191800000000ff00ff01 (2.751e-40, ...)
+#            v23: 0xff00008502201b1a00000000feff0084 (-1.701e+38, ...)
+#            v24: 0x00fffeff23221d1c1700000000ff0085 (2.351e-38, ...)
+#                          ╙───────────────────────── 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0x9d9c9b9aa6a5a4a38e8d8c8b8a898887 (..., -1.149e-15, ...)
+#            v31: 0x00000000aaa9a8a7969594939291908f (..., -3.014e-13, ...)
+#             v0: 0xc3c2c1c0aeadacab9e9d9c9b9a999897 (..., -7.898e-11, ...)
+#                                  ╙───────────────── 0xaeadacab'aaa9a8a7'a6a5a4a3 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000a5a4a3a24744413e (..., -2.856e-16, ...)
+#            v13: 0x81807b7a75746f6ea9a8a7a65d5c5756 (..., -7.490e-14, ...)
+#            v14: 0x83827d7c77767170adacabaa5f5e5958 (..., -1.963e-11, ...)
+#                                          ╙───────── 0xadacabaa'a9a8a7a6'a5a4a3a2 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0x01010101010101010101010101010101
+#            v25: 0xffffffffffffffffffffffffffffffff
+#            v26: 0x02020202020202020202020202020202
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v24: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#            v25: 0xafafafafafafafafafafafafafafafaf
+#            v26: 0xb0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xb0'af'ae <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0xadadadadadadadadadadadadadadadad
+#             v4: 0xaeaeaeaeaeaeaeaeaeaeaeaeaeaeaeae
+#             v5: 0xafafafafafafafafafafafafafafafaf
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0xaf'ae'ad <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0xff0000850002ff01 (-5.487e+303)
+#             d5:                 0x0000000000fffeff (8.289e-317)
+#             d6:                 0x1700000000000000 (6.689e-198)
+#                                                  ╙─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xb7b6b5b4b3b2b1b0 (-2.607e-40)
+#             d8:                 0xbfbebdbcbbbab9b8 (-0.1201)
+#             d9:                 0xc7c6c5c4c3c2c1c0 (-6.054e+37)
+#                                                  ╙─ 0xc7c6c5c4c3c2c1c0'bfbebdbcbbbab9b8'b7b6b5b4b3b2b1b0 <- 0x~~~~~~~~~~~~~~~~
+#            d17:                 0xb6b5b4b3b2b1b0af (-3.802e-45)
+#            d18:                 0xbebdbcbbbab9b8b7 (-1.772e-06)
+#            d19:                 0xc6c5c4c3c2c1c0bf (-8.830e+32)
+#                                                  ╙─ 0xc6c5c4c3c2c1c0bf'bebdbcbbbab9b8b7'b6b5b4b3b2b1b0af <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v17: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v18: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#                                  ╙───────────────╨─ 0x1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0xcecdcccbcac9c8c7cecdcccbcac9c8c7 (-4.113e+71, -4.113e+71)
+#            v21: 0xd6d5d4d3d2d1d0cfd6d5d4d3d2d1d0cf (-2.051e+110, -2.051e+110)
+#            v22: 0xdedddcdbdad9d8d7dedddcdbdad9d8d7 (-9.546e+148, -9.546e+148)
+#                                  ╙───────────────╨─ 0xdedddcdbdad9d8d7'd6d5d4d3d2d1d0cf'cecdcccbcac9c8c7 <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0xcdcccbcac9c8c7c6cdcccbcac9c8c7c6 (-6.065e+66, -6.065e+66)
+#            v15: 0xd5d4d3d2d1d0cfced5d4d3d2d1d0cfce (-2.985e+105, -2.985e+105)
+#            v16: 0xdddcdbdad9d8d7d6dddcdbdad9d8d7d6 (-1.408e+144, -1.408e+144)
+#                                  ╙───────────────╨─ 0xdddcdbdad9d8d7d6'd5d4d3d2d1d0cfce'cdcccbcac9c8c7c6 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#            d11:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#            d12:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#                                          ╙───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d0:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#             d1:                 0xe5e4e3e2e5e4e3e2 (-1.351e+23, -1.351e+23)
+#             d2:                 0xe9e8e7e6e9e8e7e6 (-3.520e+25, -3.520e+25)
+#                                          ╙───────╨─ 0xe9e8e7e6'e5e4e3e2'e1e0dfde <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#            d24:                 0xe4e3e2e1e4e3e2e1 (-3.363e+22, -3.363e+22)
+#            d25:                 0xe8e7e6e5e8e7e6e5 (-8.761e+24, -8.761e+24)
+#                                          ╙───────╨─ 0xe8e7e6e5'e4e3e2e1'e0dfdedd <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d23:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d24:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                                      ╙───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d6:                 0xeae9eae9eae9eae9 (-3538., -3538., -3538., -3538.)
+#             d7:                 0xecebecebecebeceb (-5036., -5036., -5036., -5036.)
+#             d8:                 0xeeedeeedeeedeeed (-7092., -7092., -7092., -7092.)
+#                                      ╙───╨───╨───╨─ 0xeeed'eceb'eae9 <- 0x~~~~~~~~~~~~~~~~
+#             d7:                 0xe9e8e9e8e9e8e9e8 (-3024., -3024., -3024., -3024.)
+#             d8:                 0xebeaebeaebeaebea (-4052., -4052., -4052., -4052.)
+#             d9:                 0xedecedecedecedec (-6064., -6064., -6064., -6064.)
+#                                      ╙───╨───╨───╨─ 0xedec'ebea'e9e8 <- 0x~~~~~~~~~~~~~~~~
+#            v26: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v27: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
+#            v28: 0x00fffeff00fffeff00fffeff00fffeff (2.351e-38, 2.351e-38, 2.351e-38, 2.351e-38)
+#                          ╙───────╨───────╨───────╨─ 0x00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v0: 0xf1f0efeef1f0efeef1f0efeef1f0efee (-2.386e+30, -2.386e+30, -2.386e+30, -2.386e+30)
+#             v1: 0xf5f4f3f2f5f4f3f2f5f4f3f2f5f4f3f2 (-6.210e+32, -6.210e+32, -6.210e+32, -6.210e+32)
+#             v2: 0xf9f8f7f6f9f8f7f6f9f8f7f6f9f8f7f6 (-1.616e+35, -1.616e+35, -1.616e+35, -1.616e+35)
+#                          ╙───────╨───────╨───────╨─ 0xf9f8f7f6'f5f4f3f2'f1f0efee <- 0x~~~~~~~~~~~~~~~~
+#            v30: 0xf0efeeedf0efeeedf0efeeedf0efeeed (-5.940e+29, -5.940e+29, -5.940e+29, -5.940e+29)
+#            v31: 0xf4f3f2f1f4f3f2f1f4f3f2f1f4f3f2f1 (-1.546e+32, -1.546e+32, -1.546e+32, -1.546e+32)
+#             v0: 0xf8f7f6f5f8f7f6f5f8f7f6f5f8f7f6f5 (-4.023e+34, -4.023e+34, -4.023e+34, -4.023e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf8f7f6f5'f4f3f2f1'f0efeeed <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0x0101010101010101
+#             d3:                 0xffffffffffffffff
+#             d4:                 0x0202020202020202
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d10:                 0xf9f9f9f9f9f9f9f9
+#            d11:                 0xfafafafafafafafa
+#            d12:                 0xfbfbfbfbfbfbfbfb
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfb'fa'f9 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xf8f8f8f8f8f8f8f8
+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8 <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0xff01ff01ff01ff01ff01ff01ff01ff01 (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v7: 0x00020002000200020002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#             v8: 0x00850085008500850085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0xfcfbfcfbfcfbfcfbfcfbfcfbfcfbfcfb (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v30: 0xfefdfefdfefdfefdfefdfefdfefdfefd (nan, nan, nan, nan, nan, nan, nan, nan)
+#            v31: 0x00ff00ff00ff00ff00ff00ff00ff00ff (1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05, 1.520e-05)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0xfbfafbfafbfafbfafbfafbfafbfafbfa (-6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04, -6.534e+04)
+#             v8: 0xfdfcfdfcfdfcfdfcfdfcfdfcfdfcfdfc (nan, nan, nan, nan, nan, nan, nan, nan)
+#             v9: 0xfffefffefffefffefffefffefffefffe (nan, nan, nan, nan, nan, nan, nan, nan)
+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xfffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
+#             v3: 0x3c3834302c2824201c18000000ff8501
+#             v4: 0x3d3935312d2925211d19000000fe00ff
+#             v5: 0x3e3a36322e2a26221e1a000000ff0002
+#             v6: 0x3f3b37332f2b27231f1b17000000ff00
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x3c3834302c2824201c1814100c080400
+#             v3: 0x3d3935312d2925211d1915110d090501
+#             v4: 0x3e3a36322e2a26221e1a16120e0a0602
+#             v5: 0x3f3b37332f2b27231f1b17130f0b0703
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x03'02'01'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x07'06'05'04 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0b'0a'09'08 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0f'0e'0d'0c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x13'12'11'10 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x17'16'15'14 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x23'22'21'20 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x27'26'25'24 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2b'2a'29'28 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2f'2e'2d'2c <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x33'32'31'30 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x37'36'35'34 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3b'3a'39'38 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3f'3e'3d'3c <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x3b37332f2b27231f1b17130f0b0703ff
+#             v6: 0x3c3834302c2824201c1814100c080400
+#             v7: 0x3d3935312d2925211d1915110d090501
+#             v8: 0x3e3a36322e2a26221e1a16120e0a0602
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─ 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ║ ╙───────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ║ ╙─────────────── 0x1e'1d'1c'1b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ║ ╙───────────────── 0x22'21'20'1f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║ ╙─────────────────── 0x26'25'24'23 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x2a'29'28'27 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x2e'2d'2c'2b <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x32'31'30'2f <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x36'35'34'33 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x3a'39'38'37 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x3e'3d'3c'3b <- 0x~~~~~~~~~~~~~~~~
+#            v18: 0x2726252423222120ff0000850002ff01 (4.288e-120, -5.487e+303)
+#            v19: 0x2f2e2d2c2b2a29280000000000fffeff (1.988e-81, 8.289e-317)
+#            v20: 0x37363534333231301700000000000000 (9.958e-43, 6.689e-198)
+#            v21: 0x3f3e3d3c3b3a39381f1e1d1c1b1a1918 (0.0004614, 8.568e-159)
+#                                  ║               ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x3f3e3d3c3b3a3938'3736353433323130'2f2e2d2c2b2a2928'2726252423222120 <- 0x~~~~~~~~~~~~~~~~
+#             v4: 0x666564636261605f464544434241403f (1.818e+185, 3.370e+30)
+#             v5: 0x6e6d6c6b6a6968674e4d4c4b4a494847 (8.509e+223, 1.580e+69)
+#             v6: 0x767574737271706f565554535251504f (4.222e+262, 7.827e+107)
+#             v7: 0x7e7d7c7b7a7978775e5d5c5b5a595857 (1.975e+301, 3.666e+146)
+#                                  ║               ╙─ 0x5e5d5c5b5a595857'565554535251504f'4e4d4c4b4a494847'464544434241403f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7e7d7c7b7a797877'767574737271706f'6e6d6c6b6a696867'666564636261605f <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0x6564636261605f5e4544434241403f3e (2.644e+180, 4.899e+25)
+#            v30: 0x6d6c6b6a696867664d4c4b4a49484746 (1.254e+219, 2.328e+64)
+#            v31: 0x7574737271706f6e5554535251504f4e (6.141e+257, 1.138e+103)
+#             v0: 0x7d7c7b7a797877765d5c5b5a59585756 (2.911e+296, 5.403e+141)
+#                                  ║               ╙─ 0x5d5c5b5a59585756'5554535251504f4e'4d4c4b4a49484746'4544434241403f3e <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x7d7c7b7a79787776'7574737271706f6e'6d6c6b6a69686766'6564636261605f5e <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x000000000002ff01 (0.000, 2.751e-40)
+#            d28:                 0x17000000ff000085 (4.136e-25, -1.701e+38)
+#            d29:                 0x1b1a191800fffeff (1.275e-22, 2.351e-38)
+#            d30:                 0x1f1e1d1c00000000 (3.348e-20, 0.000)
+#                                          ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#            d24:                 0x91908f8e81807f7e (-2.281e-28, -4.720e-38)
+#            d25:                 0x9594939285848382 (-6.001e-26, -1.246e-35)
+#            d26:                 0x9998979689888786 (-1.578e-23, -3.287e-33)
+#            d27:                 0x9d9c9b9a8d8c8b8a (-4.145e-21, -8.662e-31)
+#                                          ║       ╙─ 0x8d8c8b8a'89888786'85848382'81807f7e <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9d9c9b9a'99989796'95949392'91908f8e <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x908f8e8d807f7e7d (-5.662e-29, -1.171e-38)
+#             d5:                 0x9493929184838281 (-1.490e-26, -3.092e-36)
+#             d6:                 0x9897969588878685 (-3.918e-24, -8.157e-34)
+#             d7:                 0x9c9b9a998c8b8a89 (-1.030e-21, -2.150e-31)
+#                                          ║       ╙─ 0x8c8b8a89'88878685'84838281'807f7e7d <- 0x~~~~~~~~~~~~~~~~
+#                                          ╙───────── 0x9c9b9a99'98979695'94939291'908f8e8d <- 0x~~~~~~~~~~~~~~~~
+#            d16:                 0x19180000feffff01 (0.002487, 0.000, nan, nan)
+#            d17:                 0x1b1a000000ff0002 (0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            d18:                 0x1d1c000000000085 (0.004990, 0.000, 0.000, 7.927e-06)
+#            d19:                 0x1f1e17000000ff00 (0.006950, 0.001709, 0.000, nan)
+#                                      ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#            d23:                 0xb6b5aeada6a59e9d (-0.4192, -0.1043, -0.02596, -0.006458)
+#            d24:                 0xb8b7b0afa8a7a09f (-0.5894, -0.1464, -0.03635, -0.009026)
+#            d25:                 0xbab9b2b1aaa9a2a1 (-0.8403, -0.2091, -0.05203, -0.01295)
+#            d26:                 0xbcbbb4b3acaba4a3 (-1.183, -0.2937, -0.07294, -0.01811)
+#                                      ║   ║   ║   ╙─ 0xa4a3'a2a1'a09f'9e9d <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xacab'aaa9'a8a7'a6a5 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb4b3'b2b1'b0af'aead <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbcbb'bab9'b8b7'b6b5 <- 0x~~~~~~~~~~~~~~~~
+#             d2:                 0xb5b4adaca5a49d9c (-0.3564, -0.08862, -0.02203, -0.005478)
+#             d3:                 0xb7b6afaea7a69f9e (-0.4819, -0.1200, -0.02988, -0.007439)
+#             d4:                 0xb9b8b1b0a9a8a1a0 (-0.7148, -0.1777, -0.04419, -0.01099)
+#             d5:                 0xbbbab3b2abaaa3a2 (-0.9658, -0.2405, -0.05988, -0.01491)
+#                                      ║   ║   ║   ╙─ 0xa3a2'a1a0'9f9e'9d9c <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ║   ╙───── 0xabaa'a9a8'a7a6'a5a4 <- 0x~~~~~~~~~~~~~~~~
+#                                      ║   ╙───────── 0xb3b2'b1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                                      ╙───────────── 0xbbba'b9b8'b7b6'b5b4 <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x3332313023222120000000000002ff01 (4.149e-08, 8.789e-18, 0.000, 2.751e-40)
+#             v8: 0x373635342726252417000000ff000085 (1.086e-05, 2.306e-15, 4.136e-25, -1.701e+38)
+#             v9: 0x3b3a39382b2a29281b1a191800fffeff (0.002842, 6.045e-13, 1.275e-22, 2.351e-38)
+#            v10: 0x3f3e3d3c2f2e2d2c1f1e1d1c00000000 (0.7431, 1.584e-10, 3.348e-20, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x1f1e1d1c'1b1a1918'17000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x2f2e2d2c'2b2a2928'27262524'23222120 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x3f3e3d3c'3b3a3938'37363534'33323130 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xefeeedecdfdedddccfcecdccbfbebdbc (-1.479e+29, -3.212e+19, -6.939e+09, -1.490)
+#            v29: 0xf3f2f1f0e3e2e1e0d3d2d1d0c3c2c1c0 (-3.850e+31, -8.370e+21, -1.811e+12, -389.5)
+#            v30: 0xf7f6f5f4e7e6e5e4d7d6d5d4c7c6c5c4 (-1.002e+34, -2.181e+24, -4.724e+14, -1.018e+05)
+#            v31: 0xfbfaf9f8ebeae9e8dbdad9d8cbcac9c8 (-2.606e+36, -5.680e+26, -1.232e+17, -2.658e+07)
+#                          ║       ║       ║       ╙─ 0xcbcac9c8'c7c6c5c4'c3c2c1c0'bfbebdbc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdbdad9d8'd7d6d5d4'd3d2d1d0'cfcecdcc <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xebeae9e8'e7e6e5e4'e3e2e1e0'dfdedddc <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfbfaf9f8'f7f6f5f4'f3f2f1f0'efeeedec <- 0x~~~~~~~~~~~~~~~~
+#            v29: 0xeeedecebdedddcdbcecdcccbbebdbcbb (-3.682e+28, -7.993e+18, -1.726e+09, -0.3706)
+#            v30: 0xf2f1f0efe2e1e0dfd2d1d0cfc2c1c0bf (-9.584e+30, -2.083e+21, -4.506e+11, -96.88)
+#            v31: 0xf6f5f4f3e6e5e4e3d6d5d4d3c6c5c4c3 (-2.494e+33, -5.428e+23, -1.176e+14, -2.531e+04)
+#             v0: 0xfaf9f8f7eae9e8e7dad9d8d7cac9c8c7 (-6.490e+35, -1.414e+26, -3.066e+16, -6.612e+06)
+#                          ║       ║       ║       ╙─ 0xcac9c8c7'c6c5c4c3'c2c1c0bf'bebdbcbb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0xdad9d8d7'd6d5d4d3'd2d1d0cf'cecdcccb <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0xeae9e8e7'e6e5e4e3'e2e1e0df'dedddcdb <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0xfaf9f8f7'f6f5f4f3'f2f1f0ef'eeedeceb <- 0x~~~~~~~~~~~~~~~~
+#            d15:                 0x1c18000000ff8501
+#            d16:                 0x1d19000000fe00ff
+#            d17:                 0x1e1a000000ff0002
+#            d18:                 0x1f1b17000000ff00
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0xff'00'00'85 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x00'ff'fe'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x00'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x17'00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x1b'1a'19'18 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1f'1e'1d'1c <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0x17130f0b0703fffb
+#            d28:                 0x1814100c080400fc
+#            d29:                 0x1915110d090501fd
+#            d30:                 0x1a16120e0a0602fe
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfe'fd'fc'fb <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x02'01'00'ff <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x06'05'04'03 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x0a'09'08'07 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0e'0d'0c'0b <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x12'11'10'0f <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x16'15'14'13 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x1a'19'18'17 <- 0x~~~~~~~~~~~~~~~~
+#             d5:                 0x16120e0a0602fefa
+#             d6:                 0x17130f0b0703fffb
+#             d7:                 0x1814100c080400fc
+#             d8:                 0x1915110d090501fd
+#                                    ║ ║ ║ ║ ║ ║ ║ ╙─ 0xfd'fc'fb'fa <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ║ ╙─── 0x01'00'ff'fe <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ║ ╙───── 0x05'04'03'02 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ║ ╙─────── 0x09'08'07'06 <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ║ ╙───────── 0x0d'0c'0b'0a <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ║ ╙─────────── 0x11'10'0f'0e <- 0x~~~~~~~~~~~~~~~~
+#                                    ║ ╙───────────── 0x15'14'13'12 <- 0x~~~~~~~~~~~~~~~~
+#                                    ╙─────────────── 0x19'18'17'16 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831302928212019180000feffff01 (0.6523, 0.1621, 0.04028, 0.01001, 0.002487, 0.000, nan, nan)
+#            v26: 0x3b3a33322b2a23221b1a000000ff0002 (0.9033, 0.2249, 0.05597, 0.01393, 0.003468, 0.000, 1.520e-05, 1.192e-07)
+#            v27: 0x3d3c35342d2c25241d1c000000000085 (1.309, 0.3252, 0.08081, 0.02008, 0.004990, 0.000, 0.000, 7.927e-06)
+#            v28: 0x3f3e37362f2e27261f1e17000000ff00 (1.811, 0.4507, 0.1122, 0.02792, 0.006950, 0.001709, 0.000, nan)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000'00ff'feff <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x1700'0000'0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1f1e'1d1c'1b1a'1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x2726'2524'2322'2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2f2e'2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x3736'3534'3332'3130 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x3f3e'3d3c'3b3a'3938 <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x53524b4a43423b3a33322b2a23221b1a (58.56, 14.58, 3.629, 0.9033, 0.2249, 0.05597, 0.01393, 0.003468)
+#             v3: 0x55544d4c45443d3c35342d2c25241d1c (85.25, 21.19, 5.266, 1.309, 0.3252, 0.08081, 0.02008, 0.004990)
+#             v4: 0x57564f4e47463f3e37362f2e27261f1e (117.4, 29.22, 7.273, 1.811, 0.4507, 0.1122, 0.02792, 0.006950)
+#             v5: 0x59585150494841403938313029282120 (171.0, 42.50, 10.56, 2.625, 0.6523, 0.1621, 0.04028, 0.01001)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x2120'1f1e'1d1c'1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2928'2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3130'2f2e'2d2c'2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3938'3736'3534'3332 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4140'3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948'4746'4544'4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5150'4f4e'4d4c'4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5958'5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2922211a19 (50.53, 12.57, 3.127, 0.7778, 0.1935, 0.04813, 0.01197, 0.002977)
+#            v21: 0x54534c4b44433c3b34332c2b24231c1b (69.19, 17.17, 4.262, 1.058, 0.2625, 0.06512, 0.01616, 0.004009)
+#            v22: 0x56554e4d46453e3d36352e2d26251e1d (101.3, 25.20, 6.270, 1.560, 0.3879, 0.09650, 0.02400, 0.005970)
+#            v23: 0x5857504f4847403f3837302f2827201f (138.9, 34.47, 8.555, 2.123, 0.5269, 0.1307, 0.03244, 0.008049)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x201f'1e1d'1c1b'1a19 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2827'2625'2423'2221 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x302f'2e2d'2c2b'2a29 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x3837'3635'3433'3231 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x403f'3e3d'3c3b'3a39 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4847'4645'4443'4241 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x504f'4e4d'4c4b'4a49 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5857'5655'5453'5251 <- 0x~~~~~~~~~~~~~~~~
+#            v20: 0x52514a4942413a3932312a2901211a19
+#            v21: 0x54534c4b44433c3b34332c2bff231c1b
+#            v22: 0x56554e4d46453e3d36352e2d02251e1d
+#            v23: 0x5857504f4847403f3837302f0027201f
+#                                            ╙─────── 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v12: 0x0000000000000000fbfbfbfb59fbfbfb
+#            v13: 0x81807b7a75746f6ea9a8a7a65a5c5756
+#            v14: 0xcdcccbcac9c8c7c6cdcccbca5bc8c7c6
+#            v15: 0x00000000000000001c1800005cff8501
+#                                            ╙─────── 0x5c'5b'5a'59 <- 0x~~~~~~~~~~~~~~~~
+#            v27: 0x3d3c35342d2c25241d58000000000085
+#            v28: 0x3f3e37362f2e27261f5917000000ff00
+#            v29: 0x0000000000000000195a110d090501fd
+#            v30: 0x00000000000000001a5b120e0a0602fe
+#                                      ╙───────────── 0x5b'5a'59'58 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xff0000850002ff011f5917000000ff00 (-5.487e+303, ...)
+#            v29: 0x0000000000fffeff195a110d090501fd (8.289e-317, ...)
+#            v30: 0x17000000000000001a5b120e0a0602fe (6.689e-198, ...)
+#            v31: 0x1f1e1d1c1b1a1918d6d5d4d3c6c5c4c3 (8.568e-159, ...)
+#                                  ╙───────────────── 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0x636261605f5e5d5c1c1800005cff8501 (5.549e+170, ...)
+#            v16: 0x6b6a6968676665641d19000000fe00ff (2.713e+209, ...)
+#            v17: 0x737271706f6e6d6c1e1a000000ff0002 (1.290e+248, ...)
+#            v18: 0x7b7a7978777675741f1b17000000ff00 (6.299e+286, ...)
+#                                  ╙───────────────── 0x7b7a797877767574'737271706f6e6d6c'6b6a696867666564'636261605f5e5d5c <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x6261605f5e5d5c5b1d19000000fe00ff (8.005e+165, ...)
+#            v17: 0x6a696867666564631e1a000000ff0002 (3.983e+204, ...)
+#            v18: 0x7271706f6e6d6c6b1f1b17000000ff00 (1.861e+243, ...)
+#            v19: 0x7a797877767574731f1e17000000ff00 (9.247e+281, ...)
+#                                  ╙───────────────── 0x7a79787776757473'7271706f6e6d6c6b'6a69686766656463'6261605f5e5d5c5b <- 0x~~~~~~~~~~~~~~~~
+#             v2: 0x5352ff0143423b3a33322b2a23221b1a (..., nan, ...)
+#             v3: 0x5554000245443d3c35342d2c25241d1c (..., 1.192e-07, ...)
+#             v4: 0x5756008547463f3e37362f2e27261f1e (..., 7.927e-06, ...)
+#             v5: 0x5958ff00494841403938313029282120 (..., nan, ...)
+#                          ╙───────────────────────── 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#             v5: 0x5958ff00494841407c7b313029282120 (..., nan, ...)
+#             v6: 0x00000000000000007e7d0f0b0703fffb (..., nan, ...)
+#             v7: 0x0000000000000000807f100c080400fc (..., -7.570e-06, ...)
+#             v8: 0x00000000000000008281110d090501fd (..., -3.821e-05, ...)
+#                                      ╙───────────── 0x8281'807f'7e7d'7c7b <- 0x~~~~~~~~~~~~~~~~
+#             v7: 0x00007b7a00000000807f100c080400fc (..., 6.125e+04, ...)
+#             v8: 0x00007d7c000000008281110d090501fd (..., nan, ...)
+#             v9: 0x3b3a7f7e2b2a29281b1a191800fffeff (..., nan, ...)
+#            v10: 0x3f3e81802f2e2d2c1f1e1d1c00000000 (..., -2.289e-05, ...)
+#                          ╙───────────────────────── 0x8180'7f7e'7d7c'7b7a <- 0x~~~~~~~~~~~~~~~~
+#             v6: 0x00000000000000000002ff010703fffb (..., 2.751e-40, ...)
+#             v7: 0x00007b7a00000000ff000085080400fc (..., -1.701e+38, ...)
+#             v8: 0x00007d7c0000000000fffeff090501fd (..., 2.351e-38, ...)
+#             v9: 0x3b3a7f7e2b2a29280000000000fffeff (..., 0.000, ...)
+#                                          ╙───────── 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0x393831308584838219180000feffff01 (..., -1.246e-35, ...)
+#            v26: 0x3b3a3332898887861b1a000000ff0002 (..., -3.287e-33, ...)
+#            v27: 0x3d3c35348d8c8b8a1d58000000000085 (..., -8.662e-31, ...)
+#            v28: 0xff00008591908f8e1f5917000000ff00 (..., -2.281e-28, ...)
+#                                  ╙───────────────── 0x91908f8e'8d8c8b8a'89888786'85848382 <- 0x~~~~~~~~~~~~~~~~
+#             v8: 0x848382810000000000fffeff090501fd (-3.092e-36, ...)
+#             v9: 0x888786852b2a29280000000000fffeff (-8.157e-34, ...)
+#            v10: 0x8c8b8a892f2e2d2c1f1e1d1c00000000 (-2.150e-31, ...)
+#            v11: 0x908f8e8d00000000fafafafafafafafa (-5.662e-29, ...)
+#                          ╙───────────────────────── 0x908f8e8d'8c8b8a89'88878685'84838281 <- 0x~~~~~~~~~~~~~~~~
+#            v14: 0x01010101010101010101010101010101
+#            v15: 0xffffffffffffffffffffffffffffffff
+#            v16: 0x02020202020202020202020202020202
+#            v17: 0x00000000000000000000000000000000
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            v13: 0x91919191919191919191919191919191
+#            v14: 0x92929292929292929292929292929292
+#            v15: 0x93939393939393939393939393939393
+#            v16: 0x94949494949494949494949494949494
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x94'93'92'91 <- 0x~~~~~~~~~~~~~~~~
+#             v9: 0x90909090909090909090909090909090
+#            v10: 0x91919191919191919191919191919191
+#            v11: 0x92929292929292929292929292929292
+#            v12: 0x93939393939393939393939393939393
+#                    ╙─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─╨─ 0x93'92'91'90 <- 0x~~~~~~~~~~~~~~~~
+#             d8:                 0xff0000850002ff01 (-5.487e+303)
+#             d9:                 0x0000000000fffeff (8.289e-317)
+#            d10:                 0x1700000000000000 (6.689e-198)
+#            d11:                 0x1f1e1d1c1b1a1918 (8.568e-159)
+#                                                  ╙─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#             d4:                 0x9b9a999897969594 (-1.050e-175)
+#             d5:                 0xa3a2a1a09f9e9d9c (-5.007e-137)
+#             d6:                 0xabaaa9a8a7a6a5a4 (-2.438e-98)
+#             d7:                 0xb3b2b1b0afaeadac (-1.163e-59)
+#                                                  ╙─ 0xb3b2b1b0afaeadac'abaaa9a8a7a6a5a4'a3a2a1a09f9e9d9c'9b9a999897969594 <- 0x~~~~~~~~~~~~~~~~
+#            d26:                 0x9a99989796959493 (-1.542e-180)
+#            d27:                 0xa2a1a09f9e9d9c9b (-7.228e-142)
+#            d28:                 0xaaa9a8a7a6a5a4a3 (-3.580e-103)
+#            d29:                 0xb2b1b0afaeadacab (-1.680e-64)
+#                                                  ╙─ 0xb2b1b0afaeadacab'aaa9a8a7a6a5a4a3'a2a1a09f9e9d9c9b'9a99989796959493 <- 0x~~~~~~~~~~~~~~~~
+#            v19: 0xff0000850002ff01ff0000850002ff01 (-5.487e+303, -5.487e+303)
+#            v20: 0x0000000000fffeff0000000000fffeff (8.289e-317, 8.289e-317)
+#            v21: 0x17000000000000001700000000000000 (6.689e-198, 6.689e-198)
+#            v22: 0x1f1e1d1c1b1a19181f1e1d1c1b1a1918 (8.568e-159, 8.568e-159)
+#                                  ╙───────────────╨─ 0x1f1e1d1c1b1a1918'1700000000000000'0000000000fffeff'ff0000850002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v28: 0xbab9b8b7b6b5b4b3bab9b8b7b6b5b4b3 (-8.311e-26, -8.311e-26)
+#            v29: 0xc2c1c0bfbebdbcbbc2c1c0bfbebdbcbb (-3.904e+13, -3.904e+13)
+#            v30: 0xcac9c8c7c6c5c4c3cac9c8c7c6c5c4c3 (-1.929e+52, -1.929e+52)
+#            v31: 0xd2d1d0cfcecdcccbd2d1d0cfcecdcccb (-9.073e+90, -9.073e+90)
+#                                  ╙───────────────╨─ 0xd2d1d0cfcecdcccb'cac9c8c7c6c5c4c3'c2c1c0bfbebdbcbb'bab9b8b7b6b5b4b3 <- 0x~~~~~~~~~~~~~~~~
+#            v15: 0xb9b8b7b6b5b4b3b2b9b8b7b6b5b4b3b2 (-1.219e-30, -1.219e-30)
+#            v16: 0xc1c0bfbebdbcbbbac1c0bfbebdbcbbba (-5.620e+08, -5.620e+08)
+#            v17: 0xc9c8c7c6c5c4c3c2c9c8c7c6c5c4c3c2 (-2.829e+47, -2.829e+47)
+#            v18: 0xd1d0cfcecdcccbcad1d0cfcecdcccbca (-1.306e+86, -1.306e+86)
+#                                  ╙───────────────╨─ 0xd1d0cfcecdcccbca'c9c8c7c6c5c4c3c2'c1c0bfbebdbcbbba'b9b8b7b6b5b4b3b2 <- 0x~~~~~~~~~~~~~~~~
+#            d31:                 0x0002ff010002ff01 (2.751e-40, 2.751e-40)
+#             d0:                 0xff000085ff000085 (-1.701e+38, -1.701e+38)
+#             d1:                 0x00fffeff00fffeff (2.351e-38, 2.351e-38)
+#             d2:                 0x0000000000000000 (0.000, 0.000)
+#                                          ╙───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d28:                 0xd5d4d3d2d5d4d3d2 (-2.925e+13, -2.925e+13)
+#            d29:                 0xd9d8d7d6d9d8d7d6 (-7.629e+15, -7.629e+15)
+#            d30:                 0xdddcdbdadddcdbda (-1.989e+18, -1.989e+18)
+#            d31:                 0xe1e0dfdee1e0dfde (-5.185e+20, -5.185e+20)
+#                                          ╙───────╨─ 0xe1e0dfde'dddcdbda'd9d8d7d6'd5d4d3d2 <- 0x~~~~~~~~~~~~~~~~
+#            d11:                 0xd4d3d2d1d4d3d2d1 (-7.278e+12, -7.278e+12)
+#            d12:                 0xd8d7d6d5d8d7d6d5 (-1.899e+15, -1.899e+15)
+#            d13:                 0xdcdbdad9dcdbdad9 (-4.951e+17, -4.951e+17)
+#            d14:                 0xe0dfdedde0dfdedd (-1.291e+20, -1.291e+20)
+#                                          ╙───────╨─ 0xe0dfdedd'dcdbdad9'd8d7d6d5'd4d3d2d1 <- 0x~~~~~~~~~~~~~~~~
+#            d19:                 0xff01ff01ff01ff01 (nan, nan, nan, nan)
+#            d20:                 0x0002000200020002 (1.192e-07, 1.192e-07, 1.192e-07, 1.192e-07)
+#            d21:                 0x0085008500850085 (7.927e-06, 7.927e-06, 7.927e-06, 7.927e-06)
+#            d22:                 0xff00ff00ff00ff00 (nan, nan, nan, nan)
+#                                      ╙───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0xe2e1e2e1e2e1e2e1 (-880.5, -880.5, -880.5, -880.5)
+#            d23:                 0xe4e3e4e3e4e3e4e3 (-1251., -1251., -1251., -1251.)
+#            d24:                 0xe6e5e6e5e6e5e6e5 (-1765., -1765., -1765., -1765.)
+#            d25:                 0xe8e7e8e7e8e7e8e7 (-2510., -2510., -2510., -2510.)
+#                                      ╙───╨───╨───╨─ 0xe8e7'e6e5'e4e3'e2e1 <- 0x~~~~~~~~~~~~~~~~
+#            d20:                 0xe1e0e1e0e1e0e1e0 (-752.0, -752.0, -752.0, -752.0)
+#            d21:                 0xe3e2e3e2e3e2e3e2 (-1009., -1009., -1009., -1009.)
+#            d22:                 0xe5e4e5e4e5e4e5e4 (-1508., -1508., -1508., -1508.)
+#            d23:                 0xe7e6e7e6e7e6e7e6 (-2022., -2022., -2022., -2022.)
+#                                      ╙───╨───╨───╨─ 0xe7e6'e5e4'e3e2'e1e0 <- 0x~~~~~~~~~~~~~~~~
+#            v16: 0x0002ff010002ff010002ff010002ff01 (2.751e-40, 2.751e-40, 2.751e-40, 2.751e-40)
+#            v17: 0xff000085ff000085ff000085ff000085 (-1.701e+38, -1.701e+38, -1.701e+38, -1.701e+38)
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+#            v19: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ╙───────╨───────╨───────╨─ 0x00000000'00fffeff'ff000085'0002ff01 <- 0x~~~~~~~~~~~~~~~~
+#            v25: 0xebeae9e8ebeae9e8ebeae9e8ebeae9e8 (-5.680e+26, -5.680e+26, -5.680e+26, -5.680e+26)
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+#            v28: 0xf7f6f5f4f7f6f5f4f7f6f5f4f7f6f5f4 (-1.002e+34, -1.002e+34, -1.002e+34, -1.002e+34)
+#                          ╙───────╨───────╨───────╨─ 0xf7f6f5f4'f3f2f1f0'efeeedec'ebeae9e8 <- 0x~~~~~~~~~~~~~~~~
+#            v23: 0xeae9e8e7eae9e8e7eae9e8e7eae9e8e7 (-1.414e+26, -1.414e+26, -1.414e+26, -1.414e+26)
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+#                          ╙───────╨───────╨───────╨─ 0xf6f5f4f3'f2f1f0ef'eeedeceb'eae9e8e7 <- 0x~~~~~~~~~~~~~~~~
+#            d22:                 0x0101010101010101
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+#            d25:                 0x0000000000000000
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0x00'02'ff'01 <- 0x~~~~~~~~~~~~~~~~
+#            d27:                 0xf7f7f7f7f7f7f7f7
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+#            d29:                 0xf9f9f9f9f9f9f9f9
+#            d30:                 0xfafafafafafafafa
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xfa'f9'f8'f7 <- 0x~~~~~~~~~~~~~~~~
+#            d29:                 0xf6f6f6f6f6f6f6f6
+#            d30:                 0xf7f7f7f7f7f7f7f7
+#            d31:                 0xf8f8f8f8f8f8f8f8
+#             d0:                 0xf9f9f9f9f9f9f9f9
+#                                    ╙─╨─╨─╨─╨─╨─╨─╨─ 0xf9'f8'f7'f6 <- 0x~~~~~~~~~~~~~~~~
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+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0xff00'0085'0002'ff01 <- 0x~~~~~~~~~~~~~~~~
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+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x0100'fffe'fdfc'fbfa <- 0x~~~~~~~~~~~~~~~~
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+#                      ╙───╨───╨───╨───╨───╨───╨───╨─ 0x00ff'fefd'fcfb'faf9 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ╙───────────────────── 0x1918 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x1b1a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x1d1c <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x2120 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x2524 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║   ╙───────────────────── 0x2928 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2b2a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c <- 0x~~~~~~~~~~~~~~~~
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+#   z21<639:512>: 0x4d4c4b4a494847464544434241403f3e (21.19, 14.58, 10.56, 7.273, 5.266, 3.629, 2.625, 1.811)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3f3e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x4342 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x4948 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x4b4a <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x4d4c <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x7f800000000000000000000000000000 (inf, ..., 0.000, 0.000)
+#                          ║               ║       ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x7f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, ..., 0.000)
+#                          ║       ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (...)
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+#   z22<511:384>: 0x2f2e0000000000000000000023220000 (1.583e-10, ..., 0.000, 8.782e-18)
+#                          ║               ║       ╙─ 0x23220000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x00000000000000000000000000000000 (..., 0.000)
+#                                                  ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (...)
+#
+#   z23<511:384>: 0x00000000000000000000000023220000 (..., 2.912e-315)
+#                                                  ╙─ 0x0000000023220000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║   ║       ║   ║       ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#   z20<383:256>: 0x00000000000000000000000000000000
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+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ║   ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ║       ╙───────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║   ╙───────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║       ║   ║       ╙───── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║       ╙───────────────── 0x23 <- 0x~~~~~~~~~~~~~~~~
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+#                      ╙───────────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║               ╙───────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000
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+#   z21<511:384>: 0x00000000000000000000000000000000
+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000
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+#   z22<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000
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+#   z23<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
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+#     z24<127:0>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
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+#   z24<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
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+#     z20<127:0>: 0x00000000000000000000000000000000
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+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<383:256>: 0x00000000000000000000000000000000
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+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z20<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║       ║   ║       ║   ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║   ║       ║   ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                      ║   ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║               ║       ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x7f <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
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+#   z23<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x00000000000000860000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0086 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000304
+#                          ║       ║       ║       ╙─ 0x0304 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
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+#   z24<639:512>: 0x00000000000000000000000000000000
+#                          ║       ║       ║       ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
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+#   z20<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000
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+#   z21<255:128>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
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+#   z21<511:384>: 0x00000000000000000000000000000000
+#                                                  ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000
+#                                  ║               ╙─ 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z20<127:0>: 0x0000000000000000000000000000007f
+#     z21<127:0>: 0x00000000000000000000000000000000
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+#                    ║ ║ ║   ╙─────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z21<127:0>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#     z22<127:0>: 0x000000007f807f800000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x7f80'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#   z21<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x0000'0000 <- 0x~~~~~~~~~~~~~~~~
+#     z22<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#     z23<127:0>: 0x000000007f8000000000000000000000 (0.000, inf, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x7f800000'7f800000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#   z22<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000, 0.000, 0.000)
+#                          ║       ║       ║       ╙─ 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#     z23<127:0>: 0x7f8000007f8000000000000000000000 (1.404e+306, 0.000)
+#     z24<127:0>: 0x00000000000000000000000000000000 (1.404e+306, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'7f8000007f800000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<255:128>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<383:256>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#   z24<511:384>: 0x00000000000000000000000000000000 (0.000, ...)
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#   z23<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#   z24<639:512>: 0x00000000000000000000000000000000 (0.000, 0.000)
+#                                  ║               ╙─ 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#     z24<127:0>: 0x0000000000000000000000ff00000000
+#     z25<127:0>: 0xa000000000000000000000ffc0000000
+#     z26<127:0>: 0x3700000000000000000000007f000000
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─────── 0x7f'c0'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───────── 0x00'ff'ff <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ║   ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║   ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x37'a0'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<255:128>: 0x00000000000000000000000000000000
+#   z25<255:128>: 0x00000000000000000000000000000000
+#   z26<255:128>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║   ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<383:256>: 0x00000000000000000000000000000000
+#   z25<383:256>: 0x00000000000000000000000000000000
+#   z26<383:256>: 0x00000000000000000000000000000000
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ║   ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<511:384>: 0x00000000000000000000000000000000
+#   z25<511:384>: 0x00000000000000000000000000000000
+#   z26<511:384>: 0x00000000000000000000000000000000
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ║ ╙─────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ║   ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ║ ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ║ ╙───────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║   ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#   z24<639:512>: 0x00000000000000000000000000000000
+#   z25<639:512>: 0x00000000000000000000000000000000
+#   z26<639:512>: 0x00000000000000000000000000000000
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ║ ╙─ 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ║ ╙─── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ║ ╙───── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ║ ╙─────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ║   ╙───────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ║ ╙───────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ║ ╙─────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ║ ╙───────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ║ ╙─────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ║ ╙───────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ║   ╙─────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ║ ╙─────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ║ ╙───────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#                    ╙─────────────────────────────── 0x00'00'00 <- 0x~~~~~~~~~~~~~~~~
+#     z25<127:0>: 0x292823221d1c17160000000000000000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z26<127:0>: 0x2b2a25241f1e191813120d0c07060100 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#     z27<127:0>: 0x2d2c272621201b1a1514000009080000 (0.04028, 0.01393, 0.004990, 0.001730, 0.000, 0.000, 0.000, 0.000)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x0000'0100'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x0908'0706'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x0000'0d0c'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x1514'1312'0000 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x1b1a'1918'1716 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x2120'1f1e'1d1c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x2726'2524'2322 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x2d2c'2b2a'2928 <- 0x~~~~~~~~~~~~~~~~
+#   z25<255:128>: 0x595853524d4c474641403b3a35342f2e (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z26<255:128>: 0x5b5a55544f4e494843423d3c37363130 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#   z27<255:128>: 0x5d5c575651504b4a45443f3e39383332 (171.0, 58.56, 21.19, 7.273, 2.625, 0.9033, 0.3252, 0.1122)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x3332'3130'2f2e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x3938'3736'3534 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x3f3e'3d3c'3b3a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x4544'4342'4140 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x4b4a'4948'4746 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x5150'4f4e'4d4c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x5756'5554'5352 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x5d5c'5b5a'5958 <- 0x~~~~~~~~~~~~~~~~
+#   z25<383:256>: 0x898883827d7c777671706b6a65645f5e (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z26<383:256>: 0x8b8a85847f7e797873726d6c67666160 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#   z27<383:256>: 0x8d8c878681807b7a75746f6e69686362 (-0.0001688, -5.352e-05, nan, 3.056e+04, 1.114e+04, 3796., 1380., 471.5)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x6362'6160'5f5e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x6968'6766'6564 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x6f6e'6d6c'6b6a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0x7574'7372'7170 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0x7b7a'7978'7776 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0x8180'7f7e'7d7c <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0x8786'8584'8382 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0x8d8c'8b8a'8988 <- 0x~~~~~~~~~~~~~~~~
+#   z25<511:384>: 0xb9b8b3b2adaca7a6a1a09b9a95948f8e (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#   z26<511:384>: 0xbbbab5b4afaea9a8a3a29d9c97969190 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#   z27<511:384>: 0xbdbcb7b6b1b0abaaa5a49f9e99989392 (-0.7148, -0.2405, -0.08862, -0.02988, -0.01099, -0.003712, -0.001362, -0.0004611)
+#                      ║   ║   ║   ║   ║   ║   ║   ╙─ 0x9392'9190'8f8e <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ║   ╙───── 0x9998'9796'9594 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ║   ╙───────── 0x9f9e'9d9c'9b9a <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ║   ╙───────────── 0xa5a4'a3a2'a1a0 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ║   ╙───────────────── 0xabaa'a9a8'a7a6 <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ║   ╙───────────────────── 0xb1b0'afae'adac <- 0x~~~~~~~~~~~~~~~~
+#                      ║   ╙───────────────────────── 0xb7b6'b5b4'b3b2 <- 0x~~~~~~~~~~~~~~~~
+#                      ╙───────────────────────────── 0xbdbc'bbba'b9b8 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x37a00000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ║       ╙─ 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ║       ╙───────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x000000007fff0000'0000ffff7fc00000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x37a0000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ║               ╙─ 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                          ║       ║       ╙───────── 0x5b5a5958'57565554'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ║       ╙───────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
+#                          ╙───────────────────────── 0x00000000'00000000'00000000'00000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ╙───────────────── 0x000000007f800000'0000000000000000'000000007f800000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
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+#                                  ╙───────────────── 0x0000000000000000'0000000000000000'0000000000000000'0000000000000000 <- 0x~~~~~~~~~~~~~~~~
diff --git a/test/test-trace-reference/log-write b/test/test-trace-reference/log-write
index 88a4e994..fff3143f 100644
--- a/test/test-trace-reference/log-write
+++ b/test/test-trace-reference/log-write
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diff --git a/test/test-trace-reference/log-write-colour b/test/test-trace-reference/log-write-colour
index 80207575..92faa1fd 100644
--- a/test/test-trace-reference/log-write-colour
+++ b/test/test-trace-reference/log-write-colour
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diff --git a/tools/clang_format.py b/tools/clang_format.py
index 7351506b..a0d000cd 100755
--- a/tools/clang_format.py
+++ b/tools/clang_format.py
@@ -38,8 +38,8 @@ from threaded_tests import Test, TestQueue
 import printer
 import util
 
-CLANG_FORMAT_VERSION_MAJOR = 3
-CLANG_FORMAT_VERSION_MINOR = 8
+CLANG_FORMAT_VERSION_MAJOR = 4
+CLANG_FORMAT_VERSION_MINOR = 0
 
 DEFAULT_CLANG_FORMAT = \
     'clang-format-{}.{}'.format(CLANG_FORMAT_VERSION_MAJOR,
diff --git a/tools/clang_tidy.py b/tools/clang_tidy.py
index 42a1422c..7ba18746 100755
--- a/tools/clang_tidy.py
+++ b/tools/clang_tidy.py
@@ -156,9 +156,8 @@ def ClangTidyFiles(files, clang_tidy, jobs = 1, progress_prefix = ''):
 
   queue = TestQueue(prefix = progress_prefix)
 
-  cpp_versions = ['c++98', 'c++11']
   for file in to_check:
-    for cpp_version in cpp_versions:
+    for cpp_version in config.tested_cpp_standards:
       command = [clang_tidy, file] + opts + ['-std=%s' % cpp_version]
       queue.AddTest(file, command=command)
 
diff --git a/tools/config.py b/tools/config.py
index 62a06c6f..f178d4e1 100644
--- a/tools/config.py
+++ b/tools/config.py
@@ -43,8 +43,8 @@ dir_aarch32_traces     = os.path.join(dir_tests, 'aarch32', 'traces')
 # The following set of options are tested in all combinations.
 # The full list of available build modes.
 build_options_modes = ['debug', 'release']
-# The list of C++ standard to test for.
-tested_cpp_standards = ['c++98', 'c++11']
+# The list of C++ standard to test for. The first value is used as the default.
+tested_cpp_standards = ['c++14']
 # The list of compilers tested.
 tested_compilers = ['clang++', 'g++']
 # The list of target arch/isa options to test with. Do not list 'all' as an
diff --git a/tools/generate_simulator_traces.py b/tools/generate_simulator_traces.py
index f0c43b39..3e25b0d3 100755
--- a/tools/generate_simulator_traces.py
+++ b/tools/generate_simulator_traces.py
@@ -77,7 +77,7 @@ extern "C" {
 #include <stdint.h>
 }
 
-// To add a new simulator test to test-simulator-aarch64.cc, add dummy array(s)
+// To add a new simulator test to test-simulator-aarch64.cc, add placeholder array(s)
 // below to build test-simulator-aarch64 for reference platform. Then, run
 // tools/generate_simulator_traces.py on a reference platform to regenerate this
 // file and traces files.
@@ -85,11 +85,11 @@ extern "C" {
 // ---------------------------------------------------------------------
 // ADD DUMMY ARRAYS FOR NEW SIMULATOR TEST HERE.
 // ---------------------------------------------------------------------
-const uint64_t kExpected_dummy_64[] = {0};
-const size_t kExpectedCount_dummy_64 = 0;
+const uint64_t kExpected_placeholder_64[] = {0};
+const size_t kExpectedCount_placeholder_64 = 0;
 
-const uint32_t kExpected_dummy_32[] = {0};
-const size_t kExpectedCount_dummy_32 = 0;
+const uint32_t kExpected_placeholder_32[] = {0};
+const size_t kExpectedCount_placeholder_32 = 0;
 
 // ---------------------------------------------------------------------
 // Simulator test trace output files.
diff --git a/tools/generate_tests.py b/tools/generate_tests.py
index 37f5dc01..c64bf4f6 100755
--- a/tools/generate_tests.py
+++ b/tools/generate_tests.py
@@ -34,7 +34,7 @@ From the VIXL toplevel directory run:
 
     $ ./tools/generate_tests.py
 
-The script assumes that `clang-format-3.8` is in the current path. If it isn't,
+The script assumes that `clang-format-4.0` is in the current path. If it isn't,
 you can provide your own:
 
     $ ./tools/generate_tests.py --clang-format /patch/to/clang-format
@@ -48,7 +48,7 @@ present in the `default_config_files` list. For example:
 - test/aarch32/test-assembler-cond-rd-rn-rm-ge-a32.cc
 
 Because these test cases need traces in order to build, the script will have
-generated dummy trace files in `test/aarch32/traces/`. If you look at them
+generated placeholder trace files in `test/aarch32/traces/`. If you look at them
 you'll see they are basically empty:
 
     $ cat test/aarch32/traces/sim-cond-rd-rn-immediate-adc-a32.h
@@ -687,12 +687,12 @@ def BuildOptions():
                       metavar='FILE',
                       help='Configuration files, each will generate a test file.')
   result.add_argument('--clang-format',
-                      default='clang-format-3.8', help='Path to clang-format.')
+                      default='clang-format-4.0', help='Path to clang-format.')
   result.add_argument('--jobs', '-j', type=int, metavar='N',
                       default=multiprocessing.cpu_count(),
                       help='Allow N jobs at once')
   result.add_argument('--skip-traces', action='store_true',
-                      help='Skip generation of dummy traces.')
+                      help='Skip generation of placeholder traces.')
   return result.parse_args()
 
 
@@ -773,7 +773,7 @@ def GenerateTest(generator, clang_format, skip_traces):
     out, _ = proc.communicate(generated_file.encode())
     f.write(out.decode())
   if not skip_traces:
-    # Write dummy trace files into 'test/aarch32/traces/'.
+    # Write placeholder trace files into 'test/aarch32/traces/'.
     generator.WriteEmptyTraces("test/aarch32/traces/")
   print("Generated {} {} test for \"{}\".".format(generator.test_isa.upper(),
                                                   generator.test_type,
diff --git a/tools/lint.py b/tools/lint.py
index 3ceb94f5..d4c9f65b 100755
--- a/tools/lint.py
+++ b/tools/lint.py
@@ -92,9 +92,13 @@ def Lint(filename, progress_prefix = ''):
   printer.Print(outerr)
 
   # Find the number of errors in this file.
-  res = re.search('Total errors found: (\d+)$', outerr)
-  n_errors_str = res.string[res.start(1):res.end(1)]
-  n_errors = int(n_errors_str)
+  res = re.search('Total errors found: (\d+)', outerr)
+  if res:
+    n_errors_str = res.string[res.start(1):res.end(1)]
+    n_errors = int(n_errors_str)
+  else:
+    print("Couldn't parse cpplint.py output.")
+    n_errors = -1
 
   return (filename, n_errors)
 
diff --git a/tools/test.py b/tools/test.py
index 66f315dd..9a081d0c 100755
--- a/tools/test.py
+++ b/tools/test.py
@@ -377,6 +377,7 @@ if __name__ == '__main__':
     list_options += ListCombinations(
         compiler = args.compiler,
         negative_testing = 'on',
+        std = args.std,
         mode = 'debug',
         target = 'a64,a32,t32')
 
@@ -388,21 +389,13 @@ if __name__ == '__main__':
         mode = 'release',
         target = 'a64,a32,t32')
 
-    # c++98 builds for Thumb32 target only.
-    list_options += ListCombinations(
-        compiler = args.compiler,
-        negative_testing = 'off',
-        std = 'c++98',
-        mode = args.mode,
-        target = 't32')
-
-    # c++11 builds for Aarch64 target only.
+    # Debug builds for individual targets.
     list_options += ListCombinations(
-        compiler = args.compiler,
+        compiler = args.compiler[0],
         negative_testing = 'off',
-        std = 'c++11',
-        mode = args.mode,
-        target = 'a64')
+        std = args.std,
+        mode = 'debug',
+        target = ['a32', 't32', 'a64'])
   else:
     list_options = ListCombinations(
         compiler = args.compiler,
diff --git a/tools/test_runner.py b/tools/test_runner.py
index 6a7d8b43..3a3f459c 100644
--- a/tools/test_runner.py
+++ b/tools/test_runner.py
@@ -35,8 +35,9 @@ import util
 
 # Scan matching tests and return a test manifest.
 def GetTests(runner, filters = []):
-  rc, output = util.getstatusoutput(runner +  ' --list')
-  if rc != 0: util.abort('Failed to list all tests')
+  cmd = runner +  ' --list'
+  rc, output = util.getstatusoutput(cmd)
+  if rc != 0: util.abort("Failed to list all tests. Output of " + cmd + ":\n" + output)
 
   tests = output.split()
   for f in filters:
diff --git a/tools/util.py b/tools/util.py
index bc8dcd16..9152584d 100644
--- a/tools/util.py
+++ b/tools/util.py
@@ -87,7 +87,8 @@ def GetCompilerDirectives(env):
   args += ['-E', '-dM', '-']
 
   # Instruct the compiler to dump all its preprocessor macros.
-  dump = subprocess.Popen(args, stdin=subprocess.PIPE, stdout=subprocess.PIPE)
+  dump = subprocess.Popen(args, stdin=subprocess.PIPE, stdout=subprocess.PIPE,
+                          universal_newlines=True)
   out, _ = dump.communicate()
   return {
     # Extract the macro name as key and value as element.