diff options
author | armvixl <vixl@arm.com> | 2014-05-01 11:05:00 +0100 |
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committer | Martyn Capewell <martyn.capewell@arm.com> | 2014-05-01 17:12:44 +0100 |
commit | 5799d6c5d10729eaade85ad608109c83ed1ae63b (patch) | |
tree | 39161f8f25b0c42ee7f40c6ec5bd9069d4c532e6 /doc | |
parent | b0c8ae2a5f0abc58f67322052d39bfd47edb2892 (diff) | |
download | vixl-5799d6c5d10729eaade85ad608109c83ed1ae63b.tar.gz |
VIXL Release 1.4
Refer to the README.md and LICENCE files for details.
Diffstat (limited to 'doc')
-rw-r--r-- | doc/changelog.md | 9 | ||||
-rw-r--r-- | doc/supported-instructions.md | 39 |
2 files changed, 39 insertions, 9 deletions
diff --git a/doc/changelog.md b/doc/changelog.md index 2475e553..a88efb31 100644 --- a/doc/changelog.md +++ b/doc/changelog.md @@ -1,6 +1,15 @@ VIXL Change Log =============== +* 1.4 + + Added support for `frintm`. + + Fixed simulation of `frintn` and `frinta` for corner cases. + + Added more tests for floating point instruction simulation. + + Modified `CalleeSave()` and `CalleeRestore()` to push general purpose + registers before floating point registers on the stack. + + Fixed Printf for mixed argument types, and use on real hardware. + + Improved compatibility with some 32-bit compilers. + * 1.3 + Address inaccuracies in the simulated floating point instructions. + Implement Default-NaN floating point mode. diff --git a/doc/supported-instructions.md b/doc/supported-instructions.md index 71839d4e..4c835f31 100644 --- a/doc/supported-instructions.md +++ b/doc/supported-instructions.md @@ -437,16 +437,16 @@ Load word pair with sign extension. ### ldr ### -Load integer or FP register. +Load double precision floating point literal to FP register. - void ldr(const CPURegister& rt, const MemOperand& src) + void ldr(const FPRegister& ft, double imm) ### ldr ### -Load literal to FP register. +Load integer or FP register. - void ldr(const FPRegister& ft, double imm) + void ldr(const CPURegister& rt, const MemOperand& src) ### ldr ### @@ -456,6 +456,13 @@ Load literal to register. void ldr(const Register& rt, uint64_t imm) +### ldr ### + +Load single precision floating point literal to FP register. + + void ldr(const FPRegister& ft, float imm) + + ### ldrb ### Load byte. @@ -1160,28 +1167,35 @@ FP minimum number. Move FP register to FP register. - void fmov(FPRegister fd, FPRegister fn) + void fmov(const FPRegister& fd, const FPRegister& fn) ### fmov ### Move FP register to register. - void fmov(Register rd, FPRegister fn) + void fmov(const Register& rd, const FPRegister& fn) ### fmov ### -Move immediate to FP register. +Move double precision immediate to FP register. - void fmov(FPRegister fd, double imm) + void fmov(const FPRegister& fd, double imm) ### fmov ### Move register to FP register. - void fmov(FPRegister fd, Register rn) + void fmov(const FPRegister& fd, const Register& rn) + + +### fmov ### + +Move single precision immediate to FP register. + + void fmov(const FPRegister& fd, float imm) ### fmsub ### @@ -1235,6 +1249,13 @@ FP round to integer (nearest with ties to away). void frinta(const FPRegister& fd, const FPRegister& fn) +### frintm ### + +FP round to integer (toward minus infinity). + + void frintm(const FPRegister& fd, const FPRegister& fn) + + ### frintn ### FP round to integer (nearest with ties to even). |