VIXL Release 1.6

Refer to the README.md and LICENCE files for details.

5 files changed, 113 insertions, 14 deletions

diff --git a/doc/changelog.md b/doc/changelog.md
index cbb1de67..bc249a2f 100644
--- a/doc/changelog.md
+++ b/doc/changelog.md
@@ -1,6 +1,20 @@
 VIXL Change Log
 ===============
 
+* 1.6
+    + Make literal pool management the responsibility of the macro assembler.
+    + Move code buffer management out of the Assembler.
+    + Support `ldrsw` for literals.
+    + Support binding a label to a specific offset.
+    + Add macro assembler support for load/store pair with arbitrary offset.
+    + Support Peek and Poke for CPURegLists.
+    + Fix disassembly of branch targets.
+    + Fix Decoder visitor insertion order.
+    + Separate Decoder visitors into const and non-const variants.
+    + Fix simulator for branches to tagged addresses.
+    + Add a VIM YouCompleteMe configuration file.
+    + Other small bug fixes and build system improvements.
+
 * 1.5
     + Tagged pointer support.
     + Implement support for exclusive access instructions.
diff --git a/doc/supported-instructions.md b/doc/supported-instructions.md
index 26d80cf9..a5bde8b0 100644
--- a/doc/supported-instructions.md
+++ b/doc/supported-instructions.md
@@ -507,31 +507,24 @@ Load word pair with sign extension.
 
 ### ldr ###
 
-Load double precision floating point literal to FP register.
+Load integer or FP register from literal pool.
 
-    void ldr(const FPRegister& ft, double imm)
+    void ldr(const CPURegister& rt, RawLiteral* literal)
 
 
 ### ldr ###
 
-Load integer or FP register.
+Load integer or FP register from pc + imm19 << 2.
 
-    void ldr(const CPURegister& rt, const MemOperand& src,
-             LoadStoreScalingOption option = PreferScaledOffset)
+    void ldr(const CPURegister& rt, int imm19)
 
 
 ### ldr ###
 
-Load literal to register.
-
-    void ldr(const Register& rt, uint64_t imm)
-
-
-### ldr ###
-
-Load single precision floating point literal to FP register.
+Load integer or FP register.
 
-    void ldr(const FPRegister& ft, float imm)
+    void ldr(const CPURegister& rt, const MemOperand& src,
+             LoadStoreScalingOption option = PreferScaledOffset)
 
 
 ### ldrb ###
@@ -568,6 +561,20 @@ Load half-word with sign extension.
 
 ### ldrsw ###
 
+Load word with sign extension from literal pool.
+
+    void ldrsw(const Register& rt, RawLiteral* literal)
+
+
+### ldrsw ###
+
+Load word with sign extension from pc + imm19 << 2.
+
+    void ldrsw(const Register& rt, int imm19)
+
+
+### ldrsw ###
+
 Load word with sign extension.
 
     void ldrsw(const Register& rt, const MemOperand& src,
@@ -1578,4 +1585,11 @@ Emit raw instructions into the instruction stream.
     inline void dci(Instr raw_inst)
 
 
+### place ###
+
+Place a literal at the current PC.
+
+    void place(RawLiteral* literal)
+
+
 
diff --git a/doc/topics/extending-the-disassembler.md b/doc/topics/extending-the-disassembler.md
new file mode 100644
index 00000000..d30770da
--- /dev/null
+++ b/doc/topics/extending-the-disassembler.md
@@ -0,0 +1,54 @@
+Extending the disassembler
+==========================
+
+The output of the disassembler can be extended and customized. This may be
+useful for example to add comments and annotations to the disassembly or print
+aliases for register names.
+
+The general procedure to achieve this is to create a sub-class of
+`Disassembler` and override the appropriate virtual functions.
+
+The `Disassembler` class provides virtual methods that implement how specific
+disassembly elements are printed. See
+[src/a64/disasm-a64.h](/src/a64/disasm-a64.h) for details.  At the time of
+writing, these are
+
+    virtual void AppendRegisterNameToOutput(const Instruction* instr,
+                                            CPURegister::RegisterType reg_type,
+                                            unsigned reg_code,
+                                            unsigned reg_size);
+    virtual void AppendPCRelativeOffsetToOutput(const Instruction* instr,
+                                                int64_t offset);
+    virtual void AppendAddressToOutput(const Instruction* instr,
+                                       const void* addr);
+    virtual void AppendCodeAddressToOutput(const Instruction* instr,
+                                           const void* addr);
+    virtual void AppendDataAddressToOutput(const Instruction* instr,
+                                           const void* addr);
+
+They can be overridden for example to use different register names and annotate
+code addresses.
+
+More complex modifications can be performed by overriding the visitor functions
+of the disassembler. The VIXL `Decoder` uses a visitor pattern implementation,
+so the `Disassembler` (as a sub-class of `DecoderVisitor`) must provide a
+visitor function for each sub-type of instructions. The complete list of
+visitors is defined by the macro `VISITOR_LIST` in
+[src/a64/decoder-a64.h](/src/a64/decoder-a64.h).
+
+The [/examples/custom-disassembler.h](/examples/custom-disassembler.h) and
+[/examples/custom-disassembler.cc](/examples/custom-disassembler.cc) example
+files show how the methods can be overridden to use different register names,
+annotate code addresses, and add comments:
+
+    VIXL disasm:   add x10, x16, x17
+    custom disasm: add x10, ip0, ip1 // add/sub to x10
+
+    VIXL disasm:   cbz x10, #+0x28 (addr 0x7fff8843bf6c)
+    custom disasm: cbz x10, #+0x28 (addr 0x7fff8843bf6c) (function: foo)
+
+
+One can refer to the implementation of visitor functions for the `Disassembler`
+(in [src/a64/disasm-a64.cc](/src/a64/disasm-a64.cc)) or even for the `Simulator`
+(in [src/a64/simulator-a64.cc](/src/a64/simulator-a64.cc)) to see how to extract
+information from instructions.
diff --git a/doc/topics/index.md b/doc/topics/index.md
new file mode 100644
index 00000000..d41074d5
--- /dev/null
+++ b/doc/topics/index.md
@@ -0,0 +1,8 @@
+We will try to add documentation for topics that may be useful to VIXL users. If
+you think of any topic that may be useful and is not listed here, please contact
+us at <vixl@arm.com>.
+
+You can also have a look at the ['getting started' page](doc/getting-started).
+
+* [Extending and customizing the disassembler](extending-the-disassembler.md)
+* [Using VIM YouCompleteMe with VIXL](ycm.md)
diff --git a/doc/topics/ycm.md b/doc/topics/ycm.md
new file mode 100644
index 00000000..36371cf3
--- /dev/null
+++ b/doc/topics/ycm.md
@@ -0,0 +1,9 @@
+VIM YouCompleteMe for VIXL
+==========================
+
+[YouCompleteMe](https://github.com/Valloric/YouCompleteMe) is a code completion
+engine for VIM. VIXL includes a `.ycm_extra_conf.py` to configure YCM to work in
+the VIXL repository.
+
+All you need to do to get things working is to [install YCM](https://github.com/Valloric/YouCompleteMe#full-installation-guide),
+preferably with semantic completion for C-family languages.