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| author | TatWai Chong <tatwai.chong@arm.com> | 2020-02-10 01:51:32 -0800 |
|---|---|---|
| committer | TatWai Chong <tatwai.chong@arm.com> | 2020-02-19 16:37:05 -0800 |
| commit | 47c2684c6792b186ffe5bbe797a05f75c1ed2637 (patch) | |
| tree | a53eaa2b4f1103358463e17c71bb3de692b56204 /src/aarch64/simulator-aarch64.cc | |
| parent | f07b8cee2dc89ac8d11e5e5a5727e8c5d2989cb0 (diff) | |
| download | vixl-47c2684c6792b186ffe5bbe797a05f75c1ed2637.tar.gz | |
[sve] Implement SVEFPCompareVectors instructions.
Include facge, facgt, fcmeq, fcmge, fcmgt, fcmne and fcmuo.
Change-Id: If105b60990249f1126d37e304093552cd2bea71d
Diffstat (limited to 'src/aarch64/simulator-aarch64.cc')
| -rw-r--r-- | src/aarch64/simulator-aarch64.cc | 37 |
1 files changed, 24 insertions, 13 deletions
diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc index ffe44cb2..8c21b224 100644 --- a/src/aarch64/simulator-aarch64.cc +++ b/src/aarch64/simulator-aarch64.cc @@ -388,11 +388,13 @@ SimVRegister Simulator::ExpandToSimVRegister(const SimPRegister& pg) { return result; } -void Simulator::ExtractFromSimVRegister(SimPRegister& pd, SimVRegister vreg) { +void Simulator::ExtractFromSimVRegister(VectorFormat vform, + SimPRegister& pd, + SimVRegister vreg) { SimVRegister zero; dup_immediate(kFormatVnB, zero, 0); SVEIntCompareVectorsHelper(ne, - kFormatVnB, + vform, pd, GetPTrue(), vreg, @@ -7941,33 +7943,42 @@ void Simulator::VisitSVEFPArithmeticUnpredicated(const Instruction* instr) { } void Simulator::VisitSVEFPCompareVectors(const Instruction* instr) { - USE(instr); + SimPRegister& pd = ReadPRegister(instr->GetPd()); + SimVRegister& zn = ReadVRegister(instr->GetRn()); + SimVRegister& zm = ReadVRegister(instr->GetRm()); + SimPRegister& pg = ReadPRegister(instr->GetPgLow8()); + VectorFormat vform = instr->GetSVEVectorFormat(); + SimVRegister result; + switch (instr->Mask(SVEFPCompareVectorsMask)) { case FACGE_p_p_zz: - VIXL_UNIMPLEMENTED(); + fabscmp(vform, result, zn, zm, ge); break; case FACGT_p_p_zz: - VIXL_UNIMPLEMENTED(); + fabscmp(vform, result, zn, zm, gt); break; case FCMEQ_p_p_zz: - VIXL_UNIMPLEMENTED(); + fcmp(vform, result, zn, zm, eq); break; case FCMGE_p_p_zz: - VIXL_UNIMPLEMENTED(); + fcmp(vform, result, zn, zm, ge); break; case FCMGT_p_p_zz: - VIXL_UNIMPLEMENTED(); + fcmp(vform, result, zn, zm, gt); break; case FCMNE_p_p_zz: - VIXL_UNIMPLEMENTED(); + fcmp(vform, result, zn, zm, ne); break; case FCMUO_p_p_zz: - VIXL_UNIMPLEMENTED(); + fcmp(vform, result, zn, zm, uo); break; default: VIXL_UNIMPLEMENTED(); break; } + + ExtractFromSimVRegister(vform, pd, result); + mov_zeroing(pd, pg, pd); } void Simulator::VisitSVEFPCompareWithZero(const Instruction* instr) { @@ -10697,7 +10708,7 @@ void Simulator::VisitSVEUnpackPredicateElements(const Instruction* instr) { VIXL_UNIMPLEMENTED(); break; } - Simulator::ExtractFromSimVRegister(pd, temp); + Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp); } void Simulator::VisitSVEPermutePredicateElements(const Instruction* instr) { @@ -10732,7 +10743,7 @@ void Simulator::VisitSVEPermutePredicateElements(const Instruction* instr) { VIXL_UNIMPLEMENTED(); break; } - Simulator::ExtractFromSimVRegister(pd, temp0); + Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp0); } void Simulator::VisitSVEReversePredicateElements(const Instruction* instr) { @@ -10743,7 +10754,7 @@ void Simulator::VisitSVEReversePredicateElements(const Instruction* instr) { SimPRegister& pd = ReadPRegister(instr->GetPd()); SimVRegister temp = Simulator::ExpandToSimVRegister(pn); rev(vform, temp, temp); - Simulator::ExtractFromSimVRegister(pd, temp); + Simulator::ExtractFromSimVRegister(kFormatVnB, pd, temp); break; } default: |