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| author | TatWai Chong <tatwai.chong@arm.com> | 2020-03-13 00:22:03 -0700 |
|---|---|---|
| committer | TatWai Chong <tatwai.chong@arm.com> | 2020-05-04 10:33:09 -0700 |
| commit | fa3f6bf63d30cefe7f7ec1ca830d2e22870632d2 (patch) | |
| tree | 562964b759dce2d070144664f82fad8c872db279 /src/aarch64/simulator-aarch64.cc | |
| parent | 3e2fb505fe97060fd2c3047f01199e37fca84be8 (diff) | |
| download | vixl-fa3f6bf63d30cefe7f7ec1ca830d2e22870632d2.tar.gz | |
[sve] Implement indexed sdot and udot.
Change-Id: Ie7bc03c5d2307b4d5ef74ef62ebf376bdcfb1df4
Diffstat (limited to 'src/aarch64/simulator-aarch64.cc')
| -rw-r--r-- | src/aarch64/simulator-aarch64.cc | 29 |
1 files changed, 24 insertions, 5 deletions
diff --git a/src/aarch64/simulator-aarch64.cc b/src/aarch64/simulator-aarch64.cc index 63d5a25f..50681403 100644 --- a/src/aarch64/simulator-aarch64.cc +++ b/src/aarch64/simulator-aarch64.cc @@ -10826,19 +10826,38 @@ void Simulator::VisitSVEStoreVectorRegister(const Instruction* instr) { } void Simulator::VisitSVEMulIndex(const Instruction* instr) { - USE(instr); + VectorFormat vform = instr->GetSVEVectorFormat(); + SimVRegister& zda = ReadVRegister(instr->GetRd()); + SimVRegister& zn = ReadVRegister(instr->GetRn()); + switch (instr->Mask(SVEMulIndexMask)) { case SDOT_z_zzzi_d: - VIXL_UNIMPLEMENTED(); + sdot(vform, + zda, + zn, + ReadVRegister(instr->ExtractBits(19, 16)), + instr->ExtractBit(20)); break; case SDOT_z_zzzi_s: - VIXL_UNIMPLEMENTED(); + sdot(vform, + zda, + zn, + ReadVRegister(instr->ExtractBits(18, 16)), + instr->ExtractBits(20, 19)); break; case UDOT_z_zzzi_d: - VIXL_UNIMPLEMENTED(); + udot(vform, + zda, + zn, + ReadVRegister(instr->ExtractBits(19, 16)), + instr->ExtractBit(20)); break; case UDOT_z_zzzi_s: - VIXL_UNIMPLEMENTED(); + udot(vform, + zda, + zn, + ReadVRegister(instr->ExtractBits(18, 16)), + instr->ExtractBits(20, 19)); break; default: VIXL_UNIMPLEMENTED(); |